1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
35 /* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39 #if defined (TE_SVR4) || defined (TE_DELTA)
40 const char *m68k_comment_chars = "|#";
42 const char *m68k_comment_chars = "|";
45 /* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48 /* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
50 #NO_APP at the beginning of its output. */
51 /* Also note that comments like this one will always work. */
52 const char line_comment_chars[] = "#*";
54 const char line_separator_chars[] = ";";
56 /* Chars that can be used to separate mant from exp in floating point nums */
57 CONST char EXP_CHARS[] = "eE";
59 /* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
62 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
64 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
68 const int md_reloc_size = 8; /* Size of relocation record */
70 /* Are we trying to generate PIC code? If so, absolute references
71 ought to be made into linkage table references or pc-relative
72 references. Not implemented. For ELF there are other means
73 to denote pic relocations. */
76 static int flag_short_refs; /* -l option */
77 static int flag_long_jumps; /* -S option */
78 static int flag_keep_pcrel; /* --pcrel option. */
80 #ifdef REGISTER_PREFIX_OPTIONAL
81 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
83 int flag_reg_prefix_optional;
86 /* Whether --register-prefix-optional was used on the command line. */
87 static int reg_prefix_optional_seen;
89 /* The floating point coprocessor to use by default. */
90 static enum m68k_register m68k_float_copnum = COP1;
92 /* If this is non-zero, then references to number(%pc) will be taken
93 to refer to number, rather than to %pc + number. */
94 static int m68k_abspcadd;
96 /* If this is non-zero, then the quick forms of the move, add, and sub
97 instructions are used when possible. */
98 static int m68k_quick = 1;
100 /* If this is non-zero, then if the size is not specified for a base
101 or outer displacement, the assembler assumes that the size should
103 static int m68k_rel32 = 1;
105 /* This is non-zero if m68k_rel32 was set from the command line. */
106 static int m68k_rel32_from_cmdline;
108 /* The default width to use for an index register when using a base
110 static enum m68k_size m68k_index_width_default = SIZE_LONG;
112 /* We want to warn if any text labels are misaligned. In order to get
113 the right line number, we need to record the line number for each
118 struct label_line *next;
125 /* The list of labels. */
127 static struct label_line *labels;
129 /* The current label. */
131 static struct label_line *current_label;
133 /* Its an arbitrary name: This means I don't approve of it */
134 /* See flames below */
135 static struct obstack robyn;
139 const char *m_operands;
140 unsigned long m_opcode;
144 struct m68k_incant *m_next;
147 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148 #define gettwo(x) (((x)->m_opcode)&0xffff)
150 static const enum m68k_register m68000_control_regs[] = { 0 };
151 static const enum m68k_register m68010_control_regs[] = {
155 static const enum m68k_register m68020_control_regs[] = {
156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
159 static const enum m68k_register m68040_control_regs[] = {
160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
164 static const enum m68k_register m68060_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
169 static const enum m68k_register mcf_control_regs[] = {
170 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
171 RAMBAR0, RAMBAR1, MBAR,
174 #define cpu32_control_regs m68010_control_regs
176 static const enum m68k_register *control_regs;
178 /* internal form of a 68020 instruction */
182 const char *args; /* list of opcode info */
185 int numo; /* Number of shorts in opcode */
188 struct m68k_op operands[6];
190 int nexp; /* number of exprs in use */
191 struct m68k_exp exprs[4];
193 int nfrag; /* Number of frags we have to produce */
196 int fragoff; /* Where in the current opcode the frag ends */
203 int nrel; /* Num of reloc strucs in use */
210 /* In a pc relative address the difference between the address
211 of the offset and the address that the offset is relative
212 to. This depends on the addressing mode. Basically this
213 is the value to put in the offset field to address the
214 first byte of the offset, without regarding the special
215 significance of some values (in the branch instruction, for
219 /* Whether this expression needs special pic relocation, and if
221 enum pic_relocation pic_reloc;
224 reloc[5]; /* Five is enough??? */
227 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
228 #define float_of_arch(x) ((x) & mfloat)
229 #define mmu_of_arch(x) ((x) & mmmu)
230 #define arch_coldfire_p(x) (((x) & mcf) != 0)
232 /* Macros for determining if cpu supports a specific addressing mode */
233 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
235 static struct m68k_it the_ins; /* the instruction being assembled */
237 #define op(ex) ((ex)->exp.X_op)
238 #define adds(ex) ((ex)->exp.X_add_symbol)
239 #define subs(ex) ((ex)->exp.X_op_symbol)
240 #define offs(ex) ((ex)->exp.X_add_number)
242 /* Macros for adding things to the m68k_it struct */
244 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
246 /* Static functions. */
248 static void insop PARAMS ((int, const struct m68k_incant *));
249 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
250 static void add_frag PARAMS ((symbolS *, offsetT, int));
252 /* Like addword, but goes BEFORE general operands */
256 const struct m68k_incant *opcode;
259 for(z=the_ins.numo;z>opcode->m_codenum;--z)
260 the_ins.opcode[z]=the_ins.opcode[z-1];
261 for(z=0;z<the_ins.nrel;z++)
262 the_ins.reloc[z].n+=2;
263 for (z = 0; z < the_ins.nfrag; z++)
264 the_ins.fragb[z].fragoff++;
265 the_ins.opcode[opcode->m_codenum]=w;
269 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
272 add_fix (width, exp, pc_rel, pc_fix)
274 struct m68k_exp *exp;
278 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
282 : (the_ins.numo*2)));
283 the_ins.reloc[the_ins.nrel].exp = exp->exp;
284 the_ins.reloc[the_ins.nrel].wid = width;
285 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
287 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
289 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
292 /* Cause an extra frag to be generated here, inserting up to 10 bytes
293 (that value is chosen in the frag_var call in md_assemble). TYPE
294 is the subtype of the frag to be generated; its primary type is
295 rs_machine_dependent.
297 The TYPE parameter is also used by md_convert_frag_1 and
298 md_estimate_size_before_relax. The appropriate type of fixup will
299 be emitted by md_convert_frag_1.
301 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
303 add_frag (add, off, type)
308 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
309 the_ins.fragb[the_ins.nfrag].fadd=add;
310 the_ins.fragb[the_ins.nfrag].foff=off;
311 the_ins.fragb[the_ins.nfrag++].fragty=type;
315 (op (ex) != O_constant && op (ex) != O_big)
317 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
318 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
319 static void m68k_ip PARAMS ((char *));
320 static void insert_reg PARAMS ((const char *, int));
321 static void select_control_regs PARAMS ((void));
322 static void init_regtable PARAMS ((void));
323 static int reverse_16_bits PARAMS ((int in));
324 static int reverse_8_bits PARAMS ((int in));
325 static void install_gen_operand PARAMS ((int mode, int val));
326 static void install_operand PARAMS ((int mode, int val));
327 static void s_bss PARAMS ((int));
328 static void s_data1 PARAMS ((int));
329 static void s_data2 PARAMS ((int));
330 static void s_even PARAMS ((int));
331 static void s_proc PARAMS ((int));
332 static void mri_chip PARAMS ((void));
333 static void s_chip PARAMS ((int));
334 static void s_fopt PARAMS ((int));
335 static void s_opt PARAMS ((int));
336 static void s_reg PARAMS ((int));
337 static void s_restore PARAMS ((int));
338 static void s_save PARAMS ((int));
339 static void s_mri_if PARAMS ((int));
340 static void s_mri_else PARAMS ((int));
341 static void s_mri_endi PARAMS ((int));
342 static void s_mri_break PARAMS ((int));
343 static void s_mri_next PARAMS ((int));
344 static void s_mri_for PARAMS ((int));
345 static void s_mri_endf PARAMS ((int));
346 static void s_mri_repeat PARAMS ((int));
347 static void s_mri_until PARAMS ((int));
348 static void s_mri_while PARAMS ((int));
349 static void s_mri_endw PARAMS ((int));
350 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
351 static void md_convert_frag_1 PARAMS ((fragS *));
353 static int current_architecture;
362 static const struct m68k_cpu archs[] =
364 { m68000, "68000", 0 },
365 { m68010, "68010", 0 },
366 { m68020, "68020", 0 },
367 { m68030, "68030", 0 },
368 { m68040, "68040", 0 },
369 { m68060, "68060", 0 },
370 { cpu32, "cpu32", 0 },
371 { m68881, "68881", 0 },
372 { m68851, "68851", 0 },
373 { mcf5200, "5200", 0 },
374 { mcf5206e, "5206e", 0 },
375 { mcf5307, "5307", 0},
376 { mcf5407, "5407", 0},
377 /* Aliases (effectively, so far as gas is concerned) for the above
379 { m68020, "68k", 1 },
380 { m68000, "68008", 1 },
381 { m68000, "68302", 1 },
382 { m68000, "68306", 1 },
383 { m68000, "68307", 1 },
384 { m68000, "68322", 1 },
385 { m68000, "68356", 1 },
386 { m68000, "68ec000", 1 },
387 { m68000, "68hc000", 1 },
388 { m68000, "68hc001", 1 },
389 { m68020, "68ec020", 1 },
390 { m68030, "68ec030", 1 },
391 { m68040, "68ec040", 1 },
392 { m68060, "68ec060", 1 },
393 { cpu32, "68330", 1 },
394 { cpu32, "68331", 1 },
395 { cpu32, "68332", 1 },
396 { cpu32, "68333", 1 },
397 { cpu32, "68334", 1 },
398 { cpu32, "68336", 1 },
399 { cpu32, "68340", 1 },
400 { cpu32, "68341", 1 },
401 { cpu32, "68349", 1 },
402 { cpu32, "68360", 1 },
403 { m68881, "68882", 1 },
404 { mcf5200, "5202", 1 },
405 { mcf5200, "5204", 1 },
406 { mcf5200, "5206", 1 },
409 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
411 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
412 architecture and we have a lot of relaxation modes. */
414 /* Macros used in the relaxation code. */
415 #define TAB(x,y) (((x) << 2) + (y))
416 #define TABTYPE(x) ((x) >> 2)
418 /* Relaxation states. */
424 /* Here are all the relaxation modes we support. First we can relax ordinary
425 branches. On 68020 and higher and on CPU32 all branch instructions take
426 three forms, so on these CPUs all branches always remain as such. When we
427 have to expand to the LONG form on a 68000, though, we substitute an
428 absolute jump instead. This is a direct replacement for unconditional
429 branches and a branch over a jump for conditional branches. However, if the
430 user requires PIC and disables this with --pcrel, we can only relax between
431 BYTE and SHORT forms, punting if that isn't enough. This gives us four
432 different relaxation modes for branches: */
434 #define BRANCHBWL 1 /* branch byte, word, or long */
435 #define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
436 #define BRABSJCOND 3 /* absolute jump for LONG, conditional */
437 #define BRANCHBW 4 /* branch byte or word */
439 /* We also relax coprocessor branches and DBcc's. All CPUs that support
440 coprocessor branches support them in word and long forms, so we have only
441 one relaxation mode for them. DBcc's are word only on all CPUs. We can
442 relax them to the LONG form with a branch-around sequence. This sequence
443 can use a long branch (if available) or an absolute jump (if acceptable).
444 This gives us two relaxation modes. If long branches are not available and
445 absolute jumps are not acceptable, we don't relax DBcc's. */
447 #define FBRANCH 5 /* coprocessor branch */
448 #define DBCCLBR 6 /* DBcc relaxable with a long branch */
449 #define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
451 /* That's all for instruction relaxation. However, we also relax PC-relative
452 operands. Specifically, we have three operand relaxation modes. On the
453 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
454 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
455 two. Also PC+displacement+index operands in their simple form (with a non-
456 suppressed index without memory indirection) are supported on all CPUs, but
457 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
458 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
459 form of the PC+displacement+index operand. Finally, some absolute operands
460 can be relaxed down to 16-bit PC-relative. */
462 #define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
463 #define PCINDEX 9 /* PC+displacement+index */
464 #define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
466 /* Note that calls to frag_var need to specify the maximum expansion
467 needed; this is currently 10 bytes for DBCC. */
470 How far Forward this mode will reach:
471 How far Backward this mode will reach:
472 How many bytes this mode will add to the size of the frag
473 Which mode to go to if the offset won't fit in this one
475 relax_typeS md_relax_table[] =
477 {1, 1, 0, 0}, /* First entries aren't used */
478 {1, 1, 0, 0}, /* For no good reason except */
479 {1, 1, 0, 0}, /* that the VAX doesn't either */
482 {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
483 {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
487 {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
488 {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
492 {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
493 {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
497 {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
502 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
503 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
507 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
508 {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
512 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
513 {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
517 {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
518 {32767, -32768, 2, TAB (PCREL1632, LONG)},
522 {125, -130, 0, TAB (PCINDEX, SHORT)},
523 {32765, -32770, 2, TAB (PCINDEX, LONG)},
527 {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
528 {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
533 /* These are the machine dependent pseudo-ops. These are included so
534 the assembler can work on the output from the SUN C compiler, which
538 /* This table describes all the machine specific pseudo-ops the assembler
539 has to support. The fields are:
540 pseudo-op name without dot
541 function to call to execute this pseudo-op
542 Integer arg to pass to the function
544 const pseudo_typeS md_pseudo_table[] =
546 {"data1", s_data1, 0},
547 {"data2", s_data2, 0},
550 {"skip", s_space, 0},
552 #if defined (TE_SUN3) || defined (OBJ_ELF)
553 {"align", s_align_bytes, 0},
556 {"swbeg", s_ignore, 0},
558 {"extend", float_cons, 'x'},
559 {"ldouble", float_cons, 'x'},
561 /* The following pseudo-ops are supported for MRI compatibility. */
563 {"comline", s_space, 1},
565 {"mask2", s_ignore, 0},
568 {"restore", s_restore, 0},
572 {"if.b", s_mri_if, 'b'},
573 {"if.w", s_mri_if, 'w'},
574 {"if.l", s_mri_if, 'l'},
575 {"else", s_mri_else, 0},
576 {"else.s", s_mri_else, 's'},
577 {"else.l", s_mri_else, 'l'},
578 {"endi", s_mri_endi, 0},
579 {"break", s_mri_break, 0},
580 {"break.s", s_mri_break, 's'},
581 {"break.l", s_mri_break, 'l'},
582 {"next", s_mri_next, 0},
583 {"next.s", s_mri_next, 's'},
584 {"next.l", s_mri_next, 'l'},
585 {"for", s_mri_for, 0},
586 {"for.b", s_mri_for, 'b'},
587 {"for.w", s_mri_for, 'w'},
588 {"for.l", s_mri_for, 'l'},
589 {"endf", s_mri_endf, 0},
590 {"repeat", s_mri_repeat, 0},
591 {"until", s_mri_until, 0},
592 {"until.b", s_mri_until, 'b'},
593 {"until.w", s_mri_until, 'w'},
594 {"until.l", s_mri_until, 'l'},
595 {"while", s_mri_while, 0},
596 {"while.b", s_mri_while, 'b'},
597 {"while.w", s_mri_while, 'w'},
598 {"while.l", s_mri_while, 'l'},
599 {"endw", s_mri_endw, 0},
604 /* The mote pseudo ops are put into the opcode table, since they
605 don't start with a . they look like opcodes to gas.
609 extern void obj_coff_section PARAMS ((int));
612 CONST pseudo_typeS mote_pseudo_table[] =
625 {"xdef", s_globl, 0},
627 {"align", s_align_bytes, 0},
629 {"align", s_align_ptwo, 0},
632 {"sect", obj_coff_section, 0},
633 {"section", obj_coff_section, 0},
638 #define issbyte(x) ((x)>=-128 && (x)<=127)
639 #define isubyte(x) ((x)>=0 && (x)<=255)
640 #define issword(x) ((x)>=-32768 && (x)<=32767)
641 #define isuword(x) ((x)>=0 && (x)<=65535)
643 #define isbyte(x) ((x)>= -255 && (x)<=255)
644 #define isword(x) ((x)>=-65536 && (x)<=65535)
645 #define islong(x) (1)
647 extern char *input_line_pointer;
649 static char mklower_table[256];
650 #define mklower(c) (mklower_table[(unsigned char) (c)])
651 static char notend_table[256];
652 static char alt_notend_table[256];
654 (! (notend_table[(unsigned char) *s] \
656 && alt_notend_table[(unsigned char) s[1]])))
658 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
660 #ifdef NO_PCREL_RELOCS
663 make_pcrel_absolute(fixP, add_number)
667 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
669 /* rewrite the PC relative instructions to absolute address ones.
670 * these are rumoured to be faster, and the apollo linker refuses
671 * to deal with the PC relative relocations.
673 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
678 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
684 as_fatal (_("Unknown PC relative instruction"));
689 #endif /* NO_PCREL_RELOCS */
692 tc_coff_fix2rtype (fixP)
695 if (fixP->fx_tcbit && fixP->fx_size == 4)
696 return R_RELLONG_NEG;
697 #ifdef NO_PCREL_RELOCS
698 know (fixP->fx_pcrel == 0);
699 return (fixP->fx_size == 1 ? R_RELBYTE
700 : fixP->fx_size == 2 ? R_DIR16
703 return (fixP->fx_pcrel ?
704 (fixP->fx_size == 1 ? R_PCRBYTE :
705 fixP->fx_size == 2 ? R_PCRWORD :
707 (fixP->fx_size == 1 ? R_RELBYTE :
708 fixP->fx_size == 2 ? R_RELWORD :
717 /* Compute the relocation code for a fixup of SIZE bytes, using pc
718 relative relocation if PCREL is non-zero. PIC says whether a special
719 pic relocation was requested. */
721 static bfd_reloc_code_real_type get_reloc_code
722 PARAMS ((int, int, enum pic_relocation));
724 static bfd_reloc_code_real_type
725 get_reloc_code (size, pcrel, pic)
728 enum pic_relocation pic;
736 return BFD_RELOC_8_GOT_PCREL;
738 return BFD_RELOC_16_GOT_PCREL;
740 return BFD_RELOC_32_GOT_PCREL;
748 return BFD_RELOC_8_GOTOFF;
750 return BFD_RELOC_16_GOTOFF;
752 return BFD_RELOC_32_GOTOFF;
760 return BFD_RELOC_8_PLT_PCREL;
762 return BFD_RELOC_16_PLT_PCREL;
764 return BFD_RELOC_32_PLT_PCREL;
772 return BFD_RELOC_8_PLTOFF;
774 return BFD_RELOC_16_PLTOFF;
776 return BFD_RELOC_32_PLTOFF;
786 return BFD_RELOC_8_PCREL;
788 return BFD_RELOC_16_PCREL;
790 return BFD_RELOC_32_PCREL;
810 as_bad (_("Can not do %d byte pc-relative relocation"), size);
812 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
817 as_bad (_("Can not do %d byte relocation"), size);
819 as_bad (_("Can not do %d byte pic relocation"), size);
822 return BFD_RELOC_NONE;
825 /* Here we decide which fixups can be adjusted to make them relative
826 to the beginning of the section instead of the symbol. Basically
827 we need to make sure that the dynamic relocations are done
828 correctly, so in some cases we force the original symbol to be
831 tc_m68k_fix_adjustable (fixP)
834 /* Prevent all adjustments to global symbols. */
835 if (S_IS_EXTERNAL (fixP->fx_addsy)
836 || S_IS_WEAK (fixP->fx_addsy))
839 /* adjust_reloc_syms doesn't know about the GOT */
840 switch (fixP->fx_r_type)
842 case BFD_RELOC_8_GOT_PCREL:
843 case BFD_RELOC_16_GOT_PCREL:
844 case BFD_RELOC_32_GOT_PCREL:
845 case BFD_RELOC_8_GOTOFF:
846 case BFD_RELOC_16_GOTOFF:
847 case BFD_RELOC_32_GOTOFF:
848 case BFD_RELOC_8_PLT_PCREL:
849 case BFD_RELOC_16_PLT_PCREL:
850 case BFD_RELOC_32_PLT_PCREL:
851 case BFD_RELOC_8_PLTOFF:
852 case BFD_RELOC_16_PLTOFF:
853 case BFD_RELOC_32_PLTOFF:
856 case BFD_RELOC_VTABLE_INHERIT:
857 case BFD_RELOC_VTABLE_ENTRY:
867 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
874 tc_gen_reloc (section, fixp)
879 bfd_reloc_code_real_type code;
881 /* If the tcbit is set, then this was a fixup of a negative value
882 that was never resolved. We do not have a reloc to handle this,
883 so just return. We assume that other code will have detected this
884 situation and produced a helpful error message, so we just tell the
885 user that the reloc cannot be produced. */
889 as_bad (_("Unable to produce reloc against symbol '%s'"),
890 S_GET_NAME (fixp->fx_addsy));
894 if (fixp->fx_r_type != BFD_RELOC_NONE)
896 code = fixp->fx_r_type;
898 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
899 that fixup_segment converted a non-PC relative reloc into a
900 PC relative reloc. In such a case, we need to convert the
907 code = BFD_RELOC_8_PCREL;
910 code = BFD_RELOC_16_PCREL;
913 code = BFD_RELOC_32_PCREL;
915 case BFD_RELOC_8_PCREL:
916 case BFD_RELOC_16_PCREL:
917 case BFD_RELOC_32_PCREL:
918 case BFD_RELOC_8_GOT_PCREL:
919 case BFD_RELOC_16_GOT_PCREL:
920 case BFD_RELOC_32_GOT_PCREL:
921 case BFD_RELOC_8_GOTOFF:
922 case BFD_RELOC_16_GOTOFF:
923 case BFD_RELOC_32_GOTOFF:
924 case BFD_RELOC_8_PLT_PCREL:
925 case BFD_RELOC_16_PLT_PCREL:
926 case BFD_RELOC_32_PLT_PCREL:
927 case BFD_RELOC_8_PLTOFF:
928 case BFD_RELOC_16_PLTOFF:
929 case BFD_RELOC_32_PLTOFF:
932 as_bad_where (fixp->fx_file, fixp->fx_line,
933 _("Cannot make %s relocation PC relative"),
934 bfd_get_reloc_code_name (code));
940 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
941 switch (F (fixp->fx_size, fixp->fx_pcrel))
943 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
944 MAP (1, 0, BFD_RELOC_8);
945 MAP (2, 0, BFD_RELOC_16);
946 MAP (4, 0, BFD_RELOC_32);
947 MAP (1, 1, BFD_RELOC_8_PCREL);
948 MAP (2, 1, BFD_RELOC_16_PCREL);
949 MAP (4, 1, BFD_RELOC_32_PCREL);
957 reloc = (arelent *) xmalloc (sizeof (arelent));
958 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
959 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
960 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
963 reloc->addend = fixp->fx_addnumber;
968 reloc->addend = fixp->fx_addnumber;
970 reloc->addend = (section->vma
971 /* Explicit sign extension in case char is
973 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
975 + md_pcrel_from (fixp));
978 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
979 assert (reloc->howto != 0);
984 #endif /* BFD_ASSEMBLER */
986 /* Return zero if the reference to SYMBOL from within the same segment may
990 /* On an ELF system, we can't relax an externally visible symbol,
991 because it may be overridden by a shared library. However, if
992 TARGET_OS is "elf", then we presume that we are assembling for an
993 embedded system, in which case we don't have to worry about shared
994 libraries, and we can relax anything. */
996 #define relaxable_symbol(symbol) \
997 (strcmp (TARGET_OS, "elf") == 0 \
998 || (! S_IS_EXTERNAL (symbol) \
999 && ! S_IS_WEAK (symbol)))
1003 #define relaxable_symbol(symbol) 1
1007 /* Handle of the OPCODE hash table. NULL means any use before
1008 m68k_ip_begin() will crash. */
1009 static struct hash_control *op_hash;
1011 /* Assemble an m68k instruction. */
1018 register struct m68k_op *opP;
1019 register const struct m68k_incant *opcode;
1020 register const char *s;
1021 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1022 char *pdot, *pdotmove;
1023 enum m68k_size siz1, siz2;
1027 LITTLENUM_TYPE words[6];
1028 LITTLENUM_TYPE *wordp;
1029 unsigned long ok_arch = 0;
1031 if (*instring == ' ')
1032 instring++; /* skip leading whitespace */
1034 /* Scan up to end of operation-code, which MUST end in end-of-string
1035 or exactly 1 space. */
1037 for (p = instring; *p != '\0'; p++)
1047 the_ins.error = _("No operator");
1051 /* p now points to the end of the opcode name, probably whitespace.
1052 Make sure the name is null terminated by clobbering the
1053 whitespace, look it up in the hash table, then fix it back.
1054 Remove a dot, first, since the opcode tables have none. */
1057 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1058 *pdotmove = pdotmove[1];
1064 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1069 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1070 *pdotmove = pdotmove[-1];
1077 the_ins.error = _("Unknown operator");
1081 /* found a legitimate opcode, start matching operands */
1085 if (opcode->m_operands == 0)
1087 char *old = input_line_pointer;
1089 input_line_pointer = p;
1090 /* Ahh - it's a motorola style psuedo op */
1091 mote_pseudo_table[opcode->m_opnum].poc_handler
1092 (mote_pseudo_table[opcode->m_opnum].poc_val);
1093 input_line_pointer = old;
1099 if (flag_mri && opcode->m_opnum == 0)
1101 /* In MRI mode, random garbage is allowed after an instruction
1102 which accepts no operands. */
1103 the_ins.args = opcode->m_operands;
1104 the_ins.numargs = opcode->m_opnum;
1105 the_ins.numo = opcode->m_codenum;
1106 the_ins.opcode[0] = getone (opcode);
1107 the_ins.opcode[1] = gettwo (opcode);
1111 for (opP = &the_ins.operands[0]; *p; opP++)
1113 p = crack_operand (p, opP);
1117 the_ins.error = opP->error;
1122 opsfound = opP - &the_ins.operands[0];
1124 /* This ugly hack is to support the floating pt opcodes in their
1125 standard form. Essentially, we fake a first enty of type COP#1 */
1126 if (opcode->m_operands[0] == 'I')
1130 for (n = opsfound; n > 0; --n)
1131 the_ins.operands[n] = the_ins.operands[n - 1];
1133 memset ((char *) (&the_ins.operands[0]), '\0',
1134 sizeof (the_ins.operands[0]));
1135 the_ins.operands[0].mode = CONTROL;
1136 the_ins.operands[0].reg = m68k_float_copnum;
1140 /* We've got the operands. Find an opcode that'll accept them */
1143 /* If we didn't get the right number of ops, or we have no
1144 common model with this pattern then reject this pattern. */
1146 ok_arch |= opcode->m_arch;
1147 if (opsfound != opcode->m_opnum
1148 || ((opcode->m_arch & current_architecture) == 0))
1152 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1156 /* Warning: this switch is huge! */
1157 /* I've tried to organize the cases into this order:
1158 non-alpha first, then alpha by letter. Lower-case
1159 goes directly before uppercase counterpart. */
1160 /* Code with multiple case ...: gets sorted by the lowest
1161 case ... it belongs to. I hope this makes sense. */
1267 if (opP->reg == PC || opP->reg == ZPC)
1284 if (opP->reg == PC || opP->reg == ZPC)
1303 if (opP->reg == PC || opP->reg == ZPC)
1313 if (opP->mode != IMMED)
1315 else if (s[1] == 'b'
1316 && ! isvar (&opP->disp)
1317 && (opP->disp.exp.X_op != O_constant
1318 || ! isbyte (opP->disp.exp.X_add_number)))
1320 else if (s[1] == 'B'
1321 && ! isvar (&opP->disp)
1322 && (opP->disp.exp.X_op != O_constant
1323 || ! issbyte (opP->disp.exp.X_add_number)))
1325 else if (s[1] == 'w'
1326 && ! isvar (&opP->disp)
1327 && (opP->disp.exp.X_op != O_constant
1328 || ! isword (opP->disp.exp.X_add_number)))
1330 else if (s[1] == 'W'
1331 && ! isvar (&opP->disp)
1332 && (opP->disp.exp.X_op != O_constant
1333 || ! issword (opP->disp.exp.X_add_number)))
1339 if (opP->mode != IMMED)
1344 if (opP->mode == AREG
1345 || opP->mode == CONTROL
1346 || opP->mode == FPREG
1347 || opP->mode == IMMED
1348 || opP->mode == REGLST
1349 || (opP->mode != ABSL
1351 || opP->reg == ZPC)))
1356 if (opP->mode == CONTROL
1357 || opP->mode == FPREG
1358 || opP->mode == REGLST
1359 || opP->mode == IMMED
1360 || (opP->mode != ABSL
1362 || opP->reg == ZPC)))
1390 if (opP->mode == CONTROL
1391 || opP->mode == FPREG
1392 || opP->mode == REGLST)
1397 if (opP->mode != AINC)
1402 if (opP->mode != ADEC)
1452 if (opP->reg == PC || opP->reg == ZPC)
1473 case '~': /* For now! (JF FOO is this right?) */
1495 if (opP->mode != CONTROL
1496 || (opP->reg != TT0 && opP->reg != TT1))
1501 if (opP->mode != AREG)
1506 if (opP->mode != AINDR)
1511 if (opP->mode != ABSL
1513 && strncmp (instring, "jbsr", 4) == 0))
1518 if (opP->mode != CONTROL || opP->reg != CCR)
1523 if (opP->mode != DISP
1525 || opP->reg > ADDR7)
1530 if (opP->mode != DREG)
1535 if (opP->reg != ACC)
1540 if (opP->mode != FPREG)
1545 if (opP->reg != MACSR)
1550 if (opP->reg != MASK)
1555 if (opP->mode != CONTROL
1562 if (opP->mode != CONTROL
1564 || opP->reg > last_movec_reg)
1568 const enum m68k_register *rp;
1569 for (rp = control_regs; *rp; rp++)
1570 if (*rp == opP->reg)
1578 if (opP->mode != IMMED)
1584 if (opP->mode == DREG
1585 || opP->mode == AREG
1586 || opP->mode == FPREG)
1595 opP->mask = 1 << (opP->reg - DATA0);
1598 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1601 opP->mask = 1 << (opP->reg - FP0 + 16);
1609 else if (opP->mode == CONTROL)
1618 opP->mask = 1 << 24;
1621 opP->mask = 1 << 25;
1624 opP->mask = 1 << 26;
1633 else if (opP->mode != REGLST)
1635 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1637 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1642 if (opP->mode != IMMED)
1644 else if (opP->disp.exp.X_op != O_constant
1645 || ! issbyte (opP->disp.exp.X_add_number))
1647 else if (! m68k_quick
1648 && instring[3] != 'q'
1649 && instring[4] != 'q')
1654 if (opP->mode != DREG
1655 && opP->mode != IMMED
1656 && opP->mode != ABSL)
1661 if (opP->mode != IMMED)
1663 else if (opP->disp.exp.X_op != O_constant
1664 || opP->disp.exp.X_add_number < 1
1665 || opP->disp.exp.X_add_number > 8)
1667 else if (! m68k_quick
1668 && (strncmp (instring, "add", 3) == 0
1669 || strncmp (instring, "sub", 3) == 0)
1670 && instring[3] != 'q')
1675 if (opP->mode != DREG && opP->mode != AREG)
1680 if (opP->mode != AINDR
1681 && (opP->mode != BASE
1683 && opP->reg != ZADDR0)
1684 || opP->disp.exp.X_op != O_absent
1685 || ((opP->index.reg < DATA0
1686 || opP->index.reg > DATA7)
1687 && (opP->index.reg < ADDR0
1688 || opP->index.reg > ADDR7))
1689 || opP->index.size != SIZE_UNSPEC
1690 || opP->index.scale != 1))
1695 if (opP->mode != CONTROL
1696 || ! (opP->reg == FPI
1698 || opP->reg == FPC))
1703 if (opP->mode != CONTROL || opP->reg != SR)
1708 if (opP->mode != IMMED)
1710 else if (opP->disp.exp.X_op != O_constant
1711 || opP->disp.exp.X_add_number < 0
1712 || opP->disp.exp.X_add_number > 7)
1717 if (opP->mode != CONTROL || opP->reg != USP)
1721 /* JF these are out of order. We could put them
1722 in order if we were willing to put up with
1723 bunches of #ifdef m68851s in the code.
1725 Don't forget that you need these operands
1726 to use 68030 MMU instructions. */
1728 /* Memory addressing mode used by pflushr */
1730 if (opP->mode == CONTROL
1731 || opP->mode == FPREG
1732 || opP->mode == DREG
1733 || opP->mode == AREG
1734 || opP->mode == REGLST)
1736 /* We should accept immediate operands, but they
1737 supposedly have to be quad word, and we don't
1738 handle that. I would like to see what a Motorola
1739 assembler does before doing something here. */
1740 if (opP->mode == IMMED)
1745 if (opP->mode != CONTROL
1746 || (opP->reg != SFC && opP->reg != DFC))
1751 if (opP->mode != CONTROL || opP->reg != TC)
1756 if (opP->mode != CONTROL || opP->reg != AC)
1761 if (opP->mode != CONTROL
1764 && opP->reg != SCC))
1769 if (opP->mode != CONTROL
1775 if (opP->mode != CONTROL
1778 && opP->reg != CRP))
1783 if (opP->mode != CONTROL
1784 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1785 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1790 if (opP->mode != CONTROL || opP->reg != PSR)
1795 if (opP->mode != CONTROL || opP->reg != PCSR)
1800 if (opP->mode != CONTROL
1807 } /* not a cache specifier. */
1811 if (opP->mode != ABSL)
1816 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1818 /* FIXME: kludge instead of fixing parser:
1819 upper/lower registers are *not* CONTROL
1820 registers, but ordinary ones. */
1821 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1822 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1830 } /* switch on type of operand */
1834 } /* for each operand */
1835 } /* if immediately wrong */
1842 opcode = opcode->m_next;
1847 && !(ok_arch & current_architecture))
1852 _("invalid instruction for this architecture; needs "));
1853 cp = buf + strlen (buf);
1857 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1860 strcpy (cp, _("mmu (68030 or 68851)"));
1863 strcpy (cp, _("68020 or higher"));
1866 strcpy (cp, _("68000 or higher"));
1869 strcpy (cp, _("68010 or higher"));
1873 int got_one = 0, idx;
1875 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1878 if ((archs[idx].arch & ok_arch)
1879 && ! archs[idx].alias)
1883 strcpy (cp, " or ");
1887 strcpy (cp, archs[idx].name);
1893 cp = xmalloc (strlen (buf) + 1);
1898 the_ins.error = _("operands mismatch");
1900 } /* Fell off the end */
1905 /* now assemble it */
1907 the_ins.args = opcode->m_operands;
1908 the_ins.numargs = opcode->m_opnum;
1909 the_ins.numo = opcode->m_codenum;
1910 the_ins.opcode[0] = getone (opcode);
1911 the_ins.opcode[1] = gettwo (opcode);
1913 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1915 /* This switch is a doozy.
1916 Watch the first step; its a big one! */
1944 tmpreg = 0x3c; /* 7.4 */
1945 if (strchr ("bwl", s[1]))
1946 nextword = get_num (&opP->disp, 80);
1948 nextword = get_num (&opP->disp, 0);
1949 if (isvar (&opP->disp))
1950 add_fix (s[1], &opP->disp, 0, 0);
1954 if (!isbyte (nextword))
1955 opP->error = _("operand out of range");
1960 if (!isword (nextword))
1961 opP->error = _("operand out of range");
1966 if (!issword (nextword))
1967 opP->error = _("operand out of range");
1972 addword (nextword >> 16);
1999 /* We gotta put out some float */
2000 if (op (&opP->disp) != O_big)
2005 /* Can other cases happen here? */
2006 if (op (&opP->disp) != O_constant)
2009 val = (valueT) offs (&opP->disp);
2013 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2014 val >>= LITTLENUM_NUMBER_OF_BITS;
2018 offs (&opP->disp) = gencnt;
2020 if (offs (&opP->disp) > 0)
2022 if (offs (&opP->disp) > baseo)
2024 as_warn (_("Bignum too big for %c format; truncated"),
2026 offs (&opP->disp) = baseo;
2028 baseo -= offs (&opP->disp);
2031 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2032 offs (&opP->disp)--;
2037 gen_to_words (words, baseo, (long) outro);
2038 for (wordp = words; baseo--; wordp++)
2042 tmpreg = opP->reg - DATA; /* 0.dreg */
2045 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2048 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2051 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2054 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2058 nextword = get_num (&opP->disp, 80);
2061 && ! isvar (&opP->disp)
2064 opP->disp.exp.X_op = O_symbol;
2065 #ifndef BFD_ASSEMBLER
2066 opP->disp.exp.X_add_symbol = &abs_symbol;
2068 opP->disp.exp.X_add_symbol =
2069 section_symbol (absolute_section);
2073 /* Force into index mode. Hope this works */
2075 /* We do the first bit for 32-bit displacements, and the
2076 second bit for 16 bit ones. It is possible that we
2077 should make the default be WORD instead of LONG, but
2078 I think that'd break GCC, so we put up with a little
2079 inefficiency for the sake of working output. */
2081 if (!issword (nextword)
2082 || (isvar (&opP->disp)
2083 && ((opP->disp.size == SIZE_UNSPEC
2084 && flag_short_refs == 0
2085 && cpu_of_arch (current_architecture) >= m68020
2086 && ! arch_coldfire_p (current_architecture))
2087 || opP->disp.size == SIZE_LONG)))
2089 if (cpu_of_arch (current_architecture) < m68020
2090 || arch_coldfire_p (current_architecture))
2092 _("displacement too large for this architecture; needs 68020 or higher");
2094 tmpreg = 0x3B; /* 7.3 */
2096 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2097 if (isvar (&opP->disp))
2101 if (opP->disp.size == SIZE_LONG
2103 /* If the displacement needs pic
2104 relocation it cannot be relaxed. */
2105 || opP->disp.pic_reloc != pic_none
2110 add_fix ('l', &opP->disp, 1, 2);
2114 add_frag (adds (&opP->disp),
2116 TAB (PCREL1632, SZ_UNDEF));
2123 add_fix ('l', &opP->disp, 0, 0);
2128 addword (nextword >> 16);
2133 tmpreg = 0x3A; /* 7.2 */
2135 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2137 if (isvar (&opP->disp))
2141 add_fix ('w', &opP->disp, 1, 0);
2144 add_fix ('w', &opP->disp, 0, 0);
2154 baseo = get_num (&opP->disp, 80);
2155 if (opP->mode == POST || opP->mode == PRE)
2156 outro = get_num (&opP->odisp, 80);
2157 /* Figure out the `addressing mode'.
2158 Also turn on the BASE_DISABLE bit, if needed. */
2159 if (opP->reg == PC || opP->reg == ZPC)
2161 tmpreg = 0x3b; /* 7.3 */
2162 if (opP->reg == ZPC)
2165 else if (opP->reg == 0)
2168 tmpreg = 0x30; /* 6.garbage */
2170 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2173 tmpreg = 0x30 + opP->reg - ZADDR0;
2176 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2178 siz1 = opP->disp.size;
2179 if (opP->mode == POST || opP->mode == PRE)
2180 siz2 = opP->odisp.size;
2184 /* Index register stuff */
2185 if (opP->index.reg != 0
2186 && opP->index.reg >= DATA
2187 && opP->index.reg <= ADDR7)
2189 nextword |= (opP->index.reg - DATA) << 12;
2191 if (opP->index.size == SIZE_LONG
2192 || (opP->index.size == SIZE_UNSPEC
2193 && m68k_index_width_default == SIZE_LONG))
2196 if ((opP->index.scale != 1
2197 && cpu_of_arch (current_architecture) < m68020)
2198 || (opP->index.scale == 8
2199 && arch_coldfire_p (current_architecture)))
2202 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2205 if (arch_coldfire_p (current_architecture)
2206 && opP->index.size == SIZE_WORD)
2207 opP->error = _("invalid index size for coldfire");
2209 switch (opP->index.scale)
2226 GET US OUT OF HERE! */
2228 /* Must be INDEX, with an index register. Address
2229 register cannot be ZERO-PC, and either :b was
2230 forced, or we know it will fit. For a 68000 or
2231 68010, force this mode anyways, because the
2232 larger modes aren't supported. */
2233 if (opP->mode == BASE
2234 && ((opP->reg >= ADDR0
2235 && opP->reg <= ADDR7)
2238 if (siz1 == SIZE_BYTE
2239 || cpu_of_arch (current_architecture) < m68020
2240 || arch_coldfire_p (current_architecture)
2241 || (siz1 == SIZE_UNSPEC
2242 && ! isvar (&opP->disp)
2243 && issbyte (baseo)))
2245 nextword += baseo & 0xff;
2247 if (isvar (&opP->disp))
2249 /* Do a byte relocation. If it doesn't
2250 fit (possible on m68000) let the
2251 fixup processing complain later. */
2253 add_fix ('B', &opP->disp, 1, 1);
2255 add_fix ('B', &opP->disp, 0, 0);
2257 else if (siz1 != SIZE_BYTE)
2259 if (siz1 != SIZE_UNSPEC)
2260 as_warn (_("Forcing byte displacement"));
2261 if (! issbyte (baseo))
2262 opP->error = _("byte displacement out of range");
2267 else if (siz1 == SIZE_UNSPEC
2269 && isvar (&opP->disp)
2270 && subs (&opP->disp) == NULL
2272 /* If the displacement needs pic
2273 relocation it cannot be relaxed. */
2274 && opP->disp.pic_reloc == pic_none
2278 /* The code in md_convert_frag_1 needs to be
2279 able to adjust nextword. Call frag_grow
2280 to ensure that we have enough space in
2281 the frag obstack to make all the bytes
2284 nextword += baseo & 0xff;
2286 add_frag (adds (&opP->disp), offs (&opP->disp),
2287 TAB (PCINDEX, SZ_UNDEF));
2295 nextword |= 0x40; /* No index reg */
2296 if (opP->index.reg >= ZDATA0
2297 && opP->index.reg <= ZDATA7)
2298 nextword |= (opP->index.reg - ZDATA0) << 12;
2299 else if (opP->index.reg >= ZADDR0
2300 || opP->index.reg <= ZADDR7)
2301 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2304 /* It isn't simple. */
2306 if (cpu_of_arch (current_architecture) < m68020
2307 || arch_coldfire_p (current_architecture))
2309 _("invalid operand mode for this architecture; needs 68020 or higher");
2312 /* If the guy specified a width, we assume that it is
2313 wide enough. Maybe it isn't. If so, we lose. */
2317 if (isvar (&opP->disp)
2319 : ! issword (baseo))
2324 else if (! isvar (&opP->disp) && baseo == 0)
2333 as_warn (_(":b not permitted; defaulting to :w"));
2343 /* Figure out innner displacement stuff */
2344 if (opP->mode == POST || opP->mode == PRE)
2346 if (cpu_of_arch (current_architecture) & cpu32)
2347 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2351 if (isvar (&opP->odisp)
2353 : ! issword (outro))
2358 else if (! isvar (&opP->odisp) && outro == 0)
2367 as_warn (_(":b not permitted; defaulting to :w"));
2376 if (opP->mode == POST
2377 && (nextword & 0x40) == 0)
2382 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2384 if (opP->reg == PC || opP->reg == ZPC)
2385 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2387 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2389 if (siz1 == SIZE_LONG)
2390 addword (baseo >> 16);
2391 if (siz1 != SIZE_UNSPEC)
2394 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2395 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2396 if (siz2 == SIZE_LONG)
2397 addword (outro >> 16);
2398 if (siz2 != SIZE_UNSPEC)
2404 nextword = get_num (&opP->disp, 80);
2405 switch (opP->disp.size)
2410 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2412 tmpreg = 0x38; /* 7.0 */
2416 if (isvar (&opP->disp)
2417 && !subs (&opP->disp)
2418 && adds (&opP->disp)
2420 /* If the displacement needs pic relocation it
2421 cannot be relaxed. */
2422 && opP->disp.pic_reloc == pic_none
2425 && !strchr ("~%&$?", s[0]))
2427 tmpreg = 0x3A; /* 7.2 */
2428 add_frag (adds (&opP->disp),
2430 TAB (ABSTOPCREL, SZ_UNDEF));
2433 /* Fall through into long */
2435 if (isvar (&opP->disp))
2436 add_fix ('l', &opP->disp, 0, 0);
2438 tmpreg = 0x39;/* 7.1 mode */
2439 addword (nextword >> 16);
2444 as_bad (_("unsupported byte value; use a different suffix"));
2446 case SIZE_WORD: /* Word */
2447 if (isvar (&opP->disp))
2448 add_fix ('w', &opP->disp, 0, 0);
2450 tmpreg = 0x38;/* 7.0 mode */
2458 as_bad (_("unknown/incorrect operand"));
2461 install_gen_operand (s[1], tmpreg);
2467 { /* JF: I hate floating point! */
2482 tmpreg = get_num (&opP->disp, tmpreg);
2483 if (isvar (&opP->disp))
2484 add_fix (s[1], &opP->disp, 0, 0);
2487 case 'b': /* Danger: These do no check for
2488 certain types of overflow.
2490 if (!isbyte (tmpreg))
2491 opP->error = _("out of range");
2492 insop (tmpreg, opcode);
2493 if (isvar (&opP->disp))
2494 the_ins.reloc[the_ins.nrel - 1].n =
2495 (opcode->m_codenum) * 2 + 1;
2498 if (!issbyte (tmpreg))
2499 opP->error = _("out of range");
2500 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2501 if (isvar (&opP->disp))
2502 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2505 if (!isword (tmpreg))
2506 opP->error = _("out of range");
2507 insop (tmpreg, opcode);
2508 if (isvar (&opP->disp))
2509 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2512 if (!issword (tmpreg))
2513 opP->error = _("out of range");
2514 insop (tmpreg, opcode);
2515 if (isvar (&opP->disp))
2516 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2519 /* Because of the way insop works, we put these two out
2521 insop (tmpreg, opcode);
2522 insop (tmpreg >> 16, opcode);
2523 if (isvar (&opP->disp))
2524 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2531 install_operand (s[1], tmpreg);
2542 install_operand (s[1], opP->reg - ADDR);
2546 tmpreg = get_num (&opP->disp, 80);
2550 add_fix ('B', &opP->disp, 1, -1);
2553 add_fix ('w', &opP->disp, 1, 0);
2558 if (! HAVE_LONG_BRANCH (current_architecture))
2559 as_warn (_("Can't use long branches on 68000/68010/5200"));
2560 the_ins.opcode[0] |= 0xff;
2561 add_fix ('l', &opP->disp, 1, 0);
2566 if (subs (&opP->disp)) /* We can't relax it */
2570 /* If the displacement needs pic relocation it cannot be
2572 if (opP->disp.pic_reloc != pic_none)
2575 /* This could either be a symbol, or an absolute
2576 address. If it's an absolute address, turn it into
2577 an absolute jump right here and keep it out of the
2579 if (adds (&opP->disp) == 0)
2581 if (the_ins.opcode[0] == 0x6000) /* jbra */
2582 the_ins.opcode[0] = 0x4EF1;
2583 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2584 the_ins.opcode[0] = 0x4EB1;
2587 the_ins.opcode[0] ^= 0x0100;
2588 the_ins.opcode[0] |= 0x0006;
2591 add_fix ('l', &opP->disp, 0, 0);
2597 /* Now we know it's going into the relaxer. Now figure
2598 out which mode. We try in this order of preference:
2599 long branch, absolute jump, byte/word branches only. */
2600 if (HAVE_LONG_BRANCH (current_architecture))
2601 add_frag (adds (&opP->disp), offs (&opP->disp),
2602 TAB (BRANCHBWL, SZ_UNDEF));
2603 else if (! flag_keep_pcrel)
2605 if ((the_ins.opcode[0] == 0x6000)
2606 || (the_ins.opcode[0] == 0x6100))
2607 add_frag (adds (&opP->disp), offs (&opP->disp),
2608 TAB (BRABSJUNC, SZ_UNDEF));
2610 add_frag (adds (&opP->disp), offs (&opP->disp),
2611 TAB (BRABSJCOND, SZ_UNDEF));
2614 add_frag (adds (&opP->disp), offs (&opP->disp),
2615 TAB (BRANCHBW, SZ_UNDEF));
2618 if (isvar (&opP->disp))
2620 /* Check for DBcc instructions. We can relax them,
2621 but only if we have long branches and/or absolute
2623 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2624 && (HAVE_LONG_BRANCH (current_architecture)
2625 || (! flag_keep_pcrel)))
2627 if (HAVE_LONG_BRANCH (current_architecture))
2628 add_frag (adds (&opP->disp), offs (&opP->disp),
2629 TAB (DBCCLBR, SZ_UNDEF));
2631 add_frag (adds (&opP->disp), offs (&opP->disp),
2632 TAB (DBCCABSJ, SZ_UNDEF));
2635 add_fix ('w', &opP->disp, 1, 0);
2639 case 'C': /* Fixed size LONG coproc branches */
2640 add_fix ('l', &opP->disp, 1, 0);
2644 case 'c': /* Var size Coprocesssor branches */
2645 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2647 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2648 add_fix ('l', &opP->disp, 1, 0);
2653 add_frag (adds (&opP->disp), offs (&opP->disp),
2654 TAB (FBRANCH, SZ_UNDEF));
2661 case 'C': /* Ignore it */
2664 case 'd': /* JF this is a kludge */
2665 install_operand ('s', opP->reg - ADDR);
2666 tmpreg = get_num (&opP->disp, 80);
2667 if (!issword (tmpreg))
2669 as_warn (_("Expression out of range, using 0"));
2676 install_operand (s[1], opP->reg - DATA);
2679 case 'E': /* Ignore it */
2683 install_operand (s[1], opP->reg - FP0);
2686 case 'G': /* Ignore it */
2691 tmpreg = opP->reg - COP0;
2692 install_operand (s[1], tmpreg);
2695 case 'J': /* JF foo */
2768 install_operand (s[1], tmpreg);
2772 tmpreg = get_num (&opP->disp, 55);
2773 install_operand (s[1], tmpreg & 0x7f);
2780 if (tmpreg & 0x7FF0000)
2781 as_bad (_("Floating point register in register list"));
2782 insop (reverse_16_bits (tmpreg), opcode);
2786 if (tmpreg & 0x700FFFF)
2787 as_bad (_("Wrong register in floating-point reglist"));
2788 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2796 if (tmpreg & 0x7FF0000)
2797 as_bad (_("Floating point register in register list"));
2798 insop (tmpreg, opcode);
2800 else if (s[1] == '8')
2802 if (tmpreg & 0x0FFFFFF)
2803 as_bad (_("incorrect register in reglist"));
2804 install_operand (s[1], tmpreg >> 24);
2808 if (tmpreg & 0x700FFFF)
2809 as_bad (_("wrong register in floating-point reglist"));
2811 install_operand (s[1], tmpreg >> 16);
2816 install_operand (s[1], get_num (&opP->disp, 60));
2820 tmpreg = ((opP->mode == DREG)
2821 ? 0x20 + (int) (opP->reg - DATA)
2822 : (get_num (&opP->disp, 40) & 0x1F));
2823 install_operand (s[1], tmpreg);
2827 tmpreg = get_num (&opP->disp, 10);
2830 install_operand (s[1], tmpreg);
2834 /* This depends on the fact that ADDR registers are eight
2835 more than their corresponding DATA regs, so the result
2836 will have the ADDR_REG bit set */
2837 install_operand (s[1], opP->reg - DATA);
2841 if (opP->mode == AINDR)
2842 install_operand (s[1], opP->reg - DATA);
2844 install_operand (s[1], opP->index.reg - DATA);
2848 if (opP->reg == FPI)
2850 else if (opP->reg == FPS)
2852 else if (opP->reg == FPC)
2856 install_operand (s[1], tmpreg);
2859 case 'S': /* Ignore it */
2863 install_operand (s[1], get_num (&opP->disp, 30));
2866 case 'U': /* Ignore it */
2885 as_fatal (_("failed sanity check"));
2886 } /* switch on cache token */
2887 install_operand (s[1], tmpreg);
2890 /* JF: These are out of order, I fear. */
2903 install_operand (s[1], tmpreg);
2929 install_operand (s[1], tmpreg);
2933 if (opP->reg == VAL)
2952 install_operand (s[1], tmpreg);
2966 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2977 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2983 install_operand (s[1], tmpreg);
2986 know (opP->reg == PSR);
2989 know (opP->reg == PCSR);
3004 install_operand (s[1], tmpreg);
3007 tmpreg = get_num (&opP->disp, 20);
3008 install_operand (s[1], tmpreg);
3010 case '_': /* used only for move16 absolute 32-bit address */
3011 if (isvar (&opP->disp))
3012 add_fix ('l', &opP->disp, 0, 0);
3013 tmpreg = get_num (&opP->disp, 80);
3014 addword (tmpreg >> 16);
3015 addword (tmpreg & 0xFFFF);
3018 install_operand (s[1], opP->reg - DATA0L);
3019 opP->reg -= (DATA0L);
3020 opP->reg &= 0x0F; /* remove upper/lower bit */
3027 /* By the time whe get here (FINALLY) the_ins contains the complete
3028 instruction, ready to be emitted. . . */
3032 reverse_16_bits (in)
3038 static int mask[16] =
3040 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3041 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3043 for (n = 0; n < 16; n++)
3046 out |= mask[15 - n];
3049 } /* reverse_16_bits() */
3058 static int mask[8] =
3060 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3063 for (n = 0; n < 8; n++)
3069 } /* reverse_8_bits() */
3071 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3072 (that value is chosen in the frag_var call in md_assemble). TYPE
3073 is the subtype of the frag to be generated; its primary type is
3074 rs_machine_dependent.
3076 The TYPE parameter is also used by md_convert_frag_1 and
3077 md_estimate_size_before_relax. The appropriate type of fixup will
3078 be emitted by md_convert_frag_1.
3080 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3082 install_operand (mode, val)
3089 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3092 the_ins.opcode[0] |= val << 9;
3095 the_ins.opcode[1] |= val << 12;
3098 the_ins.opcode[1] |= val << 6;
3101 the_ins.opcode[1] |= val;
3104 the_ins.opcode[2] |= val << 12;
3107 the_ins.opcode[2] |= val << 6;
3110 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3111 three words long! */
3113 the_ins.opcode[2] |= val;
3116 the_ins.opcode[1] |= val << 7;
3119 the_ins.opcode[1] |= val << 10;
3123 the_ins.opcode[1] |= val << 5;
3128 the_ins.opcode[1] |= (val << 10) | (val << 7);
3131 the_ins.opcode[1] |= (val << 12) | val;
3134 the_ins.opcode[0] |= val = 0xff;
3137 the_ins.opcode[0] |= val << 9;
3140 the_ins.opcode[1] |= val;
3143 the_ins.opcode[1] |= val;
3144 the_ins.numo++; /* What a hack */
3147 the_ins.opcode[1] |= val << 4;
3155 the_ins.opcode[0] |= (val << 6);
3158 the_ins.opcode[1] = (val >> 16);
3159 the_ins.opcode[2] = val & 0xffff;
3162 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3163 the_ins.opcode[0] |= ((val & 0x7) << 9);
3164 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3167 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3168 the_ins.opcode[0] |= ((val & 0x7) << 9);
3171 the_ins.opcode[1] |= val << 12;
3172 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3175 the_ins.opcode[0] |= (val & 0xF);
3176 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3179 the_ins.opcode[1] |= (val & 0xF);
3180 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3183 the_ins.opcode[1] |= ((val != 1) << 10);
3187 as_fatal (_("failed sanity check."));
3189 } /* install_operand() */
3192 install_gen_operand (mode, val)
3199 the_ins.opcode[0] |= val;
3202 /* This is a kludge!!! */
3203 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3212 the_ins.opcode[0] |= val;
3214 /* more stuff goes here */
3216 as_fatal (_("failed sanity check."));
3218 } /* install_gen_operand() */
3221 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3222 * then deal with the bitfield hack.
3226 crack_operand (str, opP)
3228 register struct m68k_op *opP;
3230 register int parens;
3232 register char *beg_str;
3240 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3246 else if (*str == ')')
3250 opP->error = _("Extra )");
3256 if (flag_mri && *str == '\'')
3257 inquote = ! inquote;
3259 if (!*str && parens)
3261 opP->error = _("Missing )");
3266 if (m68k_ip_op (beg_str, opP) != 0)
3273 c = *++str; /* JF bitfield hack */
3278 as_bad (_("Missing operand"));
3281 /* Detect MRI REG symbols and convert them to REGLSTs. */
3282 if (opP->mode == CONTROL && (int)opP->reg < 0)
3285 opP->mask = ~(int)opP->reg;
3292 /* This is the guts of the machine-dependent assembler. STR points to a
3293 machine dependent instruction. This function is supposed to emit
3294 the frags/bytes it assembles to.
3298 insert_reg (regname, regnum)
3299 const char *regname;
3305 #ifdef REGISTER_PREFIX
3306 if (!flag_reg_prefix_optional)
3308 buf[0] = REGISTER_PREFIX;
3309 strcpy (buf + 1, regname);
3314 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3315 &zero_address_frag));
3317 for (i = 0; regname[i]; i++)
3318 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3321 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3322 &zero_address_frag));
3331 static const struct init_entry init_table[] =
3390 /* control registers */
3391 { "sfc", SFC }, /* Source Function Code */
3393 { "dfc", DFC }, /* Destination Function Code */
3395 { "cacr", CACR }, /* Cache Control Register */
3396 { "caar", CAAR }, /* Cache Address Register */
3398 { "usp", USP }, /* User Stack Pointer */
3399 { "vbr", VBR }, /* Vector Base Register */
3400 { "msp", MSP }, /* Master Stack Pointer */
3401 { "isp", ISP }, /* Interrupt Stack Pointer */
3403 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3404 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3405 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3406 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3408 /* 68ec040 versions of same */
3409 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3410 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3411 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3412 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3414 /* mcf5200 versions of same. The ColdFire programmer's reference
3415 manual indicated that the order is 2,3,0,1, but Ken Rose
3416 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3417 { "acr0", ITT0 }, /* Access Control Unit 0 */
3418 { "acr1", ITT1 }, /* Access Control Unit 1 */
3419 { "acr2", DTT0 }, /* Access Control Unit 2 */
3420 { "acr3", DTT1 }, /* Access Control Unit 3 */
3422 { "tc", TC }, /* MMU Translation Control Register */
3425 { "mmusr", MMUSR }, /* MMU Status Register */
3426 { "srp", SRP }, /* User Root Pointer */
3427 { "urp", URP }, /* Supervisor Root Pointer */
3432 { "rombar", ROMBAR }, /* ROM Base Address Register */
3433 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3434 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3435 { "mbar", MBAR }, /* Module Base Address Register */
3436 /* end of control registers */
3470 /* 68ec030 versions of same */
3473 /* 68ec030 access control unit, identical to 030 MMU status reg */
3476 /* Suppressed data and address registers. */
3494 /* Upper and lower data and address registers, used by macw and msacw. */
3538 for (i = 0; init_table[i].name; i++)
3539 insert_reg (init_table[i].name, init_table[i].number);
3542 static int no_68851, no_68881;
3545 /* a.out machine type. Default to 68020. */
3546 int m68k_aout_machtype = 2;
3558 int shorts_this_frag;
3561 /* In MRI mode, the instruction and operands are separated by a
3562 space. Anything following the operands is a comment. The label
3563 has already been removed. */
3571 for (s = str; *s != '\0'; s++)
3573 if ((*s == ' ' || *s == '\t') && ! inquote)
3591 inquote = ! inquote;
3596 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3601 for (n = 0; n < the_ins.numargs; n++)
3602 if (the_ins.operands[n].error)
3604 er = the_ins.operands[n].error;
3610 as_bad (_("%s -- statement `%s' ignored"), er, str);
3614 /* If there is a current label, record that it marks an instruction. */
3615 if (current_label != NULL)
3617 current_label->text = 1;
3618 current_label = NULL;
3621 if (the_ins.nfrag == 0)
3623 /* No frag hacking involved; just put it out */
3624 toP = frag_more (2 * the_ins.numo);
3625 fromP = &the_ins.opcode[0];
3626 for (m = the_ins.numo; m; --m)
3628 md_number_to_chars (toP, (long) (*fromP), 2);
3632 /* put out symbol-dependent info */
3633 for (m = 0; m < the_ins.nrel; m++)
3635 switch (the_ins.reloc[m].wid)
3654 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3655 the_ins.reloc[m].wid);
3658 fixP = fix_new_exp (frag_now,
3659 ((toP - frag_now->fr_literal)
3660 - the_ins.numo * 2 + the_ins.reloc[m].n),
3662 &the_ins.reloc[m].exp,
3663 the_ins.reloc[m].pcrel,
3664 get_reloc_code (n, the_ins.reloc[m].pcrel,
3665 the_ins.reloc[m].pic_reloc));
3666 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3667 if (the_ins.reloc[m].wid == 'B')
3668 fixP->fx_signed = 1;
3673 /* There's some frag hacking */
3674 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3679 wid = 2 * the_ins.fragb[n].fragoff;
3681 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3682 toP = frag_more (wid);
3684 shorts_this_frag = 0;
3685 for (m = wid / 2; m; --m)
3687 md_number_to_chars (toP, (long) (*fromP), 2);
3692 for (m = 0; m < the_ins.nrel; m++)
3694 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3696 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3699 wid = the_ins.reloc[m].wid;
3702 the_ins.reloc[m].wid = 0;
3703 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3705 fixP = fix_new_exp (frag_now,
3706 ((toP - frag_now->fr_literal)
3707 - the_ins.numo * 2 + the_ins.reloc[m].n),
3709 &the_ins.reloc[m].exp,
3710 the_ins.reloc[m].pcrel,
3711 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3712 the_ins.reloc[m].pic_reloc));
3713 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3715 (void) frag_var (rs_machine_dependent, 10, 0,
3716 (relax_substateT) (the_ins.fragb[n].fragty),
3717 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3719 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3720 shorts_this_frag = 0;
3723 toP = frag_more (n * sizeof (short));
3726 md_number_to_chars (toP, (long) (*fromP), 2);
3732 for (m = 0; m < the_ins.nrel; m++)
3736 wid = the_ins.reloc[m].wid;
3739 the_ins.reloc[m].wid = 0;
3740 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3742 fixP = fix_new_exp (frag_now,
3743 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3744 - shorts_this_frag * 2),
3746 &the_ins.reloc[m].exp,
3747 the_ins.reloc[m].pcrel,
3748 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3749 the_ins.reloc[m].pic_reloc));
3750 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3758 * md_begin -- set up hash tables with 68000 instructions.
3759 * similar to what the vax assembler does. ---phr
3761 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3762 a copy of it at runtime, adding in the information we want but isn't
3763 there. I think it'd be better to have an awk script hack the table
3764 at compile time. Or even just xstr the table and use it as-is. But
3765 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3768 register const struct m68k_opcode *ins;
3769 register struct m68k_incant *hack, *slak;
3770 register const char *retval = 0; /* empty string, or error msg text */
3776 flag_reg_prefix_optional = 1;
3778 if (! m68k_rel32_from_cmdline)
3782 op_hash = hash_new ();
3784 obstack_begin (&robyn, 4000);
3785 for (i = 0; i < m68k_numopcodes; i++)
3787 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3790 ins = &m68k_opcodes[i];
3791 /* We *could* ignore insns that don't match our arch here
3792 but just leaving them out of the hash. */
3793 slak->m_operands = ins->args;
3794 slak->m_opnum = strlen (slak->m_operands) / 2;
3795 slak->m_arch = ins->arch;
3796 slak->m_opcode = ins->opcode;
3797 /* This is kludgey */
3798 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3799 if (i + 1 != m68k_numopcodes
3800 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3802 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3807 slak = slak->m_next;
3811 retval = hash_insert (op_hash, ins->name, (char *) hack);
3813 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3816 for (i = 0; i < m68k_numaliases; i++)
3818 const char *name = m68k_opcode_aliases[i].primary;
3819 const char *alias = m68k_opcode_aliases[i].alias;
3820 PTR val = hash_find (op_hash, name);
3822 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3823 retval = hash_insert (op_hash, alias, val);
3825 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3828 /* In MRI mode, all unsized branches are variable sized. Normally,
3829 they are word sized. */
3832 static struct m68k_opcode_alias mri_aliases[] =
3853 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3856 const char *name = mri_aliases[i].primary;
3857 const char *alias = mri_aliases[i].alias;
3858 PTR val = hash_find (op_hash, name);
3860 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3861 retval = hash_jam (op_hash, alias, val);
3863 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3867 for (i = 0; i < (int) sizeof (mklower_table); i++)
3868 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3870 for (i = 0; i < (int) sizeof (notend_table); i++)
3872 notend_table[i] = 0;
3873 alt_notend_table[i] = 0;
3875 notend_table[','] = 1;
3876 notend_table['{'] = 1;
3877 notend_table['}'] = 1;
3878 alt_notend_table['a'] = 1;
3879 alt_notend_table['A'] = 1;
3880 alt_notend_table['d'] = 1;
3881 alt_notend_table['D'] = 1;
3882 alt_notend_table['#'] = 1;
3883 alt_notend_table['&'] = 1;
3884 alt_notend_table['f'] = 1;
3885 alt_notend_table['F'] = 1;
3886 #ifdef REGISTER_PREFIX
3887 alt_notend_table[REGISTER_PREFIX] = 1;
3890 /* We need to put '(' in alt_notend_table to handle
3891 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3893 alt_notend_table['('] = 1;
3895 /* We need to put '@' in alt_notend_table to handle
3896 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3898 alt_notend_table['@'] = 1;
3900 /* We need to put digits in alt_notend_table to handle
3901 bfextu %d0{24:1},%d0
3903 alt_notend_table['0'] = 1;
3904 alt_notend_table['1'] = 1;
3905 alt_notend_table['2'] = 1;
3906 alt_notend_table['3'] = 1;
3907 alt_notend_table['4'] = 1;
3908 alt_notend_table['5'] = 1;
3909 alt_notend_table['6'] = 1;
3910 alt_notend_table['7'] = 1;
3911 alt_notend_table['8'] = 1;
3912 alt_notend_table['9'] = 1;
3914 #ifndef MIT_SYNTAX_ONLY
3915 /* Insert pseudo ops, these have to go into the opcode table since
3916 gas expects pseudo ops to start with a dot */
3919 while (mote_pseudo_table[n].poc_name)
3921 hack = (struct m68k_incant *)
3922 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3923 hash_insert (op_hash,
3924 mote_pseudo_table[n].poc_name, (char *) hack);
3925 hack->m_operands = 0;
3935 record_alignment (text_section, 2);
3936 record_alignment (data_section, 2);
3937 record_alignment (bss_section, 2);
3942 select_control_regs ()
3944 /* Note which set of "movec" control registers is available. */
3945 switch (cpu_of_arch (current_architecture))
3948 control_regs = m68000_control_regs;
3951 control_regs = m68010_control_regs;
3955 control_regs = m68020_control_regs;
3958 control_regs = m68040_control_regs;
3961 control_regs = m68060_control_regs;
3964 control_regs = cpu32_control_regs;
3970 control_regs = mcf_control_regs;
3978 m68k_init_after_args ()
3980 if (cpu_of_arch (current_architecture) == 0)
3983 const char *default_cpu = TARGET_CPU;
3985 if (*default_cpu == 'm')
3987 for (i = 0; i < n_archs; i++)
3988 if (strcasecmp (default_cpu, archs[i].name) == 0)
3992 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3993 current_architecture |= m68020;
3996 current_architecture |= archs[i].arch;
3998 /* Permit m68881 specification with all cpus; those that can't work
3999 with a coprocessor could be doing emulation. */
4000 if (current_architecture & m68851)
4002 if (current_architecture & m68040)
4004 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4007 /* What other incompatibilities could we check for? */
4009 /* Toss in some default assumptions about coprocessors. */
4011 && (cpu_of_arch (current_architecture)
4012 /* Can CPU32 have a 68881 coprocessor?? */
4013 & (m68020 | m68030 | cpu32)))
4015 current_architecture |= m68881;
4018 && (cpu_of_arch (current_architecture) & m68020up) != 0
4019 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4021 current_architecture |= m68851;
4023 if (no_68881 && (current_architecture & m68881))
4024 as_bad (_("options for 68881 and no-68881 both given"));
4025 if (no_68851 && (current_architecture & m68851))
4026 as_bad (_("options for 68851 and no-68851 both given"));
4029 /* Work out the magic number. This isn't very general. */
4030 if (current_architecture & m68000)
4031 m68k_aout_machtype = 0;
4032 else if (current_architecture & m68010)
4033 m68k_aout_machtype = 1;
4034 else if (current_architecture & m68020)
4035 m68k_aout_machtype = 2;
4037 m68k_aout_machtype = 2;
4040 /* Note which set of "movec" control registers is available. */
4041 select_control_regs ();
4043 if (cpu_of_arch (current_architecture) < m68020
4044 || arch_coldfire_p (current_architecture))
4045 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4048 /* This is called when a label is defined. */
4051 m68k_frob_label (sym)
4054 struct label_line *n;
4056 n = (struct label_line *) xmalloc (sizeof *n);
4059 as_where (&n->file, &n->line);
4065 /* This is called when a value that is not an instruction is emitted. */
4068 m68k_flush_pending_output ()
4070 current_label = NULL;
4073 /* This is called at the end of the assembly, when the final value of
4074 the label is known. We warn if this is a text symbol aligned at an
4078 m68k_frob_symbol (sym)
4081 if (S_GET_SEGMENT (sym) == reg_section
4082 && (int) S_GET_VALUE (sym) < 0)
4084 S_SET_SEGMENT (sym, absolute_section);
4085 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4087 else if ((S_GET_VALUE (sym) & 1) != 0)
4089 struct label_line *l;
4091 for (l = labels; l != NULL; l = l->next)
4093 if (l->label == sym)
4096 as_warn_where (l->file, l->line,
4097 _("text label `%s' aligned to odd boundary"),
4105 /* This is called if we go in or out of MRI mode because of the .mri
4109 m68k_mri_mode_change (on)
4114 if (! flag_reg_prefix_optional)
4116 flag_reg_prefix_optional = 1;
4117 #ifdef REGISTER_PREFIX
4122 if (! m68k_rel32_from_cmdline)
4127 if (! reg_prefix_optional_seen)
4129 #ifdef REGISTER_PREFIX_OPTIONAL
4130 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4132 flag_reg_prefix_optional = 0;
4134 #ifdef REGISTER_PREFIX
4139 if (! m68k_rel32_from_cmdline)
4144 /* Equal to MAX_PRECISION in atof-ieee.c */
4145 #define MAX_LITTLENUMS 6
4147 /* Turn a string in input_line_pointer into a floating point constant
4148 of type TYPE, and store the appropriate bytes in *LITP. The number
4149 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4150 returned, or NULL on OK. */
4153 md_atof (type, litP, sizeP)
4159 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4160 LITTLENUM_TYPE *wordP;
4191 return _("Bad call to MD_ATOF()");
4193 t = atof_ieee (input_line_pointer, type, words);
4195 input_line_pointer = t;
4197 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4198 for (wordP = words; prec--;)
4200 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4201 litP += sizeof (LITTLENUM_TYPE);
4207 md_number_to_chars (buf, val, n)
4212 number_to_chars_bigendian (buf, val, n);
4216 md_apply_fix_2 (fixP, val)
4220 addressT upper_limit;
4221 offsetT lower_limit;
4223 /* This is unnecessary but it convinces the native rs6000 compiler
4224 to generate the code we want. */
4225 char *buf = fixP->fx_frag->fr_literal;
4226 buf += fixP->fx_where;
4227 /* end ibm compiler workaround */
4229 if (val & 0x80000000)
4230 val |= ~(addressT)0x7fffffff;
4237 memset (buf, 0, fixP->fx_size);
4238 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4240 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4241 && !S_IS_DEFINED (fixP->fx_addsy)
4242 && !S_IS_WEAK (fixP->fx_addsy))
4243 S_SET_WEAK (fixP->fx_addsy);
4248 #ifdef BFD_ASSEMBLER
4249 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4250 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4254 switch (fixP->fx_size)
4256 /* The cast to offsetT below are necessary to make code correct for
4257 machines where ints are smaller than offsetT */
4261 lower_limit = - (offsetT) 0x80;
4264 *buf++ = (val >> 8);
4266 upper_limit = 0x7fff;
4267 lower_limit = - (offsetT) 0x8000;
4270 *buf++ = (val >> 24);
4271 *buf++ = (val >> 16);
4272 *buf++ = (val >> 8);
4274 upper_limit = 0x7fffffff;
4275 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4278 BAD_CASE (fixP->fx_size);
4281 /* Fix up a negative reloc. */
4282 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4284 fixP->fx_addsy = fixP->fx_subsy;
4285 fixP->fx_subsy = NULL;
4289 /* For non-pc-relative values, it's conceivable we might get something
4290 like "0xff" for a byte field. So extend the upper part of the range
4291 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4292 so that we can do any range checking at all. */
4293 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4294 upper_limit = upper_limit * 2 + 1;
4296 if ((addressT) val > upper_limit
4297 && (val > 0 || val < lower_limit))
4298 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4300 /* A one byte PC-relative reloc means a short branch. We can't use
4301 a short branch with a value of 0 or -1, because those indicate
4302 different opcodes (branches with longer offsets). fixup_segment
4303 in write.c may have clobbered fx_pcrel, so we need to examine the
4306 #ifdef BFD_ASSEMBLER
4307 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4310 && fixP->fx_size == 1
4311 && (fixP->fx_addsy == NULL
4312 || S_IS_DEFINED (fixP->fx_addsy))
4313 && (val == 0 || val == -1))
4314 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4317 #ifdef BFD_ASSEMBLER
4319 md_apply_fix (fixP, valp)
4323 md_apply_fix_2 (fixP, (addressT) *valp);
4327 void md_apply_fix (fixP, val)
4331 md_apply_fix_2 (fixP, (addressT) val);
4335 /* *fragP has been relaxed to its final size, and now needs to have
4336 the bytes inside it modified to conform to the new size There is UGLY
4340 md_convert_frag_1 (fragP)
4341 register fragS *fragP;
4346 /* Address in object code of the displacement. */
4347 register int object_address = fragP->fr_fix + fragP->fr_address;
4349 /* Address in gas core of the place to store the displacement. */
4350 /* This convinces the native rs6000 compiler to generate the code we
4352 register char *buffer_address = fragP->fr_literal;
4353 buffer_address += fragP->fr_fix;
4354 /* end ibm compiler workaround */
4356 /* The displacement of the address, from current location. */
4357 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4358 disp = (disp + fragP->fr_offset) - object_address;
4360 #ifdef BFD_ASSEMBLER
4361 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
4364 switch (fragP->fr_subtype)
4366 case TAB (BRANCHBWL, BYTE):
4367 case TAB (BRABSJUNC, BYTE):
4368 case TAB (BRABSJCOND, BYTE):
4369 case TAB (BRANCHBW, BYTE):
4370 know (issbyte (disp));
4372 as_bad (_("short branch with zero offset: use :w"));
4373 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4374 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4375 fixP->fx_pcrel_adjust = -1;
4377 case TAB (BRANCHBWL, SHORT):
4378 case TAB (BRABSJUNC, SHORT):
4379 case TAB (BRABSJCOND, SHORT):
4380 case TAB (BRANCHBW, SHORT):
4381 fragP->fr_opcode[1] = 0x00;
4382 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4383 1, RELAX_RELOC_PC16);
4386 case TAB (BRANCHBWL, LONG):
4387 fragP->fr_opcode[1] = (char) 0xFF;
4388 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4389 1, RELAX_RELOC_PC32);
4392 case TAB (BRABSJUNC, LONG):
4393 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4395 fragP->fr_opcode[0] = 0x4E;
4396 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4397 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4398 0, RELAX_RELOC_ABS32);
4401 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4403 fragP->fr_opcode[0] = 0x4E;
4404 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4405 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4406 0, RELAX_RELOC_ABS32);
4411 /* This cannot happen, because jbsr and jbra are the only two
4412 unconditional branches. */
4416 case TAB (BRABSJCOND, LONG):
4417 /* Only Bcc 68000 instructions can come here. */
4418 /* Change bcc into b!cc/jmp absl long. */
4420 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4421 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4423 /* JF: these used to be fr_opcode[2,3], but they may be in a
4424 different frag, in which case refering to them is a no-no.
4425 Only fr_opcode[0,1] are guaranteed to work. */
4426 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4427 *buffer_address++ = (char) 0xf9;
4428 fragP->fr_fix += 2; /* account for jmp instruction */
4429 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4430 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4433 case TAB (FBRANCH, SHORT):
4434 know ((fragP->fr_opcode[1] & 0x40) == 0);
4435 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4436 1, RELAX_RELOC_PC16);
4439 case TAB (FBRANCH, LONG):
4440 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4441 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4442 1, RELAX_RELOC_PC32);
4445 case TAB (DBCCLBR, SHORT):
4446 case TAB (DBCCABSJ, SHORT):
4447 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4448 1, RELAX_RELOC_PC16);
4451 case TAB (DBCCLBR, LONG):
4452 /* only DBcc instructions can come here */
4453 /* Change dbcc into dbcc/bral. */
4455 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4456 *buffer_address++ = 0x00; /* branch offset = 4 */
4457 *buffer_address++ = 0x04;
4458 *buffer_address++ = 0x60; /* put in bra pc+6 */
4459 *buffer_address++ = 0x06;
4460 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4461 *buffer_address++ = (char) 0xff;
4463 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4464 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4468 case TAB (DBCCABSJ, LONG):
4469 /* only DBcc instructions can come here */
4470 /* Change dbcc into dbcc/jmp. */
4472 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4473 *buffer_address++ = 0x00; /* branch offset = 4 */
4474 *buffer_address++ = 0x04;
4475 *buffer_address++ = 0x60; /* put in bra pc+6 */
4476 *buffer_address++ = 0x06;
4477 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4478 *buffer_address++ = (char) 0xf9;
4480 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4481 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4485 case TAB (PCREL1632, SHORT):
4486 fragP->fr_opcode[1] &= ~0x3F;
4487 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4488 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4489 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4492 case TAB (PCREL1632, LONG):
4493 /* Already set to mode 7.3; this indicates: PC indirect with
4494 suppressed index, 32-bit displacement. */
4495 *buffer_address++ = 0x01;
4496 *buffer_address++ = 0x70;
4498 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4499 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4500 fixP->fx_pcrel_adjust = 2;
4503 case TAB (PCINDEX, BYTE):
4504 assert (fragP->fr_fix >= 2);
4505 buffer_address[-2] &= ~1;
4506 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4507 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4508 fixP->fx_pcrel_adjust = 1;
4510 case TAB (PCINDEX, SHORT):
4511 assert (fragP->fr_fix >= 2);
4512 buffer_address[-2] |= 0x1;
4513 buffer_address[-1] = 0x20;
4514 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4515 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4516 fixP->fx_pcrel_adjust = 2;
4519 case TAB (PCINDEX, LONG):
4520 assert (fragP->fr_fix >= 2);
4521 buffer_address[-2] |= 0x1;
4522 buffer_address[-1] = 0x30;
4523 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4524 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4525 fixP->fx_pcrel_adjust = 2;
4528 case TAB (ABSTOPCREL, SHORT):
4529 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4530 1, RELAX_RELOC_PC16);
4533 case TAB (ABSTOPCREL, LONG):
4534 /* The thing to do here is force it to ABSOLUTE LONG, since
4535 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4536 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4538 fragP->fr_opcode[1] &= ~0x3F;
4539 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4540 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4541 0, RELAX_RELOC_ABS32);
4547 #ifndef BFD_ASSEMBLER
4550 md_convert_frag (headers, sec, fragP)
4551 object_headers *headers ATTRIBUTE_UNUSED;
4552 segT sec ATTRIBUTE_UNUSED;
4555 md_convert_frag_1 (fragP);
4561 md_convert_frag (abfd, sec, fragP)
4562 bfd *abfd ATTRIBUTE_UNUSED;
4563 segT sec ATTRIBUTE_UNUSED;
4566 md_convert_frag_1 (fragP);
4570 /* Force truly undefined symbols to their maximum size, and generally set up
4571 the frag list to be relaxed
4574 md_estimate_size_before_relax (fragP, segment)
4575 register fragS *fragP;
4580 old_fix = fragP->fr_fix;
4582 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4583 switch (fragP->fr_subtype)
4585 case TAB (BRANCHBWL, SZ_UNDEF):
4586 case TAB (BRABSJUNC, SZ_UNDEF):
4587 case TAB (BRABSJCOND, SZ_UNDEF):
4589 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4590 && relaxable_symbol (fragP->fr_symbol))
4592 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4594 else if (flag_short_refs)
4596 /* Symbol is undefined and we want short ref. */
4597 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4601 /* Symbol is still undefined. Make it LONG. */
4602 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4607 case TAB (BRANCHBW, SZ_UNDEF):
4609 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4610 && relaxable_symbol (fragP->fr_symbol))
4612 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4616 /* Symbol is undefined and we don't have long branches. */
4617 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4622 case TAB (FBRANCH, SZ_UNDEF):
4623 case TAB (DBCCLBR, SZ_UNDEF):
4624 case TAB (DBCCABSJ, SZ_UNDEF):
4625 case TAB (PCREL1632, SZ_UNDEF):
4627 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4628 && relaxable_symbol (fragP->fr_symbol))
4631 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4635 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4640 case TAB (PCINDEX, SZ_UNDEF):
4641 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4642 && relaxable_symbol (fragP->fr_symbol)))
4644 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4648 fragP->fr_subtype = TAB (PCINDEX, LONG);
4652 case TAB (ABSTOPCREL, SZ_UNDEF):
4654 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4655 && relaxable_symbol (fragP->fr_symbol)))
4657 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4661 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4670 /* Now that SZ_UNDEF are taken care of, check others. */
4671 switch (fragP->fr_subtype)
4673 case TAB (BRANCHBWL, BYTE):
4674 case TAB (BRABSJUNC, BYTE):
4675 case TAB (BRABSJCOND, BYTE):
4676 case TAB (BRANCHBW, BYTE):
4677 /* We can't do a short jump to the next instruction, so in that
4678 case we force word mode. At this point S_GET_VALUE should
4679 return the offset of the symbol within its frag. If the
4680 symbol is at the start of a frag, and it is the next frag
4681 with any data in it (usually this is just the next frag, but
4682 assembler listings may introduce empty frags), we must use
4684 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4689 stop = symbol_get_frag (fragP->fr_symbol);
4690 for (l = fragP->fr_next; l != stop; l = l->fr_next)
4691 if (l->fr_fix + l->fr_var != 0)
4695 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4702 fragP->fr_var = md_relax_table[fragP->fr_subtype].rlx_length;
4703 return fragP->fr_var + fragP->fr_fix - old_fix;
4706 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4707 /* the bit-field entries in the relocation_info struct plays hell
4708 with the byte-order problems of cross-assembly. So as a hack,
4709 I added this mach. dependent ri twiddler. Ugly, but it gets
4711 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4712 are symbolnum, most sig. byte first. Last byte is broken up with
4713 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4714 nibble as nuthin. (on Sun 3 at least) */
4715 /* Translate the internal relocation information into target-specific
4719 md_ri_to_chars (the_bytes, ri)
4721 struct reloc_info_generic *ri;
4724 md_number_to_chars (the_bytes, ri->r_address, 4);
4725 /* now the fun stuff */
4726 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4727 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4728 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4729 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4730 ((ri->r_extern << 4) & 0x10));
4733 #endif /* comment */
4735 #ifndef BFD_ASSEMBLER
4737 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4740 relax_addressT segment_address_in_file;
4743 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4744 * Out: GNU LD relocation length code: 0, 1, or 2.
4747 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4750 know (fixP->fx_addsy != NULL);
4752 md_number_to_chars (where,
4753 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4756 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4757 ? S_GET_TYPE (fixP->fx_addsy)
4758 : fixP->fx_addsy->sy_number);
4760 where[4] = (r_symbolnum >> 16) & 0x0ff;
4761 where[5] = (r_symbolnum >> 8) & 0x0ff;
4762 where[6] = r_symbolnum & 0x0ff;
4763 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4764 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4768 #endif /* OBJ_AOUT or OBJ_BOUT */
4770 #ifndef WORKING_DOT_WORD
4771 CONST int md_short_jump_size = 4;
4772 CONST int md_long_jump_size = 6;
4775 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4777 addressT from_addr, to_addr;
4778 fragS *frag ATTRIBUTE_UNUSED;
4779 symbolS *to_symbol ATTRIBUTE_UNUSED;
4783 offset = to_addr - (from_addr + 2);
4785 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4786 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4790 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4792 addressT from_addr, to_addr;
4798 if (!HAVE_LONG_BRANCH(current_architecture))
4800 offset = to_addr - S_GET_VALUE (to_symbol);
4801 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4802 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4803 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4808 offset = to_addr - (from_addr + 2);
4809 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4810 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4816 /* Different values of OK tell what its OK to return. Things that
4817 aren't OK are an error (what a shock, no?)
4820 10: Absolute 1:8 only
4821 20: Absolute 0:7 only
4822 30: absolute 0:15 only
4823 40: Absolute 0:31 only
4824 50: absolute 0:127 only
4825 55: absolute -64:63 only
4826 60: absolute -128:127 only
4827 70: absolute 0:4095 only
4834 struct m68k_exp *exp;
4837 if (exp->exp.X_op == O_absent)
4839 /* Do the same thing the VAX asm does */
4840 op (exp) = O_constant;
4846 as_warn (_("expression out of range: defaulting to 1"));
4850 else if (exp->exp.X_op == O_constant)
4855 if (offs (exp) < 1 || offs (exp) > 8)
4857 as_warn (_("expression out of range: defaulting to 1"));
4862 if (offs (exp) < 0 || offs (exp) > 7)
4866 if (offs (exp) < 0 || offs (exp) > 15)
4870 if (offs (exp) < 0 || offs (exp) > 32)
4874 if (offs (exp) < 0 || offs (exp) > 127)
4878 if (offs (exp) < -64 || offs (exp) > 63)
4882 if (offs (exp) < -128 || offs (exp) > 127)
4886 if (offs (exp) < 0 || offs (exp) > 4095)
4889 as_warn (_("expression out of range: defaulting to 0"));
4897 else if (exp->exp.X_op == O_big)
4899 if (offs (exp) <= 0 /* flonum */
4900 && (ok == 80 /* no bignums */
4901 || (ok > 10 /* small-int ranges including 0 ok */
4902 /* If we have a flonum zero, a zero integer should
4903 do as well (e.g., in moveq). */
4904 && generic_floating_point_number.exponent == 0
4905 && generic_floating_point_number.low[0] == 0)))
4907 /* HACK! Turn it into a long */
4908 LITTLENUM_TYPE words[6];
4910 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4911 op (exp) = O_constant;
4914 offs (exp) = words[1] | (words[0] << 16);
4918 op (exp) = O_constant;
4921 offs (exp) = (ok == 10) ? 1 : 0;
4922 as_warn (_("Can't deal with expression; defaulting to %ld"),
4928 if (ok >= 10 && ok <= 70)
4930 op (exp) = O_constant;
4933 offs (exp) = (ok == 10) ? 1 : 0;
4934 as_warn (_("Can't deal with expression; defaulting to %ld"),
4939 if (exp->size != SIZE_UNSPEC)
4947 if (!isbyte (offs (exp)))
4948 as_warn (_("expression doesn't fit in BYTE"));
4951 if (!isword (offs (exp)))
4952 as_warn (_("expression doesn't fit in WORD"));
4960 /* These are the back-ends for the various machine dependent pseudo-ops. */
4964 int ignore ATTRIBUTE_UNUSED;
4966 subseg_set (data_section, 1);
4967 demand_empty_rest_of_line ();
4972 int ignore ATTRIBUTE_UNUSED;
4974 subseg_set (data_section, 2);
4975 demand_empty_rest_of_line ();
4980 int ignore ATTRIBUTE_UNUSED;
4982 /* We don't support putting frags in the BSS segment, we fake it
4983 by marking in_bss, then looking at s_skip for clues. */
4985 subseg_set (bss_section, 0);
4986 demand_empty_rest_of_line ();
4991 int ignore ATTRIBUTE_UNUSED;
4994 register long temp_fill;
4996 temp = 1; /* JF should be 2? */
4997 temp_fill = get_absolute_expression ();
4998 if (!need_pass_2) /* Never make frag if expect extra pass. */
4999 frag_align (temp, (int) temp_fill, 0);
5000 demand_empty_rest_of_line ();
5001 record_alignment (now_seg, temp);
5006 int ignore ATTRIBUTE_UNUSED;
5008 demand_empty_rest_of_line ();
5011 /* Pseudo-ops handled for MRI compatibility. */
5013 /* This function returns non-zero if the argument is a conditional
5014 pseudo-op. This is called when checking whether a pending
5015 alignment is needed. */
5018 m68k_conditional_pseudoop (pop)
5021 return (pop->poc_handler == s_mri_if
5022 || pop->poc_handler == s_mri_else);
5025 /* Handle an MRI style chip specification. */
5034 s = input_line_pointer;
5035 /* We can't use get_symbol_end since the processor names are not proper
5037 while (is_part_of_name (c = *input_line_pointer++))
5039 *--input_line_pointer = 0;
5040 for (i = 0; i < n_archs; i++)
5041 if (strcasecmp (s, archs[i].name) == 0)
5045 as_bad (_("%s: unrecognized processor name"), s);
5046 *input_line_pointer = c;
5047 ignore_rest_of_line ();
5050 *input_line_pointer = c;
5052 if (*input_line_pointer == '/')
5053 current_architecture = 0;
5055 current_architecture &= m68881 | m68851;
5056 current_architecture |= archs[i].arch;
5058 while (*input_line_pointer == '/')
5060 ++input_line_pointer;
5061 s = input_line_pointer;
5062 /* We can't use get_symbol_end since the processor names are not
5064 while (is_part_of_name (c = *input_line_pointer++))
5066 *--input_line_pointer = 0;
5067 if (strcmp (s, "68881") == 0)
5068 current_architecture |= m68881;
5069 else if (strcmp (s, "68851") == 0)
5070 current_architecture |= m68851;
5071 *input_line_pointer = c;
5074 /* Update info about available control registers. */
5075 select_control_regs ();
5078 /* The MRI CHIP pseudo-op. */
5082 int ignore ATTRIBUTE_UNUSED;
5088 stop = mri_comment_field (&stopc);
5091 mri_comment_end (stop, stopc);
5092 demand_empty_rest_of_line ();
5095 /* The MRI FOPT pseudo-op. */
5099 int ignore ATTRIBUTE_UNUSED;
5103 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5107 input_line_pointer += 3;
5108 temp = get_absolute_expression ();
5109 if (temp < 0 || temp > 7)
5110 as_bad (_("bad coprocessor id"));
5112 m68k_float_copnum = COP0 + temp;
5116 as_bad (_("unrecognized fopt option"));
5117 ignore_rest_of_line ();
5121 demand_empty_rest_of_line ();
5124 /* The structure used to handle the MRI OPT pseudo-op. */
5128 /* The name of the option. */
5131 /* If this is not NULL, just call this function. The first argument
5132 is the ARG field of this structure, the second argument is
5133 whether the option was negated. */
5134 void (*pfn) PARAMS ((int arg, int on));
5136 /* If this is not NULL, and the PFN field is NULL, set the variable
5137 this points to. Set it to the ARG field if the option was not
5138 negated, and the NOTARG field otherwise. */
5141 /* The value to pass to PFN or to assign to *PVAR. */
5144 /* The value to assign to *PVAR if the option is negated. If PFN is
5145 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5146 the option may not be negated. */
5150 /* The table used to handle the MRI OPT pseudo-op. */
5152 static void skip_to_comma PARAMS ((int, int));
5153 static void opt_nest PARAMS ((int, int));
5154 static void opt_chip PARAMS ((int, int));
5155 static void opt_list PARAMS ((int, int));
5156 static void opt_list_symbols PARAMS ((int, int));
5158 static const struct opt_action opt_table[] =
5160 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5162 /* We do relaxing, so there is little use for these options. */
5163 { "b", 0, 0, 0, 0 },
5164 { "brs", 0, 0, 0, 0 },
5165 { "brb", 0, 0, 0, 0 },
5166 { "brl", 0, 0, 0, 0 },
5167 { "brw", 0, 0, 0, 0 },
5169 { "c", 0, 0, 0, 0 },
5170 { "cex", 0, 0, 0, 0 },
5171 { "case", 0, &symbols_case_sensitive, 1, 0 },
5172 { "cl", 0, 0, 0, 0 },
5173 { "cre", 0, 0, 0, 0 },
5174 { "d", 0, &flag_keep_locals, 1, 0 },
5175 { "e", 0, 0, 0, 0 },
5176 { "f", 0, &flag_short_refs, 1, 0 },
5177 { "frs", 0, &flag_short_refs, 1, 0 },
5178 { "frl", 0, &flag_short_refs, 0, 1 },
5179 { "g", 0, 0, 0, 0 },
5180 { "i", 0, 0, 0, 0 },
5181 { "m", 0, 0, 0, 0 },
5182 { "mex", 0, 0, 0, 0 },
5183 { "mc", 0, 0, 0, 0 },
5184 { "md", 0, 0, 0, 0 },
5185 { "nest", opt_nest, 0, 0, 0 },
5186 { "next", skip_to_comma, 0, 0, 0 },
5187 { "o", 0, 0, 0, 0 },
5188 { "old", 0, 0, 0, 0 },
5189 { "op", skip_to_comma, 0, 0, 0 },
5190 { "pco", 0, 0, 0, 0 },
5191 { "p", opt_chip, 0, 0, 0 },
5192 { "pcr", 0, 0, 0, 0 },
5193 { "pcs", 0, 0, 0, 0 },
5194 { "r", 0, 0, 0, 0 },
5195 { "quick", 0, &m68k_quick, 1, 0 },
5196 { "rel32", 0, &m68k_rel32, 1, 0 },
5197 { "s", opt_list, 0, 0, 0 },
5198 { "t", opt_list_symbols, 0, 0, 0 },
5199 { "w", 0, &flag_no_warnings, 0, 1 },
5203 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5205 /* The MRI OPT pseudo-op. */
5209 int ignore ATTRIBUTE_UNUSED;
5217 const struct opt_action *o;
5222 if (*input_line_pointer == '-')
5224 ++input_line_pointer;
5227 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5229 input_line_pointer += 2;
5233 s = input_line_pointer;
5234 c = get_symbol_end ();
5236 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5238 if (strcasecmp (s, o->name) == 0)
5242 /* Restore input_line_pointer now in case the option
5244 *input_line_pointer = c;
5245 (*o->pfn) (o->arg, t);
5247 else if (o->pvar != NULL)
5249 if (! t && o->arg == o->notarg)
5250 as_bad (_("option `%s' may not be negated"), s);
5251 *input_line_pointer = c;
5252 *o->pvar = t ? o->arg : o->notarg;
5255 *input_line_pointer = c;
5261 as_bad (_("option `%s' not recognized"), s);
5262 *input_line_pointer = c;
5265 while (*input_line_pointer++ == ',');
5267 /* Move back to terminating character. */
5268 --input_line_pointer;
5269 demand_empty_rest_of_line ();
5272 /* Skip ahead to a comma. This is used for OPT options which we do
5273 not suppor tand which take arguments. */
5276 skip_to_comma (arg, on)
5277 int arg ATTRIBUTE_UNUSED;
5278 int on ATTRIBUTE_UNUSED;
5280 while (*input_line_pointer != ','
5281 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5282 ++input_line_pointer;
5285 /* Handle the OPT NEST=depth option. */
5289 int arg ATTRIBUTE_UNUSED;
5290 int on ATTRIBUTE_UNUSED;
5292 if (*input_line_pointer != '=')
5294 as_bad (_("bad format of OPT NEST=depth"));
5298 ++input_line_pointer;
5299 max_macro_nest = get_absolute_expression ();
5302 /* Handle the OPT P=chip option. */
5306 int arg ATTRIBUTE_UNUSED;
5307 int on ATTRIBUTE_UNUSED;
5309 if (*input_line_pointer != '=')
5311 /* This is just OPT P, which we do not support. */
5315 ++input_line_pointer;
5319 /* Handle the OPT S option. */
5323 int arg ATTRIBUTE_UNUSED;
5329 /* Handle the OPT T option. */
5332 opt_list_symbols (arg, on)
5333 int arg ATTRIBUTE_UNUSED;
5337 listing |= LISTING_SYMBOLS;
5339 listing &=~ LISTING_SYMBOLS;
5342 /* Handle the MRI REG pseudo-op. */
5346 int ignore ATTRIBUTE_UNUSED;
5355 if (line_label == NULL)
5357 as_bad (_("missing label"));
5358 ignore_rest_of_line ();
5363 stop = mri_comment_field (&stopc);
5367 s = input_line_pointer;
5368 while (isalnum ((unsigned char) *input_line_pointer)
5369 #ifdef REGISTER_PREFIX
5370 || *input_line_pointer == REGISTER_PREFIX
5372 || *input_line_pointer == '/'
5373 || *input_line_pointer == '-')
5374 ++input_line_pointer;
5375 c = *input_line_pointer;
5376 *input_line_pointer = '\0';
5378 if (m68k_ip_op (s, &rop) != 0)
5380 if (rop.error == NULL)
5381 as_bad (_("bad register list"));
5383 as_bad (_("bad register list: %s"), rop.error);
5384 *input_line_pointer = c;
5385 ignore_rest_of_line ();
5389 *input_line_pointer = c;
5391 if (rop.mode == REGLST)
5393 else if (rop.mode == DREG)
5394 mask = 1 << (rop.reg - DATA0);
5395 else if (rop.mode == AREG)
5396 mask = 1 << (rop.reg - ADDR0 + 8);
5397 else if (rop.mode == FPREG)
5398 mask = 1 << (rop.reg - FP0 + 16);
5399 else if (rop.mode == CONTROL
5402 else if (rop.mode == CONTROL
5405 else if (rop.mode == CONTROL
5410 as_bad (_("bad register list"));
5411 ignore_rest_of_line ();
5415 S_SET_SEGMENT (line_label, reg_section);
5416 S_SET_VALUE (line_label, ~mask);
5417 symbol_set_frag (line_label, &zero_address_frag);
5420 mri_comment_end (stop, stopc);
5422 demand_empty_rest_of_line ();
5425 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5429 struct save_opts *next;
5431 int symbols_case_sensitive;
5439 /* FIXME: We don't save OPT S. */
5442 /* This variable holds the stack of saved options. */
5444 static struct save_opts *save_stack;
5446 /* The MRI SAVE pseudo-op. */
5450 int ignore ATTRIBUTE_UNUSED;
5452 struct save_opts *s;
5454 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5455 s->abspcadd = m68k_abspcadd;
5456 s->symbols_case_sensitive = symbols_case_sensitive;
5457 s->keep_locals = flag_keep_locals;
5458 s->short_refs = flag_short_refs;
5459 s->architecture = current_architecture;
5460 s->quick = m68k_quick;
5461 s->rel32 = m68k_rel32;
5462 s->listing = listing;
5463 s->no_warnings = flag_no_warnings;
5465 s->next = save_stack;
5468 demand_empty_rest_of_line ();
5471 /* The MRI RESTORE pseudo-op. */
5475 int ignore ATTRIBUTE_UNUSED;
5477 struct save_opts *s;
5479 if (save_stack == NULL)
5481 as_bad (_("restore without save"));
5482 ignore_rest_of_line ();
5487 save_stack = s->next;
5489 m68k_abspcadd = s->abspcadd;
5490 symbols_case_sensitive = s->symbols_case_sensitive;
5491 flag_keep_locals = s->keep_locals;
5492 flag_short_refs = s->short_refs;
5493 current_architecture = s->architecture;
5494 m68k_quick = s->quick;
5495 m68k_rel32 = s->rel32;
5496 listing = s->listing;
5497 flag_no_warnings = s->no_warnings;
5501 demand_empty_rest_of_line ();
5504 /* Types of MRI structured control directives. */
5506 enum mri_control_type
5514 /* This structure is used to stack the MRI structured control
5517 struct mri_control_info
5519 /* The directive within which this one is enclosed. */
5520 struct mri_control_info *outer;
5522 /* The type of directive. */
5523 enum mri_control_type type;
5525 /* Whether an ELSE has been in an IF. */
5528 /* The add or sub statement at the end of a FOR. */
5531 /* The label of the top of a FOR or REPEAT loop. */
5534 /* The label to jump to for the next iteration, or the else
5535 expression of a conditional. */
5538 /* The label to jump to to break out of the loop, or the label past
5539 the end of a conditional. */
5543 /* The stack of MRI structured control directives. */
5545 static struct mri_control_info *mri_control_stack;
5547 /* The current MRI structured control directive index number, used to
5548 generate label names. */
5550 static int mri_control_index;
5552 /* Some function prototypes. */
5554 static void mri_assemble PARAMS ((char *));
5555 static char *mri_control_label PARAMS ((void));
5556 static struct mri_control_info *push_mri_control
5557 PARAMS ((enum mri_control_type));
5558 static void pop_mri_control PARAMS ((void));
5559 static int parse_mri_condition PARAMS ((int *));
5560 static int parse_mri_control_operand
5561 PARAMS ((int *, char **, char **, char **, char **));
5562 static int swap_mri_condition PARAMS ((int));
5563 static int reverse_mri_condition PARAMS ((int));
5564 static void build_mri_control_operand
5565 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5566 const char *, int));
5567 static void parse_mri_control_expression
5568 PARAMS ((char *, int, const char *, const char *, int));
5570 /* Assemble an instruction for an MRI structured control directive. */
5578 /* md_assemble expects the opcode to be in lower case. */
5579 for (s = str; *s != ' ' && *s != '\0'; s++)
5581 if (isupper ((unsigned char) *s))
5582 *s = tolower ((unsigned char) *s);
5588 /* Generate a new MRI label structured control directive label name. */
5591 mri_control_label ()
5595 n = (char *) xmalloc (20);
5596 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5597 ++mri_control_index;
5601 /* Create a new MRI structured control directive. */
5603 static struct mri_control_info *
5604 push_mri_control (type)
5605 enum mri_control_type type;
5607 struct mri_control_info *n;
5609 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5613 if (type == mri_if || type == mri_while)
5616 n->top = mri_control_label ();
5617 n->next = mri_control_label ();
5618 n->bottom = mri_control_label ();
5620 n->outer = mri_control_stack;
5621 mri_control_stack = n;
5626 /* Pop off the stack of MRI structured control directives. */
5631 struct mri_control_info *n;
5633 n = mri_control_stack;
5634 mri_control_stack = n->outer;
5642 /* Recognize a condition code in an MRI structured control expression. */
5645 parse_mri_condition (pcc)
5650 know (*input_line_pointer == '<');
5652 ++input_line_pointer;
5653 c1 = *input_line_pointer++;
5654 c2 = *input_line_pointer++;
5656 if (*input_line_pointer != '>')
5658 as_bad (_("syntax error in structured control directive"));
5662 ++input_line_pointer;
5670 *pcc = (c1 << 8) | c2;
5675 /* Parse a single operand in an MRI structured control expression. */
5678 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5695 if (*input_line_pointer == '<')
5697 /* It's just a condition code. */
5698 return parse_mri_condition (pcc);
5701 /* Look ahead for the condition code. */
5702 for (s = input_line_pointer; *s != '\0'; ++s)
5704 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5709 as_bad (_("missing condition code in structured control directive"));
5713 *leftstart = input_line_pointer;
5715 if (*leftstop > *leftstart
5716 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5719 input_line_pointer = s;
5720 if (! parse_mri_condition (pcc))
5723 /* Look ahead for AND or OR or end of line. */
5724 for (s = input_line_pointer; *s != '\0'; ++s)
5726 if ((strncasecmp (s, "AND", 3) == 0
5727 && (s[3] == '.' || ! is_part_of_name (s[3])))
5728 || (strncasecmp (s, "OR", 2) == 0
5729 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5733 *rightstart = input_line_pointer;
5735 if (*rightstop > *rightstart
5736 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5739 input_line_pointer = s;
5744 #define MCC(b1, b2) (((b1) << 8) | (b2))
5746 /* Swap the sense of a condition. This changes the condition so that
5747 it generates the same result when the operands are swapped. */
5750 swap_mri_condition (cc)
5755 case MCC ('h', 'i'): return MCC ('c', 's');
5756 case MCC ('l', 's'): return MCC ('c', 'c');
5757 case MCC ('c', 'c'): return MCC ('l', 's');
5758 case MCC ('c', 's'): return MCC ('h', 'i');
5759 case MCC ('p', 'l'): return MCC ('m', 'i');
5760 case MCC ('m', 'i'): return MCC ('p', 'l');
5761 case MCC ('g', 'e'): return MCC ('l', 'e');
5762 case MCC ('l', 't'): return MCC ('g', 't');
5763 case MCC ('g', 't'): return MCC ('l', 't');
5764 case MCC ('l', 'e'): return MCC ('g', 'e');
5769 /* Reverse the sense of a condition. */
5772 reverse_mri_condition (cc)
5777 case MCC ('h', 'i'): return MCC ('l', 's');
5778 case MCC ('l', 's'): return MCC ('h', 'i');
5779 case MCC ('c', 'c'): return MCC ('c', 's');
5780 case MCC ('c', 's'): return MCC ('c', 'c');
5781 case MCC ('n', 'e'): return MCC ('e', 'q');
5782 case MCC ('e', 'q'): return MCC ('n', 'e');
5783 case MCC ('v', 'c'): return MCC ('v', 's');
5784 case MCC ('v', 's'): return MCC ('v', 'c');
5785 case MCC ('p', 'l'): return MCC ('m', 'i');
5786 case MCC ('m', 'i'): return MCC ('p', 'l');
5787 case MCC ('g', 'e'): return MCC ('l', 't');
5788 case MCC ('l', 't'): return MCC ('g', 'e');
5789 case MCC ('g', 't'): return MCC ('l', 'e');
5790 case MCC ('l', 'e'): return MCC ('g', 't');
5795 /* Build an MRI structured control expression. This generates test
5796 and branch instructions. It goes to TRUELAB if the condition is
5797 true, and to FALSELAB if the condition is false. Exactly one of
5798 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5799 is the size qualifier for the expression. EXTENT is the size to
5800 use for the branch. */
5803 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5804 rightstop, truelab, falselab, extent)
5811 const char *truelab;
5812 const char *falselab;
5818 if (leftstart != NULL)
5820 struct m68k_op leftop, rightop;
5823 /* Swap the compare operands, if necessary, to produce a legal
5824 m68k compare instruction. Comparing a register operand with
5825 a non-register operand requires the register to be on the
5826 right (cmp, cmpa). Comparing an immediate value with
5827 anything requires the immediate value to be on the left
5832 (void) m68k_ip_op (leftstart, &leftop);
5837 (void) m68k_ip_op (rightstart, &rightop);
5840 if (rightop.mode == IMMED
5841 || ((leftop.mode == DREG || leftop.mode == AREG)
5842 && (rightop.mode != DREG && rightop.mode != AREG)))
5846 cc = swap_mri_condition (cc);
5848 leftstart = rightstart;
5851 leftstop = rightstop;
5856 if (truelab == NULL)
5858 cc = reverse_mri_condition (cc);
5862 if (leftstart != NULL)
5864 buf = (char *) xmalloc (20
5865 + (leftstop - leftstart)
5866 + (rightstop - rightstart));
5874 memcpy (s, leftstart, leftstop - leftstart);
5875 s += leftstop - leftstart;
5877 memcpy (s, rightstart, rightstop - rightstart);
5878 s += rightstop - rightstart;
5884 buf = (char *) xmalloc (20 + strlen (truelab));
5892 strcpy (s, truelab);
5897 /* Parse an MRI structured control expression. This generates test
5898 and branch instructions. STOP is where the expression ends. It
5899 goes to TRUELAB if the condition is true, and to FALSELAB if the
5900 condition is false. Exactly one of TRUELAB and FALSELAB will be
5901 NULL, meaning to fall through. QUAL is the size qualifier for the
5902 expression. EXTENT is the size to use for the branch. */
5905 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5908 const char *truelab;
5909 const char *falselab;
5922 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5923 &rightstart, &rightstop))
5929 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5933 if (falselab != NULL)
5936 flab = mri_control_label ();
5938 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5939 rightstop, (const char *) NULL, flab, extent);
5941 input_line_pointer += 3;
5942 if (*input_line_pointer != '.'
5943 || input_line_pointer[1] == '\0')
5947 qual = input_line_pointer[1];
5948 input_line_pointer += 2;
5951 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5952 &rightstart, &rightstop))
5958 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5959 rightstop, truelab, falselab, extent);
5961 if (falselab == NULL)
5964 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5968 if (truelab != NULL)
5971 tlab = mri_control_label ();
5973 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5974 rightstop, tlab, (const char *) NULL, extent);
5976 input_line_pointer += 2;
5977 if (*input_line_pointer != '.'
5978 || input_line_pointer[1] == '\0')
5982 qual = input_line_pointer[1];
5983 input_line_pointer += 2;
5986 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5987 &rightstart, &rightstop))
5993 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5994 rightstop, truelab, falselab, extent);
5996 if (truelab == NULL)
6001 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6002 rightstop, truelab, falselab, extent);
6006 if (input_line_pointer != stop)
6007 as_bad (_("syntax error in structured control directive"));
6010 /* Handle the MRI IF pseudo-op. This may be a structured control
6011 directive, or it may be a regular assembler conditional, depending
6020 struct mri_control_info *n;
6022 /* A structured control directive must end with THEN with an
6023 optional qualifier. */
6024 s = input_line_pointer;
6025 while (! is_end_of_line[(unsigned char) *s]
6026 && (! flag_mri || *s != '*'))
6029 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6032 if (s - input_line_pointer > 1
6036 if (s - input_line_pointer < 3
6037 || strncasecmp (s - 3, "THEN", 4) != 0)
6041 as_bad (_("missing then"));
6042 ignore_rest_of_line ();
6046 /* It's a conditional. */
6051 /* Since this might be a conditional if, this pseudo-op will be
6052 called even if we are supported to be ignoring input. Double
6053 check now. Clobber *input_line_pointer so that ignore_input
6054 thinks that this is not a special pseudo-op. */
6055 c = *input_line_pointer;
6056 *input_line_pointer = 0;
6057 if (ignore_input ())
6059 *input_line_pointer = c;
6060 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6061 ++input_line_pointer;
6062 demand_empty_rest_of_line ();
6065 *input_line_pointer = c;
6067 n = push_mri_control (mri_if);
6069 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6070 n->next, s[1] == '.' ? s[2] : '\0');
6073 input_line_pointer = s + 3;
6075 input_line_pointer = s + 1;
6079 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6080 ++input_line_pointer;
6083 demand_empty_rest_of_line ();
6086 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6087 structured IF, associate the ELSE with the IF. Otherwise, assume
6088 it is a conditional else. */
6099 && (mri_control_stack == NULL
6100 || mri_control_stack->type != mri_if
6101 || mri_control_stack->else_seen))
6107 c = *input_line_pointer;
6108 *input_line_pointer = 0;
6109 if (ignore_input ())
6111 *input_line_pointer = c;
6112 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6113 ++input_line_pointer;
6114 demand_empty_rest_of_line ();
6117 *input_line_pointer = c;
6119 if (mri_control_stack == NULL
6120 || mri_control_stack->type != mri_if
6121 || mri_control_stack->else_seen)
6123 as_bad (_("else without matching if"));
6124 ignore_rest_of_line ();
6128 mri_control_stack->else_seen = 1;
6130 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6133 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6137 colon (mri_control_stack->next);
6141 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6142 ++input_line_pointer;
6145 demand_empty_rest_of_line ();
6148 /* Handle the MRI ENDI pseudo-op. */
6152 int ignore ATTRIBUTE_UNUSED;
6154 if (mri_control_stack == NULL
6155 || mri_control_stack->type != mri_if)
6157 as_bad (_("endi without matching if"));
6158 ignore_rest_of_line ();
6162 /* ignore_input will not return true for ENDI, so we don't need to
6163 worry about checking it again here. */
6165 if (! mri_control_stack->else_seen)
6166 colon (mri_control_stack->next);
6167 colon (mri_control_stack->bottom);
6173 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6174 ++input_line_pointer;
6177 demand_empty_rest_of_line ();
6180 /* Handle the MRI BREAK pseudo-op. */
6183 s_mri_break (extent)
6186 struct mri_control_info *n;
6190 n = mri_control_stack;
6192 && n->type != mri_for
6193 && n->type != mri_repeat
6194 && n->type != mri_while)
6198 as_bad (_("break outside of structured loop"));
6199 ignore_rest_of_line ();
6203 buf = (char *) xmalloc (20 + strlen (n->bottom));
6206 sprintf (buf, "bra%s %s", ex, n->bottom);
6212 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6213 ++input_line_pointer;
6216 demand_empty_rest_of_line ();
6219 /* Handle the MRI NEXT pseudo-op. */
6225 struct mri_control_info *n;
6229 n = mri_control_stack;
6231 && n->type != mri_for
6232 && n->type != mri_repeat
6233 && n->type != mri_while)
6237 as_bad (_("next outside of structured loop"));
6238 ignore_rest_of_line ();
6242 buf = (char *) xmalloc (20 + strlen (n->next));
6245 sprintf (buf, "bra%s %s", ex, n->next);
6251 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6252 ++input_line_pointer;
6255 demand_empty_rest_of_line ();
6258 /* Handle the MRI FOR pseudo-op. */
6264 const char *varstart, *varstop;
6265 const char *initstart, *initstop;
6266 const char *endstart, *endstop;
6267 const char *bystart, *bystop;
6271 struct mri_control_info *n;
6277 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6281 varstart = input_line_pointer;
6283 /* Look for the '='. */
6284 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6285 && *input_line_pointer != '=')
6286 ++input_line_pointer;
6287 if (*input_line_pointer != '=')
6289 as_bad (_("missing ="));
6290 ignore_rest_of_line ();
6294 varstop = input_line_pointer;
6295 if (varstop > varstart
6296 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6299 ++input_line_pointer;
6301 initstart = input_line_pointer;
6303 /* Look for TO or DOWNTO. */
6306 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6308 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6309 && ! is_part_of_name (input_line_pointer[2]))
6311 initstop = input_line_pointer;
6312 input_line_pointer += 2;
6315 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6316 && ! is_part_of_name (input_line_pointer[6]))
6318 initstop = input_line_pointer;
6320 input_line_pointer += 6;
6323 ++input_line_pointer;
6325 if (initstop == NULL)
6327 as_bad (_("missing to or downto"));
6328 ignore_rest_of_line ();
6331 if (initstop > initstart
6332 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6336 endstart = input_line_pointer;
6338 /* Look for BY or DO. */
6341 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6343 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6344 && ! is_part_of_name (input_line_pointer[2]))
6346 endstop = input_line_pointer;
6348 input_line_pointer += 2;
6351 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6352 && (input_line_pointer[2] == '.'
6353 || ! is_part_of_name (input_line_pointer[2])))
6355 endstop = input_line_pointer;
6356 input_line_pointer += 2;
6359 ++input_line_pointer;
6361 if (endstop == NULL)
6363 as_bad (_("missing do"));
6364 ignore_rest_of_line ();
6367 if (endstop > endstart
6368 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6374 bystop = bystart + 2;
6379 bystart = input_line_pointer;
6383 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6385 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6386 && (input_line_pointer[2] == '.'
6387 || ! is_part_of_name (input_line_pointer[2])))
6389 bystop = input_line_pointer;
6390 input_line_pointer += 2;
6393 ++input_line_pointer;
6397 as_bad (_("missing do"));
6398 ignore_rest_of_line ();
6401 if (bystop > bystart
6402 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6406 if (*input_line_pointer != '.')
6410 extent = input_line_pointer[1];
6411 input_line_pointer += 2;
6414 /* We have fully parsed the FOR operands. Now build the loop. */
6416 n = push_mri_control (mri_for);
6418 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6429 memcpy (s, initstart, initstop - initstart);
6430 s += initstop - initstart;
6432 memcpy (s, varstart, varstop - varstart);
6433 s += varstop - varstart;
6447 memcpy (s, endstart, endstop - endstart);
6448 s += endstop - endstart;
6450 memcpy (s, varstart, varstop - varstart);
6451 s += varstop - varstart;
6459 sprintf (buf, "blt%s %s", ex, n->bottom);
6461 sprintf (buf, "bgt%s %s", ex, n->bottom);
6464 /* Put together the add or sub instruction used by ENDF. */
6474 memcpy (s, bystart, bystop - bystart);
6475 s += bystop - bystart;
6477 memcpy (s, varstart, varstop - varstart);
6478 s += varstop - varstart;
6484 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6485 ++input_line_pointer;
6488 demand_empty_rest_of_line ();
6491 /* Handle the MRI ENDF pseudo-op. */
6495 int ignore ATTRIBUTE_UNUSED;
6497 if (mri_control_stack == NULL
6498 || mri_control_stack->type != mri_for)
6500 as_bad (_("endf without for"));
6501 ignore_rest_of_line ();
6505 colon (mri_control_stack->next);
6507 mri_assemble (mri_control_stack->incr);
6509 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6510 mri_assemble (mri_control_stack->incr);
6512 free (mri_control_stack->incr);
6514 colon (mri_control_stack->bottom);
6520 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6521 ++input_line_pointer;
6524 demand_empty_rest_of_line ();
6527 /* Handle the MRI REPEAT pseudo-op. */
6530 s_mri_repeat (ignore)
6531 int ignore ATTRIBUTE_UNUSED;
6533 struct mri_control_info *n;
6535 n = push_mri_control (mri_repeat);
6539 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6540 ++input_line_pointer;
6542 demand_empty_rest_of_line ();
6545 /* Handle the MRI UNTIL pseudo-op. */
6553 if (mri_control_stack == NULL
6554 || mri_control_stack->type != mri_repeat)
6556 as_bad (_("until without repeat"));
6557 ignore_rest_of_line ();
6561 colon (mri_control_stack->next);
6563 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6566 parse_mri_control_expression (s, qual, (const char *) NULL,
6567 mri_control_stack->top, '\0');
6569 colon (mri_control_stack->bottom);
6571 input_line_pointer = s;
6577 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6578 ++input_line_pointer;
6581 demand_empty_rest_of_line ();
6584 /* Handle the MRI WHILE pseudo-op. */
6592 struct mri_control_info *n;
6594 s = input_line_pointer;
6595 while (! is_end_of_line[(unsigned char) *s]
6596 && (! flag_mri || *s != '*'))
6599 while (*s == ' ' || *s == '\t')
6601 if (s - input_line_pointer > 1
6604 if (s - input_line_pointer < 2
6605 || strncasecmp (s - 1, "DO", 2) != 0)
6607 as_bad (_("missing do"));
6608 ignore_rest_of_line ();
6612 n = push_mri_control (mri_while);
6616 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6617 s[1] == '.' ? s[2] : '\0');
6619 input_line_pointer = s + 1;
6620 if (*input_line_pointer == '.')
6621 input_line_pointer += 2;
6625 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6626 ++input_line_pointer;
6629 demand_empty_rest_of_line ();
6632 /* Handle the MRI ENDW pseudo-op. */
6636 int ignore ATTRIBUTE_UNUSED;
6640 if (mri_control_stack == NULL
6641 || mri_control_stack->type != mri_while)
6643 as_bad (_("endw without while"));
6644 ignore_rest_of_line ();
6648 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6649 sprintf (buf, "bra %s", mri_control_stack->next);
6653 colon (mri_control_stack->bottom);
6659 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6660 ++input_line_pointer;
6663 demand_empty_rest_of_line ();
6668 * Invocation line includes a switch not recognized by the base assembler.
6669 * See if it's a processor-specific option. These are:
6671 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6672 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6673 * Select the architecture. Instructions or features not
6674 * supported by the selected architecture cause fatal
6675 * errors. More than one may be specified. The default is
6676 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6677 * for -m68000, and -m68882 is a synonym for -m68881.
6678 * -[A]m[c]no-68851, -[A]m[c]no-68881
6679 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6680 * so don't use or document it, but that's the way the parsing
6683 * -pic Indicates PIC.
6684 * -k Indicates PIC. (Sun 3 only.)
6685 * --pcrel Never turn PC-relative branches into absolute jumps.
6688 * Permit `|' to be used in expressions.
6693 CONST char *md_shortopts = "lSA:m:kQ:V";
6695 CONST char *md_shortopts = "lSA:m:k";
6698 struct option md_longopts[] = {
6699 #define OPTION_PIC (OPTION_MD_BASE)
6700 {"pic", no_argument, NULL, OPTION_PIC},
6701 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6702 {"register-prefix-optional", no_argument, NULL,
6703 OPTION_REGISTER_PREFIX_OPTIONAL},
6704 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6705 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6706 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6707 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6708 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6709 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6710 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6711 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6712 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6713 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6714 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6715 {"pcrel", no_argument, NULL, OPTION_PCREL},
6716 {NULL, no_argument, NULL, 0}
6718 size_t md_longopts_size = sizeof (md_longopts);
6721 md_parse_option (c, arg)
6727 case 'l': /* -l means keep external to 2 bit offset
6728 rather than 16 bit one */
6729 flag_short_refs = 1;
6732 case 'S': /* -S means that jbsr's always turn into
6734 flag_long_jumps = 1;
6737 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6738 branches into absolute jumps. */
6739 flag_keep_pcrel = 1;
6745 /* intentional fall-through */
6748 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6752 const char *oarg = arg;
6758 if (arg[0] == 'c' && arg[1] == '6')
6761 for (i = 0; i < n_archs; i++)
6762 if (!strcmp (arg, archs[i].name))
6767 as_bad (_("unrecognized option `%s'"), oarg);
6770 arch = archs[i].arch;
6773 else if (arch == m68851)
6782 if (arg[0] == 'c' && arg[1] == '6')
6785 for (i = 0; i < n_archs; i++)
6786 if (!strcmp (arg, archs[i].name))
6788 unsigned long arch = archs[i].arch;
6789 if (cpu_of_arch (arch))
6790 /* It's a cpu spec. */
6792 current_architecture &= ~m68000up;
6793 current_architecture |= arch;
6795 else if (arch == m68881)
6797 current_architecture |= m68881;
6800 else if (arch == m68851)
6802 current_architecture |= m68851;
6812 as_bad (_("unrecognized architecture specification `%s'"), arg);
6821 break; /* -pic, Position Independent Code */
6823 case OPTION_REGISTER_PREFIX_OPTIONAL:
6824 flag_reg_prefix_optional = 1;
6825 reg_prefix_optional_seen = 1;
6828 /* -V: SVR4 argument to print version ID. */
6830 print_version_id ();
6833 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6834 should be emitted or not. FIXME: Not implemented. */
6838 case OPTION_BITWISE_OR:
6843 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6845 for (s = m68k_comment_chars; *s != '\0'; s++)
6849 m68k_comment_chars = n;
6853 case OPTION_BASE_SIZE_DEFAULT_16:
6854 m68k_index_width_default = SIZE_WORD;
6857 case OPTION_BASE_SIZE_DEFAULT_32:
6858 m68k_index_width_default = SIZE_LONG;
6861 case OPTION_DISP_SIZE_DEFAULT_16:
6863 m68k_rel32_from_cmdline = 1;
6866 case OPTION_DISP_SIZE_DEFAULT_32:
6868 m68k_rel32_from_cmdline = 1;
6879 md_show_usage (stream)
6882 fprintf (stream, _("\
6884 -l use 1 word for refs to undefined symbols [default 2]\n\
6885 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6886 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6887 | -mcpu32 | -m5200\n\
6888 specify variant of 680X0 architecture [default 68020]\n\
6889 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6890 target has/lacks floating-point coprocessor\n\
6891 [default yes for 68020, 68030, and cpu32]\n"));
6892 fprintf (stream, _("\
6893 -m68851 | -mno-68851\n\
6894 target has/lacks memory-management unit coprocessor\n\
6895 [default yes for 68020 and up]\n\
6896 -pic, -k generate position independent code\n\
6897 -S turn jbsr into jsr\n\
6898 --pcrel never turn PC-relative branches into absolute jumps\n\
6899 --register-prefix-optional\n\
6900 recognize register names without prefix character\n\
6901 --bitwise-or do not treat `|' as a comment character\n"));
6902 fprintf (stream, _("\
6903 --base-size-default-16 base reg without size is 16 bits\n\
6904 --base-size-default-32 base reg without size is 32 bits (default)\n\
6905 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6906 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6911 /* TEST2: Test md_assemble() */
6912 /* Warning, this routine probably doesn't work anymore */
6916 struct m68k_it the_ins;
6924 if (!gets (buf) || !*buf)
6926 if (buf[0] == '|' || buf[1] == '.')
6928 for (cp = buf; *cp; cp++)
6933 memset (&the_ins, '\0', sizeof (the_ins));
6934 m68k_ip (&the_ins, buf);
6937 printf (_("Error %s in %s\n"), the_ins.error, buf);
6941 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6942 for (n = 0; n < the_ins.numo; n++)
6943 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6945 print_the_insn (&the_ins.opcode[0], stdout);
6946 (void) putchar ('\n');
6948 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6950 if (the_ins.operands[n].error)
6952 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6955 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6956 if (the_ins.operands[n].b_const)
6957 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6958 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6959 if (the_ins.operands[n].b_iadd)
6960 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6961 (void) putchar ('\n');
6973 while (*str && *str != ' ')
6975 if (str[-1] == ':' || str[1] == '=')
6982 /* Possible states for relaxation:
6984 0 0 branch offset byte (bra, etc)
6988 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6992 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6999 /* We have no need to default values of symbols. */
7002 md_undefined_symbol (name)
7003 char *name ATTRIBUTE_UNUSED;
7008 /* Round up a section size to the appropriate boundary. */
7010 md_section_align (segment, size)
7011 segT segment ATTRIBUTE_UNUSED;
7015 #ifdef BFD_ASSEMBLER
7016 /* For a.out, force the section size to be aligned. If we don't do
7017 this, BFD will align it for us, but it will not write out the
7018 final bytes of the section. This may be a bug in BFD, but it is
7019 easier to fix it here since that is how the other a.out targets
7023 align = bfd_get_section_alignment (stdoutput, segment);
7024 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7031 /* Exactly what point is a PC-relative offset relative TO?
7032 On the 68k, it is relative to the address of the first extension
7033 word. The difference between the addresses of the offset and the
7034 first extension word is stored in fx_pcrel_adjust. */
7036 md_pcrel_from (fixP)
7041 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7042 sign extend the value here. */
7043 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7046 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7049 #ifndef BFD_ASSEMBLER
7053 tc_coff_symbol_emit_hook (ignore)
7054 symbolS *ignore ATTRIBUTE_UNUSED;
7059 tc_coff_sizemachdep (frag)
7062 switch (frag->fr_subtype & 0x3)
7079 void m68k_elf_final_processing()
7081 /* Set file-specific flags if this is a cpu32 processor */
7082 if (cpu_of_arch (current_architecture) & cpu32)
7083 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;