1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
36 /* This string holds the chars that always start a comment. If the
37 pre-processor is disabled, these aren't very useful. The macro
38 tc_comment_chars points to this. We use this, rather than the
39 usual comment_chars, so that the --bitwise-or option will work. */
40 #if defined (TE_SVR4) || defined (TE_DELTA)
41 const char *m68k_comment_chars = "|#";
43 const char *m68k_comment_chars = "|";
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars[] = "#*";
55 const char line_separator_chars[] = ";";
57 /* Chars that can be used to separate mant from exp in floating point nums. */
58 const char EXP_CHARS[] = "eE";
60 /* Chars that mean this number is a floating point constant, as
61 in "0f12.456" or "0d1.2345e12". */
63 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
65 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
66 changed in read.c . Ideally it shouldn't have to know about it at all,
67 but nothing is ideal around here. */
69 const int md_reloc_size = 8; /* Size of relocation record. */
71 /* Are we trying to generate PIC code? If so, absolute references
72 ought to be made into linkage table references or pc-relative
73 references. Not implemented. For ELF there are other means
74 to denote pic relocations. */
77 static int flag_short_refs; /* -l option. */
78 static int flag_long_jumps; /* -S option. */
79 static int flag_keep_pcrel; /* --pcrel option. */
81 #ifdef REGISTER_PREFIX_OPTIONAL
82 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
84 int flag_reg_prefix_optional;
87 /* Whether --register-prefix-optional was used on the command line. */
88 static int reg_prefix_optional_seen;
90 /* The floating point coprocessor to use by default. */
91 static enum m68k_register m68k_float_copnum = COP1;
93 /* If this is non-zero, then references to number(%pc) will be taken
94 to refer to number, rather than to %pc + number. */
95 static int m68k_abspcadd;
97 /* If this is non-zero, then the quick forms of the move, add, and sub
98 instructions are used when possible. */
99 static int m68k_quick = 1;
101 /* If this is non-zero, then if the size is not specified for a base
102 or outer displacement, the assembler assumes that the size should
104 static int m68k_rel32 = 1;
106 /* This is non-zero if m68k_rel32 was set from the command line. */
107 static int m68k_rel32_from_cmdline;
109 /* The default width to use for an index register when using a base
111 static enum m68k_size m68k_index_width_default = SIZE_LONG;
113 /* We want to warn if any text labels are misaligned. In order to get
114 the right line number, we need to record the line number for each
118 struct label_line *next;
125 /* The list of labels. */
127 static struct label_line *labels;
129 /* The current label. */
131 static struct label_line *current_label;
133 /* Its an arbitrary name: This means I don't approve of it.
135 static struct obstack robyn;
139 const char *m_operands;
140 unsigned long m_opcode;
144 struct m68k_incant *m_next;
147 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148 #define gettwo(x) (((x)->m_opcode)&0xffff)
150 static const enum m68k_register m68000_control_regs[] = { 0 };
151 static const enum m68k_register m68010_control_regs[] = {
155 static const enum m68k_register m68020_control_regs[] = {
156 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
159 static const enum m68k_register m68040_control_regs[] = {
160 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
161 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
164 static const enum m68k_register m68060_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
166 USP, VBR, URP, SRP, PCR,
169 static const enum m68k_register mcf_control_regs[] = {
170 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
171 RAMBAR0, RAMBAR1, MBAR,
174 static const enum m68k_register mcf528x_control_regs[] = {
175 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
178 static const enum m68k_register mcfv4e_control_regs[] = {
179 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
180 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
181 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
182 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
185 #define cpu32_control_regs m68010_control_regs
187 static const enum m68k_register *control_regs;
189 /* Internal form of a 68020 instruction. */
193 const char *args; /* List of opcode info. */
196 int numo; /* Number of shorts in opcode. */
199 struct m68k_op operands[6];
201 int nexp; /* Number of exprs in use. */
202 struct m68k_exp exprs[4];
204 int nfrag; /* Number of frags we have to produce. */
207 int fragoff; /* Where in the current opcode the frag ends. */
214 int nrel; /* Num of reloc strucs in use. */
221 /* In a pc relative address the difference between the address
222 of the offset and the address that the offset is relative
223 to. This depends on the addressing mode. Basically this
224 is the value to put in the offset field to address the
225 first byte of the offset, without regarding the special
226 significance of some values (in the branch instruction, for
230 /* Whether this expression needs special pic relocation, and if
232 enum pic_relocation pic_reloc;
235 reloc[5]; /* Five is enough??? */
238 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
239 #define float_of_arch(x) ((x) & mfloat)
240 #define mmu_of_arch(x) ((x) & mmmu)
241 #define arch_coldfire_p(x) ((x) & mcfisa_a)
242 #define arch_coldfire_fpu(x) ((x) & cfloat)
244 /* Macros for determining if cpu supports a specific addressing mode. */
245 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
247 static struct m68k_it the_ins; /* The instruction being assembled. */
249 #define op(ex) ((ex)->exp.X_op)
250 #define adds(ex) ((ex)->exp.X_add_symbol)
251 #define subs(ex) ((ex)->exp.X_op_symbol)
252 #define offs(ex) ((ex)->exp.X_add_number)
254 /* Macros for adding things to the m68k_it struct. */
255 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
257 /* Static functions. */
258 static void insop PARAMS ((int, const struct m68k_incant *));
259 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
260 static void add_frag PARAMS ((symbolS *, offsetT, int));
262 /* Like addword, but goes BEFORE general operands. */
267 const struct m68k_incant *opcode;
270 for (z = the_ins.numo; z > opcode->m_codenum; --z)
271 the_ins.opcode[z] = the_ins.opcode[z - 1];
272 for (z = 0; z < the_ins.nrel; z++)
273 the_ins.reloc[z].n += 2;
274 for (z = 0; z < the_ins.nfrag; z++)
275 the_ins.fragb[z].fragoff++;
276 the_ins.opcode[opcode->m_codenum] = w;
280 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
283 add_fix (width, exp, pc_rel, pc_fix)
285 struct m68k_exp *exp;
289 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
293 : (the_ins.numo*2)));
294 the_ins.reloc[the_ins.nrel].exp = exp->exp;
295 the_ins.reloc[the_ins.nrel].wid = width;
296 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
298 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
300 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
303 /* Cause an extra frag to be generated here, inserting up to 10 bytes
304 (that value is chosen in the frag_var call in md_assemble). TYPE
305 is the subtype of the frag to be generated; its primary type is
306 rs_machine_dependent.
308 The TYPE parameter is also used by md_convert_frag_1 and
309 md_estimate_size_before_relax. The appropriate type of fixup will
310 be emitted by md_convert_frag_1.
312 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
314 add_frag (add, off, type)
319 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
320 the_ins.fragb[the_ins.nfrag].fadd = add;
321 the_ins.fragb[the_ins.nfrag].foff = off;
322 the_ins.fragb[the_ins.nfrag++].fragty = type;
326 (op (ex) != O_constant && op (ex) != O_big)
328 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
329 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
330 static void m68k_ip PARAMS ((char *));
331 static void insert_reg PARAMS ((const char *, int));
332 static void select_control_regs PARAMS ((void));
333 static void init_regtable PARAMS ((void));
334 static int reverse_16_bits PARAMS ((int in));
335 static int reverse_8_bits PARAMS ((int in));
336 static void install_gen_operand PARAMS ((int mode, int val));
337 static void install_operand PARAMS ((int mode, int val));
338 static void s_bss PARAMS ((int));
339 static void s_data1 PARAMS ((int));
340 static void s_data2 PARAMS ((int));
341 static void s_even PARAMS ((int));
342 static void s_proc PARAMS ((int));
343 static void mri_chip PARAMS ((void));
344 static void s_chip PARAMS ((int));
345 static void s_fopt PARAMS ((int));
346 static void s_opt PARAMS ((int));
347 static void s_reg PARAMS ((int));
348 static void s_restore PARAMS ((int));
349 static void s_save PARAMS ((int));
350 static void s_mri_if PARAMS ((int));
351 static void s_mri_else PARAMS ((int));
352 static void s_mri_endi PARAMS ((int));
353 static void s_mri_break PARAMS ((int));
354 static void s_mri_next PARAMS ((int));
355 static void s_mri_for PARAMS ((int));
356 static void s_mri_endf PARAMS ((int));
357 static void s_mri_repeat PARAMS ((int));
358 static void s_mri_until PARAMS ((int));
359 static void s_mri_while PARAMS ((int));
360 static void s_mri_endw PARAMS ((int));
361 static void md_convert_frag_1 PARAMS ((fragS *));
363 static int current_architecture;
364 static int current_chip;
374 static const struct m68k_cpu archs[] =
376 { m68000, m68000, "68000", 0 },
377 { m68010, m68010, "68010", 0 },
378 { m68020, m68020, "68020", 0 },
379 { m68030, m68030, "68030", 0 },
380 { m68040, m68040, "68040", 0 },
381 { m68060, m68060, "68060", 0 },
382 { cpu32, cpu32, "cpu32", 0 },
383 { m68881, m68881, "68881", 0 },
384 { m68851, m68851, "68851", 0 },
385 { mcfisa_a, mcf5200, "5200", 0 },
386 { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 },
387 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 },
388 { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 },
389 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 },
390 { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 },
391 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 },
392 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 },
393 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 },
394 /* Aliases (effectively, so far as gas is concerned) for the above
396 { m68020, m68020, "68k", 1 },
397 { m68000, m68000, "68008", 1 },
398 { m68000, m68000, "68302", 1 },
399 { m68000, m68000, "68306", 1 },
400 { m68000, m68000, "68307", 1 },
401 { m68000, m68000, "68322", 1 },
402 { m68000, m68000, "68356", 1 },
403 { m68000, m68000, "68ec000", 1 },
404 { m68000, m68000, "68hc000", 1 },
405 { m68000, m68000, "68hc001", 1 },
406 { m68020, m68020, "68ec020", 1 },
407 { m68030, m68030, "68ec030", 1 },
408 { m68040, m68040, "68ec040", 1 },
409 { m68060, m68060, "68ec060", 1 },
410 { cpu32, cpu32, "68330", 1 },
411 { cpu32, cpu32, "68331", 1 },
412 { cpu32, cpu32, "68332", 1 },
413 { cpu32, cpu32, "68333", 1 },
414 { cpu32, cpu32, "68334", 1 },
415 { cpu32, cpu32, "68336", 1 },
416 { cpu32, cpu32, "68340", 1 },
417 { cpu32, cpu32, "68341", 1 },
418 { cpu32, cpu32, "68349", 1 },
419 { cpu32, cpu32, "68360", 1 },
420 { m68881, m68881, "68882", 1 },
421 { mcfisa_a, mcf5200, "5202", 1 },
422 { mcfisa_a, mcf5200, "5204", 1 },
423 { mcfisa_a, mcf5200, "5206", 1 },
424 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 },
425 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 },
426 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 },
427 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 },
428 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 },
429 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 },
430 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 },
431 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 },
432 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 },
433 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 },
434 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 },
435 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 },
436 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 },
437 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 },
438 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 },
439 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 },
440 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 },
441 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 },
442 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 },
445 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
447 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
448 architecture and we have a lot of relaxation modes. */
450 /* Macros used in the relaxation code. */
451 #define TAB(x,y) (((x) << 2) + (y))
452 #define TABTYPE(x) ((x) >> 2)
454 /* Relaxation states. */
460 /* Here are all the relaxation modes we support. First we can relax ordinary
461 branches. On 68020 and higher and on CPU32 all branch instructions take
462 three forms, so on these CPUs all branches always remain as such. When we
463 have to expand to the LONG form on a 68000, though, we substitute an
464 absolute jump instead. This is a direct replacement for unconditional
465 branches and a branch over a jump for conditional branches. However, if the
466 user requires PIC and disables this with --pcrel, we can only relax between
467 BYTE and SHORT forms, punting if that isn't enough. This gives us four
468 different relaxation modes for branches: */
470 #define BRANCHBWL 0 /* Branch byte, word, or long. */
471 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
472 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
473 #define BRANCHBW 3 /* Branch byte or word. */
475 /* We also relax coprocessor branches and DBcc's. All CPUs that support
476 coprocessor branches support them in word and long forms, so we have only
477 one relaxation mode for them. DBcc's are word only on all CPUs. We can
478 relax them to the LONG form with a branch-around sequence. This sequence
479 can use a long branch (if available) or an absolute jump (if acceptable).
480 This gives us two relaxation modes. If long branches are not available and
481 absolute jumps are not acceptable, we don't relax DBcc's. */
483 #define FBRANCH 4 /* Coprocessor branch. */
484 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
485 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
487 /* That's all for instruction relaxation. However, we also relax PC-relative
488 operands. Specifically, we have three operand relaxation modes. On the
489 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
490 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
491 two. Also PC+displacement+index operands in their simple form (with a non-
492 suppressed index without memory indirection) are supported on all CPUs, but
493 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
494 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
495 form of the PC+displacement+index operand. Finally, some absolute operands
496 can be relaxed down to 16-bit PC-relative. */
498 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
499 #define PCINDEX 8 /* PC + displacement + index. */
500 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
502 /* Note that calls to frag_var need to specify the maximum expansion
503 needed; this is currently 10 bytes for DBCC. */
506 How far Forward this mode will reach:
507 How far Backward this mode will reach:
508 How many bytes this mode will add to the size of the frag
509 Which mode to go to if the offset won't fit in this one
511 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
512 relax_typeS md_relax_table[] =
514 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
515 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
519 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
520 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
524 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
525 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
529 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
534 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
535 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
539 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
540 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
544 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
545 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
549 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
550 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
554 { 125, -130, 0, TAB (PCINDEX, SHORT) },
555 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
559 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
560 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
565 /* These are the machine dependent pseudo-ops. These are included so
566 the assembler can work on the output from the SUN C compiler, which
569 /* This table describes all the machine specific pseudo-ops the assembler
570 has to support. The fields are:
571 pseudo-op name without dot
572 function to call to execute this pseudo-op
573 Integer arg to pass to the function. */
574 const pseudo_typeS md_pseudo_table[] =
576 {"data1", s_data1, 0},
577 {"data2", s_data2, 0},
580 {"skip", s_space, 0},
582 #if defined (TE_SUN3) || defined (OBJ_ELF)
583 {"align", s_align_bytes, 0},
586 {"swbeg", s_ignore, 0},
588 {"extend", float_cons, 'x'},
589 {"ldouble", float_cons, 'x'},
591 /* The following pseudo-ops are supported for MRI compatibility. */
593 {"comline", s_space, 1},
595 {"mask2", s_ignore, 0},
598 {"restore", s_restore, 0},
602 {"if.b", s_mri_if, 'b'},
603 {"if.w", s_mri_if, 'w'},
604 {"if.l", s_mri_if, 'l'},
605 {"else", s_mri_else, 0},
606 {"else.s", s_mri_else, 's'},
607 {"else.l", s_mri_else, 'l'},
608 {"endi", s_mri_endi, 0},
609 {"break", s_mri_break, 0},
610 {"break.s", s_mri_break, 's'},
611 {"break.l", s_mri_break, 'l'},
612 {"next", s_mri_next, 0},
613 {"next.s", s_mri_next, 's'},
614 {"next.l", s_mri_next, 'l'},
615 {"for", s_mri_for, 0},
616 {"for.b", s_mri_for, 'b'},
617 {"for.w", s_mri_for, 'w'},
618 {"for.l", s_mri_for, 'l'},
619 {"endf", s_mri_endf, 0},
620 {"repeat", s_mri_repeat, 0},
621 {"until", s_mri_until, 0},
622 {"until.b", s_mri_until, 'b'},
623 {"until.w", s_mri_until, 'w'},
624 {"until.l", s_mri_until, 'l'},
625 {"while", s_mri_while, 0},
626 {"while.b", s_mri_while, 'b'},
627 {"while.w", s_mri_while, 'w'},
628 {"while.l", s_mri_while, 'l'},
629 {"endw", s_mri_endw, 0},
634 /* The mote pseudo ops are put into the opcode table, since they
635 don't start with a . they look like opcodes to gas.
639 extern void obj_coff_section PARAMS ((int));
642 const pseudo_typeS mote_pseudo_table[] =
655 {"xdef", s_globl, 0},
657 {"align", s_align_bytes, 0},
659 {"align", s_align_ptwo, 0},
662 {"sect", obj_coff_section, 0},
663 {"section", obj_coff_section, 0},
668 #define issbyte(x) ((x)>=-128 && (x)<=127)
669 #define isubyte(x) ((x)>=0 && (x)<=255)
670 #define issword(x) ((x)>=-32768 && (x)<=32767)
671 #define isuword(x) ((x)>=0 && (x)<=65535)
673 #define isbyte(x) ((x)>= -255 && (x)<=255)
674 #define isword(x) ((x)>=-65536 && (x)<=65535)
675 #define islong(x) (1)
677 extern char *input_line_pointer;
679 static char notend_table[256];
680 static char alt_notend_table[256];
682 (! (notend_table[(unsigned char) *s] \
684 && alt_notend_table[(unsigned char) s[1]])))
686 /* Return a human readable string holding the list of chips that are
687 valid for a particular architecture, suppressing aliases (unless
688 there is only one of them). */
691 find_cf_chip (int architecture)
693 static char buf[1024];
694 int i, j, n_chips, n_alias;
698 cp = buf + strlen (buf);
700 for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i)
701 if (archs[i].arch & architecture)
709 as_fatal (_("no matching ColdFire architectures found"));
714 for (i = 0, j = 0; i < n_archs && j < n_chips; ++i)
715 if (archs[i].arch & architecture)
719 if (((j == n_chips - 1) && !(n_alias > 1))|| ! n_alias)
723 strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
728 strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
734 strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
738 strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf)));
745 strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
749 strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
754 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
756 #ifdef NO_PCREL_RELOCS
759 make_pcrel_absolute (fixP, add_number)
763 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
765 /* Rewrite the PC relative instructions to absolute address ones.
766 these are rumored to be faster, and the apollo linker refuses
767 to deal with the PC relative relocations. */
768 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
771 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
775 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
778 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
783 as_fatal (_("Unknown PC relative instruction"));
788 #endif /* NO_PCREL_RELOCS */
791 tc_coff_fix2rtype (fixP)
794 if (fixP->fx_tcbit && fixP->fx_size == 4)
795 return R_RELLONG_NEG;
796 #ifdef NO_PCREL_RELOCS
797 know (fixP->fx_pcrel == 0);
798 return (fixP->fx_size == 1 ? R_RELBYTE
799 : fixP->fx_size == 2 ? R_DIR16
802 return (fixP->fx_pcrel ?
803 (fixP->fx_size == 1 ? R_PCRBYTE :
804 fixP->fx_size == 2 ? R_PCRWORD :
806 (fixP->fx_size == 1 ? R_RELBYTE :
807 fixP->fx_size == 2 ? R_RELWORD :
816 /* Return zero if the reference to SYMBOL from within the same segment may
819 /* On an ELF system, we can't relax an externally visible symbol,
820 because it may be overridden by a shared library. However, if
821 TARGET_OS is "elf", then we presume that we are assembling for an
822 embedded system, in which case we don't have to worry about shared
823 libraries, and we can relax any external sym. */
825 #define relaxable_symbol(symbol) \
826 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
827 || S_IS_WEAK (symbol)))
829 /* Compute the relocation code for a fixup of SIZE bytes, using pc
830 relative relocation if PCREL is non-zero. PIC says whether a special
831 pic relocation was requested. */
833 static bfd_reloc_code_real_type get_reloc_code
834 PARAMS ((int, int, enum pic_relocation));
836 static bfd_reloc_code_real_type
837 get_reloc_code (size, pcrel, pic)
840 enum pic_relocation pic;
848 return BFD_RELOC_8_GOT_PCREL;
850 return BFD_RELOC_16_GOT_PCREL;
852 return BFD_RELOC_32_GOT_PCREL;
860 return BFD_RELOC_8_GOTOFF;
862 return BFD_RELOC_16_GOTOFF;
864 return BFD_RELOC_32_GOTOFF;
872 return BFD_RELOC_8_PLT_PCREL;
874 return BFD_RELOC_16_PLT_PCREL;
876 return BFD_RELOC_32_PLT_PCREL;
884 return BFD_RELOC_8_PLTOFF;
886 return BFD_RELOC_16_PLTOFF;
888 return BFD_RELOC_32_PLTOFF;
898 return BFD_RELOC_8_PCREL;
900 return BFD_RELOC_16_PCREL;
902 return BFD_RELOC_32_PCREL;
922 as_bad (_("Can not do %d byte pc-relative relocation"), size);
924 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
929 as_bad (_("Can not do %d byte relocation"), size);
931 as_bad (_("Can not do %d byte pic relocation"), size);
934 return BFD_RELOC_NONE;
937 /* Here we decide which fixups can be adjusted to make them relative
938 to the beginning of the section instead of the symbol. Basically
939 we need to make sure that the dynamic relocations are done
940 correctly, so in some cases we force the original symbol to be
943 tc_m68k_fix_adjustable (fixP)
946 /* Adjust_reloc_syms doesn't know about the GOT. */
947 switch (fixP->fx_r_type)
949 case BFD_RELOC_8_GOT_PCREL:
950 case BFD_RELOC_16_GOT_PCREL:
951 case BFD_RELOC_32_GOT_PCREL:
952 case BFD_RELOC_8_GOTOFF:
953 case BFD_RELOC_16_GOTOFF:
954 case BFD_RELOC_32_GOTOFF:
955 case BFD_RELOC_8_PLT_PCREL:
956 case BFD_RELOC_16_PLT_PCREL:
957 case BFD_RELOC_32_PLT_PCREL:
958 case BFD_RELOC_8_PLTOFF:
959 case BFD_RELOC_16_PLTOFF:
960 case BFD_RELOC_32_PLTOFF:
963 case BFD_RELOC_VTABLE_INHERIT:
964 case BFD_RELOC_VTABLE_ENTRY:
974 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
976 #define relaxable_symbol(symbol) 1
983 tc_gen_reloc (section, fixp)
984 asection *section ATTRIBUTE_UNUSED;
988 bfd_reloc_code_real_type code;
990 /* If the tcbit is set, then this was a fixup of a negative value
991 that was never resolved. We do not have a reloc to handle this,
992 so just return. We assume that other code will have detected this
993 situation and produced a helpful error message, so we just tell the
994 user that the reloc cannot be produced. */
998 as_bad_where (fixp->fx_file, fixp->fx_line,
999 _("Unable to produce reloc against symbol '%s'"),
1000 S_GET_NAME (fixp->fx_addsy));
1004 if (fixp->fx_r_type != BFD_RELOC_NONE)
1006 code = fixp->fx_r_type;
1008 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1009 that fixup_segment converted a non-PC relative reloc into a
1010 PC relative reloc. In such a case, we need to convert the
1017 code = BFD_RELOC_8_PCREL;
1020 code = BFD_RELOC_16_PCREL;
1023 code = BFD_RELOC_32_PCREL;
1025 case BFD_RELOC_8_PCREL:
1026 case BFD_RELOC_16_PCREL:
1027 case BFD_RELOC_32_PCREL:
1028 case BFD_RELOC_8_GOT_PCREL:
1029 case BFD_RELOC_16_GOT_PCREL:
1030 case BFD_RELOC_32_GOT_PCREL:
1031 case BFD_RELOC_8_GOTOFF:
1032 case BFD_RELOC_16_GOTOFF:
1033 case BFD_RELOC_32_GOTOFF:
1034 case BFD_RELOC_8_PLT_PCREL:
1035 case BFD_RELOC_16_PLT_PCREL:
1036 case BFD_RELOC_32_PLT_PCREL:
1037 case BFD_RELOC_8_PLTOFF:
1038 case BFD_RELOC_16_PLTOFF:
1039 case BFD_RELOC_32_PLTOFF:
1042 as_bad_where (fixp->fx_file, fixp->fx_line,
1043 _("Cannot make %s relocation PC relative"),
1044 bfd_get_reloc_code_name (code));
1050 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1051 switch (F (fixp->fx_size, fixp->fx_pcrel))
1053 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1054 MAP (1, 0, BFD_RELOC_8);
1055 MAP (2, 0, BFD_RELOC_16);
1056 MAP (4, 0, BFD_RELOC_32);
1057 MAP (1, 1, BFD_RELOC_8_PCREL);
1058 MAP (2, 1, BFD_RELOC_16_PCREL);
1059 MAP (4, 1, BFD_RELOC_32_PCREL);
1067 reloc = (arelent *) xmalloc (sizeof (arelent));
1068 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1069 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1070 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1073 reloc->addend = fixp->fx_addnumber;
1077 if (!fixp->fx_pcrel)
1078 reloc->addend = fixp->fx_addnumber;
1080 reloc->addend = (section->vma
1081 /* Explicit sign extension in case char is
1083 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1084 + fixp->fx_addnumber
1085 + md_pcrel_from (fixp));
1088 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1089 assert (reloc->howto != 0);
1094 #endif /* BFD_ASSEMBLER */
1096 /* Handle of the OPCODE hash table. NULL means any use before
1097 m68k_ip_begin() will crash. */
1098 static struct hash_control *op_hash;
1100 /* Assemble an m68k instruction. */
1107 register struct m68k_op *opP;
1108 register const struct m68k_incant *opcode;
1109 register const char *s;
1110 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1111 char *pdot, *pdotmove;
1112 enum m68k_size siz1, siz2;
1116 LITTLENUM_TYPE words[6];
1117 LITTLENUM_TYPE *wordp;
1118 unsigned long ok_arch = 0;
1120 if (*instring == ' ')
1121 instring++; /* Skip leading whitespace. */
1123 /* Scan up to end of operation-code, which MUST end in end-of-string
1124 or exactly 1 space. */
1126 for (p = instring; *p != '\0'; p++)
1136 the_ins.error = _("No operator");
1140 /* p now points to the end of the opcode name, probably whitespace.
1141 Make sure the name is null terminated by clobbering the
1142 whitespace, look it up in the hash table, then fix it back.
1143 Remove a dot, first, since the opcode tables have none. */
1146 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1147 *pdotmove = pdotmove[1];
1153 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1158 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1159 *pdotmove = pdotmove[-1];
1166 the_ins.error = _("Unknown operator");
1170 /* Found a legitimate opcode, start matching operands. */
1174 if (opcode->m_operands == 0)
1176 char *old = input_line_pointer;
1178 input_line_pointer = p;
1179 /* Ahh - it's a motorola style psuedo op. */
1180 mote_pseudo_table[opcode->m_opnum].poc_handler
1181 (mote_pseudo_table[opcode->m_opnum].poc_val);
1182 input_line_pointer = old;
1188 if (flag_mri && opcode->m_opnum == 0)
1190 /* In MRI mode, random garbage is allowed after an instruction
1191 which accepts no operands. */
1192 the_ins.args = opcode->m_operands;
1193 the_ins.numargs = opcode->m_opnum;
1194 the_ins.numo = opcode->m_codenum;
1195 the_ins.opcode[0] = getone (opcode);
1196 the_ins.opcode[1] = gettwo (opcode);
1200 for (opP = &the_ins.operands[0]; *p; opP++)
1202 p = crack_operand (p, opP);
1206 the_ins.error = opP->error;
1211 opsfound = opP - &the_ins.operands[0];
1213 /* This ugly hack is to support the floating pt opcodes in their
1214 standard form. Essentially, we fake a first enty of type COP#1 */
1215 if (opcode->m_operands[0] == 'I')
1219 for (n = opsfound; n > 0; --n)
1220 the_ins.operands[n] = the_ins.operands[n - 1];
1222 memset ((char *) (&the_ins.operands[0]), '\0',
1223 sizeof (the_ins.operands[0]));
1224 the_ins.operands[0].mode = CONTROL;
1225 the_ins.operands[0].reg = m68k_float_copnum;
1229 /* We've got the operands. Find an opcode that'll accept them. */
1232 /* If we didn't get the right number of ops, or we have no
1233 common model with this pattern then reject this pattern. */
1235 ok_arch |= opcode->m_arch;
1236 if (opsfound != opcode->m_opnum
1237 || ((opcode->m_arch & current_architecture) == 0))
1241 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1245 /* Warning: this switch is huge! */
1246 /* I've tried to organize the cases into this order:
1247 non-alpha first, then alpha by letter. Lower-case
1248 goes directly before uppercase counterpart. */
1249 /* Code with multiple case ...: gets sorted by the lowest
1250 case ... it belongs to. I hope this makes sense. */
1356 if (opP->reg == PC || opP->reg == ZPC)
1373 if (opP->reg == PC || opP->reg == ZPC)
1392 if (opP->reg == PC || opP->reg == ZPC)
1402 if (opP->mode != IMMED)
1404 else if (s[1] == 'b'
1405 && ! isvar (&opP->disp)
1406 && (opP->disp.exp.X_op != O_constant
1407 || ! isbyte (opP->disp.exp.X_add_number)))
1409 else if (s[1] == 'B'
1410 && ! isvar (&opP->disp)
1411 && (opP->disp.exp.X_op != O_constant
1412 || ! issbyte (opP->disp.exp.X_add_number)))
1414 else if (s[1] == 'w'
1415 && ! isvar (&opP->disp)
1416 && (opP->disp.exp.X_op != O_constant
1417 || ! isword (opP->disp.exp.X_add_number)))
1419 else if (s[1] == 'W'
1420 && ! isvar (&opP->disp)
1421 && (opP->disp.exp.X_op != O_constant
1422 || ! issword (opP->disp.exp.X_add_number)))
1428 if (opP->mode != IMMED)
1433 if (opP->mode == AREG
1434 || opP->mode == CONTROL
1435 || opP->mode == FPREG
1436 || opP->mode == IMMED
1437 || opP->mode == REGLST
1438 || (opP->mode != ABSL
1440 || opP->reg == ZPC)))
1445 if (opP->mode == CONTROL
1446 || opP->mode == FPREG
1447 || opP->mode == REGLST
1448 || opP->mode == IMMED
1449 || (opP->mode != ABSL
1451 || opP->reg == ZPC)))
1479 if (opP->mode == CONTROL
1480 || opP->mode == FPREG
1481 || opP->mode == REGLST)
1486 if (opP->mode != AINC)
1491 if (opP->mode != ADEC)
1541 if (opP->reg == PC || opP->reg == ZPC)
1562 case '~': /* For now! (JF FOO is this right?) */
1584 if (opP->mode != CONTROL
1585 || (opP->reg != TT0 && opP->reg != TT1))
1590 if (opP->mode != AREG)
1595 if (opP->mode != AINDR)
1600 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1601 && (opP->mode != DISP
1603 || opP->reg > ADDR7))
1608 if (opP->mode != ABSL
1610 && strncmp (instring, "jbsr", 4) == 0))
1633 if (opP->mode != CONTROL || opP->reg != CCR)
1638 if (opP->mode != DISP
1640 || opP->reg > ADDR7)
1645 if (opP->mode != DREG)
1650 if (opP->reg != ACC)
1655 if (opP->reg != ACC && opP->reg != ACC1
1656 && opP->reg != ACC2 && opP->reg != ACC3)
1661 if (opP->mode != FPREG)
1666 if (opP->reg != MACSR)
1671 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1676 if (opP->reg != MASK)
1681 if (opP->mode != CONTROL
1688 if (opP->mode != LSH && opP->mode != RSH)
1693 if (opP->mode != CONTROL
1695 || opP->reg > last_movec_reg)
1699 const enum m68k_register *rp;
1700 for (rp = control_regs; *rp; rp++)
1701 if (*rp == opP->reg)
1709 if (opP->mode != IMMED)
1715 if (opP->mode == DREG
1716 || opP->mode == AREG
1717 || opP->mode == FPREG)
1726 opP->mask = 1 << (opP->reg - DATA0);
1729 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1732 opP->mask = 1 << (opP->reg - FP0 + 16);
1740 else if (opP->mode == CONTROL)
1749 opP->mask = 1 << 24;
1752 opP->mask = 1 << 25;
1755 opP->mask = 1 << 26;
1764 else if (opP->mode != REGLST)
1766 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1768 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1773 if (opP->mode != IMMED)
1775 else if (opP->disp.exp.X_op != O_constant
1776 || ! issbyte (opP->disp.exp.X_add_number))
1778 else if (! m68k_quick
1779 && instring[3] != 'q'
1780 && instring[4] != 'q')
1785 if (opP->mode != DREG
1786 && opP->mode != IMMED
1787 && opP->mode != ABSL)
1792 if (opP->mode != IMMED)
1794 else if (opP->disp.exp.X_op != O_constant
1795 || opP->disp.exp.X_add_number < 1
1796 || opP->disp.exp.X_add_number > 8)
1798 else if (! m68k_quick
1799 && (strncmp (instring, "add", 3) == 0
1800 || strncmp (instring, "sub", 3) == 0)
1801 && instring[3] != 'q')
1806 if (opP->mode != DREG && opP->mode != AREG)
1811 if (opP->mode != AINDR
1812 && (opP->mode != BASE
1814 && opP->reg != ZADDR0)
1815 || opP->disp.exp.X_op != O_absent
1816 || ((opP->index.reg < DATA0
1817 || opP->index.reg > DATA7)
1818 && (opP->index.reg < ADDR0
1819 || opP->index.reg > ADDR7))
1820 || opP->index.size != SIZE_UNSPEC
1821 || opP->index.scale != 1))
1826 if (opP->mode != CONTROL
1827 || ! (opP->reg == FPI
1829 || opP->reg == FPC))
1834 if (opP->mode != CONTROL || opP->reg != SR)
1839 if (opP->mode != IMMED)
1841 else if (opP->disp.exp.X_op != O_constant
1842 || opP->disp.exp.X_add_number < 0
1843 || opP->disp.exp.X_add_number > 7)
1848 if (opP->mode != CONTROL || opP->reg != USP)
1853 if (opP->mode != IMMED)
1855 else if (opP->disp.exp.X_op != O_constant
1856 || opP->disp.exp.X_add_number < -1
1857 || opP->disp.exp.X_add_number > 7
1858 || opP->disp.exp.X_add_number == 0)
1862 /* JF these are out of order. We could put them
1863 in order if we were willing to put up with
1864 bunches of #ifdef m68851s in the code.
1866 Don't forget that you need these operands
1867 to use 68030 MMU instructions. */
1869 /* Memory addressing mode used by pflushr. */
1871 if (opP->mode == CONTROL
1872 || opP->mode == FPREG
1873 || opP->mode == DREG
1874 || opP->mode == AREG
1875 || opP->mode == REGLST)
1877 /* We should accept immediate operands, but they
1878 supposedly have to be quad word, and we don't
1879 handle that. I would like to see what a Motorola
1880 assembler does before doing something here. */
1881 if (opP->mode == IMMED)
1886 if (opP->mode != CONTROL
1887 || (opP->reg != SFC && opP->reg != DFC))
1892 if (opP->mode != CONTROL || opP->reg != TC)
1897 if (opP->mode != CONTROL || opP->reg != AC)
1902 if (opP->mode != CONTROL
1905 && opP->reg != SCC))
1910 if (opP->mode != CONTROL
1916 if (opP->mode != CONTROL
1919 && opP->reg != CRP))
1943 if (opP->mode != CONTROL
1944 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1945 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1950 if (opP->mode != CONTROL || opP->reg != PSR)
1955 if (opP->mode != CONTROL || opP->reg != PCSR)
1960 if (opP->mode != CONTROL
1969 if (opP->mode != ABSL)
1974 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1976 /* FIXME: kludge instead of fixing parser:
1977 upper/lower registers are *not* CONTROL
1978 registers, but ordinary ones. */
1979 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1980 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1987 if (!(opP->mode == AINDR
1988 || (opP->mode == DISP && !(opP->reg == PC ||
1994 if (!(opP->mode == AINDR || opP->mode == DISP))
2010 opcode = opcode->m_next;
2015 && !(ok_arch & current_architecture))
2020 _("invalid instruction for this architecture; needs "), sizeof (buf));
2021 cp = buf + strlen (buf);
2025 strncpy (cp, _("ColdFire ISA_A"), (sizeof (buf) - (cp - buf)));
2027 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2031 strncpy (cp, _("ColdFire hardware divide"), (sizeof (buf) - (cp - buf)));
2033 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2037 strncpy (cp, _("ColdFire ISA_A+"), (sizeof (buf) - (cp - buf)));
2039 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2043 strncpy (cp, _("ColdFire ISA_B"), (sizeof (buf) - (cp - buf)));
2045 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2049 strncpy (cp, _("ColdFire fpu"), (sizeof (buf) - (cp - buf)));
2051 strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf)));
2055 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
2058 strcpy (cp, _("mmu (68030 or 68851)"));
2061 strcpy (cp, _("68020 or higher"));
2064 strcpy (cp, _("68000 or higher"));
2067 strcpy (cp, _("68010 or higher"));
2071 int got_one = 0, idx;
2073 for (idx = 0; idx < n_archs; idx++)
2075 if ((archs[idx].arch & ok_arch)
2076 && ! archs[idx].alias)
2080 strcpy (cp, " or ");
2084 strcpy (cp, archs[idx].name);
2090 cp = xmalloc (strlen (buf) + 1);
2095 the_ins.error = _("operands mismatch");
2102 /* Now assemble it. */
2103 the_ins.args = opcode->m_operands;
2104 the_ins.numargs = opcode->m_opnum;
2105 the_ins.numo = opcode->m_codenum;
2106 the_ins.opcode[0] = getone (opcode);
2107 the_ins.opcode[1] = gettwo (opcode);
2109 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2111 /* This switch is a doozy.
2112 Watch the first step; its a big one! */
2145 tmpreg = 0x3c; /* 7.4 */
2146 if (strchr ("bwl", s[1]))
2147 nextword = get_num (&opP->disp, 90);
2149 nextword = get_num (&opP->disp, 0);
2150 if (isvar (&opP->disp))
2151 add_fix (s[1], &opP->disp, 0, 0);
2155 if (!isbyte (nextword))
2156 opP->error = _("operand out of range");
2161 if (!isword (nextword))
2162 opP->error = _("operand out of range");
2167 if (!issword (nextword))
2168 opP->error = _("operand out of range");
2173 addword (nextword >> 16);
2200 /* We gotta put out some float. */
2201 if (op (&opP->disp) != O_big)
2206 /* Can other cases happen here? */
2207 if (op (&opP->disp) != O_constant)
2210 val = (valueT) offs (&opP->disp);
2214 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2215 val >>= LITTLENUM_NUMBER_OF_BITS;
2219 offs (&opP->disp) = gencnt;
2221 if (offs (&opP->disp) > 0)
2223 if (offs (&opP->disp) > baseo)
2225 as_warn (_("Bignum too big for %c format; truncated"),
2227 offs (&opP->disp) = baseo;
2229 baseo -= offs (&opP->disp);
2232 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2233 offs (&opP->disp)--;
2238 gen_to_words (words, baseo, (long) outro);
2239 for (wordp = words; baseo--; wordp++)
2243 tmpreg = opP->reg - DATA; /* 0.dreg */
2246 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2249 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2252 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2255 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2259 nextword = get_num (&opP->disp, 90);
2262 && ! isvar (&opP->disp)
2265 opP->disp.exp.X_op = O_symbol;
2266 #ifndef BFD_ASSEMBLER
2267 opP->disp.exp.X_add_symbol = &abs_symbol;
2269 opP->disp.exp.X_add_symbol =
2270 section_symbol (absolute_section);
2274 /* Force into index mode. Hope this works. */
2276 /* We do the first bit for 32-bit displacements, and the
2277 second bit for 16 bit ones. It is possible that we
2278 should make the default be WORD instead of LONG, but
2279 I think that'd break GCC, so we put up with a little
2280 inefficiency for the sake of working output. */
2282 if (!issword (nextword)
2283 || (isvar (&opP->disp)
2284 && ((opP->disp.size == SIZE_UNSPEC
2285 && flag_short_refs == 0
2286 && cpu_of_arch (current_architecture) >= m68020
2287 && ! arch_coldfire_p (current_architecture))
2288 || opP->disp.size == SIZE_LONG)))
2290 if (cpu_of_arch (current_architecture) < m68020
2291 || arch_coldfire_p (current_architecture))
2293 _("displacement too large for this architecture; needs 68020 or higher");
2295 tmpreg = 0x3B; /* 7.3 */
2297 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2298 if (isvar (&opP->disp))
2302 if (opP->disp.size == SIZE_LONG
2304 /* If the displacement needs pic
2305 relocation it cannot be relaxed. */
2306 || opP->disp.pic_reloc != pic_none
2311 add_fix ('l', &opP->disp, 1, 2);
2315 add_frag (adds (&opP->disp),
2317 TAB (PCREL1632, SZ_UNDEF));
2324 add_fix ('l', &opP->disp, 0, 0);
2329 addword (nextword >> 16);
2334 tmpreg = 0x3A; /* 7.2 */
2336 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2338 if (isvar (&opP->disp))
2342 add_fix ('w', &opP->disp, 1, 0);
2345 add_fix ('w', &opP->disp, 0, 0);
2355 baseo = get_num (&opP->disp, 90);
2356 if (opP->mode == POST || opP->mode == PRE)
2357 outro = get_num (&opP->odisp, 90);
2358 /* Figure out the `addressing mode'.
2359 Also turn on the BASE_DISABLE bit, if needed. */
2360 if (opP->reg == PC || opP->reg == ZPC)
2362 tmpreg = 0x3b; /* 7.3 */
2363 if (opP->reg == ZPC)
2366 else if (opP->reg == 0)
2369 tmpreg = 0x30; /* 6.garbage */
2371 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2374 tmpreg = 0x30 + opP->reg - ZADDR0;
2377 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2379 siz1 = opP->disp.size;
2380 if (opP->mode == POST || opP->mode == PRE)
2381 siz2 = opP->odisp.size;
2385 /* Index register stuff. */
2386 if (opP->index.reg != 0
2387 && opP->index.reg >= DATA
2388 && opP->index.reg <= ADDR7)
2390 nextword |= (opP->index.reg - DATA) << 12;
2392 if (opP->index.size == SIZE_LONG
2393 || (opP->index.size == SIZE_UNSPEC
2394 && m68k_index_width_default == SIZE_LONG))
2397 if ((opP->index.scale != 1
2398 && cpu_of_arch (current_architecture) < m68020)
2399 || (opP->index.scale == 8
2400 && (arch_coldfire_p (current_architecture)
2401 && !arch_coldfire_fpu (current_architecture))))
2404 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2407 if (arch_coldfire_p (current_architecture)
2408 && opP->index.size == SIZE_WORD)
2409 opP->error = _("invalid index size for coldfire");
2411 switch (opP->index.scale)
2428 GET US OUT OF HERE! */
2430 /* Must be INDEX, with an index register. Address
2431 register cannot be ZERO-PC, and either :b was
2432 forced, or we know it will fit. For a 68000 or
2433 68010, force this mode anyways, because the
2434 larger modes aren't supported. */
2435 if (opP->mode == BASE
2436 && ((opP->reg >= ADDR0
2437 && opP->reg <= ADDR7)
2440 if (siz1 == SIZE_BYTE
2441 || cpu_of_arch (current_architecture) < m68020
2442 || arch_coldfire_p (current_architecture)
2443 || (siz1 == SIZE_UNSPEC
2444 && ! isvar (&opP->disp)
2445 && issbyte (baseo)))
2447 nextword += baseo & 0xff;
2449 if (isvar (&opP->disp))
2451 /* Do a byte relocation. If it doesn't
2452 fit (possible on m68000) let the
2453 fixup processing complain later. */
2455 add_fix ('B', &opP->disp, 1, 1);
2457 add_fix ('B', &opP->disp, 0, 0);
2459 else if (siz1 != SIZE_BYTE)
2461 if (siz1 != SIZE_UNSPEC)
2462 as_warn (_("Forcing byte displacement"));
2463 if (! issbyte (baseo))
2464 opP->error = _("byte displacement out of range");
2469 else if (siz1 == SIZE_UNSPEC
2471 && isvar (&opP->disp)
2472 && subs (&opP->disp) == NULL
2474 /* If the displacement needs pic
2475 relocation it cannot be relaxed. */
2476 && opP->disp.pic_reloc == pic_none
2480 /* The code in md_convert_frag_1 needs to be
2481 able to adjust nextword. Call frag_grow
2482 to ensure that we have enough space in
2483 the frag obstack to make all the bytes
2486 nextword += baseo & 0xff;
2488 add_frag (adds (&opP->disp), offs (&opP->disp),
2489 TAB (PCINDEX, SZ_UNDEF));
2497 nextword |= 0x40; /* No index reg. */
2498 if (opP->index.reg >= ZDATA0
2499 && opP->index.reg <= ZDATA7)
2500 nextword |= (opP->index.reg - ZDATA0) << 12;
2501 else if (opP->index.reg >= ZADDR0
2502 || opP->index.reg <= ZADDR7)
2503 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2506 /* It isn't simple. */
2508 if (cpu_of_arch (current_architecture) < m68020
2509 || arch_coldfire_p (current_architecture))
2511 _("invalid operand mode for this architecture; needs 68020 or higher");
2514 /* If the guy specified a width, we assume that it is
2515 wide enough. Maybe it isn't. If so, we lose. */
2519 if (isvar (&opP->disp)
2521 : ! issword (baseo))
2526 else if (! isvar (&opP->disp) && baseo == 0)
2535 as_warn (_(":b not permitted; defaulting to :w"));
2545 /* Figure out inner displacement stuff. */
2546 if (opP->mode == POST || opP->mode == PRE)
2548 if (cpu_of_arch (current_architecture) & cpu32)
2549 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2553 if (isvar (&opP->odisp)
2555 : ! issword (outro))
2560 else if (! isvar (&opP->odisp) && outro == 0)
2569 as_warn (_(":b not permitted; defaulting to :w"));
2578 if (opP->mode == POST
2579 && (nextword & 0x40) == 0)
2584 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2586 if (opP->reg == PC || opP->reg == ZPC)
2587 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2589 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2591 if (siz1 == SIZE_LONG)
2592 addword (baseo >> 16);
2593 if (siz1 != SIZE_UNSPEC)
2596 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2597 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2598 if (siz2 == SIZE_LONG)
2599 addword (outro >> 16);
2600 if (siz2 != SIZE_UNSPEC)
2606 nextword = get_num (&opP->disp, 90);
2607 switch (opP->disp.size)
2612 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2614 tmpreg = 0x38; /* 7.0 */
2618 if (isvar (&opP->disp)
2619 && !subs (&opP->disp)
2620 && adds (&opP->disp)
2622 /* If the displacement needs pic relocation it
2623 cannot be relaxed. */
2624 && opP->disp.pic_reloc == pic_none
2627 && !strchr ("~%&$?", s[0]))
2629 tmpreg = 0x3A; /* 7.2 */
2630 add_frag (adds (&opP->disp),
2632 TAB (ABSTOPCREL, SZ_UNDEF));
2635 /* Fall through into long. */
2637 if (isvar (&opP->disp))
2638 add_fix ('l', &opP->disp, 0, 0);
2640 tmpreg = 0x39;/* 7.1 mode */
2641 addword (nextword >> 16);
2646 as_bad (_("unsupported byte value; use a different suffix"));
2650 if (isvar (&opP->disp))
2651 add_fix ('w', &opP->disp, 0, 0);
2653 tmpreg = 0x38;/* 7.0 mode */
2661 as_bad (_("unknown/incorrect operand"));
2665 /* If s[0] is '4', then this is for the mac instructions
2666 that can have a trailing_ampersand set. If so, set 0x100
2667 bit on tmpreg so install_gen_operand can check for it and
2668 set the appropriate bit (word2, bit 5). */
2671 if (opP->trailing_ampersand)
2674 install_gen_operand (s[1], tmpreg);
2680 { /* JF: I hate floating point! */
2695 tmpreg = get_num (&opP->disp, tmpreg);
2696 if (isvar (&opP->disp))
2697 add_fix (s[1], &opP->disp, 0, 0);
2700 case 'b': /* Danger: These do no check for
2701 certain types of overflow.
2703 if (!isbyte (tmpreg))
2704 opP->error = _("out of range");
2705 insop (tmpreg, opcode);
2706 if (isvar (&opP->disp))
2707 the_ins.reloc[the_ins.nrel - 1].n =
2708 (opcode->m_codenum) * 2 + 1;
2711 if (!issbyte (tmpreg))
2712 opP->error = _("out of range");
2713 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2714 if (isvar (&opP->disp))
2715 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2718 if (!isword (tmpreg))
2719 opP->error = _("out of range");
2720 insop (tmpreg, opcode);
2721 if (isvar (&opP->disp))
2722 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2725 if (!issword (tmpreg))
2726 opP->error = _("out of range");
2727 insop (tmpreg, opcode);
2728 if (isvar (&opP->disp))
2729 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2732 /* Because of the way insop works, we put these two out
2734 insop (tmpreg, opcode);
2735 insop (tmpreg >> 16, opcode);
2736 if (isvar (&opP->disp))
2737 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2744 install_operand (s[1], tmpreg);
2755 install_operand (s[1], opP->reg - ADDR);
2759 tmpreg = get_num (&opP->disp, 90);
2763 add_fix ('B', &opP->disp, 1, -1);
2766 add_fix ('w', &opP->disp, 1, 0);
2771 if (! HAVE_LONG_BRANCH (current_architecture))
2772 as_warn (_("Can't use long branches on 68000/68010/5200"));
2773 the_ins.opcode[0] |= 0xff;
2774 add_fix ('l', &opP->disp, 1, 0);
2779 if (subs (&opP->disp)) /* We can't relax it. */
2783 /* If the displacement needs pic relocation it cannot be
2785 if (opP->disp.pic_reloc != pic_none)
2788 /* This could either be a symbol, or an absolute
2789 address. If it's an absolute address, turn it into
2790 an absolute jump right here and keep it out of the
2792 if (adds (&opP->disp) == 0)
2794 if (the_ins.opcode[0] == 0x6000) /* jbra */
2795 the_ins.opcode[0] = 0x4EF9;
2796 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2797 the_ins.opcode[0] = 0x4EB9;
2800 the_ins.opcode[0] ^= 0x0100;
2801 the_ins.opcode[0] |= 0x0006;
2804 add_fix ('l', &opP->disp, 0, 0);
2810 /* Now we know it's going into the relaxer. Now figure
2811 out which mode. We try in this order of preference:
2812 long branch, absolute jump, byte/word branches only. */
2813 if (HAVE_LONG_BRANCH (current_architecture))
2814 add_frag (adds (&opP->disp), offs (&opP->disp),
2815 TAB (BRANCHBWL, SZ_UNDEF));
2816 else if (! flag_keep_pcrel)
2818 if ((the_ins.opcode[0] == 0x6000)
2819 || (the_ins.opcode[0] == 0x6100))
2820 add_frag (adds (&opP->disp), offs (&opP->disp),
2821 TAB (BRABSJUNC, SZ_UNDEF));
2823 add_frag (adds (&opP->disp), offs (&opP->disp),
2824 TAB (BRABSJCOND, SZ_UNDEF));
2827 add_frag (adds (&opP->disp), offs (&opP->disp),
2828 TAB (BRANCHBW, SZ_UNDEF));
2831 if (isvar (&opP->disp))
2833 /* Check for DBcc instructions. We can relax them,
2834 but only if we have long branches and/or absolute
2836 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2837 && (HAVE_LONG_BRANCH (current_architecture)
2838 || (! flag_keep_pcrel)))
2840 if (HAVE_LONG_BRANCH (current_architecture))
2841 add_frag (adds (&opP->disp), offs (&opP->disp),
2842 TAB (DBCCLBR, SZ_UNDEF));
2844 add_frag (adds (&opP->disp), offs (&opP->disp),
2845 TAB (DBCCABSJ, SZ_UNDEF));
2848 add_fix ('w', &opP->disp, 1, 0);
2852 case 'C': /* Fixed size LONG coproc branches. */
2853 add_fix ('l', &opP->disp, 1, 0);
2857 case 'c': /* Var size Coprocesssor branches. */
2858 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2860 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2861 add_fix ('l', &opP->disp, 1, 0);
2866 add_frag (adds (&opP->disp), offs (&opP->disp),
2867 TAB (FBRANCH, SZ_UNDEF));
2874 case 'C': /* Ignore it. */
2877 case 'd': /* JF this is a kludge. */
2878 install_operand ('s', opP->reg - ADDR);
2879 tmpreg = get_num (&opP->disp, 90);
2880 if (!issword (tmpreg))
2882 as_warn (_("Expression out of range, using 0"));
2889 install_operand (s[1], opP->reg - DATA);
2892 case 'e': /* EMAC ACCx, reg/reg. */
2893 install_operand (s[1], opP->reg - ACC);
2896 case 'E': /* Ignore it. */
2900 install_operand (s[1], opP->reg - FP0);
2903 case 'g': /* EMAC ACCEXTx. */
2904 install_operand (s[1], opP->reg - ACCEXT01);
2907 case 'G': /* Ignore it. */
2912 tmpreg = opP->reg - COP0;
2913 install_operand (s[1], tmpreg);
2916 case 'i': /* MAC/EMAC scale factor. */
2917 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2920 case 'J': /* JF foo. */
3049 install_operand (s[1], tmpreg);
3053 tmpreg = get_num (&opP->disp, 55);
3054 install_operand (s[1], tmpreg & 0x7f);
3061 if (tmpreg & 0x7FF0000)
3062 as_bad (_("Floating point register in register list"));
3063 insop (reverse_16_bits (tmpreg), opcode);
3067 if (tmpreg & 0x700FFFF)
3068 as_bad (_("Wrong register in floating-point reglist"));
3069 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3077 if (tmpreg & 0x7FF0000)
3078 as_bad (_("Floating point register in register list"));
3079 insop (tmpreg, opcode);
3081 else if (s[1] == '8')
3083 if (tmpreg & 0x0FFFFFF)
3084 as_bad (_("incorrect register in reglist"));
3085 install_operand (s[1], tmpreg >> 24);
3089 if (tmpreg & 0x700FFFF)
3090 as_bad (_("wrong register in floating-point reglist"));
3092 install_operand (s[1], tmpreg >> 16);
3097 install_operand (s[1], get_num (&opP->disp, 60));
3101 tmpreg = ((opP->mode == DREG)
3102 ? 0x20 + (int) (opP->reg - DATA)
3103 : (get_num (&opP->disp, 40) & 0x1F));
3104 install_operand (s[1], tmpreg);
3108 tmpreg = get_num (&opP->disp, 10);
3111 install_operand (s[1], tmpreg);
3115 /* This depends on the fact that ADDR registers are eight
3116 more than their corresponding DATA regs, so the result
3117 will have the ADDR_REG bit set. */
3118 install_operand (s[1], opP->reg - DATA);
3122 if (opP->mode == AINDR)
3123 install_operand (s[1], opP->reg - DATA);
3125 install_operand (s[1], opP->index.reg - DATA);
3129 if (opP->reg == FPI)
3131 else if (opP->reg == FPS)
3133 else if (opP->reg == FPC)
3137 install_operand (s[1], tmpreg);
3140 case 'S': /* Ignore it. */
3144 install_operand (s[1], get_num (&opP->disp, 30));
3147 case 'U': /* Ignore it. */
3166 as_fatal (_("failed sanity check"));
3167 } /* switch on cache token. */
3168 install_operand (s[1], tmpreg);
3171 /* JF: These are out of order, I fear. */
3184 install_operand (s[1], tmpreg);
3210 install_operand (s[1], tmpreg);
3214 if (opP->reg == VAL)
3233 install_operand (s[1], tmpreg);
3247 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3258 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3264 install_operand (s[1], tmpreg);
3267 know (opP->reg == PSR);
3270 know (opP->reg == PCSR);
3285 install_operand (s[1], tmpreg);
3288 tmpreg = get_num (&opP->disp, 20);
3289 install_operand (s[1], tmpreg);
3291 case '_': /* used only for move16 absolute 32-bit address. */
3292 if (isvar (&opP->disp))
3293 add_fix ('l', &opP->disp, 0, 0);
3294 tmpreg = get_num (&opP->disp, 90);
3295 addword (tmpreg >> 16);
3296 addword (tmpreg & 0xFFFF);
3299 install_operand (s[1], opP->reg - DATA0L);
3300 opP->reg -= (DATA0L);
3301 opP->reg &= 0x0F; /* remove upper/lower bit. */
3304 tmpreg = get_num (&opP->disp, 80);
3307 install_operand (s[1], tmpreg);
3314 /* By the time whe get here (FINALLY) the_ins contains the complete
3315 instruction, ready to be emitted. . . */
3319 reverse_16_bits (in)
3325 static int mask[16] =
3327 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3328 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3330 for (n = 0; n < 16; n++)
3333 out |= mask[15 - n];
3336 } /* reverse_16_bits() */
3345 static int mask[8] =
3347 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3350 for (n = 0; n < 8; n++)
3356 } /* reverse_8_bits() */
3358 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3359 (that value is chosen in the frag_var call in md_assemble). TYPE
3360 is the subtype of the frag to be generated; its primary type is
3361 rs_machine_dependent.
3363 The TYPE parameter is also used by md_convert_frag_1 and
3364 md_estimate_size_before_relax. The appropriate type of fixup will
3365 be emitted by md_convert_frag_1.
3367 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3369 install_operand (mode, val)
3376 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3379 the_ins.opcode[0] |= val << 9;
3382 the_ins.opcode[1] |= val << 12;
3385 the_ins.opcode[1] |= val << 6;
3388 the_ins.opcode[1] |= val;
3391 the_ins.opcode[2] |= val << 12;
3394 the_ins.opcode[2] |= val << 6;
3397 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3398 three words long! */
3400 the_ins.opcode[2] |= val;
3403 the_ins.opcode[1] |= val << 7;
3406 the_ins.opcode[1] |= val << 10;
3410 the_ins.opcode[1] |= val << 5;
3415 the_ins.opcode[1] |= (val << 10) | (val << 7);
3418 the_ins.opcode[1] |= (val << 12) | val;
3421 the_ins.opcode[0] |= val = 0xff;
3424 the_ins.opcode[0] |= val << 9;
3427 the_ins.opcode[1] |= val;
3430 the_ins.opcode[1] |= val;
3431 the_ins.numo++; /* What a hack. */
3434 the_ins.opcode[1] |= val << 4;
3442 the_ins.opcode[0] |= (val << 6);
3445 the_ins.opcode[1] = (val >> 16);
3446 the_ins.opcode[2] = val & 0xffff;
3449 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3450 the_ins.opcode[0] |= ((val & 0x7) << 9);
3451 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3453 case 'n': /* MAC/EMAC Rx on !load. */
3454 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3455 the_ins.opcode[0] |= ((val & 0x7) << 9);
3456 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3458 case 'o': /* MAC/EMAC Rx on load. */
3459 the_ins.opcode[1] |= val << 12;
3460 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3462 case 'M': /* MAC/EMAC Ry on !load. */
3463 the_ins.opcode[0] |= (val & 0xF);
3464 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3466 case 'N': /* MAC/EMAC Ry on load. */
3467 the_ins.opcode[1] |= (val & 0xF);
3468 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3471 the_ins.opcode[1] |= ((val != 1) << 10);
3474 the_ins.opcode[0] |= ((val & 0x3) << 9);
3477 the_ins.opcode[0] |= ((val & 0x3) << 0);
3480 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3481 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3484 the_ins.opcode[0] |= ((val & 0x1) << 7);
3485 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3488 the_ins.opcode[1] |= ((val & 0x3) << 9);
3491 the_ins.opcode[0] |= (val & 0x1) <<10;
3495 as_fatal (_("failed sanity check."));
3500 install_gen_operand (mode, val)
3506 case '/': /* Special for mask loads for mac/msac insns with
3507 possible mask; trailing_ampersend set in bit 8. */
3508 the_ins.opcode[0] |= (val & 0x3f);
3509 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3512 the_ins.opcode[0] |= val;
3515 /* This is a kludge!!! */
3516 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3525 the_ins.opcode[0] |= val;
3527 /* more stuff goes here. */
3529 as_fatal (_("failed sanity check."));
3533 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3534 then deal with the bitfield hack. */
3537 crack_operand (str, opP)
3539 register struct m68k_op *opP;
3541 register int parens;
3543 register char *beg_str;
3551 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3557 else if (*str == ')')
3561 opP->error = _("Extra )");
3567 if (flag_mri && *str == '\'')
3568 inquote = ! inquote;
3570 if (!*str && parens)
3572 opP->error = _("Missing )");
3577 if (m68k_ip_op (beg_str, opP) != 0)
3584 c = *++str; /* JF bitfield hack. */
3589 as_bad (_("Missing operand"));
3592 /* Detect MRI REG symbols and convert them to REGLSTs. */
3593 if (opP->mode == CONTROL && (int)opP->reg < 0)
3596 opP->mask = ~(int)opP->reg;
3603 /* This is the guts of the machine-dependent assembler. STR points to a
3604 machine dependent instruction. This function is supposed to emit
3605 the frags/bytes it assembles to.
3609 insert_reg (regname, regnum)
3610 const char *regname;
3616 #ifdef REGISTER_PREFIX
3617 if (!flag_reg_prefix_optional)
3619 buf[0] = REGISTER_PREFIX;
3620 strcpy (buf + 1, regname);
3625 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3626 &zero_address_frag));
3628 for (i = 0; regname[i]; i++)
3629 buf[i] = TOUPPER (regname[i]);
3632 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3633 &zero_address_frag));
3642 static const struct init_entry init_table[] =
3702 { "accext01", ACCEXT01 },
3703 { "accext23", ACCEXT23 },
3707 /* Control registers. */
3708 { "sfc", SFC }, /* Source Function Code. */
3710 { "dfc", DFC }, /* Destination Function Code. */
3712 { "cacr", CACR }, /* Cache Control Register. */
3713 { "caar", CAAR }, /* Cache Address Register. */
3715 { "usp", USP }, /* User Stack Pointer. */
3716 { "vbr", VBR }, /* Vector Base Register. */
3717 { "msp", MSP }, /* Master Stack Pointer. */
3718 { "isp", ISP }, /* Interrupt Stack Pointer. */
3720 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3721 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3722 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3723 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3725 /* 68ec040 versions of same */
3726 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3727 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3728 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3729 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3731 /* mcf5200 versions of same. The ColdFire programmer's reference
3732 manual indicated that the order is 2,3,0,1, but Ken Rose
3733 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3734 { "acr0", ACR0 }, /* Access Control Unit 0. */
3735 { "acr1", ACR1 }, /* Access Control Unit 1. */
3736 { "acr2", ACR2 }, /* Access Control Unit 2. */
3737 { "acr3", ACR3 }, /* Access Control Unit 3. */
3739 { "tc", TC }, /* MMU Translation Control Register. */
3742 { "mmusr", MMUSR }, /* MMU Status Register. */
3743 { "srp", SRP }, /* User Root Pointer. */
3744 { "urp", URP }, /* Supervisor Root Pointer. */
3749 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3750 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3751 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3752 { "mbar", MBAR }, /* Module Base Address Register. */
3754 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3755 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3756 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3757 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3758 { "mpcr", MPCR }, /* mcfv4e registers. */
3759 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3760 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3761 { "asid", TC }, /* mcfv4e registers. */
3762 { "mmubar", BUSCR }, /* mcfv4e registers. */
3763 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3764 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3765 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3766 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3767 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3768 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3769 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3770 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3771 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3772 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3773 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3774 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3776 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3777 { "rambar", RAMBAR }, /* mcf528x registers. */
3778 /* End of control registers. */
3812 /* 68ec030 versions of same. */
3815 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3818 /* Suppressed data and address registers. */
3836 /* Upper and lower data and address registers, used by macw and msacw. */
3880 for (i = 0; init_table[i].name; i++)
3881 insert_reg (init_table[i].name, init_table[i].number);
3884 static int no_68851, no_68881;
3887 /* a.out machine type. Default to 68020. */
3888 int m68k_aout_machtype = 2;
3900 int shorts_this_frag;
3903 /* In MRI mode, the instruction and operands are separated by a
3904 space. Anything following the operands is a comment. The label
3905 has already been removed. */
3913 for (s = str; *s != '\0'; s++)
3915 if ((*s == ' ' || *s == '\t') && ! inquote)
3933 inquote = ! inquote;
3938 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3943 for (n = 0; n < the_ins.numargs; n++)
3944 if (the_ins.operands[n].error)
3946 er = the_ins.operands[n].error;
3952 as_bad (_("%s -- statement `%s' ignored"), er, str);
3956 /* If there is a current label, record that it marks an instruction. */
3957 if (current_label != NULL)
3959 current_label->text = 1;
3960 current_label = NULL;
3964 /* Tie dwarf2 debug info to the address at the start of the insn. */
3965 dwarf2_emit_insn (0);
3968 if (the_ins.nfrag == 0)
3970 /* No frag hacking involved; just put it out. */
3971 toP = frag_more (2 * the_ins.numo);
3972 fromP = &the_ins.opcode[0];
3973 for (m = the_ins.numo; m; --m)
3975 md_number_to_chars (toP, (long) (*fromP), 2);
3979 /* Put out symbol-dependent info. */
3980 for (m = 0; m < the_ins.nrel; m++)
3982 switch (the_ins.reloc[m].wid)
4001 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4002 the_ins.reloc[m].wid);
4005 fixP = fix_new_exp (frag_now,
4006 ((toP - frag_now->fr_literal)
4007 - the_ins.numo * 2 + the_ins.reloc[m].n),
4009 &the_ins.reloc[m].exp,
4010 the_ins.reloc[m].pcrel,
4011 get_reloc_code (n, the_ins.reloc[m].pcrel,
4012 the_ins.reloc[m].pic_reloc));
4013 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4014 if (the_ins.reloc[m].wid == 'B')
4015 fixP->fx_signed = 1;
4020 /* There's some frag hacking. */
4022 /* Calculate the max frag size. */
4025 wid = 2 * the_ins.fragb[0].fragoff;
4026 for (n = 1; n < the_ins.nfrag; n++)
4027 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4028 /* frag_var part. */
4030 /* Make sure the whole insn fits in one chunk, in particular that
4031 the var part is attached, as we access one byte before the
4032 variable frag for byte branches. */
4036 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4041 wid = 2 * the_ins.fragb[n].fragoff;
4043 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4044 toP = frag_more (wid);
4046 shorts_this_frag = 0;
4047 for (m = wid / 2; m; --m)
4049 md_number_to_chars (toP, (long) (*fromP), 2);
4054 for (m = 0; m < the_ins.nrel; m++)
4056 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4058 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4061 wid = the_ins.reloc[m].wid;
4064 the_ins.reloc[m].wid = 0;
4065 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4067 fixP = fix_new_exp (frag_now,
4068 ((toP - frag_now->fr_literal)
4069 - the_ins.numo * 2 + the_ins.reloc[m].n),
4071 &the_ins.reloc[m].exp,
4072 the_ins.reloc[m].pcrel,
4073 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4074 the_ins.reloc[m].pic_reloc));
4075 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4077 (void) frag_var (rs_machine_dependent, 10, 0,
4078 (relax_substateT) (the_ins.fragb[n].fragty),
4079 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4081 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4082 shorts_this_frag = 0;
4085 toP = frag_more (n * sizeof (short));
4088 md_number_to_chars (toP, (long) (*fromP), 2);
4094 for (m = 0; m < the_ins.nrel; m++)
4098 wid = the_ins.reloc[m].wid;
4101 the_ins.reloc[m].wid = 0;
4102 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4104 fixP = fix_new_exp (frag_now,
4105 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4106 - shorts_this_frag * 2),
4108 &the_ins.reloc[m].exp,
4109 the_ins.reloc[m].pcrel,
4110 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4111 the_ins.reloc[m].pic_reloc));
4112 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4120 * md_begin -- set up hash tables with 68000 instructions.
4121 * similar to what the vax assembler does. ---phr
4123 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4124 a copy of it at runtime, adding in the information we want but isn't
4125 there. I think it'd be better to have an awk script hack the table
4126 at compile time. Or even just xstr the table and use it as-is. But
4127 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4130 const struct m68k_opcode *ins;
4131 struct m68k_incant *hack, *slak;
4132 const char *retval = 0; /* Empty string, or error msg text. */
4137 flag_reg_prefix_optional = 1;
4139 if (! m68k_rel32_from_cmdline)
4143 op_hash = hash_new ();
4145 obstack_begin (&robyn, 4000);
4146 for (i = 0; i < m68k_numopcodes; i++)
4148 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4151 ins = &m68k_opcodes[i];
4152 /* We *could* ignore insns that don't match our arch here
4153 but just leaving them out of the hash. */
4154 slak->m_operands = ins->args;
4155 slak->m_opnum = strlen (slak->m_operands) / 2;
4156 slak->m_arch = ins->arch;
4157 slak->m_opcode = ins->opcode;
4158 /* This is kludgey. */
4159 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4160 if (i + 1 != m68k_numopcodes
4161 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
4163 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4168 slak = slak->m_next;
4172 retval = hash_insert (op_hash, ins->name, (char *) hack);
4174 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4177 for (i = 0; i < m68k_numaliases; i++)
4179 const char *name = m68k_opcode_aliases[i].primary;
4180 const char *alias = m68k_opcode_aliases[i].alias;
4181 PTR val = hash_find (op_hash, name);
4183 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4184 retval = hash_insert (op_hash, alias, val);
4186 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4189 /* In MRI mode, all unsized branches are variable sized. Normally,
4190 they are word sized. */
4193 static struct m68k_opcode_alias mri_aliases[] =
4214 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4217 const char *name = mri_aliases[i].primary;
4218 const char *alias = mri_aliases[i].alias;
4219 PTR val = hash_find (op_hash, name);
4221 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4222 retval = hash_jam (op_hash, alias, val);
4224 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4228 for (i = 0; i < (int) sizeof (notend_table); i++)
4230 notend_table[i] = 0;
4231 alt_notend_table[i] = 0;
4233 notend_table[','] = 1;
4234 notend_table['{'] = 1;
4235 notend_table['}'] = 1;
4236 alt_notend_table['a'] = 1;
4237 alt_notend_table['A'] = 1;
4238 alt_notend_table['d'] = 1;
4239 alt_notend_table['D'] = 1;
4240 alt_notend_table['#'] = 1;
4241 alt_notend_table['&'] = 1;
4242 alt_notend_table['f'] = 1;
4243 alt_notend_table['F'] = 1;
4244 #ifdef REGISTER_PREFIX
4245 alt_notend_table[REGISTER_PREFIX] = 1;
4248 /* We need to put '(' in alt_notend_table to handle
4249 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
4251 alt_notend_table['('] = 1;
4253 /* We need to put '@' in alt_notend_table to handle
4254 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
4256 alt_notend_table['@'] = 1;
4258 /* We need to put digits in alt_notend_table to handle
4259 bfextu %d0{24:1},%d0
4261 alt_notend_table['0'] = 1;
4262 alt_notend_table['1'] = 1;
4263 alt_notend_table['2'] = 1;
4264 alt_notend_table['3'] = 1;
4265 alt_notend_table['4'] = 1;
4266 alt_notend_table['5'] = 1;
4267 alt_notend_table['6'] = 1;
4268 alt_notend_table['7'] = 1;
4269 alt_notend_table['8'] = 1;
4270 alt_notend_table['9'] = 1;
4272 #ifndef MIT_SYNTAX_ONLY
4273 /* Insert pseudo ops, these have to go into the opcode table since
4274 gas expects pseudo ops to start with a dot. */
4277 while (mote_pseudo_table[n].poc_name)
4279 hack = (struct m68k_incant *)
4280 obstack_alloc (&robyn, sizeof (struct m68k_incant));
4281 hash_insert (op_hash,
4282 mote_pseudo_table[n].poc_name, (char *) hack);
4283 hack->m_operands = 0;
4293 record_alignment (text_section, 2);
4294 record_alignment (data_section, 2);
4295 record_alignment (bss_section, 2);
4300 select_control_regs ()
4302 /* Note which set of "movec" control registers is available. */
4303 switch (current_chip)
4307 as_warn (_("architecture not yet selected: defaulting to 68020"));
4308 control_regs = m68020_control_regs;
4312 control_regs = m68000_control_regs;
4315 control_regs = m68010_control_regs;
4319 control_regs = m68020_control_regs;
4322 control_regs = m68040_control_regs;
4325 control_regs = m68060_control_regs;
4328 control_regs = cpu32_control_regs;
4334 control_regs = mcf_control_regs;
4338 control_regs = mcf528x_control_regs;
4342 control_regs = mcfv4e_control_regs;
4350 m68k_init_after_args ()
4352 if (cpu_of_arch (current_architecture) == 0)
4355 const char *default_cpu = TARGET_CPU;
4357 if (*default_cpu == 'm')
4359 for (i = 0; i < n_archs; i++)
4360 if (strcasecmp (default_cpu, archs[i].name) == 0)
4364 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4365 current_architecture |= m68020;
4368 current_architecture |= archs[i].arch;
4370 /* Permit m68881 specification with all cpus; those that can't work
4371 with a coprocessor could be doing emulation. */
4372 if (current_architecture & m68851)
4374 if (current_architecture & m68040)
4376 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4379 /* What other incompatibilities could we check for? */
4381 /* Toss in some default assumptions about coprocessors. */
4383 && (cpu_of_arch (current_architecture)
4384 /* Can CPU32 have a 68881 coprocessor?? */
4385 & (m68020 | m68030 | cpu32)))
4387 current_architecture |= m68881;
4390 && (cpu_of_arch (current_architecture) & m68020up) != 0
4391 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4393 current_architecture |= m68851;
4395 if (no_68881 && (current_architecture & m68881))
4396 as_bad (_("options for 68881 and no-68881 both given"));
4397 if (no_68851 && (current_architecture & m68851))
4398 as_bad (_("options for 68851 and no-68851 both given"));
4401 /* Work out the magic number. This isn't very general. */
4402 if (current_architecture & m68000)
4403 m68k_aout_machtype = 0;
4404 else if (current_architecture & m68010)
4405 m68k_aout_machtype = 1;
4406 else if (current_architecture & m68020)
4407 m68k_aout_machtype = 2;
4409 m68k_aout_machtype = 2;
4412 /* Note which set of "movec" control registers is available. */
4413 select_control_regs ();
4415 if (cpu_of_arch (current_architecture) < m68020
4416 || arch_coldfire_p (current_architecture))
4417 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4420 /* This is called when a label is defined. */
4423 m68k_frob_label (sym)
4426 struct label_line *n;
4428 n = (struct label_line *) xmalloc (sizeof *n);
4431 as_where (&n->file, &n->line);
4437 /* This is called when a value that is not an instruction is emitted. */
4440 m68k_flush_pending_output ()
4442 current_label = NULL;
4445 /* This is called at the end of the assembly, when the final value of
4446 the label is known. We warn if this is a text symbol aligned at an
4450 m68k_frob_symbol (sym)
4453 if (S_GET_SEGMENT (sym) == reg_section
4454 && (int) S_GET_VALUE (sym) < 0)
4456 S_SET_SEGMENT (sym, absolute_section);
4457 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4459 else if ((S_GET_VALUE (sym) & 1) != 0)
4461 struct label_line *l;
4463 for (l = labels; l != NULL; l = l->next)
4465 if (l->label == sym)
4468 as_warn_where (l->file, l->line,
4469 _("text label `%s' aligned to odd boundary"),
4477 /* This is called if we go in or out of MRI mode because of the .mri
4481 m68k_mri_mode_change (on)
4486 if (! flag_reg_prefix_optional)
4488 flag_reg_prefix_optional = 1;
4489 #ifdef REGISTER_PREFIX
4494 if (! m68k_rel32_from_cmdline)
4499 if (! reg_prefix_optional_seen)
4501 #ifdef REGISTER_PREFIX_OPTIONAL
4502 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4504 flag_reg_prefix_optional = 0;
4506 #ifdef REGISTER_PREFIX
4511 if (! m68k_rel32_from_cmdline)
4516 /* Equal to MAX_PRECISION in atof-ieee.c. */
4517 #define MAX_LITTLENUMS 6
4519 /* Turn a string in input_line_pointer into a floating point constant
4520 of type TYPE, and store the appropriate bytes in *LITP. The number
4521 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4522 returned, or NULL on OK. */
4525 md_atof (type, litP, sizeP)
4531 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4532 LITTLENUM_TYPE *wordP;
4563 return _("Bad call to MD_ATOF()");
4565 t = atof_ieee (input_line_pointer, type, words);
4567 input_line_pointer = t;
4569 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4570 for (wordP = words; prec--;)
4572 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4573 litP += sizeof (LITTLENUM_TYPE);
4579 md_number_to_chars (buf, val, n)
4584 number_to_chars_bigendian (buf, val, n);
4588 md_apply_fix3 (fixP, valP, seg)
4591 segT seg ATTRIBUTE_UNUSED;
4593 offsetT val = *valP;
4594 addressT upper_limit;
4595 offsetT lower_limit;
4597 /* This is unnecessary but it convinces the native rs6000 compiler
4598 to generate the code we want. */
4599 char *buf = fixP->fx_frag->fr_literal;
4600 buf += fixP->fx_where;
4601 /* End ibm compiler workaround. */
4603 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
4605 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4611 memset (buf, 0, fixP->fx_size);
4612 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4614 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4615 && !S_IS_DEFINED (fixP->fx_addsy)
4616 && !S_IS_WEAK (fixP->fx_addsy))
4617 S_SET_WEAK (fixP->fx_addsy);
4622 #ifdef BFD_ASSEMBLER
4623 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4624 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4628 switch (fixP->fx_size)
4630 /* The cast to offsetT below are necessary to make code
4631 correct for machines where ints are smaller than offsetT. */
4635 lower_limit = - (offsetT) 0x80;
4638 *buf++ = (val >> 8);
4640 upper_limit = 0x7fff;
4641 lower_limit = - (offsetT) 0x8000;
4644 *buf++ = (val >> 24);
4645 *buf++ = (val >> 16);
4646 *buf++ = (val >> 8);
4648 upper_limit = 0x7fffffff;
4649 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4652 BAD_CASE (fixP->fx_size);
4655 /* Fix up a negative reloc. */
4656 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4658 fixP->fx_addsy = fixP->fx_subsy;
4659 fixP->fx_subsy = NULL;
4663 /* For non-pc-relative values, it's conceivable we might get something
4664 like "0xff" for a byte field. So extend the upper part of the range
4665 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4666 so that we can do any range checking at all. */
4667 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4668 upper_limit = upper_limit * 2 + 1;
4670 if ((addressT) val > upper_limit
4671 && (val > 0 || val < lower_limit))
4672 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4674 /* A one byte PC-relative reloc means a short branch. We can't use
4675 a short branch with a value of 0 or -1, because those indicate
4676 different opcodes (branches with longer offsets). fixup_segment
4677 in write.c may have clobbered fx_pcrel, so we need to examine the
4680 #ifdef BFD_ASSEMBLER
4681 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4684 && fixP->fx_size == 1
4685 && (fixP->fx_addsy == NULL
4686 || S_IS_DEFINED (fixP->fx_addsy))
4687 && (val == 0 || val == -1))
4688 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4691 /* *fragP has been relaxed to its final size, and now needs to have
4692 the bytes inside it modified to conform to the new size There is UGLY
4696 md_convert_frag_1 (fragP)
4697 register fragS *fragP;
4702 /* Address in object code of the displacement. */
4703 register int object_address = fragP->fr_fix + fragP->fr_address;
4705 /* Address in gas core of the place to store the displacement. */
4706 /* This convinces the native rs6000 compiler to generate the code we
4708 register char *buffer_address = fragP->fr_literal;
4709 buffer_address += fragP->fr_fix;
4710 /* End ibm compiler workaround. */
4712 /* The displacement of the address, from current location. */
4713 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4714 disp = (disp + fragP->fr_offset) - object_address;
4716 switch (fragP->fr_subtype)
4718 case TAB (BRANCHBWL, BYTE):
4719 case TAB (BRABSJUNC, BYTE):
4720 case TAB (BRABSJCOND, BYTE):
4721 case TAB (BRANCHBW, BYTE):
4722 know (issbyte (disp));
4724 as_bad_where (fragP->fr_file, fragP->fr_line,
4725 _("short branch with zero offset: use :w"));
4726 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4727 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4728 fixP->fx_pcrel_adjust = -1;
4730 case TAB (BRANCHBWL, SHORT):
4731 case TAB (BRABSJUNC, SHORT):
4732 case TAB (BRABSJCOND, SHORT):
4733 case TAB (BRANCHBW, SHORT):
4734 fragP->fr_opcode[1] = 0x00;
4735 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4736 1, RELAX_RELOC_PC16);
4739 case TAB (BRANCHBWL, LONG):
4740 fragP->fr_opcode[1] = (char) 0xFF;
4741 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4742 1, RELAX_RELOC_PC32);
4745 case TAB (BRABSJUNC, LONG):
4746 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4748 if (flag_keep_pcrel)
4749 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4750 fragP->fr_opcode[0] = 0x4E;
4751 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4752 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4753 0, RELAX_RELOC_ABS32);
4756 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4758 if (flag_keep_pcrel)
4759 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4760 fragP->fr_opcode[0] = 0x4E;
4761 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4762 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4763 0, RELAX_RELOC_ABS32);
4768 /* This cannot happen, because jbsr and jbra are the only two
4769 unconditional branches. */
4773 case TAB (BRABSJCOND, LONG):
4774 if (flag_keep_pcrel)
4775 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4777 /* Only Bcc 68000 instructions can come here
4778 Change bcc into b!cc/jmp absl long. */
4779 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4780 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4782 /* JF: these used to be fr_opcode[2,3], but they may be in a
4783 different frag, in which case referring to them is a no-no.
4784 Only fr_opcode[0,1] are guaranteed to work. */
4785 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4786 *buffer_address++ = (char) 0xf9;
4787 fragP->fr_fix += 2; /* Account for jmp instruction. */
4788 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4789 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4792 case TAB (FBRANCH, SHORT):
4793 know ((fragP->fr_opcode[1] & 0x40) == 0);
4794 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4795 1, RELAX_RELOC_PC16);
4798 case TAB (FBRANCH, LONG):
4799 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4800 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4801 1, RELAX_RELOC_PC32);
4804 case TAB (DBCCLBR, SHORT):
4805 case TAB (DBCCABSJ, SHORT):
4806 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4807 1, RELAX_RELOC_PC16);
4810 case TAB (DBCCLBR, LONG):
4811 /* Only DBcc instructions can come here.
4812 Change dbcc into dbcc/bral.
4813 JF: these used to be fr_opcode[2-7], but that's wrong. */
4814 if (flag_keep_pcrel)
4815 as_fatal (_("Tried to convert DBcc to absolute jump"));
4817 *buffer_address++ = 0x00; /* Branch offset = 4. */
4818 *buffer_address++ = 0x04;
4819 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4820 *buffer_address++ = 0x06;
4821 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4822 *buffer_address++ = (char) 0xff;
4824 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4825 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4829 case TAB (DBCCABSJ, LONG):
4830 /* Only DBcc instructions can come here.
4831 Change dbcc into dbcc/jmp.
4832 JF: these used to be fr_opcode[2-7], but that's wrong. */
4833 if (flag_keep_pcrel)
4834 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4836 *buffer_address++ = 0x00; /* Branch offset = 4. */
4837 *buffer_address++ = 0x04;
4838 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4839 *buffer_address++ = 0x06;
4840 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4841 *buffer_address++ = (char) 0xf9;
4843 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4844 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4848 case TAB (PCREL1632, SHORT):
4849 fragP->fr_opcode[1] &= ~0x3F;
4850 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4851 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4852 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4855 case TAB (PCREL1632, LONG):
4856 /* Already set to mode 7.3; this indicates: PC indirect with
4857 suppressed index, 32-bit displacement. */
4858 *buffer_address++ = 0x01;
4859 *buffer_address++ = 0x70;
4861 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4862 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4863 fixP->fx_pcrel_adjust = 2;
4866 case TAB (PCINDEX, BYTE):
4867 assert (fragP->fr_fix >= 2);
4868 buffer_address[-2] &= ~1;
4869 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4870 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4871 fixP->fx_pcrel_adjust = 1;
4873 case TAB (PCINDEX, SHORT):
4874 assert (fragP->fr_fix >= 2);
4875 buffer_address[-2] |= 0x1;
4876 buffer_address[-1] = 0x20;
4877 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4878 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4879 fixP->fx_pcrel_adjust = 2;
4882 case TAB (PCINDEX, LONG):
4883 assert (fragP->fr_fix >= 2);
4884 buffer_address[-2] |= 0x1;
4885 buffer_address[-1] = 0x30;
4886 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4887 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4888 fixP->fx_pcrel_adjust = 2;
4891 case TAB (ABSTOPCREL, SHORT):
4892 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4893 1, RELAX_RELOC_PC16);
4896 case TAB (ABSTOPCREL, LONG):
4897 if (flag_keep_pcrel)
4898 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4899 /* The thing to do here is force it to ABSOLUTE LONG, since
4900 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4901 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4903 fragP->fr_opcode[1] &= ~0x3F;
4904 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4905 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4906 0, RELAX_RELOC_ABS32);
4912 #ifndef BFD_ASSEMBLER
4915 md_convert_frag (headers, sec, fragP)
4916 object_headers *headers ATTRIBUTE_UNUSED;
4917 segT sec ATTRIBUTE_UNUSED;
4920 md_convert_frag_1 (fragP);
4926 md_convert_frag (abfd, sec, fragP)
4927 bfd *abfd ATTRIBUTE_UNUSED;
4928 segT sec ATTRIBUTE_UNUSED;
4931 md_convert_frag_1 (fragP);
4935 /* Force truly undefined symbols to their maximum size, and generally set up
4936 the frag list to be relaxed
4939 md_estimate_size_before_relax (fragP, segment)
4940 register fragS *fragP;
4943 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4944 switch (fragP->fr_subtype)
4946 case TAB (BRANCHBWL, SZ_UNDEF):
4947 case TAB (BRABSJUNC, SZ_UNDEF):
4948 case TAB (BRABSJCOND, SZ_UNDEF):
4950 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4951 && relaxable_symbol (fragP->fr_symbol))
4953 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4955 else if (flag_short_refs)
4957 /* Symbol is undefined and we want short ref. */
4958 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4962 /* Symbol is still undefined. Make it LONG. */
4963 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4968 case TAB (BRANCHBW, SZ_UNDEF):
4970 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4971 && relaxable_symbol (fragP->fr_symbol))
4973 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4977 /* Symbol is undefined and we don't have long branches. */
4978 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4983 case TAB (FBRANCH, SZ_UNDEF):
4984 case TAB (DBCCLBR, SZ_UNDEF):
4985 case TAB (DBCCABSJ, SZ_UNDEF):
4986 case TAB (PCREL1632, SZ_UNDEF):
4988 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4989 && relaxable_symbol (fragP->fr_symbol))
4992 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4996 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5001 case TAB (PCINDEX, SZ_UNDEF):
5002 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5003 && relaxable_symbol (fragP->fr_symbol)))
5005 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5009 fragP->fr_subtype = TAB (PCINDEX, LONG);
5013 case TAB (ABSTOPCREL, SZ_UNDEF):
5015 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5016 && relaxable_symbol (fragP->fr_symbol)))
5018 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5022 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5031 /* Now that SZ_UNDEF are taken care of, check others. */
5032 switch (fragP->fr_subtype)
5034 case TAB (BRANCHBWL, BYTE):
5035 case TAB (BRABSJUNC, BYTE):
5036 case TAB (BRABSJCOND, BYTE):
5037 case TAB (BRANCHBW, BYTE):
5038 /* We can't do a short jump to the next instruction, so in that
5039 case we force word mode. If the symbol is at the start of a
5040 frag, and it is the next frag with any data in it (usually
5041 this is just the next frag, but assembler listings may
5042 introduce empty frags), we must use word mode. */
5043 if (fragP->fr_symbol)
5047 sym_frag = symbol_get_frag (fragP->fr_symbol);
5048 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5052 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5056 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5063 return md_relax_table[fragP->fr_subtype].rlx_length;
5066 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5067 /* the bit-field entries in the relocation_info struct plays hell
5068 with the byte-order problems of cross-assembly. So as a hack,
5069 I added this mach. dependent ri twiddler. Ugly, but it gets
5071 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5072 are symbolnum, most sig. byte first. Last byte is broken up with
5073 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5074 nibble as nuthin. (on Sun 3 at least) */
5075 /* Translate the internal relocation information into target-specific
5079 md_ri_to_chars (the_bytes, ri)
5081 struct reloc_info_generic *ri;
5084 md_number_to_chars (the_bytes, ri->r_address, 4);
5085 /* Now the fun stuff. */
5086 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5087 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5088 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5089 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
5090 ((ri->r_extern << 4) & 0x10));
5095 #ifndef BFD_ASSEMBLER
5097 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5100 relax_addressT segment_address_in_file;
5103 * In: length of relocation (or of address) in chars: 1, 2 or 4.
5104 * Out: GNU LD relocation length code: 0, 1, or 2.
5107 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
5110 know (fixP->fx_addsy != NULL);
5112 md_number_to_chars (where,
5113 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
5116 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5117 ? S_GET_TYPE (fixP->fx_addsy)
5118 : fixP->fx_addsy->sy_number);
5120 where[4] = (r_symbolnum >> 16) & 0x0ff;
5121 where[5] = (r_symbolnum >> 8) & 0x0ff;
5122 where[6] = r_symbolnum & 0x0ff;
5123 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
5124 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
5128 #endif /* OBJ_AOUT or OBJ_BOUT */
5130 #ifndef WORKING_DOT_WORD
5131 const int md_short_jump_size = 4;
5132 const int md_long_jump_size = 6;
5135 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5137 addressT from_addr, to_addr;
5138 fragS *frag ATTRIBUTE_UNUSED;
5139 symbolS *to_symbol ATTRIBUTE_UNUSED;
5143 offset = to_addr - (from_addr + 2);
5145 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5146 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5150 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5152 addressT from_addr, to_addr;
5158 if (!HAVE_LONG_BRANCH (current_architecture))
5160 if (flag_keep_pcrel)
5161 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5162 offset = to_addr - S_GET_VALUE (to_symbol);
5163 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5164 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5165 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5170 offset = to_addr - (from_addr + 2);
5171 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5172 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5178 /* Different values of OK tell what its OK to return. Things that
5179 aren't OK are an error (what a shock, no?)
5182 10: Absolute 1:8 only
5183 20: Absolute 0:7 only
5184 30: absolute 0:15 only
5185 40: Absolute 0:31 only
5186 50: absolute 0:127 only
5187 55: absolute -64:63 only
5188 60: absolute -128:127 only
5189 70: absolute 0:4095 only
5190 80: absolute -1, 1:7 only
5195 struct m68k_exp *exp;
5198 if (exp->exp.X_op == O_absent)
5200 /* Do the same thing the VAX asm does. */
5201 op (exp) = O_constant;
5207 as_warn (_("expression out of range: defaulting to 1"));
5211 else if (exp->exp.X_op == O_constant)
5216 if (offs (exp) < 1 || offs (exp) > 8)
5218 as_warn (_("expression out of range: defaulting to 1"));
5223 if (offs (exp) < 0 || offs (exp) > 7)
5227 if (offs (exp) < 0 || offs (exp) > 15)
5231 if (offs (exp) < 0 || offs (exp) > 32)
5235 if (offs (exp) < 0 || offs (exp) > 127)
5239 if (offs (exp) < -64 || offs (exp) > 63)
5243 if (offs (exp) < -128 || offs (exp) > 127)
5247 if (offs (exp) < 0 || offs (exp) > 4095)
5250 as_warn (_("expression out of range: defaulting to 0"));
5259 as_warn (_("expression out of range: defaulting to 1"));
5267 else if (exp->exp.X_op == O_big)
5269 if (offs (exp) <= 0 /* flonum. */
5270 && (ok == 90 /* no bignums */
5271 || (ok > 10 /* Small-int ranges including 0 ok. */
5272 /* If we have a flonum zero, a zero integer should
5273 do as well (e.g., in moveq). */
5274 && generic_floating_point_number.exponent == 0
5275 && generic_floating_point_number.low[0] == 0)))
5277 /* HACK! Turn it into a long. */
5278 LITTLENUM_TYPE words[6];
5280 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5281 op (exp) = O_constant;
5284 offs (exp) = words[1] | (words[0] << 16);
5288 op (exp) = O_constant;
5291 offs (exp) = (ok == 10) ? 1 : 0;
5292 as_warn (_("Can't deal with expression; defaulting to %ld"),
5298 if (ok >= 10 && ok <= 80)
5300 op (exp) = O_constant;
5303 offs (exp) = (ok == 10) ? 1 : 0;
5304 as_warn (_("Can't deal with expression; defaulting to %ld"),
5309 if (exp->size != SIZE_UNSPEC)
5317 if (!isbyte (offs (exp)))
5318 as_warn (_("expression doesn't fit in BYTE"));
5321 if (!isword (offs (exp)))
5322 as_warn (_("expression doesn't fit in WORD"));
5330 /* These are the back-ends for the various machine dependent pseudo-ops. */
5334 int ignore ATTRIBUTE_UNUSED;
5336 subseg_set (data_section, 1);
5337 demand_empty_rest_of_line ();
5342 int ignore ATTRIBUTE_UNUSED;
5344 subseg_set (data_section, 2);
5345 demand_empty_rest_of_line ();
5350 int ignore ATTRIBUTE_UNUSED;
5352 /* We don't support putting frags in the BSS segment, we fake it
5353 by marking in_bss, then looking at s_skip for clues. */
5355 subseg_set (bss_section, 0);
5356 demand_empty_rest_of_line ();
5361 int ignore ATTRIBUTE_UNUSED;
5364 register long temp_fill;
5366 temp = 1; /* JF should be 2? */
5367 temp_fill = get_absolute_expression ();
5368 if (!need_pass_2) /* Never make frag if expect extra pass. */
5369 frag_align (temp, (int) temp_fill, 0);
5370 demand_empty_rest_of_line ();
5371 record_alignment (now_seg, temp);
5376 int ignore ATTRIBUTE_UNUSED;
5378 demand_empty_rest_of_line ();
5381 /* Pseudo-ops handled for MRI compatibility. */
5383 /* This function returns non-zero if the argument is a conditional
5384 pseudo-op. This is called when checking whether a pending
5385 alignment is needed. */
5388 m68k_conditional_pseudoop (pop)
5391 return (pop->poc_handler == s_mri_if
5392 || pop->poc_handler == s_mri_else);
5395 /* Handle an MRI style chip specification. */
5404 s = input_line_pointer;
5405 /* We can't use get_symbol_end since the processor names are not proper
5407 while (is_part_of_name (c = *input_line_pointer++))
5409 *--input_line_pointer = 0;
5410 for (i = 0; i < n_archs; i++)
5411 if (strcasecmp (s, archs[i].name) == 0)
5415 as_bad (_("%s: unrecognized processor name"), s);
5416 *input_line_pointer = c;
5417 ignore_rest_of_line ();
5420 *input_line_pointer = c;
5422 if (*input_line_pointer == '/')
5423 current_architecture = 0;
5425 current_architecture &= m68881 | m68851;
5426 current_architecture |= archs[i].arch;
5427 current_chip |= archs[i].chip;
5429 while (*input_line_pointer == '/')
5431 ++input_line_pointer;
5432 s = input_line_pointer;
5433 /* We can't use get_symbol_end since the processor names are not
5435 while (is_part_of_name (c = *input_line_pointer++))
5437 *--input_line_pointer = 0;
5438 if (strcmp (s, "68881") == 0)
5439 current_architecture |= m68881;
5440 else if (strcmp (s, "68851") == 0)
5441 current_architecture |= m68851;
5442 *input_line_pointer = c;
5445 /* Update info about available control registers. */
5446 select_control_regs ();
5449 /* The MRI CHIP pseudo-op. */
5453 int ignore ATTRIBUTE_UNUSED;
5459 stop = mri_comment_field (&stopc);
5462 mri_comment_end (stop, stopc);
5463 demand_empty_rest_of_line ();
5466 /* The MRI FOPT pseudo-op. */
5470 int ignore ATTRIBUTE_UNUSED;
5474 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5478 input_line_pointer += 3;
5479 temp = get_absolute_expression ();
5480 if (temp < 0 || temp > 7)
5481 as_bad (_("bad coprocessor id"));
5483 m68k_float_copnum = COP0 + temp;
5487 as_bad (_("unrecognized fopt option"));
5488 ignore_rest_of_line ();
5492 demand_empty_rest_of_line ();
5495 /* The structure used to handle the MRI OPT pseudo-op. */
5499 /* The name of the option. */
5502 /* If this is not NULL, just call this function. The first argument
5503 is the ARG field of this structure, the second argument is
5504 whether the option was negated. */
5505 void (*pfn) PARAMS ((int arg, int on));
5507 /* If this is not NULL, and the PFN field is NULL, set the variable
5508 this points to. Set it to the ARG field if the option was not
5509 negated, and the NOTARG field otherwise. */
5512 /* The value to pass to PFN or to assign to *PVAR. */
5515 /* The value to assign to *PVAR if the option is negated. If PFN is
5516 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5517 the option may not be negated. */
5521 /* The table used to handle the MRI OPT pseudo-op. */
5523 static void skip_to_comma PARAMS ((int, int));
5524 static void opt_nest PARAMS ((int, int));
5525 static void opt_chip PARAMS ((int, int));
5526 static void opt_list PARAMS ((int, int));
5527 static void opt_list_symbols PARAMS ((int, int));
5529 static const struct opt_action opt_table[] =
5531 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5533 /* We do relaxing, so there is little use for these options. */
5534 { "b", 0, 0, 0, 0 },
5535 { "brs", 0, 0, 0, 0 },
5536 { "brb", 0, 0, 0, 0 },
5537 { "brl", 0, 0, 0, 0 },
5538 { "brw", 0, 0, 0, 0 },
5540 { "c", 0, 0, 0, 0 },
5541 { "cex", 0, 0, 0, 0 },
5542 { "case", 0, &symbols_case_sensitive, 1, 0 },
5543 { "cl", 0, 0, 0, 0 },
5544 { "cre", 0, 0, 0, 0 },
5545 { "d", 0, &flag_keep_locals, 1, 0 },
5546 { "e", 0, 0, 0, 0 },
5547 { "f", 0, &flag_short_refs, 1, 0 },
5548 { "frs", 0, &flag_short_refs, 1, 0 },
5549 { "frl", 0, &flag_short_refs, 0, 1 },
5550 { "g", 0, 0, 0, 0 },
5551 { "i", 0, 0, 0, 0 },
5552 { "m", 0, 0, 0, 0 },
5553 { "mex", 0, 0, 0, 0 },
5554 { "mc", 0, 0, 0, 0 },
5555 { "md", 0, 0, 0, 0 },
5556 { "nest", opt_nest, 0, 0, 0 },
5557 { "next", skip_to_comma, 0, 0, 0 },
5558 { "o", 0, 0, 0, 0 },
5559 { "old", 0, 0, 0, 0 },
5560 { "op", skip_to_comma, 0, 0, 0 },
5561 { "pco", 0, 0, 0, 0 },
5562 { "p", opt_chip, 0, 0, 0 },
5563 { "pcr", 0, 0, 0, 0 },
5564 { "pcs", 0, 0, 0, 0 },
5565 { "r", 0, 0, 0, 0 },
5566 { "quick", 0, &m68k_quick, 1, 0 },
5567 { "rel32", 0, &m68k_rel32, 1, 0 },
5568 { "s", opt_list, 0, 0, 0 },
5569 { "t", opt_list_symbols, 0, 0, 0 },
5570 { "w", 0, &flag_no_warnings, 0, 1 },
5574 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5576 /* The MRI OPT pseudo-op. */
5580 int ignore ATTRIBUTE_UNUSED;
5588 const struct opt_action *o;
5593 if (*input_line_pointer == '-')
5595 ++input_line_pointer;
5598 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5600 input_line_pointer += 2;
5604 s = input_line_pointer;
5605 c = get_symbol_end ();
5607 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5609 if (strcasecmp (s, o->name) == 0)
5613 /* Restore input_line_pointer now in case the option
5615 *input_line_pointer = c;
5616 (*o->pfn) (o->arg, t);
5618 else if (o->pvar != NULL)
5620 if (! t && o->arg == o->notarg)
5621 as_bad (_("option `%s' may not be negated"), s);
5622 *input_line_pointer = c;
5623 *o->pvar = t ? o->arg : o->notarg;
5626 *input_line_pointer = c;
5632 as_bad (_("option `%s' not recognized"), s);
5633 *input_line_pointer = c;
5636 while (*input_line_pointer++ == ',');
5638 /* Move back to terminating character. */
5639 --input_line_pointer;
5640 demand_empty_rest_of_line ();
5643 /* Skip ahead to a comma. This is used for OPT options which we do
5644 not support and which take arguments. */
5647 skip_to_comma (arg, on)
5648 int arg ATTRIBUTE_UNUSED;
5649 int on ATTRIBUTE_UNUSED;
5651 while (*input_line_pointer != ','
5652 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5653 ++input_line_pointer;
5656 /* Handle the OPT NEST=depth option. */
5660 int arg ATTRIBUTE_UNUSED;
5661 int on ATTRIBUTE_UNUSED;
5663 if (*input_line_pointer != '=')
5665 as_bad (_("bad format of OPT NEST=depth"));
5669 ++input_line_pointer;
5670 max_macro_nest = get_absolute_expression ();
5673 /* Handle the OPT P=chip option. */
5677 int arg ATTRIBUTE_UNUSED;
5678 int on ATTRIBUTE_UNUSED;
5680 if (*input_line_pointer != '=')
5682 /* This is just OPT P, which we do not support. */
5686 ++input_line_pointer;
5690 /* Handle the OPT S option. */
5694 int arg ATTRIBUTE_UNUSED;
5700 /* Handle the OPT T option. */
5703 opt_list_symbols (arg, on)
5704 int arg ATTRIBUTE_UNUSED;
5708 listing |= LISTING_SYMBOLS;
5710 listing &= ~LISTING_SYMBOLS;
5713 /* Handle the MRI REG pseudo-op. */
5717 int ignore ATTRIBUTE_UNUSED;
5726 if (line_label == NULL)
5728 as_bad (_("missing label"));
5729 ignore_rest_of_line ();
5734 stop = mri_comment_field (&stopc);
5738 s = input_line_pointer;
5739 while (ISALNUM (*input_line_pointer)
5740 #ifdef REGISTER_PREFIX
5741 || *input_line_pointer == REGISTER_PREFIX
5743 || *input_line_pointer == '/'
5744 || *input_line_pointer == '-')
5745 ++input_line_pointer;
5746 c = *input_line_pointer;
5747 *input_line_pointer = '\0';
5749 if (m68k_ip_op (s, &rop) != 0)
5751 if (rop.error == NULL)
5752 as_bad (_("bad register list"));
5754 as_bad (_("bad register list: %s"), rop.error);
5755 *input_line_pointer = c;
5756 ignore_rest_of_line ();
5760 *input_line_pointer = c;
5762 if (rop.mode == REGLST)
5764 else if (rop.mode == DREG)
5765 mask = 1 << (rop.reg - DATA0);
5766 else if (rop.mode == AREG)
5767 mask = 1 << (rop.reg - ADDR0 + 8);
5768 else if (rop.mode == FPREG)
5769 mask = 1 << (rop.reg - FP0 + 16);
5770 else if (rop.mode == CONTROL
5773 else if (rop.mode == CONTROL
5776 else if (rop.mode == CONTROL
5781 as_bad (_("bad register list"));
5782 ignore_rest_of_line ();
5786 S_SET_SEGMENT (line_label, reg_section);
5787 S_SET_VALUE (line_label, ~mask);
5788 symbol_set_frag (line_label, &zero_address_frag);
5791 mri_comment_end (stop, stopc);
5793 demand_empty_rest_of_line ();
5796 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5800 struct save_opts *next;
5802 int symbols_case_sensitive;
5811 /* FIXME: We don't save OPT S. */
5814 /* This variable holds the stack of saved options. */
5816 static struct save_opts *save_stack;
5818 /* The MRI SAVE pseudo-op. */
5822 int ignore ATTRIBUTE_UNUSED;
5824 struct save_opts *s;
5826 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5827 s->abspcadd = m68k_abspcadd;
5828 s->symbols_case_sensitive = symbols_case_sensitive;
5829 s->keep_locals = flag_keep_locals;
5830 s->short_refs = flag_short_refs;
5831 s->architecture = current_architecture;
5832 s->chip = current_chip;
5833 s->quick = m68k_quick;
5834 s->rel32 = m68k_rel32;
5835 s->listing = listing;
5836 s->no_warnings = flag_no_warnings;
5838 s->next = save_stack;
5841 demand_empty_rest_of_line ();
5844 /* The MRI RESTORE pseudo-op. */
5848 int ignore ATTRIBUTE_UNUSED;
5850 struct save_opts *s;
5852 if (save_stack == NULL)
5854 as_bad (_("restore without save"));
5855 ignore_rest_of_line ();
5860 save_stack = s->next;
5862 m68k_abspcadd = s->abspcadd;
5863 symbols_case_sensitive = s->symbols_case_sensitive;
5864 flag_keep_locals = s->keep_locals;
5865 flag_short_refs = s->short_refs;
5866 current_architecture = s->architecture;
5867 current_chip = s->chip;
5868 m68k_quick = s->quick;
5869 m68k_rel32 = s->rel32;
5870 listing = s->listing;
5871 flag_no_warnings = s->no_warnings;
5875 demand_empty_rest_of_line ();
5878 /* Types of MRI structured control directives. */
5880 enum mri_control_type
5888 /* This structure is used to stack the MRI structured control
5891 struct mri_control_info
5893 /* The directive within which this one is enclosed. */
5894 struct mri_control_info *outer;
5896 /* The type of directive. */
5897 enum mri_control_type type;
5899 /* Whether an ELSE has been in an IF. */
5902 /* The add or sub statement at the end of a FOR. */
5905 /* The label of the top of a FOR or REPEAT loop. */
5908 /* The label to jump to for the next iteration, or the else
5909 expression of a conditional. */
5912 /* The label to jump to to break out of the loop, or the label past
5913 the end of a conditional. */
5917 /* The stack of MRI structured control directives. */
5919 static struct mri_control_info *mri_control_stack;
5921 /* The current MRI structured control directive index number, used to
5922 generate label names. */
5924 static int mri_control_index;
5926 /* Some function prototypes. */
5928 static void mri_assemble PARAMS ((char *));
5929 static char *mri_control_label PARAMS ((void));
5930 static struct mri_control_info *push_mri_control
5931 PARAMS ((enum mri_control_type));
5932 static void pop_mri_control PARAMS ((void));
5933 static int parse_mri_condition PARAMS ((int *));
5934 static int parse_mri_control_operand
5935 PARAMS ((int *, char **, char **, char **, char **));
5936 static int swap_mri_condition PARAMS ((int));
5937 static int reverse_mri_condition PARAMS ((int));
5938 static void build_mri_control_operand
5939 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5940 const char *, int));
5941 static void parse_mri_control_expression
5942 PARAMS ((char *, int, const char *, const char *, int));
5944 /* Assemble an instruction for an MRI structured control directive. */
5952 /* md_assemble expects the opcode to be in lower case. */
5953 for (s = str; *s != ' ' && *s != '\0'; s++)
5959 /* Generate a new MRI label structured control directive label name. */
5962 mri_control_label ()
5966 n = (char *) xmalloc (20);
5967 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5968 ++mri_control_index;
5972 /* Create a new MRI structured control directive. */
5974 static struct mri_control_info *
5975 push_mri_control (type)
5976 enum mri_control_type type;
5978 struct mri_control_info *n;
5980 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5984 if (type == mri_if || type == mri_while)
5987 n->top = mri_control_label ();
5988 n->next = mri_control_label ();
5989 n->bottom = mri_control_label ();
5991 n->outer = mri_control_stack;
5992 mri_control_stack = n;
5997 /* Pop off the stack of MRI structured control directives. */
6002 struct mri_control_info *n;
6004 n = mri_control_stack;
6005 mri_control_stack = n->outer;
6013 /* Recognize a condition code in an MRI structured control expression. */
6016 parse_mri_condition (pcc)
6021 know (*input_line_pointer == '<');
6023 ++input_line_pointer;
6024 c1 = *input_line_pointer++;
6025 c2 = *input_line_pointer++;
6027 if (*input_line_pointer != '>')
6029 as_bad (_("syntax error in structured control directive"));
6033 ++input_line_pointer;
6039 *pcc = (c1 << 8) | c2;
6044 /* Parse a single operand in an MRI structured control expression. */
6047 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
6064 if (*input_line_pointer == '<')
6066 /* It's just a condition code. */
6067 return parse_mri_condition (pcc);
6070 /* Look ahead for the condition code. */
6071 for (s = input_line_pointer; *s != '\0'; ++s)
6073 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6078 as_bad (_("missing condition code in structured control directive"));
6082 *leftstart = input_line_pointer;
6084 if (*leftstop > *leftstart
6085 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6088 input_line_pointer = s;
6089 if (! parse_mri_condition (pcc))
6092 /* Look ahead for AND or OR or end of line. */
6093 for (s = input_line_pointer; *s != '\0'; ++s)
6095 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6096 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6098 if ((s == input_line_pointer
6101 && ((strncasecmp (s, "AND", 3) == 0
6102 && (s[3] == '.' || ! is_part_of_name (s[3])))
6103 || (strncasecmp (s, "OR", 2) == 0
6104 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6108 *rightstart = input_line_pointer;
6110 if (*rightstop > *rightstart
6111 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6114 input_line_pointer = s;
6119 #define MCC(b1, b2) (((b1) << 8) | (b2))
6121 /* Swap the sense of a condition. This changes the condition so that
6122 it generates the same result when the operands are swapped. */
6125 swap_mri_condition (cc)
6130 case MCC ('h', 'i'): return MCC ('c', 's');
6131 case MCC ('l', 's'): return MCC ('c', 'c');
6132 /* <HS> is an alias for <CC>. */
6133 case MCC ('h', 's'):
6134 case MCC ('c', 'c'): return MCC ('l', 's');
6135 /* <LO> is an alias for <CS>. */
6136 case MCC ('l', 'o'):
6137 case MCC ('c', 's'): return MCC ('h', 'i');
6138 case MCC ('p', 'l'): return MCC ('m', 'i');
6139 case MCC ('m', 'i'): return MCC ('p', 'l');
6140 case MCC ('g', 'e'): return MCC ('l', 'e');
6141 case MCC ('l', 't'): return MCC ('g', 't');
6142 case MCC ('g', 't'): return MCC ('l', 't');
6143 case MCC ('l', 'e'): return MCC ('g', 'e');
6144 /* Issue a warning for conditions we can not swap. */
6145 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6146 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6147 case MCC ('v', 'c'):
6148 case MCC ('v', 's'):
6150 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6151 (char) (cc >> 8), (char) (cc));
6157 /* Reverse the sense of a condition. */
6160 reverse_mri_condition (cc)
6165 case MCC ('h', 'i'): return MCC ('l', 's');
6166 case MCC ('l', 's'): return MCC ('h', 'i');
6167 /* <HS> is an alias for <CC> */
6168 case MCC ('h', 's'): return MCC ('l', 'o');
6169 case MCC ('c', 'c'): return MCC ('c', 's');
6170 /* <LO> is an alias for <CS> */
6171 case MCC ('l', 'o'): return MCC ('h', 's');
6172 case MCC ('c', 's'): return MCC ('c', 'c');
6173 case MCC ('n', 'e'): return MCC ('e', 'q');
6174 case MCC ('e', 'q'): return MCC ('n', 'e');
6175 case MCC ('v', 'c'): return MCC ('v', 's');
6176 case MCC ('v', 's'): return MCC ('v', 'c');
6177 case MCC ('p', 'l'): return MCC ('m', 'i');
6178 case MCC ('m', 'i'): return MCC ('p', 'l');
6179 case MCC ('g', 'e'): return MCC ('l', 't');
6180 case MCC ('l', 't'): return MCC ('g', 'e');
6181 case MCC ('g', 't'): return MCC ('l', 'e');
6182 case MCC ('l', 'e'): return MCC ('g', 't');
6187 /* Build an MRI structured control expression. This generates test
6188 and branch instructions. It goes to TRUELAB if the condition is
6189 true, and to FALSELAB if the condition is false. Exactly one of
6190 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6191 is the size qualifier for the expression. EXTENT is the size to
6192 use for the branch. */
6195 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6196 rightstop, truelab, falselab, extent)
6203 const char *truelab;
6204 const char *falselab;
6210 if (leftstart != NULL)
6212 struct m68k_op leftop, rightop;
6215 /* Swap the compare operands, if necessary, to produce a legal
6216 m68k compare instruction. Comparing a register operand with
6217 a non-register operand requires the register to be on the
6218 right (cmp, cmpa). Comparing an immediate value with
6219 anything requires the immediate value to be on the left
6224 (void) m68k_ip_op (leftstart, &leftop);
6229 (void) m68k_ip_op (rightstart, &rightop);
6232 if (rightop.mode == IMMED
6233 || ((leftop.mode == DREG || leftop.mode == AREG)
6234 && (rightop.mode != DREG && rightop.mode != AREG)))
6238 /* Correct conditional handling:
6239 if #1 <lt> d0 then ;means if (1 < d0)
6245 cmp #1,d0 if we do *not* swap the operands
6246 bgt true we need the swapped condition!
6253 leftstart = rightstart;
6256 leftstop = rightstop;
6261 cc = swap_mri_condition (cc);
6265 if (truelab == NULL)
6267 cc = reverse_mri_condition (cc);
6271 if (leftstart != NULL)
6273 buf = (char *) xmalloc (20
6274 + (leftstop - leftstart)
6275 + (rightstop - rightstart));
6281 *s++ = TOLOWER (qual);
6283 memcpy (s, leftstart, leftstop - leftstart);
6284 s += leftstop - leftstart;
6286 memcpy (s, rightstart, rightstop - rightstart);
6287 s += rightstop - rightstart;
6293 buf = (char *) xmalloc (20 + strlen (truelab));
6299 *s++ = TOLOWER (extent);
6301 strcpy (s, truelab);
6306 /* Parse an MRI structured control expression. This generates test
6307 and branch instructions. STOP is where the expression ends. It
6308 goes to TRUELAB if the condition is true, and to FALSELAB if the
6309 condition is false. Exactly one of TRUELAB and FALSELAB will be
6310 NULL, meaning to fall through. QUAL is the size qualifier for the
6311 expression. EXTENT is the size to use for the branch. */
6314 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
6317 const char *truelab;
6318 const char *falselab;
6331 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6332 &rightstart, &rightstop))
6338 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6342 if (falselab != NULL)
6345 flab = mri_control_label ();
6347 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6348 rightstop, (const char *) NULL, flab, extent);
6350 input_line_pointer += 3;
6351 if (*input_line_pointer != '.'
6352 || input_line_pointer[1] == '\0')
6356 qual = input_line_pointer[1];
6357 input_line_pointer += 2;
6360 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6361 &rightstart, &rightstop))
6367 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6368 rightstop, truelab, falselab, extent);
6370 if (falselab == NULL)
6373 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6377 if (truelab != NULL)
6380 tlab = mri_control_label ();
6382 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6383 rightstop, tlab, (const char *) NULL, extent);
6385 input_line_pointer += 2;
6386 if (*input_line_pointer != '.'
6387 || input_line_pointer[1] == '\0')
6391 qual = input_line_pointer[1];
6392 input_line_pointer += 2;
6395 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6396 &rightstart, &rightstop))
6402 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6403 rightstop, truelab, falselab, extent);
6405 if (truelab == NULL)
6410 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6411 rightstop, truelab, falselab, extent);
6415 if (input_line_pointer != stop)
6416 as_bad (_("syntax error in structured control directive"));
6419 /* Handle the MRI IF pseudo-op. This may be a structured control
6420 directive, or it may be a regular assembler conditional, depending
6429 struct mri_control_info *n;
6431 /* A structured control directive must end with THEN with an
6432 optional qualifier. */
6433 s = input_line_pointer;
6434 /* We only accept '*' as introduction of comments if preceded by white space
6435 or at first column of a line (I think this can't actually happen here?)
6436 This is important when assembling:
6437 if d0 <ne> 12(a0,d0*2) then
6438 if d0 <ne> #CONST*20 then. */
6439 while ( ! ( is_end_of_line[(unsigned char) *s]
6442 && ( s == input_line_pointer
6444 || *(s-1) == '\t'))))
6447 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6450 if (s - input_line_pointer > 1
6454 if (s - input_line_pointer < 3
6455 || strncasecmp (s - 3, "THEN", 4) != 0)
6459 as_bad (_("missing then"));
6460 ignore_rest_of_line ();
6464 /* It's a conditional. */
6469 /* Since this might be a conditional if, this pseudo-op will be
6470 called even if we are supported to be ignoring input. Double
6471 check now. Clobber *input_line_pointer so that ignore_input
6472 thinks that this is not a special pseudo-op. */
6473 c = *input_line_pointer;
6474 *input_line_pointer = 0;
6475 if (ignore_input ())
6477 *input_line_pointer = c;
6478 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6479 ++input_line_pointer;
6480 demand_empty_rest_of_line ();
6483 *input_line_pointer = c;
6485 n = push_mri_control (mri_if);
6487 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6488 n->next, s[1] == '.' ? s[2] : '\0');
6491 input_line_pointer = s + 3;
6493 input_line_pointer = s + 1;
6497 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6498 ++input_line_pointer;
6501 demand_empty_rest_of_line ();
6504 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6505 structured IF, associate the ELSE with the IF. Otherwise, assume
6506 it is a conditional else. */
6517 && (mri_control_stack == NULL
6518 || mri_control_stack->type != mri_if
6519 || mri_control_stack->else_seen))
6525 c = *input_line_pointer;
6526 *input_line_pointer = 0;
6527 if (ignore_input ())
6529 *input_line_pointer = c;
6530 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6531 ++input_line_pointer;
6532 demand_empty_rest_of_line ();
6535 *input_line_pointer = c;
6537 if (mri_control_stack == NULL
6538 || mri_control_stack->type != mri_if
6539 || mri_control_stack->else_seen)
6541 as_bad (_("else without matching if"));
6542 ignore_rest_of_line ();
6546 mri_control_stack->else_seen = 1;
6548 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6549 q[0] = TOLOWER (qual);
6551 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6555 colon (mri_control_stack->next);
6559 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6560 ++input_line_pointer;
6563 demand_empty_rest_of_line ();
6566 /* Handle the MRI ENDI pseudo-op. */
6570 int ignore ATTRIBUTE_UNUSED;
6572 if (mri_control_stack == NULL
6573 || mri_control_stack->type != mri_if)
6575 as_bad (_("endi without matching if"));
6576 ignore_rest_of_line ();
6580 /* ignore_input will not return true for ENDI, so we don't need to
6581 worry about checking it again here. */
6583 if (! mri_control_stack->else_seen)
6584 colon (mri_control_stack->next);
6585 colon (mri_control_stack->bottom);
6591 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6592 ++input_line_pointer;
6595 demand_empty_rest_of_line ();
6598 /* Handle the MRI BREAK pseudo-op. */
6601 s_mri_break (extent)
6604 struct mri_control_info *n;
6608 n = mri_control_stack;
6610 && n->type != mri_for
6611 && n->type != mri_repeat
6612 && n->type != mri_while)
6616 as_bad (_("break outside of structured loop"));
6617 ignore_rest_of_line ();
6621 buf = (char *) xmalloc (20 + strlen (n->bottom));
6622 ex[0] = TOLOWER (extent);
6624 sprintf (buf, "bra%s %s", ex, n->bottom);
6630 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6631 ++input_line_pointer;
6634 demand_empty_rest_of_line ();
6637 /* Handle the MRI NEXT pseudo-op. */
6643 struct mri_control_info *n;
6647 n = mri_control_stack;
6649 && n->type != mri_for
6650 && n->type != mri_repeat
6651 && n->type != mri_while)
6655 as_bad (_("next outside of structured loop"));
6656 ignore_rest_of_line ();
6660 buf = (char *) xmalloc (20 + strlen (n->next));
6661 ex[0] = TOLOWER (extent);
6663 sprintf (buf, "bra%s %s", ex, n->next);
6669 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6670 ++input_line_pointer;
6673 demand_empty_rest_of_line ();
6676 /* Handle the MRI FOR pseudo-op. */
6682 const char *varstart, *varstop;
6683 const char *initstart, *initstop;
6684 const char *endstart, *endstop;
6685 const char *bystart, *bystop;
6689 struct mri_control_info *n;
6695 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6699 varstart = input_line_pointer;
6701 /* Look for the '='. */
6702 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6703 && *input_line_pointer != '=')
6704 ++input_line_pointer;
6705 if (*input_line_pointer != '=')
6707 as_bad (_("missing ="));
6708 ignore_rest_of_line ();
6712 varstop = input_line_pointer;
6713 if (varstop > varstart
6714 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6717 ++input_line_pointer;
6719 initstart = input_line_pointer;
6721 /* Look for TO or DOWNTO. */
6724 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6726 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6727 && ! is_part_of_name (input_line_pointer[2]))
6729 initstop = input_line_pointer;
6730 input_line_pointer += 2;
6733 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6734 && ! is_part_of_name (input_line_pointer[6]))
6736 initstop = input_line_pointer;
6738 input_line_pointer += 6;
6741 ++input_line_pointer;
6743 if (initstop == NULL)
6745 as_bad (_("missing to or downto"));
6746 ignore_rest_of_line ();
6749 if (initstop > initstart
6750 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6754 endstart = input_line_pointer;
6756 /* Look for BY or DO. */
6759 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6761 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6762 && ! is_part_of_name (input_line_pointer[2]))
6764 endstop = input_line_pointer;
6766 input_line_pointer += 2;
6769 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6770 && (input_line_pointer[2] == '.'
6771 || ! is_part_of_name (input_line_pointer[2])))
6773 endstop = input_line_pointer;
6774 input_line_pointer += 2;
6777 ++input_line_pointer;
6779 if (endstop == NULL)
6781 as_bad (_("missing do"));
6782 ignore_rest_of_line ();
6785 if (endstop > endstart
6786 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6792 bystop = bystart + 2;
6797 bystart = input_line_pointer;
6801 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6803 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6804 && (input_line_pointer[2] == '.'
6805 || ! is_part_of_name (input_line_pointer[2])))
6807 bystop = input_line_pointer;
6808 input_line_pointer += 2;
6811 ++input_line_pointer;
6815 as_bad (_("missing do"));
6816 ignore_rest_of_line ();
6819 if (bystop > bystart
6820 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6824 if (*input_line_pointer != '.')
6828 extent = input_line_pointer[1];
6829 input_line_pointer += 2;
6832 /* We have fully parsed the FOR operands. Now build the loop. */
6833 n = push_mri_control (mri_for);
6835 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6837 /* Move init,var. */
6844 *s++ = TOLOWER (qual);
6846 memcpy (s, initstart, initstop - initstart);
6847 s += initstop - initstart;
6849 memcpy (s, varstart, varstop - varstart);
6850 s += varstop - varstart;
6862 *s++ = TOLOWER (qual);
6864 memcpy (s, endstart, endstop - endstart);
6865 s += endstop - endstart;
6867 memcpy (s, varstart, varstop - varstart);
6868 s += varstop - varstart;
6873 ex[0] = TOLOWER (extent);
6876 sprintf (buf, "blt%s %s", ex, n->bottom);
6878 sprintf (buf, "bgt%s %s", ex, n->bottom);
6881 /* Put together the add or sub instruction used by ENDF. */
6889 *s++ = TOLOWER (qual);
6891 memcpy (s, bystart, bystop - bystart);
6892 s += bystop - bystart;
6894 memcpy (s, varstart, varstop - varstart);
6895 s += varstop - varstart;
6901 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6902 ++input_line_pointer;
6905 demand_empty_rest_of_line ();
6908 /* Handle the MRI ENDF pseudo-op. */
6912 int ignore ATTRIBUTE_UNUSED;
6914 if (mri_control_stack == NULL
6915 || mri_control_stack->type != mri_for)
6917 as_bad (_("endf without for"));
6918 ignore_rest_of_line ();
6922 colon (mri_control_stack->next);
6924 mri_assemble (mri_control_stack->incr);
6926 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6927 mri_assemble (mri_control_stack->incr);
6929 free (mri_control_stack->incr);
6931 colon (mri_control_stack->bottom);
6937 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6938 ++input_line_pointer;
6941 demand_empty_rest_of_line ();
6944 /* Handle the MRI REPEAT pseudo-op. */
6947 s_mri_repeat (ignore)
6948 int ignore ATTRIBUTE_UNUSED;
6950 struct mri_control_info *n;
6952 n = push_mri_control (mri_repeat);
6956 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6957 ++input_line_pointer;
6959 demand_empty_rest_of_line ();
6962 /* Handle the MRI UNTIL pseudo-op. */
6970 if (mri_control_stack == NULL
6971 || mri_control_stack->type != mri_repeat)
6973 as_bad (_("until without repeat"));
6974 ignore_rest_of_line ();
6978 colon (mri_control_stack->next);
6980 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6983 parse_mri_control_expression (s, qual, (const char *) NULL,
6984 mri_control_stack->top, '\0');
6986 colon (mri_control_stack->bottom);
6988 input_line_pointer = s;
6994 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6995 ++input_line_pointer;
6998 demand_empty_rest_of_line ();
7001 /* Handle the MRI WHILE pseudo-op. */
7009 struct mri_control_info *n;
7011 s = input_line_pointer;
7012 /* We only accept '*' as introduction of comments if preceded by white space
7013 or at first column of a line (I think this can't actually happen here?)
7014 This is important when assembling:
7015 while d0 <ne> 12(a0,d0*2) do
7016 while d0 <ne> #CONST*20 do. */
7017 while (! (is_end_of_line[(unsigned char) *s]
7020 && (s == input_line_pointer
7022 || *(s-1) == '\t'))))
7025 while (*s == ' ' || *s == '\t')
7027 if (s - input_line_pointer > 1
7030 if (s - input_line_pointer < 2
7031 || strncasecmp (s - 1, "DO", 2) != 0)
7033 as_bad (_("missing do"));
7034 ignore_rest_of_line ();
7038 n = push_mri_control (mri_while);
7042 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7043 s[1] == '.' ? s[2] : '\0');
7045 input_line_pointer = s + 1;
7046 if (*input_line_pointer == '.')
7047 input_line_pointer += 2;
7051 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7052 ++input_line_pointer;
7055 demand_empty_rest_of_line ();
7058 /* Handle the MRI ENDW pseudo-op. */
7062 int ignore ATTRIBUTE_UNUSED;
7066 if (mri_control_stack == NULL
7067 || mri_control_stack->type != mri_while)
7069 as_bad (_("endw without while"));
7070 ignore_rest_of_line ();
7074 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7075 sprintf (buf, "bra %s", mri_control_stack->next);
7079 colon (mri_control_stack->bottom);
7085 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7086 ++input_line_pointer;
7089 demand_empty_rest_of_line ();
7094 * Invocation line includes a switch not recognized by the base assembler.
7095 * See if it's a processor-specific option. These are:
7097 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
7098 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
7099 * Select the architecture. Instructions or features not
7100 * supported by the selected architecture cause fatal
7101 * errors. More than one may be specified. The default is
7102 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
7103 * for -m68000, and -m68882 is a synonym for -m68881.
7104 * -[A]m[c]no-68851, -[A]m[c]no-68881
7105 * Don't accept 688?1 instructions. (The "c" is kind of silly,
7106 * so don't use or document it, but that's the way the parsing
7109 * -pic Indicates PIC.
7110 * -k Indicates PIC. (Sun 3 only.)
7111 * --pcrel Never turn PC-relative branches into absolute jumps.
7114 * Permit `|' to be used in expressions.
7119 const char *md_shortopts = "lSA:m:kQ:V";
7121 const char *md_shortopts = "lSA:m:k";
7124 struct option md_longopts[] = {
7125 #define OPTION_PIC (OPTION_MD_BASE)
7126 {"pic", no_argument, NULL, OPTION_PIC},
7127 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7128 {"register-prefix-optional", no_argument, NULL,
7129 OPTION_REGISTER_PREFIX_OPTIONAL},
7130 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7131 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7132 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7133 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7134 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7135 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7136 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7137 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7138 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7139 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7140 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7141 {"pcrel", no_argument, NULL, OPTION_PCREL},
7142 {NULL, no_argument, NULL, 0}
7144 size_t md_longopts_size = sizeof (md_longopts);
7147 md_parse_option (c, arg)
7153 case 'l': /* -l means keep external to 2 bit offset
7154 rather than 16 bit one. */
7155 flag_short_refs = 1;
7158 case 'S': /* -S means that jbsr's always turn into
7160 flag_long_jumps = 1;
7163 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7164 branches into absolute jumps. */
7165 flag_keep_pcrel = 1;
7171 /* Intentional fall-through. */
7174 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7178 const char *oarg = arg;
7184 if (arg[0] == 'c' && arg[1] == '6')
7187 for (i = 0; i < n_archs; i++)
7188 if (!strcmp (arg, archs[i].name))
7193 as_bad (_("unrecognized option `%s'"), oarg);
7196 arch = archs[i].arch;
7199 else if (arch == m68851)
7208 if (arg[0] == 'c' && arg[1] == '6')
7211 for (i = 0; i < n_archs; i++)
7212 if (!strcmp (arg, archs[i].name))
7214 unsigned long arch = archs[i].arch;
7215 if (cpu_of_arch (arch))
7216 /* It's a cpu spec. */
7218 current_architecture &= ~m68000up;
7219 current_architecture |= arch;
7220 current_chip |= archs[i].chip;
7222 else if (arch == m68881)
7224 current_architecture |= m68881;
7227 else if (arch == m68851)
7229 current_architecture |= m68851;
7239 as_bad (_("unrecognized architecture specification `%s'"), arg);
7248 break; /* -pic, Position Independent Code. */
7250 case OPTION_REGISTER_PREFIX_OPTIONAL:
7251 flag_reg_prefix_optional = 1;
7252 reg_prefix_optional_seen = 1;
7255 /* -V: SVR4 argument to print version ID. */
7257 print_version_id ();
7260 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7261 should be emitted or not. FIXME: Not implemented. */
7265 case OPTION_BITWISE_OR:
7270 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7272 for (s = m68k_comment_chars; *s != '\0'; s++)
7276 m68k_comment_chars = n;
7280 case OPTION_BASE_SIZE_DEFAULT_16:
7281 m68k_index_width_default = SIZE_WORD;
7284 case OPTION_BASE_SIZE_DEFAULT_32:
7285 m68k_index_width_default = SIZE_LONG;
7288 case OPTION_DISP_SIZE_DEFAULT_16:
7290 m68k_rel32_from_cmdline = 1;
7293 case OPTION_DISP_SIZE_DEFAULT_32:
7295 m68k_rel32_from_cmdline = 1;
7306 md_show_usage (stream)
7309 const char *default_cpu = TARGET_CPU;
7311 unsigned int default_arch;
7313 /* Get the canonical name for the default target CPU. */
7314 if (*default_cpu == 'm')
7316 for (i = 0; i < n_archs; i++)
7318 if (strcasecmp (default_cpu, archs[i].name) == 0)
7320 default_arch = archs[i].arch;
7321 for (i = 0; i < n_archs; i++)
7323 if (archs[i].arch == default_arch
7326 default_cpu = archs[i].name;
7333 fprintf (stream, _("\
7335 -l use 1 word for refs to undefined symbols [default 2]\n\
7336 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7337 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
7338 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
7339 -m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
7340 specify variant of 680X0 architecture [default %s]\n\
7341 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7342 target has/lacks floating-point coprocessor\n\
7343 [default yes for 68020, 68030, and cpu32]\n"),
7345 fprintf (stream, _("\
7346 -m68851 | -mno-68851\n\
7347 target has/lacks memory-management unit coprocessor\n\
7348 [default yes for 68020 and up]\n\
7349 -pic, -k generate position independent code\n\
7350 -S turn jbsr into jsr\n\
7351 --pcrel never turn PC-relative branches into absolute jumps\n\
7352 --register-prefix-optional\n\
7353 recognize register names without prefix character\n\
7354 --bitwise-or do not treat `|' as a comment character\n"));
7355 fprintf (stream, _("\
7356 --base-size-default-16 base reg without size is 16 bits\n\
7357 --base-size-default-32 base reg without size is 32 bits (default)\n\
7358 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7359 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7364 /* TEST2: Test md_assemble() */
7365 /* Warning, this routine probably doesn't work anymore. */
7369 struct m68k_it the_ins;
7377 if (!gets (buf) || !*buf)
7379 if (buf[0] == '|' || buf[1] == '.')
7381 for (cp = buf; *cp; cp++)
7386 memset (&the_ins, '\0', sizeof (the_ins));
7387 m68k_ip (&the_ins, buf);
7390 printf (_("Error %s in %s\n"), the_ins.error, buf);
7394 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7395 for (n = 0; n < the_ins.numo; n++)
7396 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7398 print_the_insn (&the_ins.opcode[0], stdout);
7399 (void) putchar ('\n');
7401 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7403 if (the_ins.operands[n].error)
7405 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7408 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7409 if (the_ins.operands[n].b_const)
7410 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7411 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7412 if (the_ins.operands[n].b_iadd)
7413 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7414 (void) putchar ('\n');
7426 while (*str && *str != ' ')
7428 if (str[-1] == ':' || str[1] == '=')
7435 /* Possible states for relaxation:
7437 0 0 branch offset byte (bra, etc)
7441 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7445 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7452 /* We have no need to default values of symbols. */
7455 md_undefined_symbol (name)
7456 char *name ATTRIBUTE_UNUSED;
7461 /* Round up a section size to the appropriate boundary. */
7463 md_section_align (segment, size)
7464 segT segment ATTRIBUTE_UNUSED;
7468 #ifdef BFD_ASSEMBLER
7469 /* For a.out, force the section size to be aligned. If we don't do
7470 this, BFD will align it for us, but it will not write out the
7471 final bytes of the section. This may be a bug in BFD, but it is
7472 easier to fix it here since that is how the other a.out targets
7476 align = bfd_get_section_alignment (stdoutput, segment);
7477 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7484 /* Exactly what point is a PC-relative offset relative TO?
7485 On the 68k, it is relative to the address of the first extension
7486 word. The difference between the addresses of the offset and the
7487 first extension word is stored in fx_pcrel_adjust. */
7489 md_pcrel_from (fixP)
7494 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7495 sign extend the value here. */
7496 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7499 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7502 #ifndef BFD_ASSEMBLER
7506 tc_coff_symbol_emit_hook (ignore)
7507 symbolS *ignore ATTRIBUTE_UNUSED;
7512 tc_coff_sizemachdep (frag)
7515 switch (frag->fr_subtype & 0x3)
7533 m68k_elf_final_processing ()
7535 /* Set file-specific flags if this is a cpu32 processor. */
7536 if (cpu_of_arch (current_architecture) & cpu32)
7537 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7538 else if ((cpu_of_arch (current_architecture) & m68000up)
7539 && !(cpu_of_arch (current_architecture) & m68020up))
7540 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
7545 tc_m68k_regname_to_dw2regnum (const char *regname)
7547 unsigned int regnum;
7548 static const char *const regnames[] =
7550 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7551 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7552 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7556 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7557 if (strcmp (regname, regnames[regnum]) == 0)
7564 tc_m68k_frame_initial_instructions (void)
7566 static int sp_regno = -1;
7569 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7571 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7572 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);