1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if defined (TE_SVR4) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
37 const char *m68k_comment_chars = "|";
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#*";
49 const char line_separator_chars[] = "";
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
63 const int md_reloc_size = 8; /* Size of relocation record */
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
77 int flag_reg_prefix_optional;
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
97 static int m68k_rel32 = 1;
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
102 /* The default width to use for an index register when using a base
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
112 struct label_line *next;
119 /* The list of labels. */
121 static struct label_line *labels;
123 /* The current label. */
125 static struct label_line *current_label;
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
138 /* Case `g' except when BCC68000 is applicable. */
140 /* Coprocessor branches. */
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
154 /* Not currently used? */
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
162 const char *m_operands;
163 unsigned long m_opcode;
167 struct m68k_incant *m_next;
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
197 #define cpu32_control_regs m68010_control_regs
199 static const enum m68k_register *control_regs;
201 /* internal form of a 68020 instruction */
205 const char *args; /* list of opcode info */
208 int numo; /* Number of shorts in opcode */
211 struct m68k_op operands[6];
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
216 int nfrag; /* Number of frags we have to produce */
219 int fragoff; /* Where in the current opcode the frag ends */
226 int nrel; /* Num of reloc strucs in use */
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
242 /* Whether this expression needs special pic relocation, and if
244 enum pic_relocation pic_reloc;
247 reloc[5]; /* Five is enough??? */
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
254 /* Macros for determining if cpu supports a specific addressing mode */
255 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
257 static struct m68k_it the_ins; /* the instruction being assembled */
259 #define op(ex) ((ex)->exp.X_op)
260 #define adds(ex) ((ex)->exp.X_add_symbol)
261 #define subs(ex) ((ex)->exp.X_op_symbol)
262 #define offs(ex) ((ex)->exp.X_add_number)
264 /* Macros for adding things to the m68k_it struct */
266 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
268 /* Like addword, but goes BEFORE general operands */
272 struct m68k_incant *opcode;
275 for(z=the_ins.numo;z>opcode->m_codenum;--z)
276 the_ins.opcode[z]=the_ins.opcode[z-1];
277 for(z=0;z<the_ins.nrel;z++)
278 the_ins.reloc[z].n+=2;
279 for (z = 0; z < the_ins.nfrag; z++)
280 the_ins.fragb[z].fragoff++;
281 the_ins.opcode[opcode->m_codenum]=w;
285 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
288 add_fix (width, exp, pc_rel, pc_fix)
290 struct m68k_exp *exp;
294 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
298 : (the_ins.numo*2)));
299 the_ins.reloc[the_ins.nrel].exp = exp->exp;
300 the_ins.reloc[the_ins.nrel].wid = width;
301 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
303 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
305 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
308 /* Cause an extra frag to be generated here, inserting up to 10 bytes
309 (that value is chosen in the frag_var call in md_assemble). TYPE
310 is the subtype of the frag to be generated; its primary type is
311 rs_machine_dependent.
313 The TYPE parameter is also used by md_convert_frag_1 and
314 md_estimate_size_before_relax. The appropriate type of fixup will
315 be emitted by md_convert_frag_1.
317 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
319 add_frag(add,off,type)
324 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
325 the_ins.fragb[the_ins.nfrag].fadd=add;
326 the_ins.fragb[the_ins.nfrag].foff=off;
327 the_ins.fragb[the_ins.nfrag++].fragty=type;
331 (op (ex) != O_constant && op (ex) != O_big)
333 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
334 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
335 static int reverse_16_bits PARAMS ((int in));
336 static int reverse_8_bits PARAMS ((int in));
337 static void install_gen_operand PARAMS ((int mode, int val));
338 static void install_operand PARAMS ((int mode, int val));
339 static void s_bss PARAMS ((int));
340 static void s_data1 PARAMS ((int));
341 static void s_data2 PARAMS ((int));
342 static void s_even PARAMS ((int));
343 static void s_proc PARAMS ((int));
344 static void mri_chip PARAMS ((void));
345 static void s_chip PARAMS ((int));
346 static void s_fopt PARAMS ((int));
347 static void s_opt PARAMS ((int));
348 static void s_reg PARAMS ((int));
349 static void s_restore PARAMS ((int));
350 static void s_save PARAMS ((int));
351 static void s_mri_if PARAMS ((int));
352 static void s_mri_else PARAMS ((int));
353 static void s_mri_endi PARAMS ((int));
354 static void s_mri_break PARAMS ((int));
355 static void s_mri_next PARAMS ((int));
356 static void s_mri_for PARAMS ((int));
357 static void s_mri_endf PARAMS ((int));
358 static void s_mri_repeat PARAMS ((int));
359 static void s_mri_until PARAMS ((int));
360 static void s_mri_while PARAMS ((int));
361 static void s_mri_endw PARAMS ((int));
363 static int current_architecture;
371 static const struct m68k_cpu archs[] = {
372 { m68000, "68000", 0 },
373 { m68010, "68010", 0 },
374 { m68020, "68020", 0 },
375 { m68030, "68030", 0 },
376 { m68040, "68040", 0 },
377 { m68060, "68060", 0 },
378 { cpu32, "cpu32", 0 },
379 { m68881, "68881", 0 },
380 { m68851, "68851", 0 },
381 { mcf5200, "5200", 0 },
382 /* Aliases (effectively, so far as gas is concerned) for the above
384 { m68020, "68k", 1 },
385 { m68000, "68302", 1 },
386 { m68000, "68008", 1 },
387 { m68000, "68ec000", 1 },
388 { m68000, "68hc000", 1 },
389 { m68000, "68hc001", 1 },
390 { m68020, "68ec020", 1 },
391 { m68030, "68ec030", 1 },
392 { m68040, "68ec040", 1 },
393 { m68060, "68ec060", 1 },
394 { cpu32, "68330", 1 },
395 { cpu32, "68331", 1 },
396 { cpu32, "68332", 1 },
397 { cpu32, "68333", 1 },
398 { cpu32, "68340", 1 },
399 { cpu32, "68360", 1 },
400 { m68881, "68882", 1 },
403 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
405 /* BCC68000 is for patching in an extra jmp instruction for long offsets
406 on the 68000. The 68000 doesn't support long branches with branchs */
408 /* This table desribes how you change sizes for the various types of variable
409 size expressions. This version only supports two kinds. */
411 /* Note that calls to frag_var need to specify the maximum expansion
412 needed; this is currently 10 bytes for DBCC. */
415 How far Forward this mode will reach:
416 How far Backward this mode will reach:
417 How many bytes this mode will add to the size of the frag
418 Which mode to go to if the offset won't fit in this one
420 relax_typeS md_relax_table[] =
422 {1, 1, 0, 0}, /* First entries aren't used */
423 {1, 1, 0, 0}, /* For no good reason except */
424 {1, 1, 0, 0}, /* that the VAX doesn't either */
427 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
428 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
432 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
433 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
437 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
438 {(32767), (-32768), 2, TAB (PCREL, LONG)},
442 {(127), (-128), 0, TAB (BCC68000, SHORT)},
443 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
444 {0, 0, 6, 0}, /* jmp long space */
447 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
448 {(32767), (-32768), 2, TAB (DBCC, LONG)},
449 {0, 0, 10, 0}, /* bra/jmp long space */
452 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
453 {32767, -32768, 2, TAB (PCLEA, LONG)},
457 /* For, e.g., jmp pcrel indexed. */
458 {125, -130, 0, TAB (PCINDEX, SHORT)},
459 {32765, -32770, 2, TAB (PCINDEX, LONG)},
464 /* These are the machine dependent pseudo-ops. These are included so
465 the assembler can work on the output from the SUN C compiler, which
469 /* This table describes all the machine specific pseudo-ops the assembler
470 has to support. The fields are:
471 pseudo-op name without dot
472 function to call to execute this pseudo-op
473 Integer arg to pass to the function
475 const pseudo_typeS md_pseudo_table[] =
477 {"data1", s_data1, 0},
478 {"data2", s_data2, 0},
481 {"skip", s_space, 0},
483 #if defined (TE_SUN3) || defined (OBJ_ELF)
484 {"align", s_align_bytes, 0},
487 {"swbeg", s_ignore, 0},
489 {"extend", float_cons, 'x'},
490 {"ldouble", float_cons, 'x'},
492 /* The following pseudo-ops are supported for MRI compatibility. */
494 {"comline", s_space, 1},
496 {"mask2", s_ignore, 0},
499 {"restore", s_restore, 0},
503 {"if.b", s_mri_if, 'b'},
504 {"if.w", s_mri_if, 'w'},
505 {"if.l", s_mri_if, 'l'},
506 {"else", s_mri_else, 0},
507 {"else.s", s_mri_else, 's'},
508 {"else.l", s_mri_else, 'l'},
509 {"endi", s_mri_endi, 0},
510 {"break", s_mri_break, 0},
511 {"break.s", s_mri_break, 's'},
512 {"break.l", s_mri_break, 'l'},
513 {"next", s_mri_next, 0},
514 {"next.s", s_mri_next, 's'},
515 {"next.l", s_mri_next, 'l'},
516 {"for", s_mri_for, 0},
517 {"for.b", s_mri_for, 'b'},
518 {"for.w", s_mri_for, 'w'},
519 {"for.l", s_mri_for, 'l'},
520 {"endf", s_mri_endf, 0},
521 {"repeat", s_mri_repeat, 0},
522 {"until", s_mri_until, 0},
523 {"until.b", s_mri_until, 'b'},
524 {"until.w", s_mri_until, 'w'},
525 {"until.l", s_mri_until, 'l'},
526 {"while", s_mri_while, 0},
527 {"while.b", s_mri_while, 'b'},
528 {"while.w", s_mri_while, 'w'},
529 {"while.l", s_mri_while, 'l'},
530 {"endw", s_mri_endw, 0},
536 /* The mote pseudo ops are put into the opcode table, since they
537 don't start with a . they look like opcodes to gas.
539 extern void obj_coff_section ();
541 CONST pseudo_typeS mote_pseudo_table[] =
554 {"xdef", s_globl, 0},
556 {"align", s_align_bytes, 0},
558 {"align", s_align_ptwo, 0},
561 {"sect", obj_coff_section, 0},
562 {"section", obj_coff_section, 0},
567 #define issbyte(x) ((x)>=-128 && (x)<=127)
568 #define isubyte(x) ((x)>=0 && (x)<=255)
569 #define issword(x) ((x)>=-32768 && (x)<=32767)
570 #define isuword(x) ((x)>=0 && (x)<=65535)
572 #define isbyte(x) ((x)>= -255 && (x)<=255)
573 #define isword(x) ((x)>=-65536 && (x)<=65535)
574 #define islong(x) (1)
576 extern char *input_line_pointer;
578 static char mklower_table[256];
579 #define mklower(c) (mklower_table[(unsigned char)(c)])
580 static char notend_table[256];
581 static char alt_notend_table[256];
583 (! (notend_table[(unsigned char) *s] \
585 && alt_notend_table[(unsigned char) s[1]])))
587 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
589 #ifdef NO_PCREL_RELOCS
592 make_pcrel_absolute(fixP, add_number)
596 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
598 /* rewrite the PC relative instructions to absolute address ones.
599 * these are rumoured to be faster, and the apollo linker refuses
600 * to deal with the PC relative relocations.
602 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
607 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
613 as_fatal ("Unknown PC relative instruction");
618 #endif /* NO_PCREL_RELOCS */
621 tc_coff_fix2rtype (fixP)
624 if (fixP->fx_tcbit && fixP->fx_size == 4)
625 return R_RELLONG_NEG;
626 #ifdef NO_PCREL_RELOCS
627 know (fixP->fx_pcrel == 0);
628 return (fixP->fx_size == 1 ? R_RELBYTE
629 : fixP->fx_size == 2 ? R_DIR16
632 return (fixP->fx_pcrel ?
633 (fixP->fx_size == 1 ? R_PCRBYTE :
634 fixP->fx_size == 2 ? R_PCRWORD :
636 (fixP->fx_size == 1 ? R_RELBYTE :
637 fixP->fx_size == 2 ? R_RELWORD :
646 /* Compute the relocation code for a fixup of SIZE bytes, using pc
647 relative relocation if PCREL is non-zero. PIC says whether a special
648 pic relocation was requested. */
650 static bfd_reloc_code_real_type get_reloc_code
651 PARAMS ((int, int, enum pic_relocation));
653 static bfd_reloc_code_real_type
654 get_reloc_code (size, pcrel, pic)
657 enum pic_relocation pic;
665 return BFD_RELOC_8_GOT_PCREL;
667 return BFD_RELOC_16_GOT_PCREL;
669 return BFD_RELOC_32_GOT_PCREL;
677 return BFD_RELOC_8_GOTOFF;
679 return BFD_RELOC_16_GOTOFF;
681 return BFD_RELOC_32_GOTOFF;
689 return BFD_RELOC_8_PLT_PCREL;
691 return BFD_RELOC_16_PLT_PCREL;
693 return BFD_RELOC_32_PLT_PCREL;
701 return BFD_RELOC_8_PLTOFF;
703 return BFD_RELOC_16_PLTOFF;
705 return BFD_RELOC_32_PLTOFF;
715 return BFD_RELOC_8_PCREL;
717 return BFD_RELOC_16_PCREL;
719 return BFD_RELOC_32_PCREL;
736 as_bad ("Can not do %d byte %s%srelocation", size,
737 pcrel ? "pc-relative " : "",
738 pic == pic_none ? "" : "pic ");
739 return BFD_RELOC_NONE;
742 /* Here we decide which fixups can be adjusted to make them relative
743 to the beginning of the section instead of the symbol. Basically
744 we need to make sure that the dynamic relocations are done
745 correctly, so in some cases we force the original symbol to be
748 tc_m68k_fix_adjustable (fixP)
751 /* Prevent all adjustments to global symbols. */
752 if (S_IS_EXTERNAL (fixP->fx_addsy))
755 /* adjust_reloc_syms doesn't know about the GOT */
756 switch (fixP->fx_r_type)
758 case BFD_RELOC_8_GOT_PCREL:
759 case BFD_RELOC_16_GOT_PCREL:
760 case BFD_RELOC_32_GOT_PCREL:
761 case BFD_RELOC_8_GOTOFF:
762 case BFD_RELOC_16_GOTOFF:
763 case BFD_RELOC_32_GOTOFF:
764 case BFD_RELOC_8_PLT_PCREL:
765 case BFD_RELOC_16_PLT_PCREL:
766 case BFD_RELOC_32_PLT_PCREL:
767 case BFD_RELOC_8_PLTOFF:
768 case BFD_RELOC_16_PLTOFF:
769 case BFD_RELOC_32_PLTOFF:
779 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
786 tc_gen_reloc (section, fixp)
791 bfd_reloc_code_real_type code;
796 if (fixp->fx_r_type != BFD_RELOC_NONE)
798 code = fixp->fx_r_type;
800 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
801 that fixup_segment converted a non-PC relative reloc into a
802 PC relative reloc. In such a case, we need to convert the
809 code = BFD_RELOC_8_PCREL;
812 code = BFD_RELOC_16_PCREL;
815 code = BFD_RELOC_32_PCREL;
817 case BFD_RELOC_8_PCREL:
818 case BFD_RELOC_16_PCREL:
819 case BFD_RELOC_32_PCREL:
820 case BFD_RELOC_8_GOT_PCREL:
821 case BFD_RELOC_16_GOT_PCREL:
822 case BFD_RELOC_32_GOT_PCREL:
823 case BFD_RELOC_8_GOTOFF:
824 case BFD_RELOC_16_GOTOFF:
825 case BFD_RELOC_32_GOTOFF:
826 case BFD_RELOC_8_PLT_PCREL:
827 case BFD_RELOC_16_PLT_PCREL:
828 case BFD_RELOC_32_PLT_PCREL:
829 case BFD_RELOC_8_PLTOFF:
830 case BFD_RELOC_16_PLTOFF:
831 case BFD_RELOC_32_PLTOFF:
834 as_bad_where (fixp->fx_file, fixp->fx_line,
835 "Cannot make %s relocation PC relative",
836 bfd_get_reloc_code_name (code));
842 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
843 switch (F (fixp->fx_size, fixp->fx_pcrel))
845 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
846 MAP (1, 0, BFD_RELOC_8);
847 MAP (2, 0, BFD_RELOC_16);
848 MAP (4, 0, BFD_RELOC_32);
849 MAP (1, 1, BFD_RELOC_8_PCREL);
850 MAP (2, 1, BFD_RELOC_16_PCREL);
851 MAP (4, 1, BFD_RELOC_32_PCREL);
859 reloc = (arelent *) xmalloc (sizeof (arelent));
860 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
861 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
864 reloc->addend = fixp->fx_addnumber;
869 reloc->addend = fixp->fx_addnumber;
871 reloc->addend = (section->vma
872 + (fixp->fx_pcrel_adjust == 64
873 ? -1 : fixp->fx_pcrel_adjust)
875 + md_pcrel_from (fixp));
878 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
879 assert (reloc->howto != 0);
884 #endif /* BFD_ASSEMBLER */
886 /* Handle of the OPCODE hash table. NULL means any use before
887 m68k_ip_begin() will crash. */
888 static struct hash_control *op_hash;
890 /* Assemble an m68k instruction. */
897 register struct m68k_op *opP;
898 register struct m68k_incant *opcode;
899 register const char *s;
900 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
901 char *pdot, *pdotmove;
902 enum m68k_size siz1, siz2;
906 LITTLENUM_TYPE words[6];
907 LITTLENUM_TYPE *wordp;
908 unsigned long ok_arch = 0;
910 if (*instring == ' ')
911 instring++; /* skip leading whitespace */
913 /* Scan up to end of operation-code, which MUST end in end-of-string
914 or exactly 1 space. */
916 for (p = instring; *p != '\0'; p++)
926 the_ins.error = "No operator";
930 /* p now points to the end of the opcode name, probably whitespace.
931 Make sure the name is null terminated by clobbering the
932 whitespace, look it up in the hash table, then fix it back.
933 Remove a dot, first, since the opcode tables have none. */
936 for (pdotmove = pdot; pdotmove < p; pdotmove++)
937 *pdotmove = pdotmove[1];
943 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
948 for (pdotmove = p; pdotmove > pdot; pdotmove--)
949 *pdotmove = pdotmove[-1];
956 the_ins.error = "Unknown operator";
960 /* found a legitimate opcode, start matching operands */
964 if (opcode->m_operands == 0)
966 char *old = input_line_pointer;
968 input_line_pointer = p;
969 /* Ahh - it's a motorola style psuedo op */
970 mote_pseudo_table[opcode->m_opnum].poc_handler
971 (mote_pseudo_table[opcode->m_opnum].poc_val);
972 input_line_pointer = old;
978 if (flag_mri && opcode->m_opnum == 0)
980 /* In MRI mode, random garbage is allowed after an instruction
981 which accepts no operands. */
982 the_ins.args = opcode->m_operands;
983 the_ins.numargs = opcode->m_opnum;
984 the_ins.numo = opcode->m_codenum;
985 the_ins.opcode[0] = getone (opcode);
986 the_ins.opcode[1] = gettwo (opcode);
990 for (opP = &the_ins.operands[0]; *p; opP++)
992 p = crack_operand (p, opP);
996 the_ins.error = opP->error;
1001 opsfound = opP - &the_ins.operands[0];
1003 /* This ugly hack is to support the floating pt opcodes in their
1004 standard form. Essentially, we fake a first enty of type COP#1 */
1005 if (opcode->m_operands[0] == 'I')
1009 for (n = opsfound; n > 0; --n)
1010 the_ins.operands[n] = the_ins.operands[n - 1];
1012 memset ((char *) (&the_ins.operands[0]), '\0',
1013 sizeof (the_ins.operands[0]));
1014 the_ins.operands[0].mode = CONTROL;
1015 the_ins.operands[0].reg = m68k_float_copnum;
1019 /* We've got the operands. Find an opcode that'll accept them */
1022 /* If we didn't get the right number of ops, or we have no
1023 common model with this pattern then reject this pattern. */
1025 ok_arch |= opcode->m_arch;
1026 if (opsfound != opcode->m_opnum
1027 || ((opcode->m_arch & current_architecture) == 0))
1031 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1035 /* Warning: this switch is huge! */
1036 /* I've tried to organize the cases into this order:
1037 non-alpha first, then alpha by letter. Lower-case
1038 goes directly before uppercase counterpart. */
1039 /* Code with multiple case ...: gets sorted by the lowest
1040 case ... it belongs to. I hope this makes sense. */
1164 if (opP->reg == PC || opP->reg == ZPC)
1173 if (opP->mode != IMMED)
1175 else if (s[1] == 'b'
1176 && ! isvar (&opP->disp)
1177 && (opP->disp.exp.X_op != O_constant
1178 || ! isbyte (opP->disp.exp.X_add_number)))
1180 else if (s[1] == 'B'
1181 && ! isvar (&opP->disp)
1182 && (opP->disp.exp.X_op != O_constant
1183 || ! issbyte (opP->disp.exp.X_add_number)))
1185 else if (s[1] == 'w'
1186 && ! isvar (&opP->disp)
1187 && (opP->disp.exp.X_op != O_constant
1188 || ! isword (opP->disp.exp.X_add_number)))
1190 else if (s[1] == 'W'
1191 && ! isvar (&opP->disp)
1192 && (opP->disp.exp.X_op != O_constant
1193 || ! issword (opP->disp.exp.X_add_number)))
1199 if (opP->mode != IMMED)
1204 if (opP->mode == AREG
1205 || opP->mode == CONTROL
1206 || opP->mode == FPREG
1207 || opP->mode == IMMED
1208 || opP->mode == REGLST
1209 || (opP->mode != ABSL
1211 || opP->reg == ZPC)))
1216 if (opP->mode == CONTROL
1217 || opP->mode == FPREG
1218 || opP->mode == REGLST
1219 || opP->mode == IMMED
1220 || (opP->mode != ABSL
1222 || opP->reg == ZPC)))
1250 if (opP->mode == CONTROL
1251 || opP->mode == FPREG
1252 || opP->mode == REGLST)
1257 if (opP->mode != AINC)
1262 if (opP->mode != ADEC)
1312 if (opP->reg == PC || opP->reg == ZPC)
1333 case '~': /* For now! (JF FOO is this right?) */
1355 if (opP->mode != CONTROL
1356 || (opP->reg != TT0 && opP->reg != TT1))
1361 if (opP->mode != AREG)
1366 if (opP->mode != AINDR)
1371 if (opP->mode != ABSL
1373 && strncmp (instring, "jbsr", 4) == 0))
1378 if (opP->mode != CONTROL || opP->reg != CCR)
1383 if (opP->mode != DISP
1385 || opP->reg > ADDR7)
1390 if (opP->mode != DREG)
1395 if (opP->mode != FPREG)
1400 if (opP->mode != CONTROL
1407 if (opP->mode != CONTROL
1409 || opP->reg > last_movec_reg)
1413 const enum m68k_register *rp;
1414 for (rp = control_regs; *rp; rp++)
1415 if (*rp == opP->reg)
1423 if (opP->mode != IMMED)
1429 if (opP->mode == DREG
1430 || opP->mode == AREG
1431 || opP->mode == FPREG)
1440 opP->mask = 1 << (opP->reg - DATA0);
1443 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1446 opP->mask = 1 << (opP->reg - FP0 + 16);
1454 else if (opP->mode == CONTROL)
1463 opP->mask = 1 << 24;
1466 opP->mask = 1 << 25;
1469 opP->mask = 1 << 26;
1478 else if (opP->mode == ABSL
1479 && opP->disp.size == SIZE_UNSPEC
1480 && opP->disp.exp.X_op == O_constant)
1482 /* This is what the MRI REG pseudo-op generates. */
1484 opP->mask = opP->disp.exp.X_add_number;
1486 else if (opP->mode != REGLST)
1488 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1490 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1495 if (opP->mode != IMMED)
1497 else if (opP->disp.exp.X_op != O_constant
1498 || ! issbyte (opP->disp.exp.X_add_number))
1500 else if (! m68k_quick
1501 && instring[3] != 'q'
1502 && instring[4] != 'q')
1507 if (opP->mode != DREG
1508 && opP->mode != IMMED
1509 && opP->mode != ABSL)
1514 if (opP->mode != IMMED)
1516 else if (opP->disp.exp.X_op != O_constant
1517 || opP->disp.exp.X_add_number < 1
1518 || opP->disp.exp.X_add_number > 8)
1520 else if (! m68k_quick
1521 && (strncmp (instring, "add", 3) == 0
1522 || strncmp (instring, "sub", 3) == 0)
1523 && instring[3] != 'q')
1528 if (opP->mode != DREG && opP->mode != AREG)
1533 if (opP->mode != AINDR
1534 && (opP->mode != BASE
1536 && opP->reg != ZADDR0)
1537 || opP->disp.exp.X_op != O_absent
1538 || ((opP->index.reg < DATA0
1539 || opP->index.reg > DATA7)
1540 && (opP->index.reg < ADDR0
1541 || opP->index.reg > ADDR7))
1542 || opP->index.size != SIZE_UNSPEC
1543 || opP->index.scale != 1))
1548 if (opP->mode != CONTROL
1549 || ! (opP->reg == FPI
1551 || opP->reg == FPC))
1556 if (opP->mode != CONTROL || opP->reg != SR)
1561 if (opP->mode != IMMED)
1563 else if (opP->disp.exp.X_op != O_constant
1564 || opP->disp.exp.X_add_number < 0
1565 || opP->disp.exp.X_add_number > 7)
1570 if (opP->mode != CONTROL || opP->reg != USP)
1574 /* JF these are out of order. We could put them
1575 in order if we were willing to put up with
1576 bunches of #ifdef m68851s in the code.
1578 Don't forget that you need these operands
1579 to use 68030 MMU instructions. */
1581 /* Memory addressing mode used by pflushr */
1583 if (opP->mode == CONTROL
1584 || opP->mode == FPREG
1585 || opP->mode == DREG
1586 || opP->mode == AREG
1587 || opP->mode == REGLST)
1589 /* We should accept immediate operands, but they
1590 supposedly have to be quad word, and we don't
1591 handle that. I would like to see what a Motorola
1592 assembler does before doing something here. */
1593 if (opP->mode == IMMED)
1598 if (opP->mode != CONTROL
1599 || (opP->reg != SFC && opP->reg != DFC))
1604 if (opP->mode != CONTROL || opP->reg != TC)
1609 if (opP->mode != CONTROL || opP->reg != AC)
1614 if (opP->mode != CONTROL
1617 && opP->reg != SCC))
1622 if (opP->mode != CONTROL
1628 if (opP->mode != CONTROL
1631 && opP->reg != CRP))
1636 if (opP->mode != CONTROL
1637 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1638 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1643 if (opP->mode != CONTROL || opP->reg != PSR)
1648 if (opP->mode != CONTROL || opP->reg != PCSR)
1653 if (opP->mode != CONTROL
1660 } /* not a cache specifier. */
1664 if (opP->mode != ABSL)
1670 } /* switch on type of operand */
1674 } /* for each operand */
1675 } /* if immediately wrong */
1682 opcode = opcode->m_next;
1687 && !(ok_arch & current_architecture))
1692 "invalid instruction for this architecture; needs ");
1693 cp = buf + strlen (buf);
1697 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1700 strcpy (cp, "mmu (68030 or 68851)");
1703 strcpy (cp, "68020 or higher");
1706 strcpy (cp, "68000 or higher");
1709 strcpy (cp, "68010 or higher");
1713 int got_one = 0, idx;
1714 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1717 if ((archs[idx].arch & ok_arch)
1718 && ! archs[idx].alias)
1722 strcpy (cp, " or ");
1726 strcpy (cp, archs[idx].name);
1732 cp = xmalloc (strlen (buf) + 1);
1737 the_ins.error = "operands mismatch";
1739 } /* Fell off the end */
1744 /* now assemble it */
1746 the_ins.args = opcode->m_operands;
1747 the_ins.numargs = opcode->m_opnum;
1748 the_ins.numo = opcode->m_codenum;
1749 the_ins.opcode[0] = getone (opcode);
1750 the_ins.opcode[1] = gettwo (opcode);
1752 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1754 /* This switch is a doozy.
1755 Watch the first step; its a big one! */
1782 tmpreg = 0x3c; /* 7.4 */
1783 if (strchr ("bwl", s[1]))
1784 nextword = get_num (&opP->disp, 80);
1786 nextword = get_num (&opP->disp, 0);
1787 if (isvar (&opP->disp))
1788 add_fix (s[1], &opP->disp, 0, 0);
1792 if (!isbyte (nextword))
1793 opP->error = "operand out of range";
1798 if (!isword (nextword))
1799 opP->error = "operand out of range";
1804 if (!issword (nextword))
1805 opP->error = "operand out of range";
1810 addword (nextword >> 16);
1837 /* We gotta put out some float */
1838 if (op (&opP->disp) != O_big)
1843 /* Can other cases happen here? */
1844 if (op (&opP->disp) != O_constant)
1847 val = (valueT) offs (&opP->disp);
1851 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1852 val >>= LITTLENUM_NUMBER_OF_BITS;
1856 offs (&opP->disp) = gencnt;
1858 if (offs (&opP->disp) > 0)
1860 if (offs (&opP->disp) > baseo)
1862 as_warn ("Bignum too big for %c format; truncated",
1864 offs (&opP->disp) = baseo;
1866 baseo -= offs (&opP->disp);
1869 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1870 offs (&opP->disp)--;
1875 gen_to_words (words, baseo, (long) outro);
1876 for (wordp = words; baseo--; wordp++)
1880 tmpreg = opP->reg - DATA; /* 0.dreg */
1883 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1886 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1889 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1892 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1896 nextword = get_num (&opP->disp, 80);
1899 && ! isvar (&opP->disp)
1902 opP->disp.exp.X_op = O_symbol;
1903 #ifndef BFD_ASSEMBLER
1904 opP->disp.exp.X_add_symbol = &abs_symbol;
1906 opP->disp.exp.X_add_symbol =
1907 section_symbol (absolute_section);
1911 /* Force into index mode. Hope this works */
1913 /* We do the first bit for 32-bit displacements, and the
1914 second bit for 16 bit ones. It is possible that we
1915 should make the default be WORD instead of LONG, but
1916 I think that'd break GCC, so we put up with a little
1917 inefficiency for the sake of working output. */
1919 if (!issword (nextword)
1920 || (isvar (&opP->disp)
1921 && ((opP->disp.size == SIZE_UNSPEC
1922 && flag_short_refs == 0
1923 && cpu_of_arch (current_architecture) >= m68020)
1924 || opP->disp.size == SIZE_LONG)))
1926 if (cpu_of_arch (current_architecture) < m68020)
1928 "displacement too large for this architecture; needs 68020 or higher";
1930 tmpreg = 0x3B; /* 7.3 */
1932 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1933 if (isvar (&opP->disp))
1937 if (opP->disp.size == SIZE_LONG
1939 /* If the displacement needs pic
1940 relocation it cannot be relaxed. */
1941 || opP->disp.pic_reloc != pic_none
1946 add_fix ('l', &opP->disp, 1, 2);
1950 add_frag (adds (&opP->disp),
1952 TAB (PCLEA, SZ_UNDEF));
1959 add_fix ('l', &opP->disp, 0, 0);
1964 addword (nextword >> 16);
1969 tmpreg = 0x3A; /* 7.2 */
1971 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1973 if (isvar (&opP->disp))
1977 add_fix ('w', &opP->disp, 1, 0);
1980 add_fix ('w', &opP->disp, 0, 0);
1990 baseo = get_num (&opP->disp, 80);
1991 if (opP->mode == POST || opP->mode == PRE)
1992 outro = get_num (&opP->odisp, 80);
1993 /* Figure out the `addressing mode'.
1994 Also turn on the BASE_DISABLE bit, if needed. */
1995 if (opP->reg == PC || opP->reg == ZPC)
1997 tmpreg = 0x3b; /* 7.3 */
1998 if (opP->reg == ZPC)
2001 else if (opP->reg == 0)
2004 tmpreg = 0x30; /* 6.garbage */
2006 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2009 tmpreg = 0x30 + opP->reg - ZADDR0;
2012 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2014 siz1 = opP->disp.size;
2015 if (opP->mode == POST || opP->mode == PRE)
2016 siz2 = opP->odisp.size;
2020 /* Index register stuff */
2021 if (opP->index.reg != 0
2022 && opP->index.reg >= DATA
2023 && opP->index.reg <= ADDR7)
2025 nextword |= (opP->index.reg - DATA) << 12;
2027 if (opP->index.size == SIZE_LONG
2028 || (opP->index.size == SIZE_UNSPEC
2029 && m68k_index_width_default == SIZE_LONG))
2032 if ((opP->index.scale != 1
2033 && cpu_of_arch (current_architecture) < m68020)
2034 || (opP->index.scale == 8
2035 && current_architecture == mcf5200))
2038 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2041 switch (opP->index.scale)
2058 GET US OUT OF HERE! */
2060 /* Must be INDEX, with an index register. Address
2061 register cannot be ZERO-PC, and either :b was
2062 forced, or we know it will fit. For a 68000 or
2063 68010, force this mode anyways, because the
2064 larger modes aren't supported. */
2065 if (opP->mode == BASE
2066 && ((opP->reg >= ADDR0
2067 && opP->reg <= ADDR7)
2070 if (siz1 == SIZE_BYTE
2071 || cpu_of_arch (current_architecture) < m68020
2072 || (siz1 == SIZE_UNSPEC
2073 && ! isvar (&opP->disp)
2074 && issbyte (baseo)))
2076 nextword += baseo & 0xff;
2078 if (isvar (&opP->disp))
2080 /* Do a byte relocation. If it doesn't
2081 fit (possible on m68000) let the
2082 fixup processing complain later. */
2084 add_fix ('B', &opP->disp, 1, 1);
2086 add_fix ('B', &opP->disp, 0, 0);
2088 else if (siz1 != SIZE_BYTE)
2090 if (siz1 != SIZE_UNSPEC)
2091 as_warn ("Forcing byte displacement");
2092 if (! issbyte (baseo))
2093 opP->error = "byte displacement out of range";
2098 else if (siz1 == SIZE_UNSPEC
2100 && isvar (&opP->disp)
2101 && subs (&opP->disp) == NULL
2103 /* If the displacement needs pic
2104 relocation it cannot be relaxed. */
2105 && opP->disp.pic_reloc == pic_none
2109 /* The code in md_convert_frag_1 needs to be
2110 able to adjust nextword. Call frag_grow
2111 to ensure that we have enough space in
2112 the frag obstack to make all the bytes
2115 nextword += baseo & 0xff;
2117 add_frag (adds (&opP->disp), offs (&opP->disp),
2118 TAB (PCINDEX, SZ_UNDEF));
2126 nextword |= 0x40; /* No index reg */
2127 if (opP->index.reg >= ZDATA0
2128 && opP->index.reg <= ZDATA7)
2129 nextword |= (opP->index.reg - ZDATA0) << 12;
2130 else if (opP->index.reg >= ZADDR0
2131 || opP->index.reg <= ZADDR7)
2132 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2135 /* It isn't simple. */
2137 if (cpu_of_arch (current_architecture) < m68020)
2139 "invalid operand mode for this architecture; needs 68020 or higher";
2142 /* If the guy specified a width, we assume that it is
2143 wide enough. Maybe it isn't. If so, we lose. */
2147 if (isvar (&opP->disp)
2149 : ! issword (baseo))
2154 else if (! isvar (&opP->disp) && baseo == 0)
2163 as_warn (":b not permitted; defaulting to :w");
2173 /* Figure out innner displacement stuff */
2174 if (opP->mode == POST || opP->mode == PRE)
2176 if (cpu_of_arch (current_architecture) & cpu32)
2177 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2181 if (isvar (&opP->odisp)
2183 : ! issword (outro))
2188 else if (! isvar (&opP->odisp) && outro == 0)
2197 as_warn (":b not permitted; defaulting to :w");
2206 if (opP->mode == POST
2207 && (nextword & 0x40) == 0)
2212 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2214 if (opP->reg == PC || opP->reg == ZPC)
2215 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2217 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2219 if (siz1 == SIZE_LONG)
2220 addword (baseo >> 16);
2221 if (siz1 != SIZE_UNSPEC)
2224 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2225 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2226 if (siz2 == SIZE_LONG)
2227 addword (outro >> 16);
2228 if (siz2 != SIZE_UNSPEC)
2234 nextword = get_num (&opP->disp, 80);
2235 switch (opP->disp.size)
2240 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2242 tmpreg = 0x38; /* 7.0 */
2246 /* Don't generate pc relative code on 68010 and
2248 if (isvar (&opP->disp)
2249 && !subs (&opP->disp)
2250 && adds (&opP->disp)
2252 /* If the displacement needs pic relocation it
2253 cannot be relaxed. */
2254 && opP->disp.pic_reloc == pic_none
2256 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2257 && HAVE_LONG_BRANCH(current_architecture)
2259 && !strchr ("~%&$?", s[0]))
2261 tmpreg = 0x3A; /* 7.2 */
2262 add_frag (adds (&opP->disp),
2264 TAB (PCREL, SZ_UNDEF));
2267 /* Fall through into long */
2269 if (isvar (&opP->disp))
2270 add_fix ('l', &opP->disp, 0, 0);
2272 tmpreg = 0x39;/* 7.1 mode */
2273 addword (nextword >> 16);
2277 case SIZE_WORD: /* Word */
2278 if (isvar (&opP->disp))
2279 add_fix ('w', &opP->disp, 0, 0);
2281 tmpreg = 0x38;/* 7.0 mode */
2289 as_bad ("unknown/incorrect operand");
2292 install_gen_operand (s[1], tmpreg);
2298 { /* JF: I hate floating point! */
2313 tmpreg = get_num (&opP->disp, tmpreg);
2314 if (isvar (&opP->disp))
2315 add_fix (s[1], &opP->disp, 0, 0);
2318 case 'b': /* Danger: These do no check for
2319 certain types of overflow.
2321 if (!isbyte (tmpreg))
2322 opP->error = "out of range";
2323 insop (tmpreg, opcode);
2324 if (isvar (&opP->disp))
2325 the_ins.reloc[the_ins.nrel - 1].n =
2326 (opcode->m_codenum) * 2 + 1;
2329 if (!issbyte (tmpreg))
2330 opP->error = "out of range";
2331 opcode->m_opcode |= tmpreg;
2332 if (isvar (&opP->disp))
2333 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2336 if (!isword (tmpreg))
2337 opP->error = "out of range";
2338 insop (tmpreg, opcode);
2339 if (isvar (&opP->disp))
2340 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2343 if (!issword (tmpreg))
2344 opP->error = "out of range";
2345 insop (tmpreg, opcode);
2346 if (isvar (&opP->disp))
2347 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2350 /* Because of the way insop works, we put these two out
2352 insop (tmpreg, opcode);
2353 insop (tmpreg >> 16, opcode);
2354 if (isvar (&opP->disp))
2355 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2361 install_operand (s[1], tmpreg);
2372 install_operand (s[1], opP->reg - ADDR);
2376 tmpreg = get_num (&opP->disp, 80);
2380 /* The pc_fix argument winds up in fx_pcrel_adjust,
2381 which is a char, and may therefore be unsigned. We
2382 want to pass -1, but we pass 64 instead, and convert
2383 back in md_pcrel_from. */
2384 add_fix ('B', &opP->disp, 1, 64);
2387 add_fix ('w', &opP->disp, 1, 0);
2392 if (!HAVE_LONG_BRANCH(current_architecture))
2393 as_warn ("Can't use long branches on 68000/68010/5200");
2394 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2395 add_fix ('l', &opP->disp, 1, 0);
2400 if (subs (&opP->disp)) /* We can't relax it */
2404 /* If the displacement needs pic relocation it cannot be
2406 if (opP->disp.pic_reloc != pic_none)
2410 /* This could either be a symbol, or an absolute
2411 address. No matter, the frag hacking will finger it
2412 out. Not quite: it can't switch from BRANCH to
2413 BCC68000 for the case where opnd is absolute (it
2414 needs to use the 68000 hack since no conditional abs
2416 if (( !HAVE_LONG_BRANCH(current_architecture)
2417 || (0 == adds (&opP->disp)))
2418 && (the_ins.opcode[0] >= 0x6200)
2419 && (the_ins.opcode[0] <= 0x6f00))
2420 add_frag (adds (&opP->disp), offs (&opP->disp),
2421 TAB (BCC68000, SZ_UNDEF));
2423 add_frag (adds (&opP->disp), offs (&opP->disp),
2424 TAB (ABRANCH, SZ_UNDEF));
2427 if (isvar (&opP->disp))
2430 /* check for DBcc instruction */
2431 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2433 /* size varies if patch */
2434 /* needed for long form */
2435 add_frag (adds (&opP->disp), offs (&opP->disp),
2436 TAB (DBCC, SZ_UNDEF));
2440 add_fix ('w', &opP->disp, 1, 0);
2444 case 'C': /* Fixed size LONG coproc branches */
2445 add_fix ('l', &opP->disp, 1, 0);
2449 case 'c': /* Var size Coprocesssor branches */
2450 if (subs (&opP->disp))
2452 add_fix ('l', &opP->disp, 1, 0);
2453 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2455 else if (adds (&opP->disp))
2456 add_frag (adds (&opP->disp), offs (&opP->disp),
2457 TAB (FBRANCH, SZ_UNDEF));
2460 /* add_frag((symbolS *) 0, offs(&opP->disp),
2461 TAB(FBRANCH,SHORT)); */
2462 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2463 add_fix ('l', &opP->disp, 1, 0);
2473 case 'C': /* Ignore it */
2476 case 'd': /* JF this is a kludge */
2477 install_operand ('s', opP->reg - ADDR);
2478 tmpreg = get_num (&opP->disp, 80);
2479 if (!issword (tmpreg))
2481 as_warn ("Expression out of range, using 0");
2488 install_operand (s[1], opP->reg - DATA);
2492 install_operand (s[1], opP->reg - FP0);
2496 tmpreg = opP->reg - COP0;
2497 install_operand (s[1], tmpreg);
2500 case 'J': /* JF foo */
2573 install_operand (s[1], tmpreg);
2577 tmpreg = get_num (&opP->disp, 55);
2578 install_operand (s[1], tmpreg & 0x7f);
2585 if (tmpreg & 0x7FF0000)
2586 as_bad ("Floating point register in register list");
2587 insop (reverse_16_bits (tmpreg), opcode);
2591 if (tmpreg & 0x700FFFF)
2592 as_bad ("Wrong register in floating-point reglist");
2593 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2601 if (tmpreg & 0x7FF0000)
2602 as_bad ("Floating point register in register list");
2603 insop (tmpreg, opcode);
2605 else if (s[1] == '8')
2607 if (tmpreg & 0x0FFFFFF)
2608 as_bad ("incorrect register in reglist");
2609 install_operand (s[1], tmpreg >> 24);
2613 if (tmpreg & 0x700FFFF)
2614 as_bad ("wrong register in floating-point reglist");
2616 install_operand (s[1], tmpreg >> 16);
2621 install_operand (s[1], get_num (&opP->disp, 60));
2625 tmpreg = ((opP->mode == DREG)
2626 ? 0x20 + opP->reg - DATA
2627 : (get_num (&opP->disp, 40) & 0x1F));
2628 install_operand (s[1], tmpreg);
2632 tmpreg = get_num (&opP->disp, 10);
2635 install_operand (s[1], tmpreg);
2639 /* This depends on the fact that ADDR registers are eight
2640 more than their corresponding DATA regs, so the result
2641 will have the ADDR_REG bit set */
2642 install_operand (s[1], opP->reg - DATA);
2646 if (opP->mode == AINDR)
2647 install_operand (s[1], opP->reg - DATA);
2649 install_operand (s[1], opP->index.reg - DATA);
2653 if (opP->reg == FPI)
2655 else if (opP->reg == FPS)
2657 else if (opP->reg == FPC)
2661 install_operand (s[1], tmpreg);
2664 case 'S': /* Ignore it */
2668 install_operand (s[1], get_num (&opP->disp, 30));
2671 case 'U': /* Ignore it */
2690 as_fatal ("failed sanity check");
2691 } /* switch on cache token */
2692 install_operand (s[1], tmpreg);
2695 /* JF: These are out of order, I fear. */
2708 install_operand (s[1], tmpreg);
2734 install_operand (s[1], tmpreg);
2738 if (opP->reg == VAL)
2757 install_operand (s[1], tmpreg);
2771 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2782 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2788 install_operand (s[1], tmpreg);
2791 know (opP->reg == PSR);
2794 know (opP->reg == PCSR);
2809 install_operand (s[1], tmpreg);
2812 tmpreg = get_num (&opP->disp, 20);
2813 install_operand (s[1], tmpreg);
2815 case '_': /* used only for move16 absolute 32-bit address */
2816 tmpreg = get_num (&opP->disp, 80);
2817 addword (tmpreg >> 16);
2818 addword (tmpreg & 0xFFFF);
2825 /* By the time whe get here (FINALLY) the_ins contains the complete
2826 instruction, ready to be emitted. . . */
2830 reverse_16_bits (in)
2836 static int mask[16] =
2838 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2839 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2841 for (n = 0; n < 16; n++)
2844 out |= mask[15 - n];
2847 } /* reverse_16_bits() */
2856 static int mask[8] =
2858 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2861 for (n = 0; n < 8; n++)
2867 } /* reverse_8_bits() */
2869 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2870 (that value is chosen in the frag_var call in md_assemble). TYPE
2871 is the subtype of the frag to be generated; its primary type is
2872 rs_machine_dependent.
2874 The TYPE parameter is also used by md_convert_frag_1 and
2875 md_estimate_size_before_relax. The appropriate type of fixup will
2876 be emitted by md_convert_frag_1.
2878 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2880 install_operand (mode, val)
2887 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2890 the_ins.opcode[0] |= val << 9;
2893 the_ins.opcode[1] |= val << 12;
2896 the_ins.opcode[1] |= val << 6;
2899 the_ins.opcode[1] |= val;
2902 the_ins.opcode[2] |= val << 12;
2905 the_ins.opcode[2] |= val << 6;
2908 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2909 three words long! */
2911 the_ins.opcode[2] |= val;
2914 the_ins.opcode[1] |= val << 7;
2917 the_ins.opcode[1] |= val << 10;
2921 the_ins.opcode[1] |= val << 5;
2926 the_ins.opcode[1] |= (val << 10) | (val << 7);
2929 the_ins.opcode[1] |= (val << 12) | val;
2932 the_ins.opcode[0] |= val = 0xff;
2935 the_ins.opcode[0] |= val << 9;
2938 the_ins.opcode[1] |= val;
2941 the_ins.opcode[1] |= val;
2942 the_ins.numo++; /* What a hack */
2945 the_ins.opcode[1] |= val << 4;
2953 the_ins.opcode[0] |= (val << 6);
2956 the_ins.opcode[1] = (val >> 16);
2957 the_ins.opcode[2] = val & 0xffff;
2961 as_fatal ("failed sanity check.");
2963 } /* install_operand() */
2966 install_gen_operand (mode, val)
2973 the_ins.opcode[0] |= val;
2976 /* This is a kludge!!! */
2977 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2986 the_ins.opcode[0] |= val;
2988 /* more stuff goes here */
2990 as_fatal ("failed sanity check.");
2992 } /* install_gen_operand() */
2995 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2996 * then deal with the bitfield hack.
3000 crack_operand (str, opP)
3002 register struct m68k_op *opP;
3004 register int parens;
3006 register char *beg_str;
3014 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3020 else if (*str == ')')
3024 opP->error = "Extra )";
3030 if (flag_mri && *str == '\'')
3031 inquote = ! inquote;
3033 if (!*str && parens)
3035 opP->error = "Missing )";
3040 if (m68k_ip_op (beg_str, opP) != 0)
3047 c = *++str; /* JF bitfield hack */
3052 as_bad ("Missing operand");
3057 /* This is the guts of the machine-dependent assembler. STR points to a
3058 machine dependent instruction. This function is supposed to emit
3059 the frags/bytes it assembles to.
3063 insert_reg (regname, regnum)
3070 #ifdef REGISTER_PREFIX
3071 if (!flag_reg_prefix_optional)
3073 buf[0] = REGISTER_PREFIX;
3074 strcpy (buf + 1, regname);
3079 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3080 &zero_address_frag));
3082 for (i = 0; regname[i]; i++)
3083 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3086 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3087 &zero_address_frag));
3096 static const struct init_entry init_table[] =
3151 /* control registers */
3152 { "sfc", SFC }, /* Source Function Code */
3154 { "dfc", DFC }, /* Destination Function Code */
3156 { "cacr", CACR }, /* Cache Control Register */
3157 { "caar", CAAR }, /* Cache Address Register */
3159 { "usp", USP }, /* User Stack Pointer */
3160 { "vbr", VBR }, /* Vector Base Register */
3161 { "msp", MSP }, /* Master Stack Pointer */
3162 { "isp", ISP }, /* Interrupt Stack Pointer */
3164 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3165 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3166 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3167 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3169 /* 68ec040 versions of same */
3170 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3171 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3172 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3173 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3175 /* mcf5200 versions of same. The ColdFire programmer's reference
3176 manual indicated that the order is 2,3,0,1, but Ken Rose
3177 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3178 { "acr0", ITT0 }, /* Access Control Unit 0 */
3179 { "acr1", ITT1 }, /* Access Control Unit 1 */
3180 { "acr2", DTT0 }, /* Access Control Unit 2 */
3181 { "acr3", DTT1 }, /* Access Control Unit 3 */
3183 { "tc", TC }, /* MMU Translation Control Register */
3186 { "mmusr", MMUSR }, /* MMU Status Register */
3187 { "srp", SRP }, /* User Root Pointer */
3188 { "urp", URP }, /* Supervisor Root Pointer */
3193 { "rombar", ROMBAR }, /* ROM Base Address Register */
3194 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3195 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3196 { "mbar", MBAR }, /* Module Base Address Register */
3197 /* end of control registers */
3231 /* 68ec030 versions of same */
3234 /* 68ec030 access control unit, identical to 030 MMU status reg */
3237 /* Suppressed data and address registers. */
3262 for (i = 0; init_table[i].name; i++)
3263 insert_reg (init_table[i].name, init_table[i].number);
3266 static int no_68851, no_68881;
3269 /* a.out machine type. Default to 68020. */
3270 int m68k_aout_machtype = 2;
3282 int shorts_this_frag;
3285 /* In MRI mode, the instruction and operands are separated by a
3286 space. Anything following the operands is a comment. The label
3287 has already been removed. */
3295 for (s = str; *s != '\0'; s++)
3297 if ((*s == ' ' || *s == '\t') && ! inquote)
3315 inquote = ! inquote;
3320 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3325 for (n = 0; n < the_ins.numargs; n++)
3326 if (the_ins.operands[n].error)
3328 er = the_ins.operands[n].error;
3334 as_bad ("%s -- statement `%s' ignored", er, str);
3338 /* If there is a current label, record that it marks an instruction. */
3339 if (current_label != NULL)
3341 current_label->text = 1;
3342 current_label = NULL;
3345 if (the_ins.nfrag == 0)
3347 /* No frag hacking involved; just put it out */
3348 toP = frag_more (2 * the_ins.numo);
3349 fromP = &the_ins.opcode[0];
3350 for (m = the_ins.numo; m; --m)
3352 md_number_to_chars (toP, (long) (*fromP), 2);
3356 /* put out symbol-dependent info */
3357 for (m = 0; m < the_ins.nrel; m++)
3359 switch (the_ins.reloc[m].wid)
3378 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3379 the_ins.reloc[m].wid);
3382 fixP = fix_new_exp (frag_now,
3383 ((toP - frag_now->fr_literal)
3384 - the_ins.numo * 2 + the_ins.reloc[m].n),
3386 &the_ins.reloc[m].exp,
3387 the_ins.reloc[m].pcrel,
3388 get_reloc_code (n, the_ins.reloc[m].pcrel,
3389 the_ins.reloc[m].pic_reloc));
3390 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3391 if (the_ins.reloc[m].wid == 'B')
3392 fixP->fx_signed = 1;
3397 /* There's some frag hacking */
3398 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3403 wid = 2 * the_ins.fragb[n].fragoff;
3405 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3406 toP = frag_more (wid);
3408 shorts_this_frag = 0;
3409 for (m = wid / 2; m; --m)
3411 md_number_to_chars (toP, (long) (*fromP), 2);
3416 for (m = 0; m < the_ins.nrel; m++)
3418 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3420 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3423 wid = the_ins.reloc[m].wid;
3426 the_ins.reloc[m].wid = 0;
3427 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3429 fixP = fix_new_exp (frag_now,
3430 ((toP - frag_now->fr_literal)
3431 - the_ins.numo * 2 + the_ins.reloc[m].n),
3433 &the_ins.reloc[m].exp,
3434 the_ins.reloc[m].pcrel,
3435 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3436 the_ins.reloc[m].pic_reloc));
3437 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3439 (void) frag_var (rs_machine_dependent, 10, 0,
3440 (relax_substateT) (the_ins.fragb[n].fragty),
3441 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3443 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3444 shorts_this_frag = 0;
3447 toP = frag_more (n * sizeof (short));
3450 md_number_to_chars (toP, (long) (*fromP), 2);
3456 for (m = 0; m < the_ins.nrel; m++)
3460 wid = the_ins.reloc[m].wid;
3463 the_ins.reloc[m].wid = 0;
3464 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3466 fixP = fix_new_exp (frag_now,
3467 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3468 - shorts_this_frag * 2),
3470 &the_ins.reloc[m].exp,
3471 the_ins.reloc[m].pcrel,
3472 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3473 the_ins.reloc[m].pic_reloc));
3474 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3482 * md_begin -- set up hash tables with 68000 instructions.
3483 * similar to what the vax assembler does. ---phr
3485 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3486 a copy of it at runtime, adding in the information we want but isn't
3487 there. I think it'd be better to have an awk script hack the table
3488 at compile time. Or even just xstr the table and use it as-is. But
3489 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3492 register const struct m68k_opcode *ins;
3493 register struct m68k_incant *hack, *slak;
3494 register const char *retval = 0; /* empty string, or error msg text */
3495 register unsigned int i;
3500 flag_reg_prefix_optional = 1;
3502 if (! m68k_rel32_from_cmdline)
3506 op_hash = hash_new ();
3508 obstack_begin (&robyn, 4000);
3509 for (i = 0; i < m68k_numopcodes; i++)
3511 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3514 ins = &m68k_opcodes[i];
3515 /* We *could* ignore insns that don't match our arch here
3516 but just leaving them out of the hash. */
3517 slak->m_operands = ins->args;
3518 slak->m_opnum = strlen (slak->m_operands) / 2;
3519 slak->m_arch = ins->arch;
3520 slak->m_opcode = ins->opcode;
3521 /* This is kludgey */
3522 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3523 if (i + 1 != m68k_numopcodes
3524 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3526 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3531 slak = slak->m_next;
3535 retval = hash_insert (op_hash, ins->name, (char *) hack);
3537 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3540 for (i = 0; i < m68k_numaliases; i++)
3542 const char *name = m68k_opcode_aliases[i].primary;
3543 const char *alias = m68k_opcode_aliases[i].alias;
3544 PTR val = hash_find (op_hash, name);
3546 as_fatal ("Internal Error: Can't find %s in hash table", name);
3547 retval = hash_insert (op_hash, alias, val);
3549 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3552 /* In MRI mode, all unsized branches are variable sized. Normally,
3553 they are word sized. */
3556 static struct m68k_opcode_alias mri_aliases[] =
3576 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3578 const char *name = mri_aliases[i].primary;
3579 const char *alias = mri_aliases[i].alias;
3580 PTR val = hash_find (op_hash, name);
3582 as_fatal ("Internal Error: Can't find %s in hash table", name);
3583 retval = hash_jam (op_hash, alias, val);
3585 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3589 for (i = 0; i < sizeof (mklower_table); i++)
3590 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3592 for (i = 0; i < sizeof (notend_table); i++)
3594 notend_table[i] = 0;
3595 alt_notend_table[i] = 0;
3597 notend_table[','] = 1;
3598 notend_table['{'] = 1;
3599 notend_table['}'] = 1;
3600 alt_notend_table['a'] = 1;
3601 alt_notend_table['A'] = 1;
3602 alt_notend_table['d'] = 1;
3603 alt_notend_table['D'] = 1;
3604 alt_notend_table['#'] = 1;
3605 alt_notend_table['&'] = 1;
3606 alt_notend_table['f'] = 1;
3607 alt_notend_table['F'] = 1;
3608 #ifdef REGISTER_PREFIX
3609 alt_notend_table[REGISTER_PREFIX] = 1;
3612 /* We need to put '(' in alt_notend_table to handle
3613 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3615 alt_notend_table['('] = 1;
3617 /* We need to put '@' in alt_notend_table to handle
3618 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3620 alt_notend_table['@'] = 1;
3622 /* We need to put digits in alt_notend_table to handle
3623 bfextu %d0{24:1},%d0
3625 alt_notend_table['0'] = 1;
3626 alt_notend_table['1'] = 1;
3627 alt_notend_table['2'] = 1;
3628 alt_notend_table['3'] = 1;
3629 alt_notend_table['4'] = 1;
3630 alt_notend_table['5'] = 1;
3631 alt_notend_table['6'] = 1;
3632 alt_notend_table['7'] = 1;
3633 alt_notend_table['8'] = 1;
3634 alt_notend_table['9'] = 1;
3636 #ifndef MIT_SYNTAX_ONLY
3637 /* Insert pseudo ops, these have to go into the opcode table since
3638 gas expects pseudo ops to start with a dot */
3641 while (mote_pseudo_table[n].poc_name)
3643 hack = (struct m68k_incant *)
3644 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3645 hash_insert (op_hash,
3646 mote_pseudo_table[n].poc_name, (char *) hack);
3647 hack->m_operands = 0;
3657 record_alignment (text_section, 2);
3658 record_alignment (data_section, 2);
3659 record_alignment (bss_section, 2);
3664 select_control_regs ()
3666 /* Note which set of "movec" control registers is available. */
3667 switch (cpu_of_arch (current_architecture))
3670 control_regs = m68000_control_regs;
3673 control_regs = m68010_control_regs;
3677 control_regs = m68020_control_regs;
3680 control_regs = m68040_control_regs;
3683 control_regs = m68060_control_regs;
3686 control_regs = cpu32_control_regs;
3689 control_regs = mcf5200_control_regs;
3697 m68k_init_after_args ()
3699 if (cpu_of_arch (current_architecture) == 0)
3702 const char *default_cpu = TARGET_CPU;
3704 if (*default_cpu == 'm')
3706 for (i = 0; i < n_archs; i++)
3707 if (strcasecmp (default_cpu, archs[i].name) == 0)
3711 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3712 current_architecture |= m68020;
3715 current_architecture |= archs[i].arch;
3717 /* Permit m68881 specification with all cpus; those that can't work
3718 with a coprocessor could be doing emulation. */
3719 if (current_architecture & m68851)
3721 if (current_architecture & m68040)
3723 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3726 /* What other incompatibilities could we check for? */
3728 /* Toss in some default assumptions about coprocessors. */
3730 && (cpu_of_arch (current_architecture)
3731 /* Can CPU32 have a 68881 coprocessor?? */
3732 & (m68020 | m68030 | cpu32)))
3734 current_architecture |= m68881;
3737 && (cpu_of_arch (current_architecture) & m68020up) != 0
3738 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3740 current_architecture |= m68851;
3742 if (no_68881 && (current_architecture & m68881))
3743 as_bad ("options for 68881 and no-68881 both given");
3744 if (no_68851 && (current_architecture & m68851))
3745 as_bad ("options for 68851 and no-68851 both given");
3748 /* Work out the magic number. This isn't very general. */
3749 if (current_architecture & m68000)
3750 m68k_aout_machtype = 0;
3751 else if (current_architecture & m68010)
3752 m68k_aout_machtype = 1;
3753 else if (current_architecture & m68020)
3754 m68k_aout_machtype = 2;
3756 m68k_aout_machtype = 2;
3759 /* Note which set of "movec" control registers is available. */
3760 select_control_regs ();
3762 if (cpu_of_arch (current_architecture) < m68020)
3763 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3766 /* This is called when a label is defined. */
3769 m68k_frob_label (sym)
3772 struct label_line *n;
3774 n = (struct label_line *) xmalloc (sizeof *n);
3777 as_where (&n->file, &n->line);
3783 /* This is called when a value that is not an instruction is emitted. */
3786 m68k_flush_pending_output ()
3788 current_label = NULL;
3791 /* This is called at the end of the assembly, when the final value of
3792 the label is known. We warn if this is a text symbol aligned at an
3796 m68k_frob_symbol (sym)
3799 if ((S_GET_VALUE (sym) & 1) != 0)
3801 struct label_line *l;
3803 for (l = labels; l != NULL; l = l->next)
3805 if (l->label == sym)
3808 as_warn_where (l->file, l->line,
3809 "text label `%s' aligned to odd boundary",
3817 /* This is called if we go in or out of MRI mode because of the .mri
3821 m68k_mri_mode_change (on)
3826 if (! flag_reg_prefix_optional)
3828 flag_reg_prefix_optional = 1;
3829 #ifdef REGISTER_PREFIX
3834 if (! m68k_rel32_from_cmdline)
3839 if (! reg_prefix_optional_seen)
3841 #ifdef REGISTER_PREFIX_OPTIONAL
3842 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3844 flag_reg_prefix_optional = 0;
3846 #ifdef REGISTER_PREFIX
3851 if (! m68k_rel32_from_cmdline)
3856 /* Equal to MAX_PRECISION in atof-ieee.c */
3857 #define MAX_LITTLENUMS 6
3859 /* Turn a string in input_line_pointer into a floating point constant
3860 of type type, and store the appropriate bytes in *litP. The number
3861 of LITTLENUMS emitted is stored in *sizeP . An error message is
3862 returned, or NULL on OK. */
3865 md_atof (type, litP, sizeP)
3871 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3872 LITTLENUM_TYPE *wordP;
3904 return "Bad call to MD_ATOF()";
3906 t = atof_ieee (input_line_pointer, type, words);
3908 input_line_pointer = t;
3910 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3911 for (wordP = words; prec--;)
3913 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3914 litP += sizeof (LITTLENUM_TYPE);
3920 md_number_to_chars (buf, val, n)
3925 number_to_chars_bigendian (buf, val, n);
3929 md_apply_fix_2 (fixP, val)
3933 addressT upper_limit;
3934 offsetT lower_limit;
3936 /* This is unnecessary but it convinces the native rs6000 compiler
3937 to generate the code we want. */
3938 char *buf = fixP->fx_frag->fr_literal;
3939 buf += fixP->fx_where;
3940 /* end ibm compiler workaround */
3942 if (val & 0x80000000)
3943 val |= ~(addressT)0x7fffffff;
3950 memset (buf, 0, fixP->fx_size);
3951 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3956 switch (fixP->fx_size)
3958 /* The cast to offsetT below are necessary to make code correct for
3959 machines where ints are smaller than offsetT */
3963 lower_limit = - (offsetT) 0x80;
3966 *buf++ = (val >> 8);
3968 upper_limit = 0x7fff;
3969 lower_limit = - (offsetT) 0x8000;
3972 *buf++ = (val >> 24);
3973 *buf++ = (val >> 16);
3974 *buf++ = (val >> 8);
3976 upper_limit = 0x7fffffff;
3977 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3980 BAD_CASE (fixP->fx_size);
3983 /* Fix up a negative reloc. */
3984 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3986 fixP->fx_addsy = fixP->fx_subsy;
3987 fixP->fx_subsy = NULL;
3991 /* For non-pc-relative values, it's conceivable we might get something
3992 like "0xff" for a byte field. So extend the upper part of the range
3993 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3994 so that we can do any range checking at all. */
3995 if (! fixP->fx_pcrel && ! fixP->fx_signed)
3996 upper_limit = upper_limit * 2 + 1;
3998 if ((addressT) val > upper_limit
3999 && (val > 0 || val < lower_limit))
4000 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
4002 /* A one byte PC-relative reloc means a short branch. We can't use
4003 a short branch with a value of 0 or -1, because those indicate
4004 different opcodes (branches with longer offsets). */
4006 && fixP->fx_size == 1
4007 && (fixP->fx_addsy == NULL
4008 || S_IS_DEFINED (fixP->fx_addsy))
4009 && (val == 0 || val == -1))
4010 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4013 #ifdef BFD_ASSEMBLER
4015 md_apply_fix (fixP, valp)
4019 md_apply_fix_2 (fixP, (addressT) *valp);
4023 void md_apply_fix (fixP, val)
4027 md_apply_fix_2 (fixP, (addressT) val);
4031 /* *fragP has been relaxed to its final size, and now needs to have
4032 the bytes inside it modified to conform to the new size There is UGLY
4036 md_convert_frag_1 (fragP)
4037 register fragS *fragP;
4043 /* Address in object code of the displacement. */
4044 register int object_address = fragP->fr_fix + fragP->fr_address;
4046 /* Address in gas core of the place to store the displacement. */
4047 /* This convinces the native rs6000 compiler to generate the code we
4049 register char *buffer_address = fragP->fr_literal;
4050 buffer_address += fragP->fr_fix;
4051 /* end ibm compiler workaround */
4053 /* The displacement of the address, from current location. */
4054 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4055 disp = (disp + fragP->fr_offset) - object_address;
4057 #ifdef BFD_ASSEMBLER
4058 disp += fragP->fr_symbol->sy_frag->fr_address;
4061 switch (fragP->fr_subtype)
4063 case TAB (BCC68000, BYTE):
4064 case TAB (ABRANCH, BYTE):
4065 know (issbyte (disp));
4067 as_bad ("short branch with zero offset: use :w");
4068 fragP->fr_opcode[1] = disp;
4071 case TAB (DBCC, SHORT):
4072 know (issword (disp));
4075 case TAB (BCC68000, SHORT):
4076 case TAB (ABRANCH, SHORT):
4077 know (issword (disp));
4078 fragP->fr_opcode[1] = 0x00;
4081 case TAB (ABRANCH, LONG):
4082 if (!HAVE_LONG_BRANCH(current_architecture))
4084 if (fragP->fr_opcode[0] == 0x61)
4087 fragP->fr_opcode[0] = 0x4E;
4088 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4102 else if (fragP->fr_opcode[0] == 0x60)
4104 fragP->fr_opcode[0] = 0x4E;
4105 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4106 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4107 fragP->fr_offset, 0, NO_RELOC);
4113 as_bad ("Long branch offset not supported.");
4118 fragP->fr_opcode[1] = (char) 0xff;
4122 case TAB (BCC68000, LONG):
4123 /* only Bcc 68000 instructions can come here */
4124 /* change bcc into b!cc/jmp absl long */
4125 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4126 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4128 /* JF: these used to be fr_opcode[2,3], but they may be in a
4129 different frag, in which case refering to them is a no-no.
4130 Only fr_opcode[0,1] are guaranteed to work. */
4131 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4132 *buffer_address++ = (char) 0xf9;
4133 fragP->fr_fix += 2; /* account for jmp instruction */
4134 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4135 fragP->fr_offset, 0, NO_RELOC);
4139 case TAB (DBCC, LONG):
4140 /* only DBcc 68000 instructions can come here */
4141 /* change dbcc into dbcc/jmp absl long */
4142 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4143 *buffer_address++ = 0x00; /* branch offset = 4 */
4144 *buffer_address++ = 0x04;
4145 *buffer_address++ = 0x60; /* put in bra pc+6 */
4146 *buffer_address++ = 0x06;
4147 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4148 *buffer_address++ = (char) 0xf9;
4150 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4151 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4152 fragP->fr_offset, 0, NO_RELOC);
4156 case TAB (FBRANCH, SHORT):
4157 know ((fragP->fr_opcode[1] & 0x40) == 0);
4160 case TAB (FBRANCH, LONG):
4161 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4164 case TAB (PCREL, SHORT):
4167 case TAB (PCREL, LONG):
4168 /* The thing to do here is force it to ABSOLUTE LONG, since
4169 PCREL is really trying to shorten an ABSOLUTE address anyway */
4170 /* JF FOO This code has not been tested */
4171 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4173 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4174 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4175 (unsigned) fragP->fr_opcode[0],
4176 (unsigned long) fragP->fr_address);
4177 fragP->fr_opcode[1] &= ~0x3F;
4178 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4182 case TAB (PCLEA, SHORT):
4183 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4184 fragP->fr_offset, 1, NO_RELOC);
4185 fragP->fr_opcode[1] &= ~0x3F;
4186 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4189 case TAB (PCLEA, LONG):
4190 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4191 fragP->fr_offset, 1, NO_RELOC);
4192 fixP->fx_pcrel_adjust = 2;
4193 /* Already set to mode 7.3; this indicates: PC indirect with
4194 suppressed index, 32-bit displacement. */
4195 *buffer_address++ = 0x01;
4196 *buffer_address++ = 0x70;
4201 case TAB (PCINDEX, BYTE):
4203 if (!issbyte (disp))
4205 as_bad ("displacement doesn't fit in one byte");
4208 assert (fragP->fr_fix >= 2);
4209 buffer_address[-2] &= ~1;
4210 buffer_address[-1] = disp;
4213 case TAB (PCINDEX, SHORT):
4215 assert (issword (disp));
4216 assert (fragP->fr_fix >= 2);
4217 buffer_address[-2] |= 0x1;
4218 buffer_address[-1] = 0x20;
4219 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4220 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4222 fixP->fx_pcrel_adjust = 2;
4225 case TAB (PCINDEX, LONG):
4227 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4228 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4230 fixP->fx_pcrel_adjust = 2;
4231 assert (fragP->fr_fix >= 2);
4232 buffer_address[-2] |= 0x1;
4233 buffer_address[-1] = 0x30;
4240 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4241 fragP->fr_fix += ext;
4245 #ifndef BFD_ASSEMBLER
4248 md_convert_frag (headers, sec, fragP)
4249 object_headers *headers;
4253 md_convert_frag_1 (fragP);
4259 md_convert_frag (abfd, sec, fragP)
4264 md_convert_frag_1 (fragP);
4268 /* Force truly undefined symbols to their maximum size, and generally set up
4269 the frag list to be relaxed
4272 md_estimate_size_before_relax (fragP, segment)
4273 register fragS *fragP;
4277 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4279 old_fix = fragP->fr_fix;
4281 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4282 switch (fragP->fr_subtype)
4285 case TAB (ABRANCH, SZ_UNDEF):
4287 if ((fragP->fr_symbol != NULL) /* Not absolute */
4288 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4290 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4293 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4295 /* On 68000, or for absolute value, switch to abs long */
4296 /* FIXME, we should check abs val, pick short or long */
4297 if (fragP->fr_opcode[0] == 0x61)
4299 fragP->fr_opcode[0] = 0x4E;
4300 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4301 fix_new (fragP, fragP->fr_fix, 4,
4302 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4306 else if (fragP->fr_opcode[0] == 0x60)
4308 fragP->fr_opcode[0] = 0x4E;
4309 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4310 fix_new (fragP, fragP->fr_fix, 4,
4311 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4317 as_warn ("Long branch offset to extern symbol not supported.");
4321 { /* Symbol is still undefined. Make it simple */
4322 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4323 fragP->fr_offset, 1, NO_RELOC);
4325 fragP->fr_opcode[1] = (char) 0xff;
4331 } /* case TAB(ABRANCH,SZ_UNDEF) */
4333 case TAB (FBRANCH, SZ_UNDEF):
4335 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4337 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4342 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4343 fragP->fr_offset, 1, NO_RELOC);
4345 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4349 } /* TAB(FBRANCH,SZ_UNDEF) */
4351 case TAB (PCREL, SZ_UNDEF):
4353 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4355 || cpu_of_arch (current_architecture) < m68020)
4357 fragP->fr_subtype = TAB (PCREL, SHORT);
4362 fragP->fr_subtype = TAB (PCREL, LONG);
4366 } /* TAB(PCREL,SZ_UNDEF) */
4368 case TAB (BCC68000, SZ_UNDEF):
4370 if ((fragP->fr_symbol != NULL)
4371 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4373 fragP->fr_subtype = TAB (BCC68000, BYTE);
4376 /* only Bcc 68000 instructions can come here */
4377 /* change bcc into b!cc/jmp absl long */
4378 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4379 if (flag_short_refs)
4381 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4382 /* JF: these were fr_opcode[2,3] */
4383 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4384 buffer_address[1] = (char) 0xf8;
4385 fragP->fr_fix += 2; /* account for jmp instruction */
4386 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4387 fragP->fr_offset, 0, NO_RELOC);
4392 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4393 /* JF: these were fr_opcode[2,3] */
4394 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4395 buffer_address[1] = (char) 0xf9;
4396 fragP->fr_fix += 2; /* account for jmp instruction */
4397 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4398 fragP->fr_offset, 0, NO_RELOC);
4403 } /* case TAB(BCC68000,SZ_UNDEF) */
4405 case TAB (DBCC, SZ_UNDEF):
4407 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4409 fragP->fr_subtype = TAB (DBCC, SHORT);
4413 /* only DBcc 68000 instructions can come here */
4414 /* change dbcc into dbcc/jmp absl long */
4415 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4416 buffer_address[0] = 0x00; /* branch offset = 4 */
4417 buffer_address[1] = 0x04;
4418 buffer_address[2] = 0x60; /* put in bra pc + ... */
4420 if (flag_short_refs)
4422 /* JF: these were fr_opcode[5-7] */
4423 buffer_address[3] = 0x04; /* plus 4 */
4424 buffer_address[4] = 0x4e; /* Put in Jump Word */
4425 buffer_address[5] = (char) 0xf8;
4426 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4427 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4428 fragP->fr_offset, 0, NO_RELOC);
4433 /* JF: these were fr_opcode[5-7] */
4434 buffer_address[3] = 0x06; /* Plus 6 */
4435 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4436 buffer_address[5] = (char) 0xf9;
4437 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4438 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4439 fragP->fr_offset, 0, NO_RELOC);
4445 } /* case TAB(DBCC,SZ_UNDEF) */
4447 case TAB (PCLEA, SZ_UNDEF):
4449 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4451 || cpu_of_arch (current_architecture) < m68020)
4453 fragP->fr_subtype = TAB (PCLEA, SHORT);
4458 fragP->fr_subtype = TAB (PCLEA, LONG);
4462 } /* TAB(PCLEA,SZ_UNDEF) */
4464 case TAB (PCINDEX, SZ_UNDEF):
4465 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4466 || cpu_of_arch (current_architecture) < m68020)
4468 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4472 fragP->fr_subtype = TAB (PCINDEX, LONG);
4481 /* now that SZ_UNDEF are taken care of, check others */
4482 switch (fragP->fr_subtype)
4484 case TAB (BCC68000, BYTE):
4485 case TAB (ABRANCH, BYTE):
4486 /* We can't do a short jump to the next instruction, so in that
4487 case we force word mode. At this point S_GET_VALUE should
4488 return the offset of the symbol within its frag. If the
4489 symbol is at the start of a frag, and it is the next frag
4490 with any data in it (usually this is just the next frag, but
4491 assembler listings may introduce empty frags), we must use
4493 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4497 for (l = fragP->fr_next;
4498 l != fragP->fr_symbol->sy_frag;
4500 if (l->fr_fix + l->fr_var != 0)
4502 if (l == fragP->fr_symbol->sy_frag)
4504 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4512 return fragP->fr_var + fragP->fr_fix - old_fix;
4515 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4516 /* the bit-field entries in the relocation_info struct plays hell
4517 with the byte-order problems of cross-assembly. So as a hack,
4518 I added this mach. dependent ri twiddler. Ugly, but it gets
4520 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4521 are symbolnum, most sig. byte first. Last byte is broken up with
4522 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4523 nibble as nuthin. (on Sun 3 at least) */
4524 /* Translate the internal relocation information into target-specific
4528 md_ri_to_chars (the_bytes, ri)
4530 struct reloc_info_generic *ri;
4533 md_number_to_chars (the_bytes, ri->r_address, 4);
4534 /* now the fun stuff */
4535 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4536 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4537 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4538 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4539 ((ri->r_extern << 4) & 0x10));
4542 #endif /* comment */
4544 #ifndef BFD_ASSEMBLER
4546 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4549 relax_addressT segment_address_in_file;
4552 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4553 * Out: GNU LD relocation length code: 0, 1, or 2.
4556 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4559 know (fixP->fx_addsy != NULL);
4561 md_number_to_chars (where,
4562 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4565 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4566 ? S_GET_TYPE (fixP->fx_addsy)
4567 : fixP->fx_addsy->sy_number);
4569 where[4] = (r_symbolnum >> 16) & 0x0ff;
4570 where[5] = (r_symbolnum >> 8) & 0x0ff;
4571 where[6] = r_symbolnum & 0x0ff;
4572 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4573 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4577 #endif /* OBJ_AOUT or OBJ_BOUT */
4579 #ifndef WORKING_DOT_WORD
4580 CONST int md_short_jump_size = 4;
4581 CONST int md_long_jump_size = 6;
4584 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4586 addressT from_addr, to_addr;
4592 offset = to_addr - (from_addr + 2);
4594 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4595 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4599 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4601 addressT from_addr, to_addr;
4607 if (!HAVE_LONG_BRANCH(current_architecture))
4609 offset = to_addr - S_GET_VALUE (to_symbol);
4610 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4611 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4612 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4617 offset = to_addr - (from_addr + 2);
4618 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4619 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4625 /* Different values of OK tell what its OK to return. Things that
4626 aren't OK are an error (what a shock, no?)
4629 10: Absolute 1:8 only
4630 20: Absolute 0:7 only
4631 30: absolute 0:15 only
4632 40: Absolute 0:31 only
4633 50: absolute 0:127 only
4634 55: absolute -64:63 only
4635 60: absolute -128:127 only
4636 70: absolute 0:4095 only
4643 struct m68k_exp *exp;
4646 if (exp->exp.X_op == O_absent)
4648 /* Do the same thing the VAX asm does */
4649 op (exp) = O_constant;
4655 as_warn ("expression out of range: defaulting to 1");
4659 else if (exp->exp.X_op == O_constant)
4664 if (offs (exp) < 1 || offs (exp) > 8)
4666 as_warn ("expression out of range: defaulting to 1");
4671 if (offs (exp) < 0 || offs (exp) > 7)
4675 if (offs (exp) < 0 || offs (exp) > 15)
4679 if (offs (exp) < 0 || offs (exp) > 32)
4683 if (offs (exp) < 0 || offs (exp) > 127)
4687 if (offs (exp) < -64 || offs (exp) > 63)
4691 if (offs (exp) < -128 || offs (exp) > 127)
4695 if (offs (exp) < 0 || offs (exp) > 4095)
4698 as_warn ("expression out of range: defaulting to 0");
4706 else if (exp->exp.X_op == O_big)
4708 if (offs (exp) <= 0 /* flonum */
4709 && (ok == 80 /* no bignums */
4710 || (ok > 10 /* small-int ranges including 0 ok */
4711 /* If we have a flonum zero, a zero integer should
4712 do as well (e.g., in moveq). */
4713 && generic_floating_point_number.exponent == 0
4714 && generic_floating_point_number.low[0] == 0)))
4716 /* HACK! Turn it into a long */
4717 LITTLENUM_TYPE words[6];
4719 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4720 op (exp) = O_constant;
4723 offs (exp) = words[1] | (words[0] << 16);
4727 op (exp) = O_constant;
4730 offs (exp) = (ok == 10) ? 1 : 0;
4731 as_warn ("Can't deal with expression; defaulting to %ld",
4737 if (ok >= 10 && ok <= 70)
4739 op (exp) = O_constant;
4742 offs (exp) = (ok == 10) ? 1 : 0;
4743 as_warn ("Can't deal with expression; defaulting to %ld",
4748 if (exp->size != SIZE_UNSPEC)
4756 if (!isbyte (offs (exp)))
4757 as_warn ("expression doesn't fit in BYTE");
4760 if (!isword (offs (exp)))
4761 as_warn ("expression doesn't fit in WORD");
4769 /* These are the back-ends for the various machine dependent pseudo-ops. */
4770 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4776 subseg_set (data_section, 1);
4777 demand_empty_rest_of_line ();
4784 subseg_set (data_section, 2);
4785 demand_empty_rest_of_line ();
4792 /* We don't support putting frags in the BSS segment, we fake it
4793 by marking in_bss, then looking at s_skip for clues. */
4795 subseg_set (bss_section, 0);
4796 demand_empty_rest_of_line ();
4804 register long temp_fill;
4806 temp = 1; /* JF should be 2? */
4807 temp_fill = get_absolute_expression ();
4808 if (!need_pass_2) /* Never make frag if expect extra pass. */
4809 frag_align (temp, (int) temp_fill, 0);
4810 demand_empty_rest_of_line ();
4811 record_alignment (now_seg, temp);
4818 demand_empty_rest_of_line ();
4821 /* Pseudo-ops handled for MRI compatibility. */
4823 /* This function returns non-zero if the argument is a conditional
4824 pseudo-op. This is called when checking whether a pending
4825 alignment is needed. */
4828 m68k_conditional_pseudoop (pop)
4831 return (pop->poc_handler == s_mri_if
4832 || pop->poc_handler == s_mri_else);
4835 /* Handle an MRI style chip specification. */
4844 s = input_line_pointer;
4845 c = get_symbol_end ();
4846 for (i = 0; i < n_archs; i++)
4847 if (strcasecmp (s, archs[i].name) == 0)
4851 as_bad ("%s: unrecognized processor name", s);
4852 *input_line_pointer = c;
4853 ignore_rest_of_line ();
4856 *input_line_pointer = c;
4858 if (*input_line_pointer == '/')
4859 current_architecture = 0;
4861 current_architecture &= m68881 | m68851;
4862 current_architecture |= archs[i].arch;
4864 while (*input_line_pointer == '/')
4866 ++input_line_pointer;
4867 s = input_line_pointer;
4868 c = get_symbol_end ();
4869 if (strcmp (s, "68881") == 0)
4870 current_architecture |= m68881;
4871 else if (strcmp (s, "68851") == 0)
4872 current_architecture |= m68851;
4873 *input_line_pointer = c;
4876 /* Update info about available control registers. */
4877 select_control_regs ();
4880 /* The MRI CHIP pseudo-op. */
4890 stop = mri_comment_field (&stopc);
4893 mri_comment_end (stop, stopc);
4894 demand_empty_rest_of_line ();
4897 /* The MRI FOPT pseudo-op. */
4905 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4909 input_line_pointer += 3;
4910 temp = get_absolute_expression ();
4911 if (temp < 0 || temp > 7)
4912 as_bad ("bad coprocessor id");
4914 m68k_float_copnum = COP0 + temp;
4918 as_bad ("unrecognized fopt option");
4919 ignore_rest_of_line ();
4923 demand_empty_rest_of_line ();
4926 /* The structure used to handle the MRI OPT pseudo-op. */
4930 /* The name of the option. */
4933 /* If this is not NULL, just call this function. The first argument
4934 is the ARG field of this structure, the second argument is
4935 whether the option was negated. */
4936 void (*pfn) PARAMS ((int arg, int on));
4938 /* If this is not NULL, and the PFN field is NULL, set the variable
4939 this points to. Set it to the ARG field if the option was not
4940 negated, and the NOTARG field otherwise. */
4943 /* The value to pass to PFN or to assign to *PVAR. */
4946 /* The value to assign to *PVAR if the option is negated. If PFN is
4947 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4948 the option may not be negated. */
4952 /* The table used to handle the MRI OPT pseudo-op. */
4954 static void skip_to_comma PARAMS ((int, int));
4955 static void opt_nest PARAMS ((int, int));
4956 static void opt_chip PARAMS ((int, int));
4957 static void opt_list PARAMS ((int, int));
4958 static void opt_list_symbols PARAMS ((int, int));
4960 static const struct opt_action opt_table[] =
4962 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4964 /* We do relaxing, so there is little use for these options. */
4965 { "b", 0, 0, 0, 0 },
4966 { "brs", 0, 0, 0, 0 },
4967 { "brb", 0, 0, 0, 0 },
4968 { "brl", 0, 0, 0, 0 },
4969 { "brw", 0, 0, 0, 0 },
4971 { "c", 0, 0, 0, 0 },
4972 { "cex", 0, 0, 0, 0 },
4973 { "case", 0, &symbols_case_sensitive, 1, 0 },
4974 { "cl", 0, 0, 0, 0 },
4975 { "cre", 0, 0, 0, 0 },
4976 { "d", 0, &flag_keep_locals, 1, 0 },
4977 { "e", 0, 0, 0, 0 },
4978 { "f", 0, &flag_short_refs, 1, 0 },
4979 { "frs", 0, &flag_short_refs, 1, 0 },
4980 { "frl", 0, &flag_short_refs, 0, 1 },
4981 { "g", 0, 0, 0, 0 },
4982 { "i", 0, 0, 0, 0 },
4983 { "m", 0, 0, 0, 0 },
4984 { "mex", 0, 0, 0, 0 },
4985 { "mc", 0, 0, 0, 0 },
4986 { "md", 0, 0, 0, 0 },
4987 { "nest", opt_nest, 0, 0, 0 },
4988 { "next", skip_to_comma, 0, 0, 0 },
4989 { "o", 0, 0, 0, 0 },
4990 { "old", 0, 0, 0, 0 },
4991 { "op", skip_to_comma, 0, 0, 0 },
4992 { "pco", 0, 0, 0, 0 },
4993 { "p", opt_chip, 0, 0, 0 },
4994 { "pcr", 0, 0, 0, 0 },
4995 { "pcs", 0, 0, 0, 0 },
4996 { "r", 0, 0, 0, 0 },
4997 { "quick", 0, &m68k_quick, 1, 0 },
4998 { "rel32", 0, &m68k_rel32, 1, 0 },
4999 { "s", opt_list, 0, 0, 0 },
5000 { "t", opt_list_symbols, 0, 0, 0 },
5001 { "w", 0, &flag_no_warnings, 0, 1 },
5005 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5007 /* The MRI OPT pseudo-op. */
5019 const struct opt_action *o;
5024 if (*input_line_pointer == '-')
5026 ++input_line_pointer;
5029 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5031 input_line_pointer += 2;
5035 s = input_line_pointer;
5036 c = get_symbol_end ();
5038 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5040 if (strcasecmp (s, o->name) == 0)
5044 /* Restore input_line_pointer now in case the option
5046 *input_line_pointer = c;
5047 (*o->pfn) (o->arg, t);
5049 else if (o->pvar != NULL)
5051 if (! t && o->arg == o->notarg)
5052 as_bad ("option `%s' may not be negated", s);
5053 *input_line_pointer = c;
5054 *o->pvar = t ? o->arg : o->notarg;
5057 *input_line_pointer = c;
5063 as_bad ("option `%s' not recognized", s);
5064 *input_line_pointer = c;
5067 while (*input_line_pointer++ == ',');
5069 /* Move back to terminating character. */
5070 --input_line_pointer;
5071 demand_empty_rest_of_line ();
5074 /* Skip ahead to a comma. This is used for OPT options which we do
5075 not suppor tand which take arguments. */
5078 skip_to_comma (arg, on)
5082 while (*input_line_pointer != ','
5083 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5084 ++input_line_pointer;
5087 /* Handle the OPT NEST=depth option. */
5094 if (*input_line_pointer != '=')
5096 as_bad ("bad format of OPT NEST=depth");
5100 ++input_line_pointer;
5101 max_macro_nest = get_absolute_expression ();
5104 /* Handle the OPT P=chip option. */
5111 if (*input_line_pointer != '=')
5113 /* This is just OPT P, which we do not support. */
5117 ++input_line_pointer;
5121 /* Handle the OPT S option. */
5131 /* Handle the OPT T option. */
5134 opt_list_symbols (arg, on)
5139 listing |= LISTING_SYMBOLS;
5141 listing &=~ LISTING_SYMBOLS;
5144 /* Handle the MRI REG pseudo-op. */
5157 if (line_label == NULL)
5159 as_bad ("missing label");
5160 ignore_rest_of_line ();
5165 stop = mri_comment_field (&stopc);
5169 s = input_line_pointer;
5170 while (isalnum ((unsigned char) *input_line_pointer)
5171 #ifdef REGISTER_PREFIX
5172 || *input_line_pointer == REGISTER_PREFIX
5174 || *input_line_pointer == '/'
5175 || *input_line_pointer == '-')
5176 ++input_line_pointer;
5177 c = *input_line_pointer;
5178 *input_line_pointer = '\0';
5180 if (m68k_ip_op (s, &rop) != 0)
5182 if (rop.error == NULL)
5183 as_bad ("bad register list");
5185 as_bad ("bad register list: %s", rop.error);
5186 *input_line_pointer = c;
5187 ignore_rest_of_line ();
5191 *input_line_pointer = c;
5193 if (rop.mode == REGLST)
5195 else if (rop.mode == DREG)
5196 mask = 1 << (rop.reg - DATA0);
5197 else if (rop.mode == AREG)
5198 mask = 1 << (rop.reg - ADDR0 + 8);
5199 else if (rop.mode == FPREG)
5200 mask = 1 << (rop.reg - FP0 + 16);
5201 else if (rop.mode == CONTROL
5204 else if (rop.mode == CONTROL
5207 else if (rop.mode == CONTROL
5212 as_bad ("bad register list");
5213 ignore_rest_of_line ();
5217 S_SET_SEGMENT (line_label, absolute_section);
5218 S_SET_VALUE (line_label, mask);
5219 line_label->sy_frag = &zero_address_frag;
5222 mri_comment_end (stop, stopc);
5224 demand_empty_rest_of_line ();
5227 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5231 struct save_opts *next;
5233 int symbols_case_sensitive;
5241 /* FIXME: We don't save OPT S. */
5244 /* This variable holds the stack of saved options. */
5246 static struct save_opts *save_stack;
5248 /* The MRI SAVE pseudo-op. */
5254 struct save_opts *s;
5256 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5257 s->abspcadd = m68k_abspcadd;
5258 s->symbols_case_sensitive = symbols_case_sensitive;
5259 s->keep_locals = flag_keep_locals;
5260 s->short_refs = flag_short_refs;
5261 s->architecture = current_architecture;
5262 s->quick = m68k_quick;
5263 s->rel32 = m68k_rel32;
5264 s->listing = listing;
5265 s->no_warnings = flag_no_warnings;
5267 s->next = save_stack;
5270 demand_empty_rest_of_line ();
5273 /* The MRI RESTORE pseudo-op. */
5279 struct save_opts *s;
5281 if (save_stack == NULL)
5283 as_bad ("restore without save");
5284 ignore_rest_of_line ();
5289 save_stack = s->next;
5291 m68k_abspcadd = s->abspcadd;
5292 symbols_case_sensitive = s->symbols_case_sensitive;
5293 flag_keep_locals = s->keep_locals;
5294 flag_short_refs = s->short_refs;
5295 current_architecture = s->architecture;
5296 m68k_quick = s->quick;
5297 m68k_rel32 = s->rel32;
5298 listing = s->listing;
5299 flag_no_warnings = s->no_warnings;
5303 demand_empty_rest_of_line ();
5306 /* Types of MRI structured control directives. */
5308 enum mri_control_type
5316 /* This structure is used to stack the MRI structured control
5319 struct mri_control_info
5321 /* The directive within which this one is enclosed. */
5322 struct mri_control_info *outer;
5324 /* The type of directive. */
5325 enum mri_control_type type;
5327 /* Whether an ELSE has been in an IF. */
5330 /* The add or sub statement at the end of a FOR. */
5333 /* The label of the top of a FOR or REPEAT loop. */
5336 /* The label to jump to for the next iteration, or the else
5337 expression of a conditional. */
5340 /* The label to jump to to break out of the loop, or the label past
5341 the end of a conditional. */
5345 /* The stack of MRI structured control directives. */
5347 static struct mri_control_info *mri_control_stack;
5349 /* The current MRI structured control directive index number, used to
5350 generate label names. */
5352 static int mri_control_index;
5354 /* Some function prototypes. */
5356 static char *mri_control_label PARAMS ((void));
5357 static struct mri_control_info *push_mri_control
5358 PARAMS ((enum mri_control_type));
5359 static void pop_mri_control PARAMS ((void));
5360 static int parse_mri_condition PARAMS ((int *));
5361 static int parse_mri_control_operand
5362 PARAMS ((int *, char **, char **, char **, char **));
5363 static int swap_mri_condition PARAMS ((int));
5364 static int reverse_mri_condition PARAMS ((int));
5365 static void build_mri_control_operand
5366 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5367 const char *, int));
5368 static void parse_mri_control_expression
5369 PARAMS ((char *, int, const char *, const char *, int));
5371 /* Generate a new MRI label structured control directive label name. */
5374 mri_control_label ()
5378 n = (char *) xmalloc (20);
5379 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5380 ++mri_control_index;
5384 /* Create a new MRI structured control directive. */
5386 static struct mri_control_info *
5387 push_mri_control (type)
5388 enum mri_control_type type;
5390 struct mri_control_info *n;
5392 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5396 if (type == mri_if || type == mri_while)
5399 n->top = mri_control_label ();
5400 n->next = mri_control_label ();
5401 n->bottom = mri_control_label ();
5403 n->outer = mri_control_stack;
5404 mri_control_stack = n;
5409 /* Pop off the stack of MRI structured control directives. */
5414 struct mri_control_info *n;
5416 n = mri_control_stack;
5417 mri_control_stack = n->outer;
5425 /* Recognize a condition code in an MRI structured control expression. */
5428 parse_mri_condition (pcc)
5433 know (*input_line_pointer == '<');
5435 ++input_line_pointer;
5436 c1 = *input_line_pointer++;
5437 c2 = *input_line_pointer++;
5439 if (*input_line_pointer != '>')
5441 as_bad ("syntax error in structured control directive");
5445 ++input_line_pointer;
5453 *pcc = (c1 << 8) | c2;
5458 /* Parse a single operand in an MRI structured control expression. */
5461 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5478 if (*input_line_pointer == '<')
5480 /* It's just a condition code. */
5481 return parse_mri_condition (pcc);
5484 /* Look ahead for the condition code. */
5485 for (s = input_line_pointer; *s != '\0'; ++s)
5487 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5492 as_bad ("missing condition code in structured control directive");
5496 *leftstart = input_line_pointer;
5498 if (*leftstop > *leftstart
5499 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5502 input_line_pointer = s;
5503 if (! parse_mri_condition (pcc))
5506 /* Look ahead for AND or OR or end of line. */
5507 for (s = input_line_pointer; *s != '\0'; ++s)
5509 if ((strncasecmp (s, "AND", 3) == 0
5510 && (s[3] == '.' || ! is_part_of_name (s[3])))
5511 || (strncasecmp (s, "OR", 2) == 0
5512 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5516 *rightstart = input_line_pointer;
5518 if (*rightstop > *rightstart
5519 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5522 input_line_pointer = s;
5527 #define MCC(b1, b2) (((b1) << 8) | (b2))
5529 /* Swap the sense of a condition. This changes the condition so that
5530 it generates the same result when the operands are swapped. */
5533 swap_mri_condition (cc)
5538 case MCC ('h', 'i'): return MCC ('c', 's');
5539 case MCC ('l', 's'): return MCC ('c', 'c');
5540 case MCC ('c', 'c'): return MCC ('l', 's');
5541 case MCC ('c', 's'): return MCC ('h', 'i');
5542 case MCC ('p', 'l'): return MCC ('m', 'i');
5543 case MCC ('m', 'i'): return MCC ('p', 'l');
5544 case MCC ('g', 'e'): return MCC ('l', 'e');
5545 case MCC ('l', 't'): return MCC ('g', 't');
5546 case MCC ('g', 't'): return MCC ('l', 't');
5547 case MCC ('l', 'e'): return MCC ('g', 'e');
5552 /* Reverse the sense of a condition. */
5555 reverse_mri_condition (cc)
5560 case MCC ('h', 'i'): return MCC ('l', 's');
5561 case MCC ('l', 's'): return MCC ('h', 'i');
5562 case MCC ('c', 'c'): return MCC ('c', 's');
5563 case MCC ('c', 's'): return MCC ('c', 'c');
5564 case MCC ('n', 'e'): return MCC ('e', 'q');
5565 case MCC ('e', 'q'): return MCC ('n', 'e');
5566 case MCC ('v', 'c'): return MCC ('v', 's');
5567 case MCC ('v', 's'): return MCC ('v', 'c');
5568 case MCC ('p', 'l'): return MCC ('m', 'i');
5569 case MCC ('m', 'i'): return MCC ('p', 'l');
5570 case MCC ('g', 'e'): return MCC ('l', 't');
5571 case MCC ('l', 't'): return MCC ('g', 'e');
5572 case MCC ('g', 't'): return MCC ('l', 'e');
5573 case MCC ('l', 'e'): return MCC ('g', 't');
5578 /* Build an MRI structured control expression. This generates test
5579 and branch instructions. It goes to TRUELAB if the condition is
5580 true, and to FALSELAB if the condition is false. Exactly one of
5581 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5582 is the size qualifier for the expression. EXTENT is the size to
5583 use for the branch. */
5586 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5587 rightstop, truelab, falselab, extent)
5594 const char *truelab;
5595 const char *falselab;
5601 if (leftstart != NULL)
5603 struct m68k_op leftop, rightop;
5606 /* Swap the compare operands, if necessary, to produce a legal
5607 m68k compare instruction. Comparing a register operand with
5608 a non-register operand requires the register to be on the
5609 right (cmp, cmpa). Comparing an immediate value with
5610 anything requires the immediate value to be on the left
5615 (void) m68k_ip_op (leftstart, &leftop);
5620 (void) m68k_ip_op (rightstart, &rightop);
5623 if (rightop.mode == IMMED
5624 || ((leftop.mode == DREG || leftop.mode == AREG)
5625 && (rightop.mode != DREG && rightop.mode != AREG)))
5629 cc = swap_mri_condition (cc);
5631 leftstart = rightstart;
5634 leftstop = rightstop;
5639 if (truelab == NULL)
5641 cc = reverse_mri_condition (cc);
5645 if (leftstart != NULL)
5647 buf = (char *) xmalloc (20
5648 + (leftstop - leftstart)
5649 + (rightstop - rightstart));
5657 memcpy (s, leftstart, leftstop - leftstart);
5658 s += leftstop - leftstart;
5660 memcpy (s, rightstart, rightstop - rightstart);
5661 s += rightstop - rightstart;
5667 buf = (char *) xmalloc (20 + strlen (truelab));
5675 strcpy (s, truelab);
5680 /* Parse an MRI structured control expression. This generates test
5681 and branch instructions. STOP is where the expression ends. It
5682 goes to TRUELAB if the condition is true, and to FALSELAB if the
5683 condition is false. Exactly one of TRUELAB and FALSELAB will be
5684 NULL, meaning to fall through. QUAL is the size qualifier for the
5685 expression. EXTENT is the size to use for the branch. */
5688 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5691 const char *truelab;
5692 const char *falselab;
5705 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5706 &rightstart, &rightstop))
5712 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5716 if (falselab != NULL)
5719 flab = mri_control_label ();
5721 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5722 rightstop, (const char *) NULL, flab, extent);
5724 input_line_pointer += 3;
5725 if (*input_line_pointer != '.'
5726 || input_line_pointer[1] == '\0')
5730 qual = input_line_pointer[1];
5731 input_line_pointer += 2;
5734 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5735 &rightstart, &rightstop))
5741 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5742 rightstop, truelab, falselab, extent);
5744 if (falselab == NULL)
5747 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5751 if (truelab != NULL)
5754 tlab = mri_control_label ();
5756 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5757 rightstop, tlab, (const char *) NULL, extent);
5759 input_line_pointer += 2;
5760 if (*input_line_pointer != '.'
5761 || input_line_pointer[1] == '\0')
5765 qual = input_line_pointer[1];
5766 input_line_pointer += 2;
5769 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5770 &rightstart, &rightstop))
5776 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5777 rightstop, truelab, falselab, extent);
5779 if (truelab == NULL)
5784 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5785 rightstop, truelab, falselab, extent);
5789 if (input_line_pointer != stop)
5790 as_bad ("syntax error in structured control directive");
5793 /* Handle the MRI IF pseudo-op. This may be a structured control
5794 directive, or it may be a regular assembler conditional, depending
5803 struct mri_control_info *n;
5805 /* A structured control directive must end with THEN with an
5806 optional qualifier. */
5807 s = input_line_pointer;
5808 while (! is_end_of_line[(unsigned char) *s]
5809 && (! flag_mri || *s != '*'))
5812 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5815 if (s - input_line_pointer > 1
5819 if (s - input_line_pointer < 3
5820 || strncasecmp (s - 3, "THEN", 4) != 0)
5824 as_bad ("missing then");
5825 ignore_rest_of_line ();
5829 /* It's a conditional. */
5834 /* Since this might be a conditional if, this pseudo-op will be
5835 called even if we are supported to be ignoring input. Double
5836 check now. Clobber *input_line_pointer so that ignore_input
5837 thinks that this is not a special pseudo-op. */
5838 c = *input_line_pointer;
5839 *input_line_pointer = 0;
5840 if (ignore_input ())
5842 *input_line_pointer = c;
5843 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5844 ++input_line_pointer;
5845 demand_empty_rest_of_line ();
5848 *input_line_pointer = c;
5850 n = push_mri_control (mri_if);
5852 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5853 n->next, s[1] == '.' ? s[2] : '\0');
5856 input_line_pointer = s + 3;
5858 input_line_pointer = s + 1;
5862 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5863 ++input_line_pointer;
5866 demand_empty_rest_of_line ();
5869 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5870 structured IF, associate the ELSE with the IF. Otherwise, assume
5871 it is a conditional else. */
5882 && (mri_control_stack == NULL
5883 || mri_control_stack->type != mri_if
5884 || mri_control_stack->else_seen))
5890 c = *input_line_pointer;
5891 *input_line_pointer = 0;
5892 if (ignore_input ())
5894 *input_line_pointer = c;
5895 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5896 ++input_line_pointer;
5897 demand_empty_rest_of_line ();
5900 *input_line_pointer = c;
5902 if (mri_control_stack == NULL
5903 || mri_control_stack->type != mri_if
5904 || mri_control_stack->else_seen)
5906 as_bad ("else without matching if");
5907 ignore_rest_of_line ();
5911 mri_control_stack->else_seen = 1;
5913 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5916 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5920 colon (mri_control_stack->next);
5924 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5925 ++input_line_pointer;
5928 demand_empty_rest_of_line ();
5931 /* Handle the MRI ENDI pseudo-op. */
5937 if (mri_control_stack == NULL
5938 || mri_control_stack->type != mri_if)
5940 as_bad ("endi without matching if");
5941 ignore_rest_of_line ();
5945 /* ignore_input will not return true for ENDI, so we don't need to
5946 worry about checking it again here. */
5948 if (! mri_control_stack->else_seen)
5949 colon (mri_control_stack->next);
5950 colon (mri_control_stack->bottom);
5956 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5957 ++input_line_pointer;
5960 demand_empty_rest_of_line ();
5963 /* Handle the MRI BREAK pseudo-op. */
5966 s_mri_break (extent)
5969 struct mri_control_info *n;
5973 n = mri_control_stack;
5975 && n->type != mri_for
5976 && n->type != mri_repeat
5977 && n->type != mri_while)
5981 as_bad ("break outside of structured loop");
5982 ignore_rest_of_line ();
5986 buf = (char *) xmalloc (20 + strlen (n->bottom));
5989 sprintf (buf, "bra%s %s", ex, n->bottom);
5995 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5996 ++input_line_pointer;
5999 demand_empty_rest_of_line ();
6002 /* Handle the MRI NEXT pseudo-op. */
6008 struct mri_control_info *n;
6012 n = mri_control_stack;
6014 && n->type != mri_for
6015 && n->type != mri_repeat
6016 && n->type != mri_while)
6020 as_bad ("next outside of structured loop");
6021 ignore_rest_of_line ();
6025 buf = (char *) xmalloc (20 + strlen (n->next));
6028 sprintf (buf, "bra%s %s", ex, n->next);
6034 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6035 ++input_line_pointer;
6038 demand_empty_rest_of_line ();
6041 /* Handle the MRI FOR pseudo-op. */
6047 const char *varstart, *varstop;
6048 const char *initstart, *initstop;
6049 const char *endstart, *endstop;
6050 const char *bystart, *bystop;
6054 struct mri_control_info *n;
6060 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6064 varstart = input_line_pointer;
6066 /* Look for the '='. */
6067 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6068 && *input_line_pointer != '=')
6069 ++input_line_pointer;
6070 if (*input_line_pointer != '=')
6072 as_bad ("missing =");
6073 ignore_rest_of_line ();
6077 varstop = input_line_pointer;
6078 if (varstop > varstart
6079 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6082 ++input_line_pointer;
6084 initstart = input_line_pointer;
6086 /* Look for TO or DOWNTO. */
6089 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6091 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6092 && ! is_part_of_name (input_line_pointer[2]))
6094 initstop = input_line_pointer;
6095 input_line_pointer += 2;
6098 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6099 && ! is_part_of_name (input_line_pointer[6]))
6101 initstop = input_line_pointer;
6103 input_line_pointer += 6;
6106 ++input_line_pointer;
6108 if (initstop == NULL)
6110 as_bad ("missing to or downto");
6111 ignore_rest_of_line ();
6114 if (initstop > initstart
6115 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6119 endstart = input_line_pointer;
6121 /* Look for BY or DO. */
6124 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6126 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6127 && ! is_part_of_name (input_line_pointer[2]))
6129 endstop = input_line_pointer;
6131 input_line_pointer += 2;
6134 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6135 && (input_line_pointer[2] == '.'
6136 || ! is_part_of_name (input_line_pointer[2])))
6138 endstop = input_line_pointer;
6139 input_line_pointer += 2;
6142 ++input_line_pointer;
6144 if (endstop == NULL)
6146 as_bad ("missing do");
6147 ignore_rest_of_line ();
6150 if (endstop > endstart
6151 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6157 bystop = bystart + 2;
6162 bystart = input_line_pointer;
6166 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6168 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6169 && (input_line_pointer[2] == '.'
6170 || ! is_part_of_name (input_line_pointer[2])))
6172 bystop = input_line_pointer;
6173 input_line_pointer += 2;
6176 ++input_line_pointer;
6180 as_bad ("missing do");
6181 ignore_rest_of_line ();
6184 if (bystop > bystart
6185 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6189 if (*input_line_pointer != '.')
6193 extent = input_line_pointer[1];
6194 input_line_pointer += 2;
6197 /* We have fully parsed the FOR operands. Now build the loop. */
6199 n = push_mri_control (mri_for);
6201 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6212 memcpy (s, initstart, initstop - initstart);
6213 s += initstop - initstart;
6215 memcpy (s, varstart, varstop - varstart);
6216 s += varstop - varstart;
6230 memcpy (s, endstart, endstop - endstart);
6231 s += endstop - endstart;
6233 memcpy (s, varstart, varstop - varstart);
6234 s += varstop - varstart;
6242 sprintf (buf, "blt%s %s", ex, n->bottom);
6244 sprintf (buf, "bgt%s %s", ex, n->bottom);
6247 /* Put together the add or sub instruction used by ENDF. */
6257 memcpy (s, bystart, bystop - bystart);
6258 s += bystop - bystart;
6260 memcpy (s, varstart, varstop - varstart);
6261 s += varstop - varstart;
6267 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6268 ++input_line_pointer;
6271 demand_empty_rest_of_line ();
6274 /* Handle the MRI ENDF pseudo-op. */
6280 if (mri_control_stack == NULL
6281 || mri_control_stack->type != mri_for)
6283 as_bad ("endf without for");
6284 ignore_rest_of_line ();
6288 colon (mri_control_stack->next);
6290 md_assemble (mri_control_stack->incr);
6292 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6293 md_assemble (mri_control_stack->incr);
6295 free (mri_control_stack->incr);
6297 colon (mri_control_stack->bottom);
6303 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6304 ++input_line_pointer;
6307 demand_empty_rest_of_line ();
6310 /* Handle the MRI REPEAT pseudo-op. */
6313 s_mri_repeat (ignore)
6316 struct mri_control_info *n;
6318 n = push_mri_control (mri_repeat);
6322 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6323 ++input_line_pointer;
6325 demand_empty_rest_of_line ();
6328 /* Handle the MRI UNTIL pseudo-op. */
6336 if (mri_control_stack == NULL
6337 || mri_control_stack->type != mri_repeat)
6339 as_bad ("until without repeat");
6340 ignore_rest_of_line ();
6344 colon (mri_control_stack->next);
6346 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6349 parse_mri_control_expression (s, qual, (const char *) NULL,
6350 mri_control_stack->top, '\0');
6352 colon (mri_control_stack->bottom);
6354 input_line_pointer = s;
6360 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6361 ++input_line_pointer;
6364 demand_empty_rest_of_line ();
6367 /* Handle the MRI WHILE pseudo-op. */
6375 struct mri_control_info *n;
6377 s = input_line_pointer;
6378 while (! is_end_of_line[(unsigned char) *s]
6379 && (! flag_mri || *s != '*'))
6382 while (*s == ' ' || *s == '\t')
6384 if (s - input_line_pointer > 1
6387 if (s - input_line_pointer < 2
6388 || strncasecmp (s - 1, "DO", 2) != 0)
6390 as_bad ("missing do");
6391 ignore_rest_of_line ();
6395 n = push_mri_control (mri_while);
6399 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6400 s[1] == '.' ? s[2] : '\0');
6402 input_line_pointer = s + 1;
6403 if (*input_line_pointer == '.')
6404 input_line_pointer += 2;
6408 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6409 ++input_line_pointer;
6412 demand_empty_rest_of_line ();
6415 /* Handle the MRI ENDW pseudo-op. */
6423 if (mri_control_stack == NULL
6424 || mri_control_stack->type != mri_while)
6426 as_bad ("endw without while");
6427 ignore_rest_of_line ();
6431 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6432 sprintf (buf, "bra %s", mri_control_stack->next);
6436 colon (mri_control_stack->bottom);
6442 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6443 ++input_line_pointer;
6446 demand_empty_rest_of_line ();
6451 * Invocation line includes a switch not recognized by the base assembler.
6452 * See if it's a processor-specific option. These are:
6454 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6455 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6456 * Select the architecture. Instructions or features not
6457 * supported by the selected architecture cause fatal
6458 * errors. More than one may be specified. The default is
6459 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6460 * for -m68000, and -m68882 is a synonym for -m68881.
6461 * -[A]m[c]no-68851, -[A]m[c]no-68881
6462 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6463 * so don't use or document it, but that's the way the parsing
6466 * -pic Indicates PIC.
6467 * -k Indicates PIC. (Sun 3 only.)
6470 * Permit `|' to be used in expressions.
6475 CONST char *md_shortopts = "lSA:m:kQ:V";
6477 CONST char *md_shortopts = "lSA:m:k";
6480 struct option md_longopts[] = {
6481 #define OPTION_PIC (OPTION_MD_BASE)
6482 {"pic", no_argument, NULL, OPTION_PIC},
6483 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6484 {"register-prefix-optional", no_argument, NULL,
6485 OPTION_REGISTER_PREFIX_OPTIONAL},
6486 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6487 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6488 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6489 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6490 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6491 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6492 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6493 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6494 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6495 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6496 {NULL, no_argument, NULL, 0}
6498 size_t md_longopts_size = sizeof(md_longopts);
6501 md_parse_option (c, arg)
6507 case 'l': /* -l means keep external to 2 bit offset
6508 rather than 16 bit one */
6509 flag_short_refs = 1;
6512 case 'S': /* -S means that jbsr's always turn into
6514 flag_long_jumps = 1;
6520 /* intentional fall-through */
6523 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6527 const char *oarg = arg;
6533 if (arg[0] == 'c' && arg[1] == '6')
6536 for (i = 0; i < n_archs; i++)
6537 if (!strcmp (arg, archs[i].name))
6542 as_bad ("unrecognized option `%s'", oarg);
6545 arch = archs[i].arch;
6548 else if (arch == m68851)
6557 if (arg[0] == 'c' && arg[1] == '6')
6560 for (i = 0; i < n_archs; i++)
6561 if (!strcmp (arg, archs[i].name))
6563 unsigned long arch = archs[i].arch;
6564 if (cpu_of_arch (arch))
6565 /* It's a cpu spec. */
6567 current_architecture &= ~m68000up;
6568 current_architecture |= arch;
6570 else if (arch == m68881)
6572 current_architecture |= m68881;
6575 else if (arch == m68851)
6577 current_architecture |= m68851;
6587 as_bad ("unrecognized architecture specification `%s'", arg);
6596 break; /* -pic, Position Independent Code */
6598 case OPTION_REGISTER_PREFIX_OPTIONAL:
6599 flag_reg_prefix_optional = 1;
6600 reg_prefix_optional_seen = 1;
6603 /* -V: SVR4 argument to print version ID. */
6605 print_version_id ();
6608 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6609 should be emitted or not. FIXME: Not implemented. */
6613 case OPTION_BITWISE_OR:
6618 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6620 for (s = m68k_comment_chars; *s != '\0'; s++)
6624 m68k_comment_chars = n;
6628 case OPTION_BASE_SIZE_DEFAULT_16:
6629 m68k_index_width_default = SIZE_WORD;
6632 case OPTION_BASE_SIZE_DEFAULT_32:
6633 m68k_index_width_default = SIZE_LONG;
6636 case OPTION_DISP_SIZE_DEFAULT_16:
6638 m68k_rel32_from_cmdline = 1;
6641 case OPTION_DISP_SIZE_DEFAULT_32:
6643 m68k_rel32_from_cmdline = 1;
6654 md_show_usage (stream)
6659 -l use 1 word for refs to undefined symbols [default 2]\n\
6660 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6661 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6662 | -mcpu32 | -m5200\n\
6663 specify variant of 680X0 architecture [default 68020]\n\
6664 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6665 target has/lacks floating-point coprocessor\n\
6666 [default yes for 68020, 68030, and cpu32]\n");
6668 -m68851 | -mno-68851\n\
6669 target has/lacks memory-management unit coprocessor\n\
6670 [default yes for 68020 and up]\n\
6671 -pic, -k generate position independent code\n\
6672 -S turn jbsr into jsr\n\
6673 --register-prefix-optional\n\
6674 recognize register names without prefix character\n\
6675 --bitwise-or do not treat `|' as a comment character\n");
6677 --base-size-default-16 base reg without size is 16 bits\n\
6678 --base-size-default-32 base reg without size is 32 bits (default)\n\
6679 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6680 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
6685 /* TEST2: Test md_assemble() */
6686 /* Warning, this routine probably doesn't work anymore */
6690 struct m68k_it the_ins;
6698 if (!gets (buf) || !*buf)
6700 if (buf[0] == '|' || buf[1] == '.')
6702 for (cp = buf; *cp; cp++)
6707 memset (&the_ins, '\0', sizeof (the_ins));
6708 m68k_ip (&the_ins, buf);
6711 printf ("Error %s in %s\n", the_ins.error, buf);
6715 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6716 for (n = 0; n < the_ins.numo; n++)
6717 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6719 print_the_insn (&the_ins.opcode[0], stdout);
6720 (void) putchar ('\n');
6722 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6724 if (the_ins.operands[n].error)
6726 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6729 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6730 if (the_ins.operands[n].b_const)
6731 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6732 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6733 if (the_ins.operands[n].b_iadd)
6734 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6735 (void) putchar ('\n');
6747 while (*str && *str != ' ')
6749 if (str[-1] == ':' || str[1] == '=')
6756 /* Possible states for relaxation:
6758 0 0 branch offset byte (bra, etc)
6762 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6766 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6773 /* We have no need to default values of symbols. */
6777 md_undefined_symbol (name)
6783 /* Round up a section size to the appropriate boundary. */
6785 md_section_align (segment, size)
6789 return size; /* Byte alignment is fine */
6792 /* Exactly what point is a PC-relative offset relative TO?
6793 On the 68k, it is relative to the address of the first extension
6794 word. The difference between the addresses of the offset and the
6795 first extension word is stored in fx_pcrel_adjust. */
6797 md_pcrel_from (fixP)
6802 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6804 adjust = fixP->fx_pcrel_adjust;
6807 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6810 #ifndef BFD_ASSEMBLER
6813 tc_coff_symbol_emit_hook (ignore)
6819 tc_coff_sizemachdep (frag)
6822 switch (frag->fr_subtype & 0x3)
6837 /* end of tc-m68k.c */