1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
47 const char *m68k_comment_chars = "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
59 const char line_separator_chars[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
86 int flag_reg_prefix_optional;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32 = 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line *next;
127 /* The list of labels. */
129 static struct label_line *labels;
131 /* The current label. */
133 static struct label_line *current_label;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn;
144 const char *m_operands;
145 unsigned long m_opcode;
149 struct m68k_incant *m_next;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
179 static const enum m68k_register mcf51qe_ctrl[] = {
183 static const enum m68k_register mcf5206_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
187 static const enum m68k_register mcf5208_ctrl[] = {
188 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
191 static const enum m68k_register mcf5210a_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
195 static const enum m68k_register mcf5213_ctrl[] = {
196 VBR, RAMBAR, RAMBAR1, FLASHBAR,
199 static const enum m68k_register mcf5216_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
203 static const enum m68k_register mcf52223_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
207 static const enum m68k_register mcf52235_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
211 static const enum m68k_register mcf5225_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
215 static const enum m68k_register mcf5235_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
219 static const enum m68k_register mcf5249_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
223 static const enum m68k_register mcf5250_ctrl[] = {
227 static const enum m68k_register mcf5253_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
231 static const enum m68k_register mcf5271_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
235 static const enum m68k_register mcf5272_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
239 static const enum m68k_register mcf5275_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
243 static const enum m68k_register mcf5282_ctrl[] = {
244 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
247 static const enum m68k_register mcf5307_ctrl[] = {
248 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
251 static const enum m68k_register mcf5329_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
255 static const enum m68k_register mcf5373_ctrl[] = {
256 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
259 static const enum m68k_register mcfv4e_ctrl[] = {
260 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
261 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
263 MPCR /* Multiprocessor Control register */,
264 EDRAMBAR /* Embedded DRAM Base Address Register */,
265 /* Permutation control registers. */
266 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
267 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
269 TC /* ASID */, BUSCR /* MMUBAR */,
270 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
271 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
272 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
275 static const enum m68k_register mcf5407_ctrl[] = {
276 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
277 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
280 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
281 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
284 static const enum m68k_register mcf54455_ctrl[] = {
285 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
286 VBR, PC, RAMBAR1, MBAR,
288 TC /* ASID */, BUSCR /* MMUBAR */,
289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
293 static const enum m68k_register mcf5475_ctrl[] = {
294 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
295 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
297 TC /* ASID */, BUSCR /* MMUBAR */,
298 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
299 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
302 static const enum m68k_register mcf5485_ctrl[] = {
303 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
304 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
306 TC /* ASID */, BUSCR /* MMUBAR */,
307 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
308 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
311 static const enum m68k_register fido_ctrl[] = {
312 SFC, DFC, USP, VBR, CAC, MBO,
315 #define cpu32_ctrl m68010_ctrl
317 static const enum m68k_register *control_regs;
319 /* Internal form of a 68020 instruction. */
323 const char *args; /* List of opcode info. */
326 int numo; /* Number of shorts in opcode. */
329 struct m68k_op operands[6];
331 int nexp; /* Number of exprs in use. */
332 struct m68k_exp exprs[4];
334 int nfrag; /* Number of frags we have to produce. */
337 int fragoff; /* Where in the current opcode the frag ends. */
344 int nrel; /* Num of reloc strucs in use. */
351 /* In a pc relative address the difference between the address
352 of the offset and the address that the offset is relative
353 to. This depends on the addressing mode. Basically this
354 is the value to put in the offset field to address the
355 first byte of the offset, without regarding the special
356 significance of some values (in the branch instruction, for
360 /* Whether this expression needs special pic relocation, and if
362 enum pic_relocation pic_reloc;
365 reloc[5]; /* Five is enough??? */
368 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
369 #define float_of_arch(x) ((x) & mfloat)
370 #define mmu_of_arch(x) ((x) & mmmu)
371 #define arch_coldfire_p(x) ((x) & mcfisa_a)
372 #define arch_coldfire_fpu(x) ((x) & cfloat)
374 /* Macros for determining if cpu supports a specific addressing mode. */
375 #define HAVE_LONG_DISP(x) \
376 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
377 #define HAVE_LONG_CALL(x) \
378 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
379 #define HAVE_LONG_COND(x) \
380 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
381 #define HAVE_LONG_BRANCH(x) \
382 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
383 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
385 static struct m68k_it the_ins; /* The instruction being assembled. */
387 #define op(ex) ((ex)->exp.X_op)
388 #define adds(ex) ((ex)->exp.X_add_symbol)
389 #define subs(ex) ((ex)->exp.X_op_symbol)
390 #define offs(ex) ((ex)->exp.X_add_number)
392 /* Macros for adding things to the m68k_it struct. */
393 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
395 /* Like addword, but goes BEFORE general operands. */
398 insop (int w, const struct m68k_incant *opcode)
401 for (z = the_ins.numo; z > opcode->m_codenum; --z)
402 the_ins.opcode[z] = the_ins.opcode[z - 1];
403 for (z = 0; z < the_ins.nrel; z++)
404 the_ins.reloc[z].n += 2;
405 for (z = 0; z < the_ins.nfrag; z++)
406 the_ins.fragb[z].fragoff++;
407 the_ins.opcode[opcode->m_codenum] = w;
411 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
414 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
416 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
417 ? the_ins.numo * 2 - 1
419 ? the_ins.numo * 2 + 1
420 : the_ins.numo * 2));
421 the_ins.reloc[the_ins.nrel].exp = exp->exp;
422 the_ins.reloc[the_ins.nrel].wid = width;
423 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
425 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
427 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
430 /* Cause an extra frag to be generated here, inserting up to 10 bytes
431 (that value is chosen in the frag_var call in md_assemble). TYPE
432 is the subtype of the frag to be generated; its primary type is
433 rs_machine_dependent.
435 The TYPE parameter is also used by md_convert_frag_1 and
436 md_estimate_size_before_relax. The appropriate type of fixup will
437 be emitted by md_convert_frag_1.
439 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
441 add_frag (symbolS *add, offsetT off, int type)
443 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
444 the_ins.fragb[the_ins.nfrag].fadd = add;
445 the_ins.fragb[the_ins.nfrag].foff = off;
446 the_ins.fragb[the_ins.nfrag++].fragty = type;
450 (op (ex) != O_constant && op (ex) != O_big)
452 static char *crack_operand (char *str, struct m68k_op *opP);
453 static int get_num (struct m68k_exp *exp, int ok);
454 static int reverse_16_bits (int in);
455 static int reverse_8_bits (int in);
456 static void install_gen_operand (int mode, int val);
457 static void install_operand (int mode, int val);
458 static void s_bss (int);
459 static void s_data1 (int);
460 static void s_data2 (int);
461 static void s_even (int);
462 static void s_proc (int);
463 static void s_chip (int);
464 static void s_fopt (int);
465 static void s_opt (int);
466 static void s_reg (int);
467 static void s_restore (int);
468 static void s_save (int);
469 static void s_mri_if (int);
470 static void s_mri_else (int);
471 static void s_mri_endi (int);
472 static void s_mri_break (int);
473 static void s_mri_next (int);
474 static void s_mri_for (int);
475 static void s_mri_endf (int);
476 static void s_mri_repeat (int);
477 static void s_mri_until (int);
478 static void s_mri_while (int);
479 static void s_mri_endw (int);
480 static void s_m68k_cpu (int);
481 static void s_m68k_arch (int);
485 unsigned long arch; /* Architecture features. */
486 const enum m68k_register *control_regs; /* Control regs on chip */
487 const char *name; /* Name */
488 int alias; /* Alias for a cannonical name. If 1, then
489 succeeds canonical name, if -1 then
490 succeeds canonical name, if <-1 ||>1 this is a
491 deprecated name, and the next/previous name
495 /* We hold flags for features explicitly enabled and explicitly
497 static int current_architecture;
498 static int not_current_architecture;
499 static const struct m68k_cpu *selected_arch;
500 static const struct m68k_cpu *selected_cpu;
501 static int initialized;
503 /* Architecture models. */
504 static const struct m68k_cpu m68k_archs[] =
506 {m68000, m68000_ctrl, "68000", 0},
507 {m68010, m68010_ctrl, "68010", 0},
508 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
509 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
510 {m68040, m68040_ctrl, "68040", 0},
511 {m68060, m68060_ctrl, "68060", 0},
512 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
513 {fido_a, fido_ctrl, "fidoa", 0},
514 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
515 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
516 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
517 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
518 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
519 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
523 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
525 static const struct m68k_cpu m68k_extensions[] =
527 {m68851, NULL, "68851", -1},
528 {m68881, NULL, "68881", -1},
529 {m68881, NULL, "68882", -1},
531 {cfloat|m68881, NULL, "float", 0},
533 {mcfhwdiv, NULL, "div", 1},
534 {mcfusp, NULL, "usp", 1},
535 {mcfmac, NULL, "mac", 1},
536 {mcfemac, NULL, "emac", 1},
542 static const struct m68k_cpu m68k_cpus[] =
544 {m68000, m68000_ctrl, "68000", 0},
545 {m68000, m68000_ctrl, "68ec000", 1},
546 {m68000, m68000_ctrl, "68hc000", 1},
547 {m68000, m68000_ctrl, "68hc001", 1},
548 {m68000, m68000_ctrl, "68008", 1},
549 {m68000, m68000_ctrl, "68302", 1},
550 {m68000, m68000_ctrl, "68306", 1},
551 {m68000, m68000_ctrl, "68307", 1},
552 {m68000, m68000_ctrl, "68322", 1},
553 {m68000, m68000_ctrl, "68356", 1},
554 {m68010, m68010_ctrl, "68010", 0},
555 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
556 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
557 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
558 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
559 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
560 {m68040, m68040_ctrl, "68040", 0},
561 {m68040, m68040_ctrl, "68ec040", 1},
562 {m68060, m68060_ctrl, "68060", 0},
563 {m68060, m68060_ctrl, "68ec060", 1},
565 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
566 {cpu32|m68881, cpu32_ctrl, "68330", 1},
567 {cpu32|m68881, cpu32_ctrl, "68331", 1},
568 {cpu32|m68881, cpu32_ctrl, "68332", 1},
569 {cpu32|m68881, cpu32_ctrl, "68333", 1},
570 {cpu32|m68881, cpu32_ctrl, "68334", 1},
571 {cpu32|m68881, cpu32_ctrl, "68336", 1},
572 {cpu32|m68881, cpu32_ctrl, "68340", 1},
573 {cpu32|m68881, cpu32_ctrl, "68341", 1},
574 {cpu32|m68881, cpu32_ctrl, "68349", 1},
575 {cpu32|m68881, cpu32_ctrl, "68360", 1},
577 {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0},
579 {mcfisa_a, mcf_ctrl, "5200", 0},
580 {mcfisa_a, mcf_ctrl, "5202", 1},
581 {mcfisa_a, mcf_ctrl, "5204", 1},
582 {mcfisa_a, mcf5206_ctrl, "5206", 1},
584 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
600 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
601 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
609 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
617 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
618 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
619 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
624 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
634 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
645 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
647 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
648 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
649 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
650 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
651 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
652 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
654 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
655 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
656 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
657 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
658 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
659 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
660 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
662 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
663 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
664 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
665 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
666 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
667 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
668 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
670 {fido_a, fido_ctrl, "fidoa", 0},
671 {fido_a, fido_ctrl, "fido", 1},
676 static const struct m68k_cpu *m68k_lookup_cpu
677 (const char *, const struct m68k_cpu *, int, int *);
678 static int m68k_set_arch (const char *, int, int);
679 static int m68k_set_cpu (const char *, int, int);
680 static int m68k_set_extension (const char *, int, int);
681 static void m68k_init_arch (void);
683 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
684 architecture and we have a lot of relaxation modes. */
686 /* Macros used in the relaxation code. */
687 #define TAB(x,y) (((x) << 2) + (y))
688 #define TABTYPE(x) ((x) >> 2)
690 /* Relaxation states. */
696 /* Here are all the relaxation modes we support. First we can relax ordinary
697 branches. On 68020 and higher and on CPU32 all branch instructions take
698 three forms, so on these CPUs all branches always remain as such. When we
699 have to expand to the LONG form on a 68000, though, we substitute an
700 absolute jump instead. This is a direct replacement for unconditional
701 branches and a branch over a jump for conditional branches. However, if the
702 user requires PIC and disables this with --pcrel, we can only relax between
703 BYTE and SHORT forms, punting if that isn't enough. This gives us four
704 different relaxation modes for branches: */
706 #define BRANCHBWL 0 /* Branch byte, word, or long. */
707 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
708 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
709 #define BRANCHBW 3 /* Branch byte or word. */
711 /* We also relax coprocessor branches and DBcc's. All CPUs that support
712 coprocessor branches support them in word and long forms, so we have only
713 one relaxation mode for them. DBcc's are word only on all CPUs. We can
714 relax them to the LONG form with a branch-around sequence. This sequence
715 can use a long branch (if available) or an absolute jump (if acceptable).
716 This gives us two relaxation modes. If long branches are not available and
717 absolute jumps are not acceptable, we don't relax DBcc's. */
719 #define FBRANCH 4 /* Coprocessor branch. */
720 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
721 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
723 /* That's all for instruction relaxation. However, we also relax PC-relative
724 operands. Specifically, we have three operand relaxation modes. On the
725 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
726 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
727 two. Also PC+displacement+index operands in their simple form (with a non-
728 suppressed index without memory indirection) are supported on all CPUs, but
729 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
730 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
731 form of the PC+displacement+index operand. Finally, some absolute operands
732 can be relaxed down to 16-bit PC-relative. */
734 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
735 #define PCINDEX 8 /* PC + displacement + index. */
736 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
738 /* This relaxation is required for branches where there is no long
739 branch and we are in pcrel mode. We generate a bne/beq pair. */
740 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
743 /* Note that calls to frag_var need to specify the maximum expansion
744 needed; this is currently 12 bytes for bne/beq pair. */
745 #define FRAG_VAR_SIZE 12
748 How far Forward this mode will reach:
749 How far Backward this mode will reach:
750 How many bytes this mode will add to the size of the frag
751 Which mode to go to if the offset won't fit in this one
753 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
754 relax_typeS md_relax_table[] =
756 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
757 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
761 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
762 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
766 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
767 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
771 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
776 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
777 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
781 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
782 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
786 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
787 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
791 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
792 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
796 { 125, -130, 0, TAB (PCINDEX, SHORT) },
797 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
801 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
802 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
806 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
807 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
812 /* These are the machine dependent pseudo-ops. These are included so
813 the assembler can work on the output from the SUN C compiler, which
816 /* This table describes all the machine specific pseudo-ops the assembler
817 has to support. The fields are:
818 pseudo-op name without dot
819 function to call to execute this pseudo-op
820 Integer arg to pass to the function. */
821 const pseudo_typeS md_pseudo_table[] =
823 {"data1", s_data1, 0},
824 {"data2", s_data2, 0},
827 {"skip", s_space, 0},
829 #if defined (TE_SUN3) || defined (OBJ_ELF)
830 {"align", s_align_bytes, 0},
833 {"swbeg", s_ignore, 0},
835 {"extend", float_cons, 'x'},
836 {"ldouble", float_cons, 'x'},
838 {"arch", s_m68k_arch, 0},
839 {"cpu", s_m68k_cpu, 0},
841 /* The following pseudo-ops are supported for MRI compatibility. */
843 {"comline", s_space, 1},
845 {"mask2", s_ignore, 0},
848 {"restore", s_restore, 0},
852 {"if.b", s_mri_if, 'b'},
853 {"if.w", s_mri_if, 'w'},
854 {"if.l", s_mri_if, 'l'},
855 {"else", s_mri_else, 0},
856 {"else.s", s_mri_else, 's'},
857 {"else.l", s_mri_else, 'l'},
858 {"endi", s_mri_endi, 0},
859 {"break", s_mri_break, 0},
860 {"break.s", s_mri_break, 's'},
861 {"break.l", s_mri_break, 'l'},
862 {"next", s_mri_next, 0},
863 {"next.s", s_mri_next, 's'},
864 {"next.l", s_mri_next, 'l'},
865 {"for", s_mri_for, 0},
866 {"for.b", s_mri_for, 'b'},
867 {"for.w", s_mri_for, 'w'},
868 {"for.l", s_mri_for, 'l'},
869 {"endf", s_mri_endf, 0},
870 {"repeat", s_mri_repeat, 0},
871 {"until", s_mri_until, 0},
872 {"until.b", s_mri_until, 'b'},
873 {"until.w", s_mri_until, 'w'},
874 {"until.l", s_mri_until, 'l'},
875 {"while", s_mri_while, 0},
876 {"while.b", s_mri_while, 'b'},
877 {"while.w", s_mri_while, 'w'},
878 {"while.l", s_mri_while, 'l'},
879 {"endw", s_mri_endw, 0},
884 /* The mote pseudo ops are put into the opcode table, since they
885 don't start with a . they look like opcodes to gas. */
887 const pseudo_typeS mote_pseudo_table[] =
900 {"xdef", s_globl, 0},
902 {"align", s_align_bytes, 0},
904 {"align", s_align_ptwo, 0},
907 {"sect", obj_coff_section, 0},
908 {"section", obj_coff_section, 0},
913 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
914 gives identical results to a 32-bit host. */
915 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
916 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
918 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
919 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
920 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
921 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
923 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
924 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
925 #define islong(x) (1)
927 static char notend_table[256];
928 static char alt_notend_table[256];
930 (! (notend_table[(unsigned char) *s] \
932 && alt_notend_table[(unsigned char) s[1]])))
936 /* Return zero if the reference to SYMBOL from within the same segment may
939 /* On an ELF system, we can't relax an externally visible symbol,
940 because it may be overridden by a shared library. However, if
941 TARGET_OS is "elf", then we presume that we are assembling for an
942 embedded system, in which case we don't have to worry about shared
943 libraries, and we can relax any external sym. */
945 #define relaxable_symbol(symbol) \
946 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
947 || S_IS_WEAK (symbol)))
949 /* Compute the relocation code for a fixup of SIZE bytes, using pc
950 relative relocation if PCREL is non-zero. PIC says whether a special
951 pic relocation was requested. */
953 static bfd_reloc_code_real_type
954 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
962 return BFD_RELOC_8_GOT_PCREL;
964 return BFD_RELOC_16_GOT_PCREL;
966 return BFD_RELOC_32_GOT_PCREL;
974 return BFD_RELOC_8_GOTOFF;
976 return BFD_RELOC_16_GOTOFF;
978 return BFD_RELOC_32_GOTOFF;
986 return BFD_RELOC_8_PLT_PCREL;
988 return BFD_RELOC_16_PLT_PCREL;
990 return BFD_RELOC_32_PLT_PCREL;
998 return BFD_RELOC_8_PLTOFF;
1000 return BFD_RELOC_16_PLTOFF;
1002 return BFD_RELOC_32_PLTOFF;
1012 return BFD_RELOC_8_PCREL;
1014 return BFD_RELOC_16_PCREL;
1016 return BFD_RELOC_32_PCREL;
1026 return BFD_RELOC_16;
1028 return BFD_RELOC_32;
1035 if (pic == pic_none)
1036 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1038 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1042 if (pic == pic_none)
1043 as_bad (_("Can not do %d byte relocation"), size);
1045 as_bad (_("Can not do %d byte pic relocation"), size);
1048 return BFD_RELOC_NONE;
1051 /* Here we decide which fixups can be adjusted to make them relative
1052 to the beginning of the section instead of the symbol. Basically
1053 we need to make sure that the dynamic relocations are done
1054 correctly, so in some cases we force the original symbol to be
1057 tc_m68k_fix_adjustable (fixS *fixP)
1059 /* Adjust_reloc_syms doesn't know about the GOT. */
1060 switch (fixP->fx_r_type)
1062 case BFD_RELOC_8_GOT_PCREL:
1063 case BFD_RELOC_16_GOT_PCREL:
1064 case BFD_RELOC_32_GOT_PCREL:
1065 case BFD_RELOC_8_GOTOFF:
1066 case BFD_RELOC_16_GOTOFF:
1067 case BFD_RELOC_32_GOTOFF:
1068 case BFD_RELOC_8_PLT_PCREL:
1069 case BFD_RELOC_16_PLT_PCREL:
1070 case BFD_RELOC_32_PLT_PCREL:
1071 case BFD_RELOC_8_PLTOFF:
1072 case BFD_RELOC_16_PLTOFF:
1073 case BFD_RELOC_32_PLTOFF:
1076 case BFD_RELOC_VTABLE_INHERIT:
1077 case BFD_RELOC_VTABLE_ENTRY:
1085 #else /* !OBJ_ELF */
1087 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1089 /* PR gas/3041 Weak symbols are not relaxable
1090 because they must be treated as extern. */
1091 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1093 #endif /* OBJ_ELF */
1096 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1099 bfd_reloc_code_real_type code;
1101 /* If the tcbit is set, then this was a fixup of a negative value
1102 that was never resolved. We do not have a reloc to handle this,
1103 so just return. We assume that other code will have detected this
1104 situation and produced a helpful error message, so we just tell the
1105 user that the reloc cannot be produced. */
1109 as_bad_where (fixp->fx_file, fixp->fx_line,
1110 _("Unable to produce reloc against symbol '%s'"),
1111 S_GET_NAME (fixp->fx_addsy));
1115 if (fixp->fx_r_type != BFD_RELOC_NONE)
1117 code = fixp->fx_r_type;
1119 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1120 that fixup_segment converted a non-PC relative reloc into a
1121 PC relative reloc. In such a case, we need to convert the
1128 code = BFD_RELOC_8_PCREL;
1131 code = BFD_RELOC_16_PCREL;
1134 code = BFD_RELOC_32_PCREL;
1136 case BFD_RELOC_8_PCREL:
1137 case BFD_RELOC_16_PCREL:
1138 case BFD_RELOC_32_PCREL:
1139 case BFD_RELOC_8_GOT_PCREL:
1140 case BFD_RELOC_16_GOT_PCREL:
1141 case BFD_RELOC_32_GOT_PCREL:
1142 case BFD_RELOC_8_GOTOFF:
1143 case BFD_RELOC_16_GOTOFF:
1144 case BFD_RELOC_32_GOTOFF:
1145 case BFD_RELOC_8_PLT_PCREL:
1146 case BFD_RELOC_16_PLT_PCREL:
1147 case BFD_RELOC_32_PLT_PCREL:
1148 case BFD_RELOC_8_PLTOFF:
1149 case BFD_RELOC_16_PLTOFF:
1150 case BFD_RELOC_32_PLTOFF:
1153 as_bad_where (fixp->fx_file, fixp->fx_line,
1154 _("Cannot make %s relocation PC relative"),
1155 bfd_get_reloc_code_name (code));
1161 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1162 switch (F (fixp->fx_size, fixp->fx_pcrel))
1164 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1165 MAP (1, 0, BFD_RELOC_8);
1166 MAP (2, 0, BFD_RELOC_16);
1167 MAP (4, 0, BFD_RELOC_32);
1168 MAP (1, 1, BFD_RELOC_8_PCREL);
1169 MAP (2, 1, BFD_RELOC_16_PCREL);
1170 MAP (4, 1, BFD_RELOC_32_PCREL);
1178 reloc = (arelent *) xmalloc (sizeof (arelent));
1179 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1180 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1181 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1184 reloc->addend = fixp->fx_addnumber;
1185 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1187 && S_IS_WEAK (fixp->fx_addsy)
1188 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1189 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1190 to put the symbol offset into frags referencing a weak symbol. */
1191 reloc->addend = fixp->fx_addnumber
1192 - (S_GET_VALUE (fixp->fx_addsy) * 2);
1196 if (!fixp->fx_pcrel)
1197 reloc->addend = fixp->fx_addnumber;
1199 reloc->addend = (section->vma
1200 /* Explicit sign extension in case char is
1202 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1203 + fixp->fx_addnumber
1204 + md_pcrel_from (fixp));
1207 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1208 assert (reloc->howto != 0);
1213 /* Handle of the OPCODE hash table. NULL means any use before
1214 m68k_ip_begin() will crash. */
1215 static struct hash_control *op_hash;
1217 /* Assemble an m68k instruction. */
1220 m68k_ip (char *instring)
1223 register struct m68k_op *opP;
1224 register const struct m68k_incant *opcode;
1225 register const char *s;
1226 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1227 char *pdot, *pdotmove;
1228 enum m68k_size siz1, siz2;
1232 struct m68k_op operands_backup[6];
1233 LITTLENUM_TYPE words[6];
1234 LITTLENUM_TYPE *wordp;
1235 unsigned long ok_arch = 0;
1237 if (*instring == ' ')
1238 instring++; /* Skip leading whitespace. */
1240 /* Scan up to end of operation-code, which MUST end in end-of-string
1241 or exactly 1 space. */
1243 for (p = instring; *p != '\0'; p++)
1253 the_ins.error = _("No operator");
1257 /* p now points to the end of the opcode name, probably whitespace.
1258 Make sure the name is null terminated by clobbering the
1259 whitespace, look it up in the hash table, then fix it back.
1260 Remove a dot, first, since the opcode tables have none. */
1263 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1264 *pdotmove = pdotmove[1];
1270 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1275 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1276 *pdotmove = pdotmove[-1];
1283 the_ins.error = _("Unknown operator");
1287 /* Found a legitimate opcode, start matching operands. */
1291 if (opcode->m_operands == 0)
1293 char *old = input_line_pointer;
1295 input_line_pointer = p;
1296 /* Ahh - it's a motorola style psuedo op. */
1297 mote_pseudo_table[opcode->m_opnum].poc_handler
1298 (mote_pseudo_table[opcode->m_opnum].poc_val);
1299 input_line_pointer = old;
1305 if (flag_mri && opcode->m_opnum == 0)
1307 /* In MRI mode, random garbage is allowed after an instruction
1308 which accepts no operands. */
1309 the_ins.args = opcode->m_operands;
1310 the_ins.numargs = opcode->m_opnum;
1311 the_ins.numo = opcode->m_codenum;
1312 the_ins.opcode[0] = getone (opcode);
1313 the_ins.opcode[1] = gettwo (opcode);
1317 for (opP = &the_ins.operands[0]; *p; opP++)
1319 p = crack_operand (p, opP);
1323 the_ins.error = opP->error;
1328 opsfound = opP - &the_ins.operands[0];
1330 /* This ugly hack is to support the floating pt opcodes in their
1331 standard form. Essentially, we fake a first enty of type COP#1 */
1332 if (opcode->m_operands[0] == 'I')
1336 for (n = opsfound; n > 0; --n)
1337 the_ins.operands[n] = the_ins.operands[n - 1];
1339 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1340 the_ins.operands[0].mode = CONTROL;
1341 the_ins.operands[0].reg = m68k_float_copnum;
1345 /* We've got the operands. Find an opcode that'll accept them. */
1348 /* If we didn't get the right number of ops, or we have no
1349 common model with this pattern then reject this pattern. */
1351 ok_arch |= opcode->m_arch;
1352 if (opsfound != opcode->m_opnum
1353 || ((opcode->m_arch & current_architecture) == 0))
1359 /* Make a copy of the operands of this insn so that
1360 we can modify them safely, should we want to. */
1361 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1362 for (i = 0; i < opsfound; i++)
1363 operands_backup[i] = the_ins.operands[i];
1365 for (s = opcode->m_operands, opP = &operands_backup[0];
1369 /* Warning: this switch is huge! */
1370 /* I've tried to organize the cases into this order:
1371 non-alpha first, then alpha by letter. Lower-case
1372 goes directly before uppercase counterpart. */
1373 /* Code with multiple case ...: gets sorted by the lowest
1374 case ... it belongs to. I hope this makes sense. */
1480 if (opP->reg == PC || opP->reg == ZPC)
1497 if (opP->reg == PC || opP->reg == ZPC)
1516 if (opP->reg == PC || opP->reg == ZPC)
1526 if (opP->mode != IMMED)
1528 else if (s[1] == 'b'
1529 && ! isvar (&opP->disp)
1530 && (opP->disp.exp.X_op != O_constant
1531 || ! isbyte (opP->disp.exp.X_add_number)))
1533 else if (s[1] == 'B'
1534 && ! isvar (&opP->disp)
1535 && (opP->disp.exp.X_op != O_constant
1536 || ! issbyte (opP->disp.exp.X_add_number)))
1538 else if (s[1] == 'w'
1539 && ! isvar (&opP->disp)
1540 && (opP->disp.exp.X_op != O_constant
1541 || ! isword (opP->disp.exp.X_add_number)))
1543 else if (s[1] == 'W'
1544 && ! isvar (&opP->disp)
1545 && (opP->disp.exp.X_op != O_constant
1546 || ! issword (opP->disp.exp.X_add_number)))
1552 if (opP->mode != IMMED)
1557 if (opP->mode == AREG
1558 || opP->mode == CONTROL
1559 || opP->mode == FPREG
1560 || opP->mode == IMMED
1561 || opP->mode == REGLST
1562 || (opP->mode != ABSL
1564 || opP->reg == ZPC)))
1569 if (opP->mode == CONTROL
1570 || opP->mode == FPREG
1571 || opP->mode == REGLST
1572 || opP->mode == IMMED
1573 || (opP->mode != ABSL
1575 || opP->reg == ZPC)))
1603 if (opP->mode == CONTROL
1604 || opP->mode == FPREG
1605 || opP->mode == REGLST)
1610 if (opP->mode != AINC)
1615 if (opP->mode != ADEC)
1665 if (opP->reg == PC || opP->reg == ZPC)
1686 case '~': /* For now! (JF FOO is this right?) */
1708 if (opP->mode != CONTROL
1709 || (opP->reg != TT0 && opP->reg != TT1))
1714 if (opP->mode != AREG)
1719 if (opP->mode != AINDR)
1724 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1725 && (opP->mode != DISP
1727 || opP->reg > ADDR7))
1732 if (opP->mode != ABSL
1734 && strncmp (instring, "jbsr", 4) == 0))
1757 if (opP->mode != CONTROL || opP->reg != CCR)
1762 if (opP->mode != DISP
1764 || opP->reg > ADDR7)
1769 if (opP->mode != DREG)
1774 if (opP->reg != ACC)
1779 if (opP->reg != ACC && opP->reg != ACC1
1780 && opP->reg != ACC2 && opP->reg != ACC3)
1785 if (opP->mode != FPREG)
1790 if (opP->reg != MACSR)
1795 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1800 if (opP->reg != MASK)
1805 if (opP->mode != CONTROL
1812 if (opP->mode != LSH && opP->mode != RSH)
1817 if (opP->mode != CONTROL
1819 || opP->reg > last_movec_reg
1824 const enum m68k_register *rp;
1826 for (rp = control_regs; *rp; rp++)
1828 if (*rp == opP->reg)
1830 /* In most CPUs RAMBAR refers to control reg
1831 c05 (RAMBAR1), but a few CPUs have it
1832 refer to c04 (RAMBAR0). */
1833 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1835 opP->reg = RAMBAR_ALT;
1845 if (opP->mode != IMMED)
1851 if (opP->mode == DREG
1852 || opP->mode == AREG
1853 || opP->mode == FPREG)
1862 opP->mask = 1 << (opP->reg - DATA0);
1865 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1868 opP->mask = 1 << (opP->reg - FP0 + 16);
1876 else if (opP->mode == CONTROL)
1885 opP->mask = 1 << 24;
1888 opP->mask = 1 << 25;
1891 opP->mask = 1 << 26;
1900 else if (opP->mode != REGLST)
1902 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1904 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1909 if (opP->mode != IMMED)
1911 else if (opP->disp.exp.X_op != O_constant
1912 || ! issbyte (opP->disp.exp.X_add_number))
1914 else if (! m68k_quick
1915 && instring[3] != 'q'
1916 && instring[4] != 'q')
1921 if (opP->mode != DREG
1922 && opP->mode != IMMED
1923 && opP->mode != ABSL)
1928 if (opP->mode != IMMED)
1930 else if (opP->disp.exp.X_op != O_constant
1931 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1933 else if (! m68k_quick
1934 && (strncmp (instring, "add", 3) == 0
1935 || strncmp (instring, "sub", 3) == 0)
1936 && instring[3] != 'q')
1941 if (opP->mode != DREG && opP->mode != AREG)
1946 if (opP->mode != AINDR
1947 && (opP->mode != BASE
1949 && opP->reg != ZADDR0)
1950 || opP->disp.exp.X_op != O_absent
1951 || ((opP->index.reg < DATA0
1952 || opP->index.reg > DATA7)
1953 && (opP->index.reg < ADDR0
1954 || opP->index.reg > ADDR7))
1955 || opP->index.size != SIZE_UNSPEC
1956 || opP->index.scale != 1))
1961 if (opP->mode != CONTROL
1962 || ! (opP->reg == FPI
1964 || opP->reg == FPC))
1969 if (opP->mode != CONTROL || opP->reg != SR)
1974 if (opP->mode != IMMED)
1976 else if (opP->disp.exp.X_op != O_constant
1977 || TRUNC (opP->disp.exp.X_add_number) > 7)
1982 if (opP->mode != CONTROL || opP->reg != USP)
1987 if (opP->mode != IMMED)
1989 else if (opP->disp.exp.X_op != O_constant
1990 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1991 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1996 if (opP->mode != IMMED)
1998 else if (opP->disp.exp.X_op != O_constant
1999 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2004 if (opP->mode != IMMED)
2006 else if (opP->disp.exp.X_op != O_constant
2007 || TRUNC (opP->disp.exp.X_add_number) > 511)
2011 /* JF these are out of order. We could put them
2012 in order if we were willing to put up with
2013 bunches of #ifdef m68851s in the code.
2015 Don't forget that you need these operands
2016 to use 68030 MMU instructions. */
2018 /* Memory addressing mode used by pflushr. */
2020 if (opP->mode == CONTROL
2021 || opP->mode == FPREG
2022 || opP->mode == DREG
2023 || opP->mode == AREG
2024 || opP->mode == REGLST)
2026 /* We should accept immediate operands, but they
2027 supposedly have to be quad word, and we don't
2028 handle that. I would like to see what a Motorola
2029 assembler does before doing something here. */
2030 if (opP->mode == IMMED)
2035 if (opP->mode != CONTROL
2036 || (opP->reg != SFC && opP->reg != DFC))
2041 if (opP->mode != CONTROL || opP->reg != TC)
2046 if (opP->mode != CONTROL || opP->reg != AC)
2051 if (opP->mode != CONTROL
2054 && opP->reg != SCC))
2059 if (opP->mode != CONTROL
2065 if (opP->mode != CONTROL
2068 && opP->reg != CRP))
2092 if (opP->mode != CONTROL
2093 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2094 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2099 if (opP->mode != CONTROL || opP->reg != PSR)
2104 if (opP->mode != CONTROL || opP->reg != PCSR)
2109 if (opP->mode != CONTROL
2118 if (opP->mode != ABSL)
2123 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2125 /* FIXME: kludge instead of fixing parser:
2126 upper/lower registers are *not* CONTROL
2127 registers, but ordinary ones. */
2128 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2129 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2136 if (!(opP->mode == AINDR
2137 || (opP->mode == DISP
2138 && !(opP->reg == PC || opP->reg == ZPC))))
2143 if (!(opP->mode == AINDR || opP->mode == DISP))
2155 /* Since we have found the correct instruction, copy
2156 in the modifications that we may have made. */
2158 for (i = 0; i < opsfound; i++)
2159 the_ins.operands[i] = operands_backup[i];
2165 opcode = opcode->m_next;
2170 && !(ok_arch & current_architecture))
2172 const struct m68k_cpu *cpu;
2175 char *buf = xmalloc (space + 1);
2179 the_ins.error = buf;
2180 /* Make sure there's a NUL at the end of the buffer -- strncpy
2181 won't write one when it runs out of buffer */
2183 #define APPEND(STRING) \
2184 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2186 APPEND (_("invalid instruction for this architecture; needs "));
2190 APPEND (_("ColdFire ISA_A"));
2193 APPEND (_("ColdFire hardware divide"));
2196 APPEND (_("ColdFire ISA_A+"));
2199 APPEND (_("ColdFire ISA_B"));
2202 APPEND (_("ColdFire ISA_C"));
2205 APPEND (_("ColdFire fpu"));
2208 APPEND (_("M68K fpu"));
2211 APPEND (_("M68K mmu"));
2214 APPEND (_("68020 or higher"));
2217 APPEND (_("68000 or higher"));
2220 APPEND (_("68010 or higher"));
2228 for (cpu = m68k_cpus; cpu->name; cpu++)
2229 if (!cpu->alias && (cpu->arch & ok_arch))
2231 const struct m68k_cpu *alias;
2232 int seen_master = 0;
2238 for (alias = cpu; alias != m68k_cpus; alias--)
2239 if (alias[-1].alias >= 0)
2241 for (; !seen_master || alias->alias > 0; alias++)
2251 APPEND (alias->name);
2264 /* we ran out of space, so replace the end of the list
2269 strcpy (buf, " ...");
2273 the_ins.error = _("operands mismatch");
2280 /* Now assemble it. */
2281 the_ins.args = opcode->m_operands;
2282 the_ins.numargs = opcode->m_opnum;
2283 the_ins.numo = opcode->m_codenum;
2284 the_ins.opcode[0] = getone (opcode);
2285 the_ins.opcode[1] = gettwo (opcode);
2287 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2292 /* This switch is a doozy.
2293 Watch the first step; its a big one! */
2326 tmpreg = 0x3c; /* 7.4 */
2327 if (strchr ("bwl", s[1]))
2328 nextword = get_num (&opP->disp, 90);
2330 nextword = get_num (&opP->disp, 0);
2331 if (isvar (&opP->disp))
2332 add_fix (s[1], &opP->disp, 0, 0);
2336 if (!isbyte (nextword))
2337 opP->error = _("operand out of range");
2342 if (!isword (nextword))
2343 opP->error = _("operand out of range");
2348 if (!issword (nextword))
2349 opP->error = _("operand out of range");
2354 addword (nextword >> 16);
2381 /* We gotta put out some float. */
2382 if (op (&opP->disp) != O_big)
2387 /* Can other cases happen here? */
2388 if (op (&opP->disp) != O_constant)
2391 val = (valueT) offs (&opP->disp);
2395 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2396 val >>= LITTLENUM_NUMBER_OF_BITS;
2400 offs (&opP->disp) = gencnt;
2402 if (offs (&opP->disp) > 0)
2404 if (offs (&opP->disp) > baseo)
2406 as_warn (_("Bignum too big for %c format; truncated"),
2408 offs (&opP->disp) = baseo;
2410 baseo -= offs (&opP->disp);
2413 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2414 offs (&opP->disp)--;
2419 gen_to_words (words, baseo, (long) outro);
2420 for (wordp = words; baseo--; wordp++)
2424 tmpreg = opP->reg - DATA; /* 0.dreg */
2427 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2430 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2433 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2436 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2440 nextword = get_num (&opP->disp, 90);
2442 /* Convert mode 5 addressing with a zero offset into
2443 mode 2 addressing to reduce the instruction size by a
2445 if (! isvar (&opP->disp)
2447 && (opP->disp.size == SIZE_UNSPEC)
2448 && (opP->reg >= ADDR0)
2449 && (opP->reg <= ADDR7))
2451 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2456 && ! isvar (&opP->disp)
2459 opP->disp.exp.X_op = O_symbol;
2460 opP->disp.exp.X_add_symbol =
2461 section_symbol (absolute_section);
2464 /* Force into index mode. Hope this works. */
2466 /* We do the first bit for 32-bit displacements, and the
2467 second bit for 16 bit ones. It is possible that we
2468 should make the default be WORD instead of LONG, but
2469 I think that'd break GCC, so we put up with a little
2470 inefficiency for the sake of working output. */
2472 if (!issword (nextword)
2473 || (isvar (&opP->disp)
2474 && ((opP->disp.size == SIZE_UNSPEC
2475 && flag_short_refs == 0
2476 && cpu_of_arch (current_architecture) >= m68020
2477 && ! arch_coldfire_p (current_architecture))
2478 || opP->disp.size == SIZE_LONG)))
2480 if (cpu_of_arch (current_architecture) < m68020
2481 || arch_coldfire_p (current_architecture))
2483 _("displacement too large for this architecture; needs 68020 or higher");
2485 tmpreg = 0x3B; /* 7.3 */
2487 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2488 if (isvar (&opP->disp))
2492 if (opP->disp.size == SIZE_LONG
2494 /* If the displacement needs pic
2495 relocation it cannot be relaxed. */
2496 || opP->disp.pic_reloc != pic_none
2501 add_fix ('l', &opP->disp, 1, 2);
2505 add_frag (adds (&opP->disp),
2506 SEXT (offs (&opP->disp)),
2507 TAB (PCREL1632, SZ_UNDEF));
2514 add_fix ('l', &opP->disp, 0, 0);
2519 addword (nextword >> 16);
2524 tmpreg = 0x3A; /* 7.2 */
2526 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2528 if (isvar (&opP->disp))
2532 add_fix ('w', &opP->disp, 1, 0);
2535 add_fix ('w', &opP->disp, 0, 0);
2545 baseo = get_num (&opP->disp, 90);
2546 if (opP->mode == POST || opP->mode == PRE)
2547 outro = get_num (&opP->odisp, 90);
2548 /* Figure out the `addressing mode'.
2549 Also turn on the BASE_DISABLE bit, if needed. */
2550 if (opP->reg == PC || opP->reg == ZPC)
2552 tmpreg = 0x3b; /* 7.3 */
2553 if (opP->reg == ZPC)
2556 else if (opP->reg == 0)
2559 tmpreg = 0x30; /* 6.garbage */
2561 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2564 tmpreg = 0x30 + opP->reg - ZADDR0;
2567 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2569 siz1 = opP->disp.size;
2570 if (opP->mode == POST || opP->mode == PRE)
2571 siz2 = opP->odisp.size;
2575 /* Index register stuff. */
2576 if (opP->index.reg != 0
2577 && opP->index.reg >= DATA
2578 && opP->index.reg <= ADDR7)
2580 nextword |= (opP->index.reg - DATA) << 12;
2582 if (opP->index.size == SIZE_LONG
2583 || (opP->index.size == SIZE_UNSPEC
2584 && m68k_index_width_default == SIZE_LONG))
2587 if ((opP->index.scale != 1
2588 && cpu_of_arch (current_architecture) < m68020)
2589 || (opP->index.scale == 8
2590 && (arch_coldfire_p (current_architecture)
2591 && !arch_coldfire_fpu (current_architecture))))
2594 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2597 if (arch_coldfire_p (current_architecture)
2598 && opP->index.size == SIZE_WORD)
2599 opP->error = _("invalid index size for coldfire");
2601 switch (opP->index.scale)
2618 GET US OUT OF HERE! */
2620 /* Must be INDEX, with an index register. Address
2621 register cannot be ZERO-PC, and either :b was
2622 forced, or we know it will fit. For a 68000 or
2623 68010, force this mode anyways, because the
2624 larger modes aren't supported. */
2625 if (opP->mode == BASE
2626 && ((opP->reg >= ADDR0
2627 && opP->reg <= ADDR7)
2630 if (siz1 == SIZE_BYTE
2631 || cpu_of_arch (current_architecture) < m68020
2632 || arch_coldfire_p (current_architecture)
2633 || (siz1 == SIZE_UNSPEC
2634 && ! isvar (&opP->disp)
2635 && issbyte (baseo)))
2637 nextword += baseo & 0xff;
2639 if (isvar (&opP->disp))
2641 /* Do a byte relocation. If it doesn't
2642 fit (possible on m68000) let the
2643 fixup processing complain later. */
2645 add_fix ('B', &opP->disp, 1, 1);
2647 add_fix ('B', &opP->disp, 0, 0);
2649 else if (siz1 != SIZE_BYTE)
2651 if (siz1 != SIZE_UNSPEC)
2652 as_warn (_("Forcing byte displacement"));
2653 if (! issbyte (baseo))
2654 opP->error = _("byte displacement out of range");
2659 else if (siz1 == SIZE_UNSPEC
2661 && isvar (&opP->disp)
2662 && subs (&opP->disp) == NULL
2664 /* If the displacement needs pic
2665 relocation it cannot be relaxed. */
2666 && opP->disp.pic_reloc == pic_none
2670 /* The code in md_convert_frag_1 needs to be
2671 able to adjust nextword. Call frag_grow
2672 to ensure that we have enough space in
2673 the frag obstack to make all the bytes
2676 nextword += baseo & 0xff;
2678 add_frag (adds (&opP->disp),
2679 SEXT (offs (&opP->disp)),
2680 TAB (PCINDEX, SZ_UNDEF));
2688 nextword |= 0x40; /* No index reg. */
2689 if (opP->index.reg >= ZDATA0
2690 && opP->index.reg <= ZDATA7)
2691 nextword |= (opP->index.reg - ZDATA0) << 12;
2692 else if (opP->index.reg >= ZADDR0
2693 || opP->index.reg <= ZADDR7)
2694 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2697 /* It isn't simple. */
2699 if (cpu_of_arch (current_architecture) < m68020
2700 || arch_coldfire_p (current_architecture))
2702 _("invalid operand mode for this architecture; needs 68020 or higher");
2705 /* If the guy specified a width, we assume that it is
2706 wide enough. Maybe it isn't. If so, we lose. */
2710 if (isvar (&opP->disp)
2712 : ! issword (baseo))
2717 else if (! isvar (&opP->disp) && baseo == 0)
2726 as_warn (_(":b not permitted; defaulting to :w"));
2736 /* Figure out inner displacement stuff. */
2737 if (opP->mode == POST || opP->mode == PRE)
2739 if (cpu_of_arch (current_architecture) & cpu32)
2740 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2744 if (isvar (&opP->odisp)
2746 : ! issword (outro))
2751 else if (! isvar (&opP->odisp) && outro == 0)
2760 as_warn (_(":b not permitted; defaulting to :w"));
2769 if (opP->mode == POST
2770 && (nextword & 0x40) == 0)
2775 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2777 if (opP->reg == PC || opP->reg == ZPC)
2778 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2780 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2782 if (siz1 == SIZE_LONG)
2783 addword (baseo >> 16);
2784 if (siz1 != SIZE_UNSPEC)
2787 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2788 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2789 if (siz2 == SIZE_LONG)
2790 addword (outro >> 16);
2791 if (siz2 != SIZE_UNSPEC)
2797 nextword = get_num (&opP->disp, 90);
2798 switch (opP->disp.size)
2803 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2805 tmpreg = 0x38; /* 7.0 */
2809 if (isvar (&opP->disp)
2810 && !subs (&opP->disp)
2811 && adds (&opP->disp)
2813 /* If the displacement needs pic relocation it
2814 cannot be relaxed. */
2815 && opP->disp.pic_reloc == pic_none
2818 && !strchr ("~%&$?", s[0]))
2820 tmpreg = 0x3A; /* 7.2 */
2821 add_frag (adds (&opP->disp),
2822 SEXT (offs (&opP->disp)),
2823 TAB (ABSTOPCREL, SZ_UNDEF));
2826 /* Fall through into long. */
2828 if (isvar (&opP->disp))
2829 add_fix ('l', &opP->disp, 0, 0);
2831 tmpreg = 0x39;/* 7.1 mode */
2832 addword (nextword >> 16);
2837 as_bad (_("unsupported byte value; use a different suffix"));
2841 if (isvar (&opP->disp))
2842 add_fix ('w', &opP->disp, 0, 0);
2844 tmpreg = 0x38;/* 7.0 mode */
2852 as_bad (_("unknown/incorrect operand"));
2856 /* If s[0] is '4', then this is for the mac instructions
2857 that can have a trailing_ampersand set. If so, set 0x100
2858 bit on tmpreg so install_gen_operand can check for it and
2859 set the appropriate bit (word2, bit 5). */
2862 if (opP->trailing_ampersand)
2865 install_gen_operand (s[1], tmpreg);
2871 { /* JF: I hate floating point! */
2886 tmpreg = get_num (&opP->disp, tmpreg);
2887 if (isvar (&opP->disp))
2888 add_fix (s[1], &opP->disp, 0, 0);
2891 case 'b': /* Danger: These do no check for
2892 certain types of overflow.
2894 if (!isbyte (tmpreg))
2895 opP->error = _("out of range");
2896 insop (tmpreg, opcode);
2897 if (isvar (&opP->disp))
2898 the_ins.reloc[the_ins.nrel - 1].n =
2899 (opcode->m_codenum) * 2 + 1;
2902 if (!issbyte (tmpreg))
2903 opP->error = _("out of range");
2904 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2905 if (isvar (&opP->disp))
2906 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2909 if (!isword (tmpreg))
2910 opP->error = _("out of range");
2911 insop (tmpreg, opcode);
2912 if (isvar (&opP->disp))
2913 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2916 if (!issword (tmpreg))
2917 opP->error = _("out of range");
2918 insop (tmpreg, opcode);
2919 if (isvar (&opP->disp))
2920 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2923 /* Because of the way insop works, we put these two out
2925 insop (tmpreg, opcode);
2926 insop (tmpreg >> 16, opcode);
2927 if (isvar (&opP->disp))
2928 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2935 install_operand (s[1], tmpreg);
2946 install_operand (s[1], opP->reg - ADDR);
2950 tmpreg = get_num (&opP->disp, 90);
2955 add_fix ('B', &opP->disp, 1, -1);
2958 add_fix ('w', &opP->disp, 1, 0);
2963 the_ins.opcode[0] |= 0xff;
2964 add_fix ('l', &opP->disp, 1, 0);
2968 case 'g': /* Conditional branch */
2969 have_disp = HAVE_LONG_CALL (current_architecture);
2972 case 'b': /* Unconditional branch */
2973 have_disp = HAVE_LONG_BRANCH (current_architecture);
2974 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
2977 case 's': /* Unconditional subroutine */
2978 have_disp = HAVE_LONG_CALL (current_architecture);
2981 if (subs (&opP->disp) /* We can't relax it. */
2983 /* If the displacement needs pic relocation it cannot be
2985 || opP->disp.pic_reloc != pic_none
2990 as_warn (_("Can't use long branches on this architecture"));
2994 /* This could either be a symbol, or an absolute
2995 address. If it's an absolute address, turn it into
2996 an absolute jump right here and keep it out of the
2998 if (adds (&opP->disp) == 0)
3000 if (the_ins.opcode[0] == 0x6000) /* jbra */
3001 the_ins.opcode[0] = 0x4EF9;
3002 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
3003 the_ins.opcode[0] = 0x4EB9;
3006 the_ins.opcode[0] ^= 0x0100;
3007 the_ins.opcode[0] |= 0x0006;
3010 add_fix ('l', &opP->disp, 0, 0);
3016 /* Now we know it's going into the relaxer. Now figure
3017 out which mode. We try in this order of preference:
3018 long branch, absolute jump, byte/word branches only. */
3020 add_frag (adds (&opP->disp),
3021 SEXT (offs (&opP->disp)),
3022 TAB (BRANCHBWL, SZ_UNDEF));
3023 else if (! flag_keep_pcrel)
3025 if ((the_ins.opcode[0] == 0x6000)
3026 || (the_ins.opcode[0] == 0x6100))
3027 add_frag (adds (&opP->disp),
3028 SEXT (offs (&opP->disp)),
3029 TAB (BRABSJUNC, SZ_UNDEF));
3031 add_frag (adds (&opP->disp),
3032 SEXT (offs (&opP->disp)),
3033 TAB (BRABSJCOND, SZ_UNDEF));
3036 add_frag (adds (&opP->disp),
3037 SEXT (offs (&opP->disp)),
3038 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3039 : TAB (BRANCHBW, SZ_UNDEF)));
3042 if (isvar (&opP->disp))
3044 /* Check for DBcc instructions. We can relax them,
3045 but only if we have long branches and/or absolute
3047 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3048 && (HAVE_LONG_BRANCH (current_architecture)
3049 || ! flag_keep_pcrel))
3051 if (HAVE_LONG_BRANCH (current_architecture))
3052 add_frag (adds (&opP->disp),
3053 SEXT (offs (&opP->disp)),
3054 TAB (DBCCLBR, SZ_UNDEF));
3056 add_frag (adds (&opP->disp),
3057 SEXT (offs (&opP->disp)),
3058 TAB (DBCCABSJ, SZ_UNDEF));
3061 add_fix ('w', &opP->disp, 1, 0);
3065 case 'C': /* Fixed size LONG coproc branches. */
3066 add_fix ('l', &opP->disp, 1, 0);
3070 case 'c': /* Var size Coprocesssor branches. */
3071 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3073 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3074 add_fix ('l', &opP->disp, 1, 0);
3079 add_frag (adds (&opP->disp),
3080 SEXT (offs (&opP->disp)),
3081 TAB (FBRANCH, SZ_UNDEF));
3088 case 'C': /* Ignore it. */
3091 case 'd': /* JF this is a kludge. */
3092 install_operand ('s', opP->reg - ADDR);
3093 tmpreg = get_num (&opP->disp, 90);
3094 if (!issword (tmpreg))
3096 as_warn (_("Expression out of range, using 0"));
3103 install_operand (s[1], opP->reg - DATA);
3106 case 'e': /* EMAC ACCx, reg/reg. */
3107 install_operand (s[1], opP->reg - ACC);
3110 case 'E': /* Ignore it. */
3114 install_operand (s[1], opP->reg - FP0);
3117 case 'g': /* EMAC ACCEXTx. */
3118 install_operand (s[1], opP->reg - ACCEXT01);
3121 case 'G': /* Ignore it. */
3126 tmpreg = opP->reg - COP0;
3127 install_operand (s[1], tmpreg);
3130 case 'i': /* MAC/EMAC scale factor. */
3131 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3134 case 'J': /* JF foo. */
3274 install_operand (s[1], tmpreg);
3278 tmpreg = get_num (&opP->disp, 55);
3279 install_operand (s[1], tmpreg & 0x7f);
3286 if (tmpreg & 0x7FF0000)
3287 as_bad (_("Floating point register in register list"));
3288 insop (reverse_16_bits (tmpreg), opcode);
3292 if (tmpreg & 0x700FFFF)
3293 as_bad (_("Wrong register in floating-point reglist"));
3294 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3302 if (tmpreg & 0x7FF0000)
3303 as_bad (_("Floating point register in register list"));
3304 insop (tmpreg, opcode);
3306 else if (s[1] == '8')
3308 if (tmpreg & 0x0FFFFFF)
3309 as_bad (_("incorrect register in reglist"));
3310 install_operand (s[1], tmpreg >> 24);
3314 if (tmpreg & 0x700FFFF)
3315 as_bad (_("wrong register in floating-point reglist"));
3317 install_operand (s[1], tmpreg >> 16);
3322 install_operand (s[1], get_num (&opP->disp, 60));
3326 tmpreg = ((opP->mode == DREG)
3327 ? 0x20 + (int) (opP->reg - DATA)
3328 : (get_num (&opP->disp, 40) & 0x1F));
3329 install_operand (s[1], tmpreg);
3333 tmpreg = get_num (&opP->disp, 10);
3336 install_operand (s[1], tmpreg);
3340 /* This depends on the fact that ADDR registers are eight
3341 more than their corresponding DATA regs, so the result
3342 will have the ADDR_REG bit set. */
3343 install_operand (s[1], opP->reg - DATA);
3347 if (opP->mode == AINDR)
3348 install_operand (s[1], opP->reg - DATA);
3350 install_operand (s[1], opP->index.reg - DATA);
3354 if (opP->reg == FPI)
3356 else if (opP->reg == FPS)
3358 else if (opP->reg == FPC)
3362 install_operand (s[1], tmpreg);
3365 case 'S': /* Ignore it. */
3369 install_operand (s[1], get_num (&opP->disp, 30));
3372 case 'U': /* Ignore it. */
3391 as_fatal (_("failed sanity check"));
3392 } /* switch on cache token. */
3393 install_operand (s[1], tmpreg);
3396 /* JF: These are out of order, I fear. */
3409 install_operand (s[1], tmpreg);
3435 install_operand (s[1], tmpreg);
3439 if (opP->reg == VAL)
3458 install_operand (s[1], tmpreg);
3472 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3483 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3489 install_operand (s[1], tmpreg);
3492 know (opP->reg == PSR);
3495 know (opP->reg == PCSR);
3510 install_operand (s[1], tmpreg);
3513 tmpreg = get_num (&opP->disp, 20);
3514 install_operand (s[1], tmpreg);
3516 case '_': /* used only for move16 absolute 32-bit address. */
3517 if (isvar (&opP->disp))
3518 add_fix ('l', &opP->disp, 0, 0);
3519 tmpreg = get_num (&opP->disp, 90);
3520 addword (tmpreg >> 16);
3521 addword (tmpreg & 0xFFFF);
3524 install_operand (s[1], opP->reg - DATA0L);
3525 opP->reg -= (DATA0L);
3526 opP->reg &= 0x0F; /* remove upper/lower bit. */
3529 tmpreg = get_num (&opP->disp, 80);
3532 install_operand (s[1], tmpreg);
3535 tmpreg = get_num (&opP->disp, 10);
3536 install_operand (s[1], tmpreg - 1);
3539 tmpreg = get_num (&opP->disp, 65);
3540 install_operand (s[1], tmpreg);
3547 /* By the time whe get here (FINALLY) the_ins contains the complete
3548 instruction, ready to be emitted. . . */
3552 reverse_16_bits (int in)
3557 static int mask[16] =
3559 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3560 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3562 for (n = 0; n < 16; n++)
3565 out |= mask[15 - n];
3568 } /* reverse_16_bits() */
3571 reverse_8_bits (int in)
3576 static int mask[8] =
3578 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3581 for (n = 0; n < 8; n++)
3587 } /* reverse_8_bits() */
3589 /* Cause an extra frag to be generated here, inserting up to
3590 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3591 generated; its primary type is rs_machine_dependent.
3593 The TYPE parameter is also used by md_convert_frag_1 and
3594 md_estimate_size_before_relax. The appropriate type of fixup will
3595 be emitted by md_convert_frag_1.
3597 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3599 install_operand (int mode, int val)
3604 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3607 the_ins.opcode[0] |= val << 9;
3610 the_ins.opcode[1] |= val << 9;
3613 the_ins.opcode[1] |= val << 12;
3616 the_ins.opcode[1] |= val << 6;
3619 the_ins.opcode[1] |= val;
3622 the_ins.opcode[2] |= val << 12;
3625 the_ins.opcode[2] |= val << 6;
3628 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3629 three words long! */
3631 the_ins.opcode[2] |= val;
3634 the_ins.opcode[1] |= val << 7;
3637 the_ins.opcode[1] |= val << 10;
3641 the_ins.opcode[1] |= val << 5;
3646 the_ins.opcode[1] |= (val << 10) | (val << 7);
3649 the_ins.opcode[1] |= (val << 12) | val;
3652 the_ins.opcode[0] |= val = 0xff;
3655 the_ins.opcode[0] |= val << 9;
3658 the_ins.opcode[1] |= val;
3661 the_ins.opcode[1] |= val;
3662 the_ins.numo++; /* What a hack. */
3665 the_ins.opcode[1] |= val << 4;
3673 the_ins.opcode[0] |= (val << 6);
3676 the_ins.opcode[1] = (val >> 16);
3677 the_ins.opcode[2] = val & 0xffff;
3680 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3681 the_ins.opcode[0] |= ((val & 0x7) << 9);
3682 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3684 case 'n': /* MAC/EMAC Rx on !load. */
3685 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3686 the_ins.opcode[0] |= ((val & 0x7) << 9);
3687 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3689 case 'o': /* MAC/EMAC Rx on load. */
3690 the_ins.opcode[1] |= val << 12;
3691 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3693 case 'M': /* MAC/EMAC Ry on !load. */
3694 the_ins.opcode[0] |= (val & 0xF);
3695 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3697 case 'N': /* MAC/EMAC Ry on load. */
3698 the_ins.opcode[1] |= (val & 0xF);
3699 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3702 the_ins.opcode[1] |= ((val != 1) << 10);
3705 the_ins.opcode[0] |= ((val & 0x3) << 9);
3708 the_ins.opcode[0] |= ((val & 0x3) << 0);
3710 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3711 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3712 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3714 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3715 the_ins.opcode[0] |= ((val & 0x1) << 7);
3716 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3719 the_ins.opcode[1] |= ((val & 0x3) << 9);
3722 the_ins.opcode[0] |= (val & 0x1) <<10;
3726 as_fatal (_("failed sanity check."));
3731 install_gen_operand (int mode, int val)
3735 case '/': /* Special for mask loads for mac/msac insns with
3736 possible mask; trailing_ampersend set in bit 8. */
3737 the_ins.opcode[0] |= (val & 0x3f);
3738 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3741 the_ins.opcode[0] |= val;
3744 /* This is a kludge!!! */
3745 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3754 the_ins.opcode[0] |= val;
3756 /* more stuff goes here. */
3758 as_fatal (_("failed sanity check."));
3762 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3763 then deal with the bitfield hack. */
3766 crack_operand (char *str, struct m68k_op *opP)
3768 register int parens;
3770 register char *beg_str;
3778 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3784 else if (*str == ')')
3788 opP->error = _("Extra )");
3794 if (flag_mri && *str == '\'')
3795 inquote = ! inquote;
3797 if (!*str && parens)
3799 opP->error = _("Missing )");
3804 if (m68k_ip_op (beg_str, opP) != 0)
3811 c = *++str; /* JF bitfield hack. */
3816 as_bad (_("Missing operand"));
3819 /* Detect MRI REG symbols and convert them to REGLSTs. */
3820 if (opP->mode == CONTROL && (int)opP->reg < 0)
3823 opP->mask = ~(int)opP->reg;
3830 /* This is the guts of the machine-dependent assembler. STR points to a
3831 machine dependent instruction. This function is supposed to emit
3832 the frags/bytes it assembles to.
3836 insert_reg (const char *regname, int regnum)
3841 #ifdef REGISTER_PREFIX
3842 if (!flag_reg_prefix_optional)
3844 buf[0] = REGISTER_PREFIX;
3845 strcpy (buf + 1, regname);
3850 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3851 &zero_address_frag));
3853 for (i = 0; regname[i]; i++)
3854 buf[i] = TOUPPER (regname[i]);
3857 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3858 &zero_address_frag));
3867 static const struct init_entry init_table[] =
3927 { "accext01", ACCEXT01 },
3928 { "accext23", ACCEXT23 },
3932 /* Control registers. */
3933 { "sfc", SFC }, /* Source Function Code. */
3935 { "dfc", DFC }, /* Destination Function Code. */
3937 { "cacr", CACR }, /* Cache Control Register. */
3938 { "caar", CAAR }, /* Cache Address Register. */
3940 { "usp", USP }, /* User Stack Pointer. */
3941 { "vbr", VBR }, /* Vector Base Register. */
3942 { "msp", MSP }, /* Master Stack Pointer. */
3943 { "isp", ISP }, /* Interrupt Stack Pointer. */
3945 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3946 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3947 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3948 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3950 /* 68ec040 versions of same */
3951 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3952 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3953 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3954 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3956 /* Coldfire versions of same. The ColdFire programmer's reference
3957 manual indicated that the order is 2,3,0,1, but Ken Rose
3958 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3959 { "acr0", ACR0 }, /* Access Control Unit 0. */
3960 { "acr1", ACR1 }, /* Access Control Unit 1. */
3961 { "acr2", ACR2 }, /* Access Control Unit 2. */
3962 { "acr3", ACR3 }, /* Access Control Unit 3. */
3964 { "tc", TC }, /* MMU Translation Control Register. */
3968 { "mmusr", MMUSR }, /* MMU Status Register. */
3969 { "srp", SRP }, /* User Root Pointer. */
3970 { "urp", URP }, /* Supervisor Root Pointer. */
3973 { "mmubar", MMUBAR },
3976 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3977 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3978 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3979 { "mbar", MBAR }, /* Module Base Address Register. */
3981 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3982 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3983 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3984 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3985 { "mpcr", MPCR }, /* mcfv4e registers. */
3986 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3987 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3988 { "asid", TC }, /* mcfv4e registers. */
3989 { "mmubar", BUSCR }, /* mcfv4e registers. */
3990 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3991 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3992 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3993 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3994 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3995 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3996 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3997 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3998 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3999 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4000 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4001 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4003 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4004 { "rambar", RAMBAR }, /* mcf528x registers. */
4006 { "mbar2", MBAR2 }, /* mcf5249 registers. */
4008 { "cac", CAC }, /* fido registers. */
4009 { "mbb", MBO }, /* fido registers (obsolete). */
4010 { "mbo", MBO }, /* fido registers. */
4011 /* End of control registers. */
4045 /* 68ec030 versions of same. */
4048 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4051 /* Suppressed data and address registers. */
4069 /* Upper and lower data and address registers, used by macw and msacw. */
4110 init_regtable (void)
4113 for (i = 0; init_table[i].name; i++)
4114 insert_reg (init_table[i].name, init_table[i].number);
4118 md_assemble (char *str)
4125 int shorts_this_frag;
4128 if (!selected_cpu && !selected_arch)
4130 /* We've not selected an architecture yet. Set the default
4131 now. We do this lazily so that an initial .cpu or .arch directive
4133 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4134 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4139 /* In MRI mode, the instruction and operands are separated by a
4140 space. Anything following the operands is a comment. The label
4141 has already been removed. */
4149 for (s = str; *s != '\0'; s++)
4151 if ((*s == ' ' || *s == '\t') && ! inquote)
4169 inquote = ! inquote;
4174 memset (&the_ins, '\0', sizeof (the_ins));
4179 for (n = 0; n < the_ins.numargs; n++)
4180 if (the_ins.operands[n].error)
4182 er = the_ins.operands[n].error;
4188 as_bad (_("%s -- statement `%s' ignored"), er, str);
4192 /* If there is a current label, record that it marks an instruction. */
4193 if (current_label != NULL)
4195 current_label->text = 1;
4196 current_label = NULL;
4200 /* Tie dwarf2 debug info to the address at the start of the insn. */
4201 dwarf2_emit_insn (0);
4204 if (the_ins.nfrag == 0)
4206 /* No frag hacking involved; just put it out. */
4207 toP = frag_more (2 * the_ins.numo);
4208 fromP = &the_ins.opcode[0];
4209 for (m = the_ins.numo; m; --m)
4211 md_number_to_chars (toP, (long) (*fromP), 2);
4215 /* Put out symbol-dependent info. */
4216 for (m = 0; m < the_ins.nrel; m++)
4218 switch (the_ins.reloc[m].wid)
4237 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4238 the_ins.reloc[m].wid);
4241 fixP = fix_new_exp (frag_now,
4242 ((toP - frag_now->fr_literal)
4243 - the_ins.numo * 2 + the_ins.reloc[m].n),
4245 &the_ins.reloc[m].exp,
4246 the_ins.reloc[m].pcrel,
4247 get_reloc_code (n, the_ins.reloc[m].pcrel,
4248 the_ins.reloc[m].pic_reloc));
4249 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4250 if (the_ins.reloc[m].wid == 'B')
4251 fixP->fx_signed = 1;
4256 /* There's some frag hacking. */
4258 /* Calculate the max frag size. */
4261 wid = 2 * the_ins.fragb[0].fragoff;
4262 for (n = 1; n < the_ins.nfrag; n++)
4263 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4264 /* frag_var part. */
4265 wid += FRAG_VAR_SIZE;
4266 /* Make sure the whole insn fits in one chunk, in particular that
4267 the var part is attached, as we access one byte before the
4268 variable frag for byte branches. */
4272 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4277 wid = 2 * the_ins.fragb[n].fragoff;
4279 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4280 toP = frag_more (wid);
4282 shorts_this_frag = 0;
4283 for (m = wid / 2; m; --m)
4285 md_number_to_chars (toP, (long) (*fromP), 2);
4290 for (m = 0; m < the_ins.nrel; m++)
4292 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4294 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4297 wid = the_ins.reloc[m].wid;
4300 the_ins.reloc[m].wid = 0;
4301 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4303 fixP = fix_new_exp (frag_now,
4304 ((toP - frag_now->fr_literal)
4305 - the_ins.numo * 2 + the_ins.reloc[m].n),
4307 &the_ins.reloc[m].exp,
4308 the_ins.reloc[m].pcrel,
4309 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4310 the_ins.reloc[m].pic_reloc));
4311 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4313 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4314 (relax_substateT) (the_ins.fragb[n].fragty),
4315 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4317 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4318 shorts_this_frag = 0;
4321 toP = frag_more (n * 2);
4324 md_number_to_chars (toP, (long) (*fromP), 2);
4330 for (m = 0; m < the_ins.nrel; m++)
4334 wid = the_ins.reloc[m].wid;
4337 the_ins.reloc[m].wid = 0;
4338 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4340 fixP = fix_new_exp (frag_now,
4341 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4342 - shorts_this_frag * 2),
4344 &the_ins.reloc[m].exp,
4345 the_ins.reloc[m].pcrel,
4346 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4347 the_ins.reloc[m].pic_reloc));
4348 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4352 /* Comparison function used by qsort to rank the opcode entries by name. */
4355 m68k_compare_opcode (const void * v1, const void * v2)
4357 struct m68k_opcode * op1, * op2;
4363 op1 = *(struct m68k_opcode **) v1;
4364 op2 = *(struct m68k_opcode **) v2;
4366 /* Compare the two names. If different, return the comparison.
4367 If the same, return the order they are in the opcode table. */
4368 ret = strcmp (op1->name, op2->name);
4379 const struct m68k_opcode *ins;
4380 struct m68k_incant *hack, *slak;
4381 const char *retval = 0; /* Empty string, or error msg text. */
4384 /* Set up hash tables with 68000 instructions.
4385 similar to what the vax assembler does. */
4386 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4387 a copy of it at runtime, adding in the information we want but isn't
4388 there. I think it'd be better to have an awk script hack the table
4389 at compile time. Or even just xstr the table and use it as-is. But
4390 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4395 flag_reg_prefix_optional = 1;
4397 if (! m68k_rel32_from_cmdline)
4401 /* First sort the opcode table into alphabetical order to seperate
4402 the order that the assembler wants to see the opcodes from the
4403 order that the disassembler wants to see them. */
4404 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4405 if (!m68k_sorted_opcodes)
4406 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4407 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4409 for (i = m68k_numopcodes; i--;)
4410 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4412 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4413 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4415 op_hash = hash_new ();
4417 obstack_begin (&robyn, 4000);
4418 for (i = 0; i < m68k_numopcodes; i++)
4420 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4423 ins = m68k_sorted_opcodes[i];
4425 /* We must enter all insns into the table, because .arch and
4426 .cpu directives can change things. */
4427 slak->m_operands = ins->args;
4428 slak->m_arch = ins->arch;
4429 slak->m_opcode = ins->opcode;
4431 /* In most cases we can determine the number of opcode words
4432 by checking the second word of the mask. Unfortunately
4433 some instructions have 2 opcode words, but no fixed bits
4434 in the second word. A leading dot in the operands
4435 string also indicates 2 opcodes. */
4436 if (*slak->m_operands == '.')
4439 slak->m_codenum = 2;
4441 else if (ins->match & 0xffffL)
4442 slak->m_codenum = 2;
4444 slak->m_codenum = 1;
4445 slak->m_opnum = strlen (slak->m_operands) / 2;
4447 if (i + 1 != m68k_numopcodes
4448 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4450 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4455 slak = slak->m_next;
4459 retval = hash_insert (op_hash, ins->name, (char *) hack);
4461 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4464 for (i = 0; i < m68k_numaliases; i++)
4466 const char *name = m68k_opcode_aliases[i].primary;
4467 const char *alias = m68k_opcode_aliases[i].alias;
4468 PTR val = hash_find (op_hash, name);
4471 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4472 retval = hash_insert (op_hash, alias, val);
4474 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4477 /* In MRI mode, all unsized branches are variable sized. Normally,
4478 they are word sized. */
4481 static struct m68k_opcode_alias mri_aliases[] =
4502 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4505 const char *name = mri_aliases[i].primary;
4506 const char *alias = mri_aliases[i].alias;
4507 PTR val = hash_find (op_hash, name);
4510 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4511 retval = hash_jam (op_hash, alias, val);
4513 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4517 for (i = 0; i < (int) sizeof (notend_table); i++)
4519 notend_table[i] = 0;
4520 alt_notend_table[i] = 0;
4523 notend_table[','] = 1;
4524 notend_table['{'] = 1;
4525 notend_table['}'] = 1;
4526 alt_notend_table['a'] = 1;
4527 alt_notend_table['A'] = 1;
4528 alt_notend_table['d'] = 1;
4529 alt_notend_table['D'] = 1;
4530 alt_notend_table['#'] = 1;
4531 alt_notend_table['&'] = 1;
4532 alt_notend_table['f'] = 1;
4533 alt_notend_table['F'] = 1;
4534 #ifdef REGISTER_PREFIX
4535 alt_notend_table[REGISTER_PREFIX] = 1;
4538 /* We need to put '(' in alt_notend_table to handle
4539 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4540 alt_notend_table['('] = 1;
4542 /* We need to put '@' in alt_notend_table to handle
4543 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4544 alt_notend_table['@'] = 1;
4546 /* We need to put digits in alt_notend_table to handle
4547 bfextu %d0{24:1},%d0 */
4548 alt_notend_table['0'] = 1;
4549 alt_notend_table['1'] = 1;
4550 alt_notend_table['2'] = 1;
4551 alt_notend_table['3'] = 1;
4552 alt_notend_table['4'] = 1;
4553 alt_notend_table['5'] = 1;
4554 alt_notend_table['6'] = 1;
4555 alt_notend_table['7'] = 1;
4556 alt_notend_table['8'] = 1;
4557 alt_notend_table['9'] = 1;
4559 #ifndef MIT_SYNTAX_ONLY
4560 /* Insert pseudo ops, these have to go into the opcode table since
4561 gas expects pseudo ops to start with a dot. */
4565 while (mote_pseudo_table[n].poc_name)
4567 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4568 hash_insert (op_hash,
4569 mote_pseudo_table[n].poc_name, (char *) hack);
4570 hack->m_operands = 0;
4580 record_alignment (text_section, 2);
4581 record_alignment (data_section, 2);
4582 record_alignment (bss_section, 2);
4587 /* This is called when a label is defined. */
4590 m68k_frob_label (symbolS *sym)
4592 struct label_line *n;
4594 n = (struct label_line *) xmalloc (sizeof *n);
4597 as_where (&n->file, &n->line);
4603 dwarf2_emit_label (sym);
4607 /* This is called when a value that is not an instruction is emitted. */
4610 m68k_flush_pending_output (void)
4612 current_label = NULL;
4615 /* This is called at the end of the assembly, when the final value of
4616 the label is known. We warn if this is a text symbol aligned at an
4620 m68k_frob_symbol (symbolS *sym)
4622 if (S_GET_SEGMENT (sym) == reg_section
4623 && (int) S_GET_VALUE (sym) < 0)
4625 S_SET_SEGMENT (sym, absolute_section);
4626 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4628 else if ((S_GET_VALUE (sym) & 1) != 0)
4630 struct label_line *l;
4632 for (l = labels; l != NULL; l = l->next)
4634 if (l->label == sym)
4637 as_warn_where (l->file, l->line,
4638 _("text label `%s' aligned to odd boundary"),
4646 /* This is called if we go in or out of MRI mode because of the .mri
4650 m68k_mri_mode_change (int on)
4654 if (! flag_reg_prefix_optional)
4656 flag_reg_prefix_optional = 1;
4657 #ifdef REGISTER_PREFIX
4662 if (! m68k_rel32_from_cmdline)
4667 if (! reg_prefix_optional_seen)
4669 #ifdef REGISTER_PREFIX_OPTIONAL
4670 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4672 flag_reg_prefix_optional = 0;
4674 #ifdef REGISTER_PREFIX
4679 if (! m68k_rel32_from_cmdline)
4685 md_atof (int type, char *litP, int *sizeP)
4687 return ieee_md_atof (type, litP, sizeP, TRUE);
4691 md_number_to_chars (char *buf, valueT val, int n)
4693 number_to_chars_bigendian (buf, val, n);
4697 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4699 offsetT val = *valP;
4700 addressT upper_limit;
4701 offsetT lower_limit;
4703 /* This is unnecessary but it convinces the native rs6000 compiler
4704 to generate the code we want. */
4705 char *buf = fixP->fx_frag->fr_literal;
4706 buf += fixP->fx_where;
4707 /* End ibm compiler workaround. */
4711 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4717 memset (buf, 0, fixP->fx_size);
4718 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4720 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4721 && !S_IS_DEFINED (fixP->fx_addsy)
4722 && !S_IS_WEAK (fixP->fx_addsy))
4723 S_SET_WEAK (fixP->fx_addsy);
4726 #elif defined(OBJ_AOUT)
4727 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4728 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4730 memset (buf, 0, fixP->fx_size);
4731 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4736 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4737 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4740 switch (fixP->fx_size)
4742 /* The cast to offsetT below are necessary to make code
4743 correct for machines where ints are smaller than offsetT. */
4747 lower_limit = - (offsetT) 0x80;
4750 *buf++ = (val >> 8);
4752 upper_limit = 0x7fff;
4753 lower_limit = - (offsetT) 0x8000;
4756 *buf++ = (val >> 24);
4757 *buf++ = (val >> 16);
4758 *buf++ = (val >> 8);
4760 upper_limit = 0x7fffffff;
4761 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4764 BAD_CASE (fixP->fx_size);
4767 /* Fix up a negative reloc. */
4768 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4770 fixP->fx_addsy = fixP->fx_subsy;
4771 fixP->fx_subsy = NULL;
4775 /* For non-pc-relative values, it's conceivable we might get something
4776 like "0xff" for a byte field. So extend the upper part of the range
4777 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4778 so that we can do any range checking at all. */
4779 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4780 upper_limit = upper_limit * 2 + 1;
4782 if ((addressT) val > upper_limit
4783 && (val > 0 || val < lower_limit))
4784 as_bad_where (fixP->fx_file, fixP->fx_line,
4785 _("value %ld out of range"), (long)val);
4787 /* A one byte PC-relative reloc means a short branch. We can't use
4788 a short branch with a value of 0 or -1, because those indicate
4789 different opcodes (branches with longer offsets). fixup_segment
4790 in write.c may have clobbered fx_pcrel, so we need to examine the
4793 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4794 && fixP->fx_size == 1
4795 && (fixP->fx_addsy == NULL
4796 || S_IS_DEFINED (fixP->fx_addsy))
4797 && (val == 0 || val == -1))
4798 as_bad_where (fixP->fx_file, fixP->fx_line,
4799 _("invalid byte branch offset"));
4802 /* *fragP has been relaxed to its final size, and now needs to have
4803 the bytes inside it modified to conform to the new size There is UGLY
4807 md_convert_frag_1 (fragS *fragP)
4812 /* Address in object code of the displacement. */
4813 register int object_address = fragP->fr_fix + fragP->fr_address;
4815 /* Address in gas core of the place to store the displacement. */
4816 /* This convinces the native rs6000 compiler to generate the code we
4818 register char *buffer_address = fragP->fr_literal;
4819 buffer_address += fragP->fr_fix;
4820 /* End ibm compiler workaround. */
4822 /* The displacement of the address, from current location. */
4823 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4824 disp = (disp + fragP->fr_offset) - object_address;
4826 switch (fragP->fr_subtype)
4828 case TAB (BRANCHBWL, BYTE):
4829 case TAB (BRABSJUNC, BYTE):
4830 case TAB (BRABSJCOND, BYTE):
4831 case TAB (BRANCHBW, BYTE):
4832 case TAB (BRANCHBWPL, BYTE):
4833 know (issbyte (disp));
4835 as_bad_where (fragP->fr_file, fragP->fr_line,
4836 _("short branch with zero offset: use :w"));
4837 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4838 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4839 fixP->fx_pcrel_adjust = -1;
4841 case TAB (BRANCHBWL, SHORT):
4842 case TAB (BRABSJUNC, SHORT):
4843 case TAB (BRABSJCOND, SHORT):
4844 case TAB (BRANCHBW, SHORT):
4845 case TAB (BRANCHBWPL, SHORT):
4846 fragP->fr_opcode[1] = 0x00;
4847 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4848 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4851 case TAB (BRANCHBWL, LONG):
4852 fragP->fr_opcode[1] = (char) 0xFF;
4853 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4854 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4857 case TAB (BRANCHBWPL, LONG):
4858 /* Here we are converting an unconditional branch into a pair of
4859 conditional branches, in order to get the range. */
4860 fragP->fr_opcode[0] = 0x66; /* bne */
4861 fragP->fr_opcode[1] = 0xFF;
4862 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4863 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4864 fixP->fx_file = fragP->fr_file;
4865 fixP->fx_line = fragP->fr_line;
4866 fragP->fr_fix += 4; /* Skip first offset */
4867 buffer_address += 4;
4868 *buffer_address++ = 0x67; /* beq */
4869 *buffer_address++ = 0xff;
4870 fragP->fr_fix += 2; /* Skip second branch opcode */
4871 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4872 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4875 case TAB (BRABSJUNC, LONG):
4876 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4878 if (flag_keep_pcrel)
4879 as_bad_where (fragP->fr_file, fragP->fr_line,
4880 _("Conversion of PC relative BSR to absolute JSR"));
4881 fragP->fr_opcode[0] = 0x4E;
4882 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4883 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4884 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4887 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4889 if (flag_keep_pcrel)
4890 as_bad_where (fragP->fr_file, fragP->fr_line,
4891 _("Conversion of PC relative branch to absolute jump"));
4892 fragP->fr_opcode[0] = 0x4E;
4893 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4894 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4895 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4900 /* This cannot happen, because jbsr and jbra are the only two
4901 unconditional branches. */
4905 case TAB (BRABSJCOND, LONG):
4906 if (flag_keep_pcrel)
4907 as_bad_where (fragP->fr_file, fragP->fr_line,
4908 _("Conversion of PC relative conditional branch to absolute jump"));
4910 /* Only Bcc 68000 instructions can come here
4911 Change bcc into b!cc/jmp absl long. */
4912 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4913 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4915 /* JF: these used to be fr_opcode[2,3], but they may be in a
4916 different frag, in which case referring to them is a no-no.
4917 Only fr_opcode[0,1] are guaranteed to work. */
4918 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4919 *buffer_address++ = (char) 0xf9;
4920 fragP->fr_fix += 2; /* Account for jmp instruction. */
4921 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4922 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4925 case TAB (FBRANCH, SHORT):
4926 know ((fragP->fr_opcode[1] & 0x40) == 0);
4927 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4928 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4931 case TAB (FBRANCH, LONG):
4932 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4933 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4934 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4937 case TAB (DBCCLBR, SHORT):
4938 case TAB (DBCCABSJ, SHORT):
4939 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4940 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4943 case TAB (DBCCLBR, LONG):
4944 /* Only DBcc instructions can come here.
4945 Change dbcc into dbcc/bral.
4946 JF: these used to be fr_opcode[2-7], but that's wrong. */
4947 if (flag_keep_pcrel)
4948 as_bad_where (fragP->fr_file, fragP->fr_line,
4949 _("Conversion of DBcc to absolute jump"));
4951 *buffer_address++ = 0x00; /* Branch offset = 4. */
4952 *buffer_address++ = 0x04;
4953 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4954 *buffer_address++ = 0x06;
4955 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4956 *buffer_address++ = (char) 0xff;
4958 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4959 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4960 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4963 case TAB (DBCCABSJ, LONG):
4964 /* Only DBcc instructions can come here.
4965 Change dbcc into dbcc/jmp.
4966 JF: these used to be fr_opcode[2-7], but that's wrong. */
4967 if (flag_keep_pcrel)
4968 as_bad_where (fragP->fr_file, fragP->fr_line,
4969 _("Conversion of PC relative conditional branch to absolute jump"));
4971 *buffer_address++ = 0x00; /* Branch offset = 4. */
4972 *buffer_address++ = 0x04;
4973 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4974 *buffer_address++ = 0x06;
4975 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4976 *buffer_address++ = (char) 0xf9;
4978 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4979 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4980 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4983 case TAB (PCREL1632, SHORT):
4984 fragP->fr_opcode[1] &= ~0x3F;
4985 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4986 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4987 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4990 case TAB (PCREL1632, LONG):
4991 /* Already set to mode 7.3; this indicates: PC indirect with
4992 suppressed index, 32-bit displacement. */
4993 *buffer_address++ = 0x01;
4994 *buffer_address++ = 0x70;
4996 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4997 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4998 fixP->fx_pcrel_adjust = 2;
5001 case TAB (PCINDEX, BYTE):
5002 assert (fragP->fr_fix >= 2);
5003 buffer_address[-2] &= ~1;
5004 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5005 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5006 fixP->fx_pcrel_adjust = 1;
5008 case TAB (PCINDEX, SHORT):
5009 assert (fragP->fr_fix >= 2);
5010 buffer_address[-2] |= 0x1;
5011 buffer_address[-1] = 0x20;
5012 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5013 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5014 fixP->fx_pcrel_adjust = 2;
5017 case TAB (PCINDEX, LONG):
5018 assert (fragP->fr_fix >= 2);
5019 buffer_address[-2] |= 0x1;
5020 buffer_address[-1] = 0x30;
5021 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5022 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5023 fixP->fx_pcrel_adjust = 2;
5026 case TAB (ABSTOPCREL, SHORT):
5027 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5028 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5031 case TAB (ABSTOPCREL, LONG):
5032 if (flag_keep_pcrel)
5033 as_fatal (_("Conversion of PC relative displacement to absolute"));
5034 /* The thing to do here is force it to ABSOLUTE LONG, since
5035 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5036 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5038 fragP->fr_opcode[1] &= ~0x3F;
5039 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5040 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5041 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5047 fixP->fx_file = fragP->fr_file;
5048 fixP->fx_line = fragP->fr_line;
5053 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5054 segT sec ATTRIBUTE_UNUSED,
5057 md_convert_frag_1 (fragP);
5060 /* Force truly undefined symbols to their maximum size, and generally set up
5061 the frag list to be relaxed
5064 md_estimate_size_before_relax (fragS *fragP, segT segment)
5066 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5067 switch (fragP->fr_subtype)
5069 case TAB (BRANCHBWL, SZ_UNDEF):
5070 case TAB (BRANCHBWPL, SZ_UNDEF):
5071 case TAB (BRABSJUNC, SZ_UNDEF):
5072 case TAB (BRABSJCOND, SZ_UNDEF):
5074 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5075 && relaxable_symbol (fragP->fr_symbol))
5077 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5079 else if (flag_short_refs)
5081 /* Symbol is undefined and we want short ref. */
5082 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5086 /* Symbol is still undefined. Make it LONG. */
5087 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5092 case TAB (BRANCHBW, SZ_UNDEF):
5094 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5095 && relaxable_symbol (fragP->fr_symbol))
5097 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5101 /* Symbol is undefined and we don't have long branches. */
5102 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5107 case TAB (FBRANCH, SZ_UNDEF):
5108 case TAB (DBCCLBR, SZ_UNDEF):
5109 case TAB (DBCCABSJ, SZ_UNDEF):
5110 case TAB (PCREL1632, SZ_UNDEF):
5112 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5113 && relaxable_symbol (fragP->fr_symbol))
5116 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5120 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5125 case TAB (PCINDEX, SZ_UNDEF):
5126 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5127 && relaxable_symbol (fragP->fr_symbol)))
5129 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5133 fragP->fr_subtype = TAB (PCINDEX, LONG);
5137 case TAB (ABSTOPCREL, SZ_UNDEF):
5139 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5140 && relaxable_symbol (fragP->fr_symbol)))
5142 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5146 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5155 /* Now that SZ_UNDEF are taken care of, check others. */
5156 switch (fragP->fr_subtype)
5158 case TAB (BRANCHBWL, BYTE):
5159 case TAB (BRABSJUNC, BYTE):
5160 case TAB (BRABSJCOND, BYTE):
5161 case TAB (BRANCHBW, BYTE):
5162 /* We can't do a short jump to the next instruction, so in that
5163 case we force word mode. If the symbol is at the start of a
5164 frag, and it is the next frag with any data in it (usually
5165 this is just the next frag, but assembler listings may
5166 introduce empty frags), we must use word mode. */
5167 if (fragP->fr_symbol)
5171 sym_frag = symbol_get_frag (fragP->fr_symbol);
5172 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5176 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5180 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5187 return md_relax_table[fragP->fr_subtype].rlx_length;
5190 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5191 /* the bit-field entries in the relocation_info struct plays hell
5192 with the byte-order problems of cross-assembly. So as a hack,
5193 I added this mach. dependent ri twiddler. Ugly, but it gets
5195 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5196 are symbolnum, most sig. byte first. Last byte is broken up with
5197 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5198 nibble as nuthin. (on Sun 3 at least) */
5199 /* Translate the internal relocation information into target-specific
5203 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5206 md_number_to_chars (the_bytes, ri->r_address, 4);
5207 /* Now the fun stuff. */
5208 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5209 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5210 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5211 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5212 | ((ri->r_length << 5) & 0x60)
5213 | ((ri->r_extern << 4) & 0x10));
5218 #endif /* OBJ_AOUT or OBJ_BOUT */
5220 #ifndef WORKING_DOT_WORD
5221 int md_short_jump_size = 4;
5222 int md_long_jump_size = 6;
5225 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5226 fragS *frag ATTRIBUTE_UNUSED,
5227 symbolS *to_symbol ATTRIBUTE_UNUSED)
5231 offset = to_addr - (from_addr + 2);
5233 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5234 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5238 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5239 fragS *frag, symbolS *to_symbol)
5243 if (!HAVE_LONG_BRANCH (current_architecture))
5245 if (flag_keep_pcrel)
5246 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5247 offset = to_addr - S_GET_VALUE (to_symbol);
5248 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5249 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5250 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5255 offset = to_addr - (from_addr + 2);
5256 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5257 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5263 /* Different values of OK tell what its OK to return. Things that
5264 aren't OK are an error (what a shock, no?)
5267 10: Absolute 1:8 only
5268 20: Absolute 0:7 only
5269 30: absolute 0:15 only
5270 40: Absolute 0:31 only
5271 50: absolute 0:127 only
5272 55: absolute -64:63 only
5273 60: absolute -128:127 only
5274 65: absolute 0:511 only
5275 70: absolute 0:4095 only
5276 80: absolute -1, 1:7 only
5280 get_num (struct m68k_exp *exp, int ok)
5282 if (exp->exp.X_op == O_absent)
5284 /* Do the same thing the VAX asm does. */
5285 op (exp) = O_constant;
5291 as_warn (_("expression out of range: defaulting to 1"));
5295 else if (exp->exp.X_op == O_constant)
5300 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5302 as_warn (_("expression out of range: defaulting to 1"));
5307 if ((valueT) TRUNC (offs (exp)) > 7)
5311 if ((valueT) TRUNC (offs (exp)) > 15)
5315 if ((valueT) TRUNC (offs (exp)) > 32)
5319 if ((valueT) TRUNC (offs (exp)) > 127)
5323 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5327 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5331 if ((valueT) TRUNC (offs (exp)) > 511)
5335 if ((valueT) TRUNC (offs (exp)) > 4095)
5338 as_warn (_("expression out of range: defaulting to 0"));
5343 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5344 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5346 as_warn (_("expression out of range: defaulting to 1"));
5354 else if (exp->exp.X_op == O_big)
5356 if (offs (exp) <= 0 /* flonum. */
5357 && (ok == 90 /* no bignums */
5358 || (ok > 10 /* Small-int ranges including 0 ok. */
5359 /* If we have a flonum zero, a zero integer should
5360 do as well (e.g., in moveq). */
5361 && generic_floating_point_number.exponent == 0
5362 && generic_floating_point_number.low[0] == 0)))
5364 /* HACK! Turn it into a long. */
5365 LITTLENUM_TYPE words[6];
5367 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5368 op (exp) = O_constant;
5371 offs (exp) = words[1] | (words[0] << 16);
5375 op (exp) = O_constant;
5378 offs (exp) = (ok == 10) ? 1 : 0;
5379 as_warn (_("Can't deal with expression; defaulting to %ld"),
5385 if (ok >= 10 && ok <= 80)
5387 op (exp) = O_constant;
5390 offs (exp) = (ok == 10) ? 1 : 0;
5391 as_warn (_("Can't deal with expression; defaulting to %ld"),
5396 if (exp->size != SIZE_UNSPEC)
5404 if (!isbyte (offs (exp)))
5405 as_warn (_("expression doesn't fit in BYTE"));
5408 if (!isword (offs (exp)))
5409 as_warn (_("expression doesn't fit in WORD"));
5417 /* These are the back-ends for the various machine dependent pseudo-ops. */
5420 s_data1 (int ignore ATTRIBUTE_UNUSED)
5422 subseg_set (data_section, 1);
5423 demand_empty_rest_of_line ();
5427 s_data2 (int ignore ATTRIBUTE_UNUSED)
5429 subseg_set (data_section, 2);
5430 demand_empty_rest_of_line ();
5434 s_bss (int ignore ATTRIBUTE_UNUSED)
5436 /* We don't support putting frags in the BSS segment, we fake it
5437 by marking in_bss, then looking at s_skip for clues. */
5439 subseg_set (bss_section, 0);
5440 demand_empty_rest_of_line ();
5444 s_even (int ignore ATTRIBUTE_UNUSED)
5447 register long temp_fill;
5449 temp = 1; /* JF should be 2? */
5450 temp_fill = get_absolute_expression ();
5451 if (!need_pass_2) /* Never make frag if expect extra pass. */
5452 frag_align (temp, (int) temp_fill, 0);
5453 demand_empty_rest_of_line ();
5454 record_alignment (now_seg, temp);
5458 s_proc (int ignore ATTRIBUTE_UNUSED)
5460 demand_empty_rest_of_line ();
5463 /* Pseudo-ops handled for MRI compatibility. */
5465 /* This function returns non-zero if the argument is a conditional
5466 pseudo-op. This is called when checking whether a pending
5467 alignment is needed. */
5470 m68k_conditional_pseudoop (pseudo_typeS *pop)
5472 return (pop->poc_handler == s_mri_if
5473 || pop->poc_handler == s_mri_else);
5476 /* Handle an MRI style chip specification. */
5485 s = input_line_pointer;
5486 /* We can't use get_symbol_end since the processor names are not proper
5488 while (is_part_of_name (c = *input_line_pointer++))
5490 *--input_line_pointer = 0;
5491 for (i = 0; m68k_cpus[i].name; i++)
5492 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5494 if (!m68k_cpus[i].name)
5496 as_bad (_("%s: unrecognized processor name"), s);
5497 *input_line_pointer = c;
5498 ignore_rest_of_line ();
5501 *input_line_pointer = c;
5503 if (*input_line_pointer == '/')
5504 current_architecture = 0;
5506 current_architecture &= m68881 | m68851;
5507 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5508 control_regs = m68k_cpus[i].control_regs;
5510 while (*input_line_pointer == '/')
5512 ++input_line_pointer;
5513 s = input_line_pointer;
5514 /* We can't use get_symbol_end since the processor names are not
5516 while (is_part_of_name (c = *input_line_pointer++))
5518 *--input_line_pointer = 0;
5519 if (strcmp (s, "68881") == 0)
5520 current_architecture |= m68881;
5521 else if (strcmp (s, "68851") == 0)
5522 current_architecture |= m68851;
5523 *input_line_pointer = c;
5527 /* The MRI CHIP pseudo-op. */
5530 s_chip (int ignore ATTRIBUTE_UNUSED)
5536 stop = mri_comment_field (&stopc);
5539 mri_comment_end (stop, stopc);
5540 demand_empty_rest_of_line ();
5543 /* The MRI FOPT pseudo-op. */
5546 s_fopt (int ignore ATTRIBUTE_UNUSED)
5550 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5554 input_line_pointer += 3;
5555 temp = get_absolute_expression ();
5556 if (temp < 0 || temp > 7)
5557 as_bad (_("bad coprocessor id"));
5559 m68k_float_copnum = COP0 + temp;
5563 as_bad (_("unrecognized fopt option"));
5564 ignore_rest_of_line ();
5568 demand_empty_rest_of_line ();
5571 /* The structure used to handle the MRI OPT pseudo-op. */
5575 /* The name of the option. */
5578 /* If this is not NULL, just call this function. The first argument
5579 is the ARG field of this structure, the second argument is
5580 whether the option was negated. */
5581 void (*pfn) (int arg, int on);
5583 /* If this is not NULL, and the PFN field is NULL, set the variable
5584 this points to. Set it to the ARG field if the option was not
5585 negated, and the NOTARG field otherwise. */
5588 /* The value to pass to PFN or to assign to *PVAR. */
5591 /* The value to assign to *PVAR if the option is negated. If PFN is
5592 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5593 the option may not be negated. */
5597 /* The table used to handle the MRI OPT pseudo-op. */
5599 static void skip_to_comma (int, int);
5600 static void opt_nest (int, int);
5601 static void opt_chip (int, int);
5602 static void opt_list (int, int);
5603 static void opt_list_symbols (int, int);
5605 static const struct opt_action opt_table[] =
5607 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5609 /* We do relaxing, so there is little use for these options. */
5610 { "b", 0, 0, 0, 0 },
5611 { "brs", 0, 0, 0, 0 },
5612 { "brb", 0, 0, 0, 0 },
5613 { "brl", 0, 0, 0, 0 },
5614 { "brw", 0, 0, 0, 0 },
5616 { "c", 0, 0, 0, 0 },
5617 { "cex", 0, 0, 0, 0 },
5618 { "case", 0, &symbols_case_sensitive, 1, 0 },
5619 { "cl", 0, 0, 0, 0 },
5620 { "cre", 0, 0, 0, 0 },
5621 { "d", 0, &flag_keep_locals, 1, 0 },
5622 { "e", 0, 0, 0, 0 },
5623 { "f", 0, &flag_short_refs, 1, 0 },
5624 { "frs", 0, &flag_short_refs, 1, 0 },
5625 { "frl", 0, &flag_short_refs, 0, 1 },
5626 { "g", 0, 0, 0, 0 },
5627 { "i", 0, 0, 0, 0 },
5628 { "m", 0, 0, 0, 0 },
5629 { "mex", 0, 0, 0, 0 },
5630 { "mc", 0, 0, 0, 0 },
5631 { "md", 0, 0, 0, 0 },
5632 { "nest", opt_nest, 0, 0, 0 },
5633 { "next", skip_to_comma, 0, 0, 0 },
5634 { "o", 0, 0, 0, 0 },
5635 { "old", 0, 0, 0, 0 },
5636 { "op", skip_to_comma, 0, 0, 0 },
5637 { "pco", 0, 0, 0, 0 },
5638 { "p", opt_chip, 0, 0, 0 },
5639 { "pcr", 0, 0, 0, 0 },
5640 { "pcs", 0, 0, 0, 0 },
5641 { "r", 0, 0, 0, 0 },
5642 { "quick", 0, &m68k_quick, 1, 0 },
5643 { "rel32", 0, &m68k_rel32, 1, 0 },
5644 { "s", opt_list, 0, 0, 0 },
5645 { "t", opt_list_symbols, 0, 0, 0 },
5646 { "w", 0, &flag_no_warnings, 0, 1 },
5650 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5652 /* The MRI OPT pseudo-op. */
5655 s_opt (int ignore ATTRIBUTE_UNUSED)
5663 const struct opt_action *o;
5668 if (*input_line_pointer == '-')
5670 ++input_line_pointer;
5673 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5675 input_line_pointer += 2;
5679 s = input_line_pointer;
5680 c = get_symbol_end ();
5682 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5684 if (strcasecmp (s, o->name) == 0)
5688 /* Restore input_line_pointer now in case the option
5690 *input_line_pointer = c;
5691 (*o->pfn) (o->arg, t);
5693 else if (o->pvar != NULL)
5695 if (! t && o->arg == o->notarg)
5696 as_bad (_("option `%s' may not be negated"), s);
5697 *input_line_pointer = c;
5698 *o->pvar = t ? o->arg : o->notarg;
5701 *input_line_pointer = c;
5707 as_bad (_("option `%s' not recognized"), s);
5708 *input_line_pointer = c;
5711 while (*input_line_pointer++ == ',');
5713 /* Move back to terminating character. */
5714 --input_line_pointer;
5715 demand_empty_rest_of_line ();
5718 /* Skip ahead to a comma. This is used for OPT options which we do
5719 not support and which take arguments. */
5722 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5724 while (*input_line_pointer != ','
5725 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5726 ++input_line_pointer;
5729 /* Handle the OPT NEST=depth option. */
5732 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5734 if (*input_line_pointer != '=')
5736 as_bad (_("bad format of OPT NEST=depth"));
5740 ++input_line_pointer;
5741 max_macro_nest = get_absolute_expression ();
5744 /* Handle the OPT P=chip option. */
5747 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5749 if (*input_line_pointer != '=')
5751 /* This is just OPT P, which we do not support. */
5755 ++input_line_pointer;
5759 /* Handle the OPT S option. */
5762 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5767 /* Handle the OPT T option. */
5770 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5773 listing |= LISTING_SYMBOLS;
5775 listing &= ~LISTING_SYMBOLS;
5778 /* Handle the MRI REG pseudo-op. */
5781 s_reg (int ignore ATTRIBUTE_UNUSED)
5790 if (line_label == NULL)
5792 as_bad (_("missing label"));
5793 ignore_rest_of_line ();
5798 stop = mri_comment_field (&stopc);
5802 s = input_line_pointer;
5803 while (ISALNUM (*input_line_pointer)
5804 #ifdef REGISTER_PREFIX
5805 || *input_line_pointer == REGISTER_PREFIX
5807 || *input_line_pointer == '/'
5808 || *input_line_pointer == '-')
5809 ++input_line_pointer;
5810 c = *input_line_pointer;
5811 *input_line_pointer = '\0';
5813 if (m68k_ip_op (s, &rop) != 0)
5815 if (rop.error == NULL)
5816 as_bad (_("bad register list"));
5818 as_bad (_("bad register list: %s"), rop.error);
5819 *input_line_pointer = c;
5820 ignore_rest_of_line ();
5824 *input_line_pointer = c;
5826 if (rop.mode == REGLST)
5828 else if (rop.mode == DREG)
5829 mask = 1 << (rop.reg - DATA0);
5830 else if (rop.mode == AREG)
5831 mask = 1 << (rop.reg - ADDR0 + 8);
5832 else if (rop.mode == FPREG)
5833 mask = 1 << (rop.reg - FP0 + 16);
5834 else if (rop.mode == CONTROL
5837 else if (rop.mode == CONTROL
5840 else if (rop.mode == CONTROL
5845 as_bad (_("bad register list"));
5846 ignore_rest_of_line ();
5850 S_SET_SEGMENT (line_label, reg_section);
5851 S_SET_VALUE (line_label, ~mask);
5852 symbol_set_frag (line_label, &zero_address_frag);
5855 mri_comment_end (stop, stopc);
5857 demand_empty_rest_of_line ();
5860 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5864 struct save_opts *next;
5866 int symbols_case_sensitive;
5870 const enum m68k_register *control_regs;
5875 /* FIXME: We don't save OPT S. */
5878 /* This variable holds the stack of saved options. */
5880 static struct save_opts *save_stack;
5882 /* The MRI SAVE pseudo-op. */
5885 s_save (int ignore ATTRIBUTE_UNUSED)
5887 struct save_opts *s;
5889 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5890 s->abspcadd = m68k_abspcadd;
5891 s->symbols_case_sensitive = symbols_case_sensitive;
5892 s->keep_locals = flag_keep_locals;
5893 s->short_refs = flag_short_refs;
5894 s->architecture = current_architecture;
5895 s->control_regs = control_regs;
5896 s->quick = m68k_quick;
5897 s->rel32 = m68k_rel32;
5898 s->listing = listing;
5899 s->no_warnings = flag_no_warnings;
5901 s->next = save_stack;
5904 demand_empty_rest_of_line ();
5907 /* The MRI RESTORE pseudo-op. */
5910 s_restore (int ignore ATTRIBUTE_UNUSED)
5912 struct save_opts *s;
5914 if (save_stack == NULL)
5916 as_bad (_("restore without save"));
5917 ignore_rest_of_line ();
5922 save_stack = s->next;
5924 m68k_abspcadd = s->abspcadd;
5925 symbols_case_sensitive = s->symbols_case_sensitive;
5926 flag_keep_locals = s->keep_locals;
5927 flag_short_refs = s->short_refs;
5928 current_architecture = s->architecture;
5929 control_regs = s->control_regs;
5930 m68k_quick = s->quick;
5931 m68k_rel32 = s->rel32;
5932 listing = s->listing;
5933 flag_no_warnings = s->no_warnings;
5937 demand_empty_rest_of_line ();
5940 /* Types of MRI structured control directives. */
5942 enum mri_control_type
5950 /* This structure is used to stack the MRI structured control
5953 struct mri_control_info
5955 /* The directive within which this one is enclosed. */
5956 struct mri_control_info *outer;
5958 /* The type of directive. */
5959 enum mri_control_type type;
5961 /* Whether an ELSE has been in an IF. */
5964 /* The add or sub statement at the end of a FOR. */
5967 /* The label of the top of a FOR or REPEAT loop. */
5970 /* The label to jump to for the next iteration, or the else
5971 expression of a conditional. */
5974 /* The label to jump to to break out of the loop, or the label past
5975 the end of a conditional. */
5979 /* The stack of MRI structured control directives. */
5981 static struct mri_control_info *mri_control_stack;
5983 /* The current MRI structured control directive index number, used to
5984 generate label names. */
5986 static int mri_control_index;
5988 /* Assemble an instruction for an MRI structured control directive. */
5991 mri_assemble (char *str)
5995 /* md_assemble expects the opcode to be in lower case. */
5996 for (s = str; *s != ' ' && *s != '\0'; s++)
6002 /* Generate a new MRI label structured control directive label name. */
6005 mri_control_label (void)
6009 n = (char *) xmalloc (20);
6010 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6011 ++mri_control_index;
6015 /* Create a new MRI structured control directive. */
6017 static struct mri_control_info *
6018 push_mri_control (enum mri_control_type type)
6020 struct mri_control_info *n;
6022 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6026 if (type == mri_if || type == mri_while)
6029 n->top = mri_control_label ();
6030 n->next = mri_control_label ();
6031 n->bottom = mri_control_label ();
6033 n->outer = mri_control_stack;
6034 mri_control_stack = n;
6039 /* Pop off the stack of MRI structured control directives. */
6042 pop_mri_control (void)
6044 struct mri_control_info *n;
6046 n = mri_control_stack;
6047 mri_control_stack = n->outer;
6055 /* Recognize a condition code in an MRI structured control expression. */
6058 parse_mri_condition (int *pcc)
6062 know (*input_line_pointer == '<');
6064 ++input_line_pointer;
6065 c1 = *input_line_pointer++;
6066 c2 = *input_line_pointer++;
6068 if (*input_line_pointer != '>')
6070 as_bad (_("syntax error in structured control directive"));
6074 ++input_line_pointer;
6080 *pcc = (c1 << 8) | c2;
6085 /* Parse a single operand in an MRI structured control expression. */
6088 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6089 char **rightstart, char **rightstop)
6101 if (*input_line_pointer == '<')
6103 /* It's just a condition code. */
6104 return parse_mri_condition (pcc);
6107 /* Look ahead for the condition code. */
6108 for (s = input_line_pointer; *s != '\0'; ++s)
6110 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6115 as_bad (_("missing condition code in structured control directive"));
6119 *leftstart = input_line_pointer;
6121 if (*leftstop > *leftstart
6122 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6125 input_line_pointer = s;
6126 if (! parse_mri_condition (pcc))
6129 /* Look ahead for AND or OR or end of line. */
6130 for (s = input_line_pointer; *s != '\0'; ++s)
6132 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6133 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6135 if ((s == input_line_pointer
6138 && ((strncasecmp (s, "AND", 3) == 0
6139 && (s[3] == '.' || ! is_part_of_name (s[3])))
6140 || (strncasecmp (s, "OR", 2) == 0
6141 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6145 *rightstart = input_line_pointer;
6147 if (*rightstop > *rightstart
6148 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6151 input_line_pointer = s;
6156 #define MCC(b1, b2) (((b1) << 8) | (b2))
6158 /* Swap the sense of a condition. This changes the condition so that
6159 it generates the same result when the operands are swapped. */
6162 swap_mri_condition (int cc)
6166 case MCC ('h', 'i'): return MCC ('c', 's');
6167 case MCC ('l', 's'): return MCC ('c', 'c');
6168 /* <HS> is an alias for <CC>. */
6169 case MCC ('h', 's'):
6170 case MCC ('c', 'c'): return MCC ('l', 's');
6171 /* <LO> is an alias for <CS>. */
6172 case MCC ('l', 'o'):
6173 case MCC ('c', 's'): return MCC ('h', 'i');
6174 case MCC ('p', 'l'): return MCC ('m', 'i');
6175 case MCC ('m', 'i'): return MCC ('p', 'l');
6176 case MCC ('g', 'e'): return MCC ('l', 'e');
6177 case MCC ('l', 't'): return MCC ('g', 't');
6178 case MCC ('g', 't'): return MCC ('l', 't');
6179 case MCC ('l', 'e'): return MCC ('g', 'e');
6180 /* Issue a warning for conditions we can not swap. */
6181 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6182 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6183 case MCC ('v', 'c'):
6184 case MCC ('v', 's'):
6186 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6187 (char) (cc >> 8), (char) (cc));
6193 /* Reverse the sense of a condition. */
6196 reverse_mri_condition (int cc)
6200 case MCC ('h', 'i'): return MCC ('l', 's');
6201 case MCC ('l', 's'): return MCC ('h', 'i');
6202 /* <HS> is an alias for <CC> */
6203 case MCC ('h', 's'): return MCC ('l', 'o');
6204 case MCC ('c', 'c'): return MCC ('c', 's');
6205 /* <LO> is an alias for <CS> */
6206 case MCC ('l', 'o'): return MCC ('h', 's');
6207 case MCC ('c', 's'): return MCC ('c', 'c');
6208 case MCC ('n', 'e'): return MCC ('e', 'q');
6209 case MCC ('e', 'q'): return MCC ('n', 'e');
6210 case MCC ('v', 'c'): return MCC ('v', 's');
6211 case MCC ('v', 's'): return MCC ('v', 'c');
6212 case MCC ('p', 'l'): return MCC ('m', 'i');
6213 case MCC ('m', 'i'): return MCC ('p', 'l');
6214 case MCC ('g', 'e'): return MCC ('l', 't');
6215 case MCC ('l', 't'): return MCC ('g', 'e');
6216 case MCC ('g', 't'): return MCC ('l', 'e');
6217 case MCC ('l', 'e'): return MCC ('g', 't');
6222 /* Build an MRI structured control expression. This generates test
6223 and branch instructions. It goes to TRUELAB if the condition is
6224 true, and to FALSELAB if the condition is false. Exactly one of
6225 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6226 is the size qualifier for the expression. EXTENT is the size to
6227 use for the branch. */
6230 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6231 char *rightstart, char *rightstop,
6232 const char *truelab, const char *falselab,
6238 if (leftstart != NULL)
6240 struct m68k_op leftop, rightop;
6243 /* Swap the compare operands, if necessary, to produce a legal
6244 m68k compare instruction. Comparing a register operand with
6245 a non-register operand requires the register to be on the
6246 right (cmp, cmpa). Comparing an immediate value with
6247 anything requires the immediate value to be on the left
6252 (void) m68k_ip_op (leftstart, &leftop);
6257 (void) m68k_ip_op (rightstart, &rightop);
6260 if (rightop.mode == IMMED
6261 || ((leftop.mode == DREG || leftop.mode == AREG)
6262 && (rightop.mode != DREG && rightop.mode != AREG)))
6266 /* Correct conditional handling:
6267 if #1 <lt> d0 then ;means if (1 < d0)
6273 cmp #1,d0 if we do *not* swap the operands
6274 bgt true we need the swapped condition!
6281 leftstart = rightstart;
6284 leftstop = rightstop;
6289 cc = swap_mri_condition (cc);
6293 if (truelab == NULL)
6295 cc = reverse_mri_condition (cc);
6299 if (leftstart != NULL)
6301 buf = (char *) xmalloc (20
6302 + (leftstop - leftstart)
6303 + (rightstop - rightstart));
6309 *s++ = TOLOWER (qual);
6311 memcpy (s, leftstart, leftstop - leftstart);
6312 s += leftstop - leftstart;
6314 memcpy (s, rightstart, rightstop - rightstart);
6315 s += rightstop - rightstart;
6321 buf = (char *) xmalloc (20 + strlen (truelab));
6327 *s++ = TOLOWER (extent);
6329 strcpy (s, truelab);
6334 /* Parse an MRI structured control expression. This generates test
6335 and branch instructions. STOP is where the expression ends. It
6336 goes to TRUELAB if the condition is true, and to FALSELAB if the
6337 condition is false. Exactly one of TRUELAB and FALSELAB will be
6338 NULL, meaning to fall through. QUAL is the size qualifier for the
6339 expression. EXTENT is the size to use for the branch. */
6342 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6343 const char *falselab, int extent)
6355 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6356 &rightstart, &rightstop))
6362 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6366 if (falselab != NULL)
6369 flab = mri_control_label ();
6371 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6372 rightstop, (const char *) NULL, flab, extent);
6374 input_line_pointer += 3;
6375 if (*input_line_pointer != '.'
6376 || input_line_pointer[1] == '\0')
6380 qual = input_line_pointer[1];
6381 input_line_pointer += 2;
6384 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6385 &rightstart, &rightstop))
6391 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6392 rightstop, truelab, falselab, extent);
6394 if (falselab == NULL)
6397 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6401 if (truelab != NULL)
6404 tlab = mri_control_label ();
6406 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6407 rightstop, tlab, (const char *) NULL, extent);
6409 input_line_pointer += 2;
6410 if (*input_line_pointer != '.'
6411 || input_line_pointer[1] == '\0')
6415 qual = input_line_pointer[1];
6416 input_line_pointer += 2;
6419 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6420 &rightstart, &rightstop))
6426 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6427 rightstop, truelab, falselab, extent);
6429 if (truelab == NULL)
6434 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6435 rightstop, truelab, falselab, extent);
6439 if (input_line_pointer != stop)
6440 as_bad (_("syntax error in structured control directive"));
6443 /* Handle the MRI IF pseudo-op. This may be a structured control
6444 directive, or it may be a regular assembler conditional, depending
6452 struct mri_control_info *n;
6454 /* A structured control directive must end with THEN with an
6455 optional qualifier. */
6456 s = input_line_pointer;
6457 /* We only accept '*' as introduction of comments if preceded by white space
6458 or at first column of a line (I think this can't actually happen here?)
6459 This is important when assembling:
6460 if d0 <ne> 12(a0,d0*2) then
6461 if d0 <ne> #CONST*20 then. */
6462 while (! (is_end_of_line[(unsigned char) *s]
6465 && (s == input_line_pointer
6467 || *(s-1) == '\t'))))
6470 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6473 if (s - input_line_pointer > 1
6477 if (s - input_line_pointer < 3
6478 || strncasecmp (s - 3, "THEN", 4) != 0)
6482 as_bad (_("missing then"));
6483 ignore_rest_of_line ();
6487 /* It's a conditional. */
6492 /* Since this might be a conditional if, this pseudo-op will be
6493 called even if we are supported to be ignoring input. Double
6494 check now. Clobber *input_line_pointer so that ignore_input
6495 thinks that this is not a special pseudo-op. */
6496 c = *input_line_pointer;
6497 *input_line_pointer = 0;
6498 if (ignore_input ())
6500 *input_line_pointer = c;
6501 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6502 ++input_line_pointer;
6503 demand_empty_rest_of_line ();
6506 *input_line_pointer = c;
6508 n = push_mri_control (mri_if);
6510 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6511 n->next, s[1] == '.' ? s[2] : '\0');
6514 input_line_pointer = s + 3;
6516 input_line_pointer = s + 1;
6520 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6521 ++input_line_pointer;
6524 demand_empty_rest_of_line ();
6527 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6528 structured IF, associate the ELSE with the IF. Otherwise, assume
6529 it is a conditional else. */
6532 s_mri_else (int qual)
6539 && (mri_control_stack == NULL
6540 || mri_control_stack->type != mri_if
6541 || mri_control_stack->else_seen))
6547 c = *input_line_pointer;
6548 *input_line_pointer = 0;
6549 if (ignore_input ())
6551 *input_line_pointer = c;
6552 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6553 ++input_line_pointer;
6554 demand_empty_rest_of_line ();
6557 *input_line_pointer = c;
6559 if (mri_control_stack == NULL
6560 || mri_control_stack->type != mri_if
6561 || mri_control_stack->else_seen)
6563 as_bad (_("else without matching if"));
6564 ignore_rest_of_line ();
6568 mri_control_stack->else_seen = 1;
6570 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6571 q[0] = TOLOWER (qual);
6573 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6577 colon (mri_control_stack->next);
6581 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6582 ++input_line_pointer;
6585 demand_empty_rest_of_line ();
6588 /* Handle the MRI ENDI pseudo-op. */
6591 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6593 if (mri_control_stack == NULL
6594 || mri_control_stack->type != mri_if)
6596 as_bad (_("endi without matching if"));
6597 ignore_rest_of_line ();
6601 /* ignore_input will not return true for ENDI, so we don't need to
6602 worry about checking it again here. */
6604 if (! mri_control_stack->else_seen)
6605 colon (mri_control_stack->next);
6606 colon (mri_control_stack->bottom);
6612 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6613 ++input_line_pointer;
6616 demand_empty_rest_of_line ();
6619 /* Handle the MRI BREAK pseudo-op. */
6622 s_mri_break (int extent)
6624 struct mri_control_info *n;
6628 n = mri_control_stack;
6630 && n->type != mri_for
6631 && n->type != mri_repeat
6632 && n->type != mri_while)
6636 as_bad (_("break outside of structured loop"));
6637 ignore_rest_of_line ();
6641 buf = (char *) xmalloc (20 + strlen (n->bottom));
6642 ex[0] = TOLOWER (extent);
6644 sprintf (buf, "bra%s %s", ex, n->bottom);
6650 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6651 ++input_line_pointer;
6654 demand_empty_rest_of_line ();
6657 /* Handle the MRI NEXT pseudo-op. */
6660 s_mri_next (int extent)
6662 struct mri_control_info *n;
6666 n = mri_control_stack;
6668 && n->type != mri_for
6669 && n->type != mri_repeat
6670 && n->type != mri_while)
6674 as_bad (_("next outside of structured loop"));
6675 ignore_rest_of_line ();
6679 buf = (char *) xmalloc (20 + strlen (n->next));
6680 ex[0] = TOLOWER (extent);
6682 sprintf (buf, "bra%s %s", ex, n->next);
6688 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6689 ++input_line_pointer;
6692 demand_empty_rest_of_line ();
6695 /* Handle the MRI FOR pseudo-op. */
6698 s_mri_for (int qual)
6700 const char *varstart, *varstop;
6701 const char *initstart, *initstop;
6702 const char *endstart, *endstop;
6703 const char *bystart, *bystop;
6707 struct mri_control_info *n;
6713 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6717 varstart = input_line_pointer;
6719 /* Look for the '='. */
6720 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6721 && *input_line_pointer != '=')
6722 ++input_line_pointer;
6723 if (*input_line_pointer != '=')
6725 as_bad (_("missing ="));
6726 ignore_rest_of_line ();
6730 varstop = input_line_pointer;
6731 if (varstop > varstart
6732 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6735 ++input_line_pointer;
6737 initstart = input_line_pointer;
6739 /* Look for TO or DOWNTO. */
6742 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6744 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6745 && ! is_part_of_name (input_line_pointer[2]))
6747 initstop = input_line_pointer;
6748 input_line_pointer += 2;
6751 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6752 && ! is_part_of_name (input_line_pointer[6]))
6754 initstop = input_line_pointer;
6756 input_line_pointer += 6;
6759 ++input_line_pointer;
6761 if (initstop == NULL)
6763 as_bad (_("missing to or downto"));
6764 ignore_rest_of_line ();
6767 if (initstop > initstart
6768 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6772 endstart = input_line_pointer;
6774 /* Look for BY or DO. */
6777 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6779 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6780 && ! is_part_of_name (input_line_pointer[2]))
6782 endstop = input_line_pointer;
6784 input_line_pointer += 2;
6787 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6788 && (input_line_pointer[2] == '.'
6789 || ! is_part_of_name (input_line_pointer[2])))
6791 endstop = input_line_pointer;
6792 input_line_pointer += 2;
6795 ++input_line_pointer;
6797 if (endstop == NULL)
6799 as_bad (_("missing do"));
6800 ignore_rest_of_line ();
6803 if (endstop > endstart
6804 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6810 bystop = bystart + 2;
6815 bystart = input_line_pointer;
6819 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6821 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6822 && (input_line_pointer[2] == '.'
6823 || ! is_part_of_name (input_line_pointer[2])))
6825 bystop = input_line_pointer;
6826 input_line_pointer += 2;
6829 ++input_line_pointer;
6833 as_bad (_("missing do"));
6834 ignore_rest_of_line ();
6837 if (bystop > bystart
6838 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6842 if (*input_line_pointer != '.')
6846 extent = input_line_pointer[1];
6847 input_line_pointer += 2;
6850 /* We have fully parsed the FOR operands. Now build the loop. */
6851 n = push_mri_control (mri_for);
6853 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6855 /* Move init,var. */
6862 *s++ = TOLOWER (qual);
6864 memcpy (s, initstart, initstop - initstart);
6865 s += initstop - initstart;
6867 memcpy (s, varstart, varstop - varstart);
6868 s += varstop - varstart;
6880 *s++ = TOLOWER (qual);
6882 memcpy (s, endstart, endstop - endstart);
6883 s += endstop - endstart;
6885 memcpy (s, varstart, varstop - varstart);
6886 s += varstop - varstart;
6891 ex[0] = TOLOWER (extent);
6894 sprintf (buf, "blt%s %s", ex, n->bottom);
6896 sprintf (buf, "bgt%s %s", ex, n->bottom);
6899 /* Put together the add or sub instruction used by ENDF. */
6907 *s++ = TOLOWER (qual);
6909 memcpy (s, bystart, bystop - bystart);
6910 s += bystop - bystart;
6912 memcpy (s, varstart, varstop - varstart);
6913 s += varstop - varstart;
6919 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6920 ++input_line_pointer;
6923 demand_empty_rest_of_line ();
6926 /* Handle the MRI ENDF pseudo-op. */
6929 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6931 if (mri_control_stack == NULL
6932 || mri_control_stack->type != mri_for)
6934 as_bad (_("endf without for"));
6935 ignore_rest_of_line ();
6939 colon (mri_control_stack->next);
6941 mri_assemble (mri_control_stack->incr);
6943 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6944 mri_assemble (mri_control_stack->incr);
6946 free (mri_control_stack->incr);
6948 colon (mri_control_stack->bottom);
6954 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6955 ++input_line_pointer;
6958 demand_empty_rest_of_line ();
6961 /* Handle the MRI REPEAT pseudo-op. */
6964 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6966 struct mri_control_info *n;
6968 n = push_mri_control (mri_repeat);
6972 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6973 ++input_line_pointer;
6975 demand_empty_rest_of_line ();
6978 /* Handle the MRI UNTIL pseudo-op. */
6981 s_mri_until (int qual)
6985 if (mri_control_stack == NULL
6986 || mri_control_stack->type != mri_repeat)
6988 as_bad (_("until without repeat"));
6989 ignore_rest_of_line ();
6993 colon (mri_control_stack->next);
6995 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6998 parse_mri_control_expression (s, qual, (const char *) NULL,
6999 mri_control_stack->top, '\0');
7001 colon (mri_control_stack->bottom);
7003 input_line_pointer = s;
7009 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7010 ++input_line_pointer;
7013 demand_empty_rest_of_line ();
7016 /* Handle the MRI WHILE pseudo-op. */
7019 s_mri_while (int qual)
7023 struct mri_control_info *n;
7025 s = input_line_pointer;
7026 /* We only accept '*' as introduction of comments if preceded by white space
7027 or at first column of a line (I think this can't actually happen here?)
7028 This is important when assembling:
7029 while d0 <ne> 12(a0,d0*2) do
7030 while d0 <ne> #CONST*20 do. */
7031 while (! (is_end_of_line[(unsigned char) *s]
7034 && (s == input_line_pointer
7036 || *(s-1) == '\t'))))
7039 while (*s == ' ' || *s == '\t')
7041 if (s - input_line_pointer > 1
7044 if (s - input_line_pointer < 2
7045 || strncasecmp (s - 1, "DO", 2) != 0)
7047 as_bad (_("missing do"));
7048 ignore_rest_of_line ();
7052 n = push_mri_control (mri_while);
7056 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7057 s[1] == '.' ? s[2] : '\0');
7059 input_line_pointer = s + 1;
7060 if (*input_line_pointer == '.')
7061 input_line_pointer += 2;
7065 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7066 ++input_line_pointer;
7069 demand_empty_rest_of_line ();
7072 /* Handle the MRI ENDW pseudo-op. */
7075 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7079 if (mri_control_stack == NULL
7080 || mri_control_stack->type != mri_while)
7082 as_bad (_("endw without while"));
7083 ignore_rest_of_line ();
7087 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7088 sprintf (buf, "bra %s", mri_control_stack->next);
7092 colon (mri_control_stack->bottom);
7098 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7099 ++input_line_pointer;
7102 demand_empty_rest_of_line ();
7105 /* Parse a .cpu directive. */
7108 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7115 as_bad (_("already assembled instructions"));
7116 ignore_rest_of_line ();
7120 name = input_line_pointer;
7121 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7122 input_line_pointer++;
7123 saved_char = *input_line_pointer;
7124 *input_line_pointer = 0;
7126 m68k_set_cpu (name, 1, 0);
7128 *input_line_pointer = saved_char;
7129 demand_empty_rest_of_line ();
7133 /* Parse a .arch directive. */
7136 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7143 as_bad (_("already assembled instructions"));
7144 ignore_rest_of_line ();
7148 name = input_line_pointer;
7149 while (*input_line_pointer && *input_line_pointer != ','
7150 && !ISSPACE (*input_line_pointer))
7151 input_line_pointer++;
7152 saved_char = *input_line_pointer;
7153 *input_line_pointer = 0;
7155 if (m68k_set_arch (name, 1, 0))
7157 /* Scan extensions. */
7160 *input_line_pointer++ = saved_char;
7161 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7163 name = input_line_pointer;
7164 while (*input_line_pointer && *input_line_pointer != ','
7165 && !ISSPACE (*input_line_pointer))
7166 input_line_pointer++;
7167 saved_char = *input_line_pointer;
7168 *input_line_pointer = 0;
7170 while (m68k_set_extension (name, 1, 0));
7173 *input_line_pointer = saved_char;
7174 demand_empty_rest_of_line ();
7178 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7179 if none is found, the caller is responsible for emitting an error
7180 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7181 cpu name, if it begins with a '6' (possibly skipping an intervening
7182 'c'. We also allow a 'c' in the same place. if NEGATED is
7183 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7184 the option is indeed negated. */
7186 static const struct m68k_cpu *
7187 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7188 int allow_m, int *negated)
7190 /* allow negated value? */
7195 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7202 /* Remove 'm' or 'mc' prefix from 68k variants. */
7209 else if (arg[1] == 'c' && arg[2] == '6')
7213 else if (arg[0] == 'c' && arg[1] == '6')
7216 for (; table->name; table++)
7217 if (!strcmp (arg, table->name))
7219 if (table->alias < -1 || table->alias > 1)
7220 as_bad (_("`%s' is deprecated, use `%s'"),
7221 table->name, table[table->alias < 0 ? 1 : -1].name);
7227 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7230 m68k_set_cpu (char const *name, int allow_m, int silent)
7232 const struct m68k_cpu *cpu;
7234 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7239 as_bad (_("cpu `%s' unrecognized"), name);
7243 if (selected_cpu && selected_cpu != cpu)
7245 as_bad (_("already selected `%s' processor"),
7246 selected_cpu->name);
7253 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7256 m68k_set_arch (char const *name, int allow_m, int silent)
7258 const struct m68k_cpu *arch;
7260 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7265 as_bad (_("architecture `%s' unrecognized"), name);
7269 if (selected_arch && selected_arch != arch)
7271 as_bad (_("already selected `%s' architecture"),
7272 selected_arch->name);
7276 selected_arch = arch;
7280 /* Set the architecture extension, issuing errors if it is
7281 unrecognized, or invalid */
7284 m68k_set_extension (char const *name, int allow_m, int silent)
7287 const struct m68k_cpu *ext;
7289 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7294 as_bad (_("extension `%s' unrecognized"), name);
7299 not_current_architecture |= ext->arch;
7301 current_architecture |= ext->arch;
7306 Invocation line includes a switch not recognized by the base assembler.
7310 const char *md_shortopts = "lSA:m:kQ:V";
7312 const char *md_shortopts = "lSA:m:k";
7315 struct option md_longopts[] = {
7316 #define OPTION_PIC (OPTION_MD_BASE)
7317 {"pic", no_argument, NULL, OPTION_PIC},
7318 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7319 {"register-prefix-optional", no_argument, NULL,
7320 OPTION_REGISTER_PREFIX_OPTIONAL},
7321 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7322 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7323 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7324 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7325 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7326 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7327 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7328 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7329 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7330 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7331 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7332 {"pcrel", no_argument, NULL, OPTION_PCREL},
7333 {NULL, no_argument, NULL, 0}
7335 size_t md_longopts_size = sizeof (md_longopts);
7338 md_parse_option (int c, char *arg)
7342 case 'l': /* -l means keep external to 2 bit offset
7343 rather than 16 bit one. */
7344 flag_short_refs = 1;
7347 case 'S': /* -S means that jbsr's always turn into
7349 flag_long_jumps = 1;
7352 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7353 branches into absolute jumps. */
7354 flag_keep_pcrel = 1;
7360 break; /* -pic, Position Independent Code. */
7362 case OPTION_REGISTER_PREFIX_OPTIONAL:
7363 flag_reg_prefix_optional = 1;
7364 reg_prefix_optional_seen = 1;
7367 /* -V: SVR4 argument to print version ID. */
7369 print_version_id ();
7372 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7373 should be emitted or not. FIXME: Not implemented. */
7377 case OPTION_BITWISE_OR:
7382 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7384 for (s = m68k_comment_chars; *s != '\0'; s++)
7388 m68k_comment_chars = n;
7392 case OPTION_BASE_SIZE_DEFAULT_16:
7393 m68k_index_width_default = SIZE_WORD;
7396 case OPTION_BASE_SIZE_DEFAULT_32:
7397 m68k_index_width_default = SIZE_LONG;
7400 case OPTION_DISP_SIZE_DEFAULT_16:
7402 m68k_rel32_from_cmdline = 1;
7405 case OPTION_DISP_SIZE_DEFAULT_32:
7407 m68k_rel32_from_cmdline = 1;
7412 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7415 /* Intentional fall-through. */
7417 if (!strncmp (arg, "arch=", 5))
7418 m68k_set_arch (arg + 5, 1, 0);
7419 else if (!strncmp (arg, "cpu=", 4))
7420 m68k_set_cpu (arg + 4, 1, 0);
7421 else if (m68k_set_extension (arg, 0, 1))
7423 else if (m68k_set_arch (arg, 0, 1))
7425 else if (m68k_set_cpu (arg, 0, 1))
7438 /* Setup tables from the selected arch and/or cpu */
7441 m68k_init_arch (void)
7443 if (not_current_architecture & current_architecture)
7445 as_bad (_("architecture features both enabled and disabled"));
7446 not_current_architecture &= ~current_architecture;
7450 current_architecture |= selected_arch->arch;
7451 control_regs = selected_arch->control_regs;
7454 current_architecture |= selected_cpu->arch;
7456 current_architecture &= ~not_current_architecture;
7458 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7460 /* Determine which float is really meant. */
7461 if (current_architecture & (m68k_mask & ~m68881))
7462 current_architecture ^= cfloat;
7464 current_architecture ^= m68881;
7469 control_regs = selected_cpu->control_regs;
7470 if (current_architecture & ~selected_cpu->arch)
7472 as_bad (_("selected processor does not have all features of selected architecture"));
7473 current_architecture
7474 = selected_cpu->arch & ~not_current_architecture;
7478 if ((current_architecture & m68k_mask)
7479 && (current_architecture & ~m68k_mask))
7481 as_bad (_ ("m68k and cf features both selected"));
7482 if (current_architecture & m68k_mask)
7483 current_architecture &= m68k_mask;
7485 current_architecture &= ~m68k_mask;
7488 /* Permit m68881 specification with all cpus; those that can't work
7489 with a coprocessor could be doing emulation. */
7490 if (current_architecture & m68851)
7492 if (current_architecture & m68040)
7493 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7495 /* What other incompatibilities could we check for? */
7497 if (cpu_of_arch (current_architecture) < m68020
7498 || arch_coldfire_p (current_architecture))
7499 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7505 md_show_usage (FILE *stream)
7507 const char *default_cpu = TARGET_CPU;
7509 unsigned int default_arch;
7511 /* Get the canonical name for the default target CPU. */
7512 if (*default_cpu == 'm')
7514 for (i = 0; m68k_cpus[i].name; i++)
7516 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7518 default_arch = m68k_cpus[i].arch;
7519 while (m68k_cpus[i].alias > 0)
7521 while (m68k_cpus[i].alias < 0)
7523 default_cpu = m68k_cpus[i].name;
7527 fprintf (stream, _("\
7528 -march=<arch> set architecture\n\
7529 -mcpu=<cpu> set cpu [default %s]\n\
7531 for (i = 0; m68k_extensions[i].name; i++)
7532 fprintf (stream, _("\
7533 -m[no-]%-16s enable/disable%s architecture extension\n\
7534 "), m68k_extensions[i].name,
7535 m68k_extensions[i].alias > 0 ? " ColdFire"
7536 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7538 fprintf (stream, _("\
7539 -l use 1 word for refs to undefined symbols [default 2]\n\
7540 -pic, -k generate position independent code\n\
7541 -S turn jbsr into jsr\n\
7542 --pcrel never turn PC-relative branches into absolute jumps\n\
7543 --register-prefix-optional\n\
7544 recognize register names without prefix character\n\
7545 --bitwise-or do not treat `|' as a comment character\n\
7546 --base-size-default-16 base reg without size is 16 bits\n\
7547 --base-size-default-32 base reg without size is 32 bits (default)\n\
7548 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7549 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7552 fprintf (stream, _("Architecture variants are: "));
7553 for (i = 0; m68k_archs[i].name; i++)
7556 fprintf (stream, " | ");
7557 fprintf (stream, m68k_archs[i].name);
7559 fprintf (stream, "\n");
7561 fprintf (stream, _("Processor variants are: "));
7562 for (i = 0; m68k_cpus[i].name; i++)
7565 fprintf (stream, " | ");
7566 fprintf (stream, m68k_cpus[i].name);
7568 fprintf (stream, _("\n"));
7573 /* TEST2: Test md_assemble() */
7574 /* Warning, this routine probably doesn't work anymore. */
7578 struct m68k_it the_ins;
7586 if (!gets (buf) || !*buf)
7588 if (buf[0] == '|' || buf[1] == '.')
7590 for (cp = buf; *cp; cp++)
7595 memset (&the_ins, '\0', sizeof (the_ins));
7596 m68k_ip (&the_ins, buf);
7599 printf (_("Error %s in %s\n"), the_ins.error, buf);
7603 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7604 for (n = 0; n < the_ins.numo; n++)
7605 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7607 print_the_insn (&the_ins.opcode[0], stdout);
7608 (void) putchar ('\n');
7610 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7612 if (the_ins.operands[n].error)
7614 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7617 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7618 the_ins.operands[n].reg);
7619 if (the_ins.operands[n].b_const)
7620 printf ("Constant: '%.*s', ",
7621 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7622 the_ins.operands[n].b_const);
7623 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7624 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7625 if (the_ins.operands[n].b_iadd)
7626 printf ("Iadd: '%.*s',",
7627 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7628 the_ins.operands[n].b_iadd);
7637 is_label (char *str)
7641 while (*str && *str != ' ')
7643 if (str[-1] == ':' || str[1] == '=')
7650 /* Possible states for relaxation:
7652 0 0 branch offset byte (bra, etc)
7656 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7660 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7667 /* We have no need to default values of symbols. */
7670 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7675 /* Round up a section size to the appropriate boundary. */
7677 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7680 /* For a.out, force the section size to be aligned. If we don't do
7681 this, BFD will align it for us, but it will not write out the
7682 final bytes of the section. This may be a bug in BFD, but it is
7683 easier to fix it here since that is how the other a.out targets
7687 align = bfd_get_section_alignment (stdoutput, segment);
7688 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7694 /* Exactly what point is a PC-relative offset relative TO?
7695 On the 68k, it is relative to the address of the first extension
7696 word. The difference between the addresses of the offset and the
7697 first extension word is stored in fx_pcrel_adjust. */
7699 md_pcrel_from (fixS *fixP)
7703 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7704 sign extend the value here. */
7705 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7708 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7713 m68k_elf_final_processing (void)
7717 if (arch_coldfire_fpu (current_architecture))
7718 flags |= EF_M68K_CFV4E;
7719 /* Set file-specific flags if this is a cpu32 processor. */
7720 if (cpu_of_arch (current_architecture) & cpu32)
7721 flags |= EF_M68K_CPU32;
7722 else if (cpu_of_arch (current_architecture) & fido_a)
7723 flags |= EF_M68K_FIDO;
7724 else if ((cpu_of_arch (current_architecture) & m68000up)
7725 && !(cpu_of_arch (current_architecture) & m68020up))
7726 flags |= EF_M68K_M68000;
7728 if (current_architecture & mcfisa_a)
7730 static const unsigned isa_features[][2] =
7732 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7733 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7734 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7735 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7736 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7737 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7738 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7741 static const unsigned mac_features[][2] =
7743 {EF_M68K_CF_MAC, mcfmac},
7744 {EF_M68K_CF_EMAC, mcfemac},
7750 pattern = (current_architecture
7751 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7752 for (ix = 0; isa_features[ix][1]; ix++)
7754 if (pattern == isa_features[ix][1])
7756 flags |= isa_features[ix][0];
7760 if (!isa_features[ix][1])
7763 as_warn (_("Not a defined coldfire architecture"));
7767 if (current_architecture & cfloat)
7768 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7770 pattern = current_architecture & (mcfmac|mcfemac);
7773 for (ix = 0; mac_features[ix][1]; ix++)
7775 if (pattern == mac_features[ix][1])
7777 flags |= mac_features[ix][0];
7781 if (!mac_features[ix][1])
7786 elf_elfheader (stdoutput)->e_flags |= flags;
7791 tc_m68k_regname_to_dw2regnum (char *regname)
7793 unsigned int regnum;
7794 static const char *const regnames[] =
7796 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7797 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7798 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7802 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7803 if (strcmp (regname, regnames[regnum]) == 0)
7810 tc_m68k_frame_initial_instructions (void)
7812 static int sp_regno = -1;
7815 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7817 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7818 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);