1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
34 /* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38 #if defined (TE_SVR4) || defined (TE_DELTA)
39 const char *m68k_comment_chars = "|#";
41 const char *m68k_comment_chars = "|";
44 /* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47 /* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50 /* Also note that comments like this one will always work. */
51 const char line_comment_chars[] = "#*";
53 const char line_separator_chars[] = ";";
55 /* Chars that can be used to separate mant from exp in floating point nums */
56 CONST char EXP_CHARS[] = "eE";
58 /* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
61 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
63 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
67 const int md_reloc_size = 8; /* Size of relocation record */
69 /* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
71 references. Not implemented. For ELF there are other means
72 to denote pic relocations. */
75 static int flag_short_refs; /* -l option */
76 static int flag_long_jumps; /* -S option */
77 static int flag_keep_pcrel; /* --pcrel option. */
79 #ifdef REGISTER_PREFIX_OPTIONAL
80 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
82 int flag_reg_prefix_optional;
85 /* Whether --register-prefix-optional was used on the command line. */
86 static int reg_prefix_optional_seen;
88 /* The floating point coprocessor to use by default. */
89 static enum m68k_register m68k_float_copnum = COP1;
91 /* If this is non-zero, then references to number(%pc) will be taken
92 to refer to number, rather than to %pc + number. */
93 static int m68k_abspcadd;
95 /* If this is non-zero, then the quick forms of the move, add, and sub
96 instructions are used when possible. */
97 static int m68k_quick = 1;
99 /* If this is non-zero, then if the size is not specified for a base
100 or outer displacement, the assembler assumes that the size should
102 static int m68k_rel32 = 1;
104 /* This is non-zero if m68k_rel32 was set from the command line. */
105 static int m68k_rel32_from_cmdline;
107 /* The default width to use for an index register when using a base
109 static enum m68k_size m68k_index_width_default = SIZE_LONG;
111 /* We want to warn if any text labels are misaligned. In order to get
112 the right line number, we need to record the line number for each
117 struct label_line *next;
124 /* The list of labels. */
126 static struct label_line *labels;
128 /* The current label. */
130 static struct label_line *current_label;
132 /* Its an arbitrary name: This means I don't approve of it */
133 /* See flames below */
134 static struct obstack robyn;
138 const char *m_operands;
139 unsigned long m_opcode;
143 struct m68k_incant *m_next;
146 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
147 #define gettwo(x) (((x)->m_opcode)&0xffff)
149 static const enum m68k_register m68000_control_regs[] = { 0 };
150 static const enum m68k_register m68010_control_regs[] = {
154 static const enum m68k_register m68020_control_regs[] = {
155 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
158 static const enum m68k_register m68040_control_regs[] = {
159 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
160 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
163 static const enum m68k_register m68060_control_regs[] = {
164 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
165 USP, VBR, URP, SRP, PCR,
168 static const enum m68k_register mcf_control_regs[] = {
169 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
170 RAMBAR0, RAMBAR1, MBAR,
173 #define cpu32_control_regs m68010_control_regs
175 static const enum m68k_register *control_regs;
177 /* internal form of a 68020 instruction */
181 const char *args; /* list of opcode info */
184 int numo; /* Number of shorts in opcode */
187 struct m68k_op operands[6];
189 int nexp; /* number of exprs in use */
190 struct m68k_exp exprs[4];
192 int nfrag; /* Number of frags we have to produce */
195 int fragoff; /* Where in the current opcode the frag ends */
202 int nrel; /* Num of reloc strucs in use */
209 /* In a pc relative address the difference between the address
210 of the offset and the address that the offset is relative
211 to. This depends on the addressing mode. Basically this
212 is the value to put in the offset field to address the
213 first byte of the offset, without regarding the special
214 significance of some values (in the branch instruction, for
218 /* Whether this expression needs special pic relocation, and if
220 enum pic_relocation pic_reloc;
223 reloc[5]; /* Five is enough??? */
226 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
227 #define float_of_arch(x) ((x) & mfloat)
228 #define mmu_of_arch(x) ((x) & mmmu)
229 #define arch_coldfire_p(x) (((x) & mcf) != 0)
231 /* Macros for determining if cpu supports a specific addressing mode */
232 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
234 static struct m68k_it the_ins; /* the instruction being assembled */
236 #define op(ex) ((ex)->exp.X_op)
237 #define adds(ex) ((ex)->exp.X_add_symbol)
238 #define subs(ex) ((ex)->exp.X_op_symbol)
239 #define offs(ex) ((ex)->exp.X_add_number)
241 /* Macros for adding things to the m68k_it struct */
243 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
245 /* Static functions. */
247 static void insop PARAMS ((int, const struct m68k_incant *));
248 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
249 static void add_frag PARAMS ((symbolS *, offsetT, int));
251 /* Like addword, but goes BEFORE general operands */
255 const struct m68k_incant *opcode;
258 for(z=the_ins.numo;z>opcode->m_codenum;--z)
259 the_ins.opcode[z]=the_ins.opcode[z-1];
260 for(z=0;z<the_ins.nrel;z++)
261 the_ins.reloc[z].n+=2;
262 for (z = 0; z < the_ins.nfrag; z++)
263 the_ins.fragb[z].fragoff++;
264 the_ins.opcode[opcode->m_codenum]=w;
268 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
271 add_fix (width, exp, pc_rel, pc_fix)
273 struct m68k_exp *exp;
277 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
281 : (the_ins.numo*2)));
282 the_ins.reloc[the_ins.nrel].exp = exp->exp;
283 the_ins.reloc[the_ins.nrel].wid = width;
284 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
286 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
288 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
291 /* Cause an extra frag to be generated here, inserting up to 10 bytes
292 (that value is chosen in the frag_var call in md_assemble). TYPE
293 is the subtype of the frag to be generated; its primary type is
294 rs_machine_dependent.
296 The TYPE parameter is also used by md_convert_frag_1 and
297 md_estimate_size_before_relax. The appropriate type of fixup will
298 be emitted by md_convert_frag_1.
300 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
302 add_frag (add, off, type)
307 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
308 the_ins.fragb[the_ins.nfrag].fadd=add;
309 the_ins.fragb[the_ins.nfrag].foff=off;
310 the_ins.fragb[the_ins.nfrag++].fragty=type;
314 (op (ex) != O_constant && op (ex) != O_big)
316 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
317 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
318 static void m68k_ip PARAMS ((char *));
319 static void insert_reg PARAMS ((const char *, int));
320 static void select_control_regs PARAMS ((void));
321 static void init_regtable PARAMS ((void));
322 static int reverse_16_bits PARAMS ((int in));
323 static int reverse_8_bits PARAMS ((int in));
324 static void install_gen_operand PARAMS ((int mode, int val));
325 static void install_operand PARAMS ((int mode, int val));
326 static void s_bss PARAMS ((int));
327 static void s_data1 PARAMS ((int));
328 static void s_data2 PARAMS ((int));
329 static void s_even PARAMS ((int));
330 static void s_proc PARAMS ((int));
331 static void mri_chip PARAMS ((void));
332 static void s_chip PARAMS ((int));
333 static void s_fopt PARAMS ((int));
334 static void s_opt PARAMS ((int));
335 static void s_reg PARAMS ((int));
336 static void s_restore PARAMS ((int));
337 static void s_save PARAMS ((int));
338 static void s_mri_if PARAMS ((int));
339 static void s_mri_else PARAMS ((int));
340 static void s_mri_endi PARAMS ((int));
341 static void s_mri_break PARAMS ((int));
342 static void s_mri_next PARAMS ((int));
343 static void s_mri_for PARAMS ((int));
344 static void s_mri_endf PARAMS ((int));
345 static void s_mri_repeat PARAMS ((int));
346 static void s_mri_until PARAMS ((int));
347 static void s_mri_while PARAMS ((int));
348 static void s_mri_endw PARAMS ((int));
349 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
350 static void md_convert_frag_1 PARAMS ((fragS *));
352 static int current_architecture;
360 static const struct m68k_cpu archs[] = {
361 { m68000, "68000", 0 },
362 { m68010, "68010", 0 },
363 { m68020, "68020", 0 },
364 { m68030, "68030", 0 },
365 { m68040, "68040", 0 },
366 { m68060, "68060", 0 },
367 { cpu32, "cpu32", 0 },
368 { m68881, "68881", 0 },
369 { m68851, "68851", 0 },
370 { mcf5200, "5200", 0 },
371 { mcf5206e, "5206e", 0 },
372 { mcf5307, "5307", 0},
373 /* Aliases (effectively, so far as gas is concerned) for the above
375 { m68020, "68k", 1 },
376 { m68000, "68008", 1 },
377 { m68000, "68302", 1 },
378 { m68000, "68306", 1 },
379 { m68000, "68307", 1 },
380 { m68000, "68322", 1 },
381 { m68000, "68356", 1 },
382 { m68000, "68ec000", 1 },
383 { m68000, "68hc000", 1 },
384 { m68000, "68hc001", 1 },
385 { m68020, "68ec020", 1 },
386 { m68030, "68ec030", 1 },
387 { m68040, "68ec040", 1 },
388 { m68060, "68ec060", 1 },
389 { cpu32, "68330", 1 },
390 { cpu32, "68331", 1 },
391 { cpu32, "68332", 1 },
392 { cpu32, "68333", 1 },
393 { cpu32, "68334", 1 },
394 { cpu32, "68336", 1 },
395 { cpu32, "68340", 1 },
396 { cpu32, "68341", 1 },
397 { cpu32, "68349", 1 },
398 { cpu32, "68360", 1 },
399 { m68881, "68882", 1 },
400 { mcf5200, "5202", 1 },
401 { mcf5200, "5204", 1 },
402 { mcf5200, "5206", 1 },
405 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
407 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
408 architecture and we have a lot of relaxation modes. */
410 /* Macros used in the relaxation code. */
411 #define TAB(x,y) (((x) << 2) + (y))
412 #define TABTYPE(x) ((x) >> 2)
414 /* Relaxation states. */
420 /* Here are all the relaxation modes we support. First we can relax ordinary
421 branches. On 68020 and higher and on CPU32 all branch instructions take
422 three forms, so on these CPUs all branches always remain as such. When we
423 have to expand to the LONG form on a 68000, though, we substitute an
424 absolute jump instead. This is a direct replacement for unconditional
425 branches and a branch over a jump for conditional branches. However, if the
426 user requires PIC and disables this with --pcrel, we can only relax between
427 BYTE and SHORT forms, punting if that isn't enough. This gives us four
428 different relaxation modes for branches: */
430 #define BRANCHBWL 1 /* branch byte, word, or long */
431 #define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
432 #define BRABSJCOND 3 /* absolute jump for LONG, conditional */
433 #define BRANCHBW 4 /* branch byte or word */
435 /* We also relax coprocessor branches and DBcc's. All CPUs that support
436 coprocessor branches support them in word and long forms, so we have only
437 one relaxation mode for them. DBcc's are word only on all CPUs. We can
438 relax them to the LONG form with a branch-around sequence. This sequence
439 can use a long branch (if available) or an absolute jump (if acceptable).
440 This gives us two relaxation modes. If long branches are not available and
441 absolute jumps are not acceptable, we don't relax DBcc's. */
443 #define FBRANCH 5 /* coprocessor branch */
444 #define DBCCLBR 6 /* DBcc relaxable with a long branch */
445 #define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
447 /* That's all for instruction relaxation. However, we also relax PC-relative
448 operands. Specifically, we have three operand relaxation modes. On the
449 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
450 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
451 two. Also PC+displacement+index operands in their simple form (with a non-
452 suppressed index without memory indirection) are supported on all CPUs, but
453 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
454 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
455 form of the PC+displacement+index operand. Finally, some absolute operands
456 can be relaxed down to 16-bit PC-relative. */
458 #define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
459 #define PCINDEX 9 /* PC+displacement+index */
460 #define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
462 /* Note that calls to frag_var need to specify the maximum expansion
463 needed; this is currently 10 bytes for DBCC. */
466 How far Forward this mode will reach:
467 How far Backward this mode will reach:
468 How many bytes this mode will add to the size of the frag
469 Which mode to go to if the offset won't fit in this one
471 relax_typeS md_relax_table[] =
473 {1, 1, 0, 0}, /* First entries aren't used */
474 {1, 1, 0, 0}, /* For no good reason except */
475 {1, 1, 0, 0}, /* that the VAX doesn't either */
478 {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
479 {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
483 {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
484 {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
488 {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
489 {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
493 {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
498 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
499 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
503 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
504 {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
508 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
509 {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
513 {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
514 {32767, -32768, 2, TAB (PCREL1632, LONG)},
518 {125, -130, 0, TAB (PCINDEX, SHORT)},
519 {32765, -32770, 2, TAB (PCINDEX, LONG)},
523 {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
524 {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
529 /* These are the machine dependent pseudo-ops. These are included so
530 the assembler can work on the output from the SUN C compiler, which
534 /* This table describes all the machine specific pseudo-ops the assembler
535 has to support. The fields are:
536 pseudo-op name without dot
537 function to call to execute this pseudo-op
538 Integer arg to pass to the function
540 const pseudo_typeS md_pseudo_table[] =
542 {"data1", s_data1, 0},
543 {"data2", s_data2, 0},
546 {"skip", s_space, 0},
548 #if defined (TE_SUN3) || defined (OBJ_ELF)
549 {"align", s_align_bytes, 0},
552 {"swbeg", s_ignore, 0},
554 {"extend", float_cons, 'x'},
555 {"ldouble", float_cons, 'x'},
557 /* The following pseudo-ops are supported for MRI compatibility. */
559 {"comline", s_space, 1},
561 {"mask2", s_ignore, 0},
564 {"restore", s_restore, 0},
568 {"if.b", s_mri_if, 'b'},
569 {"if.w", s_mri_if, 'w'},
570 {"if.l", s_mri_if, 'l'},
571 {"else", s_mri_else, 0},
572 {"else.s", s_mri_else, 's'},
573 {"else.l", s_mri_else, 'l'},
574 {"endi", s_mri_endi, 0},
575 {"break", s_mri_break, 0},
576 {"break.s", s_mri_break, 's'},
577 {"break.l", s_mri_break, 'l'},
578 {"next", s_mri_next, 0},
579 {"next.s", s_mri_next, 's'},
580 {"next.l", s_mri_next, 'l'},
581 {"for", s_mri_for, 0},
582 {"for.b", s_mri_for, 'b'},
583 {"for.w", s_mri_for, 'w'},
584 {"for.l", s_mri_for, 'l'},
585 {"endf", s_mri_endf, 0},
586 {"repeat", s_mri_repeat, 0},
587 {"until", s_mri_until, 0},
588 {"until.b", s_mri_until, 'b'},
589 {"until.w", s_mri_until, 'w'},
590 {"until.l", s_mri_until, 'l'},
591 {"while", s_mri_while, 0},
592 {"while.b", s_mri_while, 'b'},
593 {"while.w", s_mri_while, 'w'},
594 {"while.l", s_mri_while, 'l'},
595 {"endw", s_mri_endw, 0},
600 /* The mote pseudo ops are put into the opcode table, since they
601 don't start with a . they look like opcodes to gas.
605 extern void obj_coff_section PARAMS ((int));
608 CONST pseudo_typeS mote_pseudo_table[] =
621 {"xdef", s_globl, 0},
623 {"align", s_align_bytes, 0},
625 {"align", s_align_ptwo, 0},
628 {"sect", obj_coff_section, 0},
629 {"section", obj_coff_section, 0},
634 #define issbyte(x) ((x)>=-128 && (x)<=127)
635 #define isubyte(x) ((x)>=0 && (x)<=255)
636 #define issword(x) ((x)>=-32768 && (x)<=32767)
637 #define isuword(x) ((x)>=0 && (x)<=65535)
639 #define isbyte(x) ((x)>= -255 && (x)<=255)
640 #define isword(x) ((x)>=-65536 && (x)<=65535)
641 #define islong(x) (1)
643 extern char *input_line_pointer;
645 static char mklower_table[256];
646 #define mklower(c) (mklower_table[(unsigned char)(c)])
647 static char notend_table[256];
648 static char alt_notend_table[256];
650 (! (notend_table[(unsigned char) *s] \
652 && alt_notend_table[(unsigned char) s[1]])))
654 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
656 #ifdef NO_PCREL_RELOCS
659 make_pcrel_absolute(fixP, add_number)
663 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
665 /* rewrite the PC relative instructions to absolute address ones.
666 * these are rumoured to be faster, and the apollo linker refuses
667 * to deal with the PC relative relocations.
669 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
674 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
680 as_fatal (_("Unknown PC relative instruction"));
685 #endif /* NO_PCREL_RELOCS */
688 tc_coff_fix2rtype (fixP)
691 if (fixP->fx_tcbit && fixP->fx_size == 4)
692 return R_RELLONG_NEG;
693 #ifdef NO_PCREL_RELOCS
694 know (fixP->fx_pcrel == 0);
695 return (fixP->fx_size == 1 ? R_RELBYTE
696 : fixP->fx_size == 2 ? R_DIR16
699 return (fixP->fx_pcrel ?
700 (fixP->fx_size == 1 ? R_PCRBYTE :
701 fixP->fx_size == 2 ? R_PCRWORD :
703 (fixP->fx_size == 1 ? R_RELBYTE :
704 fixP->fx_size == 2 ? R_RELWORD :
713 /* Compute the relocation code for a fixup of SIZE bytes, using pc
714 relative relocation if PCREL is non-zero. PIC says whether a special
715 pic relocation was requested. */
717 static bfd_reloc_code_real_type get_reloc_code
718 PARAMS ((int, int, enum pic_relocation));
720 static bfd_reloc_code_real_type
721 get_reloc_code (size, pcrel, pic)
724 enum pic_relocation pic;
732 return BFD_RELOC_8_GOT_PCREL;
734 return BFD_RELOC_16_GOT_PCREL;
736 return BFD_RELOC_32_GOT_PCREL;
744 return BFD_RELOC_8_GOTOFF;
746 return BFD_RELOC_16_GOTOFF;
748 return BFD_RELOC_32_GOTOFF;
756 return BFD_RELOC_8_PLT_PCREL;
758 return BFD_RELOC_16_PLT_PCREL;
760 return BFD_RELOC_32_PLT_PCREL;
768 return BFD_RELOC_8_PLTOFF;
770 return BFD_RELOC_16_PLTOFF;
772 return BFD_RELOC_32_PLTOFF;
782 return BFD_RELOC_8_PCREL;
784 return BFD_RELOC_16_PCREL;
786 return BFD_RELOC_32_PCREL;
806 as_bad (_("Can not do %d byte pc-relative relocation"), size);
808 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
813 as_bad (_("Can not do %d byte relocation"), size);
815 as_bad (_("Can not do %d byte pic relocation"), size);
818 return BFD_RELOC_NONE;
821 /* Here we decide which fixups can be adjusted to make them relative
822 to the beginning of the section instead of the symbol. Basically
823 we need to make sure that the dynamic relocations are done
824 correctly, so in some cases we force the original symbol to be
827 tc_m68k_fix_adjustable (fixP)
830 /* Prevent all adjustments to global symbols. */
831 if (S_IS_EXTERNAL (fixP->fx_addsy)
832 || S_IS_WEAK (fixP->fx_addsy))
835 /* adjust_reloc_syms doesn't know about the GOT */
836 switch (fixP->fx_r_type)
838 case BFD_RELOC_8_GOT_PCREL:
839 case BFD_RELOC_16_GOT_PCREL:
840 case BFD_RELOC_32_GOT_PCREL:
841 case BFD_RELOC_8_GOTOFF:
842 case BFD_RELOC_16_GOTOFF:
843 case BFD_RELOC_32_GOTOFF:
844 case BFD_RELOC_8_PLT_PCREL:
845 case BFD_RELOC_16_PLT_PCREL:
846 case BFD_RELOC_32_PLT_PCREL:
847 case BFD_RELOC_8_PLTOFF:
848 case BFD_RELOC_16_PLTOFF:
849 case BFD_RELOC_32_PLTOFF:
852 case BFD_RELOC_VTABLE_INHERIT:
853 case BFD_RELOC_VTABLE_ENTRY:
863 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
870 tc_gen_reloc (section, fixp)
875 bfd_reloc_code_real_type code;
880 if (fixp->fx_r_type != BFD_RELOC_NONE)
882 code = fixp->fx_r_type;
884 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
885 that fixup_segment converted a non-PC relative reloc into a
886 PC relative reloc. In such a case, we need to convert the
893 code = BFD_RELOC_8_PCREL;
896 code = BFD_RELOC_16_PCREL;
899 code = BFD_RELOC_32_PCREL;
901 case BFD_RELOC_8_PCREL:
902 case BFD_RELOC_16_PCREL:
903 case BFD_RELOC_32_PCREL:
904 case BFD_RELOC_8_GOT_PCREL:
905 case BFD_RELOC_16_GOT_PCREL:
906 case BFD_RELOC_32_GOT_PCREL:
907 case BFD_RELOC_8_GOTOFF:
908 case BFD_RELOC_16_GOTOFF:
909 case BFD_RELOC_32_GOTOFF:
910 case BFD_RELOC_8_PLT_PCREL:
911 case BFD_RELOC_16_PLT_PCREL:
912 case BFD_RELOC_32_PLT_PCREL:
913 case BFD_RELOC_8_PLTOFF:
914 case BFD_RELOC_16_PLTOFF:
915 case BFD_RELOC_32_PLTOFF:
918 as_bad_where (fixp->fx_file, fixp->fx_line,
919 _("Cannot make %s relocation PC relative"),
920 bfd_get_reloc_code_name (code));
926 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
927 switch (F (fixp->fx_size, fixp->fx_pcrel))
929 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
930 MAP (1, 0, BFD_RELOC_8);
931 MAP (2, 0, BFD_RELOC_16);
932 MAP (4, 0, BFD_RELOC_32);
933 MAP (1, 1, BFD_RELOC_8_PCREL);
934 MAP (2, 1, BFD_RELOC_16_PCREL);
935 MAP (4, 1, BFD_RELOC_32_PCREL);
943 reloc = (arelent *) xmalloc (sizeof (arelent));
944 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
945 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
946 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
949 reloc->addend = fixp->fx_addnumber;
954 reloc->addend = fixp->fx_addnumber;
956 reloc->addend = (section->vma
957 + (fixp->fx_pcrel_adjust == 64
958 ? -1 : fixp->fx_pcrel_adjust)
960 + md_pcrel_from (fixp));
963 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
964 assert (reloc->howto != 0);
969 #endif /* BFD_ASSEMBLER */
971 /* Return zero if the reference to SYMBOL from within the same segment may
975 /* On an ELF system, we can't relax an externally visible symbol,
976 because it may be overridden by a shared library. However, if
977 TARGET_OS is "elf", then we presume that we are assembling for an
978 embedded system, in which case we don't have to worry about shared
979 libraries, and we can relax anything. */
981 #define relaxable_symbol(symbol) \
982 (strcmp (TARGET_OS, "elf") == 0 \
983 || (! S_IS_EXTERNAL (symbol) \
984 && ! S_IS_WEAK (symbol)))
988 #define relaxable_symbol(symbol) 1
992 /* Handle of the OPCODE hash table. NULL means any use before
993 m68k_ip_begin() will crash. */
994 static struct hash_control *op_hash;
996 /* Assemble an m68k instruction. */
1003 register struct m68k_op *opP;
1004 register const struct m68k_incant *opcode;
1005 register const char *s;
1006 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1007 char *pdot, *pdotmove;
1008 enum m68k_size siz1, siz2;
1012 LITTLENUM_TYPE words[6];
1013 LITTLENUM_TYPE *wordp;
1014 unsigned long ok_arch = 0;
1016 if (*instring == ' ')
1017 instring++; /* skip leading whitespace */
1019 /* Scan up to end of operation-code, which MUST end in end-of-string
1020 or exactly 1 space. */
1022 for (p = instring; *p != '\0'; p++)
1032 the_ins.error = _("No operator");
1036 /* p now points to the end of the opcode name, probably whitespace.
1037 Make sure the name is null terminated by clobbering the
1038 whitespace, look it up in the hash table, then fix it back.
1039 Remove a dot, first, since the opcode tables have none. */
1042 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1043 *pdotmove = pdotmove[1];
1049 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1054 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1055 *pdotmove = pdotmove[-1];
1062 the_ins.error = _("Unknown operator");
1066 /* found a legitimate opcode, start matching operands */
1070 if (opcode->m_operands == 0)
1072 char *old = input_line_pointer;
1074 input_line_pointer = p;
1075 /* Ahh - it's a motorola style psuedo op */
1076 mote_pseudo_table[opcode->m_opnum].poc_handler
1077 (mote_pseudo_table[opcode->m_opnum].poc_val);
1078 input_line_pointer = old;
1084 if (flag_mri && opcode->m_opnum == 0)
1086 /* In MRI mode, random garbage is allowed after an instruction
1087 which accepts no operands. */
1088 the_ins.args = opcode->m_operands;
1089 the_ins.numargs = opcode->m_opnum;
1090 the_ins.numo = opcode->m_codenum;
1091 the_ins.opcode[0] = getone (opcode);
1092 the_ins.opcode[1] = gettwo (opcode);
1096 for (opP = &the_ins.operands[0]; *p; opP++)
1098 p = crack_operand (p, opP);
1102 the_ins.error = opP->error;
1107 opsfound = opP - &the_ins.operands[0];
1109 /* This ugly hack is to support the floating pt opcodes in their
1110 standard form. Essentially, we fake a first enty of type COP#1 */
1111 if (opcode->m_operands[0] == 'I')
1115 for (n = opsfound; n > 0; --n)
1116 the_ins.operands[n] = the_ins.operands[n - 1];
1118 memset ((char *) (&the_ins.operands[0]), '\0',
1119 sizeof (the_ins.operands[0]));
1120 the_ins.operands[0].mode = CONTROL;
1121 the_ins.operands[0].reg = m68k_float_copnum;
1125 /* We've got the operands. Find an opcode that'll accept them */
1128 /* If we didn't get the right number of ops, or we have no
1129 common model with this pattern then reject this pattern. */
1131 ok_arch |= opcode->m_arch;
1132 if (opsfound != opcode->m_opnum
1133 || ((opcode->m_arch & current_architecture) == 0))
1137 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1141 /* Warning: this switch is huge! */
1142 /* I've tried to organize the cases into this order:
1143 non-alpha first, then alpha by letter. Lower-case
1144 goes directly before uppercase counterpart. */
1145 /* Code with multiple case ...: gets sorted by the lowest
1146 case ... it belongs to. I hope this makes sense. */
1252 if (opP->reg == PC || opP->reg == ZPC)
1269 if (opP->reg == PC || opP->reg == ZPC)
1288 if (opP->reg == PC || opP->reg == ZPC)
1298 if (opP->mode != IMMED)
1300 else if (s[1] == 'b'
1301 && ! isvar (&opP->disp)
1302 && (opP->disp.exp.X_op != O_constant
1303 || ! isbyte (opP->disp.exp.X_add_number)))
1305 else if (s[1] == 'B'
1306 && ! isvar (&opP->disp)
1307 && (opP->disp.exp.X_op != O_constant
1308 || ! issbyte (opP->disp.exp.X_add_number)))
1310 else if (s[1] == 'w'
1311 && ! isvar (&opP->disp)
1312 && (opP->disp.exp.X_op != O_constant
1313 || ! isword (opP->disp.exp.X_add_number)))
1315 else if (s[1] == 'W'
1316 && ! isvar (&opP->disp)
1317 && (opP->disp.exp.X_op != O_constant
1318 || ! issword (opP->disp.exp.X_add_number)))
1324 if (opP->mode != IMMED)
1329 if (opP->mode == AREG
1330 || opP->mode == CONTROL
1331 || opP->mode == FPREG
1332 || opP->mode == IMMED
1333 || opP->mode == REGLST
1334 || (opP->mode != ABSL
1336 || opP->reg == ZPC)))
1341 if (opP->mode == CONTROL
1342 || opP->mode == FPREG
1343 || opP->mode == REGLST
1344 || opP->mode == IMMED
1345 || (opP->mode != ABSL
1347 || opP->reg == ZPC)))
1375 if (opP->mode == CONTROL
1376 || opP->mode == FPREG
1377 || opP->mode == REGLST)
1382 if (opP->mode != AINC)
1387 if (opP->mode != ADEC)
1437 if (opP->reg == PC || opP->reg == ZPC)
1458 case '~': /* For now! (JF FOO is this right?) */
1480 if (opP->mode != CONTROL
1481 || (opP->reg != TT0 && opP->reg != TT1))
1486 if (opP->mode != AREG)
1491 if (opP->mode != AINDR)
1496 if (opP->mode != ABSL
1498 && strncmp (instring, "jbsr", 4) == 0))
1503 if (opP->mode != CONTROL || opP->reg != CCR)
1508 if (opP->mode != DISP
1510 || opP->reg > ADDR7)
1515 if (opP->mode != DREG)
1520 if (opP->reg != ACC)
1525 if (opP->mode != FPREG)
1530 if (opP->reg != MACSR)
1535 if (opP->reg != MASK)
1540 if (opP->mode != CONTROL
1547 if (opP->mode != CONTROL
1549 || opP->reg > last_movec_reg)
1553 const enum m68k_register *rp;
1554 for (rp = control_regs; *rp; rp++)
1555 if (*rp == opP->reg)
1563 if (opP->mode != IMMED)
1569 if (opP->mode == DREG
1570 || opP->mode == AREG
1571 || opP->mode == FPREG)
1580 opP->mask = 1 << (opP->reg - DATA0);
1583 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1586 opP->mask = 1 << (opP->reg - FP0 + 16);
1594 else if (opP->mode == CONTROL)
1603 opP->mask = 1 << 24;
1606 opP->mask = 1 << 25;
1609 opP->mask = 1 << 26;
1618 else if (opP->mode != REGLST)
1620 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1622 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1627 if (opP->mode != IMMED)
1629 else if (opP->disp.exp.X_op != O_constant
1630 || ! issbyte (opP->disp.exp.X_add_number))
1632 else if (! m68k_quick
1633 && instring[3] != 'q'
1634 && instring[4] != 'q')
1639 if (opP->mode != DREG
1640 && opP->mode != IMMED
1641 && opP->mode != ABSL)
1646 if (opP->mode != IMMED)
1648 else if (opP->disp.exp.X_op != O_constant
1649 || opP->disp.exp.X_add_number < 1
1650 || opP->disp.exp.X_add_number > 8)
1652 else if (! m68k_quick
1653 && (strncmp (instring, "add", 3) == 0
1654 || strncmp (instring, "sub", 3) == 0)
1655 && instring[3] != 'q')
1660 if (opP->mode != DREG && opP->mode != AREG)
1665 if (opP->mode != AINDR
1666 && (opP->mode != BASE
1668 && opP->reg != ZADDR0)
1669 || opP->disp.exp.X_op != O_absent
1670 || ((opP->index.reg < DATA0
1671 || opP->index.reg > DATA7)
1672 && (opP->index.reg < ADDR0
1673 || opP->index.reg > ADDR7))
1674 || opP->index.size != SIZE_UNSPEC
1675 || opP->index.scale != 1))
1680 if (opP->mode != CONTROL
1681 || ! (opP->reg == FPI
1683 || opP->reg == FPC))
1688 if (opP->mode != CONTROL || opP->reg != SR)
1693 if (opP->mode != IMMED)
1695 else if (opP->disp.exp.X_op != O_constant
1696 || opP->disp.exp.X_add_number < 0
1697 || opP->disp.exp.X_add_number > 7)
1702 if (opP->mode != CONTROL || opP->reg != USP)
1706 /* JF these are out of order. We could put them
1707 in order if we were willing to put up with
1708 bunches of #ifdef m68851s in the code.
1710 Don't forget that you need these operands
1711 to use 68030 MMU instructions. */
1713 /* Memory addressing mode used by pflushr */
1715 if (opP->mode == CONTROL
1716 || opP->mode == FPREG
1717 || opP->mode == DREG
1718 || opP->mode == AREG
1719 || opP->mode == REGLST)
1721 /* We should accept immediate operands, but they
1722 supposedly have to be quad word, and we don't
1723 handle that. I would like to see what a Motorola
1724 assembler does before doing something here. */
1725 if (opP->mode == IMMED)
1730 if (opP->mode != CONTROL
1731 || (opP->reg != SFC && opP->reg != DFC))
1736 if (opP->mode != CONTROL || opP->reg != TC)
1741 if (opP->mode != CONTROL || opP->reg != AC)
1746 if (opP->mode != CONTROL
1749 && opP->reg != SCC))
1754 if (opP->mode != CONTROL
1760 if (opP->mode != CONTROL
1763 && opP->reg != CRP))
1768 if (opP->mode != CONTROL
1769 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1770 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1775 if (opP->mode != CONTROL || opP->reg != PSR)
1780 if (opP->mode != CONTROL || opP->reg != PCSR)
1785 if (opP->mode != CONTROL
1792 } /* not a cache specifier. */
1796 if (opP->mode != ABSL)
1801 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1803 /* FIXME: kludge instead of fixing parser:
1804 upper/lower registers are *not* CONTROL
1805 registers, but ordinary ones. */
1806 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1807 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1815 } /* switch on type of operand */
1819 } /* for each operand */
1820 } /* if immediately wrong */
1827 opcode = opcode->m_next;
1832 && !(ok_arch & current_architecture))
1837 _("invalid instruction for this architecture; needs "));
1838 cp = buf + strlen (buf);
1842 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1845 strcpy (cp, _("mmu (68030 or 68851)"));
1848 strcpy (cp, _("68020 or higher"));
1851 strcpy (cp, _("68000 or higher"));
1854 strcpy (cp, _("68010 or higher"));
1858 int got_one = 0, idx;
1860 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1863 if ((archs[idx].arch & ok_arch)
1864 && ! archs[idx].alias)
1868 strcpy (cp, " or ");
1872 strcpy (cp, archs[idx].name);
1878 cp = xmalloc (strlen (buf) + 1);
1883 the_ins.error = _("operands mismatch");
1885 } /* Fell off the end */
1890 /* now assemble it */
1892 the_ins.args = opcode->m_operands;
1893 the_ins.numargs = opcode->m_opnum;
1894 the_ins.numo = opcode->m_codenum;
1895 the_ins.opcode[0] = getone (opcode);
1896 the_ins.opcode[1] = gettwo (opcode);
1898 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1900 /* This switch is a doozy.
1901 Watch the first step; its a big one! */
1929 tmpreg = 0x3c; /* 7.4 */
1930 if (strchr ("bwl", s[1]))
1931 nextword = get_num (&opP->disp, 80);
1933 nextword = get_num (&opP->disp, 0);
1934 if (isvar (&opP->disp))
1935 add_fix (s[1], &opP->disp, 0, 0);
1939 if (!isbyte (nextword))
1940 opP->error = _("operand out of range");
1945 if (!isword (nextword))
1946 opP->error = _("operand out of range");
1951 if (!issword (nextword))
1952 opP->error = _("operand out of range");
1957 addword (nextword >> 16);
1984 /* We gotta put out some float */
1985 if (op (&opP->disp) != O_big)
1990 /* Can other cases happen here? */
1991 if (op (&opP->disp) != O_constant)
1994 val = (valueT) offs (&opP->disp);
1998 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1999 val >>= LITTLENUM_NUMBER_OF_BITS;
2003 offs (&opP->disp) = gencnt;
2005 if (offs (&opP->disp) > 0)
2007 if (offs (&opP->disp) > baseo)
2009 as_warn (_("Bignum too big for %c format; truncated"),
2011 offs (&opP->disp) = baseo;
2013 baseo -= offs (&opP->disp);
2016 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2017 offs (&opP->disp)--;
2022 gen_to_words (words, baseo, (long) outro);
2023 for (wordp = words; baseo--; wordp++)
2027 tmpreg = opP->reg - DATA; /* 0.dreg */
2030 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2033 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2036 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2039 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2043 nextword = get_num (&opP->disp, 80);
2046 && ! isvar (&opP->disp)
2049 opP->disp.exp.X_op = O_symbol;
2050 #ifndef BFD_ASSEMBLER
2051 opP->disp.exp.X_add_symbol = &abs_symbol;
2053 opP->disp.exp.X_add_symbol =
2054 section_symbol (absolute_section);
2058 /* Force into index mode. Hope this works */
2060 /* We do the first bit for 32-bit displacements, and the
2061 second bit for 16 bit ones. It is possible that we
2062 should make the default be WORD instead of LONG, but
2063 I think that'd break GCC, so we put up with a little
2064 inefficiency for the sake of working output. */
2066 if (!issword (nextword)
2067 || (isvar (&opP->disp)
2068 && ((opP->disp.size == SIZE_UNSPEC
2069 && flag_short_refs == 0
2070 && cpu_of_arch (current_architecture) >= m68020
2071 && ! arch_coldfire_p (current_architecture))
2072 || opP->disp.size == SIZE_LONG)))
2074 if (cpu_of_arch (current_architecture) < m68020
2075 || arch_coldfire_p (current_architecture))
2077 _("displacement too large for this architecture; needs 68020 or higher");
2079 tmpreg = 0x3B; /* 7.3 */
2081 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2082 if (isvar (&opP->disp))
2086 if (opP->disp.size == SIZE_LONG
2088 /* If the displacement needs pic
2089 relocation it cannot be relaxed. */
2090 || opP->disp.pic_reloc != pic_none
2095 add_fix ('l', &opP->disp, 1, 2);
2099 add_frag (adds (&opP->disp),
2101 TAB (PCREL1632, SZ_UNDEF));
2108 add_fix ('l', &opP->disp, 0, 0);
2113 addword (nextword >> 16);
2118 tmpreg = 0x3A; /* 7.2 */
2120 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2122 if (isvar (&opP->disp))
2126 add_fix ('w', &opP->disp, 1, 0);
2129 add_fix ('w', &opP->disp, 0, 0);
2139 baseo = get_num (&opP->disp, 80);
2140 if (opP->mode == POST || opP->mode == PRE)
2141 outro = get_num (&opP->odisp, 80);
2142 /* Figure out the `addressing mode'.
2143 Also turn on the BASE_DISABLE bit, if needed. */
2144 if (opP->reg == PC || opP->reg == ZPC)
2146 tmpreg = 0x3b; /* 7.3 */
2147 if (opP->reg == ZPC)
2150 else if (opP->reg == 0)
2153 tmpreg = 0x30; /* 6.garbage */
2155 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2158 tmpreg = 0x30 + opP->reg - ZADDR0;
2161 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2163 siz1 = opP->disp.size;
2164 if (opP->mode == POST || opP->mode == PRE)
2165 siz2 = opP->odisp.size;
2169 /* Index register stuff */
2170 if (opP->index.reg != 0
2171 && opP->index.reg >= DATA
2172 && opP->index.reg <= ADDR7)
2174 nextword |= (opP->index.reg - DATA) << 12;
2176 if (opP->index.size == SIZE_LONG
2177 || (opP->index.size == SIZE_UNSPEC
2178 && m68k_index_width_default == SIZE_LONG))
2181 if ((opP->index.scale != 1
2182 && cpu_of_arch (current_architecture) < m68020)
2183 || (opP->index.scale == 8
2184 && arch_coldfire_p (current_architecture)))
2187 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2190 if (arch_coldfire_p (current_architecture)
2191 && opP->index.size == SIZE_WORD)
2192 opP->error = _("invalid index size for coldfire");
2194 switch (opP->index.scale)
2211 GET US OUT OF HERE! */
2213 /* Must be INDEX, with an index register. Address
2214 register cannot be ZERO-PC, and either :b was
2215 forced, or we know it will fit. For a 68000 or
2216 68010, force this mode anyways, because the
2217 larger modes aren't supported. */
2218 if (opP->mode == BASE
2219 && ((opP->reg >= ADDR0
2220 && opP->reg <= ADDR7)
2223 if (siz1 == SIZE_BYTE
2224 || cpu_of_arch (current_architecture) < m68020
2225 || arch_coldfire_p (current_architecture)
2226 || (siz1 == SIZE_UNSPEC
2227 && ! isvar (&opP->disp)
2228 && issbyte (baseo)))
2230 nextword += baseo & 0xff;
2232 if (isvar (&opP->disp))
2234 /* Do a byte relocation. If it doesn't
2235 fit (possible on m68000) let the
2236 fixup processing complain later. */
2238 add_fix ('B', &opP->disp, 1, 1);
2240 add_fix ('B', &opP->disp, 0, 0);
2242 else if (siz1 != SIZE_BYTE)
2244 if (siz1 != SIZE_UNSPEC)
2245 as_warn (_("Forcing byte displacement"));
2246 if (! issbyte (baseo))
2247 opP->error = _("byte displacement out of range");
2252 else if (siz1 == SIZE_UNSPEC
2254 && isvar (&opP->disp)
2255 && subs (&opP->disp) == NULL
2257 /* If the displacement needs pic
2258 relocation it cannot be relaxed. */
2259 && opP->disp.pic_reloc == pic_none
2263 /* The code in md_convert_frag_1 needs to be
2264 able to adjust nextword. Call frag_grow
2265 to ensure that we have enough space in
2266 the frag obstack to make all the bytes
2269 nextword += baseo & 0xff;
2271 add_frag (adds (&opP->disp), offs (&opP->disp),
2272 TAB (PCINDEX, SZ_UNDEF));
2280 nextword |= 0x40; /* No index reg */
2281 if (opP->index.reg >= ZDATA0
2282 && opP->index.reg <= ZDATA7)
2283 nextword |= (opP->index.reg - ZDATA0) << 12;
2284 else if (opP->index.reg >= ZADDR0
2285 || opP->index.reg <= ZADDR7)
2286 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2289 /* It isn't simple. */
2291 if (cpu_of_arch (current_architecture) < m68020
2292 || arch_coldfire_p (current_architecture))
2294 _("invalid operand mode for this architecture; needs 68020 or higher");
2297 /* If the guy specified a width, we assume that it is
2298 wide enough. Maybe it isn't. If so, we lose. */
2302 if (isvar (&opP->disp)
2304 : ! issword (baseo))
2309 else if (! isvar (&opP->disp) && baseo == 0)
2318 as_warn (_(":b not permitted; defaulting to :w"));
2328 /* Figure out innner displacement stuff */
2329 if (opP->mode == POST || opP->mode == PRE)
2331 if (cpu_of_arch (current_architecture) & cpu32)
2332 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2336 if (isvar (&opP->odisp)
2338 : ! issword (outro))
2343 else if (! isvar (&opP->odisp) && outro == 0)
2352 as_warn (_(":b not permitted; defaulting to :w"));
2361 if (opP->mode == POST
2362 && (nextword & 0x40) == 0)
2367 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2369 if (opP->reg == PC || opP->reg == ZPC)
2370 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2372 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2374 if (siz1 == SIZE_LONG)
2375 addword (baseo >> 16);
2376 if (siz1 != SIZE_UNSPEC)
2379 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2380 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2381 if (siz2 == SIZE_LONG)
2382 addword (outro >> 16);
2383 if (siz2 != SIZE_UNSPEC)
2389 nextword = get_num (&opP->disp, 80);
2390 switch (opP->disp.size)
2395 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2397 tmpreg = 0x38; /* 7.0 */
2401 if (isvar (&opP->disp)
2402 && !subs (&opP->disp)
2403 && adds (&opP->disp)
2405 /* If the displacement needs pic relocation it
2406 cannot be relaxed. */
2407 && opP->disp.pic_reloc == pic_none
2410 && !strchr ("~%&$?", s[0]))
2412 tmpreg = 0x3A; /* 7.2 */
2413 add_frag (adds (&opP->disp),
2415 TAB (ABSTOPCREL, SZ_UNDEF));
2418 /* Fall through into long */
2420 if (isvar (&opP->disp))
2421 add_fix ('l', &opP->disp, 0, 0);
2423 tmpreg = 0x39;/* 7.1 mode */
2424 addword (nextword >> 16);
2429 as_bad (_("unsupported byte value; use a different suffix"));
2431 case SIZE_WORD: /* Word */
2432 if (isvar (&opP->disp))
2433 add_fix ('w', &opP->disp, 0, 0);
2435 tmpreg = 0x38;/* 7.0 mode */
2443 as_bad (_("unknown/incorrect operand"));
2446 install_gen_operand (s[1], tmpreg);
2452 { /* JF: I hate floating point! */
2467 tmpreg = get_num (&opP->disp, tmpreg);
2468 if (isvar (&opP->disp))
2469 add_fix (s[1], &opP->disp, 0, 0);
2472 case 'b': /* Danger: These do no check for
2473 certain types of overflow.
2475 if (!isbyte (tmpreg))
2476 opP->error = _("out of range");
2477 insop (tmpreg, opcode);
2478 if (isvar (&opP->disp))
2479 the_ins.reloc[the_ins.nrel - 1].n =
2480 (opcode->m_codenum) * 2 + 1;
2483 if (!issbyte (tmpreg))
2484 opP->error = _("out of range");
2485 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2486 if (isvar (&opP->disp))
2487 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2490 if (!isword (tmpreg))
2491 opP->error = _("out of range");
2492 insop (tmpreg, opcode);
2493 if (isvar (&opP->disp))
2494 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2497 if (!issword (tmpreg))
2498 opP->error = _("out of range");
2499 insop (tmpreg, opcode);
2500 if (isvar (&opP->disp))
2501 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2504 /* Because of the way insop works, we put these two out
2506 insop (tmpreg, opcode);
2507 insop (tmpreg >> 16, opcode);
2508 if (isvar (&opP->disp))
2509 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2516 install_operand (s[1], tmpreg);
2527 install_operand (s[1], opP->reg - ADDR);
2531 tmpreg = get_num (&opP->disp, 80);
2535 /* The pc_fix argument winds up in fx_pcrel_adjust,
2536 which is a char, and may therefore be unsigned. We
2537 want to pass -1, but we pass 64 instead, and convert
2538 back in md_pcrel_from. */
2539 add_fix ('B', &opP->disp, 1, 64);
2542 add_fix ('w', &opP->disp, 1, 0);
2547 if (! HAVE_LONG_BRANCH (current_architecture))
2548 as_warn (_("Can't use long branches on 68000/68010/5200"));
2549 the_ins.opcode[0] |= 0xff;
2550 add_fix ('l', &opP->disp, 1, 0);
2555 if (subs (&opP->disp)) /* We can't relax it */
2559 /* If the displacement needs pic relocation it cannot be
2561 if (opP->disp.pic_reloc != pic_none)
2564 /* This could either be a symbol, or an absolute
2565 address. If it's an absolute address, turn it into
2566 an absolute jump right here and keep it out of the
2568 if (adds (&opP->disp) == 0)
2570 if (the_ins.opcode[0] == 0x6000) /* jbra */
2571 the_ins.opcode[0] = 0x4EF1;
2572 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2573 the_ins.opcode[0] = 0x4EB1;
2576 the_ins.opcode[0] ^= 0x0100;
2577 the_ins.opcode[0] |= 0x0006;
2580 add_fix ('l', &opP->disp, 0, 0);
2586 /* Now we know it's going into the relaxer. Now figure
2587 out which mode. We try in this order of preference:
2588 long branch, absolute jump, byte/word branches only. */
2589 if (HAVE_LONG_BRANCH (current_architecture))
2590 add_frag (adds (&opP->disp), offs (&opP->disp),
2591 TAB (BRANCHBWL, SZ_UNDEF));
2592 else if (! flag_keep_pcrel)
2594 if ((the_ins.opcode[0] == 0x6000)
2595 || (the_ins.opcode[0] == 0x6100))
2596 add_frag (adds (&opP->disp), offs (&opP->disp),
2597 TAB (BRABSJUNC, SZ_UNDEF));
2599 add_frag (adds (&opP->disp), offs (&opP->disp),
2600 TAB (BRABSJCOND, SZ_UNDEF));
2603 add_frag (adds (&opP->disp), offs (&opP->disp),
2604 TAB (BRANCHBW, SZ_UNDEF));
2607 if (isvar (&opP->disp))
2609 /* Check for DBcc instructions. We can relax them,
2610 but only if we have long branches and/or absolute
2612 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2613 && (HAVE_LONG_BRANCH (current_architecture)
2614 || (! flag_keep_pcrel)))
2616 if (HAVE_LONG_BRANCH (current_architecture))
2617 add_frag (adds (&opP->disp), offs (&opP->disp),
2618 TAB (DBCCLBR, SZ_UNDEF));
2620 add_frag (adds (&opP->disp), offs (&opP->disp),
2621 TAB (DBCCABSJ, SZ_UNDEF));
2624 add_fix ('w', &opP->disp, 1, 0);
2628 case 'C': /* Fixed size LONG coproc branches */
2629 add_fix ('l', &opP->disp, 1, 0);
2633 case 'c': /* Var size Coprocesssor branches */
2634 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2636 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2637 add_fix ('l', &opP->disp, 1, 0);
2642 add_frag (adds (&opP->disp), offs (&opP->disp),
2643 TAB (FBRANCH, SZ_UNDEF));
2650 case 'C': /* Ignore it */
2653 case 'd': /* JF this is a kludge */
2654 install_operand ('s', opP->reg - ADDR);
2655 tmpreg = get_num (&opP->disp, 80);
2656 if (!issword (tmpreg))
2658 as_warn (_("Expression out of range, using 0"));
2665 install_operand (s[1], opP->reg - DATA);
2668 case 'E': /* Ignore it */
2672 install_operand (s[1], opP->reg - FP0);
2675 case 'G': /* Ignore it */
2680 tmpreg = opP->reg - COP0;
2681 install_operand (s[1], tmpreg);
2684 case 'J': /* JF foo */
2757 install_operand (s[1], tmpreg);
2761 tmpreg = get_num (&opP->disp, 55);
2762 install_operand (s[1], tmpreg & 0x7f);
2769 if (tmpreg & 0x7FF0000)
2770 as_bad (_("Floating point register in register list"));
2771 insop (reverse_16_bits (tmpreg), opcode);
2775 if (tmpreg & 0x700FFFF)
2776 as_bad (_("Wrong register in floating-point reglist"));
2777 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2785 if (tmpreg & 0x7FF0000)
2786 as_bad (_("Floating point register in register list"));
2787 insop (tmpreg, opcode);
2789 else if (s[1] == '8')
2791 if (tmpreg & 0x0FFFFFF)
2792 as_bad (_("incorrect register in reglist"));
2793 install_operand (s[1], tmpreg >> 24);
2797 if (tmpreg & 0x700FFFF)
2798 as_bad (_("wrong register in floating-point reglist"));
2800 install_operand (s[1], tmpreg >> 16);
2805 install_operand (s[1], get_num (&opP->disp, 60));
2809 tmpreg = ((opP->mode == DREG)
2810 ? 0x20 + (int) (opP->reg - DATA)
2811 : (get_num (&opP->disp, 40) & 0x1F));
2812 install_operand (s[1], tmpreg);
2816 tmpreg = get_num (&opP->disp, 10);
2819 install_operand (s[1], tmpreg);
2823 /* This depends on the fact that ADDR registers are eight
2824 more than their corresponding DATA regs, so the result
2825 will have the ADDR_REG bit set */
2826 install_operand (s[1], opP->reg - DATA);
2830 if (opP->mode == AINDR)
2831 install_operand (s[1], opP->reg - DATA);
2833 install_operand (s[1], opP->index.reg - DATA);
2837 if (opP->reg == FPI)
2839 else if (opP->reg == FPS)
2841 else if (opP->reg == FPC)
2845 install_operand (s[1], tmpreg);
2848 case 'S': /* Ignore it */
2852 install_operand (s[1], get_num (&opP->disp, 30));
2855 case 'U': /* Ignore it */
2874 as_fatal (_("failed sanity check"));
2875 } /* switch on cache token */
2876 install_operand (s[1], tmpreg);
2879 /* JF: These are out of order, I fear. */
2892 install_operand (s[1], tmpreg);
2918 install_operand (s[1], tmpreg);
2922 if (opP->reg == VAL)
2941 install_operand (s[1], tmpreg);
2955 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2966 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2972 install_operand (s[1], tmpreg);
2975 know (opP->reg == PSR);
2978 know (opP->reg == PCSR);
2993 install_operand (s[1], tmpreg);
2996 tmpreg = get_num (&opP->disp, 20);
2997 install_operand (s[1], tmpreg);
2999 case '_': /* used only for move16 absolute 32-bit address */
3000 if (isvar (&opP->disp))
3001 add_fix ('l', &opP->disp, 0, 0);
3002 tmpreg = get_num (&opP->disp, 80);
3003 addword (tmpreg >> 16);
3004 addword (tmpreg & 0xFFFF);
3007 install_operand (s[1], opP->reg - DATA0L);
3008 opP->reg -= (DATA0L);
3009 opP->reg &= 0x0F; /* remove upper/lower bit */
3016 /* By the time whe get here (FINALLY) the_ins contains the complete
3017 instruction, ready to be emitted. . . */
3021 reverse_16_bits (in)
3027 static int mask[16] =
3029 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3030 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3032 for (n = 0; n < 16; n++)
3035 out |= mask[15 - n];
3038 } /* reverse_16_bits() */
3047 static int mask[8] =
3049 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3052 for (n = 0; n < 8; n++)
3058 } /* reverse_8_bits() */
3060 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3061 (that value is chosen in the frag_var call in md_assemble). TYPE
3062 is the subtype of the frag to be generated; its primary type is
3063 rs_machine_dependent.
3065 The TYPE parameter is also used by md_convert_frag_1 and
3066 md_estimate_size_before_relax. The appropriate type of fixup will
3067 be emitted by md_convert_frag_1.
3069 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3071 install_operand (mode, val)
3078 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3081 the_ins.opcode[0] |= val << 9;
3084 the_ins.opcode[1] |= val << 12;
3087 the_ins.opcode[1] |= val << 6;
3090 the_ins.opcode[1] |= val;
3093 the_ins.opcode[2] |= val << 12;
3096 the_ins.opcode[2] |= val << 6;
3099 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3100 three words long! */
3102 the_ins.opcode[2] |= val;
3105 the_ins.opcode[1] |= val << 7;
3108 the_ins.opcode[1] |= val << 10;
3112 the_ins.opcode[1] |= val << 5;
3117 the_ins.opcode[1] |= (val << 10) | (val << 7);
3120 the_ins.opcode[1] |= (val << 12) | val;
3123 the_ins.opcode[0] |= val = 0xff;
3126 the_ins.opcode[0] |= val << 9;
3129 the_ins.opcode[1] |= val;
3132 the_ins.opcode[1] |= val;
3133 the_ins.numo++; /* What a hack */
3136 the_ins.opcode[1] |= val << 4;
3144 the_ins.opcode[0] |= (val << 6);
3147 the_ins.opcode[1] = (val >> 16);
3148 the_ins.opcode[2] = val & 0xffff;
3151 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3152 the_ins.opcode[0] |= ((val & 0x7) << 9);
3153 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3156 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3157 the_ins.opcode[0] |= ((val & 0x7) << 9);
3160 the_ins.opcode[1] |= val << 12;
3161 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3164 the_ins.opcode[0] |= (val & 0xF);
3165 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3168 the_ins.opcode[1] |= (val & 0xF);
3169 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3172 the_ins.opcode[1] |= ((val != 1) << 10);
3176 as_fatal (_("failed sanity check."));
3178 } /* install_operand() */
3181 install_gen_operand (mode, val)
3188 the_ins.opcode[0] |= val;
3191 /* This is a kludge!!! */
3192 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3201 the_ins.opcode[0] |= val;
3203 /* more stuff goes here */
3205 as_fatal (_("failed sanity check."));
3207 } /* install_gen_operand() */
3210 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3211 * then deal with the bitfield hack.
3215 crack_operand (str, opP)
3217 register struct m68k_op *opP;
3219 register int parens;
3221 register char *beg_str;
3229 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3235 else if (*str == ')')
3239 opP->error = _("Extra )");
3245 if (flag_mri && *str == '\'')
3246 inquote = ! inquote;
3248 if (!*str && parens)
3250 opP->error = _("Missing )");
3255 if (m68k_ip_op (beg_str, opP) != 0)
3262 c = *++str; /* JF bitfield hack */
3267 as_bad (_("Missing operand"));
3270 /* Detect MRI REG symbols and convert them to REGLSTs. */
3271 if (opP->mode == CONTROL && (int)opP->reg < 0)
3274 opP->mask = ~(int)opP->reg;
3281 /* This is the guts of the machine-dependent assembler. STR points to a
3282 machine dependent instruction. This function is supposed to emit
3283 the frags/bytes it assembles to.
3287 insert_reg (regname, regnum)
3288 const char *regname;
3294 #ifdef REGISTER_PREFIX
3295 if (!flag_reg_prefix_optional)
3297 buf[0] = REGISTER_PREFIX;
3298 strcpy (buf + 1, regname);
3303 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3304 &zero_address_frag));
3306 for (i = 0; regname[i]; i++)
3307 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3310 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3311 &zero_address_frag));
3320 static const struct init_entry init_table[] =
3379 /* control registers */
3380 { "sfc", SFC }, /* Source Function Code */
3382 { "dfc", DFC }, /* Destination Function Code */
3384 { "cacr", CACR }, /* Cache Control Register */
3385 { "caar", CAAR }, /* Cache Address Register */
3387 { "usp", USP }, /* User Stack Pointer */
3388 { "vbr", VBR }, /* Vector Base Register */
3389 { "msp", MSP }, /* Master Stack Pointer */
3390 { "isp", ISP }, /* Interrupt Stack Pointer */
3392 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3393 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3394 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3395 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3397 /* 68ec040 versions of same */
3398 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3399 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3400 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3401 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3403 /* mcf5200 versions of same. The ColdFire programmer's reference
3404 manual indicated that the order is 2,3,0,1, but Ken Rose
3405 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3406 { "acr0", ITT0 }, /* Access Control Unit 0 */
3407 { "acr1", ITT1 }, /* Access Control Unit 1 */
3408 { "acr2", DTT0 }, /* Access Control Unit 2 */
3409 { "acr3", DTT1 }, /* Access Control Unit 3 */
3411 { "tc", TC }, /* MMU Translation Control Register */
3414 { "mmusr", MMUSR }, /* MMU Status Register */
3415 { "srp", SRP }, /* User Root Pointer */
3416 { "urp", URP }, /* Supervisor Root Pointer */
3421 { "rombar", ROMBAR }, /* ROM Base Address Register */
3422 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3423 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3424 { "mbar", MBAR }, /* Module Base Address Register */
3425 /* end of control registers */
3459 /* 68ec030 versions of same */
3462 /* 68ec030 access control unit, identical to 030 MMU status reg */
3465 /* Suppressed data and address registers. */
3483 /* Upper and lower data and address registers, used by macw and msacw. */
3527 for (i = 0; init_table[i].name; i++)
3528 insert_reg (init_table[i].name, init_table[i].number);
3531 static int no_68851, no_68881;
3534 /* a.out machine type. Default to 68020. */
3535 int m68k_aout_machtype = 2;
3547 int shorts_this_frag;
3550 /* In MRI mode, the instruction and operands are separated by a
3551 space. Anything following the operands is a comment. The label
3552 has already been removed. */
3560 for (s = str; *s != '\0'; s++)
3562 if ((*s == ' ' || *s == '\t') && ! inquote)
3580 inquote = ! inquote;
3585 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3590 for (n = 0; n < the_ins.numargs; n++)
3591 if (the_ins.operands[n].error)
3593 er = the_ins.operands[n].error;
3599 as_bad (_("%s -- statement `%s' ignored"), er, str);
3603 /* If there is a current label, record that it marks an instruction. */
3604 if (current_label != NULL)
3606 current_label->text = 1;
3607 current_label = NULL;
3610 if (the_ins.nfrag == 0)
3612 /* No frag hacking involved; just put it out */
3613 toP = frag_more (2 * the_ins.numo);
3614 fromP = &the_ins.opcode[0];
3615 for (m = the_ins.numo; m; --m)
3617 md_number_to_chars (toP, (long) (*fromP), 2);
3621 /* put out symbol-dependent info */
3622 for (m = 0; m < the_ins.nrel; m++)
3624 switch (the_ins.reloc[m].wid)
3643 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3644 the_ins.reloc[m].wid);
3647 fixP = fix_new_exp (frag_now,
3648 ((toP - frag_now->fr_literal)
3649 - the_ins.numo * 2 + the_ins.reloc[m].n),
3651 &the_ins.reloc[m].exp,
3652 the_ins.reloc[m].pcrel,
3653 get_reloc_code (n, the_ins.reloc[m].pcrel,
3654 the_ins.reloc[m].pic_reloc));
3655 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3656 if (the_ins.reloc[m].wid == 'B')
3657 fixP->fx_signed = 1;
3662 /* There's some frag hacking */
3663 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3668 wid = 2 * the_ins.fragb[n].fragoff;
3670 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3671 toP = frag_more (wid);
3673 shorts_this_frag = 0;
3674 for (m = wid / 2; m; --m)
3676 md_number_to_chars (toP, (long) (*fromP), 2);
3681 for (m = 0; m < the_ins.nrel; m++)
3683 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3685 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3688 wid = the_ins.reloc[m].wid;
3691 the_ins.reloc[m].wid = 0;
3692 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3694 fixP = fix_new_exp (frag_now,
3695 ((toP - frag_now->fr_literal)
3696 - the_ins.numo * 2 + the_ins.reloc[m].n),
3698 &the_ins.reloc[m].exp,
3699 the_ins.reloc[m].pcrel,
3700 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3701 the_ins.reloc[m].pic_reloc));
3702 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3704 (void) frag_var (rs_machine_dependent, 10, 0,
3705 (relax_substateT) (the_ins.fragb[n].fragty),
3706 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3708 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3709 shorts_this_frag = 0;
3712 toP = frag_more (n * sizeof (short));
3715 md_number_to_chars (toP, (long) (*fromP), 2);
3721 for (m = 0; m < the_ins.nrel; m++)
3725 wid = the_ins.reloc[m].wid;
3728 the_ins.reloc[m].wid = 0;
3729 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3731 fixP = fix_new_exp (frag_now,
3732 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3733 - shorts_this_frag * 2),
3735 &the_ins.reloc[m].exp,
3736 the_ins.reloc[m].pcrel,
3737 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3738 the_ins.reloc[m].pic_reloc));
3739 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3747 * md_begin -- set up hash tables with 68000 instructions.
3748 * similar to what the vax assembler does. ---phr
3750 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3751 a copy of it at runtime, adding in the information we want but isn't
3752 there. I think it'd be better to have an awk script hack the table
3753 at compile time. Or even just xstr the table and use it as-is. But
3754 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3757 register const struct m68k_opcode *ins;
3758 register struct m68k_incant *hack, *slak;
3759 register const char *retval = 0; /* empty string, or error msg text */
3765 flag_reg_prefix_optional = 1;
3767 if (! m68k_rel32_from_cmdline)
3771 op_hash = hash_new ();
3773 obstack_begin (&robyn, 4000);
3774 for (i = 0; i < m68k_numopcodes; i++)
3776 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3779 ins = &m68k_opcodes[i];
3780 /* We *could* ignore insns that don't match our arch here
3781 but just leaving them out of the hash. */
3782 slak->m_operands = ins->args;
3783 slak->m_opnum = strlen (slak->m_operands) / 2;
3784 slak->m_arch = ins->arch;
3785 slak->m_opcode = ins->opcode;
3786 /* This is kludgey */
3787 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3788 if (i + 1 != m68k_numopcodes
3789 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3791 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3796 slak = slak->m_next;
3800 retval = hash_insert (op_hash, ins->name, (char *) hack);
3802 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3805 for (i = 0; i < m68k_numaliases; i++)
3807 const char *name = m68k_opcode_aliases[i].primary;
3808 const char *alias = m68k_opcode_aliases[i].alias;
3809 PTR val = hash_find (op_hash, name);
3811 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3812 retval = hash_insert (op_hash, alias, val);
3814 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3817 /* In MRI mode, all unsized branches are variable sized. Normally,
3818 they are word sized. */
3821 static struct m68k_opcode_alias mri_aliases[] =
3842 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3845 const char *name = mri_aliases[i].primary;
3846 const char *alias = mri_aliases[i].alias;
3847 PTR val = hash_find (op_hash, name);
3849 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3850 retval = hash_jam (op_hash, alias, val);
3852 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3856 for (i = 0; i < (int) sizeof (mklower_table); i++)
3857 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3859 for (i = 0; i < (int) sizeof (notend_table); i++)
3861 notend_table[i] = 0;
3862 alt_notend_table[i] = 0;
3864 notend_table[','] = 1;
3865 notend_table['{'] = 1;
3866 notend_table['}'] = 1;
3867 alt_notend_table['a'] = 1;
3868 alt_notend_table['A'] = 1;
3869 alt_notend_table['d'] = 1;
3870 alt_notend_table['D'] = 1;
3871 alt_notend_table['#'] = 1;
3872 alt_notend_table['&'] = 1;
3873 alt_notend_table['f'] = 1;
3874 alt_notend_table['F'] = 1;
3875 #ifdef REGISTER_PREFIX
3876 alt_notend_table[REGISTER_PREFIX] = 1;
3879 /* We need to put '(' in alt_notend_table to handle
3880 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3882 alt_notend_table['('] = 1;
3884 /* We need to put '@' in alt_notend_table to handle
3885 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3887 alt_notend_table['@'] = 1;
3889 /* We need to put digits in alt_notend_table to handle
3890 bfextu %d0{24:1},%d0
3892 alt_notend_table['0'] = 1;
3893 alt_notend_table['1'] = 1;
3894 alt_notend_table['2'] = 1;
3895 alt_notend_table['3'] = 1;
3896 alt_notend_table['4'] = 1;
3897 alt_notend_table['5'] = 1;
3898 alt_notend_table['6'] = 1;
3899 alt_notend_table['7'] = 1;
3900 alt_notend_table['8'] = 1;
3901 alt_notend_table['9'] = 1;
3903 #ifndef MIT_SYNTAX_ONLY
3904 /* Insert pseudo ops, these have to go into the opcode table since
3905 gas expects pseudo ops to start with a dot */
3908 while (mote_pseudo_table[n].poc_name)
3910 hack = (struct m68k_incant *)
3911 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3912 hash_insert (op_hash,
3913 mote_pseudo_table[n].poc_name, (char *) hack);
3914 hack->m_operands = 0;
3924 record_alignment (text_section, 2);
3925 record_alignment (data_section, 2);
3926 record_alignment (bss_section, 2);
3931 select_control_regs ()
3933 /* Note which set of "movec" control registers is available. */
3934 switch (cpu_of_arch (current_architecture))
3937 control_regs = m68000_control_regs;
3940 control_regs = m68010_control_regs;
3944 control_regs = m68020_control_regs;
3947 control_regs = m68040_control_regs;
3950 control_regs = m68060_control_regs;
3953 control_regs = cpu32_control_regs;
3958 control_regs = mcf_control_regs;
3966 m68k_init_after_args ()
3968 if (cpu_of_arch (current_architecture) == 0)
3971 const char *default_cpu = TARGET_CPU;
3973 if (*default_cpu == 'm')
3975 for (i = 0; i < n_archs; i++)
3976 if (strcasecmp (default_cpu, archs[i].name) == 0)
3980 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3981 current_architecture |= m68020;
3984 current_architecture |= archs[i].arch;
3986 /* Permit m68881 specification with all cpus; those that can't work
3987 with a coprocessor could be doing emulation. */
3988 if (current_architecture & m68851)
3990 if (current_architecture & m68040)
3992 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3995 /* What other incompatibilities could we check for? */
3997 /* Toss in some default assumptions about coprocessors. */
3999 && (cpu_of_arch (current_architecture)
4000 /* Can CPU32 have a 68881 coprocessor?? */
4001 & (m68020 | m68030 | cpu32)))
4003 current_architecture |= m68881;
4006 && (cpu_of_arch (current_architecture) & m68020up) != 0
4007 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4009 current_architecture |= m68851;
4011 if (no_68881 && (current_architecture & m68881))
4012 as_bad (_("options for 68881 and no-68881 both given"));
4013 if (no_68851 && (current_architecture & m68851))
4014 as_bad (_("options for 68851 and no-68851 both given"));
4017 /* Work out the magic number. This isn't very general. */
4018 if (current_architecture & m68000)
4019 m68k_aout_machtype = 0;
4020 else if (current_architecture & m68010)
4021 m68k_aout_machtype = 1;
4022 else if (current_architecture & m68020)
4023 m68k_aout_machtype = 2;
4025 m68k_aout_machtype = 2;
4028 /* Note which set of "movec" control registers is available. */
4029 select_control_regs ();
4031 if (cpu_of_arch (current_architecture) < m68020
4032 || arch_coldfire_p (current_architecture))
4033 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4036 /* This is called when a label is defined. */
4039 m68k_frob_label (sym)
4042 struct label_line *n;
4044 n = (struct label_line *) xmalloc (sizeof *n);
4047 as_where (&n->file, &n->line);
4053 /* This is called when a value that is not an instruction is emitted. */
4056 m68k_flush_pending_output ()
4058 current_label = NULL;
4061 /* This is called at the end of the assembly, when the final value of
4062 the label is known. We warn if this is a text symbol aligned at an
4066 m68k_frob_symbol (sym)
4069 if (S_GET_SEGMENT (sym) == reg_section
4070 && (int) S_GET_VALUE (sym) < 0)
4072 S_SET_SEGMENT (sym, absolute_section);
4073 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4075 else if ((S_GET_VALUE (sym) & 1) != 0)
4077 struct label_line *l;
4079 for (l = labels; l != NULL; l = l->next)
4081 if (l->label == sym)
4084 as_warn_where (l->file, l->line,
4085 _("text label `%s' aligned to odd boundary"),
4093 /* This is called if we go in or out of MRI mode because of the .mri
4097 m68k_mri_mode_change (on)
4102 if (! flag_reg_prefix_optional)
4104 flag_reg_prefix_optional = 1;
4105 #ifdef REGISTER_PREFIX
4110 if (! m68k_rel32_from_cmdline)
4115 if (! reg_prefix_optional_seen)
4117 #ifdef REGISTER_PREFIX_OPTIONAL
4118 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4120 flag_reg_prefix_optional = 0;
4122 #ifdef REGISTER_PREFIX
4127 if (! m68k_rel32_from_cmdline)
4132 /* Equal to MAX_PRECISION in atof-ieee.c */
4133 #define MAX_LITTLENUMS 6
4135 /* Turn a string in input_line_pointer into a floating point constant
4136 of type TYPE, and store the appropriate bytes in *LITP. The number
4137 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4138 returned, or NULL on OK. */
4141 md_atof (type, litP, sizeP)
4147 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4148 LITTLENUM_TYPE *wordP;
4179 return _("Bad call to MD_ATOF()");
4181 t = atof_ieee (input_line_pointer, type, words);
4183 input_line_pointer = t;
4185 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4186 for (wordP = words; prec--;)
4188 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4189 litP += sizeof (LITTLENUM_TYPE);
4195 md_number_to_chars (buf, val, n)
4200 number_to_chars_bigendian (buf, val, n);
4204 md_apply_fix_2 (fixP, val)
4208 addressT upper_limit;
4209 offsetT lower_limit;
4211 /* This is unnecessary but it convinces the native rs6000 compiler
4212 to generate the code we want. */
4213 char *buf = fixP->fx_frag->fr_literal;
4214 buf += fixP->fx_where;
4215 /* end ibm compiler workaround */
4217 if (val & 0x80000000)
4218 val |= ~(addressT)0x7fffffff;
4225 memset (buf, 0, fixP->fx_size);
4226 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4228 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4229 && !S_IS_DEFINED (fixP->fx_addsy)
4230 && !S_IS_WEAK (fixP->fx_addsy))
4231 S_SET_WEAK (fixP->fx_addsy);
4236 #ifdef BFD_ASSEMBLER
4237 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4238 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4242 switch (fixP->fx_size)
4244 /* The cast to offsetT below are necessary to make code correct for
4245 machines where ints are smaller than offsetT */
4249 lower_limit = - (offsetT) 0x80;
4252 *buf++ = (val >> 8);
4254 upper_limit = 0x7fff;
4255 lower_limit = - (offsetT) 0x8000;
4258 *buf++ = (val >> 24);
4259 *buf++ = (val >> 16);
4260 *buf++ = (val >> 8);
4262 upper_limit = 0x7fffffff;
4263 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4266 BAD_CASE (fixP->fx_size);
4269 /* Fix up a negative reloc. */
4270 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4272 fixP->fx_addsy = fixP->fx_subsy;
4273 fixP->fx_subsy = NULL;
4277 /* For non-pc-relative values, it's conceivable we might get something
4278 like "0xff" for a byte field. So extend the upper part of the range
4279 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4280 so that we can do any range checking at all. */
4281 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4282 upper_limit = upper_limit * 2 + 1;
4284 if ((addressT) val > upper_limit
4285 && (val > 0 || val < lower_limit))
4286 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4288 /* A one byte PC-relative reloc means a short branch. We can't use
4289 a short branch with a value of 0 or -1, because those indicate
4290 different opcodes (branches with longer offsets). fixup_segment
4291 in write.c may have clobbered fx_pcrel, so we need to examine the
4294 #ifdef BFD_ASSEMBLER
4295 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4298 && fixP->fx_size == 1
4299 && (fixP->fx_addsy == NULL
4300 || S_IS_DEFINED (fixP->fx_addsy))
4301 && (val == 0 || val == -1))
4302 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4305 #ifdef BFD_ASSEMBLER
4307 md_apply_fix (fixP, valp)
4311 md_apply_fix_2 (fixP, (addressT) *valp);
4315 void md_apply_fix (fixP, val)
4319 md_apply_fix_2 (fixP, (addressT) val);
4323 /* *fragP has been relaxed to its final size, and now needs to have
4324 the bytes inside it modified to conform to the new size There is UGLY
4328 md_convert_frag_1 (fragP)
4329 register fragS *fragP;
4334 /* Address in object code of the displacement. */
4335 register int object_address = fragP->fr_fix + fragP->fr_address;
4337 /* Address in gas core of the place to store the displacement. */
4338 /* This convinces the native rs6000 compiler to generate the code we
4340 register char *buffer_address = fragP->fr_literal;
4341 buffer_address += fragP->fr_fix;
4342 /* end ibm compiler workaround */
4344 /* The displacement of the address, from current location. */
4345 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4346 disp = (disp + fragP->fr_offset) - object_address;
4348 #ifdef BFD_ASSEMBLER
4349 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
4352 switch (fragP->fr_subtype)
4354 case TAB (BRANCHBWL, BYTE):
4355 case TAB (BRABSJUNC, BYTE):
4356 case TAB (BRABSJCOND, BYTE):
4357 case TAB (BRANCHBW, BYTE):
4358 know (issbyte (disp));
4360 as_bad (_("short branch with zero offset: use :w"));
4361 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4362 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4363 fixP->fx_pcrel_adjust = -1;
4365 case TAB (BRANCHBWL, SHORT):
4366 case TAB (BRABSJUNC, SHORT):
4367 case TAB (BRABSJCOND, SHORT):
4368 case TAB (BRANCHBW, SHORT):
4369 fragP->fr_opcode[1] = 0x00;
4370 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4371 1, RELAX_RELOC_PC16);
4374 case TAB (BRANCHBWL, LONG):
4375 fragP->fr_opcode[1] = (char) 0xFF;
4376 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4377 1, RELAX_RELOC_PC32);
4380 case TAB (BRABSJUNC, LONG):
4381 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4383 fragP->fr_opcode[0] = 0x4E;
4384 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4385 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4386 0, RELAX_RELOC_ABS32);
4389 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4391 fragP->fr_opcode[0] = 0x4E;
4392 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4393 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4394 0, RELAX_RELOC_ABS32);
4399 /* This cannot happen, because jbsr and jbra are the only two
4400 unconditional branches. */
4404 case TAB (BRABSJCOND, LONG):
4405 /* Only Bcc 68000 instructions can come here. */
4406 /* Change bcc into b!cc/jmp absl long. */
4408 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4409 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4411 /* JF: these used to be fr_opcode[2,3], but they may be in a
4412 different frag, in which case refering to them is a no-no.
4413 Only fr_opcode[0,1] are guaranteed to work. */
4414 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4415 *buffer_address++ = (char) 0xf9;
4416 fragP->fr_fix += 2; /* account for jmp instruction */
4417 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4418 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4421 case TAB (FBRANCH, SHORT):
4422 know ((fragP->fr_opcode[1] & 0x40) == 0);
4423 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4424 1, RELAX_RELOC_PC16);
4427 case TAB (FBRANCH, LONG):
4428 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4429 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4430 1, RELAX_RELOC_PC32);
4433 case TAB (DBCCLBR, SHORT):
4434 case TAB (DBCCABSJ, SHORT):
4435 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4436 1, RELAX_RELOC_PC16);
4439 case TAB (DBCCLBR, LONG):
4440 /* only DBcc instructions can come here */
4441 /* Change dbcc into dbcc/bral. */
4443 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4444 *buffer_address++ = 0x00; /* branch offset = 4 */
4445 *buffer_address++ = 0x04;
4446 *buffer_address++ = 0x60; /* put in bra pc+6 */
4447 *buffer_address++ = 0x06;
4448 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4449 *buffer_address++ = (char) 0xff;
4451 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4452 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4456 case TAB (DBCCABSJ, LONG):
4457 /* only DBcc instructions can come here */
4458 /* Change dbcc into dbcc/jmp. */
4460 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4461 *buffer_address++ = 0x00; /* branch offset = 4 */
4462 *buffer_address++ = 0x04;
4463 *buffer_address++ = 0x60; /* put in bra pc+6 */
4464 *buffer_address++ = 0x06;
4465 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4466 *buffer_address++ = (char) 0xf9;
4468 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4469 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4473 case TAB (PCREL1632, SHORT):
4474 fragP->fr_opcode[1] &= ~0x3F;
4475 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4476 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4477 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4480 case TAB (PCREL1632, LONG):
4481 /* Already set to mode 7.3; this indicates: PC indirect with
4482 suppressed index, 32-bit displacement. */
4483 *buffer_address++ = 0x01;
4484 *buffer_address++ = 0x70;
4486 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4487 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4488 fixP->fx_pcrel_adjust = 2;
4491 case TAB (PCINDEX, BYTE):
4492 assert (fragP->fr_fix >= 2);
4493 buffer_address[-2] &= ~1;
4494 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4495 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4496 fixP->fx_pcrel_adjust = 1;
4498 case TAB (PCINDEX, SHORT):
4499 assert (fragP->fr_fix >= 2);
4500 buffer_address[-2] |= 0x1;
4501 buffer_address[-1] = 0x20;
4502 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4503 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4504 fixP->fx_pcrel_adjust = 2;
4507 case TAB (PCINDEX, LONG):
4508 assert (fragP->fr_fix >= 2);
4509 buffer_address[-2] |= 0x1;
4510 buffer_address[-1] = 0x30;
4511 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4512 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4513 fixP->fx_pcrel_adjust = 2;
4516 case TAB (ABSTOPCREL, SHORT):
4517 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4518 1, RELAX_RELOC_PC16);
4521 case TAB (ABSTOPCREL, LONG):
4522 /* The thing to do here is force it to ABSOLUTE LONG, since
4523 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4524 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4526 fragP->fr_opcode[1] &= ~0x3F;
4527 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4528 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4529 0, RELAX_RELOC_ABS32);
4535 #ifndef BFD_ASSEMBLER
4538 md_convert_frag (headers, sec, fragP)
4539 object_headers *headers ATTRIBUTE_UNUSED;
4540 segT sec ATTRIBUTE_UNUSED;
4543 md_convert_frag_1 (fragP);
4549 md_convert_frag (abfd, sec, fragP)
4550 bfd *abfd ATTRIBUTE_UNUSED;
4551 segT sec ATTRIBUTE_UNUSED;
4554 md_convert_frag_1 (fragP);
4558 /* Force truly undefined symbols to their maximum size, and generally set up
4559 the frag list to be relaxed
4562 md_estimate_size_before_relax (fragP, segment)
4563 register fragS *fragP;
4567 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4569 old_fix = fragP->fr_fix;
4571 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4572 switch (fragP->fr_subtype)
4574 case TAB (BRANCHBWL, SZ_UNDEF):
4575 case TAB (BRABSJUNC, SZ_UNDEF):
4577 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4578 && relaxable_symbol (fragP->fr_symbol))
4580 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4582 else if (flag_short_refs)
4584 /* Symbol is undefined and we want short ref. */
4585 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4590 /* Symbol is still undefined. Make it LONG. */
4591 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4597 case TAB (BRABSJCOND, SZ_UNDEF):
4599 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4600 && relaxable_symbol (fragP->fr_symbol))
4602 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4604 else if (flag_short_refs)
4606 /* Symbol is undefined and we want short ref. */
4607 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4612 /* Symbol is still undefined. Make it LONG. */
4613 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4619 case TAB (BRANCHBW, SZ_UNDEF):
4621 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4622 && relaxable_symbol (fragP->fr_symbol))
4624 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4628 /* Symbol is undefined and we don't have long branches. */
4629 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4635 case TAB (FBRANCH, SZ_UNDEF):
4637 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4638 && relaxable_symbol (fragP->fr_symbol))
4641 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4646 fragP->fr_subtype = TAB (FBRANCH, LONG);
4652 case TAB (DBCCLBR, SZ_UNDEF):
4653 case TAB (DBCCABSJ, SZ_UNDEF):
4655 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4656 && relaxable_symbol (fragP->fr_symbol)
4659 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4664 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4665 fragP->fr_var += 10;
4670 case TAB (PCREL1632, SZ_UNDEF):
4672 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4673 && relaxable_symbol (fragP->fr_symbol))
4676 fragP->fr_subtype = TAB (PCREL1632, SHORT);
4681 fragP->fr_subtype = TAB (PCREL1632, LONG);
4687 case TAB (PCINDEX, SZ_UNDEF):
4688 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4689 && relaxable_symbol (fragP->fr_symbol)))
4691 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4695 fragP->fr_subtype = TAB (PCINDEX, LONG);
4700 case TAB (ABSTOPCREL, SZ_UNDEF):
4702 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4703 && relaxable_symbol (fragP->fr_symbol)))
4705 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4710 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4720 /* Now that SZ_UNDEF are taken care of, check others. */
4721 switch (fragP->fr_subtype)
4723 case TAB (BRANCHBWL, BYTE):
4724 case TAB (BRABSJUNC, BYTE):
4725 case TAB (BRABSJCOND, BYTE):
4726 case TAB (BRANCHBW, BYTE):
4727 /* We can't do a short jump to the next instruction, so in that
4728 case we force word mode. At this point S_GET_VALUE should
4729 return the offset of the symbol within its frag. If the
4730 symbol is at the start of a frag, and it is the next frag
4731 with any data in it (usually this is just the next frag, but
4732 assembler listings may introduce empty frags), we must use
4734 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4739 stop = symbol_get_frag (fragP->fr_symbol);
4740 for (l = fragP->fr_next; l != stop; l = l->fr_next)
4741 if (l->fr_fix + l->fr_var != 0)
4745 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4753 return fragP->fr_var + fragP->fr_fix - old_fix;
4756 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4757 /* the bit-field entries in the relocation_info struct plays hell
4758 with the byte-order problems of cross-assembly. So as a hack,
4759 I added this mach. dependent ri twiddler. Ugly, but it gets
4761 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4762 are symbolnum, most sig. byte first. Last byte is broken up with
4763 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4764 nibble as nuthin. (on Sun 3 at least) */
4765 /* Translate the internal relocation information into target-specific
4769 md_ri_to_chars (the_bytes, ri)
4771 struct reloc_info_generic *ri;
4774 md_number_to_chars (the_bytes, ri->r_address, 4);
4775 /* now the fun stuff */
4776 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4777 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4778 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4779 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4780 ((ri->r_extern << 4) & 0x10));
4783 #endif /* comment */
4785 #ifndef BFD_ASSEMBLER
4787 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4790 relax_addressT segment_address_in_file;
4793 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4794 * Out: GNU LD relocation length code: 0, 1, or 2.
4797 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4800 know (fixP->fx_addsy != NULL);
4802 md_number_to_chars (where,
4803 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4806 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4807 ? S_GET_TYPE (fixP->fx_addsy)
4808 : fixP->fx_addsy->sy_number);
4810 where[4] = (r_symbolnum >> 16) & 0x0ff;
4811 where[5] = (r_symbolnum >> 8) & 0x0ff;
4812 where[6] = r_symbolnum & 0x0ff;
4813 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4814 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4818 #endif /* OBJ_AOUT or OBJ_BOUT */
4820 #ifndef WORKING_DOT_WORD
4821 CONST int md_short_jump_size = 4;
4822 CONST int md_long_jump_size = 6;
4825 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4827 addressT from_addr, to_addr;
4828 fragS *frag ATTRIBUTE_UNUSED;
4829 symbolS *to_symbol ATTRIBUTE_UNUSED;
4833 offset = to_addr - (from_addr + 2);
4835 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4836 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4840 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4842 addressT from_addr, to_addr;
4848 if (!HAVE_LONG_BRANCH(current_architecture))
4850 offset = to_addr - S_GET_VALUE (to_symbol);
4851 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4852 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4853 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4858 offset = to_addr - (from_addr + 2);
4859 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4860 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4866 /* Different values of OK tell what its OK to return. Things that
4867 aren't OK are an error (what a shock, no?)
4870 10: Absolute 1:8 only
4871 20: Absolute 0:7 only
4872 30: absolute 0:15 only
4873 40: Absolute 0:31 only
4874 50: absolute 0:127 only
4875 55: absolute -64:63 only
4876 60: absolute -128:127 only
4877 70: absolute 0:4095 only
4884 struct m68k_exp *exp;
4887 if (exp->exp.X_op == O_absent)
4889 /* Do the same thing the VAX asm does */
4890 op (exp) = O_constant;
4896 as_warn (_("expression out of range: defaulting to 1"));
4900 else if (exp->exp.X_op == O_constant)
4905 if (offs (exp) < 1 || offs (exp) > 8)
4907 as_warn (_("expression out of range: defaulting to 1"));
4912 if (offs (exp) < 0 || offs (exp) > 7)
4916 if (offs (exp) < 0 || offs (exp) > 15)
4920 if (offs (exp) < 0 || offs (exp) > 32)
4924 if (offs (exp) < 0 || offs (exp) > 127)
4928 if (offs (exp) < -64 || offs (exp) > 63)
4932 if (offs (exp) < -128 || offs (exp) > 127)
4936 if (offs (exp) < 0 || offs (exp) > 4095)
4939 as_warn (_("expression out of range: defaulting to 0"));
4947 else if (exp->exp.X_op == O_big)
4949 if (offs (exp) <= 0 /* flonum */
4950 && (ok == 80 /* no bignums */
4951 || (ok > 10 /* small-int ranges including 0 ok */
4952 /* If we have a flonum zero, a zero integer should
4953 do as well (e.g., in moveq). */
4954 && generic_floating_point_number.exponent == 0
4955 && generic_floating_point_number.low[0] == 0)))
4957 /* HACK! Turn it into a long */
4958 LITTLENUM_TYPE words[6];
4960 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4961 op (exp) = O_constant;
4964 offs (exp) = words[1] | (words[0] << 16);
4968 op (exp) = O_constant;
4971 offs (exp) = (ok == 10) ? 1 : 0;
4972 as_warn (_("Can't deal with expression; defaulting to %ld"),
4978 if (ok >= 10 && ok <= 70)
4980 op (exp) = O_constant;
4983 offs (exp) = (ok == 10) ? 1 : 0;
4984 as_warn (_("Can't deal with expression; defaulting to %ld"),
4989 if (exp->size != SIZE_UNSPEC)
4997 if (!isbyte (offs (exp)))
4998 as_warn (_("expression doesn't fit in BYTE"));
5001 if (!isword (offs (exp)))
5002 as_warn (_("expression doesn't fit in WORD"));
5010 /* These are the back-ends for the various machine dependent pseudo-ops. */
5014 int ignore ATTRIBUTE_UNUSED;
5016 subseg_set (data_section, 1);
5017 demand_empty_rest_of_line ();
5022 int ignore ATTRIBUTE_UNUSED;
5024 subseg_set (data_section, 2);
5025 demand_empty_rest_of_line ();
5030 int ignore ATTRIBUTE_UNUSED;
5032 /* We don't support putting frags in the BSS segment, we fake it
5033 by marking in_bss, then looking at s_skip for clues. */
5035 subseg_set (bss_section, 0);
5036 demand_empty_rest_of_line ();
5041 int ignore ATTRIBUTE_UNUSED;
5044 register long temp_fill;
5046 temp = 1; /* JF should be 2? */
5047 temp_fill = get_absolute_expression ();
5048 if (!need_pass_2) /* Never make frag if expect extra pass. */
5049 frag_align (temp, (int) temp_fill, 0);
5050 demand_empty_rest_of_line ();
5051 record_alignment (now_seg, temp);
5056 int ignore ATTRIBUTE_UNUSED;
5058 demand_empty_rest_of_line ();
5061 /* Pseudo-ops handled for MRI compatibility. */
5063 /* This function returns non-zero if the argument is a conditional
5064 pseudo-op. This is called when checking whether a pending
5065 alignment is needed. */
5068 m68k_conditional_pseudoop (pop)
5071 return (pop->poc_handler == s_mri_if
5072 || pop->poc_handler == s_mri_else);
5075 /* Handle an MRI style chip specification. */
5084 s = input_line_pointer;
5085 /* We can't use get_symbol_end since the processor names are not proper
5087 while (is_part_of_name (c = *input_line_pointer++))
5089 *--input_line_pointer = 0;
5090 for (i = 0; i < n_archs; i++)
5091 if (strcasecmp (s, archs[i].name) == 0)
5095 as_bad (_("%s: unrecognized processor name"), s);
5096 *input_line_pointer = c;
5097 ignore_rest_of_line ();
5100 *input_line_pointer = c;
5102 if (*input_line_pointer == '/')
5103 current_architecture = 0;
5105 current_architecture &= m68881 | m68851;
5106 current_architecture |= archs[i].arch;
5108 while (*input_line_pointer == '/')
5110 ++input_line_pointer;
5111 s = input_line_pointer;
5112 /* We can't use get_symbol_end since the processor names are not
5114 while (is_part_of_name (c = *input_line_pointer++))
5116 *--input_line_pointer = 0;
5117 if (strcmp (s, "68881") == 0)
5118 current_architecture |= m68881;
5119 else if (strcmp (s, "68851") == 0)
5120 current_architecture |= m68851;
5121 *input_line_pointer = c;
5124 /* Update info about available control registers. */
5125 select_control_regs ();
5128 /* The MRI CHIP pseudo-op. */
5132 int ignore ATTRIBUTE_UNUSED;
5138 stop = mri_comment_field (&stopc);
5141 mri_comment_end (stop, stopc);
5142 demand_empty_rest_of_line ();
5145 /* The MRI FOPT pseudo-op. */
5149 int ignore ATTRIBUTE_UNUSED;
5153 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5157 input_line_pointer += 3;
5158 temp = get_absolute_expression ();
5159 if (temp < 0 || temp > 7)
5160 as_bad (_("bad coprocessor id"));
5162 m68k_float_copnum = COP0 + temp;
5166 as_bad (_("unrecognized fopt option"));
5167 ignore_rest_of_line ();
5171 demand_empty_rest_of_line ();
5174 /* The structure used to handle the MRI OPT pseudo-op. */
5178 /* The name of the option. */
5181 /* If this is not NULL, just call this function. The first argument
5182 is the ARG field of this structure, the second argument is
5183 whether the option was negated. */
5184 void (*pfn) PARAMS ((int arg, int on));
5186 /* If this is not NULL, and the PFN field is NULL, set the variable
5187 this points to. Set it to the ARG field if the option was not
5188 negated, and the NOTARG field otherwise. */
5191 /* The value to pass to PFN or to assign to *PVAR. */
5194 /* The value to assign to *PVAR if the option is negated. If PFN is
5195 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5196 the option may not be negated. */
5200 /* The table used to handle the MRI OPT pseudo-op. */
5202 static void skip_to_comma PARAMS ((int, int));
5203 static void opt_nest PARAMS ((int, int));
5204 static void opt_chip PARAMS ((int, int));
5205 static void opt_list PARAMS ((int, int));
5206 static void opt_list_symbols PARAMS ((int, int));
5208 static const struct opt_action opt_table[] =
5210 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5212 /* We do relaxing, so there is little use for these options. */
5213 { "b", 0, 0, 0, 0 },
5214 { "brs", 0, 0, 0, 0 },
5215 { "brb", 0, 0, 0, 0 },
5216 { "brl", 0, 0, 0, 0 },
5217 { "brw", 0, 0, 0, 0 },
5219 { "c", 0, 0, 0, 0 },
5220 { "cex", 0, 0, 0, 0 },
5221 { "case", 0, &symbols_case_sensitive, 1, 0 },
5222 { "cl", 0, 0, 0, 0 },
5223 { "cre", 0, 0, 0, 0 },
5224 { "d", 0, &flag_keep_locals, 1, 0 },
5225 { "e", 0, 0, 0, 0 },
5226 { "f", 0, &flag_short_refs, 1, 0 },
5227 { "frs", 0, &flag_short_refs, 1, 0 },
5228 { "frl", 0, &flag_short_refs, 0, 1 },
5229 { "g", 0, 0, 0, 0 },
5230 { "i", 0, 0, 0, 0 },
5231 { "m", 0, 0, 0, 0 },
5232 { "mex", 0, 0, 0, 0 },
5233 { "mc", 0, 0, 0, 0 },
5234 { "md", 0, 0, 0, 0 },
5235 { "nest", opt_nest, 0, 0, 0 },
5236 { "next", skip_to_comma, 0, 0, 0 },
5237 { "o", 0, 0, 0, 0 },
5238 { "old", 0, 0, 0, 0 },
5239 { "op", skip_to_comma, 0, 0, 0 },
5240 { "pco", 0, 0, 0, 0 },
5241 { "p", opt_chip, 0, 0, 0 },
5242 { "pcr", 0, 0, 0, 0 },
5243 { "pcs", 0, 0, 0, 0 },
5244 { "r", 0, 0, 0, 0 },
5245 { "quick", 0, &m68k_quick, 1, 0 },
5246 { "rel32", 0, &m68k_rel32, 1, 0 },
5247 { "s", opt_list, 0, 0, 0 },
5248 { "t", opt_list_symbols, 0, 0, 0 },
5249 { "w", 0, &flag_no_warnings, 0, 1 },
5253 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5255 /* The MRI OPT pseudo-op. */
5259 int ignore ATTRIBUTE_UNUSED;
5267 const struct opt_action *o;
5272 if (*input_line_pointer == '-')
5274 ++input_line_pointer;
5277 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5279 input_line_pointer += 2;
5283 s = input_line_pointer;
5284 c = get_symbol_end ();
5286 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5288 if (strcasecmp (s, o->name) == 0)
5292 /* Restore input_line_pointer now in case the option
5294 *input_line_pointer = c;
5295 (*o->pfn) (o->arg, t);
5297 else if (o->pvar != NULL)
5299 if (! t && o->arg == o->notarg)
5300 as_bad (_("option `%s' may not be negated"), s);
5301 *input_line_pointer = c;
5302 *o->pvar = t ? o->arg : o->notarg;
5305 *input_line_pointer = c;
5311 as_bad (_("option `%s' not recognized"), s);
5312 *input_line_pointer = c;
5315 while (*input_line_pointer++ == ',');
5317 /* Move back to terminating character. */
5318 --input_line_pointer;
5319 demand_empty_rest_of_line ();
5322 /* Skip ahead to a comma. This is used for OPT options which we do
5323 not suppor tand which take arguments. */
5326 skip_to_comma (arg, on)
5327 int arg ATTRIBUTE_UNUSED;
5328 int on ATTRIBUTE_UNUSED;
5330 while (*input_line_pointer != ','
5331 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5332 ++input_line_pointer;
5335 /* Handle the OPT NEST=depth option. */
5339 int arg ATTRIBUTE_UNUSED;
5340 int on ATTRIBUTE_UNUSED;
5342 if (*input_line_pointer != '=')
5344 as_bad (_("bad format of OPT NEST=depth"));
5348 ++input_line_pointer;
5349 max_macro_nest = get_absolute_expression ();
5352 /* Handle the OPT P=chip option. */
5356 int arg ATTRIBUTE_UNUSED;
5357 int on ATTRIBUTE_UNUSED;
5359 if (*input_line_pointer != '=')
5361 /* This is just OPT P, which we do not support. */
5365 ++input_line_pointer;
5369 /* Handle the OPT S option. */
5373 int arg ATTRIBUTE_UNUSED;
5379 /* Handle the OPT T option. */
5382 opt_list_symbols (arg, on)
5383 int arg ATTRIBUTE_UNUSED;
5387 listing |= LISTING_SYMBOLS;
5389 listing &=~ LISTING_SYMBOLS;
5392 /* Handle the MRI REG pseudo-op. */
5396 int ignore ATTRIBUTE_UNUSED;
5405 if (line_label == NULL)
5407 as_bad (_("missing label"));
5408 ignore_rest_of_line ();
5413 stop = mri_comment_field (&stopc);
5417 s = input_line_pointer;
5418 while (isalnum ((unsigned char) *input_line_pointer)
5419 #ifdef REGISTER_PREFIX
5420 || *input_line_pointer == REGISTER_PREFIX
5422 || *input_line_pointer == '/'
5423 || *input_line_pointer == '-')
5424 ++input_line_pointer;
5425 c = *input_line_pointer;
5426 *input_line_pointer = '\0';
5428 if (m68k_ip_op (s, &rop) != 0)
5430 if (rop.error == NULL)
5431 as_bad (_("bad register list"));
5433 as_bad (_("bad register list: %s"), rop.error);
5434 *input_line_pointer = c;
5435 ignore_rest_of_line ();
5439 *input_line_pointer = c;
5441 if (rop.mode == REGLST)
5443 else if (rop.mode == DREG)
5444 mask = 1 << (rop.reg - DATA0);
5445 else if (rop.mode == AREG)
5446 mask = 1 << (rop.reg - ADDR0 + 8);
5447 else if (rop.mode == FPREG)
5448 mask = 1 << (rop.reg - FP0 + 16);
5449 else if (rop.mode == CONTROL
5452 else if (rop.mode == CONTROL
5455 else if (rop.mode == CONTROL
5460 as_bad (_("bad register list"));
5461 ignore_rest_of_line ();
5465 S_SET_SEGMENT (line_label, reg_section);
5466 S_SET_VALUE (line_label, ~mask);
5467 symbol_set_frag (line_label, &zero_address_frag);
5470 mri_comment_end (stop, stopc);
5472 demand_empty_rest_of_line ();
5475 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5479 struct save_opts *next;
5481 int symbols_case_sensitive;
5489 /* FIXME: We don't save OPT S. */
5492 /* This variable holds the stack of saved options. */
5494 static struct save_opts *save_stack;
5496 /* The MRI SAVE pseudo-op. */
5500 int ignore ATTRIBUTE_UNUSED;
5502 struct save_opts *s;
5504 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5505 s->abspcadd = m68k_abspcadd;
5506 s->symbols_case_sensitive = symbols_case_sensitive;
5507 s->keep_locals = flag_keep_locals;
5508 s->short_refs = flag_short_refs;
5509 s->architecture = current_architecture;
5510 s->quick = m68k_quick;
5511 s->rel32 = m68k_rel32;
5512 s->listing = listing;
5513 s->no_warnings = flag_no_warnings;
5515 s->next = save_stack;
5518 demand_empty_rest_of_line ();
5521 /* The MRI RESTORE pseudo-op. */
5525 int ignore ATTRIBUTE_UNUSED;
5527 struct save_opts *s;
5529 if (save_stack == NULL)
5531 as_bad (_("restore without save"));
5532 ignore_rest_of_line ();
5537 save_stack = s->next;
5539 m68k_abspcadd = s->abspcadd;
5540 symbols_case_sensitive = s->symbols_case_sensitive;
5541 flag_keep_locals = s->keep_locals;
5542 flag_short_refs = s->short_refs;
5543 current_architecture = s->architecture;
5544 m68k_quick = s->quick;
5545 m68k_rel32 = s->rel32;
5546 listing = s->listing;
5547 flag_no_warnings = s->no_warnings;
5551 demand_empty_rest_of_line ();
5554 /* Types of MRI structured control directives. */
5556 enum mri_control_type
5564 /* This structure is used to stack the MRI structured control
5567 struct mri_control_info
5569 /* The directive within which this one is enclosed. */
5570 struct mri_control_info *outer;
5572 /* The type of directive. */
5573 enum mri_control_type type;
5575 /* Whether an ELSE has been in an IF. */
5578 /* The add or sub statement at the end of a FOR. */
5581 /* The label of the top of a FOR or REPEAT loop. */
5584 /* The label to jump to for the next iteration, or the else
5585 expression of a conditional. */
5588 /* The label to jump to to break out of the loop, or the label past
5589 the end of a conditional. */
5593 /* The stack of MRI structured control directives. */
5595 static struct mri_control_info *mri_control_stack;
5597 /* The current MRI structured control directive index number, used to
5598 generate label names. */
5600 static int mri_control_index;
5602 /* Some function prototypes. */
5604 static void mri_assemble PARAMS ((char *));
5605 static char *mri_control_label PARAMS ((void));
5606 static struct mri_control_info *push_mri_control
5607 PARAMS ((enum mri_control_type));
5608 static void pop_mri_control PARAMS ((void));
5609 static int parse_mri_condition PARAMS ((int *));
5610 static int parse_mri_control_operand
5611 PARAMS ((int *, char **, char **, char **, char **));
5612 static int swap_mri_condition PARAMS ((int));
5613 static int reverse_mri_condition PARAMS ((int));
5614 static void build_mri_control_operand
5615 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5616 const char *, int));
5617 static void parse_mri_control_expression
5618 PARAMS ((char *, int, const char *, const char *, int));
5620 /* Assemble an instruction for an MRI structured control directive. */
5628 /* md_assemble expects the opcode to be in lower case. */
5629 for (s = str; *s != ' ' && *s != '\0'; s++)
5631 if (isupper ((unsigned char) *s))
5632 *s = tolower ((unsigned char) *s);
5638 /* Generate a new MRI label structured control directive label name. */
5641 mri_control_label ()
5645 n = (char *) xmalloc (20);
5646 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5647 ++mri_control_index;
5651 /* Create a new MRI structured control directive. */
5653 static struct mri_control_info *
5654 push_mri_control (type)
5655 enum mri_control_type type;
5657 struct mri_control_info *n;
5659 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5663 if (type == mri_if || type == mri_while)
5666 n->top = mri_control_label ();
5667 n->next = mri_control_label ();
5668 n->bottom = mri_control_label ();
5670 n->outer = mri_control_stack;
5671 mri_control_stack = n;
5676 /* Pop off the stack of MRI structured control directives. */
5681 struct mri_control_info *n;
5683 n = mri_control_stack;
5684 mri_control_stack = n->outer;
5692 /* Recognize a condition code in an MRI structured control expression. */
5695 parse_mri_condition (pcc)
5700 know (*input_line_pointer == '<');
5702 ++input_line_pointer;
5703 c1 = *input_line_pointer++;
5704 c2 = *input_line_pointer++;
5706 if (*input_line_pointer != '>')
5708 as_bad (_("syntax error in structured control directive"));
5712 ++input_line_pointer;
5720 *pcc = (c1 << 8) | c2;
5725 /* Parse a single operand in an MRI structured control expression. */
5728 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5745 if (*input_line_pointer == '<')
5747 /* It's just a condition code. */
5748 return parse_mri_condition (pcc);
5751 /* Look ahead for the condition code. */
5752 for (s = input_line_pointer; *s != '\0'; ++s)
5754 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5759 as_bad (_("missing condition code in structured control directive"));
5763 *leftstart = input_line_pointer;
5765 if (*leftstop > *leftstart
5766 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5769 input_line_pointer = s;
5770 if (! parse_mri_condition (pcc))
5773 /* Look ahead for AND or OR or end of line. */
5774 for (s = input_line_pointer; *s != '\0'; ++s)
5776 if ((strncasecmp (s, "AND", 3) == 0
5777 && (s[3] == '.' || ! is_part_of_name (s[3])))
5778 || (strncasecmp (s, "OR", 2) == 0
5779 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5783 *rightstart = input_line_pointer;
5785 if (*rightstop > *rightstart
5786 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5789 input_line_pointer = s;
5794 #define MCC(b1, b2) (((b1) << 8) | (b2))
5796 /* Swap the sense of a condition. This changes the condition so that
5797 it generates the same result when the operands are swapped. */
5800 swap_mri_condition (cc)
5805 case MCC ('h', 'i'): return MCC ('c', 's');
5806 case MCC ('l', 's'): return MCC ('c', 'c');
5807 case MCC ('c', 'c'): return MCC ('l', 's');
5808 case MCC ('c', 's'): return MCC ('h', 'i');
5809 case MCC ('p', 'l'): return MCC ('m', 'i');
5810 case MCC ('m', 'i'): return MCC ('p', 'l');
5811 case MCC ('g', 'e'): return MCC ('l', 'e');
5812 case MCC ('l', 't'): return MCC ('g', 't');
5813 case MCC ('g', 't'): return MCC ('l', 't');
5814 case MCC ('l', 'e'): return MCC ('g', 'e');
5819 /* Reverse the sense of a condition. */
5822 reverse_mri_condition (cc)
5827 case MCC ('h', 'i'): return MCC ('l', 's');
5828 case MCC ('l', 's'): return MCC ('h', 'i');
5829 case MCC ('c', 'c'): return MCC ('c', 's');
5830 case MCC ('c', 's'): return MCC ('c', 'c');
5831 case MCC ('n', 'e'): return MCC ('e', 'q');
5832 case MCC ('e', 'q'): return MCC ('n', 'e');
5833 case MCC ('v', 'c'): return MCC ('v', 's');
5834 case MCC ('v', 's'): return MCC ('v', 'c');
5835 case MCC ('p', 'l'): return MCC ('m', 'i');
5836 case MCC ('m', 'i'): return MCC ('p', 'l');
5837 case MCC ('g', 'e'): return MCC ('l', 't');
5838 case MCC ('l', 't'): return MCC ('g', 'e');
5839 case MCC ('g', 't'): return MCC ('l', 'e');
5840 case MCC ('l', 'e'): return MCC ('g', 't');
5845 /* Build an MRI structured control expression. This generates test
5846 and branch instructions. It goes to TRUELAB if the condition is
5847 true, and to FALSELAB if the condition is false. Exactly one of
5848 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5849 is the size qualifier for the expression. EXTENT is the size to
5850 use for the branch. */
5853 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5854 rightstop, truelab, falselab, extent)
5861 const char *truelab;
5862 const char *falselab;
5868 if (leftstart != NULL)
5870 struct m68k_op leftop, rightop;
5873 /* Swap the compare operands, if necessary, to produce a legal
5874 m68k compare instruction. Comparing a register operand with
5875 a non-register operand requires the register to be on the
5876 right (cmp, cmpa). Comparing an immediate value with
5877 anything requires the immediate value to be on the left
5882 (void) m68k_ip_op (leftstart, &leftop);
5887 (void) m68k_ip_op (rightstart, &rightop);
5890 if (rightop.mode == IMMED
5891 || ((leftop.mode == DREG || leftop.mode == AREG)
5892 && (rightop.mode != DREG && rightop.mode != AREG)))
5896 cc = swap_mri_condition (cc);
5898 leftstart = rightstart;
5901 leftstop = rightstop;
5906 if (truelab == NULL)
5908 cc = reverse_mri_condition (cc);
5912 if (leftstart != NULL)
5914 buf = (char *) xmalloc (20
5915 + (leftstop - leftstart)
5916 + (rightstop - rightstart));
5924 memcpy (s, leftstart, leftstop - leftstart);
5925 s += leftstop - leftstart;
5927 memcpy (s, rightstart, rightstop - rightstart);
5928 s += rightstop - rightstart;
5934 buf = (char *) xmalloc (20 + strlen (truelab));
5942 strcpy (s, truelab);
5947 /* Parse an MRI structured control expression. This generates test
5948 and branch instructions. STOP is where the expression ends. It
5949 goes to TRUELAB if the condition is true, and to FALSELAB if the
5950 condition is false. Exactly one of TRUELAB and FALSELAB will be
5951 NULL, meaning to fall through. QUAL is the size qualifier for the
5952 expression. EXTENT is the size to use for the branch. */
5955 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5958 const char *truelab;
5959 const char *falselab;
5972 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5973 &rightstart, &rightstop))
5979 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5983 if (falselab != NULL)
5986 flab = mri_control_label ();
5988 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5989 rightstop, (const char *) NULL, flab, extent);
5991 input_line_pointer += 3;
5992 if (*input_line_pointer != '.'
5993 || input_line_pointer[1] == '\0')
5997 qual = input_line_pointer[1];
5998 input_line_pointer += 2;
6001 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6002 &rightstart, &rightstop))
6008 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6009 rightstop, truelab, falselab, extent);
6011 if (falselab == NULL)
6014 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6018 if (truelab != NULL)
6021 tlab = mri_control_label ();
6023 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6024 rightstop, tlab, (const char *) NULL, extent);
6026 input_line_pointer += 2;
6027 if (*input_line_pointer != '.'
6028 || input_line_pointer[1] == '\0')
6032 qual = input_line_pointer[1];
6033 input_line_pointer += 2;
6036 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6037 &rightstart, &rightstop))
6043 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6044 rightstop, truelab, falselab, extent);
6046 if (truelab == NULL)
6051 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6052 rightstop, truelab, falselab, extent);
6056 if (input_line_pointer != stop)
6057 as_bad (_("syntax error in structured control directive"));
6060 /* Handle the MRI IF pseudo-op. This may be a structured control
6061 directive, or it may be a regular assembler conditional, depending
6070 struct mri_control_info *n;
6072 /* A structured control directive must end with THEN with an
6073 optional qualifier. */
6074 s = input_line_pointer;
6075 while (! is_end_of_line[(unsigned char) *s]
6076 && (! flag_mri || *s != '*'))
6079 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6082 if (s - input_line_pointer > 1
6086 if (s - input_line_pointer < 3
6087 || strncasecmp (s - 3, "THEN", 4) != 0)
6091 as_bad (_("missing then"));
6092 ignore_rest_of_line ();
6096 /* It's a conditional. */
6101 /* Since this might be a conditional if, this pseudo-op will be
6102 called even if we are supported to be ignoring input. Double
6103 check now. Clobber *input_line_pointer so that ignore_input
6104 thinks that this is not a special pseudo-op. */
6105 c = *input_line_pointer;
6106 *input_line_pointer = 0;
6107 if (ignore_input ())
6109 *input_line_pointer = c;
6110 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6111 ++input_line_pointer;
6112 demand_empty_rest_of_line ();
6115 *input_line_pointer = c;
6117 n = push_mri_control (mri_if);
6119 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6120 n->next, s[1] == '.' ? s[2] : '\0');
6123 input_line_pointer = s + 3;
6125 input_line_pointer = s + 1;
6129 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6130 ++input_line_pointer;
6133 demand_empty_rest_of_line ();
6136 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6137 structured IF, associate the ELSE with the IF. Otherwise, assume
6138 it is a conditional else. */
6149 && (mri_control_stack == NULL
6150 || mri_control_stack->type != mri_if
6151 || mri_control_stack->else_seen))
6157 c = *input_line_pointer;
6158 *input_line_pointer = 0;
6159 if (ignore_input ())
6161 *input_line_pointer = c;
6162 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6163 ++input_line_pointer;
6164 demand_empty_rest_of_line ();
6167 *input_line_pointer = c;
6169 if (mri_control_stack == NULL
6170 || mri_control_stack->type != mri_if
6171 || mri_control_stack->else_seen)
6173 as_bad (_("else without matching if"));
6174 ignore_rest_of_line ();
6178 mri_control_stack->else_seen = 1;
6180 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6183 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6187 colon (mri_control_stack->next);
6191 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6192 ++input_line_pointer;
6195 demand_empty_rest_of_line ();
6198 /* Handle the MRI ENDI pseudo-op. */
6202 int ignore ATTRIBUTE_UNUSED;
6204 if (mri_control_stack == NULL
6205 || mri_control_stack->type != mri_if)
6207 as_bad (_("endi without matching if"));
6208 ignore_rest_of_line ();
6212 /* ignore_input will not return true for ENDI, so we don't need to
6213 worry about checking it again here. */
6215 if (! mri_control_stack->else_seen)
6216 colon (mri_control_stack->next);
6217 colon (mri_control_stack->bottom);
6223 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6224 ++input_line_pointer;
6227 demand_empty_rest_of_line ();
6230 /* Handle the MRI BREAK pseudo-op. */
6233 s_mri_break (extent)
6236 struct mri_control_info *n;
6240 n = mri_control_stack;
6242 && n->type != mri_for
6243 && n->type != mri_repeat
6244 && n->type != mri_while)
6248 as_bad (_("break outside of structured loop"));
6249 ignore_rest_of_line ();
6253 buf = (char *) xmalloc (20 + strlen (n->bottom));
6256 sprintf (buf, "bra%s %s", ex, n->bottom);
6262 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6263 ++input_line_pointer;
6266 demand_empty_rest_of_line ();
6269 /* Handle the MRI NEXT pseudo-op. */
6275 struct mri_control_info *n;
6279 n = mri_control_stack;
6281 && n->type != mri_for
6282 && n->type != mri_repeat
6283 && n->type != mri_while)
6287 as_bad (_("next outside of structured loop"));
6288 ignore_rest_of_line ();
6292 buf = (char *) xmalloc (20 + strlen (n->next));
6295 sprintf (buf, "bra%s %s", ex, n->next);
6301 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6302 ++input_line_pointer;
6305 demand_empty_rest_of_line ();
6308 /* Handle the MRI FOR pseudo-op. */
6314 const char *varstart, *varstop;
6315 const char *initstart, *initstop;
6316 const char *endstart, *endstop;
6317 const char *bystart, *bystop;
6321 struct mri_control_info *n;
6327 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6331 varstart = input_line_pointer;
6333 /* Look for the '='. */
6334 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6335 && *input_line_pointer != '=')
6336 ++input_line_pointer;
6337 if (*input_line_pointer != '=')
6339 as_bad (_("missing ="));
6340 ignore_rest_of_line ();
6344 varstop = input_line_pointer;
6345 if (varstop > varstart
6346 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6349 ++input_line_pointer;
6351 initstart = input_line_pointer;
6353 /* Look for TO or DOWNTO. */
6356 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6358 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6359 && ! is_part_of_name (input_line_pointer[2]))
6361 initstop = input_line_pointer;
6362 input_line_pointer += 2;
6365 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6366 && ! is_part_of_name (input_line_pointer[6]))
6368 initstop = input_line_pointer;
6370 input_line_pointer += 6;
6373 ++input_line_pointer;
6375 if (initstop == NULL)
6377 as_bad (_("missing to or downto"));
6378 ignore_rest_of_line ();
6381 if (initstop > initstart
6382 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6386 endstart = input_line_pointer;
6388 /* Look for BY or DO. */
6391 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6393 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6394 && ! is_part_of_name (input_line_pointer[2]))
6396 endstop = input_line_pointer;
6398 input_line_pointer += 2;
6401 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6402 && (input_line_pointer[2] == '.'
6403 || ! is_part_of_name (input_line_pointer[2])))
6405 endstop = input_line_pointer;
6406 input_line_pointer += 2;
6409 ++input_line_pointer;
6411 if (endstop == NULL)
6413 as_bad (_("missing do"));
6414 ignore_rest_of_line ();
6417 if (endstop > endstart
6418 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6424 bystop = bystart + 2;
6429 bystart = input_line_pointer;
6433 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6435 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6436 && (input_line_pointer[2] == '.'
6437 || ! is_part_of_name (input_line_pointer[2])))
6439 bystop = input_line_pointer;
6440 input_line_pointer += 2;
6443 ++input_line_pointer;
6447 as_bad (_("missing do"));
6448 ignore_rest_of_line ();
6451 if (bystop > bystart
6452 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6456 if (*input_line_pointer != '.')
6460 extent = input_line_pointer[1];
6461 input_line_pointer += 2;
6464 /* We have fully parsed the FOR operands. Now build the loop. */
6466 n = push_mri_control (mri_for);
6468 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6479 memcpy (s, initstart, initstop - initstart);
6480 s += initstop - initstart;
6482 memcpy (s, varstart, varstop - varstart);
6483 s += varstop - varstart;
6497 memcpy (s, endstart, endstop - endstart);
6498 s += endstop - endstart;
6500 memcpy (s, varstart, varstop - varstart);
6501 s += varstop - varstart;
6509 sprintf (buf, "blt%s %s", ex, n->bottom);
6511 sprintf (buf, "bgt%s %s", ex, n->bottom);
6514 /* Put together the add or sub instruction used by ENDF. */
6524 memcpy (s, bystart, bystop - bystart);
6525 s += bystop - bystart;
6527 memcpy (s, varstart, varstop - varstart);
6528 s += varstop - varstart;
6534 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6535 ++input_line_pointer;
6538 demand_empty_rest_of_line ();
6541 /* Handle the MRI ENDF pseudo-op. */
6545 int ignore ATTRIBUTE_UNUSED;
6547 if (mri_control_stack == NULL
6548 || mri_control_stack->type != mri_for)
6550 as_bad (_("endf without for"));
6551 ignore_rest_of_line ();
6555 colon (mri_control_stack->next);
6557 mri_assemble (mri_control_stack->incr);
6559 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6560 mri_assemble (mri_control_stack->incr);
6562 free (mri_control_stack->incr);
6564 colon (mri_control_stack->bottom);
6570 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6571 ++input_line_pointer;
6574 demand_empty_rest_of_line ();
6577 /* Handle the MRI REPEAT pseudo-op. */
6580 s_mri_repeat (ignore)
6581 int ignore ATTRIBUTE_UNUSED;
6583 struct mri_control_info *n;
6585 n = push_mri_control (mri_repeat);
6589 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6590 ++input_line_pointer;
6592 demand_empty_rest_of_line ();
6595 /* Handle the MRI UNTIL pseudo-op. */
6603 if (mri_control_stack == NULL
6604 || mri_control_stack->type != mri_repeat)
6606 as_bad (_("until without repeat"));
6607 ignore_rest_of_line ();
6611 colon (mri_control_stack->next);
6613 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6616 parse_mri_control_expression (s, qual, (const char *) NULL,
6617 mri_control_stack->top, '\0');
6619 colon (mri_control_stack->bottom);
6621 input_line_pointer = s;
6627 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6628 ++input_line_pointer;
6631 demand_empty_rest_of_line ();
6634 /* Handle the MRI WHILE pseudo-op. */
6642 struct mri_control_info *n;
6644 s = input_line_pointer;
6645 while (! is_end_of_line[(unsigned char) *s]
6646 && (! flag_mri || *s != '*'))
6649 while (*s == ' ' || *s == '\t')
6651 if (s - input_line_pointer > 1
6654 if (s - input_line_pointer < 2
6655 || strncasecmp (s - 1, "DO", 2) != 0)
6657 as_bad (_("missing do"));
6658 ignore_rest_of_line ();
6662 n = push_mri_control (mri_while);
6666 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6667 s[1] == '.' ? s[2] : '\0');
6669 input_line_pointer = s + 1;
6670 if (*input_line_pointer == '.')
6671 input_line_pointer += 2;
6675 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6676 ++input_line_pointer;
6679 demand_empty_rest_of_line ();
6682 /* Handle the MRI ENDW pseudo-op. */
6686 int ignore ATTRIBUTE_UNUSED;
6690 if (mri_control_stack == NULL
6691 || mri_control_stack->type != mri_while)
6693 as_bad (_("endw without while"));
6694 ignore_rest_of_line ();
6698 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6699 sprintf (buf, "bra %s", mri_control_stack->next);
6703 colon (mri_control_stack->bottom);
6709 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6710 ++input_line_pointer;
6713 demand_empty_rest_of_line ();
6718 * Invocation line includes a switch not recognized by the base assembler.
6719 * See if it's a processor-specific option. These are:
6721 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6722 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6723 * Select the architecture. Instructions or features not
6724 * supported by the selected architecture cause fatal
6725 * errors. More than one may be specified. The default is
6726 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6727 * for -m68000, and -m68882 is a synonym for -m68881.
6728 * -[A]m[c]no-68851, -[A]m[c]no-68881
6729 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6730 * so don't use or document it, but that's the way the parsing
6733 * -pic Indicates PIC.
6734 * -k Indicates PIC. (Sun 3 only.)
6735 * --pcrel Never turn PC-relative branches into absolute jumps.
6738 * Permit `|' to be used in expressions.
6743 CONST char *md_shortopts = "lSA:m:kQ:V";
6745 CONST char *md_shortopts = "lSA:m:k";
6748 struct option md_longopts[] = {
6749 #define OPTION_PIC (OPTION_MD_BASE)
6750 {"pic", no_argument, NULL, OPTION_PIC},
6751 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6752 {"register-prefix-optional", no_argument, NULL,
6753 OPTION_REGISTER_PREFIX_OPTIONAL},
6754 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6755 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6756 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6757 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6758 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6759 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6760 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6761 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6762 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6763 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6764 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6765 {"pcrel", no_argument, NULL, OPTION_PCREL},
6766 {NULL, no_argument, NULL, 0}
6768 size_t md_longopts_size = sizeof(md_longopts);
6771 md_parse_option (c, arg)
6777 case 'l': /* -l means keep external to 2 bit offset
6778 rather than 16 bit one */
6779 flag_short_refs = 1;
6782 case 'S': /* -S means that jbsr's always turn into
6784 flag_long_jumps = 1;
6787 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6788 branches into absolute jumps. */
6789 flag_keep_pcrel = 1;
6795 /* intentional fall-through */
6798 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6802 const char *oarg = arg;
6808 if (arg[0] == 'c' && arg[1] == '6')
6811 for (i = 0; i < n_archs; i++)
6812 if (!strcmp (arg, archs[i].name))
6817 as_bad (_("unrecognized option `%s'"), oarg);
6820 arch = archs[i].arch;
6823 else if (arch == m68851)
6832 if (arg[0] == 'c' && arg[1] == '6')
6835 for (i = 0; i < n_archs; i++)
6836 if (!strcmp (arg, archs[i].name))
6838 unsigned long arch = archs[i].arch;
6839 if (cpu_of_arch (arch))
6840 /* It's a cpu spec. */
6842 current_architecture &= ~m68000up;
6843 current_architecture |= arch;
6845 else if (arch == m68881)
6847 current_architecture |= m68881;
6850 else if (arch == m68851)
6852 current_architecture |= m68851;
6862 as_bad (_("unrecognized architecture specification `%s'"), arg);
6871 break; /* -pic, Position Independent Code */
6873 case OPTION_REGISTER_PREFIX_OPTIONAL:
6874 flag_reg_prefix_optional = 1;
6875 reg_prefix_optional_seen = 1;
6878 /* -V: SVR4 argument to print version ID. */
6880 print_version_id ();
6883 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6884 should be emitted or not. FIXME: Not implemented. */
6888 case OPTION_BITWISE_OR:
6893 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6895 for (s = m68k_comment_chars; *s != '\0'; s++)
6899 m68k_comment_chars = n;
6903 case OPTION_BASE_SIZE_DEFAULT_16:
6904 m68k_index_width_default = SIZE_WORD;
6907 case OPTION_BASE_SIZE_DEFAULT_32:
6908 m68k_index_width_default = SIZE_LONG;
6911 case OPTION_DISP_SIZE_DEFAULT_16:
6913 m68k_rel32_from_cmdline = 1;
6916 case OPTION_DISP_SIZE_DEFAULT_32:
6918 m68k_rel32_from_cmdline = 1;
6929 md_show_usage (stream)
6932 fprintf(stream, _("\
6934 -l use 1 word for refs to undefined symbols [default 2]\n\
6935 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6936 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6937 | -mcpu32 | -m5200\n\
6938 specify variant of 680X0 architecture [default 68020]\n\
6939 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6940 target has/lacks floating-point coprocessor\n\
6941 [default yes for 68020, 68030, and cpu32]\n"));
6942 fprintf(stream, _("\
6943 -m68851 | -mno-68851\n\
6944 target has/lacks memory-management unit coprocessor\n\
6945 [default yes for 68020 and up]\n\
6946 -pic, -k generate position independent code\n\
6947 -S turn jbsr into jsr\n\
6948 --pcrel never turn PC-relative branches into absolute jumps\n\
6949 --register-prefix-optional\n\
6950 recognize register names without prefix character\n\
6951 --bitwise-or do not treat `|' as a comment character\n"));
6952 fprintf (stream, _("\
6953 --base-size-default-16 base reg without size is 16 bits\n\
6954 --base-size-default-32 base reg without size is 32 bits (default)\n\
6955 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6956 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6961 /* TEST2: Test md_assemble() */
6962 /* Warning, this routine probably doesn't work anymore */
6966 struct m68k_it the_ins;
6974 if (!gets (buf) || !*buf)
6976 if (buf[0] == '|' || buf[1] == '.')
6978 for (cp = buf; *cp; cp++)
6983 memset (&the_ins, '\0', sizeof (the_ins));
6984 m68k_ip (&the_ins, buf);
6987 printf (_("Error %s in %s\n"), the_ins.error, buf);
6991 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6992 for (n = 0; n < the_ins.numo; n++)
6993 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6995 print_the_insn (&the_ins.opcode[0], stdout);
6996 (void) putchar ('\n');
6998 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7000 if (the_ins.operands[n].error)
7002 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7005 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7006 if (the_ins.operands[n].b_const)
7007 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7008 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7009 if (the_ins.operands[n].b_iadd)
7010 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7011 (void) putchar ('\n');
7023 while (*str && *str != ' ')
7025 if (str[-1] == ':' || str[1] == '=')
7032 /* Possible states for relaxation:
7034 0 0 branch offset byte (bra, etc)
7038 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7042 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7049 /* We have no need to default values of symbols. */
7053 md_undefined_symbol (name)
7054 char *name ATTRIBUTE_UNUSED;
7059 /* Round up a section size to the appropriate boundary. */
7061 md_section_align (segment, size)
7062 segT segment ATTRIBUTE_UNUSED;
7066 #ifdef BFD_ASSEMBLER
7067 /* For a.out, force the section size to be aligned. If we don't do
7068 this, BFD will align it for us, but it will not write out the
7069 final bytes of the section. This may be a bug in BFD, but it is
7070 easier to fix it here since that is how the other a.out targets
7074 align = bfd_get_section_alignment (stdoutput, segment);
7075 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7082 /* Exactly what point is a PC-relative offset relative TO?
7083 On the 68k, it is relative to the address of the first extension
7084 word. The difference between the addresses of the offset and the
7085 first extension word is stored in fx_pcrel_adjust. */
7087 md_pcrel_from (fixP)
7092 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
7094 adjust = fixP->fx_pcrel_adjust;
7097 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7100 #ifndef BFD_ASSEMBLER
7105 tc_coff_symbol_emit_hook (ignore)
7106 symbolS *ignore ATTRIBUTE_UNUSED;
7111 tc_coff_sizemachdep (frag)
7114 switch (frag->fr_subtype & 0x3)
7131 void m68k_elf_final_processing()
7133 /* Set file-specific flags if this is a cpu32 processor */
7134 if (cpu_of_arch (current_architecture) & cpu32)
7135 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;