1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "safe-ctype.h"
27 #include "dwarf2dbg.h"
28 #include "dw2gencfi.h"
30 #include "opcode/m68k.h"
31 #include "m68k-parse.h"
37 /* This string holds the chars that always start a comment. If the
38 pre-processor is disabled, these aren't very useful. The macro
39 tc_comment_chars points to this. We use this, rather than the
40 usual comment_chars, so that the --bitwise-or option will work. */
41 #if defined (TE_SVR4) || defined (TE_DELTA)
42 const char *m68k_comment_chars = "|#";
44 const char *m68k_comment_chars = "|";
47 /* This array holds the chars that only start a comment at the beginning of
48 a line. If the line seems to have the form '# 123 filename'
49 .line and .file directives will appear in the pre-processed output */
50 /* Note that input_file.c hand checks for '#' at the beginning of the
51 first line of the input file. This is because the compiler outputs
52 #NO_APP at the beginning of its output. */
53 /* Also note that comments like this one will always work. */
54 const char line_comment_chars[] = "#*";
56 const char line_separator_chars[] = ";";
58 /* Chars that can be used to separate mant from exp in floating point nums. */
59 const char EXP_CHARS[] = "eE";
61 /* Chars that mean this number is a floating point constant, as
62 in "0f12.456" or "0d1.2345e12". */
64 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
66 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here. */
70 const int md_reloc_size = 8; /* Size of relocation record. */
72 /* Are we trying to generate PIC code? If so, absolute references
73 ought to be made into linkage table references or pc-relative
74 references. Not implemented. For ELF there are other means
75 to denote pic relocations. */
78 static int flag_short_refs; /* -l option. */
79 static int flag_long_jumps; /* -S option. */
80 static int flag_keep_pcrel; /* --pcrel option. */
82 #ifdef REGISTER_PREFIX_OPTIONAL
83 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 int flag_reg_prefix_optional;
88 /* Whether --register-prefix-optional was used on the command line. */
89 static int reg_prefix_optional_seen;
91 /* The floating point coprocessor to use by default. */
92 static enum m68k_register m68k_float_copnum = COP1;
94 /* If this is non-zero, then references to number(%pc) will be taken
95 to refer to number, rather than to %pc + number. */
96 static int m68k_abspcadd;
98 /* If this is non-zero, then the quick forms of the move, add, and sub
99 instructions are used when possible. */
100 static int m68k_quick = 1;
102 /* If this is non-zero, then if the size is not specified for a base
103 or outer displacement, the assembler assumes that the size should
105 static int m68k_rel32 = 1;
107 /* This is non-zero if m68k_rel32 was set from the command line. */
108 static int m68k_rel32_from_cmdline;
110 /* The default width to use for an index register when using a base
112 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114 /* We want to warn if any text labels are misaligned. In order to get
115 the right line number, we need to record the line number for each
119 struct label_line *next;
126 /* The list of labels. */
128 static struct label_line *labels;
130 /* The current label. */
132 static struct label_line *current_label;
134 /* Its an arbitrary name: This means I don't approve of it.
136 static struct obstack robyn;
140 const char *m_operands;
141 unsigned long m_opcode;
145 struct m68k_incant *m_next;
148 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
149 #define gettwo(x) (((x)->m_opcode)&0xffff)
151 static const enum m68k_register m68000_control_regs[] = { 0 };
152 static const enum m68k_register m68010_control_regs[] = {
156 static const enum m68k_register m68020_control_regs[] = {
157 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
160 static const enum m68k_register m68040_control_regs[] = {
161 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
162 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
165 static const enum m68k_register m68060_control_regs[] = {
166 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
167 USP, VBR, URP, SRP, PCR,
170 static const enum m68k_register mcf_control_regs[] = {
171 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
172 RAMBAR0, RAMBAR1, MBAR,
175 #define cpu32_control_regs m68010_control_regs
177 static const enum m68k_register *control_regs;
179 /* Internal form of a 68020 instruction. */
183 const char *args; /* List of opcode info. */
186 int numo; /* Number of shorts in opcode. */
189 struct m68k_op operands[6];
191 int nexp; /* Number of exprs in use. */
192 struct m68k_exp exprs[4];
194 int nfrag; /* Number of frags we have to produce. */
197 int fragoff; /* Where in the current opcode the frag ends. */
204 int nrel; /* Num of reloc strucs in use. */
211 /* In a pc relative address the difference between the address
212 of the offset and the address that the offset is relative
213 to. This depends on the addressing mode. Basically this
214 is the value to put in the offset field to address the
215 first byte of the offset, without regarding the special
216 significance of some values (in the branch instruction, for
220 /* Whether this expression needs special pic relocation, and if
222 enum pic_relocation pic_reloc;
225 reloc[5]; /* Five is enough??? */
228 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
229 #define float_of_arch(x) ((x) & mfloat)
230 #define mmu_of_arch(x) ((x) & mmmu)
231 #define arch_coldfire_p(x) (((x) & mcf) != 0)
233 /* Macros for determining if cpu supports a specific addressing mode. */
234 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
236 static struct m68k_it the_ins; /* The instruction being assembled. */
238 #define op(ex) ((ex)->exp.X_op)
239 #define adds(ex) ((ex)->exp.X_add_symbol)
240 #define subs(ex) ((ex)->exp.X_op_symbol)
241 #define offs(ex) ((ex)->exp.X_add_number)
243 /* Macros for adding things to the m68k_it struct. */
244 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
246 /* Static functions. */
247 static void insop PARAMS ((int, const struct m68k_incant *));
248 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
249 static void add_frag PARAMS ((symbolS *, offsetT, int));
251 /* Like addword, but goes BEFORE general operands. */
256 const struct m68k_incant *opcode;
259 for (z = the_ins.numo; z > opcode->m_codenum; --z)
260 the_ins.opcode[z] = the_ins.opcode[z - 1];
261 for (z = 0; z < the_ins.nrel; z++)
262 the_ins.reloc[z].n += 2;
263 for (z = 0; z < the_ins.nfrag; z++)
264 the_ins.fragb[z].fragoff++;
265 the_ins.opcode[opcode->m_codenum] = w;
269 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
272 add_fix (width, exp, pc_rel, pc_fix)
274 struct m68k_exp *exp;
278 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
282 : (the_ins.numo*2)));
283 the_ins.reloc[the_ins.nrel].exp = exp->exp;
284 the_ins.reloc[the_ins.nrel].wid = width;
285 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
287 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
289 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
292 /* Cause an extra frag to be generated here, inserting up to 10 bytes
293 (that value is chosen in the frag_var call in md_assemble). TYPE
294 is the subtype of the frag to be generated; its primary type is
295 rs_machine_dependent.
297 The TYPE parameter is also used by md_convert_frag_1 and
298 md_estimate_size_before_relax. The appropriate type of fixup will
299 be emitted by md_convert_frag_1.
301 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
303 add_frag (add, off, type)
308 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
309 the_ins.fragb[the_ins.nfrag].fadd = add;
310 the_ins.fragb[the_ins.nfrag].foff = off;
311 the_ins.fragb[the_ins.nfrag++].fragty = type;
315 (op (ex) != O_constant && op (ex) != O_big)
317 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
318 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
319 static void m68k_ip PARAMS ((char *));
320 static void insert_reg PARAMS ((const char *, int));
321 static void select_control_regs PARAMS ((void));
322 static void init_regtable PARAMS ((void));
323 static int reverse_16_bits PARAMS ((int in));
324 static int reverse_8_bits PARAMS ((int in));
325 static void install_gen_operand PARAMS ((int mode, int val));
326 static void install_operand PARAMS ((int mode, int val));
327 static void s_bss PARAMS ((int));
328 static void s_data1 PARAMS ((int));
329 static void s_data2 PARAMS ((int));
330 static void s_even PARAMS ((int));
331 static void s_proc PARAMS ((int));
332 static void mri_chip PARAMS ((void));
333 static void s_chip PARAMS ((int));
334 static void s_fopt PARAMS ((int));
335 static void s_opt PARAMS ((int));
336 static void s_reg PARAMS ((int));
337 static void s_restore PARAMS ((int));
338 static void s_save PARAMS ((int));
339 static void s_mri_if PARAMS ((int));
340 static void s_mri_else PARAMS ((int));
341 static void s_mri_endi PARAMS ((int));
342 static void s_mri_break PARAMS ((int));
343 static void s_mri_next PARAMS ((int));
344 static void s_mri_for PARAMS ((int));
345 static void s_mri_endf PARAMS ((int));
346 static void s_mri_repeat PARAMS ((int));
347 static void s_mri_until PARAMS ((int));
348 static void s_mri_while PARAMS ((int));
349 static void s_mri_endw PARAMS ((int));
350 static void md_convert_frag_1 PARAMS ((fragS *));
352 static int current_architecture;
361 static const struct m68k_cpu archs[] =
363 { m68000, "68000", 0 },
364 { m68010, "68010", 0 },
365 { m68020, "68020", 0 },
366 { m68030, "68030", 0 },
367 { m68040, "68040", 0 },
368 { m68060, "68060", 0 },
369 { cpu32, "cpu32", 0 },
370 { m68881, "68881", 0 },
371 { m68851, "68851", 0 },
372 { mcf5200, "5200", 0 },
373 { mcf5206e, "5206e", 0 },
374 { mcf5307, "5307", 0},
375 { mcf5407, "5407", 0},
376 /* Aliases (effectively, so far as gas is concerned) for the above
378 { m68020, "68k", 1 },
379 { m68000, "68008", 1 },
380 { m68000, "68302", 1 },
381 { m68000, "68306", 1 },
382 { m68000, "68307", 1 },
383 { m68000, "68322", 1 },
384 { m68000, "68356", 1 },
385 { m68000, "68ec000", 1 },
386 { m68000, "68hc000", 1 },
387 { m68000, "68hc001", 1 },
388 { m68020, "68ec020", 1 },
389 { m68030, "68ec030", 1 },
390 { m68040, "68ec040", 1 },
391 { m68060, "68ec060", 1 },
392 { cpu32, "68330", 1 },
393 { cpu32, "68331", 1 },
394 { cpu32, "68332", 1 },
395 { cpu32, "68333", 1 },
396 { cpu32, "68334", 1 },
397 { cpu32, "68336", 1 },
398 { cpu32, "68340", 1 },
399 { cpu32, "68341", 1 },
400 { cpu32, "68349", 1 },
401 { cpu32, "68360", 1 },
402 { m68881, "68882", 1 },
403 { mcf5200, "5202", 1 },
404 { mcf5200, "5204", 1 },
405 { mcf5200, "5206", 1 },
408 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
410 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
411 architecture and we have a lot of relaxation modes. */
413 /* Macros used in the relaxation code. */
414 #define TAB(x,y) (((x) << 2) + (y))
415 #define TABTYPE(x) ((x) >> 2)
417 /* Relaxation states. */
423 /* Here are all the relaxation modes we support. First we can relax ordinary
424 branches. On 68020 and higher and on CPU32 all branch instructions take
425 three forms, so on these CPUs all branches always remain as such. When we
426 have to expand to the LONG form on a 68000, though, we substitute an
427 absolute jump instead. This is a direct replacement for unconditional
428 branches and a branch over a jump for conditional branches. However, if the
429 user requires PIC and disables this with --pcrel, we can only relax between
430 BYTE and SHORT forms, punting if that isn't enough. This gives us four
431 different relaxation modes for branches: */
433 #define BRANCHBWL 0 /* Branch byte, word, or long. */
434 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
435 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
436 #define BRANCHBW 3 /* Branch byte or word. */
438 /* We also relax coprocessor branches and DBcc's. All CPUs that support
439 coprocessor branches support them in word and long forms, so we have only
440 one relaxation mode for them. DBcc's are word only on all CPUs. We can
441 relax them to the LONG form with a branch-around sequence. This sequence
442 can use a long branch (if available) or an absolute jump (if acceptable).
443 This gives us two relaxation modes. If long branches are not available and
444 absolute jumps are not acceptable, we don't relax DBcc's. */
446 #define FBRANCH 4 /* Coprocessor branch. */
447 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
448 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
450 /* That's all for instruction relaxation. However, we also relax PC-relative
451 operands. Specifically, we have three operand relaxation modes. On the
452 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
453 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
454 two. Also PC+displacement+index operands in their simple form (with a non-
455 suppressed index without memory indirection) are supported on all CPUs, but
456 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
457 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
458 form of the PC+displacement+index operand. Finally, some absolute operands
459 can be relaxed down to 16-bit PC-relative. */
461 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
462 #define PCINDEX 8 /* PC + displacement + index. */
463 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
465 /* Note that calls to frag_var need to specify the maximum expansion
466 needed; this is currently 10 bytes for DBCC. */
469 How far Forward this mode will reach:
470 How far Backward this mode will reach:
471 How many bytes this mode will add to the size of the frag
472 Which mode to go to if the offset won't fit in this one
474 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
475 relax_typeS md_relax_table[] =
477 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
478 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
482 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
483 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
487 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
488 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
492 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
497 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
498 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
502 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
503 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
507 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
508 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
512 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
513 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
517 { 125, -130, 0, TAB (PCINDEX, SHORT) },
518 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
522 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
523 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
528 /* These are the machine dependent pseudo-ops. These are included so
529 the assembler can work on the output from the SUN C compiler, which
532 /* This table describes all the machine specific pseudo-ops the assembler
533 has to support. The fields are:
534 pseudo-op name without dot
535 function to call to execute this pseudo-op
536 Integer arg to pass to the function. */
537 const pseudo_typeS md_pseudo_table[] =
539 {"data1", s_data1, 0},
540 {"data2", s_data2, 0},
543 {"skip", s_space, 0},
545 #if defined (TE_SUN3) || defined (OBJ_ELF)
546 {"align", s_align_bytes, 0},
549 {"swbeg", s_ignore, 0},
551 {"extend", float_cons, 'x'},
552 {"ldouble", float_cons, 'x'},
554 /* The following pseudo-ops are supported for MRI compatibility. */
556 {"comline", s_space, 1},
558 {"mask2", s_ignore, 0},
561 {"restore", s_restore, 0},
565 {"if.b", s_mri_if, 'b'},
566 {"if.w", s_mri_if, 'w'},
567 {"if.l", s_mri_if, 'l'},
568 {"else", s_mri_else, 0},
569 {"else.s", s_mri_else, 's'},
570 {"else.l", s_mri_else, 'l'},
571 {"endi", s_mri_endi, 0},
572 {"break", s_mri_break, 0},
573 {"break.s", s_mri_break, 's'},
574 {"break.l", s_mri_break, 'l'},
575 {"next", s_mri_next, 0},
576 {"next.s", s_mri_next, 's'},
577 {"next.l", s_mri_next, 'l'},
578 {"for", s_mri_for, 0},
579 {"for.b", s_mri_for, 'b'},
580 {"for.w", s_mri_for, 'w'},
581 {"for.l", s_mri_for, 'l'},
582 {"endf", s_mri_endf, 0},
583 {"repeat", s_mri_repeat, 0},
584 {"until", s_mri_until, 0},
585 {"until.b", s_mri_until, 'b'},
586 {"until.w", s_mri_until, 'w'},
587 {"until.l", s_mri_until, 'l'},
588 {"while", s_mri_while, 0},
589 {"while.b", s_mri_while, 'b'},
590 {"while.w", s_mri_while, 'w'},
591 {"while.l", s_mri_while, 'l'},
592 {"endw", s_mri_endw, 0},
597 /* The mote pseudo ops are put into the opcode table, since they
598 don't start with a . they look like opcodes to gas.
602 extern void obj_coff_section PARAMS ((int));
605 const pseudo_typeS mote_pseudo_table[] =
618 {"xdef", s_globl, 0},
620 {"align", s_align_bytes, 0},
622 {"align", s_align_ptwo, 0},
625 {"sect", obj_coff_section, 0},
626 {"section", obj_coff_section, 0},
631 #define issbyte(x) ((x)>=-128 && (x)<=127)
632 #define isubyte(x) ((x)>=0 && (x)<=255)
633 #define issword(x) ((x)>=-32768 && (x)<=32767)
634 #define isuword(x) ((x)>=0 && (x)<=65535)
636 #define isbyte(x) ((x)>= -255 && (x)<=255)
637 #define isword(x) ((x)>=-65536 && (x)<=65535)
638 #define islong(x) (1)
640 extern char *input_line_pointer;
642 static char notend_table[256];
643 static char alt_notend_table[256];
645 (! (notend_table[(unsigned char) *s] \
647 && alt_notend_table[(unsigned char) s[1]])))
649 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
651 #ifdef NO_PCREL_RELOCS
654 make_pcrel_absolute(fixP, add_number)
658 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
660 /* Rewrite the PC relative instructions to absolute address ones.
661 these are rumoured to be faster, and the apollo linker refuses
662 to deal with the PC relative relocations. */
663 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
666 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
670 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
673 as_fatal(_("Tried to convert PC relative BSR to absolute JSR"));
678 as_fatal (_("Unknown PC relative instruction"));
683 #endif /* NO_PCREL_RELOCS */
686 tc_coff_fix2rtype (fixP)
689 if (fixP->fx_tcbit && fixP->fx_size == 4)
690 return R_RELLONG_NEG;
691 #ifdef NO_PCREL_RELOCS
692 know (fixP->fx_pcrel == 0);
693 return (fixP->fx_size == 1 ? R_RELBYTE
694 : fixP->fx_size == 2 ? R_DIR16
697 return (fixP->fx_pcrel ?
698 (fixP->fx_size == 1 ? R_PCRBYTE :
699 fixP->fx_size == 2 ? R_PCRWORD :
701 (fixP->fx_size == 1 ? R_RELBYTE :
702 fixP->fx_size == 2 ? R_RELWORD :
711 /* Return zero if the reference to SYMBOL from within the same segment may
714 /* On an ELF system, we can't relax an externally visible symbol,
715 because it may be overridden by a shared library. However, if
716 TARGET_OS is "elf", then we presume that we are assembling for an
717 embedded system, in which case we don't have to worry about shared
718 libraries, and we can relax any external sym. */
720 #define relaxable_symbol(symbol) \
721 (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \
722 || S_IS_WEAK (symbol)))
724 /* Compute the relocation code for a fixup of SIZE bytes, using pc
725 relative relocation if PCREL is non-zero. PIC says whether a special
726 pic relocation was requested. */
728 static bfd_reloc_code_real_type get_reloc_code
729 PARAMS ((int, int, enum pic_relocation));
731 static bfd_reloc_code_real_type
732 get_reloc_code (size, pcrel, pic)
735 enum pic_relocation pic;
743 return BFD_RELOC_8_GOT_PCREL;
745 return BFD_RELOC_16_GOT_PCREL;
747 return BFD_RELOC_32_GOT_PCREL;
755 return BFD_RELOC_8_GOTOFF;
757 return BFD_RELOC_16_GOTOFF;
759 return BFD_RELOC_32_GOTOFF;
767 return BFD_RELOC_8_PLT_PCREL;
769 return BFD_RELOC_16_PLT_PCREL;
771 return BFD_RELOC_32_PLT_PCREL;
779 return BFD_RELOC_8_PLTOFF;
781 return BFD_RELOC_16_PLTOFF;
783 return BFD_RELOC_32_PLTOFF;
793 return BFD_RELOC_8_PCREL;
795 return BFD_RELOC_16_PCREL;
797 return BFD_RELOC_32_PCREL;
817 as_bad (_("Can not do %d byte pc-relative relocation"), size);
819 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
824 as_bad (_("Can not do %d byte relocation"), size);
826 as_bad (_("Can not do %d byte pic relocation"), size);
829 return BFD_RELOC_NONE;
832 /* Here we decide which fixups can be adjusted to make them relative
833 to the beginning of the section instead of the symbol. Basically
834 we need to make sure that the dynamic relocations are done
835 correctly, so in some cases we force the original symbol to be
838 tc_m68k_fix_adjustable (fixP)
841 /* Adjust_reloc_syms doesn't know about the GOT. */
842 switch (fixP->fx_r_type)
844 case BFD_RELOC_8_GOT_PCREL:
845 case BFD_RELOC_16_GOT_PCREL:
846 case BFD_RELOC_32_GOT_PCREL:
847 case BFD_RELOC_8_GOTOFF:
848 case BFD_RELOC_16_GOTOFF:
849 case BFD_RELOC_32_GOTOFF:
850 case BFD_RELOC_8_PLT_PCREL:
851 case BFD_RELOC_16_PLT_PCREL:
852 case BFD_RELOC_32_PLT_PCREL:
853 case BFD_RELOC_8_PLTOFF:
854 case BFD_RELOC_16_PLTOFF:
855 case BFD_RELOC_32_PLTOFF:
858 case BFD_RELOC_VTABLE_INHERIT:
859 case BFD_RELOC_VTABLE_ENTRY:
869 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
871 #define relaxable_symbol(symbol) 1
878 tc_gen_reloc (section, fixp)
879 asection *section ATTRIBUTE_UNUSED;
883 bfd_reloc_code_real_type code;
885 /* If the tcbit is set, then this was a fixup of a negative value
886 that was never resolved. We do not have a reloc to handle this,
887 so just return. We assume that other code will have detected this
888 situation and produced a helpful error message, so we just tell the
889 user that the reloc cannot be produced. */
893 as_bad_where (fixp->fx_file, fixp->fx_line,
894 _("Unable to produce reloc against symbol '%s'"),
895 S_GET_NAME (fixp->fx_addsy));
899 if (fixp->fx_r_type != BFD_RELOC_NONE)
901 code = fixp->fx_r_type;
903 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
904 that fixup_segment converted a non-PC relative reloc into a
905 PC relative reloc. In such a case, we need to convert the
912 code = BFD_RELOC_8_PCREL;
915 code = BFD_RELOC_16_PCREL;
918 code = BFD_RELOC_32_PCREL;
920 case BFD_RELOC_8_PCREL:
921 case BFD_RELOC_16_PCREL:
922 case BFD_RELOC_32_PCREL:
923 case BFD_RELOC_8_GOT_PCREL:
924 case BFD_RELOC_16_GOT_PCREL:
925 case BFD_RELOC_32_GOT_PCREL:
926 case BFD_RELOC_8_GOTOFF:
927 case BFD_RELOC_16_GOTOFF:
928 case BFD_RELOC_32_GOTOFF:
929 case BFD_RELOC_8_PLT_PCREL:
930 case BFD_RELOC_16_PLT_PCREL:
931 case BFD_RELOC_32_PLT_PCREL:
932 case BFD_RELOC_8_PLTOFF:
933 case BFD_RELOC_16_PLTOFF:
934 case BFD_RELOC_32_PLTOFF:
937 as_bad_where (fixp->fx_file, fixp->fx_line,
938 _("Cannot make %s relocation PC relative"),
939 bfd_get_reloc_code_name (code));
945 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
946 switch (F (fixp->fx_size, fixp->fx_pcrel))
948 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
949 MAP (1, 0, BFD_RELOC_8);
950 MAP (2, 0, BFD_RELOC_16);
951 MAP (4, 0, BFD_RELOC_32);
952 MAP (1, 1, BFD_RELOC_8_PCREL);
953 MAP (2, 1, BFD_RELOC_16_PCREL);
954 MAP (4, 1, BFD_RELOC_32_PCREL);
962 reloc = (arelent *) xmalloc (sizeof (arelent));
963 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
964 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
965 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
968 reloc->addend = fixp->fx_addnumber;
973 reloc->addend = fixp->fx_addnumber;
975 reloc->addend = (section->vma
976 /* Explicit sign extension in case char is
978 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
980 + md_pcrel_from (fixp));
983 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
984 assert (reloc->howto != 0);
989 #endif /* BFD_ASSEMBLER */
991 /* Handle of the OPCODE hash table. NULL means any use before
992 m68k_ip_begin() will crash. */
993 static struct hash_control *op_hash;
995 /* Assemble an m68k instruction. */
1002 register struct m68k_op *opP;
1003 register const struct m68k_incant *opcode;
1004 register const char *s;
1005 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1006 char *pdot, *pdotmove;
1007 enum m68k_size siz1, siz2;
1011 LITTLENUM_TYPE words[6];
1012 LITTLENUM_TYPE *wordp;
1013 unsigned long ok_arch = 0;
1015 if (*instring == ' ')
1016 instring++; /* Skip leading whitespace. */
1018 /* Scan up to end of operation-code, which MUST end in end-of-string
1019 or exactly 1 space. */
1021 for (p = instring; *p != '\0'; p++)
1031 the_ins.error = _("No operator");
1035 /* p now points to the end of the opcode name, probably whitespace.
1036 Make sure the name is null terminated by clobbering the
1037 whitespace, look it up in the hash table, then fix it back.
1038 Remove a dot, first, since the opcode tables have none. */
1041 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1042 *pdotmove = pdotmove[1];
1048 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1053 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1054 *pdotmove = pdotmove[-1];
1061 the_ins.error = _("Unknown operator");
1065 /* Found a legitimate opcode, start matching operands. */
1069 if (opcode->m_operands == 0)
1071 char *old = input_line_pointer;
1073 input_line_pointer = p;
1074 /* Ahh - it's a motorola style psuedo op. */
1075 mote_pseudo_table[opcode->m_opnum].poc_handler
1076 (mote_pseudo_table[opcode->m_opnum].poc_val);
1077 input_line_pointer = old;
1083 if (flag_mri && opcode->m_opnum == 0)
1085 /* In MRI mode, random garbage is allowed after an instruction
1086 which accepts no operands. */
1087 the_ins.args = opcode->m_operands;
1088 the_ins.numargs = opcode->m_opnum;
1089 the_ins.numo = opcode->m_codenum;
1090 the_ins.opcode[0] = getone (opcode);
1091 the_ins.opcode[1] = gettwo (opcode);
1095 for (opP = &the_ins.operands[0]; *p; opP++)
1097 p = crack_operand (p, opP);
1101 the_ins.error = opP->error;
1106 opsfound = opP - &the_ins.operands[0];
1108 /* This ugly hack is to support the floating pt opcodes in their
1109 standard form. Essentially, we fake a first enty of type COP#1 */
1110 if (opcode->m_operands[0] == 'I')
1114 for (n = opsfound; n > 0; --n)
1115 the_ins.operands[n] = the_ins.operands[n - 1];
1117 memset ((char *) (&the_ins.operands[0]), '\0',
1118 sizeof (the_ins.operands[0]));
1119 the_ins.operands[0].mode = CONTROL;
1120 the_ins.operands[0].reg = m68k_float_copnum;
1124 /* We've got the operands. Find an opcode that'll accept them. */
1127 /* If we didn't get the right number of ops, or we have no
1128 common model with this pattern then reject this pattern. */
1130 ok_arch |= opcode->m_arch;
1131 if (opsfound != opcode->m_opnum
1132 || ((opcode->m_arch & current_architecture) == 0))
1136 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1140 /* Warning: this switch is huge! */
1141 /* I've tried to organize the cases into this order:
1142 non-alpha first, then alpha by letter. Lower-case
1143 goes directly before uppercase counterpart. */
1144 /* Code with multiple case ...: gets sorted by the lowest
1145 case ... it belongs to. I hope this makes sense. */
1251 if (opP->reg == PC || opP->reg == ZPC)
1268 if (opP->reg == PC || opP->reg == ZPC)
1287 if (opP->reg == PC || opP->reg == ZPC)
1297 if (opP->mode != IMMED)
1299 else if (s[1] == 'b'
1300 && ! isvar (&opP->disp)
1301 && (opP->disp.exp.X_op != O_constant
1302 || ! isbyte (opP->disp.exp.X_add_number)))
1304 else if (s[1] == 'B'
1305 && ! isvar (&opP->disp)
1306 && (opP->disp.exp.X_op != O_constant
1307 || ! issbyte (opP->disp.exp.X_add_number)))
1309 else if (s[1] == 'w'
1310 && ! isvar (&opP->disp)
1311 && (opP->disp.exp.X_op != O_constant
1312 || ! isword (opP->disp.exp.X_add_number)))
1314 else if (s[1] == 'W'
1315 && ! isvar (&opP->disp)
1316 && (opP->disp.exp.X_op != O_constant
1317 || ! issword (opP->disp.exp.X_add_number)))
1323 if (opP->mode != IMMED)
1328 if (opP->mode == AREG
1329 || opP->mode == CONTROL
1330 || opP->mode == FPREG
1331 || opP->mode == IMMED
1332 || opP->mode == REGLST
1333 || (opP->mode != ABSL
1335 || opP->reg == ZPC)))
1340 if (opP->mode == CONTROL
1341 || opP->mode == FPREG
1342 || opP->mode == REGLST
1343 || opP->mode == IMMED
1344 || (opP->mode != ABSL
1346 || opP->reg == ZPC)))
1374 if (opP->mode == CONTROL
1375 || opP->mode == FPREG
1376 || opP->mode == REGLST)
1381 if (opP->mode != AINC)
1386 if (opP->mode != ADEC)
1436 if (opP->reg == PC || opP->reg == ZPC)
1457 case '~': /* For now! (JF FOO is this right?) */
1479 if (opP->mode != CONTROL
1480 || (opP->reg != TT0 && opP->reg != TT1))
1485 if (opP->mode != AREG)
1490 if (opP->mode != AINDR)
1495 if (opP->mode != ABSL
1497 && strncmp (instring, "jbsr", 4) == 0))
1502 if (opP->mode != CONTROL || opP->reg != CCR)
1507 if (opP->mode != DISP
1509 || opP->reg > ADDR7)
1514 if (opP->mode != DREG)
1519 if (opP->reg != ACC)
1524 if (opP->mode != FPREG)
1529 if (opP->reg != MACSR)
1534 if (opP->reg != MASK)
1539 if (opP->mode != CONTROL
1546 if (opP->mode != CONTROL
1548 || opP->reg > last_movec_reg)
1552 const enum m68k_register *rp;
1553 for (rp = control_regs; *rp; rp++)
1554 if (*rp == opP->reg)
1562 if (opP->mode != IMMED)
1568 if (opP->mode == DREG
1569 || opP->mode == AREG
1570 || opP->mode == FPREG)
1579 opP->mask = 1 << (opP->reg - DATA0);
1582 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1585 opP->mask = 1 << (opP->reg - FP0 + 16);
1593 else if (opP->mode == CONTROL)
1602 opP->mask = 1 << 24;
1605 opP->mask = 1 << 25;
1608 opP->mask = 1 << 26;
1617 else if (opP->mode != REGLST)
1619 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1621 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1626 if (opP->mode != IMMED)
1628 else if (opP->disp.exp.X_op != O_constant
1629 || ! issbyte (opP->disp.exp.X_add_number))
1631 else if (! m68k_quick
1632 && instring[3] != 'q'
1633 && instring[4] != 'q')
1638 if (opP->mode != DREG
1639 && opP->mode != IMMED
1640 && opP->mode != ABSL)
1645 if (opP->mode != IMMED)
1647 else if (opP->disp.exp.X_op != O_constant
1648 || opP->disp.exp.X_add_number < 1
1649 || opP->disp.exp.X_add_number > 8)
1651 else if (! m68k_quick
1652 && (strncmp (instring, "add", 3) == 0
1653 || strncmp (instring, "sub", 3) == 0)
1654 && instring[3] != 'q')
1659 if (opP->mode != DREG && opP->mode != AREG)
1664 if (opP->mode != AINDR
1665 && (opP->mode != BASE
1667 && opP->reg != ZADDR0)
1668 || opP->disp.exp.X_op != O_absent
1669 || ((opP->index.reg < DATA0
1670 || opP->index.reg > DATA7)
1671 && (opP->index.reg < ADDR0
1672 || opP->index.reg > ADDR7))
1673 || opP->index.size != SIZE_UNSPEC
1674 || opP->index.scale != 1))
1679 if (opP->mode != CONTROL
1680 || ! (opP->reg == FPI
1682 || opP->reg == FPC))
1687 if (opP->mode != CONTROL || opP->reg != SR)
1692 if (opP->mode != IMMED)
1694 else if (opP->disp.exp.X_op != O_constant
1695 || opP->disp.exp.X_add_number < 0
1696 || opP->disp.exp.X_add_number > 7)
1701 if (opP->mode != CONTROL || opP->reg != USP)
1705 /* JF these are out of order. We could put them
1706 in order if we were willing to put up with
1707 bunches of #ifdef m68851s in the code.
1709 Don't forget that you need these operands
1710 to use 68030 MMU instructions. */
1712 /* Memory addressing mode used by pflushr. */
1714 if (opP->mode == CONTROL
1715 || opP->mode == FPREG
1716 || opP->mode == DREG
1717 || opP->mode == AREG
1718 || opP->mode == REGLST)
1720 /* We should accept immediate operands, but they
1721 supposedly have to be quad word, and we don't
1722 handle that. I would like to see what a Motorola
1723 assembler does before doing something here. */
1724 if (opP->mode == IMMED)
1729 if (opP->mode != CONTROL
1730 || (opP->reg != SFC && opP->reg != DFC))
1735 if (opP->mode != CONTROL || opP->reg != TC)
1740 if (opP->mode != CONTROL || opP->reg != AC)
1745 if (opP->mode != CONTROL
1748 && opP->reg != SCC))
1753 if (opP->mode != CONTROL
1759 if (opP->mode != CONTROL
1762 && opP->reg != CRP))
1767 if (opP->mode != CONTROL
1768 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1769 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1774 if (opP->mode != CONTROL || opP->reg != PSR)
1779 if (opP->mode != CONTROL || opP->reg != PCSR)
1784 if (opP->mode != CONTROL
1793 if (opP->mode != ABSL)
1798 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1800 /* FIXME: kludge instead of fixing parser:
1801 upper/lower registers are *not* CONTROL
1802 registers, but ordinary ones. */
1803 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1804 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1822 opcode = opcode->m_next;
1827 && !(ok_arch & current_architecture))
1832 _("invalid instruction for this architecture; needs "));
1833 cp = buf + strlen (buf);
1837 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1840 strcpy (cp, _("mmu (68030 or 68851)"));
1843 strcpy (cp, _("68020 or higher"));
1846 strcpy (cp, _("68000 or higher"));
1849 strcpy (cp, _("68010 or higher"));
1853 int got_one = 0, idx;
1855 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1858 if ((archs[idx].arch & ok_arch)
1859 && ! archs[idx].alias)
1863 strcpy (cp, " or ");
1867 strcpy (cp, archs[idx].name);
1873 cp = xmalloc (strlen (buf) + 1);
1878 the_ins.error = _("operands mismatch");
1885 /* Now assemble it. */
1886 the_ins.args = opcode->m_operands;
1887 the_ins.numargs = opcode->m_opnum;
1888 the_ins.numo = opcode->m_codenum;
1889 the_ins.opcode[0] = getone (opcode);
1890 the_ins.opcode[1] = gettwo (opcode);
1892 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1894 /* This switch is a doozy.
1895 Watch the first step; its a big one! */
1923 tmpreg = 0x3c; /* 7.4 */
1924 if (strchr ("bwl", s[1]))
1925 nextword = get_num (&opP->disp, 80);
1927 nextword = get_num (&opP->disp, 0);
1928 if (isvar (&opP->disp))
1929 add_fix (s[1], &opP->disp, 0, 0);
1933 if (!isbyte (nextword))
1934 opP->error = _("operand out of range");
1939 if (!isword (nextword))
1940 opP->error = _("operand out of range");
1945 if (!issword (nextword))
1946 opP->error = _("operand out of range");
1951 addword (nextword >> 16);
1978 /* We gotta put out some float. */
1979 if (op (&opP->disp) != O_big)
1984 /* Can other cases happen here? */
1985 if (op (&opP->disp) != O_constant)
1988 val = (valueT) offs (&opP->disp);
1992 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1993 val >>= LITTLENUM_NUMBER_OF_BITS;
1997 offs (&opP->disp) = gencnt;
1999 if (offs (&opP->disp) > 0)
2001 if (offs (&opP->disp) > baseo)
2003 as_warn (_("Bignum too big for %c format; truncated"),
2005 offs (&opP->disp) = baseo;
2007 baseo -= offs (&opP->disp);
2010 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2011 offs (&opP->disp)--;
2016 gen_to_words (words, baseo, (long) outro);
2017 for (wordp = words; baseo--; wordp++)
2021 tmpreg = opP->reg - DATA; /* 0.dreg */
2024 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2027 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2030 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2033 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2037 nextword = get_num (&opP->disp, 80);
2040 && ! isvar (&opP->disp)
2043 opP->disp.exp.X_op = O_symbol;
2044 #ifndef BFD_ASSEMBLER
2045 opP->disp.exp.X_add_symbol = &abs_symbol;
2047 opP->disp.exp.X_add_symbol =
2048 section_symbol (absolute_section);
2052 /* Force into index mode. Hope this works. */
2054 /* We do the first bit for 32-bit displacements, and the
2055 second bit for 16 bit ones. It is possible that we
2056 should make the default be WORD instead of LONG, but
2057 I think that'd break GCC, so we put up with a little
2058 inefficiency for the sake of working output. */
2060 if (!issword (nextword)
2061 || (isvar (&opP->disp)
2062 && ((opP->disp.size == SIZE_UNSPEC
2063 && flag_short_refs == 0
2064 && cpu_of_arch (current_architecture) >= m68020
2065 && ! arch_coldfire_p (current_architecture))
2066 || opP->disp.size == SIZE_LONG)))
2068 if (cpu_of_arch (current_architecture) < m68020
2069 || arch_coldfire_p (current_architecture))
2071 _("displacement too large for this architecture; needs 68020 or higher");
2073 tmpreg = 0x3B; /* 7.3 */
2075 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2076 if (isvar (&opP->disp))
2080 if (opP->disp.size == SIZE_LONG
2082 /* If the displacement needs pic
2083 relocation it cannot be relaxed. */
2084 || opP->disp.pic_reloc != pic_none
2089 add_fix ('l', &opP->disp, 1, 2);
2093 add_frag (adds (&opP->disp),
2095 TAB (PCREL1632, SZ_UNDEF));
2102 add_fix ('l', &opP->disp, 0, 0);
2107 addword (nextword >> 16);
2112 tmpreg = 0x3A; /* 7.2 */
2114 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2116 if (isvar (&opP->disp))
2120 add_fix ('w', &opP->disp, 1, 0);
2123 add_fix ('w', &opP->disp, 0, 0);
2133 baseo = get_num (&opP->disp, 80);
2134 if (opP->mode == POST || opP->mode == PRE)
2135 outro = get_num (&opP->odisp, 80);
2136 /* Figure out the `addressing mode'.
2137 Also turn on the BASE_DISABLE bit, if needed. */
2138 if (opP->reg == PC || opP->reg == ZPC)
2140 tmpreg = 0x3b; /* 7.3 */
2141 if (opP->reg == ZPC)
2144 else if (opP->reg == 0)
2147 tmpreg = 0x30; /* 6.garbage */
2149 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2152 tmpreg = 0x30 + opP->reg - ZADDR0;
2155 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2157 siz1 = opP->disp.size;
2158 if (opP->mode == POST || opP->mode == PRE)
2159 siz2 = opP->odisp.size;
2163 /* Index register stuff. */
2164 if (opP->index.reg != 0
2165 && opP->index.reg >= DATA
2166 && opP->index.reg <= ADDR7)
2168 nextword |= (opP->index.reg - DATA) << 12;
2170 if (opP->index.size == SIZE_LONG
2171 || (opP->index.size == SIZE_UNSPEC
2172 && m68k_index_width_default == SIZE_LONG))
2175 if ((opP->index.scale != 1
2176 && cpu_of_arch (current_architecture) < m68020)
2177 || (opP->index.scale == 8
2178 && arch_coldfire_p (current_architecture)))
2181 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2184 if (arch_coldfire_p (current_architecture)
2185 && opP->index.size == SIZE_WORD)
2186 opP->error = _("invalid index size for coldfire");
2188 switch (opP->index.scale)
2205 GET US OUT OF HERE! */
2207 /* Must be INDEX, with an index register. Address
2208 register cannot be ZERO-PC, and either :b was
2209 forced, or we know it will fit. For a 68000 or
2210 68010, force this mode anyways, because the
2211 larger modes aren't supported. */
2212 if (opP->mode == BASE
2213 && ((opP->reg >= ADDR0
2214 && opP->reg <= ADDR7)
2217 if (siz1 == SIZE_BYTE
2218 || cpu_of_arch (current_architecture) < m68020
2219 || arch_coldfire_p (current_architecture)
2220 || (siz1 == SIZE_UNSPEC
2221 && ! isvar (&opP->disp)
2222 && issbyte (baseo)))
2224 nextword += baseo & 0xff;
2226 if (isvar (&opP->disp))
2228 /* Do a byte relocation. If it doesn't
2229 fit (possible on m68000) let the
2230 fixup processing complain later. */
2232 add_fix ('B', &opP->disp, 1, 1);
2234 add_fix ('B', &opP->disp, 0, 0);
2236 else if (siz1 != SIZE_BYTE)
2238 if (siz1 != SIZE_UNSPEC)
2239 as_warn (_("Forcing byte displacement"));
2240 if (! issbyte (baseo))
2241 opP->error = _("byte displacement out of range");
2246 else if (siz1 == SIZE_UNSPEC
2248 && isvar (&opP->disp)
2249 && subs (&opP->disp) == NULL
2251 /* If the displacement needs pic
2252 relocation it cannot be relaxed. */
2253 && opP->disp.pic_reloc == pic_none
2257 /* The code in md_convert_frag_1 needs to be
2258 able to adjust nextword. Call frag_grow
2259 to ensure that we have enough space in
2260 the frag obstack to make all the bytes
2263 nextword += baseo & 0xff;
2265 add_frag (adds (&opP->disp), offs (&opP->disp),
2266 TAB (PCINDEX, SZ_UNDEF));
2274 nextword |= 0x40; /* No index reg. */
2275 if (opP->index.reg >= ZDATA0
2276 && opP->index.reg <= ZDATA7)
2277 nextword |= (opP->index.reg - ZDATA0) << 12;
2278 else if (opP->index.reg >= ZADDR0
2279 || opP->index.reg <= ZADDR7)
2280 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2283 /* It isn't simple. */
2285 if (cpu_of_arch (current_architecture) < m68020
2286 || arch_coldfire_p (current_architecture))
2288 _("invalid operand mode for this architecture; needs 68020 or higher");
2291 /* If the guy specified a width, we assume that it is
2292 wide enough. Maybe it isn't. If so, we lose. */
2296 if (isvar (&opP->disp)
2298 : ! issword (baseo))
2303 else if (! isvar (&opP->disp) && baseo == 0)
2312 as_warn (_(":b not permitted; defaulting to :w"));
2322 /* Figure out innner displacement stuff. */
2323 if (opP->mode == POST || opP->mode == PRE)
2325 if (cpu_of_arch (current_architecture) & cpu32)
2326 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2330 if (isvar (&opP->odisp)
2332 : ! issword (outro))
2337 else if (! isvar (&opP->odisp) && outro == 0)
2346 as_warn (_(":b not permitted; defaulting to :w"));
2355 if (opP->mode == POST
2356 && (nextword & 0x40) == 0)
2361 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2363 if (opP->reg == PC || opP->reg == ZPC)
2364 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2366 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2368 if (siz1 == SIZE_LONG)
2369 addword (baseo >> 16);
2370 if (siz1 != SIZE_UNSPEC)
2373 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2374 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2375 if (siz2 == SIZE_LONG)
2376 addword (outro >> 16);
2377 if (siz2 != SIZE_UNSPEC)
2383 nextword = get_num (&opP->disp, 80);
2384 switch (opP->disp.size)
2389 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2391 tmpreg = 0x38; /* 7.0 */
2395 if (isvar (&opP->disp)
2396 && !subs (&opP->disp)
2397 && adds (&opP->disp)
2399 /* If the displacement needs pic relocation it
2400 cannot be relaxed. */
2401 && opP->disp.pic_reloc == pic_none
2404 && !strchr ("~%&$?", s[0]))
2406 tmpreg = 0x3A; /* 7.2 */
2407 add_frag (adds (&opP->disp),
2409 TAB (ABSTOPCREL, SZ_UNDEF));
2412 /* Fall through into long. */
2414 if (isvar (&opP->disp))
2415 add_fix ('l', &opP->disp, 0, 0);
2417 tmpreg = 0x39;/* 7.1 mode */
2418 addword (nextword >> 16);
2423 as_bad (_("unsupported byte value; use a different suffix"));
2427 if (isvar (&opP->disp))
2428 add_fix ('w', &opP->disp, 0, 0);
2430 tmpreg = 0x38;/* 7.0 mode */
2438 as_bad (_("unknown/incorrect operand"));
2441 install_gen_operand (s[1], tmpreg);
2447 { /* JF: I hate floating point! */
2462 tmpreg = get_num (&opP->disp, tmpreg);
2463 if (isvar (&opP->disp))
2464 add_fix (s[1], &opP->disp, 0, 0);
2467 case 'b': /* Danger: These do no check for
2468 certain types of overflow.
2470 if (!isbyte (tmpreg))
2471 opP->error = _("out of range");
2472 insop (tmpreg, opcode);
2473 if (isvar (&opP->disp))
2474 the_ins.reloc[the_ins.nrel - 1].n =
2475 (opcode->m_codenum) * 2 + 1;
2478 if (!issbyte (tmpreg))
2479 opP->error = _("out of range");
2480 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2481 if (isvar (&opP->disp))
2482 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2485 if (!isword (tmpreg))
2486 opP->error = _("out of range");
2487 insop (tmpreg, opcode);
2488 if (isvar (&opP->disp))
2489 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2492 if (!issword (tmpreg))
2493 opP->error = _("out of range");
2494 insop (tmpreg, opcode);
2495 if (isvar (&opP->disp))
2496 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2499 /* Because of the way insop works, we put these two out
2501 insop (tmpreg, opcode);
2502 insop (tmpreg >> 16, opcode);
2503 if (isvar (&opP->disp))
2504 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2511 install_operand (s[1], tmpreg);
2522 install_operand (s[1], opP->reg - ADDR);
2526 tmpreg = get_num (&opP->disp, 80);
2530 add_fix ('B', &opP->disp, 1, -1);
2533 add_fix ('w', &opP->disp, 1, 0);
2538 if (! HAVE_LONG_BRANCH (current_architecture))
2539 as_warn (_("Can't use long branches on 68000/68010/5200"));
2540 the_ins.opcode[0] |= 0xff;
2541 add_fix ('l', &opP->disp, 1, 0);
2546 if (subs (&opP->disp)) /* We can't relax it. */
2550 /* If the displacement needs pic relocation it cannot be
2552 if (opP->disp.pic_reloc != pic_none)
2555 /* This could either be a symbol, or an absolute
2556 address. If it's an absolute address, turn it into
2557 an absolute jump right here and keep it out of the
2559 if (adds (&opP->disp) == 0)
2561 if (the_ins.opcode[0] == 0x6000) /* jbra */
2562 the_ins.opcode[0] = 0x4EF9;
2563 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2564 the_ins.opcode[0] = 0x4EB9;
2567 the_ins.opcode[0] ^= 0x0100;
2568 the_ins.opcode[0] |= 0x0006;
2571 add_fix ('l', &opP->disp, 0, 0);
2577 /* Now we know it's going into the relaxer. Now figure
2578 out which mode. We try in this order of preference:
2579 long branch, absolute jump, byte/word branches only. */
2580 if (HAVE_LONG_BRANCH (current_architecture))
2581 add_frag (adds (&opP->disp), offs (&opP->disp),
2582 TAB (BRANCHBWL, SZ_UNDEF));
2583 else if (! flag_keep_pcrel)
2585 if ((the_ins.opcode[0] == 0x6000)
2586 || (the_ins.opcode[0] == 0x6100))
2587 add_frag (adds (&opP->disp), offs (&opP->disp),
2588 TAB (BRABSJUNC, SZ_UNDEF));
2590 add_frag (adds (&opP->disp), offs (&opP->disp),
2591 TAB (BRABSJCOND, SZ_UNDEF));
2594 add_frag (adds (&opP->disp), offs (&opP->disp),
2595 TAB (BRANCHBW, SZ_UNDEF));
2598 if (isvar (&opP->disp))
2600 /* Check for DBcc instructions. We can relax them,
2601 but only if we have long branches and/or absolute
2603 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2604 && (HAVE_LONG_BRANCH (current_architecture)
2605 || (! flag_keep_pcrel)))
2607 if (HAVE_LONG_BRANCH (current_architecture))
2608 add_frag (adds (&opP->disp), offs (&opP->disp),
2609 TAB (DBCCLBR, SZ_UNDEF));
2611 add_frag (adds (&opP->disp), offs (&opP->disp),
2612 TAB (DBCCABSJ, SZ_UNDEF));
2615 add_fix ('w', &opP->disp, 1, 0);
2619 case 'C': /* Fixed size LONG coproc branches. */
2620 add_fix ('l', &opP->disp, 1, 0);
2624 case 'c': /* Var size Coprocesssor branches. */
2625 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2627 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2628 add_fix ('l', &opP->disp, 1, 0);
2633 add_frag (adds (&opP->disp), offs (&opP->disp),
2634 TAB (FBRANCH, SZ_UNDEF));
2641 case 'C': /* Ignore it. */
2644 case 'd': /* JF this is a kludge. */
2645 install_operand ('s', opP->reg - ADDR);
2646 tmpreg = get_num (&opP->disp, 80);
2647 if (!issword (tmpreg))
2649 as_warn (_("Expression out of range, using 0"));
2656 install_operand (s[1], opP->reg - DATA);
2659 case 'E': /* Ignore it. */
2663 install_operand (s[1], opP->reg - FP0);
2666 case 'G': /* Ignore it. */
2671 tmpreg = opP->reg - COP0;
2672 install_operand (s[1], tmpreg);
2675 case 'J': /* JF foo. */
2748 install_operand (s[1], tmpreg);
2752 tmpreg = get_num (&opP->disp, 55);
2753 install_operand (s[1], tmpreg & 0x7f);
2760 if (tmpreg & 0x7FF0000)
2761 as_bad (_("Floating point register in register list"));
2762 insop (reverse_16_bits (tmpreg), opcode);
2766 if (tmpreg & 0x700FFFF)
2767 as_bad (_("Wrong register in floating-point reglist"));
2768 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2776 if (tmpreg & 0x7FF0000)
2777 as_bad (_("Floating point register in register list"));
2778 insop (tmpreg, opcode);
2780 else if (s[1] == '8')
2782 if (tmpreg & 0x0FFFFFF)
2783 as_bad (_("incorrect register in reglist"));
2784 install_operand (s[1], tmpreg >> 24);
2788 if (tmpreg & 0x700FFFF)
2789 as_bad (_("wrong register in floating-point reglist"));
2791 install_operand (s[1], tmpreg >> 16);
2796 install_operand (s[1], get_num (&opP->disp, 60));
2800 tmpreg = ((opP->mode == DREG)
2801 ? 0x20 + (int) (opP->reg - DATA)
2802 : (get_num (&opP->disp, 40) & 0x1F));
2803 install_operand (s[1], tmpreg);
2807 tmpreg = get_num (&opP->disp, 10);
2810 install_operand (s[1], tmpreg);
2814 /* This depends on the fact that ADDR registers are eight
2815 more than their corresponding DATA regs, so the result
2816 will have the ADDR_REG bit set. */
2817 install_operand (s[1], opP->reg - DATA);
2821 if (opP->mode == AINDR)
2822 install_operand (s[1], opP->reg - DATA);
2824 install_operand (s[1], opP->index.reg - DATA);
2828 if (opP->reg == FPI)
2830 else if (opP->reg == FPS)
2832 else if (opP->reg == FPC)
2836 install_operand (s[1], tmpreg);
2839 case 'S': /* Ignore it. */
2843 install_operand (s[1], get_num (&opP->disp, 30));
2846 case 'U': /* Ignore it. */
2865 as_fatal (_("failed sanity check"));
2866 } /* switch on cache token. */
2867 install_operand (s[1], tmpreg);
2870 /* JF: These are out of order, I fear. */
2883 install_operand (s[1], tmpreg);
2909 install_operand (s[1], tmpreg);
2913 if (opP->reg == VAL)
2932 install_operand (s[1], tmpreg);
2946 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2957 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2963 install_operand (s[1], tmpreg);
2966 know (opP->reg == PSR);
2969 know (opP->reg == PCSR);
2984 install_operand (s[1], tmpreg);
2987 tmpreg = get_num (&opP->disp, 20);
2988 install_operand (s[1], tmpreg);
2990 case '_': /* used only for move16 absolute 32-bit address. */
2991 if (isvar (&opP->disp))
2992 add_fix ('l', &opP->disp, 0, 0);
2993 tmpreg = get_num (&opP->disp, 80);
2994 addword (tmpreg >> 16);
2995 addword (tmpreg & 0xFFFF);
2998 install_operand (s[1], opP->reg - DATA0L);
2999 opP->reg -= (DATA0L);
3000 opP->reg &= 0x0F; /* remove upper/lower bit. */
3007 /* By the time whe get here (FINALLY) the_ins contains the complete
3008 instruction, ready to be emitted. . . */
3012 reverse_16_bits (in)
3018 static int mask[16] =
3020 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3021 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3023 for (n = 0; n < 16; n++)
3026 out |= mask[15 - n];
3029 } /* reverse_16_bits() */
3038 static int mask[8] =
3040 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3043 for (n = 0; n < 8; n++)
3049 } /* reverse_8_bits() */
3051 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3052 (that value is chosen in the frag_var call in md_assemble). TYPE
3053 is the subtype of the frag to be generated; its primary type is
3054 rs_machine_dependent.
3056 The TYPE parameter is also used by md_convert_frag_1 and
3057 md_estimate_size_before_relax. The appropriate type of fixup will
3058 be emitted by md_convert_frag_1.
3060 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3062 install_operand (mode, val)
3069 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3072 the_ins.opcode[0] |= val << 9;
3075 the_ins.opcode[1] |= val << 12;
3078 the_ins.opcode[1] |= val << 6;
3081 the_ins.opcode[1] |= val;
3084 the_ins.opcode[2] |= val << 12;
3087 the_ins.opcode[2] |= val << 6;
3090 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3091 three words long! */
3093 the_ins.opcode[2] |= val;
3096 the_ins.opcode[1] |= val << 7;
3099 the_ins.opcode[1] |= val << 10;
3103 the_ins.opcode[1] |= val << 5;
3108 the_ins.opcode[1] |= (val << 10) | (val << 7);
3111 the_ins.opcode[1] |= (val << 12) | val;
3114 the_ins.opcode[0] |= val = 0xff;
3117 the_ins.opcode[0] |= val << 9;
3120 the_ins.opcode[1] |= val;
3123 the_ins.opcode[1] |= val;
3124 the_ins.numo++; /* What a hack. */
3127 the_ins.opcode[1] |= val << 4;
3135 the_ins.opcode[0] |= (val << 6);
3138 the_ins.opcode[1] = (val >> 16);
3139 the_ins.opcode[2] = val & 0xffff;
3142 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3143 the_ins.opcode[0] |= ((val & 0x7) << 9);
3144 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3147 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3148 the_ins.opcode[0] |= ((val & 0x7) << 9);
3151 the_ins.opcode[1] |= val << 12;
3152 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3155 the_ins.opcode[0] |= (val & 0xF);
3156 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3159 the_ins.opcode[1] |= (val & 0xF);
3160 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3163 the_ins.opcode[1] |= ((val != 1) << 10);
3167 as_fatal (_("failed sanity check."));
3169 } /* install_operand() */
3172 install_gen_operand (mode, val)
3179 the_ins.opcode[0] |= val;
3182 /* This is a kludge!!! */
3183 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3192 the_ins.opcode[0] |= val;
3194 /* more stuff goes here. */
3196 as_fatal (_("failed sanity check."));
3198 } /* install_gen_operand() */
3201 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3202 * then deal with the bitfield hack.
3206 crack_operand (str, opP)
3208 register struct m68k_op *opP;
3210 register int parens;
3212 register char *beg_str;
3220 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3226 else if (*str == ')')
3230 opP->error = _("Extra )");
3236 if (flag_mri && *str == '\'')
3237 inquote = ! inquote;
3239 if (!*str && parens)
3241 opP->error = _("Missing )");
3246 if (m68k_ip_op (beg_str, opP) != 0)
3253 c = *++str; /* JF bitfield hack. */
3258 as_bad (_("Missing operand"));
3261 /* Detect MRI REG symbols and convert them to REGLSTs. */
3262 if (opP->mode == CONTROL && (int)opP->reg < 0)
3265 opP->mask = ~(int)opP->reg;
3272 /* This is the guts of the machine-dependent assembler. STR points to a
3273 machine dependent instruction. This function is supposed to emit
3274 the frags/bytes it assembles to.
3278 insert_reg (regname, regnum)
3279 const char *regname;
3285 #ifdef REGISTER_PREFIX
3286 if (!flag_reg_prefix_optional)
3288 buf[0] = REGISTER_PREFIX;
3289 strcpy (buf + 1, regname);
3294 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3295 &zero_address_frag));
3297 for (i = 0; regname[i]; i++)
3298 buf[i] = TOUPPER (regname[i]);
3301 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3302 &zero_address_frag));
3311 static const struct init_entry init_table[] =
3370 /* Control registers. */
3371 { "sfc", SFC }, /* Source Function Code. */
3373 { "dfc", DFC }, /* Destination Function Code. */
3375 { "cacr", CACR }, /* Cache Control Register. */
3376 { "caar", CAAR }, /* Cache Address Register. */
3378 { "usp", USP }, /* User Stack Pointer. */
3379 { "vbr", VBR }, /* Vector Base Register. */
3380 { "msp", MSP }, /* Master Stack Pointer. */
3381 { "isp", ISP }, /* Interrupt Stack Pointer. */
3383 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3384 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3385 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3386 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3388 /* 68ec040 versions of same */
3389 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3390 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3391 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3392 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3394 /* mcf5200 versions of same. The ColdFire programmer's reference
3395 manual indicated that the order is 2,3,0,1, but Ken Rose
3396 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3397 { "acr0", ITT0 }, /* Access Control Unit 0. */
3398 { "acr1", ITT1 }, /* Access Control Unit 1. */
3399 { "acr2", DTT0 }, /* Access Control Unit 2. */
3400 { "acr3", DTT1 }, /* Access Control Unit 3. */
3402 { "tc", TC }, /* MMU Translation Control Register. */
3405 { "mmusr", MMUSR }, /* MMU Status Register. */
3406 { "srp", SRP }, /* User Root Pointer. */
3407 { "urp", URP }, /* Supervisor Root Pointer. */
3412 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3413 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3414 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3415 { "mbar", MBAR }, /* Module Base Address Register. */
3416 /* End of control registers. */
3450 /* 68ec030 versions of same. */
3453 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3456 /* Suppressed data and address registers. */
3474 /* Upper and lower data and address registers, used by macw and msacw. */
3518 for (i = 0; init_table[i].name; i++)
3519 insert_reg (init_table[i].name, init_table[i].number);
3522 static int no_68851, no_68881;
3525 /* a.out machine type. Default to 68020. */
3526 int m68k_aout_machtype = 2;
3538 int shorts_this_frag;
3541 /* In MRI mode, the instruction and operands are separated by a
3542 space. Anything following the operands is a comment. The label
3543 has already been removed. */
3551 for (s = str; *s != '\0'; s++)
3553 if ((*s == ' ' || *s == '\t') && ! inquote)
3571 inquote = ! inquote;
3576 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3581 for (n = 0; n < the_ins.numargs; n++)
3582 if (the_ins.operands[n].error)
3584 er = the_ins.operands[n].error;
3590 as_bad (_("%s -- statement `%s' ignored"), er, str);
3594 /* If there is a current label, record that it marks an instruction. */
3595 if (current_label != NULL)
3597 current_label->text = 1;
3598 current_label = NULL;
3602 /* Tie dwarf2 debug info to the address at the start of the insn. */
3603 dwarf2_emit_insn (0);
3606 if (the_ins.nfrag == 0)
3608 /* No frag hacking involved; just put it out. */
3609 toP = frag_more (2 * the_ins.numo);
3610 fromP = &the_ins.opcode[0];
3611 for (m = the_ins.numo; m; --m)
3613 md_number_to_chars (toP, (long) (*fromP), 2);
3617 /* Put out symbol-dependent info. */
3618 for (m = 0; m < the_ins.nrel; m++)
3620 switch (the_ins.reloc[m].wid)
3639 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3640 the_ins.reloc[m].wid);
3643 fixP = fix_new_exp (frag_now,
3644 ((toP - frag_now->fr_literal)
3645 - the_ins.numo * 2 + the_ins.reloc[m].n),
3647 &the_ins.reloc[m].exp,
3648 the_ins.reloc[m].pcrel,
3649 get_reloc_code (n, the_ins.reloc[m].pcrel,
3650 the_ins.reloc[m].pic_reloc));
3651 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3652 if (the_ins.reloc[m].wid == 'B')
3653 fixP->fx_signed = 1;
3658 /* There's some frag hacking. */
3660 /* Calculate the max frag size. */
3663 wid = 2 * the_ins.fragb[0].fragoff;
3664 for (n = 1; n < the_ins.nfrag; n++)
3665 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3666 /* frag_var part. */
3668 /* Make sure the whole insn fits in one chunk, in particular that
3669 the var part is attached, as we access one byte before the
3670 variable frag for byte branches. */
3674 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3679 wid = 2 * the_ins.fragb[n].fragoff;
3681 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3682 toP = frag_more (wid);
3684 shorts_this_frag = 0;
3685 for (m = wid / 2; m; --m)
3687 md_number_to_chars (toP, (long) (*fromP), 2);
3692 for (m = 0; m < the_ins.nrel; m++)
3694 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3696 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3699 wid = the_ins.reloc[m].wid;
3702 the_ins.reloc[m].wid = 0;
3703 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3705 fixP = fix_new_exp (frag_now,
3706 ((toP - frag_now->fr_literal)
3707 - the_ins.numo * 2 + the_ins.reloc[m].n),
3709 &the_ins.reloc[m].exp,
3710 the_ins.reloc[m].pcrel,
3711 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3712 the_ins.reloc[m].pic_reloc));
3713 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3715 (void) frag_var (rs_machine_dependent, 10, 0,
3716 (relax_substateT) (the_ins.fragb[n].fragty),
3717 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3719 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3720 shorts_this_frag = 0;
3723 toP = frag_more (n * sizeof (short));
3726 md_number_to_chars (toP, (long) (*fromP), 2);
3732 for (m = 0; m < the_ins.nrel; m++)
3736 wid = the_ins.reloc[m].wid;
3739 the_ins.reloc[m].wid = 0;
3740 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3742 fixP = fix_new_exp (frag_now,
3743 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3744 - shorts_this_frag * 2),
3746 &the_ins.reloc[m].exp,
3747 the_ins.reloc[m].pcrel,
3748 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3749 the_ins.reloc[m].pic_reloc));
3750 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3758 * md_begin -- set up hash tables with 68000 instructions.
3759 * similar to what the vax assembler does. ---phr
3761 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3762 a copy of it at runtime, adding in the information we want but isn't
3763 there. I think it'd be better to have an awk script hack the table
3764 at compile time. Or even just xstr the table and use it as-is. But
3765 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3768 const struct m68k_opcode *ins;
3769 struct m68k_incant *hack, *slak;
3770 const char *retval = 0; /* Empty string, or error msg text. */
3775 flag_reg_prefix_optional = 1;
3777 if (! m68k_rel32_from_cmdline)
3781 op_hash = hash_new ();
3783 obstack_begin (&robyn, 4000);
3784 for (i = 0; i < m68k_numopcodes; i++)
3786 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3789 ins = &m68k_opcodes[i];
3790 /* We *could* ignore insns that don't match our arch here
3791 but just leaving them out of the hash. */
3792 slak->m_operands = ins->args;
3793 slak->m_opnum = strlen (slak->m_operands) / 2;
3794 slak->m_arch = ins->arch;
3795 slak->m_opcode = ins->opcode;
3796 /* This is kludgey. */
3797 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3798 if (i + 1 != m68k_numopcodes
3799 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3801 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3806 slak = slak->m_next;
3810 retval = hash_insert (op_hash, ins->name, (char *) hack);
3812 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3815 for (i = 0; i < m68k_numaliases; i++)
3817 const char *name = m68k_opcode_aliases[i].primary;
3818 const char *alias = m68k_opcode_aliases[i].alias;
3819 PTR val = hash_find (op_hash, name);
3821 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3822 retval = hash_insert (op_hash, alias, val);
3824 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3827 /* In MRI mode, all unsized branches are variable sized. Normally,
3828 they are word sized. */
3831 static struct m68k_opcode_alias mri_aliases[] =
3852 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3855 const char *name = mri_aliases[i].primary;
3856 const char *alias = mri_aliases[i].alias;
3857 PTR val = hash_find (op_hash, name);
3859 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3860 retval = hash_jam (op_hash, alias, val);
3862 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3866 for (i = 0; i < (int) sizeof (notend_table); i++)
3868 notend_table[i] = 0;
3869 alt_notend_table[i] = 0;
3871 notend_table[','] = 1;
3872 notend_table['{'] = 1;
3873 notend_table['}'] = 1;
3874 alt_notend_table['a'] = 1;
3875 alt_notend_table['A'] = 1;
3876 alt_notend_table['d'] = 1;
3877 alt_notend_table['D'] = 1;
3878 alt_notend_table['#'] = 1;
3879 alt_notend_table['&'] = 1;
3880 alt_notend_table['f'] = 1;
3881 alt_notend_table['F'] = 1;
3882 #ifdef REGISTER_PREFIX
3883 alt_notend_table[REGISTER_PREFIX] = 1;
3886 /* We need to put '(' in alt_notend_table to handle
3887 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3889 alt_notend_table['('] = 1;
3891 /* We need to put '@' in alt_notend_table to handle
3892 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3894 alt_notend_table['@'] = 1;
3896 /* We need to put digits in alt_notend_table to handle
3897 bfextu %d0{24:1},%d0
3899 alt_notend_table['0'] = 1;
3900 alt_notend_table['1'] = 1;
3901 alt_notend_table['2'] = 1;
3902 alt_notend_table['3'] = 1;
3903 alt_notend_table['4'] = 1;
3904 alt_notend_table['5'] = 1;
3905 alt_notend_table['6'] = 1;
3906 alt_notend_table['7'] = 1;
3907 alt_notend_table['8'] = 1;
3908 alt_notend_table['9'] = 1;
3910 #ifndef MIT_SYNTAX_ONLY
3911 /* Insert pseudo ops, these have to go into the opcode table since
3912 gas expects pseudo ops to start with a dot. */
3915 while (mote_pseudo_table[n].poc_name)
3917 hack = (struct m68k_incant *)
3918 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3919 hash_insert (op_hash,
3920 mote_pseudo_table[n].poc_name, (char *) hack);
3921 hack->m_operands = 0;
3931 record_alignment (text_section, 2);
3932 record_alignment (data_section, 2);
3933 record_alignment (bss_section, 2);
3938 select_control_regs ()
3940 /* Note which set of "movec" control registers is available. */
3941 switch (cpu_of_arch (current_architecture))
3944 as_warn (_("architecture not yet selected: defaulting to 68020"));
3945 control_regs = m68020_control_regs;
3949 control_regs = m68000_control_regs;
3952 control_regs = m68010_control_regs;
3956 control_regs = m68020_control_regs;
3959 control_regs = m68040_control_regs;
3962 control_regs = m68060_control_regs;
3965 control_regs = cpu32_control_regs;
3971 control_regs = mcf_control_regs;
3979 m68k_init_after_args ()
3981 if (cpu_of_arch (current_architecture) == 0)
3984 const char *default_cpu = TARGET_CPU;
3986 if (*default_cpu == 'm')
3988 for (i = 0; i < n_archs; i++)
3989 if (strcasecmp (default_cpu, archs[i].name) == 0)
3993 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3994 current_architecture |= m68020;
3997 current_architecture |= archs[i].arch;
3999 /* Permit m68881 specification with all cpus; those that can't work
4000 with a coprocessor could be doing emulation. */
4001 if (current_architecture & m68851)
4003 if (current_architecture & m68040)
4005 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4008 /* What other incompatibilities could we check for? */
4010 /* Toss in some default assumptions about coprocessors. */
4012 && (cpu_of_arch (current_architecture)
4013 /* Can CPU32 have a 68881 coprocessor?? */
4014 & (m68020 | m68030 | cpu32)))
4016 current_architecture |= m68881;
4019 && (cpu_of_arch (current_architecture) & m68020up) != 0
4020 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4022 current_architecture |= m68851;
4024 if (no_68881 && (current_architecture & m68881))
4025 as_bad (_("options for 68881 and no-68881 both given"));
4026 if (no_68851 && (current_architecture & m68851))
4027 as_bad (_("options for 68851 and no-68851 both given"));
4030 /* Work out the magic number. This isn't very general. */
4031 if (current_architecture & m68000)
4032 m68k_aout_machtype = 0;
4033 else if (current_architecture & m68010)
4034 m68k_aout_machtype = 1;
4035 else if (current_architecture & m68020)
4036 m68k_aout_machtype = 2;
4038 m68k_aout_machtype = 2;
4041 /* Note which set of "movec" control registers is available. */
4042 select_control_regs ();
4044 if (cpu_of_arch (current_architecture) < m68020
4045 || arch_coldfire_p (current_architecture))
4046 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4049 /* This is called when a label is defined. */
4052 m68k_frob_label (sym)
4055 struct label_line *n;
4057 n = (struct label_line *) xmalloc (sizeof *n);
4060 as_where (&n->file, &n->line);
4066 /* This is called when a value that is not an instruction is emitted. */
4069 m68k_flush_pending_output ()
4071 current_label = NULL;
4074 /* This is called at the end of the assembly, when the final value of
4075 the label is known. We warn if this is a text symbol aligned at an
4079 m68k_frob_symbol (sym)
4082 if (S_GET_SEGMENT (sym) == reg_section
4083 && (int) S_GET_VALUE (sym) < 0)
4085 S_SET_SEGMENT (sym, absolute_section);
4086 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4088 else if ((S_GET_VALUE (sym) & 1) != 0)
4090 struct label_line *l;
4092 for (l = labels; l != NULL; l = l->next)
4094 if (l->label == sym)
4097 as_warn_where (l->file, l->line,
4098 _("text label `%s' aligned to odd boundary"),
4106 /* This is called if we go in or out of MRI mode because of the .mri
4110 m68k_mri_mode_change (on)
4115 if (! flag_reg_prefix_optional)
4117 flag_reg_prefix_optional = 1;
4118 #ifdef REGISTER_PREFIX
4123 if (! m68k_rel32_from_cmdline)
4128 if (! reg_prefix_optional_seen)
4130 #ifdef REGISTER_PREFIX_OPTIONAL
4131 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4133 flag_reg_prefix_optional = 0;
4135 #ifdef REGISTER_PREFIX
4140 if (! m68k_rel32_from_cmdline)
4145 /* Equal to MAX_PRECISION in atof-ieee.c. */
4146 #define MAX_LITTLENUMS 6
4148 /* Turn a string in input_line_pointer into a floating point constant
4149 of type TYPE, and store the appropriate bytes in *LITP. The number
4150 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4151 returned, or NULL on OK. */
4154 md_atof (type, litP, sizeP)
4160 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4161 LITTLENUM_TYPE *wordP;
4192 return _("Bad call to MD_ATOF()");
4194 t = atof_ieee (input_line_pointer, type, words);
4196 input_line_pointer = t;
4198 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4199 for (wordP = words; prec--;)
4201 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4202 litP += sizeof (LITTLENUM_TYPE);
4208 md_number_to_chars (buf, val, n)
4213 number_to_chars_bigendian (buf, val, n);
4217 md_apply_fix3 (fixP, valP, seg)
4220 segT seg ATTRIBUTE_UNUSED;
4222 offsetT val = *valP;
4223 addressT upper_limit;
4224 offsetT lower_limit;
4226 /* This is unnecessary but it convinces the native rs6000 compiler
4227 to generate the code we want. */
4228 char *buf = fixP->fx_frag->fr_literal;
4229 buf += fixP->fx_where;
4230 /* End ibm compiler workaround. */
4232 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
4234 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4240 memset (buf, 0, fixP->fx_size);
4241 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4243 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4244 && !S_IS_DEFINED (fixP->fx_addsy)
4245 && !S_IS_WEAK (fixP->fx_addsy))
4246 S_SET_WEAK (fixP->fx_addsy);
4251 #ifdef BFD_ASSEMBLER
4252 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4253 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4257 switch (fixP->fx_size)
4259 /* The cast to offsetT below are necessary to make code
4260 correct for machines where ints are smaller than offsetT. */
4264 lower_limit = - (offsetT) 0x80;
4267 *buf++ = (val >> 8);
4269 upper_limit = 0x7fff;
4270 lower_limit = - (offsetT) 0x8000;
4273 *buf++ = (val >> 24);
4274 *buf++ = (val >> 16);
4275 *buf++ = (val >> 8);
4277 upper_limit = 0x7fffffff;
4278 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4281 BAD_CASE (fixP->fx_size);
4284 /* Fix up a negative reloc. */
4285 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4287 fixP->fx_addsy = fixP->fx_subsy;
4288 fixP->fx_subsy = NULL;
4292 /* For non-pc-relative values, it's conceivable we might get something
4293 like "0xff" for a byte field. So extend the upper part of the range
4294 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4295 so that we can do any range checking at all. */
4296 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4297 upper_limit = upper_limit * 2 + 1;
4299 if ((addressT) val > upper_limit
4300 && (val > 0 || val < lower_limit))
4301 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4303 /* A one byte PC-relative reloc means a short branch. We can't use
4304 a short branch with a value of 0 or -1, because those indicate
4305 different opcodes (branches with longer offsets). fixup_segment
4306 in write.c may have clobbered fx_pcrel, so we need to examine the
4309 #ifdef BFD_ASSEMBLER
4310 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4313 && fixP->fx_size == 1
4314 && (fixP->fx_addsy == NULL
4315 || S_IS_DEFINED (fixP->fx_addsy))
4316 && (val == 0 || val == -1))
4317 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4320 /* *fragP has been relaxed to its final size, and now needs to have
4321 the bytes inside it modified to conform to the new size There is UGLY
4325 md_convert_frag_1 (fragP)
4326 register fragS *fragP;
4331 /* Address in object code of the displacement. */
4332 register int object_address = fragP->fr_fix + fragP->fr_address;
4334 /* Address in gas core of the place to store the displacement. */
4335 /* This convinces the native rs6000 compiler to generate the code we
4337 register char *buffer_address = fragP->fr_literal;
4338 buffer_address += fragP->fr_fix;
4339 /* End ibm compiler workaround. */
4341 /* The displacement of the address, from current location. */
4342 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4343 disp = (disp + fragP->fr_offset) - object_address;
4345 switch (fragP->fr_subtype)
4347 case TAB (BRANCHBWL, BYTE):
4348 case TAB (BRABSJUNC, BYTE):
4349 case TAB (BRABSJCOND, BYTE):
4350 case TAB (BRANCHBW, BYTE):
4351 know (issbyte (disp));
4353 as_bad_where (fragP->fr_file, fragP->fr_line,
4354 _("short branch with zero offset: use :w"));
4355 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4356 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4357 fixP->fx_pcrel_adjust = -1;
4359 case TAB (BRANCHBWL, SHORT):
4360 case TAB (BRABSJUNC, SHORT):
4361 case TAB (BRABSJCOND, SHORT):
4362 case TAB (BRANCHBW, SHORT):
4363 fragP->fr_opcode[1] = 0x00;
4364 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4365 1, RELAX_RELOC_PC16);
4368 case TAB (BRANCHBWL, LONG):
4369 fragP->fr_opcode[1] = (char) 0xFF;
4370 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4371 1, RELAX_RELOC_PC32);
4374 case TAB (BRABSJUNC, LONG):
4375 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4377 if (flag_keep_pcrel)
4378 as_fatal(_("Tried to convert PC relative BSR to absolute JSR"));
4379 fragP->fr_opcode[0] = 0x4E;
4380 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4381 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4382 0, RELAX_RELOC_ABS32);
4385 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4387 if (flag_keep_pcrel)
4388 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
4389 fragP->fr_opcode[0] = 0x4E;
4390 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4391 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4392 0, RELAX_RELOC_ABS32);
4397 /* This cannot happen, because jbsr and jbra are the only two
4398 unconditional branches. */
4402 case TAB (BRABSJCOND, LONG):
4403 if (flag_keep_pcrel)
4404 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
4406 /* Only Bcc 68000 instructions can come here
4407 Change bcc into b!cc/jmp absl long. */
4408 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4409 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4411 /* JF: these used to be fr_opcode[2,3], but they may be in a
4412 different frag, in which case refering to them is a no-no.
4413 Only fr_opcode[0,1] are guaranteed to work. */
4414 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4415 *buffer_address++ = (char) 0xf9;
4416 fragP->fr_fix += 2; /* Account for jmp instruction. */
4417 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4418 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4421 case TAB (FBRANCH, SHORT):
4422 know ((fragP->fr_opcode[1] & 0x40) == 0);
4423 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4424 1, RELAX_RELOC_PC16);
4427 case TAB (FBRANCH, LONG):
4428 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4429 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4430 1, RELAX_RELOC_PC32);
4433 case TAB (DBCCLBR, SHORT):
4434 case TAB (DBCCABSJ, SHORT):
4435 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4436 1, RELAX_RELOC_PC16);
4439 case TAB (DBCCLBR, LONG):
4440 /* Only DBcc instructions can come here.
4441 Change dbcc into dbcc/bral.
4442 JF: these used to be fr_opcode[2-7], but that's wrong. */
4443 if (flag_keep_pcrel)
4444 as_fatal(_("Tried to convert DBcc to absolute jump"));
4446 *buffer_address++ = 0x00; /* Branch offset = 4. */
4447 *buffer_address++ = 0x04;
4448 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4449 *buffer_address++ = 0x06;
4450 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4451 *buffer_address++ = (char) 0xff;
4453 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4454 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4458 case TAB (DBCCABSJ, LONG):
4459 /* Only DBcc instructions can come here.
4460 Change dbcc into dbcc/jmp.
4461 JF: these used to be fr_opcode[2-7], but that's wrong. */
4462 if (flag_keep_pcrel)
4463 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
4465 *buffer_address++ = 0x00; /* Branch offset = 4. */
4466 *buffer_address++ = 0x04;
4467 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4468 *buffer_address++ = 0x06;
4469 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4470 *buffer_address++ = (char) 0xf9;
4472 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4473 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4477 case TAB (PCREL1632, SHORT):
4478 fragP->fr_opcode[1] &= ~0x3F;
4479 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4480 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4481 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4484 case TAB (PCREL1632, LONG):
4485 /* Already set to mode 7.3; this indicates: PC indirect with
4486 suppressed index, 32-bit displacement. */
4487 *buffer_address++ = 0x01;
4488 *buffer_address++ = 0x70;
4490 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4491 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4492 fixP->fx_pcrel_adjust = 2;
4495 case TAB (PCINDEX, BYTE):
4496 assert (fragP->fr_fix >= 2);
4497 buffer_address[-2] &= ~1;
4498 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4499 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4500 fixP->fx_pcrel_adjust = 1;
4502 case TAB (PCINDEX, SHORT):
4503 assert (fragP->fr_fix >= 2);
4504 buffer_address[-2] |= 0x1;
4505 buffer_address[-1] = 0x20;
4506 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4507 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4508 fixP->fx_pcrel_adjust = 2;
4511 case TAB (PCINDEX, LONG):
4512 assert (fragP->fr_fix >= 2);
4513 buffer_address[-2] |= 0x1;
4514 buffer_address[-1] = 0x30;
4515 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4516 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4517 fixP->fx_pcrel_adjust = 2;
4520 case TAB (ABSTOPCREL, SHORT):
4521 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4522 1, RELAX_RELOC_PC16);
4525 case TAB (ABSTOPCREL, LONG):
4526 if (flag_keep_pcrel)
4527 as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
4528 /* The thing to do here is force it to ABSOLUTE LONG, since
4529 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4530 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4532 fragP->fr_opcode[1] &= ~0x3F;
4533 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4534 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4535 0, RELAX_RELOC_ABS32);
4541 #ifndef BFD_ASSEMBLER
4544 md_convert_frag (headers, sec, fragP)
4545 object_headers *headers ATTRIBUTE_UNUSED;
4546 segT sec ATTRIBUTE_UNUSED;
4549 md_convert_frag_1 (fragP);
4555 md_convert_frag (abfd, sec, fragP)
4556 bfd *abfd ATTRIBUTE_UNUSED;
4557 segT sec ATTRIBUTE_UNUSED;
4560 md_convert_frag_1 (fragP);
4564 /* Force truly undefined symbols to their maximum size, and generally set up
4565 the frag list to be relaxed
4568 md_estimate_size_before_relax (fragP, segment)
4569 register fragS *fragP;
4572 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4573 switch (fragP->fr_subtype)
4575 case TAB (BRANCHBWL, SZ_UNDEF):
4576 case TAB (BRABSJUNC, SZ_UNDEF):
4577 case TAB (BRABSJCOND, SZ_UNDEF):
4579 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4580 && relaxable_symbol (fragP->fr_symbol))
4582 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4584 else if (flag_short_refs)
4586 /* Symbol is undefined and we want short ref. */
4587 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4591 /* Symbol is still undefined. Make it LONG. */
4592 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4597 case TAB (BRANCHBW, SZ_UNDEF):
4599 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4600 && relaxable_symbol (fragP->fr_symbol))
4602 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4606 /* Symbol is undefined and we don't have long branches. */
4607 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4612 case TAB (FBRANCH, SZ_UNDEF):
4613 case TAB (DBCCLBR, SZ_UNDEF):
4614 case TAB (DBCCABSJ, SZ_UNDEF):
4615 case TAB (PCREL1632, SZ_UNDEF):
4617 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4618 && relaxable_symbol (fragP->fr_symbol))
4621 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4625 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4630 case TAB (PCINDEX, SZ_UNDEF):
4631 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4632 && relaxable_symbol (fragP->fr_symbol)))
4634 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4638 fragP->fr_subtype = TAB (PCINDEX, LONG);
4642 case TAB (ABSTOPCREL, SZ_UNDEF):
4644 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4645 && relaxable_symbol (fragP->fr_symbol)))
4647 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4651 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4660 /* Now that SZ_UNDEF are taken care of, check others. */
4661 switch (fragP->fr_subtype)
4663 case TAB (BRANCHBWL, BYTE):
4664 case TAB (BRABSJUNC, BYTE):
4665 case TAB (BRABSJCOND, BYTE):
4666 case TAB (BRANCHBW, BYTE):
4667 /* We can't do a short jump to the next instruction, so in that
4668 case we force word mode. If the symbol is at the start of a
4669 frag, and it is the next frag with any data in it (usually
4670 this is just the next frag, but assembler listings may
4671 introduce empty frags), we must use word mode. */
4672 if (fragP->fr_symbol)
4676 sym_frag = symbol_get_frag (fragP->fr_symbol);
4677 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
4681 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
4685 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4692 return md_relax_table[fragP->fr_subtype].rlx_length;
4695 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4696 /* the bit-field entries in the relocation_info struct plays hell
4697 with the byte-order problems of cross-assembly. So as a hack,
4698 I added this mach. dependent ri twiddler. Ugly, but it gets
4700 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4701 are symbolnum, most sig. byte first. Last byte is broken up with
4702 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4703 nibble as nuthin. (on Sun 3 at least) */
4704 /* Translate the internal relocation information into target-specific
4708 md_ri_to_chars (the_bytes, ri)
4710 struct reloc_info_generic *ri;
4713 md_number_to_chars (the_bytes, ri->r_address, 4);
4714 /* Now the fun stuff. */
4715 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4716 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4717 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4718 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4719 ((ri->r_extern << 4) & 0x10));
4724 #ifndef BFD_ASSEMBLER
4726 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4729 relax_addressT segment_address_in_file;
4732 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4733 * Out: GNU LD relocation length code: 0, 1, or 2.
4736 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4739 know (fixP->fx_addsy != NULL);
4741 md_number_to_chars (where,
4742 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4745 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4746 ? S_GET_TYPE (fixP->fx_addsy)
4747 : fixP->fx_addsy->sy_number);
4749 where[4] = (r_symbolnum >> 16) & 0x0ff;
4750 where[5] = (r_symbolnum >> 8) & 0x0ff;
4751 where[6] = r_symbolnum & 0x0ff;
4752 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4753 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4757 #endif /* OBJ_AOUT or OBJ_BOUT */
4759 #ifndef WORKING_DOT_WORD
4760 const int md_short_jump_size = 4;
4761 const int md_long_jump_size = 6;
4764 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4766 addressT from_addr, to_addr;
4767 fragS *frag ATTRIBUTE_UNUSED;
4768 symbolS *to_symbol ATTRIBUTE_UNUSED;
4772 offset = to_addr - (from_addr + 2);
4774 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4775 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4779 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4781 addressT from_addr, to_addr;
4787 if (!HAVE_LONG_BRANCH(current_architecture))
4789 if (flag_keep_pcrel)
4790 as_fatal(_("Tried to convert PC relative branch to absolute jump"));
4791 offset = to_addr - S_GET_VALUE (to_symbol);
4792 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4793 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4794 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4799 offset = to_addr - (from_addr + 2);
4800 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4801 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4807 /* Different values of OK tell what its OK to return. Things that
4808 aren't OK are an error (what a shock, no?)
4811 10: Absolute 1:8 only
4812 20: Absolute 0:7 only
4813 30: absolute 0:15 only
4814 40: Absolute 0:31 only
4815 50: absolute 0:127 only
4816 55: absolute -64:63 only
4817 60: absolute -128:127 only
4818 70: absolute 0:4095 only
4825 struct m68k_exp *exp;
4828 if (exp->exp.X_op == O_absent)
4830 /* Do the same thing the VAX asm does. */
4831 op (exp) = O_constant;
4837 as_warn (_("expression out of range: defaulting to 1"));
4841 else if (exp->exp.X_op == O_constant)
4846 if (offs (exp) < 1 || offs (exp) > 8)
4848 as_warn (_("expression out of range: defaulting to 1"));
4853 if (offs (exp) < 0 || offs (exp) > 7)
4857 if (offs (exp) < 0 || offs (exp) > 15)
4861 if (offs (exp) < 0 || offs (exp) > 32)
4865 if (offs (exp) < 0 || offs (exp) > 127)
4869 if (offs (exp) < -64 || offs (exp) > 63)
4873 if (offs (exp) < -128 || offs (exp) > 127)
4877 if (offs (exp) < 0 || offs (exp) > 4095)
4880 as_warn (_("expression out of range: defaulting to 0"));
4888 else if (exp->exp.X_op == O_big)
4890 if (offs (exp) <= 0 /* flonum. */
4891 && (ok == 80 /* no bignums. */
4892 || (ok > 10 /* Small-int ranges including 0 ok. */
4893 /* If we have a flonum zero, a zero integer should
4894 do as well (e.g., in moveq). */
4895 && generic_floating_point_number.exponent == 0
4896 && generic_floating_point_number.low[0] == 0)))
4898 /* HACK! Turn it into a long. */
4899 LITTLENUM_TYPE words[6];
4901 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4902 op (exp) = O_constant;
4905 offs (exp) = words[1] | (words[0] << 16);
4909 op (exp) = O_constant;
4912 offs (exp) = (ok == 10) ? 1 : 0;
4913 as_warn (_("Can't deal with expression; defaulting to %ld"),
4919 if (ok >= 10 && ok <= 70)
4921 op (exp) = O_constant;
4924 offs (exp) = (ok == 10) ? 1 : 0;
4925 as_warn (_("Can't deal with expression; defaulting to %ld"),
4930 if (exp->size != SIZE_UNSPEC)
4938 if (!isbyte (offs (exp)))
4939 as_warn (_("expression doesn't fit in BYTE"));
4942 if (!isword (offs (exp)))
4943 as_warn (_("expression doesn't fit in WORD"));
4951 /* These are the back-ends for the various machine dependent pseudo-ops. */
4955 int ignore ATTRIBUTE_UNUSED;
4957 subseg_set (data_section, 1);
4958 demand_empty_rest_of_line ();
4963 int ignore ATTRIBUTE_UNUSED;
4965 subseg_set (data_section, 2);
4966 demand_empty_rest_of_line ();
4971 int ignore ATTRIBUTE_UNUSED;
4973 /* We don't support putting frags in the BSS segment, we fake it
4974 by marking in_bss, then looking at s_skip for clues. */
4976 subseg_set (bss_section, 0);
4977 demand_empty_rest_of_line ();
4982 int ignore ATTRIBUTE_UNUSED;
4985 register long temp_fill;
4987 temp = 1; /* JF should be 2? */
4988 temp_fill = get_absolute_expression ();
4989 if (!need_pass_2) /* Never make frag if expect extra pass. */
4990 frag_align (temp, (int) temp_fill, 0);
4991 demand_empty_rest_of_line ();
4992 record_alignment (now_seg, temp);
4997 int ignore ATTRIBUTE_UNUSED;
4999 demand_empty_rest_of_line ();
5002 /* Pseudo-ops handled for MRI compatibility. */
5004 /* This function returns non-zero if the argument is a conditional
5005 pseudo-op. This is called when checking whether a pending
5006 alignment is needed. */
5009 m68k_conditional_pseudoop (pop)
5012 return (pop->poc_handler == s_mri_if
5013 || pop->poc_handler == s_mri_else);
5016 /* Handle an MRI style chip specification. */
5025 s = input_line_pointer;
5026 /* We can't use get_symbol_end since the processor names are not proper
5028 while (is_part_of_name (c = *input_line_pointer++))
5030 *--input_line_pointer = 0;
5031 for (i = 0; i < n_archs; i++)
5032 if (strcasecmp (s, archs[i].name) == 0)
5036 as_bad (_("%s: unrecognized processor name"), s);
5037 *input_line_pointer = c;
5038 ignore_rest_of_line ();
5041 *input_line_pointer = c;
5043 if (*input_line_pointer == '/')
5044 current_architecture = 0;
5046 current_architecture &= m68881 | m68851;
5047 current_architecture |= archs[i].arch;
5049 while (*input_line_pointer == '/')
5051 ++input_line_pointer;
5052 s = input_line_pointer;
5053 /* We can't use get_symbol_end since the processor names are not
5055 while (is_part_of_name (c = *input_line_pointer++))
5057 *--input_line_pointer = 0;
5058 if (strcmp (s, "68881") == 0)
5059 current_architecture |= m68881;
5060 else if (strcmp (s, "68851") == 0)
5061 current_architecture |= m68851;
5062 *input_line_pointer = c;
5065 /* Update info about available control registers. */
5066 select_control_regs ();
5069 /* The MRI CHIP pseudo-op. */
5073 int ignore ATTRIBUTE_UNUSED;
5079 stop = mri_comment_field (&stopc);
5082 mri_comment_end (stop, stopc);
5083 demand_empty_rest_of_line ();
5086 /* The MRI FOPT pseudo-op. */
5090 int ignore ATTRIBUTE_UNUSED;
5094 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5098 input_line_pointer += 3;
5099 temp = get_absolute_expression ();
5100 if (temp < 0 || temp > 7)
5101 as_bad (_("bad coprocessor id"));
5103 m68k_float_copnum = COP0 + temp;
5107 as_bad (_("unrecognized fopt option"));
5108 ignore_rest_of_line ();
5112 demand_empty_rest_of_line ();
5115 /* The structure used to handle the MRI OPT pseudo-op. */
5119 /* The name of the option. */
5122 /* If this is not NULL, just call this function. The first argument
5123 is the ARG field of this structure, the second argument is
5124 whether the option was negated. */
5125 void (*pfn) PARAMS ((int arg, int on));
5127 /* If this is not NULL, and the PFN field is NULL, set the variable
5128 this points to. Set it to the ARG field if the option was not
5129 negated, and the NOTARG field otherwise. */
5132 /* The value to pass to PFN or to assign to *PVAR. */
5135 /* The value to assign to *PVAR if the option is negated. If PFN is
5136 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5137 the option may not be negated. */
5141 /* The table used to handle the MRI OPT pseudo-op. */
5143 static void skip_to_comma PARAMS ((int, int));
5144 static void opt_nest PARAMS ((int, int));
5145 static void opt_chip PARAMS ((int, int));
5146 static void opt_list PARAMS ((int, int));
5147 static void opt_list_symbols PARAMS ((int, int));
5149 static const struct opt_action opt_table[] =
5151 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5153 /* We do relaxing, so there is little use for these options. */
5154 { "b", 0, 0, 0, 0 },
5155 { "brs", 0, 0, 0, 0 },
5156 { "brb", 0, 0, 0, 0 },
5157 { "brl", 0, 0, 0, 0 },
5158 { "brw", 0, 0, 0, 0 },
5160 { "c", 0, 0, 0, 0 },
5161 { "cex", 0, 0, 0, 0 },
5162 { "case", 0, &symbols_case_sensitive, 1, 0 },
5163 { "cl", 0, 0, 0, 0 },
5164 { "cre", 0, 0, 0, 0 },
5165 { "d", 0, &flag_keep_locals, 1, 0 },
5166 { "e", 0, 0, 0, 0 },
5167 { "f", 0, &flag_short_refs, 1, 0 },
5168 { "frs", 0, &flag_short_refs, 1, 0 },
5169 { "frl", 0, &flag_short_refs, 0, 1 },
5170 { "g", 0, 0, 0, 0 },
5171 { "i", 0, 0, 0, 0 },
5172 { "m", 0, 0, 0, 0 },
5173 { "mex", 0, 0, 0, 0 },
5174 { "mc", 0, 0, 0, 0 },
5175 { "md", 0, 0, 0, 0 },
5176 { "nest", opt_nest, 0, 0, 0 },
5177 { "next", skip_to_comma, 0, 0, 0 },
5178 { "o", 0, 0, 0, 0 },
5179 { "old", 0, 0, 0, 0 },
5180 { "op", skip_to_comma, 0, 0, 0 },
5181 { "pco", 0, 0, 0, 0 },
5182 { "p", opt_chip, 0, 0, 0 },
5183 { "pcr", 0, 0, 0, 0 },
5184 { "pcs", 0, 0, 0, 0 },
5185 { "r", 0, 0, 0, 0 },
5186 { "quick", 0, &m68k_quick, 1, 0 },
5187 { "rel32", 0, &m68k_rel32, 1, 0 },
5188 { "s", opt_list, 0, 0, 0 },
5189 { "t", opt_list_symbols, 0, 0, 0 },
5190 { "w", 0, &flag_no_warnings, 0, 1 },
5194 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5196 /* The MRI OPT pseudo-op. */
5200 int ignore ATTRIBUTE_UNUSED;
5208 const struct opt_action *o;
5213 if (*input_line_pointer == '-')
5215 ++input_line_pointer;
5218 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5220 input_line_pointer += 2;
5224 s = input_line_pointer;
5225 c = get_symbol_end ();
5227 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5229 if (strcasecmp (s, o->name) == 0)
5233 /* Restore input_line_pointer now in case the option
5235 *input_line_pointer = c;
5236 (*o->pfn) (o->arg, t);
5238 else if (o->pvar != NULL)
5240 if (! t && o->arg == o->notarg)
5241 as_bad (_("option `%s' may not be negated"), s);
5242 *input_line_pointer = c;
5243 *o->pvar = t ? o->arg : o->notarg;
5246 *input_line_pointer = c;
5252 as_bad (_("option `%s' not recognized"), s);
5253 *input_line_pointer = c;
5256 while (*input_line_pointer++ == ',');
5258 /* Move back to terminating character. */
5259 --input_line_pointer;
5260 demand_empty_rest_of_line ();
5263 /* Skip ahead to a comma. This is used for OPT options which we do
5264 not suppor tand which take arguments. */
5267 skip_to_comma (arg, on)
5268 int arg ATTRIBUTE_UNUSED;
5269 int on ATTRIBUTE_UNUSED;
5271 while (*input_line_pointer != ','
5272 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5273 ++input_line_pointer;
5276 /* Handle the OPT NEST=depth option. */
5280 int arg ATTRIBUTE_UNUSED;
5281 int on ATTRIBUTE_UNUSED;
5283 if (*input_line_pointer != '=')
5285 as_bad (_("bad format of OPT NEST=depth"));
5289 ++input_line_pointer;
5290 max_macro_nest = get_absolute_expression ();
5293 /* Handle the OPT P=chip option. */
5297 int arg ATTRIBUTE_UNUSED;
5298 int on ATTRIBUTE_UNUSED;
5300 if (*input_line_pointer != '=')
5302 /* This is just OPT P, which we do not support. */
5306 ++input_line_pointer;
5310 /* Handle the OPT S option. */
5314 int arg ATTRIBUTE_UNUSED;
5320 /* Handle the OPT T option. */
5323 opt_list_symbols (arg, on)
5324 int arg ATTRIBUTE_UNUSED;
5328 listing |= LISTING_SYMBOLS;
5330 listing &= ~LISTING_SYMBOLS;
5333 /* Handle the MRI REG pseudo-op. */
5337 int ignore ATTRIBUTE_UNUSED;
5346 if (line_label == NULL)
5348 as_bad (_("missing label"));
5349 ignore_rest_of_line ();
5354 stop = mri_comment_field (&stopc);
5358 s = input_line_pointer;
5359 while (ISALNUM (*input_line_pointer)
5360 #ifdef REGISTER_PREFIX
5361 || *input_line_pointer == REGISTER_PREFIX
5363 || *input_line_pointer == '/'
5364 || *input_line_pointer == '-')
5365 ++input_line_pointer;
5366 c = *input_line_pointer;
5367 *input_line_pointer = '\0';
5369 if (m68k_ip_op (s, &rop) != 0)
5371 if (rop.error == NULL)
5372 as_bad (_("bad register list"));
5374 as_bad (_("bad register list: %s"), rop.error);
5375 *input_line_pointer = c;
5376 ignore_rest_of_line ();
5380 *input_line_pointer = c;
5382 if (rop.mode == REGLST)
5384 else if (rop.mode == DREG)
5385 mask = 1 << (rop.reg - DATA0);
5386 else if (rop.mode == AREG)
5387 mask = 1 << (rop.reg - ADDR0 + 8);
5388 else if (rop.mode == FPREG)
5389 mask = 1 << (rop.reg - FP0 + 16);
5390 else if (rop.mode == CONTROL
5393 else if (rop.mode == CONTROL
5396 else if (rop.mode == CONTROL
5401 as_bad (_("bad register list"));
5402 ignore_rest_of_line ();
5406 S_SET_SEGMENT (line_label, reg_section);
5407 S_SET_VALUE (line_label, ~mask);
5408 symbol_set_frag (line_label, &zero_address_frag);
5411 mri_comment_end (stop, stopc);
5413 demand_empty_rest_of_line ();
5416 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5420 struct save_opts *next;
5422 int symbols_case_sensitive;
5430 /* FIXME: We don't save OPT S. */
5433 /* This variable holds the stack of saved options. */
5435 static struct save_opts *save_stack;
5437 /* The MRI SAVE pseudo-op. */
5441 int ignore ATTRIBUTE_UNUSED;
5443 struct save_opts *s;
5445 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5446 s->abspcadd = m68k_abspcadd;
5447 s->symbols_case_sensitive = symbols_case_sensitive;
5448 s->keep_locals = flag_keep_locals;
5449 s->short_refs = flag_short_refs;
5450 s->architecture = current_architecture;
5451 s->quick = m68k_quick;
5452 s->rel32 = m68k_rel32;
5453 s->listing = listing;
5454 s->no_warnings = flag_no_warnings;
5456 s->next = save_stack;
5459 demand_empty_rest_of_line ();
5462 /* The MRI RESTORE pseudo-op. */
5466 int ignore ATTRIBUTE_UNUSED;
5468 struct save_opts *s;
5470 if (save_stack == NULL)
5472 as_bad (_("restore without save"));
5473 ignore_rest_of_line ();
5478 save_stack = s->next;
5480 m68k_abspcadd = s->abspcadd;
5481 symbols_case_sensitive = s->symbols_case_sensitive;
5482 flag_keep_locals = s->keep_locals;
5483 flag_short_refs = s->short_refs;
5484 current_architecture = s->architecture;
5485 m68k_quick = s->quick;
5486 m68k_rel32 = s->rel32;
5487 listing = s->listing;
5488 flag_no_warnings = s->no_warnings;
5492 demand_empty_rest_of_line ();
5495 /* Types of MRI structured control directives. */
5497 enum mri_control_type
5505 /* This structure is used to stack the MRI structured control
5508 struct mri_control_info
5510 /* The directive within which this one is enclosed. */
5511 struct mri_control_info *outer;
5513 /* The type of directive. */
5514 enum mri_control_type type;
5516 /* Whether an ELSE has been in an IF. */
5519 /* The add or sub statement at the end of a FOR. */
5522 /* The label of the top of a FOR or REPEAT loop. */
5525 /* The label to jump to for the next iteration, or the else
5526 expression of a conditional. */
5529 /* The label to jump to to break out of the loop, or the label past
5530 the end of a conditional. */
5534 /* The stack of MRI structured control directives. */
5536 static struct mri_control_info *mri_control_stack;
5538 /* The current MRI structured control directive index number, used to
5539 generate label names. */
5541 static int mri_control_index;
5543 /* Some function prototypes. */
5545 static void mri_assemble PARAMS ((char *));
5546 static char *mri_control_label PARAMS ((void));
5547 static struct mri_control_info *push_mri_control
5548 PARAMS ((enum mri_control_type));
5549 static void pop_mri_control PARAMS ((void));
5550 static int parse_mri_condition PARAMS ((int *));
5551 static int parse_mri_control_operand
5552 PARAMS ((int *, char **, char **, char **, char **));
5553 static int swap_mri_condition PARAMS ((int));
5554 static int reverse_mri_condition PARAMS ((int));
5555 static void build_mri_control_operand
5556 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5557 const char *, int));
5558 static void parse_mri_control_expression
5559 PARAMS ((char *, int, const char *, const char *, int));
5561 /* Assemble an instruction for an MRI structured control directive. */
5569 /* md_assemble expects the opcode to be in lower case. */
5570 for (s = str; *s != ' ' && *s != '\0'; s++)
5576 /* Generate a new MRI label structured control directive label name. */
5579 mri_control_label ()
5583 n = (char *) xmalloc (20);
5584 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5585 ++mri_control_index;
5589 /* Create a new MRI structured control directive. */
5591 static struct mri_control_info *
5592 push_mri_control (type)
5593 enum mri_control_type type;
5595 struct mri_control_info *n;
5597 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5601 if (type == mri_if || type == mri_while)
5604 n->top = mri_control_label ();
5605 n->next = mri_control_label ();
5606 n->bottom = mri_control_label ();
5608 n->outer = mri_control_stack;
5609 mri_control_stack = n;
5614 /* Pop off the stack of MRI structured control directives. */
5619 struct mri_control_info *n;
5621 n = mri_control_stack;
5622 mri_control_stack = n->outer;
5630 /* Recognize a condition code in an MRI structured control expression. */
5633 parse_mri_condition (pcc)
5638 know (*input_line_pointer == '<');
5640 ++input_line_pointer;
5641 c1 = *input_line_pointer++;
5642 c2 = *input_line_pointer++;
5644 if (*input_line_pointer != '>')
5646 as_bad (_("syntax error in structured control directive"));
5650 ++input_line_pointer;
5656 *pcc = (c1 << 8) | c2;
5661 /* Parse a single operand in an MRI structured control expression. */
5664 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5681 if (*input_line_pointer == '<')
5683 /* It's just a condition code. */
5684 return parse_mri_condition (pcc);
5687 /* Look ahead for the condition code. */
5688 for (s = input_line_pointer; *s != '\0'; ++s)
5690 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5695 as_bad (_("missing condition code in structured control directive"));
5699 *leftstart = input_line_pointer;
5701 if (*leftstop > *leftstart
5702 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5705 input_line_pointer = s;
5706 if (! parse_mri_condition (pcc))
5709 /* Look ahead for AND or OR or end of line. */
5710 for (s = input_line_pointer; *s != '\0'; ++s)
5712 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5713 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5715 if ((s == input_line_pointer
5718 && ((strncasecmp (s, "AND", 3) == 0
5719 && (s[3] == '.' || ! is_part_of_name (s[3])))
5720 || (strncasecmp (s, "OR", 2) == 0
5721 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5725 *rightstart = input_line_pointer;
5727 if (*rightstop > *rightstart
5728 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5731 input_line_pointer = s;
5736 #define MCC(b1, b2) (((b1) << 8) | (b2))
5738 /* Swap the sense of a condition. This changes the condition so that
5739 it generates the same result when the operands are swapped. */
5742 swap_mri_condition (cc)
5747 case MCC ('h', 'i'): return MCC ('c', 's');
5748 case MCC ('l', 's'): return MCC ('c', 'c');
5749 /* <HS> is an alias for <CC>. */
5750 case MCC ('h', 's'):
5751 case MCC ('c', 'c'): return MCC ('l', 's');
5752 /* <LO> is an alias for <CS>. */
5753 case MCC ('l', 'o'):
5754 case MCC ('c', 's'): return MCC ('h', 'i');
5755 case MCC ('p', 'l'): return MCC ('m', 'i');
5756 case MCC ('m', 'i'): return MCC ('p', 'l');
5757 case MCC ('g', 'e'): return MCC ('l', 'e');
5758 case MCC ('l', 't'): return MCC ('g', 't');
5759 case MCC ('g', 't'): return MCC ('l', 't');
5760 case MCC ('l', 'e'): return MCC ('g', 'e');
5761 /* Issue a warning for conditions we can not swap. */
5762 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5763 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5764 case MCC ('v', 'c'):
5765 case MCC ('v', 's'):
5767 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5768 (char) (cc >> 8), (char) (cc));
5774 /* Reverse the sense of a condition. */
5777 reverse_mri_condition (cc)
5782 case MCC ('h', 'i'): return MCC ('l', 's');
5783 case MCC ('l', 's'): return MCC ('h', 'i');
5784 /* <HS> is an alias for <CC> */
5785 case MCC ('h', 's'): return MCC ('l', 'o');
5786 case MCC ('c', 'c'): return MCC ('c', 's');
5787 /* <LO> is an alias for <CS> */
5788 case MCC ('l', 'o'): return MCC ('h', 's');
5789 case MCC ('c', 's'): return MCC ('c', 'c');
5790 case MCC ('n', 'e'): return MCC ('e', 'q');
5791 case MCC ('e', 'q'): return MCC ('n', 'e');
5792 case MCC ('v', 'c'): return MCC ('v', 's');
5793 case MCC ('v', 's'): return MCC ('v', 'c');
5794 case MCC ('p', 'l'): return MCC ('m', 'i');
5795 case MCC ('m', 'i'): return MCC ('p', 'l');
5796 case MCC ('g', 'e'): return MCC ('l', 't');
5797 case MCC ('l', 't'): return MCC ('g', 'e');
5798 case MCC ('g', 't'): return MCC ('l', 'e');
5799 case MCC ('l', 'e'): return MCC ('g', 't');
5804 /* Build an MRI structured control expression. This generates test
5805 and branch instructions. It goes to TRUELAB if the condition is
5806 true, and to FALSELAB if the condition is false. Exactly one of
5807 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5808 is the size qualifier for the expression. EXTENT is the size to
5809 use for the branch. */
5812 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5813 rightstop, truelab, falselab, extent)
5820 const char *truelab;
5821 const char *falselab;
5827 if (leftstart != NULL)
5829 struct m68k_op leftop, rightop;
5832 /* Swap the compare operands, if necessary, to produce a legal
5833 m68k compare instruction. Comparing a register operand with
5834 a non-register operand requires the register to be on the
5835 right (cmp, cmpa). Comparing an immediate value with
5836 anything requires the immediate value to be on the left
5841 (void) m68k_ip_op (leftstart, &leftop);
5846 (void) m68k_ip_op (rightstart, &rightop);
5849 if (rightop.mode == IMMED
5850 || ((leftop.mode == DREG || leftop.mode == AREG)
5851 && (rightop.mode != DREG && rightop.mode != AREG)))
5855 /* Correct conditional handling:
5856 if #1 <lt> d0 then ;means if (1 < d0)
5862 cmp #1,d0 if we do *not* swap the operands
5863 bgt true we need the swapped condition!
5870 leftstart = rightstart;
5873 leftstop = rightstop;
5878 cc = swap_mri_condition (cc);
5882 if (truelab == NULL)
5884 cc = reverse_mri_condition (cc);
5888 if (leftstart != NULL)
5890 buf = (char *) xmalloc (20
5891 + (leftstop - leftstart)
5892 + (rightstop - rightstart));
5898 *s++ = TOLOWER (qual);
5900 memcpy (s, leftstart, leftstop - leftstart);
5901 s += leftstop - leftstart;
5903 memcpy (s, rightstart, rightstop - rightstart);
5904 s += rightstop - rightstart;
5910 buf = (char *) xmalloc (20 + strlen (truelab));
5916 *s++ = TOLOWER (extent);
5918 strcpy (s, truelab);
5923 /* Parse an MRI structured control expression. This generates test
5924 and branch instructions. STOP is where the expression ends. It
5925 goes to TRUELAB if the condition is true, and to FALSELAB if the
5926 condition is false. Exactly one of TRUELAB and FALSELAB will be
5927 NULL, meaning to fall through. QUAL is the size qualifier for the
5928 expression. EXTENT is the size to use for the branch. */
5931 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5934 const char *truelab;
5935 const char *falselab;
5948 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5949 &rightstart, &rightstop))
5955 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5959 if (falselab != NULL)
5962 flab = mri_control_label ();
5964 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5965 rightstop, (const char *) NULL, flab, extent);
5967 input_line_pointer += 3;
5968 if (*input_line_pointer != '.'
5969 || input_line_pointer[1] == '\0')
5973 qual = input_line_pointer[1];
5974 input_line_pointer += 2;
5977 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5978 &rightstart, &rightstop))
5984 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5985 rightstop, truelab, falselab, extent);
5987 if (falselab == NULL)
5990 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5994 if (truelab != NULL)
5997 tlab = mri_control_label ();
5999 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6000 rightstop, tlab, (const char *) NULL, extent);
6002 input_line_pointer += 2;
6003 if (*input_line_pointer != '.'
6004 || input_line_pointer[1] == '\0')
6008 qual = input_line_pointer[1];
6009 input_line_pointer += 2;
6012 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6013 &rightstart, &rightstop))
6019 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6020 rightstop, truelab, falselab, extent);
6022 if (truelab == NULL)
6027 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6028 rightstop, truelab, falselab, extent);
6032 if (input_line_pointer != stop)
6033 as_bad (_("syntax error in structured control directive"));
6036 /* Handle the MRI IF pseudo-op. This may be a structured control
6037 directive, or it may be a regular assembler conditional, depending
6046 struct mri_control_info *n;
6048 /* A structured control directive must end with THEN with an
6049 optional qualifier. */
6050 s = input_line_pointer;
6051 /* We only accept '*' as introduction of comments if preceded by white space
6052 or at first column of a line (I think this can't actually happen here?)
6053 This is important when assembling:
6054 if d0 <ne> 12(a0,d0*2) then
6055 if d0 <ne> #CONST*20 then. */
6056 while ( ! ( is_end_of_line[(unsigned char) *s]
6059 && ( s == input_line_pointer
6061 || *(s-1) == '\t'))))
6064 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6067 if (s - input_line_pointer > 1
6071 if (s - input_line_pointer < 3
6072 || strncasecmp (s - 3, "THEN", 4) != 0)
6076 as_bad (_("missing then"));
6077 ignore_rest_of_line ();
6081 /* It's a conditional. */
6086 /* Since this might be a conditional if, this pseudo-op will be
6087 called even if we are supported to be ignoring input. Double
6088 check now. Clobber *input_line_pointer so that ignore_input
6089 thinks that this is not a special pseudo-op. */
6090 c = *input_line_pointer;
6091 *input_line_pointer = 0;
6092 if (ignore_input ())
6094 *input_line_pointer = c;
6095 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6096 ++input_line_pointer;
6097 demand_empty_rest_of_line ();
6100 *input_line_pointer = c;
6102 n = push_mri_control (mri_if);
6104 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6105 n->next, s[1] == '.' ? s[2] : '\0');
6108 input_line_pointer = s + 3;
6110 input_line_pointer = s + 1;
6114 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6115 ++input_line_pointer;
6118 demand_empty_rest_of_line ();
6121 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6122 structured IF, associate the ELSE with the IF. Otherwise, assume
6123 it is a conditional else. */
6134 && (mri_control_stack == NULL
6135 || mri_control_stack->type != mri_if
6136 || mri_control_stack->else_seen))
6142 c = *input_line_pointer;
6143 *input_line_pointer = 0;
6144 if (ignore_input ())
6146 *input_line_pointer = c;
6147 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6148 ++input_line_pointer;
6149 demand_empty_rest_of_line ();
6152 *input_line_pointer = c;
6154 if (mri_control_stack == NULL
6155 || mri_control_stack->type != mri_if
6156 || mri_control_stack->else_seen)
6158 as_bad (_("else without matching if"));
6159 ignore_rest_of_line ();
6163 mri_control_stack->else_seen = 1;
6165 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6166 q[0] = TOLOWER (qual);
6168 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6172 colon (mri_control_stack->next);
6176 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6177 ++input_line_pointer;
6180 demand_empty_rest_of_line ();
6183 /* Handle the MRI ENDI pseudo-op. */
6187 int ignore ATTRIBUTE_UNUSED;
6189 if (mri_control_stack == NULL
6190 || mri_control_stack->type != mri_if)
6192 as_bad (_("endi without matching if"));
6193 ignore_rest_of_line ();
6197 /* ignore_input will not return true for ENDI, so we don't need to
6198 worry about checking it again here. */
6200 if (! mri_control_stack->else_seen)
6201 colon (mri_control_stack->next);
6202 colon (mri_control_stack->bottom);
6208 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6209 ++input_line_pointer;
6212 demand_empty_rest_of_line ();
6215 /* Handle the MRI BREAK pseudo-op. */
6218 s_mri_break (extent)
6221 struct mri_control_info *n;
6225 n = mri_control_stack;
6227 && n->type != mri_for
6228 && n->type != mri_repeat
6229 && n->type != mri_while)
6233 as_bad (_("break outside of structured loop"));
6234 ignore_rest_of_line ();
6238 buf = (char *) xmalloc (20 + strlen (n->bottom));
6239 ex[0] = TOLOWER (extent);
6241 sprintf (buf, "bra%s %s", ex, n->bottom);
6247 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6248 ++input_line_pointer;
6251 demand_empty_rest_of_line ();
6254 /* Handle the MRI NEXT pseudo-op. */
6260 struct mri_control_info *n;
6264 n = mri_control_stack;
6266 && n->type != mri_for
6267 && n->type != mri_repeat
6268 && n->type != mri_while)
6272 as_bad (_("next outside of structured loop"));
6273 ignore_rest_of_line ();
6277 buf = (char *) xmalloc (20 + strlen (n->next));
6278 ex[0] = TOLOWER (extent);
6280 sprintf (buf, "bra%s %s", ex, n->next);
6286 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6287 ++input_line_pointer;
6290 demand_empty_rest_of_line ();
6293 /* Handle the MRI FOR pseudo-op. */
6299 const char *varstart, *varstop;
6300 const char *initstart, *initstop;
6301 const char *endstart, *endstop;
6302 const char *bystart, *bystop;
6306 struct mri_control_info *n;
6312 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6316 varstart = input_line_pointer;
6318 /* Look for the '='. */
6319 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6320 && *input_line_pointer != '=')
6321 ++input_line_pointer;
6322 if (*input_line_pointer != '=')
6324 as_bad (_("missing ="));
6325 ignore_rest_of_line ();
6329 varstop = input_line_pointer;
6330 if (varstop > varstart
6331 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6334 ++input_line_pointer;
6336 initstart = input_line_pointer;
6338 /* Look for TO or DOWNTO. */
6341 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6343 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6344 && ! is_part_of_name (input_line_pointer[2]))
6346 initstop = input_line_pointer;
6347 input_line_pointer += 2;
6350 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6351 && ! is_part_of_name (input_line_pointer[6]))
6353 initstop = input_line_pointer;
6355 input_line_pointer += 6;
6358 ++input_line_pointer;
6360 if (initstop == NULL)
6362 as_bad (_("missing to or downto"));
6363 ignore_rest_of_line ();
6366 if (initstop > initstart
6367 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6371 endstart = input_line_pointer;
6373 /* Look for BY or DO. */
6376 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6378 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6379 && ! is_part_of_name (input_line_pointer[2]))
6381 endstop = input_line_pointer;
6383 input_line_pointer += 2;
6386 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6387 && (input_line_pointer[2] == '.'
6388 || ! is_part_of_name (input_line_pointer[2])))
6390 endstop = input_line_pointer;
6391 input_line_pointer += 2;
6394 ++input_line_pointer;
6396 if (endstop == NULL)
6398 as_bad (_("missing do"));
6399 ignore_rest_of_line ();
6402 if (endstop > endstart
6403 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6409 bystop = bystart + 2;
6414 bystart = input_line_pointer;
6418 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6420 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6421 && (input_line_pointer[2] == '.'
6422 || ! is_part_of_name (input_line_pointer[2])))
6424 bystop = input_line_pointer;
6425 input_line_pointer += 2;
6428 ++input_line_pointer;
6432 as_bad (_("missing do"));
6433 ignore_rest_of_line ();
6436 if (bystop > bystart
6437 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6441 if (*input_line_pointer != '.')
6445 extent = input_line_pointer[1];
6446 input_line_pointer += 2;
6449 /* We have fully parsed the FOR operands. Now build the loop. */
6450 n = push_mri_control (mri_for);
6452 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6454 /* Move init,var. */
6461 *s++ = TOLOWER (qual);
6463 memcpy (s, initstart, initstop - initstart);
6464 s += initstop - initstart;
6466 memcpy (s, varstart, varstop - varstart);
6467 s += varstop - varstart;
6479 *s++ = TOLOWER (qual);
6481 memcpy (s, endstart, endstop - endstart);
6482 s += endstop - endstart;
6484 memcpy (s, varstart, varstop - varstart);
6485 s += varstop - varstart;
6490 ex[0] = TOLOWER (extent);
6493 sprintf (buf, "blt%s %s", ex, n->bottom);
6495 sprintf (buf, "bgt%s %s", ex, n->bottom);
6498 /* Put together the add or sub instruction used by ENDF. */
6506 *s++ = TOLOWER (qual);
6508 memcpy (s, bystart, bystop - bystart);
6509 s += bystop - bystart;
6511 memcpy (s, varstart, varstop - varstart);
6512 s += varstop - varstart;
6518 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6519 ++input_line_pointer;
6522 demand_empty_rest_of_line ();
6525 /* Handle the MRI ENDF pseudo-op. */
6529 int ignore ATTRIBUTE_UNUSED;
6531 if (mri_control_stack == NULL
6532 || mri_control_stack->type != mri_for)
6534 as_bad (_("endf without for"));
6535 ignore_rest_of_line ();
6539 colon (mri_control_stack->next);
6541 mri_assemble (mri_control_stack->incr);
6543 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6544 mri_assemble (mri_control_stack->incr);
6546 free (mri_control_stack->incr);
6548 colon (mri_control_stack->bottom);
6554 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6555 ++input_line_pointer;
6558 demand_empty_rest_of_line ();
6561 /* Handle the MRI REPEAT pseudo-op. */
6564 s_mri_repeat (ignore)
6565 int ignore ATTRIBUTE_UNUSED;
6567 struct mri_control_info *n;
6569 n = push_mri_control (mri_repeat);
6573 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6574 ++input_line_pointer;
6576 demand_empty_rest_of_line ();
6579 /* Handle the MRI UNTIL pseudo-op. */
6587 if (mri_control_stack == NULL
6588 || mri_control_stack->type != mri_repeat)
6590 as_bad (_("until without repeat"));
6591 ignore_rest_of_line ();
6595 colon (mri_control_stack->next);
6597 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6600 parse_mri_control_expression (s, qual, (const char *) NULL,
6601 mri_control_stack->top, '\0');
6603 colon (mri_control_stack->bottom);
6605 input_line_pointer = s;
6611 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6612 ++input_line_pointer;
6615 demand_empty_rest_of_line ();
6618 /* Handle the MRI WHILE pseudo-op. */
6626 struct mri_control_info *n;
6628 s = input_line_pointer;
6629 /* We only accept '*' as introduction of comments if preceded by white space
6630 or at first column of a line (I think this can't actually happen here?)
6631 This is important when assembling:
6632 while d0 <ne> 12(a0,d0*2) do
6633 while d0 <ne> #CONST*20 do. */
6634 while (! (is_end_of_line[(unsigned char) *s]
6637 && (s == input_line_pointer
6639 || *(s-1) == '\t'))))
6642 while (*s == ' ' || *s == '\t')
6644 if (s - input_line_pointer > 1
6647 if (s - input_line_pointer < 2
6648 || strncasecmp (s - 1, "DO", 2) != 0)
6650 as_bad (_("missing do"));
6651 ignore_rest_of_line ();
6655 n = push_mri_control (mri_while);
6659 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6660 s[1] == '.' ? s[2] : '\0');
6662 input_line_pointer = s + 1;
6663 if (*input_line_pointer == '.')
6664 input_line_pointer += 2;
6668 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6669 ++input_line_pointer;
6672 demand_empty_rest_of_line ();
6675 /* Handle the MRI ENDW pseudo-op. */
6679 int ignore ATTRIBUTE_UNUSED;
6683 if (mri_control_stack == NULL
6684 || mri_control_stack->type != mri_while)
6686 as_bad (_("endw without while"));
6687 ignore_rest_of_line ();
6691 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6692 sprintf (buf, "bra %s", mri_control_stack->next);
6696 colon (mri_control_stack->bottom);
6702 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6703 ++input_line_pointer;
6706 demand_empty_rest_of_line ();
6711 * Invocation line includes a switch not recognized by the base assembler.
6712 * See if it's a processor-specific option. These are:
6714 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6715 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6716 * Select the architecture. Instructions or features not
6717 * supported by the selected architecture cause fatal
6718 * errors. More than one may be specified. The default is
6719 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6720 * for -m68000, and -m68882 is a synonym for -m68881.
6721 * -[A]m[c]no-68851, -[A]m[c]no-68881
6722 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6723 * so don't use or document it, but that's the way the parsing
6726 * -pic Indicates PIC.
6727 * -k Indicates PIC. (Sun 3 only.)
6728 * --pcrel Never turn PC-relative branches into absolute jumps.
6731 * Permit `|' to be used in expressions.
6736 const char *md_shortopts = "lSA:m:kQ:V";
6738 const char *md_shortopts = "lSA:m:k";
6741 struct option md_longopts[] = {
6742 #define OPTION_PIC (OPTION_MD_BASE)
6743 {"pic", no_argument, NULL, OPTION_PIC},
6744 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6745 {"register-prefix-optional", no_argument, NULL,
6746 OPTION_REGISTER_PREFIX_OPTIONAL},
6747 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6748 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6749 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6750 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6751 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6752 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6753 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6754 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6755 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6756 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6757 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6758 {"pcrel", no_argument, NULL, OPTION_PCREL},
6759 {NULL, no_argument, NULL, 0}
6761 size_t md_longopts_size = sizeof (md_longopts);
6764 md_parse_option (c, arg)
6770 case 'l': /* -l means keep external to 2 bit offset
6771 rather than 16 bit one. */
6772 flag_short_refs = 1;
6775 case 'S': /* -S means that jbsr's always turn into
6777 flag_long_jumps = 1;
6780 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6781 branches into absolute jumps. */
6782 flag_keep_pcrel = 1;
6788 /* Intentional fall-through. */
6791 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6795 const char *oarg = arg;
6801 if (arg[0] == 'c' && arg[1] == '6')
6804 for (i = 0; i < n_archs; i++)
6805 if (!strcmp (arg, archs[i].name))
6810 as_bad (_("unrecognized option `%s'"), oarg);
6813 arch = archs[i].arch;
6816 else if (arch == m68851)
6825 if (arg[0] == 'c' && arg[1] == '6')
6828 for (i = 0; i < n_archs; i++)
6829 if (!strcmp (arg, archs[i].name))
6831 unsigned long arch = archs[i].arch;
6832 if (cpu_of_arch (arch))
6833 /* It's a cpu spec. */
6835 current_architecture &= ~m68000up;
6836 current_architecture |= arch;
6838 else if (arch == m68881)
6840 current_architecture |= m68881;
6843 else if (arch == m68851)
6845 current_architecture |= m68851;
6855 as_bad (_("unrecognized architecture specification `%s'"), arg);
6864 break; /* -pic, Position Independent Code. */
6866 case OPTION_REGISTER_PREFIX_OPTIONAL:
6867 flag_reg_prefix_optional = 1;
6868 reg_prefix_optional_seen = 1;
6871 /* -V: SVR4 argument to print version ID. */
6873 print_version_id ();
6876 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6877 should be emitted or not. FIXME: Not implemented. */
6881 case OPTION_BITWISE_OR:
6886 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6888 for (s = m68k_comment_chars; *s != '\0'; s++)
6892 m68k_comment_chars = n;
6896 case OPTION_BASE_SIZE_DEFAULT_16:
6897 m68k_index_width_default = SIZE_WORD;
6900 case OPTION_BASE_SIZE_DEFAULT_32:
6901 m68k_index_width_default = SIZE_LONG;
6904 case OPTION_DISP_SIZE_DEFAULT_16:
6906 m68k_rel32_from_cmdline = 1;
6909 case OPTION_DISP_SIZE_DEFAULT_32:
6911 m68k_rel32_from_cmdline = 1;
6922 md_show_usage (stream)
6925 const char *default_cpu = TARGET_CPU;
6927 unsigned int default_arch;
6929 /* Get the canonical name for the default target CPU. */
6930 if (*default_cpu == 'm')
6932 for (i = 0; i < n_archs; i++)
6934 if (strcasecmp (default_cpu, archs[i].name) == 0)
6936 default_arch = archs[i].arch;
6937 for (i = 0; i < n_archs; i++)
6939 if (archs[i].arch == default_arch
6942 default_cpu = archs[i].name;
6949 fprintf (stream, _("\
6951 -l use 1 word for refs to undefined symbols [default 2]\n\
6952 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
6953 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6954 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
6955 specify variant of 680X0 architecture [default %s]\n\
6956 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6957 target has/lacks floating-point coprocessor\n\
6958 [default yes for 68020, 68030, and cpu32]\n"),
6960 fprintf (stream, _("\
6961 -m68851 | -mno-68851\n\
6962 target has/lacks memory-management unit coprocessor\n\
6963 [default yes for 68020 and up]\n\
6964 -pic, -k generate position independent code\n\
6965 -S turn jbsr into jsr\n\
6966 --pcrel never turn PC-relative branches into absolute jumps\n\
6967 --register-prefix-optional\n\
6968 recognize register names without prefix character\n\
6969 --bitwise-or do not treat `|' as a comment character\n"));
6970 fprintf (stream, _("\
6971 --base-size-default-16 base reg without size is 16 bits\n\
6972 --base-size-default-32 base reg without size is 32 bits (default)\n\
6973 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6974 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6979 /* TEST2: Test md_assemble() */
6980 /* Warning, this routine probably doesn't work anymore. */
6984 struct m68k_it the_ins;
6992 if (!gets (buf) || !*buf)
6994 if (buf[0] == '|' || buf[1] == '.')
6996 for (cp = buf; *cp; cp++)
7001 memset (&the_ins, '\0', sizeof (the_ins));
7002 m68k_ip (&the_ins, buf);
7005 printf (_("Error %s in %s\n"), the_ins.error, buf);
7009 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7010 for (n = 0; n < the_ins.numo; n++)
7011 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7013 print_the_insn (&the_ins.opcode[0], stdout);
7014 (void) putchar ('\n');
7016 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7018 if (the_ins.operands[n].error)
7020 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7023 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7024 if (the_ins.operands[n].b_const)
7025 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7026 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7027 if (the_ins.operands[n].b_iadd)
7028 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7029 (void) putchar ('\n');
7041 while (*str && *str != ' ')
7043 if (str[-1] == ':' || str[1] == '=')
7050 /* Possible states for relaxation:
7052 0 0 branch offset byte (bra, etc)
7056 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7060 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7067 /* We have no need to default values of symbols. */
7070 md_undefined_symbol (name)
7071 char *name ATTRIBUTE_UNUSED;
7076 /* Round up a section size to the appropriate boundary. */
7078 md_section_align (segment, size)
7079 segT segment ATTRIBUTE_UNUSED;
7083 #ifdef BFD_ASSEMBLER
7084 /* For a.out, force the section size to be aligned. If we don't do
7085 this, BFD will align it for us, but it will not write out the
7086 final bytes of the section. This may be a bug in BFD, but it is
7087 easier to fix it here since that is how the other a.out targets
7091 align = bfd_get_section_alignment (stdoutput, segment);
7092 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7099 /* Exactly what point is a PC-relative offset relative TO?
7100 On the 68k, it is relative to the address of the first extension
7101 word. The difference between the addresses of the offset and the
7102 first extension word is stored in fx_pcrel_adjust. */
7104 md_pcrel_from (fixP)
7109 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7110 sign extend the value here. */
7111 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7114 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7117 #ifndef BFD_ASSEMBLER
7121 tc_coff_symbol_emit_hook (ignore)
7122 symbolS *ignore ATTRIBUTE_UNUSED;
7127 tc_coff_sizemachdep (frag)
7130 switch (frag->fr_subtype & 0x3)
7148 m68k_elf_final_processing ()
7150 /* Set file-specific flags if this is a cpu32 processor. */
7151 if (cpu_of_arch (current_architecture) & cpu32)
7152 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7153 else if ((cpu_of_arch (current_architecture) & m68000up)
7154 && !(cpu_of_arch (current_architecture) & m68020up))
7155 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
7160 tc_m68k_regname_to_dw2regnum (const char *regname)
7162 unsigned int regnum;
7163 static const char *const regnames[] =
7165 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7166 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7167 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7171 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7172 if (strcmp (regname, regnames[regnum]) == 0)
7179 tc_m68k_frame_initial_instructions (void)
7181 static int sp_regno = -1;
7184 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7186 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7187 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);