1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if defined (TE_SVR4) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
37 const char *m68k_comment_chars = "|";
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#*";
49 const char line_separator_chars[] = "";
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
63 const int md_reloc_size = 8; /* Size of relocation record */
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
77 int flag_reg_prefix_optional;
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
97 static int m68k_rel32 = 1;
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
102 /* The default width to use for an index register when using a base
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
112 struct label_line *next;
119 /* The list of labels. */
121 static struct label_line *labels;
123 /* The current label. */
125 static struct label_line *current_label;
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
138 /* Case `g' except when BCC68000 is applicable. */
140 /* Coprocessor branches. */
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
154 /* Not currently used? */
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
162 const char *m_operands;
163 unsigned long m_opcode;
167 struct m68k_incant *m_next;
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
197 #define cpu32_control_regs m68010_control_regs
199 static const enum m68k_register *control_regs;
201 /* internal form of a 68020 instruction */
205 const char *args; /* list of opcode info */
208 int numo; /* Number of shorts in opcode */
211 struct m68k_op operands[6];
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
216 int nfrag; /* Number of frags we have to produce */
219 int fragoff; /* Where in the current opcode the frag ends */
226 int nrel; /* Num of reloc strucs in use */
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
242 /* Whether this expression needs special pic relocation, and if
244 enum pic_relocation pic_reloc;
247 reloc[5]; /* Five is enough??? */
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
254 /* Macros for determining if cpu supports a specific addressing mode */
255 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
257 static struct m68k_it the_ins; /* the instruction being assembled */
259 #define op(ex) ((ex)->exp.X_op)
260 #define adds(ex) ((ex)->exp.X_add_symbol)
261 #define subs(ex) ((ex)->exp.X_op_symbol)
262 #define offs(ex) ((ex)->exp.X_add_number)
264 /* Macros for adding things to the m68k_it struct */
266 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
268 /* Static functions. */
270 static void insop PARAMS ((int, const struct m68k_incant *));
271 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
272 static void add_frag PARAMS ((symbolS *, offsetT, int));
274 /* Like addword, but goes BEFORE general operands */
278 const struct m68k_incant *opcode;
281 for(z=the_ins.numo;z>opcode->m_codenum;--z)
282 the_ins.opcode[z]=the_ins.opcode[z-1];
283 for(z=0;z<the_ins.nrel;z++)
284 the_ins.reloc[z].n+=2;
285 for (z = 0; z < the_ins.nfrag; z++)
286 the_ins.fragb[z].fragoff++;
287 the_ins.opcode[opcode->m_codenum]=w;
291 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
294 add_fix (width, exp, pc_rel, pc_fix)
296 struct m68k_exp *exp;
300 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
304 : (the_ins.numo*2)));
305 the_ins.reloc[the_ins.nrel].exp = exp->exp;
306 the_ins.reloc[the_ins.nrel].wid = width;
307 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
309 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
311 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
314 /* Cause an extra frag to be generated here, inserting up to 10 bytes
315 (that value is chosen in the frag_var call in md_assemble). TYPE
316 is the subtype of the frag to be generated; its primary type is
317 rs_machine_dependent.
319 The TYPE parameter is also used by md_convert_frag_1 and
320 md_estimate_size_before_relax. The appropriate type of fixup will
321 be emitted by md_convert_frag_1.
323 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
325 add_frag (add, off, type)
330 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
331 the_ins.fragb[the_ins.nfrag].fadd=add;
332 the_ins.fragb[the_ins.nfrag].foff=off;
333 the_ins.fragb[the_ins.nfrag++].fragty=type;
337 (op (ex) != O_constant && op (ex) != O_big)
339 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
340 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
341 static void m68k_ip PARAMS ((char *));
342 static void insert_reg PARAMS ((const char *, int));
343 static void select_control_regs PARAMS ((void));
344 static void init_regtable PARAMS ((void));
345 static int reverse_16_bits PARAMS ((int in));
346 static int reverse_8_bits PARAMS ((int in));
347 static void install_gen_operand PARAMS ((int mode, int val));
348 static void install_operand PARAMS ((int mode, int val));
349 static void s_bss PARAMS ((int));
350 static void s_data1 PARAMS ((int));
351 static void s_data2 PARAMS ((int));
352 static void s_even PARAMS ((int));
353 static void s_proc PARAMS ((int));
354 static void mri_chip PARAMS ((void));
355 static void s_chip PARAMS ((int));
356 static void s_fopt PARAMS ((int));
357 static void s_opt PARAMS ((int));
358 static void s_reg PARAMS ((int));
359 static void s_restore PARAMS ((int));
360 static void s_save PARAMS ((int));
361 static void s_mri_if PARAMS ((int));
362 static void s_mri_else PARAMS ((int));
363 static void s_mri_endi PARAMS ((int));
364 static void s_mri_break PARAMS ((int));
365 static void s_mri_next PARAMS ((int));
366 static void s_mri_for PARAMS ((int));
367 static void s_mri_endf PARAMS ((int));
368 static void s_mri_repeat PARAMS ((int));
369 static void s_mri_until PARAMS ((int));
370 static void s_mri_while PARAMS ((int));
371 static void s_mri_endw PARAMS ((int));
372 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
373 static void md_convert_frag_1 PARAMS ((fragS *));
375 static int current_architecture;
383 static const struct m68k_cpu archs[] = {
384 { m68000, "68000", 0 },
385 { m68010, "68010", 0 },
386 { m68020, "68020", 0 },
387 { m68030, "68030", 0 },
388 { m68040, "68040", 0 },
389 { m68060, "68060", 0 },
390 { cpu32, "cpu32", 0 },
391 { m68881, "68881", 0 },
392 { m68851, "68851", 0 },
393 { mcf5200, "5200", 0 },
394 /* Aliases (effectively, so far as gas is concerned) for the above
396 { m68020, "68k", 1 },
397 { m68000, "68008", 1 },
398 { m68000, "68302", 1 },
399 { m68000, "68306", 1 },
400 { m68000, "68307", 1 },
401 { m68000, "68322", 1 },
402 { m68000, "68356", 1 },
403 { m68000, "68ec000", 1 },
404 { m68000, "68hc000", 1 },
405 { m68000, "68hc001", 1 },
406 { m68020, "68ec020", 1 },
407 { m68030, "68ec030", 1 },
408 { m68040, "68ec040", 1 },
409 { m68060, "68ec060", 1 },
410 { cpu32, "68330", 1 },
411 { cpu32, "68331", 1 },
412 { cpu32, "68332", 1 },
413 { cpu32, "68333", 1 },
414 { cpu32, "68334", 1 },
415 { cpu32, "68336", 1 },
416 { cpu32, "68340", 1 },
417 { cpu32, "68341", 1 },
418 { cpu32, "68349", 1 },
419 { cpu32, "68360", 1 },
420 { m68881, "68882", 1 },
423 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
425 /* BCC68000 is for patching in an extra jmp instruction for long offsets
426 on the 68000. The 68000 doesn't support long branches with branchs */
428 /* This table desribes how you change sizes for the various types of variable
429 size expressions. This version only supports two kinds. */
431 /* Note that calls to frag_var need to specify the maximum expansion
432 needed; this is currently 10 bytes for DBCC. */
435 How far Forward this mode will reach:
436 How far Backward this mode will reach:
437 How many bytes this mode will add to the size of the frag
438 Which mode to go to if the offset won't fit in this one
440 relax_typeS md_relax_table[] =
442 {1, 1, 0, 0}, /* First entries aren't used */
443 {1, 1, 0, 0}, /* For no good reason except */
444 {1, 1, 0, 0}, /* that the VAX doesn't either */
447 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
448 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
452 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
453 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
457 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
458 {(32767), (-32768), 2, TAB (PCREL, LONG)},
462 {(127), (-128), 0, TAB (BCC68000, SHORT)},
463 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
464 {0, 0, 6, 0}, /* jmp long space */
467 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
468 {(32767), (-32768), 2, TAB (DBCC, LONG)},
469 {0, 0, 10, 0}, /* bra/jmp long space */
472 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
473 {32767, -32768, 2, TAB (PCLEA, LONG)},
477 /* For, e.g., jmp pcrel indexed. */
478 {125, -130, 0, TAB (PCINDEX, SHORT)},
479 {32765, -32770, 2, TAB (PCINDEX, LONG)},
484 /* These are the machine dependent pseudo-ops. These are included so
485 the assembler can work on the output from the SUN C compiler, which
489 /* This table describes all the machine specific pseudo-ops the assembler
490 has to support. The fields are:
491 pseudo-op name without dot
492 function to call to execute this pseudo-op
493 Integer arg to pass to the function
495 const pseudo_typeS md_pseudo_table[] =
497 {"data1", s_data1, 0},
498 {"data2", s_data2, 0},
501 {"skip", s_space, 0},
503 #if defined (TE_SUN3) || defined (OBJ_ELF)
504 {"align", s_align_bytes, 0},
507 {"swbeg", s_ignore, 0},
509 {"extend", float_cons, 'x'},
510 {"ldouble", float_cons, 'x'},
512 /* The following pseudo-ops are supported for MRI compatibility. */
514 {"comline", s_space, 1},
516 {"mask2", s_ignore, 0},
519 {"restore", s_restore, 0},
523 {"if.b", s_mri_if, 'b'},
524 {"if.w", s_mri_if, 'w'},
525 {"if.l", s_mri_if, 'l'},
526 {"else", s_mri_else, 0},
527 {"else.s", s_mri_else, 's'},
528 {"else.l", s_mri_else, 'l'},
529 {"endi", s_mri_endi, 0},
530 {"break", s_mri_break, 0},
531 {"break.s", s_mri_break, 's'},
532 {"break.l", s_mri_break, 'l'},
533 {"next", s_mri_next, 0},
534 {"next.s", s_mri_next, 's'},
535 {"next.l", s_mri_next, 'l'},
536 {"for", s_mri_for, 0},
537 {"for.b", s_mri_for, 'b'},
538 {"for.w", s_mri_for, 'w'},
539 {"for.l", s_mri_for, 'l'},
540 {"endf", s_mri_endf, 0},
541 {"repeat", s_mri_repeat, 0},
542 {"until", s_mri_until, 0},
543 {"until.b", s_mri_until, 'b'},
544 {"until.w", s_mri_until, 'w'},
545 {"until.l", s_mri_until, 'l'},
546 {"while", s_mri_while, 0},
547 {"while.b", s_mri_while, 'b'},
548 {"while.w", s_mri_while, 'w'},
549 {"while.l", s_mri_while, 'l'},
550 {"endw", s_mri_endw, 0},
556 /* The mote pseudo ops are put into the opcode table, since they
557 don't start with a . they look like opcodes to gas.
561 extern void obj_coff_section PARAMS ((int));
564 CONST pseudo_typeS mote_pseudo_table[] =
577 {"xdef", s_globl, 0},
579 {"align", s_align_bytes, 0},
581 {"align", s_align_ptwo, 0},
584 {"sect", obj_coff_section, 0},
585 {"section", obj_coff_section, 0},
590 #define issbyte(x) ((x)>=-128 && (x)<=127)
591 #define isubyte(x) ((x)>=0 && (x)<=255)
592 #define issword(x) ((x)>=-32768 && (x)<=32767)
593 #define isuword(x) ((x)>=0 && (x)<=65535)
595 #define isbyte(x) ((x)>= -255 && (x)<=255)
596 #define isword(x) ((x)>=-65536 && (x)<=65535)
597 #define islong(x) (1)
599 extern char *input_line_pointer;
601 static char mklower_table[256];
602 #define mklower(c) (mklower_table[(unsigned char)(c)])
603 static char notend_table[256];
604 static char alt_notend_table[256];
606 (! (notend_table[(unsigned char) *s] \
608 && alt_notend_table[(unsigned char) s[1]])))
610 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
612 #ifdef NO_PCREL_RELOCS
615 make_pcrel_absolute(fixP, add_number)
619 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
621 /* rewrite the PC relative instructions to absolute address ones.
622 * these are rumoured to be faster, and the apollo linker refuses
623 * to deal with the PC relative relocations.
625 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
630 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
636 as_fatal (_("Unknown PC relative instruction"));
641 #endif /* NO_PCREL_RELOCS */
644 tc_coff_fix2rtype (fixP)
647 if (fixP->fx_tcbit && fixP->fx_size == 4)
648 return R_RELLONG_NEG;
649 #ifdef NO_PCREL_RELOCS
650 know (fixP->fx_pcrel == 0);
651 return (fixP->fx_size == 1 ? R_RELBYTE
652 : fixP->fx_size == 2 ? R_DIR16
655 return (fixP->fx_pcrel ?
656 (fixP->fx_size == 1 ? R_PCRBYTE :
657 fixP->fx_size == 2 ? R_PCRWORD :
659 (fixP->fx_size == 1 ? R_RELBYTE :
660 fixP->fx_size == 2 ? R_RELWORD :
669 /* Compute the relocation code for a fixup of SIZE bytes, using pc
670 relative relocation if PCREL is non-zero. PIC says whether a special
671 pic relocation was requested. */
673 static bfd_reloc_code_real_type get_reloc_code
674 PARAMS ((int, int, enum pic_relocation));
676 static bfd_reloc_code_real_type
677 get_reloc_code (size, pcrel, pic)
680 enum pic_relocation pic;
688 return BFD_RELOC_8_GOT_PCREL;
690 return BFD_RELOC_16_GOT_PCREL;
692 return BFD_RELOC_32_GOT_PCREL;
700 return BFD_RELOC_8_GOTOFF;
702 return BFD_RELOC_16_GOTOFF;
704 return BFD_RELOC_32_GOTOFF;
712 return BFD_RELOC_8_PLT_PCREL;
714 return BFD_RELOC_16_PLT_PCREL;
716 return BFD_RELOC_32_PLT_PCREL;
724 return BFD_RELOC_8_PLTOFF;
726 return BFD_RELOC_16_PLTOFF;
728 return BFD_RELOC_32_PLTOFF;
738 return BFD_RELOC_8_PCREL;
740 return BFD_RELOC_16_PCREL;
742 return BFD_RELOC_32_PCREL;
762 as_bad (_("Can not do %d byte pc-relative relocation"), size);
764 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
769 as_bad (_("Can not do %d byte relocation"), size);
771 as_bad (_("Can not do %d byte pic relocation"), size);
774 return BFD_RELOC_NONE;
777 /* Here we decide which fixups can be adjusted to make them relative
778 to the beginning of the section instead of the symbol. Basically
779 we need to make sure that the dynamic relocations are done
780 correctly, so in some cases we force the original symbol to be
783 tc_m68k_fix_adjustable (fixP)
786 /* Prevent all adjustments to global symbols. */
787 if (S_IS_EXTERNAL (fixP->fx_addsy)
788 || S_IS_WEAK (fixP->fx_addsy))
791 /* adjust_reloc_syms doesn't know about the GOT */
792 switch (fixP->fx_r_type)
794 case BFD_RELOC_8_GOT_PCREL:
795 case BFD_RELOC_16_GOT_PCREL:
796 case BFD_RELOC_32_GOT_PCREL:
797 case BFD_RELOC_8_GOTOFF:
798 case BFD_RELOC_16_GOTOFF:
799 case BFD_RELOC_32_GOTOFF:
800 case BFD_RELOC_8_PLT_PCREL:
801 case BFD_RELOC_16_PLT_PCREL:
802 case BFD_RELOC_32_PLT_PCREL:
803 case BFD_RELOC_8_PLTOFF:
804 case BFD_RELOC_16_PLTOFF:
805 case BFD_RELOC_32_PLTOFF:
808 case BFD_RELOC_VTABLE_INHERIT:
809 case BFD_RELOC_VTABLE_ENTRY:
819 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
826 tc_gen_reloc (section, fixp)
831 bfd_reloc_code_real_type code;
836 if (fixp->fx_r_type != BFD_RELOC_NONE)
838 code = fixp->fx_r_type;
840 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
841 that fixup_segment converted a non-PC relative reloc into a
842 PC relative reloc. In such a case, we need to convert the
849 code = BFD_RELOC_8_PCREL;
852 code = BFD_RELOC_16_PCREL;
855 code = BFD_RELOC_32_PCREL;
857 case BFD_RELOC_8_PCREL:
858 case BFD_RELOC_16_PCREL:
859 case BFD_RELOC_32_PCREL:
860 case BFD_RELOC_8_GOT_PCREL:
861 case BFD_RELOC_16_GOT_PCREL:
862 case BFD_RELOC_32_GOT_PCREL:
863 case BFD_RELOC_8_GOTOFF:
864 case BFD_RELOC_16_GOTOFF:
865 case BFD_RELOC_32_GOTOFF:
866 case BFD_RELOC_8_PLT_PCREL:
867 case BFD_RELOC_16_PLT_PCREL:
868 case BFD_RELOC_32_PLT_PCREL:
869 case BFD_RELOC_8_PLTOFF:
870 case BFD_RELOC_16_PLTOFF:
871 case BFD_RELOC_32_PLTOFF:
874 as_bad_where (fixp->fx_file, fixp->fx_line,
875 _("Cannot make %s relocation PC relative"),
876 bfd_get_reloc_code_name (code));
882 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
883 switch (F (fixp->fx_size, fixp->fx_pcrel))
885 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
886 MAP (1, 0, BFD_RELOC_8);
887 MAP (2, 0, BFD_RELOC_16);
888 MAP (4, 0, BFD_RELOC_32);
889 MAP (1, 1, BFD_RELOC_8_PCREL);
890 MAP (2, 1, BFD_RELOC_16_PCREL);
891 MAP (4, 1, BFD_RELOC_32_PCREL);
899 reloc = (arelent *) xmalloc (sizeof (arelent));
900 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
901 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
904 reloc->addend = fixp->fx_addnumber;
909 reloc->addend = fixp->fx_addnumber;
911 reloc->addend = (section->vma
912 + (fixp->fx_pcrel_adjust == 64
913 ? -1 : fixp->fx_pcrel_adjust)
915 + md_pcrel_from (fixp));
918 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
919 assert (reloc->howto != 0);
924 #endif /* BFD_ASSEMBLER */
926 /* Return zero if the reference to SYMBOL from within the same segment may
930 /* On an ELF system, we can't relax an externally visible symbol,
931 because it may be overridden by a shared library. However, if
932 TARGET_OS is "elf", then we presume that we are assembling for an
933 embedded system, in which case we don't have to worry about shared
934 libraries, and we can relax anything. */
936 #define relaxable_symbol(symbol) \
937 (strcmp (TARGET_OS, "elf") == 0 \
938 || (! S_IS_EXTERNAL (symbol) \
939 && ! S_IS_WEAK (symbol)))
943 #define relaxable_symbol(symbol) 1
947 /* Handle of the OPCODE hash table. NULL means any use before
948 m68k_ip_begin() will crash. */
949 static struct hash_control *op_hash;
951 /* Assemble an m68k instruction. */
958 register struct m68k_op *opP;
959 register const struct m68k_incant *opcode;
960 register const char *s;
961 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
962 char *pdot, *pdotmove;
963 enum m68k_size siz1, siz2;
967 LITTLENUM_TYPE words[6];
968 LITTLENUM_TYPE *wordp;
969 unsigned long ok_arch = 0;
971 if (*instring == ' ')
972 instring++; /* skip leading whitespace */
974 /* Scan up to end of operation-code, which MUST end in end-of-string
975 or exactly 1 space. */
977 for (p = instring; *p != '\0'; p++)
987 the_ins.error = _("No operator");
991 /* p now points to the end of the opcode name, probably whitespace.
992 Make sure the name is null terminated by clobbering the
993 whitespace, look it up in the hash table, then fix it back.
994 Remove a dot, first, since the opcode tables have none. */
997 for (pdotmove = pdot; pdotmove < p; pdotmove++)
998 *pdotmove = pdotmove[1];
1004 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1009 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1010 *pdotmove = pdotmove[-1];
1017 the_ins.error = _("Unknown operator");
1021 /* found a legitimate opcode, start matching operands */
1025 if (opcode->m_operands == 0)
1027 char *old = input_line_pointer;
1029 input_line_pointer = p;
1030 /* Ahh - it's a motorola style psuedo op */
1031 mote_pseudo_table[opcode->m_opnum].poc_handler
1032 (mote_pseudo_table[opcode->m_opnum].poc_val);
1033 input_line_pointer = old;
1039 if (flag_mri && opcode->m_opnum == 0)
1041 /* In MRI mode, random garbage is allowed after an instruction
1042 which accepts no operands. */
1043 the_ins.args = opcode->m_operands;
1044 the_ins.numargs = opcode->m_opnum;
1045 the_ins.numo = opcode->m_codenum;
1046 the_ins.opcode[0] = getone (opcode);
1047 the_ins.opcode[1] = gettwo (opcode);
1051 for (opP = &the_ins.operands[0]; *p; opP++)
1053 p = crack_operand (p, opP);
1057 the_ins.error = opP->error;
1062 opsfound = opP - &the_ins.operands[0];
1064 /* This ugly hack is to support the floating pt opcodes in their
1065 standard form. Essentially, we fake a first enty of type COP#1 */
1066 if (opcode->m_operands[0] == 'I')
1070 for (n = opsfound; n > 0; --n)
1071 the_ins.operands[n] = the_ins.operands[n - 1];
1073 memset ((char *) (&the_ins.operands[0]), '\0',
1074 sizeof (the_ins.operands[0]));
1075 the_ins.operands[0].mode = CONTROL;
1076 the_ins.operands[0].reg = m68k_float_copnum;
1080 /* We've got the operands. Find an opcode that'll accept them */
1083 /* If we didn't get the right number of ops, or we have no
1084 common model with this pattern then reject this pattern. */
1086 ok_arch |= opcode->m_arch;
1087 if (opsfound != opcode->m_opnum
1088 || ((opcode->m_arch & current_architecture) == 0))
1092 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1096 /* Warning: this switch is huge! */
1097 /* I've tried to organize the cases into this order:
1098 non-alpha first, then alpha by letter. Lower-case
1099 goes directly before uppercase counterpart. */
1100 /* Code with multiple case ...: gets sorted by the lowest
1101 case ... it belongs to. I hope this makes sense. */
1207 if (opP->reg == PC || opP->reg == ZPC)
1224 if (opP->reg == PC || opP->reg == ZPC)
1243 if (opP->reg == PC || opP->reg == ZPC)
1253 if (opP->mode != IMMED)
1255 else if (s[1] == 'b'
1256 && ! isvar (&opP->disp)
1257 && (opP->disp.exp.X_op != O_constant
1258 || ! isbyte (opP->disp.exp.X_add_number)))
1260 else if (s[1] == 'B'
1261 && ! isvar (&opP->disp)
1262 && (opP->disp.exp.X_op != O_constant
1263 || ! issbyte (opP->disp.exp.X_add_number)))
1265 else if (s[1] == 'w'
1266 && ! isvar (&opP->disp)
1267 && (opP->disp.exp.X_op != O_constant
1268 || ! isword (opP->disp.exp.X_add_number)))
1270 else if (s[1] == 'W'
1271 && ! isvar (&opP->disp)
1272 && (opP->disp.exp.X_op != O_constant
1273 || ! issword (opP->disp.exp.X_add_number)))
1279 if (opP->mode != IMMED)
1284 if (opP->mode == AREG
1285 || opP->mode == CONTROL
1286 || opP->mode == FPREG
1287 || opP->mode == IMMED
1288 || opP->mode == REGLST
1289 || (opP->mode != ABSL
1291 || opP->reg == ZPC)))
1296 if (opP->mode == CONTROL
1297 || opP->mode == FPREG
1298 || opP->mode == REGLST
1299 || opP->mode == IMMED
1300 || (opP->mode != ABSL
1302 || opP->reg == ZPC)))
1330 if (opP->mode == CONTROL
1331 || opP->mode == FPREG
1332 || opP->mode == REGLST)
1337 if (opP->mode != AINC)
1342 if (opP->mode != ADEC)
1392 if (opP->reg == PC || opP->reg == ZPC)
1413 case '~': /* For now! (JF FOO is this right?) */
1435 if (opP->mode != CONTROL
1436 || (opP->reg != TT0 && opP->reg != TT1))
1441 if (opP->mode != AREG)
1446 if (opP->mode != AINDR)
1451 if (opP->mode != ABSL
1453 && strncmp (instring, "jbsr", 4) == 0))
1458 if (opP->mode != CONTROL || opP->reg != CCR)
1463 if (opP->mode != DISP
1465 || opP->reg > ADDR7)
1470 if (opP->mode != DREG)
1475 if (opP->mode != FPREG)
1480 if (opP->mode != CONTROL
1487 if (opP->mode != CONTROL
1489 || opP->reg > last_movec_reg)
1493 const enum m68k_register *rp;
1494 for (rp = control_regs; *rp; rp++)
1495 if (*rp == opP->reg)
1503 if (opP->mode != IMMED)
1509 if (opP->mode == DREG
1510 || opP->mode == AREG
1511 || opP->mode == FPREG)
1520 opP->mask = 1 << (opP->reg - DATA0);
1523 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1526 opP->mask = 1 << (opP->reg - FP0 + 16);
1534 else if (opP->mode == CONTROL)
1543 opP->mask = 1 << 24;
1546 opP->mask = 1 << 25;
1549 opP->mask = 1 << 26;
1558 else if (opP->mode != REGLST)
1560 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1562 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1567 if (opP->mode != IMMED)
1569 else if (opP->disp.exp.X_op != O_constant
1570 || ! issbyte (opP->disp.exp.X_add_number))
1572 else if (! m68k_quick
1573 && instring[3] != 'q'
1574 && instring[4] != 'q')
1579 if (opP->mode != DREG
1580 && opP->mode != IMMED
1581 && opP->mode != ABSL)
1586 if (opP->mode != IMMED)
1588 else if (opP->disp.exp.X_op != O_constant
1589 || opP->disp.exp.X_add_number < 1
1590 || opP->disp.exp.X_add_number > 8)
1592 else if (! m68k_quick
1593 && (strncmp (instring, "add", 3) == 0
1594 || strncmp (instring, "sub", 3) == 0)
1595 && instring[3] != 'q')
1600 if (opP->mode != DREG && opP->mode != AREG)
1605 if (opP->mode != AINDR
1606 && (opP->mode != BASE
1608 && opP->reg != ZADDR0)
1609 || opP->disp.exp.X_op != O_absent
1610 || ((opP->index.reg < DATA0
1611 || opP->index.reg > DATA7)
1612 && (opP->index.reg < ADDR0
1613 || opP->index.reg > ADDR7))
1614 || opP->index.size != SIZE_UNSPEC
1615 || opP->index.scale != 1))
1620 if (opP->mode != CONTROL
1621 || ! (opP->reg == FPI
1623 || opP->reg == FPC))
1628 if (opP->mode != CONTROL || opP->reg != SR)
1633 if (opP->mode != IMMED)
1635 else if (opP->disp.exp.X_op != O_constant
1636 || opP->disp.exp.X_add_number < 0
1637 || opP->disp.exp.X_add_number > 7)
1642 if (opP->mode != CONTROL || opP->reg != USP)
1646 /* JF these are out of order. We could put them
1647 in order if we were willing to put up with
1648 bunches of #ifdef m68851s in the code.
1650 Don't forget that you need these operands
1651 to use 68030 MMU instructions. */
1653 /* Memory addressing mode used by pflushr */
1655 if (opP->mode == CONTROL
1656 || opP->mode == FPREG
1657 || opP->mode == DREG
1658 || opP->mode == AREG
1659 || opP->mode == REGLST)
1661 /* We should accept immediate operands, but they
1662 supposedly have to be quad word, and we don't
1663 handle that. I would like to see what a Motorola
1664 assembler does before doing something here. */
1665 if (opP->mode == IMMED)
1670 if (opP->mode != CONTROL
1671 || (opP->reg != SFC && opP->reg != DFC))
1676 if (opP->mode != CONTROL || opP->reg != TC)
1681 if (opP->mode != CONTROL || opP->reg != AC)
1686 if (opP->mode != CONTROL
1689 && opP->reg != SCC))
1694 if (opP->mode != CONTROL
1700 if (opP->mode != CONTROL
1703 && opP->reg != CRP))
1708 if (opP->mode != CONTROL
1709 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1710 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1715 if (opP->mode != CONTROL || opP->reg != PSR)
1720 if (opP->mode != CONTROL || opP->reg != PCSR)
1725 if (opP->mode != CONTROL
1732 } /* not a cache specifier. */
1736 if (opP->mode != ABSL)
1742 } /* switch on type of operand */
1746 } /* for each operand */
1747 } /* if immediately wrong */
1754 opcode = opcode->m_next;
1759 && !(ok_arch & current_architecture))
1764 _("invalid instruction for this architecture; needs "));
1765 cp = buf + strlen (buf);
1769 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1772 strcpy (cp, _("mmu (68030 or 68851)"));
1775 strcpy (cp, _("68020 or higher"));
1778 strcpy (cp, _("68000 or higher"));
1781 strcpy (cp, _("68010 or higher"));
1785 int got_one = 0, idx;
1786 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1789 if ((archs[idx].arch & ok_arch)
1790 && ! archs[idx].alias)
1794 strcpy (cp, " or ");
1798 strcpy (cp, archs[idx].name);
1804 cp = xmalloc (strlen (buf) + 1);
1809 the_ins.error = _("operands mismatch");
1811 } /* Fell off the end */
1816 /* now assemble it */
1818 the_ins.args = opcode->m_operands;
1819 the_ins.numargs = opcode->m_opnum;
1820 the_ins.numo = opcode->m_codenum;
1821 the_ins.opcode[0] = getone (opcode);
1822 the_ins.opcode[1] = gettwo (opcode);
1824 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1826 /* This switch is a doozy.
1827 Watch the first step; its a big one! */
1855 tmpreg = 0x3c; /* 7.4 */
1856 if (strchr ("bwl", s[1]))
1857 nextword = get_num (&opP->disp, 80);
1859 nextword = get_num (&opP->disp, 0);
1860 if (isvar (&opP->disp))
1861 add_fix (s[1], &opP->disp, 0, 0);
1865 if (!isbyte (nextword))
1866 opP->error = _("operand out of range");
1871 if (!isword (nextword))
1872 opP->error = _("operand out of range");
1877 if (!issword (nextword))
1878 opP->error = _("operand out of range");
1883 addword (nextword >> 16);
1910 /* We gotta put out some float */
1911 if (op (&opP->disp) != O_big)
1916 /* Can other cases happen here? */
1917 if (op (&opP->disp) != O_constant)
1920 val = (valueT) offs (&opP->disp);
1924 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1925 val >>= LITTLENUM_NUMBER_OF_BITS;
1929 offs (&opP->disp) = gencnt;
1931 if (offs (&opP->disp) > 0)
1933 if (offs (&opP->disp) > baseo)
1935 as_warn (_("Bignum too big for %c format; truncated"),
1937 offs (&opP->disp) = baseo;
1939 baseo -= offs (&opP->disp);
1942 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1943 offs (&opP->disp)--;
1948 gen_to_words (words, baseo, (long) outro);
1949 for (wordp = words; baseo--; wordp++)
1953 tmpreg = opP->reg - DATA; /* 0.dreg */
1956 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1959 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1962 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1965 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1969 nextword = get_num (&opP->disp, 80);
1972 && ! isvar (&opP->disp)
1975 opP->disp.exp.X_op = O_symbol;
1976 #ifndef BFD_ASSEMBLER
1977 opP->disp.exp.X_add_symbol = &abs_symbol;
1979 opP->disp.exp.X_add_symbol =
1980 section_symbol (absolute_section);
1984 /* Force into index mode. Hope this works */
1986 /* We do the first bit for 32-bit displacements, and the
1987 second bit for 16 bit ones. It is possible that we
1988 should make the default be WORD instead of LONG, but
1989 I think that'd break GCC, so we put up with a little
1990 inefficiency for the sake of working output. */
1992 if (!issword (nextword)
1993 || (isvar (&opP->disp)
1994 && ((opP->disp.size == SIZE_UNSPEC
1995 && flag_short_refs == 0
1996 && cpu_of_arch (current_architecture) >= m68020
1997 && cpu_of_arch (current_architecture) != mcf5200)
1998 || opP->disp.size == SIZE_LONG)))
2000 if (cpu_of_arch (current_architecture) < m68020
2001 || cpu_of_arch (current_architecture) == mcf5200)
2003 _("displacement too large for this architecture; needs 68020 or higher");
2005 tmpreg = 0x3B; /* 7.3 */
2007 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2008 if (isvar (&opP->disp))
2012 if (opP->disp.size == SIZE_LONG
2014 /* If the displacement needs pic
2015 relocation it cannot be relaxed. */
2016 || opP->disp.pic_reloc != pic_none
2021 add_fix ('l', &opP->disp, 1, 2);
2025 add_frag (adds (&opP->disp),
2027 TAB (PCLEA, SZ_UNDEF));
2034 add_fix ('l', &opP->disp, 0, 0);
2039 addword (nextword >> 16);
2044 tmpreg = 0x3A; /* 7.2 */
2046 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2048 if (isvar (&opP->disp))
2052 add_fix ('w', &opP->disp, 1, 0);
2055 add_fix ('w', &opP->disp, 0, 0);
2065 baseo = get_num (&opP->disp, 80);
2066 if (opP->mode == POST || opP->mode == PRE)
2067 outro = get_num (&opP->odisp, 80);
2068 /* Figure out the `addressing mode'.
2069 Also turn on the BASE_DISABLE bit, if needed. */
2070 if (opP->reg == PC || opP->reg == ZPC)
2072 tmpreg = 0x3b; /* 7.3 */
2073 if (opP->reg == ZPC)
2076 else if (opP->reg == 0)
2079 tmpreg = 0x30; /* 6.garbage */
2081 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2084 tmpreg = 0x30 + opP->reg - ZADDR0;
2087 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2089 siz1 = opP->disp.size;
2090 if (opP->mode == POST || opP->mode == PRE)
2091 siz2 = opP->odisp.size;
2095 /* Index register stuff */
2096 if (opP->index.reg != 0
2097 && opP->index.reg >= DATA
2098 && opP->index.reg <= ADDR7)
2100 nextword |= (opP->index.reg - DATA) << 12;
2102 if (opP->index.size == SIZE_LONG
2103 || (opP->index.size == SIZE_UNSPEC
2104 && m68k_index_width_default == SIZE_LONG))
2107 if ((opP->index.scale != 1
2108 && cpu_of_arch (current_architecture) < m68020)
2109 || (opP->index.scale == 8
2110 && current_architecture == mcf5200))
2113 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2116 switch (opP->index.scale)
2133 GET US OUT OF HERE! */
2135 /* Must be INDEX, with an index register. Address
2136 register cannot be ZERO-PC, and either :b was
2137 forced, or we know it will fit. For a 68000 or
2138 68010, force this mode anyways, because the
2139 larger modes aren't supported. */
2140 if (opP->mode == BASE
2141 && ((opP->reg >= ADDR0
2142 && opP->reg <= ADDR7)
2145 if (siz1 == SIZE_BYTE
2146 || cpu_of_arch (current_architecture) < m68020
2147 || cpu_of_arch (current_architecture) == mcf5200
2148 || (siz1 == SIZE_UNSPEC
2149 && ! isvar (&opP->disp)
2150 && issbyte (baseo)))
2152 nextword += baseo & 0xff;
2154 if (isvar (&opP->disp))
2156 /* Do a byte relocation. If it doesn't
2157 fit (possible on m68000) let the
2158 fixup processing complain later. */
2160 add_fix ('B', &opP->disp, 1, 1);
2162 add_fix ('B', &opP->disp, 0, 0);
2164 else if (siz1 != SIZE_BYTE)
2166 if (siz1 != SIZE_UNSPEC)
2167 as_warn (_("Forcing byte displacement"));
2168 if (! issbyte (baseo))
2169 opP->error = _("byte displacement out of range");
2174 else if (siz1 == SIZE_UNSPEC
2176 && isvar (&opP->disp)
2177 && subs (&opP->disp) == NULL
2179 /* If the displacement needs pic
2180 relocation it cannot be relaxed. */
2181 && opP->disp.pic_reloc == pic_none
2185 /* The code in md_convert_frag_1 needs to be
2186 able to adjust nextword. Call frag_grow
2187 to ensure that we have enough space in
2188 the frag obstack to make all the bytes
2191 nextword += baseo & 0xff;
2193 add_frag (adds (&opP->disp), offs (&opP->disp),
2194 TAB (PCINDEX, SZ_UNDEF));
2202 nextword |= 0x40; /* No index reg */
2203 if (opP->index.reg >= ZDATA0
2204 && opP->index.reg <= ZDATA7)
2205 nextword |= (opP->index.reg - ZDATA0) << 12;
2206 else if (opP->index.reg >= ZADDR0
2207 || opP->index.reg <= ZADDR7)
2208 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2211 /* It isn't simple. */
2213 if (cpu_of_arch (current_architecture) < m68020
2214 || cpu_of_arch (current_architecture) == mcf5200)
2216 _("invalid operand mode for this architecture; needs 68020 or higher");
2219 /* If the guy specified a width, we assume that it is
2220 wide enough. Maybe it isn't. If so, we lose. */
2224 if (isvar (&opP->disp)
2226 : ! issword (baseo))
2231 else if (! isvar (&opP->disp) && baseo == 0)
2240 as_warn (_(":b not permitted; defaulting to :w"));
2250 /* Figure out innner displacement stuff */
2251 if (opP->mode == POST || opP->mode == PRE)
2253 if (cpu_of_arch (current_architecture) & cpu32)
2254 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2258 if (isvar (&opP->odisp)
2260 : ! issword (outro))
2265 else if (! isvar (&opP->odisp) && outro == 0)
2274 as_warn (_(":b not permitted; defaulting to :w"));
2283 if (opP->mode == POST
2284 && (nextword & 0x40) == 0)
2289 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2291 if (opP->reg == PC || opP->reg == ZPC)
2292 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2294 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2296 if (siz1 == SIZE_LONG)
2297 addword (baseo >> 16);
2298 if (siz1 != SIZE_UNSPEC)
2301 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2302 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2303 if (siz2 == SIZE_LONG)
2304 addword (outro >> 16);
2305 if (siz2 != SIZE_UNSPEC)
2311 nextword = get_num (&opP->disp, 80);
2312 switch (opP->disp.size)
2317 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2319 tmpreg = 0x38; /* 7.0 */
2323 /* Don't generate pc relative code on 68010 and
2325 if (isvar (&opP->disp)
2326 && !subs (&opP->disp)
2327 && adds (&opP->disp)
2329 /* If the displacement needs pic relocation it
2330 cannot be relaxed. */
2331 && opP->disp.pic_reloc == pic_none
2333 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2334 && relaxable_symbol (adds (&opP->disp))
2335 && HAVE_LONG_BRANCH(current_architecture)
2337 && !strchr ("~%&$?", s[0]))
2339 tmpreg = 0x3A; /* 7.2 */
2340 add_frag (adds (&opP->disp),
2342 TAB (PCREL, SZ_UNDEF));
2345 /* Fall through into long */
2347 if (isvar (&opP->disp))
2348 add_fix ('l', &opP->disp, 0, 0);
2350 tmpreg = 0x39;/* 7.1 mode */
2351 addword (nextword >> 16);
2356 as_bad (_("unsupported byte value; use a different suffix"));
2358 case SIZE_WORD: /* Word */
2359 if (isvar (&opP->disp))
2360 add_fix ('w', &opP->disp, 0, 0);
2362 tmpreg = 0x38;/* 7.0 mode */
2370 as_bad (_("unknown/incorrect operand"));
2373 install_gen_operand (s[1], tmpreg);
2379 { /* JF: I hate floating point! */
2394 tmpreg = get_num (&opP->disp, tmpreg);
2395 if (isvar (&opP->disp))
2396 add_fix (s[1], &opP->disp, 0, 0);
2399 case 'b': /* Danger: These do no check for
2400 certain types of overflow.
2402 if (!isbyte (tmpreg))
2403 opP->error = _("out of range");
2404 insop (tmpreg, opcode);
2405 if (isvar (&opP->disp))
2406 the_ins.reloc[the_ins.nrel - 1].n =
2407 (opcode->m_codenum) * 2 + 1;
2410 if (!issbyte (tmpreg))
2411 opP->error = _("out of range");
2412 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2413 if (isvar (&opP->disp))
2414 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2417 if (!isword (tmpreg))
2418 opP->error = _("out of range");
2419 insop (tmpreg, opcode);
2420 if (isvar (&opP->disp))
2421 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2424 if (!issword (tmpreg))
2425 opP->error = _("out of range");
2426 insop (tmpreg, opcode);
2427 if (isvar (&opP->disp))
2428 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2431 /* Because of the way insop works, we put these two out
2433 insop (tmpreg, opcode);
2434 insop (tmpreg >> 16, opcode);
2435 if (isvar (&opP->disp))
2436 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2443 install_operand (s[1], tmpreg);
2454 install_operand (s[1], opP->reg - ADDR);
2458 tmpreg = get_num (&opP->disp, 80);
2462 /* The pc_fix argument winds up in fx_pcrel_adjust,
2463 which is a char, and may therefore be unsigned. We
2464 want to pass -1, but we pass 64 instead, and convert
2465 back in md_pcrel_from. */
2466 add_fix ('B', &opP->disp, 1, 64);
2469 add_fix ('w', &opP->disp, 1, 0);
2474 if (!HAVE_LONG_BRANCH(current_architecture))
2475 as_warn (_("Can't use long branches on 68000/68010/5200"));
2476 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2477 add_fix ('l', &opP->disp, 1, 0);
2482 if (subs (&opP->disp)) /* We can't relax it */
2486 /* If the displacement needs pic relocation it cannot be
2488 if (opP->disp.pic_reloc != pic_none)
2492 /* This could either be a symbol, or an absolute
2493 address. No matter, the frag hacking will finger it
2494 out. Not quite: it can't switch from BRANCH to
2495 BCC68000 for the case where opnd is absolute (it
2496 needs to use the 68000 hack since no conditional abs
2498 if (( !HAVE_LONG_BRANCH(current_architecture)
2499 || (0 == adds (&opP->disp)))
2500 && (the_ins.opcode[0] >= 0x6200)
2501 && (the_ins.opcode[0] <= 0x6f00))
2502 add_frag (adds (&opP->disp), offs (&opP->disp),
2503 TAB (BCC68000, SZ_UNDEF));
2505 add_frag (adds (&opP->disp), offs (&opP->disp),
2506 TAB (ABRANCH, SZ_UNDEF));
2509 if (isvar (&opP->disp))
2512 /* check for DBcc instruction */
2513 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2515 /* size varies if patch */
2516 /* needed for long form */
2517 add_frag (adds (&opP->disp), offs (&opP->disp),
2518 TAB (DBCC, SZ_UNDEF));
2522 add_fix ('w', &opP->disp, 1, 0);
2526 case 'C': /* Fixed size LONG coproc branches */
2527 add_fix ('l', &opP->disp, 1, 0);
2531 case 'c': /* Var size Coprocesssor branches */
2532 if (subs (&opP->disp))
2534 add_fix ('l', &opP->disp, 1, 0);
2535 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2537 else if (adds (&opP->disp))
2538 add_frag (adds (&opP->disp), offs (&opP->disp),
2539 TAB (FBRANCH, SZ_UNDEF));
2542 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2543 TAB(FBRANCH,SHORT)); */
2544 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2545 add_fix ('l', &opP->disp, 1, 0);
2555 case 'C': /* Ignore it */
2558 case 'd': /* JF this is a kludge */
2559 install_operand ('s', opP->reg - ADDR);
2560 tmpreg = get_num (&opP->disp, 80);
2561 if (!issword (tmpreg))
2563 as_warn (_("Expression out of range, using 0"));
2570 install_operand (s[1], opP->reg - DATA);
2574 install_operand (s[1], opP->reg - FP0);
2578 tmpreg = opP->reg - COP0;
2579 install_operand (s[1], tmpreg);
2582 case 'J': /* JF foo */
2655 install_operand (s[1], tmpreg);
2659 tmpreg = get_num (&opP->disp, 55);
2660 install_operand (s[1], tmpreg & 0x7f);
2667 if (tmpreg & 0x7FF0000)
2668 as_bad (_("Floating point register in register list"));
2669 insop (reverse_16_bits (tmpreg), opcode);
2673 if (tmpreg & 0x700FFFF)
2674 as_bad (_("Wrong register in floating-point reglist"));
2675 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2683 if (tmpreg & 0x7FF0000)
2684 as_bad (_("Floating point register in register list"));
2685 insop (tmpreg, opcode);
2687 else if (s[1] == '8')
2689 if (tmpreg & 0x0FFFFFF)
2690 as_bad (_("incorrect register in reglist"));
2691 install_operand (s[1], tmpreg >> 24);
2695 if (tmpreg & 0x700FFFF)
2696 as_bad (_("wrong register in floating-point reglist"));
2698 install_operand (s[1], tmpreg >> 16);
2703 install_operand (s[1], get_num (&opP->disp, 60));
2707 tmpreg = ((opP->mode == DREG)
2708 ? 0x20 + opP->reg - DATA
2709 : (get_num (&opP->disp, 40) & 0x1F));
2710 install_operand (s[1], tmpreg);
2714 tmpreg = get_num (&opP->disp, 10);
2717 install_operand (s[1], tmpreg);
2721 /* This depends on the fact that ADDR registers are eight
2722 more than their corresponding DATA regs, so the result
2723 will have the ADDR_REG bit set */
2724 install_operand (s[1], opP->reg - DATA);
2728 if (opP->mode == AINDR)
2729 install_operand (s[1], opP->reg - DATA);
2731 install_operand (s[1], opP->index.reg - DATA);
2735 if (opP->reg == FPI)
2737 else if (opP->reg == FPS)
2739 else if (opP->reg == FPC)
2743 install_operand (s[1], tmpreg);
2746 case 'S': /* Ignore it */
2750 install_operand (s[1], get_num (&opP->disp, 30));
2753 case 'U': /* Ignore it */
2772 as_fatal (_("failed sanity check"));
2773 } /* switch on cache token */
2774 install_operand (s[1], tmpreg);
2777 /* JF: These are out of order, I fear. */
2790 install_operand (s[1], tmpreg);
2816 install_operand (s[1], tmpreg);
2820 if (opP->reg == VAL)
2839 install_operand (s[1], tmpreg);
2853 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2864 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2870 install_operand (s[1], tmpreg);
2873 know (opP->reg == PSR);
2876 know (opP->reg == PCSR);
2891 install_operand (s[1], tmpreg);
2894 tmpreg = get_num (&opP->disp, 20);
2895 install_operand (s[1], tmpreg);
2897 case '_': /* used only for move16 absolute 32-bit address */
2898 if (isvar (&opP->disp))
2899 add_fix ('l', &opP->disp, 0, 0);
2900 tmpreg = get_num (&opP->disp, 80);
2901 addword (tmpreg >> 16);
2902 addword (tmpreg & 0xFFFF);
2909 /* By the time whe get here (FINALLY) the_ins contains the complete
2910 instruction, ready to be emitted. . . */
2914 reverse_16_bits (in)
2920 static int mask[16] =
2922 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2923 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2925 for (n = 0; n < 16; n++)
2928 out |= mask[15 - n];
2931 } /* reverse_16_bits() */
2940 static int mask[8] =
2942 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2945 for (n = 0; n < 8; n++)
2951 } /* reverse_8_bits() */
2953 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2954 (that value is chosen in the frag_var call in md_assemble). TYPE
2955 is the subtype of the frag to be generated; its primary type is
2956 rs_machine_dependent.
2958 The TYPE parameter is also used by md_convert_frag_1 and
2959 md_estimate_size_before_relax. The appropriate type of fixup will
2960 be emitted by md_convert_frag_1.
2962 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2964 install_operand (mode, val)
2971 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2974 the_ins.opcode[0] |= val << 9;
2977 the_ins.opcode[1] |= val << 12;
2980 the_ins.opcode[1] |= val << 6;
2983 the_ins.opcode[1] |= val;
2986 the_ins.opcode[2] |= val << 12;
2989 the_ins.opcode[2] |= val << 6;
2992 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2993 three words long! */
2995 the_ins.opcode[2] |= val;
2998 the_ins.opcode[1] |= val << 7;
3001 the_ins.opcode[1] |= val << 10;
3005 the_ins.opcode[1] |= val << 5;
3010 the_ins.opcode[1] |= (val << 10) | (val << 7);
3013 the_ins.opcode[1] |= (val << 12) | val;
3016 the_ins.opcode[0] |= val = 0xff;
3019 the_ins.opcode[0] |= val << 9;
3022 the_ins.opcode[1] |= val;
3025 the_ins.opcode[1] |= val;
3026 the_ins.numo++; /* What a hack */
3029 the_ins.opcode[1] |= val << 4;
3037 the_ins.opcode[0] |= (val << 6);
3040 the_ins.opcode[1] = (val >> 16);
3041 the_ins.opcode[2] = val & 0xffff;
3045 as_fatal (_("failed sanity check."));
3047 } /* install_operand() */
3050 install_gen_operand (mode, val)
3057 the_ins.opcode[0] |= val;
3060 /* This is a kludge!!! */
3061 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3070 the_ins.opcode[0] |= val;
3072 /* more stuff goes here */
3074 as_fatal (_("failed sanity check."));
3076 } /* install_gen_operand() */
3079 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3080 * then deal with the bitfield hack.
3084 crack_operand (str, opP)
3086 register struct m68k_op *opP;
3088 register int parens;
3090 register char *beg_str;
3098 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3104 else if (*str == ')')
3108 opP->error = _("Extra )");
3114 if (flag_mri && *str == '\'')
3115 inquote = ! inquote;
3117 if (!*str && parens)
3119 opP->error = _("Missing )");
3124 if (m68k_ip_op (beg_str, opP) != 0)
3131 c = *++str; /* JF bitfield hack */
3136 as_bad (_("Missing operand"));
3139 /* Detect MRI REG symbols and convert them to REGLSTs. */
3140 if (opP->mode == CONTROL && (int)opP->reg < 0)
3143 opP->mask = ~(int)opP->reg;
3150 /* This is the guts of the machine-dependent assembler. STR points to a
3151 machine dependent instruction. This function is supposed to emit
3152 the frags/bytes it assembles to.
3156 insert_reg (regname, regnum)
3157 const char *regname;
3163 #ifdef REGISTER_PREFIX
3164 if (!flag_reg_prefix_optional)
3166 buf[0] = REGISTER_PREFIX;
3167 strcpy (buf + 1, regname);
3172 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3173 &zero_address_frag));
3175 for (i = 0; regname[i]; i++)
3176 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3179 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3180 &zero_address_frag));
3189 static const struct init_entry init_table[] =
3244 /* control registers */
3245 { "sfc", SFC }, /* Source Function Code */
3247 { "dfc", DFC }, /* Destination Function Code */
3249 { "cacr", CACR }, /* Cache Control Register */
3250 { "caar", CAAR }, /* Cache Address Register */
3252 { "usp", USP }, /* User Stack Pointer */
3253 { "vbr", VBR }, /* Vector Base Register */
3254 { "msp", MSP }, /* Master Stack Pointer */
3255 { "isp", ISP }, /* Interrupt Stack Pointer */
3257 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3258 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3259 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3260 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3262 /* 68ec040 versions of same */
3263 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3264 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3265 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3266 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3268 /* mcf5200 versions of same. The ColdFire programmer's reference
3269 manual indicated that the order is 2,3,0,1, but Ken Rose
3270 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3271 { "acr0", ITT0 }, /* Access Control Unit 0 */
3272 { "acr1", ITT1 }, /* Access Control Unit 1 */
3273 { "acr2", DTT0 }, /* Access Control Unit 2 */
3274 { "acr3", DTT1 }, /* Access Control Unit 3 */
3276 { "tc", TC }, /* MMU Translation Control Register */
3279 { "mmusr", MMUSR }, /* MMU Status Register */
3280 { "srp", SRP }, /* User Root Pointer */
3281 { "urp", URP }, /* Supervisor Root Pointer */
3286 { "rombar", ROMBAR }, /* ROM Base Address Register */
3287 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3288 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3289 { "mbar", MBAR }, /* Module Base Address Register */
3290 /* end of control registers */
3324 /* 68ec030 versions of same */
3327 /* 68ec030 access control unit, identical to 030 MMU status reg */
3330 /* Suppressed data and address registers. */
3355 for (i = 0; init_table[i].name; i++)
3356 insert_reg (init_table[i].name, init_table[i].number);
3359 static int no_68851, no_68881;
3362 /* a.out machine type. Default to 68020. */
3363 int m68k_aout_machtype = 2;
3375 int shorts_this_frag;
3378 /* In MRI mode, the instruction and operands are separated by a
3379 space. Anything following the operands is a comment. The label
3380 has already been removed. */
3388 for (s = str; *s != '\0'; s++)
3390 if ((*s == ' ' || *s == '\t') && ! inquote)
3408 inquote = ! inquote;
3413 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3418 for (n = 0; n < the_ins.numargs; n++)
3419 if (the_ins.operands[n].error)
3421 er = the_ins.operands[n].error;
3427 as_bad (_("%s -- statement `%s' ignored"), er, str);
3431 /* If there is a current label, record that it marks an instruction. */
3432 if (current_label != NULL)
3434 current_label->text = 1;
3435 current_label = NULL;
3438 if (the_ins.nfrag == 0)
3440 /* No frag hacking involved; just put it out */
3441 toP = frag_more (2 * the_ins.numo);
3442 fromP = &the_ins.opcode[0];
3443 for (m = the_ins.numo; m; --m)
3445 md_number_to_chars (toP, (long) (*fromP), 2);
3449 /* put out symbol-dependent info */
3450 for (m = 0; m < the_ins.nrel; m++)
3452 switch (the_ins.reloc[m].wid)
3471 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3472 the_ins.reloc[m].wid);
3475 fixP = fix_new_exp (frag_now,
3476 ((toP - frag_now->fr_literal)
3477 - the_ins.numo * 2 + the_ins.reloc[m].n),
3479 &the_ins.reloc[m].exp,
3480 the_ins.reloc[m].pcrel,
3481 get_reloc_code (n, the_ins.reloc[m].pcrel,
3482 the_ins.reloc[m].pic_reloc));
3483 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3484 if (the_ins.reloc[m].wid == 'B')
3485 fixP->fx_signed = 1;
3490 /* There's some frag hacking */
3491 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3496 wid = 2 * the_ins.fragb[n].fragoff;
3498 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3499 toP = frag_more (wid);
3501 shorts_this_frag = 0;
3502 for (m = wid / 2; m; --m)
3504 md_number_to_chars (toP, (long) (*fromP), 2);
3509 for (m = 0; m < the_ins.nrel; m++)
3511 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3513 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3516 wid = the_ins.reloc[m].wid;
3519 the_ins.reloc[m].wid = 0;
3520 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3522 fixP = fix_new_exp (frag_now,
3523 ((toP - frag_now->fr_literal)
3524 - the_ins.numo * 2 + the_ins.reloc[m].n),
3526 &the_ins.reloc[m].exp,
3527 the_ins.reloc[m].pcrel,
3528 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3529 the_ins.reloc[m].pic_reloc));
3530 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3532 (void) frag_var (rs_machine_dependent, 10, 0,
3533 (relax_substateT) (the_ins.fragb[n].fragty),
3534 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3536 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3537 shorts_this_frag = 0;
3540 toP = frag_more (n * sizeof (short));
3543 md_number_to_chars (toP, (long) (*fromP), 2);
3549 for (m = 0; m < the_ins.nrel; m++)
3553 wid = the_ins.reloc[m].wid;
3556 the_ins.reloc[m].wid = 0;
3557 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3559 fixP = fix_new_exp (frag_now,
3560 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3561 - shorts_this_frag * 2),
3563 &the_ins.reloc[m].exp,
3564 the_ins.reloc[m].pcrel,
3565 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3566 the_ins.reloc[m].pic_reloc));
3567 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3575 * md_begin -- set up hash tables with 68000 instructions.
3576 * similar to what the vax assembler does. ---phr
3578 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3579 a copy of it at runtime, adding in the information we want but isn't
3580 there. I think it'd be better to have an awk script hack the table
3581 at compile time. Or even just xstr the table and use it as-is. But
3582 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3585 register const struct m68k_opcode *ins;
3586 register struct m68k_incant *hack, *slak;
3587 register const char *retval = 0; /* empty string, or error msg text */
3588 register unsigned int i;
3593 flag_reg_prefix_optional = 1;
3595 if (! m68k_rel32_from_cmdline)
3599 op_hash = hash_new ();
3601 obstack_begin (&robyn, 4000);
3602 for (i = 0; i < m68k_numopcodes; i++)
3604 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3607 ins = &m68k_opcodes[i];
3608 /* We *could* ignore insns that don't match our arch here
3609 but just leaving them out of the hash. */
3610 slak->m_operands = ins->args;
3611 slak->m_opnum = strlen (slak->m_operands) / 2;
3612 slak->m_arch = ins->arch;
3613 slak->m_opcode = ins->opcode;
3614 /* This is kludgey */
3615 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3616 if (i + 1 != m68k_numopcodes
3617 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3619 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3624 slak = slak->m_next;
3628 retval = hash_insert (op_hash, ins->name, (char *) hack);
3630 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3633 for (i = 0; i < m68k_numaliases; i++)
3635 const char *name = m68k_opcode_aliases[i].primary;
3636 const char *alias = m68k_opcode_aliases[i].alias;
3637 PTR val = hash_find (op_hash, name);
3639 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3640 retval = hash_insert (op_hash, alias, val);
3642 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3645 /* In MRI mode, all unsized branches are variable sized. Normally,
3646 they are word sized. */
3649 static struct m68k_opcode_alias mri_aliases[] =
3669 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3671 const char *name = mri_aliases[i].primary;
3672 const char *alias = mri_aliases[i].alias;
3673 PTR val = hash_find (op_hash, name);
3675 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3676 retval = hash_jam (op_hash, alias, val);
3678 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3682 for (i = 0; i < sizeof (mklower_table); i++)
3683 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3685 for (i = 0; i < sizeof (notend_table); i++)
3687 notend_table[i] = 0;
3688 alt_notend_table[i] = 0;
3690 notend_table[','] = 1;
3691 notend_table['{'] = 1;
3692 notend_table['}'] = 1;
3693 alt_notend_table['a'] = 1;
3694 alt_notend_table['A'] = 1;
3695 alt_notend_table['d'] = 1;
3696 alt_notend_table['D'] = 1;
3697 alt_notend_table['#'] = 1;
3698 alt_notend_table['&'] = 1;
3699 alt_notend_table['f'] = 1;
3700 alt_notend_table['F'] = 1;
3701 #ifdef REGISTER_PREFIX
3702 alt_notend_table[REGISTER_PREFIX] = 1;
3705 /* We need to put '(' in alt_notend_table to handle
3706 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3708 alt_notend_table['('] = 1;
3710 /* We need to put '@' in alt_notend_table to handle
3711 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3713 alt_notend_table['@'] = 1;
3715 /* We need to put digits in alt_notend_table to handle
3716 bfextu %d0{24:1},%d0
3718 alt_notend_table['0'] = 1;
3719 alt_notend_table['1'] = 1;
3720 alt_notend_table['2'] = 1;
3721 alt_notend_table['3'] = 1;
3722 alt_notend_table['4'] = 1;
3723 alt_notend_table['5'] = 1;
3724 alt_notend_table['6'] = 1;
3725 alt_notend_table['7'] = 1;
3726 alt_notend_table['8'] = 1;
3727 alt_notend_table['9'] = 1;
3729 #ifndef MIT_SYNTAX_ONLY
3730 /* Insert pseudo ops, these have to go into the opcode table since
3731 gas expects pseudo ops to start with a dot */
3734 while (mote_pseudo_table[n].poc_name)
3736 hack = (struct m68k_incant *)
3737 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3738 hash_insert (op_hash,
3739 mote_pseudo_table[n].poc_name, (char *) hack);
3740 hack->m_operands = 0;
3750 record_alignment (text_section, 2);
3751 record_alignment (data_section, 2);
3752 record_alignment (bss_section, 2);
3757 select_control_regs ()
3759 /* Note which set of "movec" control registers is available. */
3760 switch (cpu_of_arch (current_architecture))
3763 control_regs = m68000_control_regs;
3766 control_regs = m68010_control_regs;
3770 control_regs = m68020_control_regs;
3773 control_regs = m68040_control_regs;
3776 control_regs = m68060_control_regs;
3779 control_regs = cpu32_control_regs;
3782 control_regs = mcf5200_control_regs;
3790 m68k_init_after_args ()
3792 if (cpu_of_arch (current_architecture) == 0)
3795 const char *default_cpu = TARGET_CPU;
3797 if (*default_cpu == 'm')
3799 for (i = 0; i < n_archs; i++)
3800 if (strcasecmp (default_cpu, archs[i].name) == 0)
3804 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3805 current_architecture |= m68020;
3808 current_architecture |= archs[i].arch;
3810 /* Permit m68881 specification with all cpus; those that can't work
3811 with a coprocessor could be doing emulation. */
3812 if (current_architecture & m68851)
3814 if (current_architecture & m68040)
3816 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3819 /* What other incompatibilities could we check for? */
3821 /* Toss in some default assumptions about coprocessors. */
3823 && (cpu_of_arch (current_architecture)
3824 /* Can CPU32 have a 68881 coprocessor?? */
3825 & (m68020 | m68030 | cpu32)))
3827 current_architecture |= m68881;
3830 && (cpu_of_arch (current_architecture) & m68020up) != 0
3831 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3833 current_architecture |= m68851;
3835 if (no_68881 && (current_architecture & m68881))
3836 as_bad (_("options for 68881 and no-68881 both given"));
3837 if (no_68851 && (current_architecture & m68851))
3838 as_bad (_("options for 68851 and no-68851 both given"));
3841 /* Work out the magic number. This isn't very general. */
3842 if (current_architecture & m68000)
3843 m68k_aout_machtype = 0;
3844 else if (current_architecture & m68010)
3845 m68k_aout_machtype = 1;
3846 else if (current_architecture & m68020)
3847 m68k_aout_machtype = 2;
3849 m68k_aout_machtype = 2;
3852 /* Note which set of "movec" control registers is available. */
3853 select_control_regs ();
3855 if (cpu_of_arch (current_architecture) < m68020
3856 || cpu_of_arch (current_architecture) == mcf5200)
3857 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3860 /* This is called when a label is defined. */
3863 m68k_frob_label (sym)
3866 struct label_line *n;
3868 n = (struct label_line *) xmalloc (sizeof *n);
3871 as_where (&n->file, &n->line);
3877 /* This is called when a value that is not an instruction is emitted. */
3880 m68k_flush_pending_output ()
3882 current_label = NULL;
3885 /* This is called at the end of the assembly, when the final value of
3886 the label is known. We warn if this is a text symbol aligned at an
3890 m68k_frob_symbol (sym)
3893 if (S_GET_SEGMENT (sym) == reg_section
3894 && (int) S_GET_VALUE (sym) < 0)
3896 S_SET_SEGMENT (sym, absolute_section);
3897 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
3899 else if ((S_GET_VALUE (sym) & 1) != 0)
3901 struct label_line *l;
3903 for (l = labels; l != NULL; l = l->next)
3905 if (l->label == sym)
3908 as_warn_where (l->file, l->line,
3909 _("text label `%s' aligned to odd boundary"),
3917 /* This is called if we go in or out of MRI mode because of the .mri
3921 m68k_mri_mode_change (on)
3926 if (! flag_reg_prefix_optional)
3928 flag_reg_prefix_optional = 1;
3929 #ifdef REGISTER_PREFIX
3934 if (! m68k_rel32_from_cmdline)
3939 if (! reg_prefix_optional_seen)
3941 #ifdef REGISTER_PREFIX_OPTIONAL
3942 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3944 flag_reg_prefix_optional = 0;
3946 #ifdef REGISTER_PREFIX
3951 if (! m68k_rel32_from_cmdline)
3956 /* Equal to MAX_PRECISION in atof-ieee.c */
3957 #define MAX_LITTLENUMS 6
3959 /* Turn a string in input_line_pointer into a floating point constant
3960 of type type, and store the appropriate bytes in *litP. The number
3961 of LITTLENUMS emitted is stored in *sizeP . An error message is
3962 returned, or NULL on OK. */
3965 md_atof (type, litP, sizeP)
3971 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3972 LITTLENUM_TYPE *wordP;
4003 return _("Bad call to MD_ATOF()");
4005 t = atof_ieee (input_line_pointer, type, words);
4007 input_line_pointer = t;
4009 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4010 for (wordP = words; prec--;)
4012 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4013 litP += sizeof (LITTLENUM_TYPE);
4019 md_number_to_chars (buf, val, n)
4024 number_to_chars_bigendian (buf, val, n);
4028 md_apply_fix_2 (fixP, val)
4032 addressT upper_limit;
4033 offsetT lower_limit;
4035 /* This is unnecessary but it convinces the native rs6000 compiler
4036 to generate the code we want. */
4037 char *buf = fixP->fx_frag->fr_literal;
4038 buf += fixP->fx_where;
4039 /* end ibm compiler workaround */
4041 if (val & 0x80000000)
4042 val |= ~(addressT)0x7fffffff;
4049 memset (buf, 0, fixP->fx_size);
4050 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4052 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4053 && !S_IS_DEFINED (fixP->fx_addsy)
4054 && !S_IS_WEAK (fixP->fx_addsy))
4055 S_SET_WEAK (fixP->fx_addsy);
4060 #ifdef BFD_ASSEMBLER
4061 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4062 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4066 switch (fixP->fx_size)
4068 /* The cast to offsetT below are necessary to make code correct for
4069 machines where ints are smaller than offsetT */
4073 lower_limit = - (offsetT) 0x80;
4076 *buf++ = (val >> 8);
4078 upper_limit = 0x7fff;
4079 lower_limit = - (offsetT) 0x8000;
4082 *buf++ = (val >> 24);
4083 *buf++ = (val >> 16);
4084 *buf++ = (val >> 8);
4086 upper_limit = 0x7fffffff;
4087 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4090 BAD_CASE (fixP->fx_size);
4093 /* Fix up a negative reloc. */
4094 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4096 fixP->fx_addsy = fixP->fx_subsy;
4097 fixP->fx_subsy = NULL;
4101 /* For non-pc-relative values, it's conceivable we might get something
4102 like "0xff" for a byte field. So extend the upper part of the range
4103 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4104 so that we can do any range checking at all. */
4105 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4106 upper_limit = upper_limit * 2 + 1;
4108 if ((addressT) val > upper_limit
4109 && (val > 0 || val < lower_limit))
4110 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4112 /* A one byte PC-relative reloc means a short branch. We can't use
4113 a short branch with a value of 0 or -1, because those indicate
4114 different opcodes (branches with longer offsets). fixup_segment
4115 in write.c may have clobbered fx_pcrel, so we need to examine the
4118 #ifdef BFD_ASSEMBLER
4119 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4122 && fixP->fx_size == 1
4123 && (fixP->fx_addsy == NULL
4124 || S_IS_DEFINED (fixP->fx_addsy))
4125 && (val == 0 || val == -1))
4126 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4129 #ifdef BFD_ASSEMBLER
4131 md_apply_fix (fixP, valp)
4135 md_apply_fix_2 (fixP, (addressT) *valp);
4139 void md_apply_fix (fixP, val)
4143 md_apply_fix_2 (fixP, (addressT) val);
4147 /* *fragP has been relaxed to its final size, and now needs to have
4148 the bytes inside it modified to conform to the new size There is UGLY
4152 md_convert_frag_1 (fragP)
4153 register fragS *fragP;
4159 /* Address in object code of the displacement. */
4160 register int object_address = fragP->fr_fix + fragP->fr_address;
4162 /* Address in gas core of the place to store the displacement. */
4163 /* This convinces the native rs6000 compiler to generate the code we
4165 register char *buffer_address = fragP->fr_literal;
4166 buffer_address += fragP->fr_fix;
4167 /* end ibm compiler workaround */
4169 /* The displacement of the address, from current location. */
4170 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4171 disp = (disp + fragP->fr_offset) - object_address;
4173 #ifdef BFD_ASSEMBLER
4174 disp += fragP->fr_symbol->sy_frag->fr_address;
4177 switch (fragP->fr_subtype)
4179 case TAB (BCC68000, BYTE):
4180 case TAB (ABRANCH, BYTE):
4181 know (issbyte (disp));
4183 as_bad (_("short branch with zero offset: use :w"));
4184 fragP->fr_opcode[1] = disp;
4187 case TAB (DBCC, SHORT):
4188 know (issword (disp));
4191 case TAB (BCC68000, SHORT):
4192 case TAB (ABRANCH, SHORT):
4193 know (issword (disp));
4194 fragP->fr_opcode[1] = 0x00;
4197 case TAB (ABRANCH, LONG):
4198 if (!HAVE_LONG_BRANCH(current_architecture))
4200 if (fragP->fr_opcode[0] == 0x61)
4203 fragP->fr_opcode[0] = 0x4E;
4204 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4218 else if (fragP->fr_opcode[0] == 0x60)
4220 fragP->fr_opcode[0] = 0x4E;
4221 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4222 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4223 fragP->fr_offset, 0, NO_RELOC);
4229 as_bad (_("Long branch offset not supported."));
4234 fragP->fr_opcode[1] = (char) 0xff;
4238 case TAB (BCC68000, LONG):
4239 /* only Bcc 68000 instructions can come here */
4240 /* change bcc into b!cc/jmp absl long */
4241 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4242 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4244 /* JF: these used to be fr_opcode[2,3], but they may be in a
4245 different frag, in which case refering to them is a no-no.
4246 Only fr_opcode[0,1] are guaranteed to work. */
4247 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4248 *buffer_address++ = (char) 0xf9;
4249 fragP->fr_fix += 2; /* account for jmp instruction */
4250 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4251 fragP->fr_offset, 0, NO_RELOC);
4255 case TAB (DBCC, LONG):
4256 /* only DBcc 68000 instructions can come here */
4257 /* change dbcc into dbcc/jmp absl long */
4258 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4259 *buffer_address++ = 0x00; /* branch offset = 4 */
4260 *buffer_address++ = 0x04;
4261 *buffer_address++ = 0x60; /* put in bra pc+6 */
4262 *buffer_address++ = 0x06;
4263 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4264 *buffer_address++ = (char) 0xf9;
4266 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4267 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4268 fragP->fr_offset, 0, NO_RELOC);
4272 case TAB (FBRANCH, SHORT):
4273 know ((fragP->fr_opcode[1] & 0x40) == 0);
4276 case TAB (FBRANCH, LONG):
4277 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4280 case TAB (PCREL, SHORT):
4283 case TAB (PCREL, LONG):
4284 /* The thing to do here is force it to ABSOLUTE LONG, since
4285 PCREL is really trying to shorten an ABSOLUTE address anyway */
4286 /* JF FOO This code has not been tested */
4287 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4289 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4290 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4291 (unsigned) fragP->fr_opcode[0],
4292 (unsigned long) fragP->fr_address);
4293 fragP->fr_opcode[1] &= ~0x3F;
4294 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4298 case TAB (PCLEA, SHORT):
4299 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4300 fragP->fr_offset, 1, NO_RELOC);
4301 fragP->fr_opcode[1] &= ~0x3F;
4302 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4305 case TAB (PCLEA, LONG):
4306 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4307 fragP->fr_offset, 1, NO_RELOC);
4308 fixP->fx_pcrel_adjust = 2;
4309 /* Already set to mode 7.3; this indicates: PC indirect with
4310 suppressed index, 32-bit displacement. */
4311 *buffer_address++ = 0x01;
4312 *buffer_address++ = 0x70;
4317 case TAB (PCINDEX, BYTE):
4319 if (!issbyte (disp))
4321 as_bad (_("displacement doesn't fit in one byte"));
4324 assert (fragP->fr_fix >= 2);
4325 buffer_address[-2] &= ~1;
4326 buffer_address[-1] = disp;
4329 case TAB (PCINDEX, SHORT):
4331 assert (issword (disp));
4332 assert (fragP->fr_fix >= 2);
4333 buffer_address[-2] |= 0x1;
4334 buffer_address[-1] = 0x20;
4335 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4336 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4338 fixP->fx_pcrel_adjust = 2;
4341 case TAB (PCINDEX, LONG):
4343 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4344 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4346 fixP->fx_pcrel_adjust = 2;
4347 assert (fragP->fr_fix >= 2);
4348 buffer_address[-2] |= 0x1;
4349 buffer_address[-1] = 0x30;
4356 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4357 fragP->fr_fix += ext;
4361 #ifndef BFD_ASSEMBLER
4364 md_convert_frag (headers, sec, fragP)
4365 object_headers *headers;
4369 md_convert_frag_1 (fragP);
4375 md_convert_frag (abfd, sec, fragP)
4380 md_convert_frag_1 (fragP);
4384 /* Force truly undefined symbols to their maximum size, and generally set up
4385 the frag list to be relaxed
4388 md_estimate_size_before_relax (fragP, segment)
4389 register fragS *fragP;
4393 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4395 old_fix = fragP->fr_fix;
4397 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4398 switch (fragP->fr_subtype)
4401 case TAB (ABRANCH, SZ_UNDEF):
4403 if ((fragP->fr_symbol != NULL) /* Not absolute */
4404 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4405 && relaxable_symbol (fragP->fr_symbol))
4407 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4410 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4412 /* On 68000, or for absolute value, switch to abs long */
4413 /* FIXME, we should check abs val, pick short or long */
4414 if (fragP->fr_opcode[0] == 0x61)
4416 fragP->fr_opcode[0] = 0x4E;
4417 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4418 fix_new (fragP, fragP->fr_fix, 4,
4419 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4423 else if (fragP->fr_opcode[0] == 0x60)
4425 fragP->fr_opcode[0] = 0x4E;
4426 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4427 fix_new (fragP, fragP->fr_fix, 4,
4428 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4434 as_warn (_("Long branch offset to extern symbol not supported."));
4438 { /* Symbol is still undefined. Make it simple */
4439 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4440 fragP->fr_offset, 1, NO_RELOC);
4442 fragP->fr_opcode[1] = (char) 0xff;
4448 } /* case TAB(ABRANCH,SZ_UNDEF) */
4450 case TAB (FBRANCH, SZ_UNDEF):
4452 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4453 && relaxable_symbol (fragP->fr_symbol))
4456 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4461 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4462 fragP->fr_offset, 1, NO_RELOC);
4464 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4468 } /* TAB(FBRANCH,SZ_UNDEF) */
4470 case TAB (PCREL, SZ_UNDEF):
4472 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4473 && relaxable_symbol (fragP->fr_symbol))
4475 || cpu_of_arch (current_architecture) < m68020
4476 || cpu_of_arch (current_architecture) == mcf5200)
4478 fragP->fr_subtype = TAB (PCREL, SHORT);
4483 fragP->fr_subtype = TAB (PCREL, LONG);
4487 } /* TAB(PCREL,SZ_UNDEF) */
4489 case TAB (BCC68000, SZ_UNDEF):
4491 if ((fragP->fr_symbol != NULL)
4492 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4493 && relaxable_symbol (fragP->fr_symbol))
4495 fragP->fr_subtype = TAB (BCC68000, BYTE);
4498 /* only Bcc 68000 instructions can come here */
4499 /* change bcc into b!cc/jmp absl long */
4500 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4501 if (flag_short_refs)
4503 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4504 /* JF: these were fr_opcode[2,3] */
4505 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4506 buffer_address[1] = (char) 0xf8;
4507 fragP->fr_fix += 2; /* account for jmp instruction */
4508 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4509 fragP->fr_offset, 0, NO_RELOC);
4514 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4515 /* JF: these were fr_opcode[2,3] */
4516 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4517 buffer_address[1] = (char) 0xf9;
4518 fragP->fr_fix += 2; /* account for jmp instruction */
4519 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4520 fragP->fr_offset, 0, NO_RELOC);
4525 } /* case TAB(BCC68000,SZ_UNDEF) */
4527 case TAB (DBCC, SZ_UNDEF):
4529 if (fragP->fr_symbol != NULL
4530 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4531 && relaxable_symbol (fragP->fr_symbol))
4533 fragP->fr_subtype = TAB (DBCC, SHORT);
4537 /* only DBcc 68000 instructions can come here */
4538 /* change dbcc into dbcc/jmp absl long */
4539 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4540 buffer_address[0] = 0x00; /* branch offset = 4 */
4541 buffer_address[1] = 0x04;
4542 buffer_address[2] = 0x60; /* put in bra pc + ... */
4544 if (flag_short_refs)
4546 /* JF: these were fr_opcode[5-7] */
4547 buffer_address[3] = 0x04; /* plus 4 */
4548 buffer_address[4] = 0x4e; /* Put in Jump Word */
4549 buffer_address[5] = (char) 0xf8;
4550 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4551 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4552 fragP->fr_offset, 0, NO_RELOC);
4557 /* JF: these were fr_opcode[5-7] */
4558 buffer_address[3] = 0x06; /* Plus 6 */
4559 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4560 buffer_address[5] = (char) 0xf9;
4561 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4562 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4563 fragP->fr_offset, 0, NO_RELOC);
4569 } /* case TAB(DBCC,SZ_UNDEF) */
4571 case TAB (PCLEA, SZ_UNDEF):
4573 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4574 && relaxable_symbol (fragP->fr_symbol))
4576 || cpu_of_arch (current_architecture) < m68020
4577 || cpu_of_arch (current_architecture) == mcf5200)
4579 fragP->fr_subtype = TAB (PCLEA, SHORT);
4584 fragP->fr_subtype = TAB (PCLEA, LONG);
4588 } /* TAB(PCLEA,SZ_UNDEF) */
4590 case TAB (PCINDEX, SZ_UNDEF):
4591 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4592 && relaxable_symbol (fragP->fr_symbol))
4593 || cpu_of_arch (current_architecture) < m68020
4594 || cpu_of_arch (current_architecture) == mcf5200)
4596 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4600 fragP->fr_subtype = TAB (PCINDEX, LONG);
4609 /* now that SZ_UNDEF are taken care of, check others */
4610 switch (fragP->fr_subtype)
4612 case TAB (BCC68000, BYTE):
4613 case TAB (ABRANCH, BYTE):
4614 /* We can't do a short jump to the next instruction, so in that
4615 case we force word mode. At this point S_GET_VALUE should
4616 return the offset of the symbol within its frag. If the
4617 symbol is at the start of a frag, and it is the next frag
4618 with any data in it (usually this is just the next frag, but
4619 assembler listings may introduce empty frags), we must use
4621 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4625 for (l = fragP->fr_next;
4626 l != fragP->fr_symbol->sy_frag;
4628 if (l->fr_fix + l->fr_var != 0)
4630 if (l == fragP->fr_symbol->sy_frag)
4632 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4640 return fragP->fr_var + fragP->fr_fix - old_fix;
4643 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4644 /* the bit-field entries in the relocation_info struct plays hell
4645 with the byte-order problems of cross-assembly. So as a hack,
4646 I added this mach. dependent ri twiddler. Ugly, but it gets
4648 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4649 are symbolnum, most sig. byte first. Last byte is broken up with
4650 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4651 nibble as nuthin. (on Sun 3 at least) */
4652 /* Translate the internal relocation information into target-specific
4656 md_ri_to_chars (the_bytes, ri)
4658 struct reloc_info_generic *ri;
4661 md_number_to_chars (the_bytes, ri->r_address, 4);
4662 /* now the fun stuff */
4663 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4664 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4665 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4666 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4667 ((ri->r_extern << 4) & 0x10));
4670 #endif /* comment */
4672 #ifndef BFD_ASSEMBLER
4674 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4677 relax_addressT segment_address_in_file;
4680 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4681 * Out: GNU LD relocation length code: 0, 1, or 2.
4684 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4687 know (fixP->fx_addsy != NULL);
4689 md_number_to_chars (where,
4690 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4693 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4694 ? S_GET_TYPE (fixP->fx_addsy)
4695 : fixP->fx_addsy->sy_number);
4697 where[4] = (r_symbolnum >> 16) & 0x0ff;
4698 where[5] = (r_symbolnum >> 8) & 0x0ff;
4699 where[6] = r_symbolnum & 0x0ff;
4700 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4701 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4705 #endif /* OBJ_AOUT or OBJ_BOUT */
4707 #ifndef WORKING_DOT_WORD
4708 CONST int md_short_jump_size = 4;
4709 CONST int md_long_jump_size = 6;
4712 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4714 addressT from_addr, to_addr;
4720 offset = to_addr - (from_addr + 2);
4722 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4723 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4727 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4729 addressT from_addr, to_addr;
4735 if (!HAVE_LONG_BRANCH(current_architecture))
4737 offset = to_addr - S_GET_VALUE (to_symbol);
4738 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4739 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4740 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4745 offset = to_addr - (from_addr + 2);
4746 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4747 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4753 /* Different values of OK tell what its OK to return. Things that
4754 aren't OK are an error (what a shock, no?)
4757 10: Absolute 1:8 only
4758 20: Absolute 0:7 only
4759 30: absolute 0:15 only
4760 40: Absolute 0:31 only
4761 50: absolute 0:127 only
4762 55: absolute -64:63 only
4763 60: absolute -128:127 only
4764 70: absolute 0:4095 only
4771 struct m68k_exp *exp;
4774 if (exp->exp.X_op == O_absent)
4776 /* Do the same thing the VAX asm does */
4777 op (exp) = O_constant;
4783 as_warn (_("expression out of range: defaulting to 1"));
4787 else if (exp->exp.X_op == O_constant)
4792 if (offs (exp) < 1 || offs (exp) > 8)
4794 as_warn (_("expression out of range: defaulting to 1"));
4799 if (offs (exp) < 0 || offs (exp) > 7)
4803 if (offs (exp) < 0 || offs (exp) > 15)
4807 if (offs (exp) < 0 || offs (exp) > 32)
4811 if (offs (exp) < 0 || offs (exp) > 127)
4815 if (offs (exp) < -64 || offs (exp) > 63)
4819 if (offs (exp) < -128 || offs (exp) > 127)
4823 if (offs (exp) < 0 || offs (exp) > 4095)
4826 as_warn (_("expression out of range: defaulting to 0"));
4834 else if (exp->exp.X_op == O_big)
4836 if (offs (exp) <= 0 /* flonum */
4837 && (ok == 80 /* no bignums */
4838 || (ok > 10 /* small-int ranges including 0 ok */
4839 /* If we have a flonum zero, a zero integer should
4840 do as well (e.g., in moveq). */
4841 && generic_floating_point_number.exponent == 0
4842 && generic_floating_point_number.low[0] == 0)))
4844 /* HACK! Turn it into a long */
4845 LITTLENUM_TYPE words[6];
4847 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4848 op (exp) = O_constant;
4851 offs (exp) = words[1] | (words[0] << 16);
4855 op (exp) = O_constant;
4858 offs (exp) = (ok == 10) ? 1 : 0;
4859 as_warn (_("Can't deal with expression; defaulting to %ld"),
4865 if (ok >= 10 && ok <= 70)
4867 op (exp) = O_constant;
4870 offs (exp) = (ok == 10) ? 1 : 0;
4871 as_warn (_("Can't deal with expression; defaulting to %ld"),
4876 if (exp->size != SIZE_UNSPEC)
4884 if (!isbyte (offs (exp)))
4885 as_warn (_("expression doesn't fit in BYTE"));
4888 if (!isword (offs (exp)))
4889 as_warn (_("expression doesn't fit in WORD"));
4897 /* These are the back-ends for the various machine dependent pseudo-ops. */
4903 subseg_set (data_section, 1);
4904 demand_empty_rest_of_line ();
4911 subseg_set (data_section, 2);
4912 demand_empty_rest_of_line ();
4919 /* We don't support putting frags in the BSS segment, we fake it
4920 by marking in_bss, then looking at s_skip for clues. */
4922 subseg_set (bss_section, 0);
4923 demand_empty_rest_of_line ();
4931 register long temp_fill;
4933 temp = 1; /* JF should be 2? */
4934 temp_fill = get_absolute_expression ();
4935 if (!need_pass_2) /* Never make frag if expect extra pass. */
4936 frag_align (temp, (int) temp_fill, 0);
4937 demand_empty_rest_of_line ();
4938 record_alignment (now_seg, temp);
4945 demand_empty_rest_of_line ();
4948 /* Pseudo-ops handled for MRI compatibility. */
4950 /* This function returns non-zero if the argument is a conditional
4951 pseudo-op. This is called when checking whether a pending
4952 alignment is needed. */
4955 m68k_conditional_pseudoop (pop)
4958 return (pop->poc_handler == s_mri_if
4959 || pop->poc_handler == s_mri_else);
4962 /* Handle an MRI style chip specification. */
4971 s = input_line_pointer;
4972 /* We can't use get_symbol_end since the processor names are not proper
4974 while (is_part_of_name (c = *input_line_pointer++))
4976 *--input_line_pointer = 0;
4977 for (i = 0; i < n_archs; i++)
4978 if (strcasecmp (s, archs[i].name) == 0)
4982 as_bad (_("%s: unrecognized processor name"), s);
4983 *input_line_pointer = c;
4984 ignore_rest_of_line ();
4987 *input_line_pointer = c;
4989 if (*input_line_pointer == '/')
4990 current_architecture = 0;
4992 current_architecture &= m68881 | m68851;
4993 current_architecture |= archs[i].arch;
4995 while (*input_line_pointer == '/')
4997 ++input_line_pointer;
4998 s = input_line_pointer;
4999 /* We can't use get_symbol_end since the processor names are not
5001 while (is_part_of_name (c = *input_line_pointer++))
5003 *--input_line_pointer = 0;
5004 if (strcmp (s, "68881") == 0)
5005 current_architecture |= m68881;
5006 else if (strcmp (s, "68851") == 0)
5007 current_architecture |= m68851;
5008 *input_line_pointer = c;
5011 /* Update info about available control registers. */
5012 select_control_regs ();
5015 /* The MRI CHIP pseudo-op. */
5025 stop = mri_comment_field (&stopc);
5028 mri_comment_end (stop, stopc);
5029 demand_empty_rest_of_line ();
5032 /* The MRI FOPT pseudo-op. */
5040 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5044 input_line_pointer += 3;
5045 temp = get_absolute_expression ();
5046 if (temp < 0 || temp > 7)
5047 as_bad (_("bad coprocessor id"));
5049 m68k_float_copnum = COP0 + temp;
5053 as_bad (_("unrecognized fopt option"));
5054 ignore_rest_of_line ();
5058 demand_empty_rest_of_line ();
5061 /* The structure used to handle the MRI OPT pseudo-op. */
5065 /* The name of the option. */
5068 /* If this is not NULL, just call this function. The first argument
5069 is the ARG field of this structure, the second argument is
5070 whether the option was negated. */
5071 void (*pfn) PARAMS ((int arg, int on));
5073 /* If this is not NULL, and the PFN field is NULL, set the variable
5074 this points to. Set it to the ARG field if the option was not
5075 negated, and the NOTARG field otherwise. */
5078 /* The value to pass to PFN or to assign to *PVAR. */
5081 /* The value to assign to *PVAR if the option is negated. If PFN is
5082 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5083 the option may not be negated. */
5087 /* The table used to handle the MRI OPT pseudo-op. */
5089 static void skip_to_comma PARAMS ((int, int));
5090 static void opt_nest PARAMS ((int, int));
5091 static void opt_chip PARAMS ((int, int));
5092 static void opt_list PARAMS ((int, int));
5093 static void opt_list_symbols PARAMS ((int, int));
5095 static const struct opt_action opt_table[] =
5097 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5099 /* We do relaxing, so there is little use for these options. */
5100 { "b", 0, 0, 0, 0 },
5101 { "brs", 0, 0, 0, 0 },
5102 { "brb", 0, 0, 0, 0 },
5103 { "brl", 0, 0, 0, 0 },
5104 { "brw", 0, 0, 0, 0 },
5106 { "c", 0, 0, 0, 0 },
5107 { "cex", 0, 0, 0, 0 },
5108 { "case", 0, &symbols_case_sensitive, 1, 0 },
5109 { "cl", 0, 0, 0, 0 },
5110 { "cre", 0, 0, 0, 0 },
5111 { "d", 0, &flag_keep_locals, 1, 0 },
5112 { "e", 0, 0, 0, 0 },
5113 { "f", 0, &flag_short_refs, 1, 0 },
5114 { "frs", 0, &flag_short_refs, 1, 0 },
5115 { "frl", 0, &flag_short_refs, 0, 1 },
5116 { "g", 0, 0, 0, 0 },
5117 { "i", 0, 0, 0, 0 },
5118 { "m", 0, 0, 0, 0 },
5119 { "mex", 0, 0, 0, 0 },
5120 { "mc", 0, 0, 0, 0 },
5121 { "md", 0, 0, 0, 0 },
5122 { "nest", opt_nest, 0, 0, 0 },
5123 { "next", skip_to_comma, 0, 0, 0 },
5124 { "o", 0, 0, 0, 0 },
5125 { "old", 0, 0, 0, 0 },
5126 { "op", skip_to_comma, 0, 0, 0 },
5127 { "pco", 0, 0, 0, 0 },
5128 { "p", opt_chip, 0, 0, 0 },
5129 { "pcr", 0, 0, 0, 0 },
5130 { "pcs", 0, 0, 0, 0 },
5131 { "r", 0, 0, 0, 0 },
5132 { "quick", 0, &m68k_quick, 1, 0 },
5133 { "rel32", 0, &m68k_rel32, 1, 0 },
5134 { "s", opt_list, 0, 0, 0 },
5135 { "t", opt_list_symbols, 0, 0, 0 },
5136 { "w", 0, &flag_no_warnings, 0, 1 },
5140 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5142 /* The MRI OPT pseudo-op. */
5154 const struct opt_action *o;
5159 if (*input_line_pointer == '-')
5161 ++input_line_pointer;
5164 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5166 input_line_pointer += 2;
5170 s = input_line_pointer;
5171 c = get_symbol_end ();
5173 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5175 if (strcasecmp (s, o->name) == 0)
5179 /* Restore input_line_pointer now in case the option
5181 *input_line_pointer = c;
5182 (*o->pfn) (o->arg, t);
5184 else if (o->pvar != NULL)
5186 if (! t && o->arg == o->notarg)
5187 as_bad (_("option `%s' may not be negated"), s);
5188 *input_line_pointer = c;
5189 *o->pvar = t ? o->arg : o->notarg;
5192 *input_line_pointer = c;
5198 as_bad (_("option `%s' not recognized"), s);
5199 *input_line_pointer = c;
5202 while (*input_line_pointer++ == ',');
5204 /* Move back to terminating character. */
5205 --input_line_pointer;
5206 demand_empty_rest_of_line ();
5209 /* Skip ahead to a comma. This is used for OPT options which we do
5210 not suppor tand which take arguments. */
5213 skip_to_comma (arg, on)
5217 while (*input_line_pointer != ','
5218 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5219 ++input_line_pointer;
5222 /* Handle the OPT NEST=depth option. */
5229 if (*input_line_pointer != '=')
5231 as_bad (_("bad format of OPT NEST=depth"));
5235 ++input_line_pointer;
5236 max_macro_nest = get_absolute_expression ();
5239 /* Handle the OPT P=chip option. */
5246 if (*input_line_pointer != '=')
5248 /* This is just OPT P, which we do not support. */
5252 ++input_line_pointer;
5256 /* Handle the OPT S option. */
5266 /* Handle the OPT T option. */
5269 opt_list_symbols (arg, on)
5274 listing |= LISTING_SYMBOLS;
5276 listing &=~ LISTING_SYMBOLS;
5279 /* Handle the MRI REG pseudo-op. */
5292 if (line_label == NULL)
5294 as_bad (_("missing label"));
5295 ignore_rest_of_line ();
5300 stop = mri_comment_field (&stopc);
5304 s = input_line_pointer;
5305 while (isalnum ((unsigned char) *input_line_pointer)
5306 #ifdef REGISTER_PREFIX
5307 || *input_line_pointer == REGISTER_PREFIX
5309 || *input_line_pointer == '/'
5310 || *input_line_pointer == '-')
5311 ++input_line_pointer;
5312 c = *input_line_pointer;
5313 *input_line_pointer = '\0';
5315 if (m68k_ip_op (s, &rop) != 0)
5317 if (rop.error == NULL)
5318 as_bad (_("bad register list"));
5320 as_bad (_("bad register list: %s"), rop.error);
5321 *input_line_pointer = c;
5322 ignore_rest_of_line ();
5326 *input_line_pointer = c;
5328 if (rop.mode == REGLST)
5330 else if (rop.mode == DREG)
5331 mask = 1 << (rop.reg - DATA0);
5332 else if (rop.mode == AREG)
5333 mask = 1 << (rop.reg - ADDR0 + 8);
5334 else if (rop.mode == FPREG)
5335 mask = 1 << (rop.reg - FP0 + 16);
5336 else if (rop.mode == CONTROL
5339 else if (rop.mode == CONTROL
5342 else if (rop.mode == CONTROL
5347 as_bad (_("bad register list"));
5348 ignore_rest_of_line ();
5352 S_SET_SEGMENT (line_label, reg_section);
5353 S_SET_VALUE (line_label, ~mask);
5354 line_label->sy_frag = &zero_address_frag;
5357 mri_comment_end (stop, stopc);
5359 demand_empty_rest_of_line ();
5362 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5366 struct save_opts *next;
5368 int symbols_case_sensitive;
5376 /* FIXME: We don't save OPT S. */
5379 /* This variable holds the stack of saved options. */
5381 static struct save_opts *save_stack;
5383 /* The MRI SAVE pseudo-op. */
5389 struct save_opts *s;
5391 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5392 s->abspcadd = m68k_abspcadd;
5393 s->symbols_case_sensitive = symbols_case_sensitive;
5394 s->keep_locals = flag_keep_locals;
5395 s->short_refs = flag_short_refs;
5396 s->architecture = current_architecture;
5397 s->quick = m68k_quick;
5398 s->rel32 = m68k_rel32;
5399 s->listing = listing;
5400 s->no_warnings = flag_no_warnings;
5402 s->next = save_stack;
5405 demand_empty_rest_of_line ();
5408 /* The MRI RESTORE pseudo-op. */
5414 struct save_opts *s;
5416 if (save_stack == NULL)
5418 as_bad (_("restore without save"));
5419 ignore_rest_of_line ();
5424 save_stack = s->next;
5426 m68k_abspcadd = s->abspcadd;
5427 symbols_case_sensitive = s->symbols_case_sensitive;
5428 flag_keep_locals = s->keep_locals;
5429 flag_short_refs = s->short_refs;
5430 current_architecture = s->architecture;
5431 m68k_quick = s->quick;
5432 m68k_rel32 = s->rel32;
5433 listing = s->listing;
5434 flag_no_warnings = s->no_warnings;
5438 demand_empty_rest_of_line ();
5441 /* Types of MRI structured control directives. */
5443 enum mri_control_type
5451 /* This structure is used to stack the MRI structured control
5454 struct mri_control_info
5456 /* The directive within which this one is enclosed. */
5457 struct mri_control_info *outer;
5459 /* The type of directive. */
5460 enum mri_control_type type;
5462 /* Whether an ELSE has been in an IF. */
5465 /* The add or sub statement at the end of a FOR. */
5468 /* The label of the top of a FOR or REPEAT loop. */
5471 /* The label to jump to for the next iteration, or the else
5472 expression of a conditional. */
5475 /* The label to jump to to break out of the loop, or the label past
5476 the end of a conditional. */
5480 /* The stack of MRI structured control directives. */
5482 static struct mri_control_info *mri_control_stack;
5484 /* The current MRI structured control directive index number, used to
5485 generate label names. */
5487 static int mri_control_index;
5489 /* Some function prototypes. */
5491 static void mri_assemble PARAMS ((char *));
5492 static char *mri_control_label PARAMS ((void));
5493 static struct mri_control_info *push_mri_control
5494 PARAMS ((enum mri_control_type));
5495 static void pop_mri_control PARAMS ((void));
5496 static int parse_mri_condition PARAMS ((int *));
5497 static int parse_mri_control_operand
5498 PARAMS ((int *, char **, char **, char **, char **));
5499 static int swap_mri_condition PARAMS ((int));
5500 static int reverse_mri_condition PARAMS ((int));
5501 static void build_mri_control_operand
5502 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5503 const char *, int));
5504 static void parse_mri_control_expression
5505 PARAMS ((char *, int, const char *, const char *, int));
5507 /* Assemble an instruction for an MRI structured control directive. */
5515 /* md_assemble expects the opcode to be in lower case. */
5516 for (s = str; *s != ' ' && *s != '\0'; s++)
5518 if (isupper ((unsigned char) *s))
5519 *s = tolower ((unsigned char) *s);
5525 /* Generate a new MRI label structured control directive label name. */
5528 mri_control_label ()
5532 n = (char *) xmalloc (20);
5533 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5534 ++mri_control_index;
5538 /* Create a new MRI structured control directive. */
5540 static struct mri_control_info *
5541 push_mri_control (type)
5542 enum mri_control_type type;
5544 struct mri_control_info *n;
5546 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5550 if (type == mri_if || type == mri_while)
5553 n->top = mri_control_label ();
5554 n->next = mri_control_label ();
5555 n->bottom = mri_control_label ();
5557 n->outer = mri_control_stack;
5558 mri_control_stack = n;
5563 /* Pop off the stack of MRI structured control directives. */
5568 struct mri_control_info *n;
5570 n = mri_control_stack;
5571 mri_control_stack = n->outer;
5579 /* Recognize a condition code in an MRI structured control expression. */
5582 parse_mri_condition (pcc)
5587 know (*input_line_pointer == '<');
5589 ++input_line_pointer;
5590 c1 = *input_line_pointer++;
5591 c2 = *input_line_pointer++;
5593 if (*input_line_pointer != '>')
5595 as_bad (_("syntax error in structured control directive"));
5599 ++input_line_pointer;
5607 *pcc = (c1 << 8) | c2;
5612 /* Parse a single operand in an MRI structured control expression. */
5615 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5632 if (*input_line_pointer == '<')
5634 /* It's just a condition code. */
5635 return parse_mri_condition (pcc);
5638 /* Look ahead for the condition code. */
5639 for (s = input_line_pointer; *s != '\0'; ++s)
5641 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5646 as_bad (_("missing condition code in structured control directive"));
5650 *leftstart = input_line_pointer;
5652 if (*leftstop > *leftstart
5653 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5656 input_line_pointer = s;
5657 if (! parse_mri_condition (pcc))
5660 /* Look ahead for AND or OR or end of line. */
5661 for (s = input_line_pointer; *s != '\0'; ++s)
5663 if ((strncasecmp (s, "AND", 3) == 0
5664 && (s[3] == '.' || ! is_part_of_name (s[3])))
5665 || (strncasecmp (s, "OR", 2) == 0
5666 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5670 *rightstart = input_line_pointer;
5672 if (*rightstop > *rightstart
5673 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5676 input_line_pointer = s;
5681 #define MCC(b1, b2) (((b1) << 8) | (b2))
5683 /* Swap the sense of a condition. This changes the condition so that
5684 it generates the same result when the operands are swapped. */
5687 swap_mri_condition (cc)
5692 case MCC ('h', 'i'): return MCC ('c', 's');
5693 case MCC ('l', 's'): return MCC ('c', 'c');
5694 case MCC ('c', 'c'): return MCC ('l', 's');
5695 case MCC ('c', 's'): return MCC ('h', 'i');
5696 case MCC ('p', 'l'): return MCC ('m', 'i');
5697 case MCC ('m', 'i'): return MCC ('p', 'l');
5698 case MCC ('g', 'e'): return MCC ('l', 'e');
5699 case MCC ('l', 't'): return MCC ('g', 't');
5700 case MCC ('g', 't'): return MCC ('l', 't');
5701 case MCC ('l', 'e'): return MCC ('g', 'e');
5706 /* Reverse the sense of a condition. */
5709 reverse_mri_condition (cc)
5714 case MCC ('h', 'i'): return MCC ('l', 's');
5715 case MCC ('l', 's'): return MCC ('h', 'i');
5716 case MCC ('c', 'c'): return MCC ('c', 's');
5717 case MCC ('c', 's'): return MCC ('c', 'c');
5718 case MCC ('n', 'e'): return MCC ('e', 'q');
5719 case MCC ('e', 'q'): return MCC ('n', 'e');
5720 case MCC ('v', 'c'): return MCC ('v', 's');
5721 case MCC ('v', 's'): return MCC ('v', 'c');
5722 case MCC ('p', 'l'): return MCC ('m', 'i');
5723 case MCC ('m', 'i'): return MCC ('p', 'l');
5724 case MCC ('g', 'e'): return MCC ('l', 't');
5725 case MCC ('l', 't'): return MCC ('g', 'e');
5726 case MCC ('g', 't'): return MCC ('l', 'e');
5727 case MCC ('l', 'e'): return MCC ('g', 't');
5732 /* Build an MRI structured control expression. This generates test
5733 and branch instructions. It goes to TRUELAB if the condition is
5734 true, and to FALSELAB if the condition is false. Exactly one of
5735 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5736 is the size qualifier for the expression. EXTENT is the size to
5737 use for the branch. */
5740 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5741 rightstop, truelab, falselab, extent)
5748 const char *truelab;
5749 const char *falselab;
5755 if (leftstart != NULL)
5757 struct m68k_op leftop, rightop;
5760 /* Swap the compare operands, if necessary, to produce a legal
5761 m68k compare instruction. Comparing a register operand with
5762 a non-register operand requires the register to be on the
5763 right (cmp, cmpa). Comparing an immediate value with
5764 anything requires the immediate value to be on the left
5769 (void) m68k_ip_op (leftstart, &leftop);
5774 (void) m68k_ip_op (rightstart, &rightop);
5777 if (rightop.mode == IMMED
5778 || ((leftop.mode == DREG || leftop.mode == AREG)
5779 && (rightop.mode != DREG && rightop.mode != AREG)))
5783 cc = swap_mri_condition (cc);
5785 leftstart = rightstart;
5788 leftstop = rightstop;
5793 if (truelab == NULL)
5795 cc = reverse_mri_condition (cc);
5799 if (leftstart != NULL)
5801 buf = (char *) xmalloc (20
5802 + (leftstop - leftstart)
5803 + (rightstop - rightstart));
5811 memcpy (s, leftstart, leftstop - leftstart);
5812 s += leftstop - leftstart;
5814 memcpy (s, rightstart, rightstop - rightstart);
5815 s += rightstop - rightstart;
5821 buf = (char *) xmalloc (20 + strlen (truelab));
5829 strcpy (s, truelab);
5834 /* Parse an MRI structured control expression. This generates test
5835 and branch instructions. STOP is where the expression ends. It
5836 goes to TRUELAB if the condition is true, and to FALSELAB if the
5837 condition is false. Exactly one of TRUELAB and FALSELAB will be
5838 NULL, meaning to fall through. QUAL is the size qualifier for the
5839 expression. EXTENT is the size to use for the branch. */
5842 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5845 const char *truelab;
5846 const char *falselab;
5859 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5860 &rightstart, &rightstop))
5866 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5870 if (falselab != NULL)
5873 flab = mri_control_label ();
5875 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5876 rightstop, (const char *) NULL, flab, extent);
5878 input_line_pointer += 3;
5879 if (*input_line_pointer != '.'
5880 || input_line_pointer[1] == '\0')
5884 qual = input_line_pointer[1];
5885 input_line_pointer += 2;
5888 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5889 &rightstart, &rightstop))
5895 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5896 rightstop, truelab, falselab, extent);
5898 if (falselab == NULL)
5901 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5905 if (truelab != NULL)
5908 tlab = mri_control_label ();
5910 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5911 rightstop, tlab, (const char *) NULL, extent);
5913 input_line_pointer += 2;
5914 if (*input_line_pointer != '.'
5915 || input_line_pointer[1] == '\0')
5919 qual = input_line_pointer[1];
5920 input_line_pointer += 2;
5923 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5924 &rightstart, &rightstop))
5930 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5931 rightstop, truelab, falselab, extent);
5933 if (truelab == NULL)
5938 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5939 rightstop, truelab, falselab, extent);
5943 if (input_line_pointer != stop)
5944 as_bad (_("syntax error in structured control directive"));
5947 /* Handle the MRI IF pseudo-op. This may be a structured control
5948 directive, or it may be a regular assembler conditional, depending
5957 struct mri_control_info *n;
5959 /* A structured control directive must end with THEN with an
5960 optional qualifier. */
5961 s = input_line_pointer;
5962 while (! is_end_of_line[(unsigned char) *s]
5963 && (! flag_mri || *s != '*'))
5966 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5969 if (s - input_line_pointer > 1
5973 if (s - input_line_pointer < 3
5974 || strncasecmp (s - 3, "THEN", 4) != 0)
5978 as_bad (_("missing then"));
5979 ignore_rest_of_line ();
5983 /* It's a conditional. */
5988 /* Since this might be a conditional if, this pseudo-op will be
5989 called even if we are supported to be ignoring input. Double
5990 check now. Clobber *input_line_pointer so that ignore_input
5991 thinks that this is not a special pseudo-op. */
5992 c = *input_line_pointer;
5993 *input_line_pointer = 0;
5994 if (ignore_input ())
5996 *input_line_pointer = c;
5997 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5998 ++input_line_pointer;
5999 demand_empty_rest_of_line ();
6002 *input_line_pointer = c;
6004 n = push_mri_control (mri_if);
6006 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6007 n->next, s[1] == '.' ? s[2] : '\0');
6010 input_line_pointer = s + 3;
6012 input_line_pointer = s + 1;
6016 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6017 ++input_line_pointer;
6020 demand_empty_rest_of_line ();
6023 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6024 structured IF, associate the ELSE with the IF. Otherwise, assume
6025 it is a conditional else. */
6036 && (mri_control_stack == NULL
6037 || mri_control_stack->type != mri_if
6038 || mri_control_stack->else_seen))
6044 c = *input_line_pointer;
6045 *input_line_pointer = 0;
6046 if (ignore_input ())
6048 *input_line_pointer = c;
6049 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6050 ++input_line_pointer;
6051 demand_empty_rest_of_line ();
6054 *input_line_pointer = c;
6056 if (mri_control_stack == NULL
6057 || mri_control_stack->type != mri_if
6058 || mri_control_stack->else_seen)
6060 as_bad (_("else without matching if"));
6061 ignore_rest_of_line ();
6065 mri_control_stack->else_seen = 1;
6067 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6070 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6074 colon (mri_control_stack->next);
6078 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6079 ++input_line_pointer;
6082 demand_empty_rest_of_line ();
6085 /* Handle the MRI ENDI pseudo-op. */
6091 if (mri_control_stack == NULL
6092 || mri_control_stack->type != mri_if)
6094 as_bad (_("endi without matching if"));
6095 ignore_rest_of_line ();
6099 /* ignore_input will not return true for ENDI, so we don't need to
6100 worry about checking it again here. */
6102 if (! mri_control_stack->else_seen)
6103 colon (mri_control_stack->next);
6104 colon (mri_control_stack->bottom);
6110 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6111 ++input_line_pointer;
6114 demand_empty_rest_of_line ();
6117 /* Handle the MRI BREAK pseudo-op. */
6120 s_mri_break (extent)
6123 struct mri_control_info *n;
6127 n = mri_control_stack;
6129 && n->type != mri_for
6130 && n->type != mri_repeat
6131 && n->type != mri_while)
6135 as_bad (_("break outside of structured loop"));
6136 ignore_rest_of_line ();
6140 buf = (char *) xmalloc (20 + strlen (n->bottom));
6143 sprintf (buf, "bra%s %s", ex, n->bottom);
6149 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6150 ++input_line_pointer;
6153 demand_empty_rest_of_line ();
6156 /* Handle the MRI NEXT pseudo-op. */
6162 struct mri_control_info *n;
6166 n = mri_control_stack;
6168 && n->type != mri_for
6169 && n->type != mri_repeat
6170 && n->type != mri_while)
6174 as_bad (_("next outside of structured loop"));
6175 ignore_rest_of_line ();
6179 buf = (char *) xmalloc (20 + strlen (n->next));
6182 sprintf (buf, "bra%s %s", ex, n->next);
6188 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6189 ++input_line_pointer;
6192 demand_empty_rest_of_line ();
6195 /* Handle the MRI FOR pseudo-op. */
6201 const char *varstart, *varstop;
6202 const char *initstart, *initstop;
6203 const char *endstart, *endstop;
6204 const char *bystart, *bystop;
6208 struct mri_control_info *n;
6214 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6218 varstart = input_line_pointer;
6220 /* Look for the '='. */
6221 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6222 && *input_line_pointer != '=')
6223 ++input_line_pointer;
6224 if (*input_line_pointer != '=')
6226 as_bad (_("missing ="));
6227 ignore_rest_of_line ();
6231 varstop = input_line_pointer;
6232 if (varstop > varstart
6233 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6236 ++input_line_pointer;
6238 initstart = input_line_pointer;
6240 /* Look for TO or DOWNTO. */
6243 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6245 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6246 && ! is_part_of_name (input_line_pointer[2]))
6248 initstop = input_line_pointer;
6249 input_line_pointer += 2;
6252 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6253 && ! is_part_of_name (input_line_pointer[6]))
6255 initstop = input_line_pointer;
6257 input_line_pointer += 6;
6260 ++input_line_pointer;
6262 if (initstop == NULL)
6264 as_bad (_("missing to or downto"));
6265 ignore_rest_of_line ();
6268 if (initstop > initstart
6269 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6273 endstart = input_line_pointer;
6275 /* Look for BY or DO. */
6278 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6280 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6281 && ! is_part_of_name (input_line_pointer[2]))
6283 endstop = input_line_pointer;
6285 input_line_pointer += 2;
6288 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6289 && (input_line_pointer[2] == '.'
6290 || ! is_part_of_name (input_line_pointer[2])))
6292 endstop = input_line_pointer;
6293 input_line_pointer += 2;
6296 ++input_line_pointer;
6298 if (endstop == NULL)
6300 as_bad (_("missing do"));
6301 ignore_rest_of_line ();
6304 if (endstop > endstart
6305 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6311 bystop = bystart + 2;
6316 bystart = input_line_pointer;
6320 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6322 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6323 && (input_line_pointer[2] == '.'
6324 || ! is_part_of_name (input_line_pointer[2])))
6326 bystop = input_line_pointer;
6327 input_line_pointer += 2;
6330 ++input_line_pointer;
6334 as_bad (_("missing do"));
6335 ignore_rest_of_line ();
6338 if (bystop > bystart
6339 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6343 if (*input_line_pointer != '.')
6347 extent = input_line_pointer[1];
6348 input_line_pointer += 2;
6351 /* We have fully parsed the FOR operands. Now build the loop. */
6353 n = push_mri_control (mri_for);
6355 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6366 memcpy (s, initstart, initstop - initstart);
6367 s += initstop - initstart;
6369 memcpy (s, varstart, varstop - varstart);
6370 s += varstop - varstart;
6384 memcpy (s, endstart, endstop - endstart);
6385 s += endstop - endstart;
6387 memcpy (s, varstart, varstop - varstart);
6388 s += varstop - varstart;
6396 sprintf (buf, "blt%s %s", ex, n->bottom);
6398 sprintf (buf, "bgt%s %s", ex, n->bottom);
6401 /* Put together the add or sub instruction used by ENDF. */
6411 memcpy (s, bystart, bystop - bystart);
6412 s += bystop - bystart;
6414 memcpy (s, varstart, varstop - varstart);
6415 s += varstop - varstart;
6421 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6422 ++input_line_pointer;
6425 demand_empty_rest_of_line ();
6428 /* Handle the MRI ENDF pseudo-op. */
6434 if (mri_control_stack == NULL
6435 || mri_control_stack->type != mri_for)
6437 as_bad (_("endf without for"));
6438 ignore_rest_of_line ();
6442 colon (mri_control_stack->next);
6444 mri_assemble (mri_control_stack->incr);
6446 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6447 mri_assemble (mri_control_stack->incr);
6449 free (mri_control_stack->incr);
6451 colon (mri_control_stack->bottom);
6457 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6458 ++input_line_pointer;
6461 demand_empty_rest_of_line ();
6464 /* Handle the MRI REPEAT pseudo-op. */
6467 s_mri_repeat (ignore)
6470 struct mri_control_info *n;
6472 n = push_mri_control (mri_repeat);
6476 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6477 ++input_line_pointer;
6479 demand_empty_rest_of_line ();
6482 /* Handle the MRI UNTIL pseudo-op. */
6490 if (mri_control_stack == NULL
6491 || mri_control_stack->type != mri_repeat)
6493 as_bad (_("until without repeat"));
6494 ignore_rest_of_line ();
6498 colon (mri_control_stack->next);
6500 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6503 parse_mri_control_expression (s, qual, (const char *) NULL,
6504 mri_control_stack->top, '\0');
6506 colon (mri_control_stack->bottom);
6508 input_line_pointer = s;
6514 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6515 ++input_line_pointer;
6518 demand_empty_rest_of_line ();
6521 /* Handle the MRI WHILE pseudo-op. */
6529 struct mri_control_info *n;
6531 s = input_line_pointer;
6532 while (! is_end_of_line[(unsigned char) *s]
6533 && (! flag_mri || *s != '*'))
6536 while (*s == ' ' || *s == '\t')
6538 if (s - input_line_pointer > 1
6541 if (s - input_line_pointer < 2
6542 || strncasecmp (s - 1, "DO", 2) != 0)
6544 as_bad (_("missing do"));
6545 ignore_rest_of_line ();
6549 n = push_mri_control (mri_while);
6553 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6554 s[1] == '.' ? s[2] : '\0');
6556 input_line_pointer = s + 1;
6557 if (*input_line_pointer == '.')
6558 input_line_pointer += 2;
6562 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6563 ++input_line_pointer;
6566 demand_empty_rest_of_line ();
6569 /* Handle the MRI ENDW pseudo-op. */
6577 if (mri_control_stack == NULL
6578 || mri_control_stack->type != mri_while)
6580 as_bad (_("endw without while"));
6581 ignore_rest_of_line ();
6585 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6586 sprintf (buf, "bra %s", mri_control_stack->next);
6590 colon (mri_control_stack->bottom);
6596 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6597 ++input_line_pointer;
6600 demand_empty_rest_of_line ();
6605 * Invocation line includes a switch not recognized by the base assembler.
6606 * See if it's a processor-specific option. These are:
6608 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6609 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6610 * Select the architecture. Instructions or features not
6611 * supported by the selected architecture cause fatal
6612 * errors. More than one may be specified. The default is
6613 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6614 * for -m68000, and -m68882 is a synonym for -m68881.
6615 * -[A]m[c]no-68851, -[A]m[c]no-68881
6616 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6617 * so don't use or document it, but that's the way the parsing
6620 * -pic Indicates PIC.
6621 * -k Indicates PIC. (Sun 3 only.)
6624 * Permit `|' to be used in expressions.
6629 CONST char *md_shortopts = "lSA:m:kQ:V";
6631 CONST char *md_shortopts = "lSA:m:k";
6634 struct option md_longopts[] = {
6635 #define OPTION_PIC (OPTION_MD_BASE)
6636 {"pic", no_argument, NULL, OPTION_PIC},
6637 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6638 {"register-prefix-optional", no_argument, NULL,
6639 OPTION_REGISTER_PREFIX_OPTIONAL},
6640 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6641 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6642 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6643 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6644 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6645 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6646 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6647 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6648 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6649 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6650 {NULL, no_argument, NULL, 0}
6652 size_t md_longopts_size = sizeof(md_longopts);
6655 md_parse_option (c, arg)
6661 case 'l': /* -l means keep external to 2 bit offset
6662 rather than 16 bit one */
6663 flag_short_refs = 1;
6666 case 'S': /* -S means that jbsr's always turn into
6668 flag_long_jumps = 1;
6674 /* intentional fall-through */
6677 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6681 const char *oarg = arg;
6687 if (arg[0] == 'c' && arg[1] == '6')
6690 for (i = 0; i < n_archs; i++)
6691 if (!strcmp (arg, archs[i].name))
6696 as_bad (_("unrecognized option `%s'"), oarg);
6699 arch = archs[i].arch;
6702 else if (arch == m68851)
6711 if (arg[0] == 'c' && arg[1] == '6')
6714 for (i = 0; i < n_archs; i++)
6715 if (!strcmp (arg, archs[i].name))
6717 unsigned long arch = archs[i].arch;
6718 if (cpu_of_arch (arch))
6719 /* It's a cpu spec. */
6721 current_architecture &= ~m68000up;
6722 current_architecture |= arch;
6724 else if (arch == m68881)
6726 current_architecture |= m68881;
6729 else if (arch == m68851)
6731 current_architecture |= m68851;
6741 as_bad (_("unrecognized architecture specification `%s'"), arg);
6750 break; /* -pic, Position Independent Code */
6752 case OPTION_REGISTER_PREFIX_OPTIONAL:
6753 flag_reg_prefix_optional = 1;
6754 reg_prefix_optional_seen = 1;
6757 /* -V: SVR4 argument to print version ID. */
6759 print_version_id ();
6762 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6763 should be emitted or not. FIXME: Not implemented. */
6767 case OPTION_BITWISE_OR:
6772 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6774 for (s = m68k_comment_chars; *s != '\0'; s++)
6778 m68k_comment_chars = n;
6782 case OPTION_BASE_SIZE_DEFAULT_16:
6783 m68k_index_width_default = SIZE_WORD;
6786 case OPTION_BASE_SIZE_DEFAULT_32:
6787 m68k_index_width_default = SIZE_LONG;
6790 case OPTION_DISP_SIZE_DEFAULT_16:
6792 m68k_rel32_from_cmdline = 1;
6795 case OPTION_DISP_SIZE_DEFAULT_32:
6797 m68k_rel32_from_cmdline = 1;
6808 md_show_usage (stream)
6811 fprintf(stream, _("\
6813 -l use 1 word for refs to undefined symbols [default 2]\n\
6814 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6815 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6816 | -mcpu32 | -m5200\n\
6817 specify variant of 680X0 architecture [default 68020]\n\
6818 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6819 target has/lacks floating-point coprocessor\n\
6820 [default yes for 68020, 68030, and cpu32]\n"));
6821 fprintf(stream, _("\
6822 -m68851 | -mno-68851\n\
6823 target has/lacks memory-management unit coprocessor\n\
6824 [default yes for 68020 and up]\n\
6825 -pic, -k generate position independent code\n\
6826 -S turn jbsr into jsr\n\
6827 --register-prefix-optional\n\
6828 recognize register names without prefix character\n\
6829 --bitwise-or do not treat `|' as a comment character\n"));
6830 fprintf (stream, _("\
6831 --base-size-default-16 base reg without size is 16 bits\n\
6832 --base-size-default-32 base reg without size is 32 bits (default)\n\
6833 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6834 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6839 /* TEST2: Test md_assemble() */
6840 /* Warning, this routine probably doesn't work anymore */
6844 struct m68k_it the_ins;
6852 if (!gets (buf) || !*buf)
6854 if (buf[0] == '|' || buf[1] == '.')
6856 for (cp = buf; *cp; cp++)
6861 memset (&the_ins, '\0', sizeof (the_ins));
6862 m68k_ip (&the_ins, buf);
6865 printf (_("Error %s in %s\n"), the_ins.error, buf);
6869 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
6870 for (n = 0; n < the_ins.numo; n++)
6871 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6873 print_the_insn (&the_ins.opcode[0], stdout);
6874 (void) putchar ('\n');
6876 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6878 if (the_ins.operands[n].error)
6880 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6883 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6884 if (the_ins.operands[n].b_const)
6885 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6886 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6887 if (the_ins.operands[n].b_iadd)
6888 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6889 (void) putchar ('\n');
6901 while (*str && *str != ' ')
6903 if (str[-1] == ':' || str[1] == '=')
6910 /* Possible states for relaxation:
6912 0 0 branch offset byte (bra, etc)
6916 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6920 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6927 /* We have no need to default values of symbols. */
6931 md_undefined_symbol (name)
6937 /* Round up a section size to the appropriate boundary. */
6939 md_section_align (segment, size)
6944 #ifdef BFD_ASSEMBLER
6945 /* For a.out, force the section size to be aligned. If we don't do
6946 this, BFD will align it for us, but it will not write out the
6947 final bytes of the section. This may be a bug in BFD, but it is
6948 easier to fix it here since that is how the other a.out targets
6952 align = bfd_get_section_alignment (stdoutput, segment);
6953 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6960 /* Exactly what point is a PC-relative offset relative TO?
6961 On the 68k, it is relative to the address of the first extension
6962 word. The difference between the addresses of the offset and the
6963 first extension word is stored in fx_pcrel_adjust. */
6965 md_pcrel_from (fixP)
6970 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6972 adjust = fixP->fx_pcrel_adjust;
6975 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6978 #ifndef BFD_ASSEMBLER
6983 tc_coff_symbol_emit_hook (ignore)
6989 tc_coff_sizemachdep (frag)
6992 switch (frag->fr_subtype & 0x3)
7009 /* end of tc-m68k.c */