1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
37 const char *m68k_comment_chars = "|";
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#";
49 const char line_separator_chars[] = "";
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
63 const int md_reloc_size = 8; /* Size of relocation record */
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
77 int flag_reg_prefix_optional;
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
97 static int m68k_rel32 = 1;
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
102 /* The default width to use for an index register when using a base
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
106 /* Its an arbitrary name: This means I don't approve of it */
107 /* See flames below */
108 static struct obstack robyn;
110 #define TAB(x,y) (((x)<<2)+(y))
111 #define TABTYPE(xy) ((xy) >> 2)
117 /* Case `g' except when BCC68000 is applicable. */
119 /* Coprocessor branches. */
121 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
122 supported on all cpus. Widens to 32-bit absolute. */
124 /* For inserting an extra jmp instruction with long offset on 68000,
125 for expanding conditional branches. (Not bsr or bra.) Since the
126 68000 doesn't support 32-bit displacements for conditional
127 branches, we fake it by reversing the condition and branching
128 around a jmp with an absolute long operand. */
130 /* For the DBcc "instructions". If the displacement requires 32 bits,
131 the branch-around-a-jump game is played here too. */
133 /* Not currently used? */
135 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
141 const char *m_operands;
142 unsigned long m_opcode;
146 struct m68k_incant *m_next;
149 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
150 #define gettwo(x) (((x)->m_opcode)&0xffff)
152 static const enum m68k_register m68000_control_regs[] = { 0 };
153 static const enum m68k_register m68010_control_regs[] = {
157 static const enum m68k_register m68020_control_regs[] = {
158 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
161 static const enum m68k_register m68040_control_regs[] = {
162 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
163 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
166 static const enum m68k_register m68060_control_regs[] = {
167 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
168 USP, VBR, URP, SRP, PCR,
171 static const enum m68k_register mcf5200_control_regs[] = {
172 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
173 RAMBAR0, RAMBAR1, MBAR,
176 #define cpu32_control_regs m68010_control_regs
178 static const enum m68k_register *control_regs;
180 /* internal form of a 68020 instruction */
184 const char *args; /* list of opcode info */
187 int numo; /* Number of shorts in opcode */
190 struct m68k_op operands[6];
192 int nexp; /* number of exprs in use */
193 struct m68k_exp exprs[4];
195 int nfrag; /* Number of frags we have to produce */
198 int fragoff; /* Where in the current opcode the frag ends */
205 int nrel; /* Num of reloc strucs in use */
212 /* In a pc relative address the difference between the address
213 of the offset and the address that the offset is relative
214 to. This depends on the addressing mode. Basically this
215 is the value to put in the offset field to address the
216 first byte of the offset, without regarding the special
217 significance of some values (in the branch instruction, for
221 /* Whether this expression needs special pic relocation, and if
223 enum pic_relocation pic_reloc;
226 reloc[5]; /* Five is enough??? */
229 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
230 #define float_of_arch(x) ((x) & mfloat)
231 #define mmu_of_arch(x) ((x) & mmmu)
233 static struct m68k_it the_ins; /* the instruction being assembled */
235 #define op(ex) ((ex)->exp.X_op)
236 #define adds(ex) ((ex)->exp.X_add_symbol)
237 #define subs(ex) ((ex)->exp.X_op_symbol)
238 #define offs(ex) ((ex)->exp.X_add_number)
240 /* Macros for adding things to the m68k_it struct */
242 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
244 /* Like addword, but goes BEFORE general operands */
248 struct m68k_incant *opcode;
251 for(z=the_ins.numo;z>opcode->m_codenum;--z)
252 the_ins.opcode[z]=the_ins.opcode[z-1];
253 for(z=0;z<the_ins.nrel;z++)
254 the_ins.reloc[z].n+=2;
255 for (z = 0; z < the_ins.nfrag; z++)
256 the_ins.fragb[z].fragoff++;
257 the_ins.opcode[opcode->m_codenum]=w;
261 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
264 add_fix (width, exp, pc_rel, pc_fix)
266 struct m68k_exp *exp;
270 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
274 : (the_ins.numo*2)));
275 the_ins.reloc[the_ins.nrel].exp = exp->exp;
276 the_ins.reloc[the_ins.nrel].wid = width;
277 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
279 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
281 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
284 /* Cause an extra frag to be generated here, inserting up to 10 bytes
285 (that value is chosen in the frag_var call in md_assemble). TYPE
286 is the subtype of the frag to be generated; its primary type is
287 rs_machine_dependent.
289 The TYPE parameter is also used by md_convert_frag_1 and
290 md_estimate_size_before_relax. The appropriate type of fixup will
291 be emitted by md_convert_frag_1.
293 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
295 add_frag(add,off,type)
300 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
301 the_ins.fragb[the_ins.nfrag].fadd=add;
302 the_ins.fragb[the_ins.nfrag].foff=off;
303 the_ins.fragb[the_ins.nfrag++].fragty=type;
307 (op (ex) != O_constant && op (ex) != O_big)
309 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
310 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
311 static int reverse_16_bits PARAMS ((int in));
312 static int reverse_8_bits PARAMS ((int in));
313 static void install_gen_operand PARAMS ((int mode, int val));
314 static void install_operand PARAMS ((int mode, int val));
315 static void s_bss PARAMS ((int));
316 static void s_data1 PARAMS ((int));
317 static void s_data2 PARAMS ((int));
318 static void s_even PARAMS ((int));
319 static void s_proc PARAMS ((int));
320 static void mri_chip PARAMS ((void));
321 static void s_chip PARAMS ((int));
322 static void s_fopt PARAMS ((int));
323 static void s_opt PARAMS ((int));
324 static void s_reg PARAMS ((int));
325 static void s_restore PARAMS ((int));
326 static void s_save PARAMS ((int));
327 static void s_mri_if PARAMS ((int));
328 static void s_mri_else PARAMS ((int));
329 static void s_mri_endi PARAMS ((int));
330 static void s_mri_break PARAMS ((int));
331 static void s_mri_next PARAMS ((int));
332 static void s_mri_for PARAMS ((int));
333 static void s_mri_endf PARAMS ((int));
334 static void s_mri_repeat PARAMS ((int));
335 static void s_mri_until PARAMS ((int));
336 static void s_mri_while PARAMS ((int));
337 static void s_mri_endw PARAMS ((int));
339 static int current_architecture;
347 static const struct m68k_cpu archs[] = {
348 { m68000, "68000", 0 },
349 { m68010, "68010", 0 },
350 { m68020, "68020", 0 },
351 { m68030, "68030", 0 },
352 { m68040, "68040", 0 },
353 { m68060, "68060", 0 },
354 { cpu32, "cpu32", 0 },
355 { m68881, "68881", 0 },
356 { m68851, "68851", 0 },
357 { mcf5200, "5200", 0 },
358 /* Aliases (effectively, so far as gas is concerned) for the above
360 { m68020, "68k", 1 },
361 { m68000, "68302", 1 },
362 { m68000, "68008", 1 },
363 { m68000, "68ec000", 1 },
364 { m68000, "68hc000", 1 },
365 { m68000, "68hc001", 1 },
366 { m68020, "68ec020", 1 },
367 { m68030, "68ec030", 1 },
368 { m68040, "68ec040", 1 },
369 { m68060, "68ec060", 1 },
370 { cpu32, "68330", 1 },
371 { cpu32, "68331", 1 },
372 { cpu32, "68332", 1 },
373 { cpu32, "68333", 1 },
374 { cpu32, "68340", 1 },
375 { cpu32, "68360", 1 },
376 { m68881, "68882", 1 },
379 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
381 /* BCC68000 is for patching in an extra jmp instruction for long offsets
382 on the 68000. The 68000 doesn't support long branches with branchs */
384 /* This table desribes how you change sizes for the various types of variable
385 size expressions. This version only supports two kinds. */
387 /* Note that calls to frag_var need to specify the maximum expansion
388 needed; this is currently 10 bytes for DBCC. */
391 How far Forward this mode will reach:
392 How far Backward this mode will reach:
393 How many bytes this mode will add to the size of the frag
394 Which mode to go to if the offset won't fit in this one
396 relax_typeS md_relax_table[] =
398 {1, 1, 0, 0}, /* First entries aren't used */
399 {1, 1, 0, 0}, /* For no good reason except */
400 {1, 1, 0, 0}, /* that the VAX doesn't either */
403 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
404 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
408 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
409 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
413 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
414 {(32767), (-32768), 2, TAB (PCREL, LONG)},
418 {(127), (-128), 0, TAB (BCC68000, SHORT)},
419 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
420 {0, 0, 6, 0}, /* jmp long space */
423 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
424 {(32767), (-32768), 2, TAB (DBCC, LONG)},
425 {0, 0, 10, 0}, /* bra/jmp long space */
428 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
429 {32767, -32768, 2, TAB (PCLEA, LONG)},
433 /* For, e.g., jmp pcrel indexed. */
434 {125, -130, 0, TAB (PCINDEX, SHORT)},
435 {32765, -32770, 2, TAB (PCINDEX, LONG)},
440 /* These are the machine dependent pseudo-ops. These are included so
441 the assembler can work on the output from the SUN C compiler, which
445 /* This table describes all the machine specific pseudo-ops the assembler
446 has to support. The fields are:
447 pseudo-op name without dot
448 function to call to execute this pseudo-op
449 Integer arg to pass to the function
451 const pseudo_typeS md_pseudo_table[] =
453 {"data1", s_data1, 0},
454 {"data2", s_data2, 0},
457 {"skip", s_space, 0},
459 #if defined (TE_SUN3) || defined (OBJ_ELF)
460 {"align", s_align_bytes, 0},
463 {"swbeg", s_ignore, 0},
465 {"extend", float_cons, 'x'},
466 {"ldouble", float_cons, 'x'},
468 /* The following pseudo-ops are supported for MRI compatibility. */
470 {"comline", s_space, 1},
472 {"mask2", s_ignore, 0},
475 {"restore", s_restore, 0},
479 {"if.b", s_mri_if, 'b'},
480 {"if.w", s_mri_if, 'w'},
481 {"if.l", s_mri_if, 'l'},
482 {"else", s_mri_else, 0},
483 {"else.s", s_mri_else, 's'},
484 {"else.l", s_mri_else, 'l'},
485 {"endi", s_mri_endi, 0},
486 {"break", s_mri_break, 0},
487 {"break.s", s_mri_break, 's'},
488 {"break.l", s_mri_break, 'l'},
489 {"next", s_mri_next, 0},
490 {"next.s", s_mri_next, 's'},
491 {"next.l", s_mri_next, 'l'},
492 {"for", s_mri_for, 0},
493 {"for.b", s_mri_for, 'b'},
494 {"for.w", s_mri_for, 'w'},
495 {"for.l", s_mri_for, 'l'},
496 {"endf", s_mri_endf, 0},
497 {"repeat", s_mri_repeat, 0},
498 {"until", s_mri_until, 0},
499 {"until.b", s_mri_until, 'b'},
500 {"until.w", s_mri_until, 'w'},
501 {"until.l", s_mri_until, 'l'},
502 {"while", s_mri_while, 0},
503 {"while.b", s_mri_while, 'b'},
504 {"while.w", s_mri_while, 'w'},
505 {"while.l", s_mri_while, 'l'},
506 {"endw", s_mri_endw, 0},
512 /* The mote pseudo ops are put into the opcode table, since they
513 don't start with a . they look like opcodes to gas.
515 extern void obj_coff_section ();
517 CONST pseudo_typeS mote_pseudo_table[] =
530 {"xdef", s_globl, 0},
532 {"align", s_align_bytes, 0},
534 {"align", s_align_ptwo, 0},
537 {"sect", obj_coff_section, 0},
538 {"section", obj_coff_section, 0},
543 #define issbyte(x) ((x)>=-128 && (x)<=127)
544 #define isubyte(x) ((x)>=0 && (x)<=255)
545 #define issword(x) ((x)>=-32768 && (x)<=32767)
546 #define isuword(x) ((x)>=0 && (x)<=65535)
548 #define isbyte(x) ((x)>= -255 && (x)<=255)
549 #define isword(x) ((x)>=-65536 && (x)<=65535)
550 #define islong(x) (1)
552 extern char *input_line_pointer;
554 static char mklower_table[256];
555 #define mklower(c) (mklower_table[(unsigned char)(c)])
556 static char notend_table[256];
557 static char alt_notend_table[256];
559 (! (notend_table[(unsigned char) *s] \
561 && alt_notend_table[(unsigned char) s[1]])))
563 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
565 #ifdef NO_PCREL_RELOCS
568 make_pcrel_absolute(fixP, add_number)
572 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
574 /* rewrite the PC relative instructions to absolute address ones.
575 * these are rumoured to be faster, and the apollo linker refuses
576 * to deal with the PC relative relocations.
578 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
583 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
589 as_fatal ("Unknown PC relative instruction");
594 #endif /* NO_PCREL_RELOCS */
597 tc_coff_fix2rtype (fixP)
600 if (fixP->fx_tcbit && fixP->fx_size == 4)
601 return R_RELLONG_NEG;
602 #ifdef NO_PCREL_RELOCS
603 know (fixP->fx_pcrel == 0);
604 return (fixP->fx_size == 1 ? R_RELBYTE
605 : fixP->fx_size == 2 ? R_DIR16
608 return (fixP->fx_pcrel ?
609 (fixP->fx_size == 1 ? R_PCRBYTE :
610 fixP->fx_size == 2 ? R_PCRWORD :
612 (fixP->fx_size == 1 ? R_RELBYTE :
613 fixP->fx_size == 2 ? R_RELWORD :
622 /* Compute the relocation code for a fixup of SIZE bytes, using pc
623 relative relocation if PCREL is non-zero. PIC says whether a special
624 pic relocation was requested. */
626 static bfd_reloc_code_real_type get_reloc_code
627 PARAMS ((int, int, enum pic_relocation));
629 static bfd_reloc_code_real_type
630 get_reloc_code (size, pcrel, pic)
633 enum pic_relocation pic;
641 return BFD_RELOC_8_GOT_PCREL;
643 return BFD_RELOC_16_GOT_PCREL;
645 return BFD_RELOC_32_GOT_PCREL;
653 return BFD_RELOC_8_GOTOFF;
655 return BFD_RELOC_16_GOTOFF;
657 return BFD_RELOC_32_GOTOFF;
665 return BFD_RELOC_8_PLT_PCREL;
667 return BFD_RELOC_16_PLT_PCREL;
669 return BFD_RELOC_32_PLT_PCREL;
677 return BFD_RELOC_8_PLTOFF;
679 return BFD_RELOC_16_PLTOFF;
681 return BFD_RELOC_32_PLTOFF;
691 return BFD_RELOC_8_PCREL;
693 return BFD_RELOC_16_PCREL;
695 return BFD_RELOC_32_PCREL;
712 as_bad ("Can not do %d byte %s%srelocation", size,
713 pcrel ? "pc-relative " : "",
714 pic == pic_none ? "" : "pic ");
715 return BFD_RELOC_NONE;
718 /* Here we decide which fixups can be adjusted to make them relative
719 to the beginning of the section instead of the symbol. Basically
720 we need to make sure that the dynamic relocations are done
721 correctly, so in some cases we force the original symbol to be
724 tc_m68k_fix_adjustable (fixP)
727 /* Prevent all adjustments to global symbols. */
728 if (S_IS_EXTERNAL (fixP->fx_addsy))
731 /* adjust_reloc_syms doesn't know about the GOT */
732 switch (fixP->fx_r_type)
734 case BFD_RELOC_8_GOT_PCREL:
735 case BFD_RELOC_16_GOT_PCREL:
736 case BFD_RELOC_32_GOT_PCREL:
737 case BFD_RELOC_8_GOTOFF:
738 case BFD_RELOC_16_GOTOFF:
739 case BFD_RELOC_32_GOTOFF:
740 case BFD_RELOC_8_PLT_PCREL:
741 case BFD_RELOC_16_PLT_PCREL:
742 case BFD_RELOC_32_PLT_PCREL:
743 case BFD_RELOC_8_PLTOFF:
744 case BFD_RELOC_16_PLTOFF:
745 case BFD_RELOC_32_PLTOFF:
755 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
762 tc_gen_reloc (section, fixp)
767 bfd_reloc_code_real_type code;
772 if (fixp->fx_r_type != BFD_RELOC_NONE)
774 code = fixp->fx_r_type;
776 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
777 that fixup_segment converted a non-PC relative reloc into a
778 PC relative reloc. In such a case, we need to convert the
785 code = BFD_RELOC_8_PCREL;
788 code = BFD_RELOC_16_PCREL;
791 code = BFD_RELOC_32_PCREL;
793 case BFD_RELOC_8_PCREL:
794 case BFD_RELOC_16_PCREL:
795 case BFD_RELOC_32_PCREL:
796 case BFD_RELOC_8_GOT_PCREL:
797 case BFD_RELOC_16_GOT_PCREL:
798 case BFD_RELOC_32_GOT_PCREL:
799 case BFD_RELOC_8_GOTOFF:
800 case BFD_RELOC_16_GOTOFF:
801 case BFD_RELOC_32_GOTOFF:
802 case BFD_RELOC_8_PLT_PCREL:
803 case BFD_RELOC_16_PLT_PCREL:
804 case BFD_RELOC_32_PLT_PCREL:
805 case BFD_RELOC_8_PLTOFF:
806 case BFD_RELOC_16_PLTOFF:
807 case BFD_RELOC_32_PLTOFF:
810 as_bad_where (fixp->fx_file, fixp->fx_line,
811 "Cannot make %s relocation PC relative",
812 bfd_get_reloc_code_name (code));
818 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
819 switch (F (fixp->fx_size, fixp->fx_pcrel))
821 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
822 MAP (1, 0, BFD_RELOC_8);
823 MAP (2, 0, BFD_RELOC_16);
824 MAP (4, 0, BFD_RELOC_32);
825 MAP (1, 1, BFD_RELOC_8_PCREL);
826 MAP (2, 1, BFD_RELOC_16_PCREL);
827 MAP (4, 1, BFD_RELOC_32_PCREL);
835 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
837 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
838 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
841 reloc->addend = fixp->fx_addnumber;
846 reloc->addend = fixp->fx_addnumber;
848 reloc->addend = (section->vma
849 + (fixp->fx_pcrel_adjust == 64
850 ? -1 : fixp->fx_pcrel_adjust)
852 + md_pcrel_from (fixp));
855 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
856 assert (reloc->howto != 0);
861 #endif /* BFD_ASSEMBLER */
863 /* Handle of the OPCODE hash table. NULL means any use before
864 m68k_ip_begin() will crash. */
865 static struct hash_control *op_hash;
867 /* Assemble an m68k instruction. */
874 register struct m68k_op *opP;
875 register struct m68k_incant *opcode;
876 register const char *s;
877 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
878 char *pdot, *pdotmove;
879 enum m68k_size siz1, siz2;
883 char *crack_operand ();
884 LITTLENUM_TYPE words[6];
885 LITTLENUM_TYPE *wordp;
886 unsigned long ok_arch = 0;
888 if (*instring == ' ')
889 instring++; /* skip leading whitespace */
891 /* Scan up to end of operation-code, which MUST end in end-of-string
892 or exactly 1 space. */
894 for (p = instring; *p != '\0'; p++)
904 the_ins.error = "No operator";
908 /* p now points to the end of the opcode name, probably whitespace.
909 Make sure the name is null terminated by clobbering the
910 whitespace, look it up in the hash table, then fix it back.
911 Remove a dot, first, since the opcode tables have none. */
914 for (pdotmove = pdot; pdotmove < p; pdotmove++)
915 *pdotmove = pdotmove[1];
921 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
926 for (pdotmove = p; pdotmove > pdot; pdotmove--)
927 *pdotmove = pdotmove[-1];
934 the_ins.error = "Unknown operator";
938 /* found a legitimate opcode, start matching operands */
942 if (opcode->m_operands == 0)
944 char *old = input_line_pointer;
946 input_line_pointer = p;
947 /* Ahh - it's a motorola style psuedo op */
948 mote_pseudo_table[opcode->m_opnum].poc_handler
949 (mote_pseudo_table[opcode->m_opnum].poc_val);
950 input_line_pointer = old;
956 if (flag_mri && opcode->m_opnum == 0)
958 /* In MRI mode, random garbage is allowed after an instruction
959 which accepts no operands. */
960 the_ins.args = opcode->m_operands;
961 the_ins.numargs = opcode->m_opnum;
962 the_ins.numo = opcode->m_codenum;
963 the_ins.opcode[0] = getone (opcode);
964 the_ins.opcode[1] = gettwo (opcode);
968 for (opP = &the_ins.operands[0]; *p; opP++)
970 p = crack_operand (p, opP);
974 the_ins.error = opP->error;
979 opsfound = opP - &the_ins.operands[0];
981 /* This ugly hack is to support the floating pt opcodes in their
982 standard form. Essentially, we fake a first enty of type COP#1 */
983 if (opcode->m_operands[0] == 'I')
987 for (n = opsfound; n > 0; --n)
988 the_ins.operands[n] = the_ins.operands[n - 1];
990 memset ((char *) (&the_ins.operands[0]), '\0',
991 sizeof (the_ins.operands[0]));
992 the_ins.operands[0].mode = CONTROL;
993 the_ins.operands[0].reg = m68k_float_copnum;
997 /* We've got the operands. Find an opcode that'll accept them */
1000 /* If we didn't get the right number of ops, or we have no
1001 common model with this pattern then reject this pattern. */
1003 ok_arch |= opcode->m_arch;
1004 if (opsfound != opcode->m_opnum
1005 || ((opcode->m_arch & current_architecture) == 0))
1009 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1013 /* Warning: this switch is huge! */
1014 /* I've tried to organize the cases into this order:
1015 non-alpha first, then alpha by letter. Lower-case
1016 goes directly before uppercase counterpart. */
1017 /* Code with multiple case ...: gets sorted by the lowest
1018 case ... it belongs to. I hope this makes sense. */
1148 if (opP->mode != IMMED)
1150 else if (s[1] == 'b'
1151 && ! isvar (&opP->disp)
1152 && (opP->disp.exp.X_op != O_constant
1153 || ! isbyte (opP->disp.exp.X_add_number)))
1155 else if (s[1] == 'B'
1156 && ! isvar (&opP->disp)
1157 && (opP->disp.exp.X_op != O_constant
1158 || ! issbyte (opP->disp.exp.X_add_number)))
1160 else if (s[1] == 'w'
1161 && ! isvar (&opP->disp)
1162 && (opP->disp.exp.X_op != O_constant
1163 || ! isword (opP->disp.exp.X_add_number)))
1165 else if (s[1] == 'W'
1166 && ! isvar (&opP->disp)
1167 && (opP->disp.exp.X_op != O_constant
1168 || ! issword (opP->disp.exp.X_add_number)))
1174 if (opP->mode != IMMED)
1179 if (opP->mode == AREG
1180 || opP->mode == CONTROL
1181 || opP->mode == FPREG
1182 || opP->mode == IMMED
1183 || opP->mode == REGLST
1184 || (opP->mode != ABSL
1186 || opP->reg == ZPC)))
1191 if (opP->mode == CONTROL
1192 || opP->mode == FPREG
1193 || opP->mode == REGLST
1194 || opP->mode == IMMED
1195 || (opP->mode != ABSL
1197 || opP->reg == ZPC)))
1225 if (opP->mode == CONTROL
1226 || opP->mode == FPREG
1227 || opP->mode == REGLST)
1232 if (opP->mode != AINC)
1237 if (opP->mode != ADEC)
1287 if (opP->reg == PC || opP->reg == ZPC)
1308 case '~': /* For now! (JF FOO is this right?) */
1330 if (opP->mode != CONTROL
1331 || (opP->reg != TT0 && opP->reg != TT1))
1336 if (opP->mode != AREG)
1341 if (opP->mode != AINDR)
1346 if (opP->mode != ABSL
1348 && strncmp (instring, "jbsr", 4) == 0))
1353 if (opP->mode != CONTROL || opP->reg != CCR)
1358 if (opP->mode != DISP
1360 || opP->reg > ADDR7)
1365 if (opP->mode != DREG)
1370 if (opP->mode != FPREG)
1375 if (opP->mode != CONTROL
1382 if (opP->mode != CONTROL
1384 || opP->reg > last_movec_reg)
1388 const enum m68k_register *rp;
1389 for (rp = control_regs; *rp; rp++)
1390 if (*rp == opP->reg)
1398 if (opP->mode != IMMED)
1404 if (opP->mode == DREG
1405 || opP->mode == AREG
1406 || opP->mode == FPREG)
1415 opP->mask = 1 << (opP->reg - DATA0);
1418 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1421 opP->mask = 1 << (opP->reg - FP0 + 16);
1429 else if (opP->mode == CONTROL)
1438 opP->mask = 1 << 24;
1441 opP->mask = 1 << 25;
1444 opP->mask = 1 << 26;
1453 else if (opP->mode == ABSL
1454 && opP->disp.size == SIZE_UNSPEC
1455 && opP->disp.exp.X_op == O_constant)
1457 /* This is what the MRI REG pseudo-op generates. */
1459 opP->mask = opP->disp.exp.X_add_number;
1461 else if (opP->mode != REGLST)
1463 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1465 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1470 if (opP->mode != IMMED)
1472 else if (opP->disp.exp.X_op != O_constant
1473 || ! issbyte (opP->disp.exp.X_add_number))
1475 else if (! m68k_quick
1476 && instring[3] != 'q'
1477 && instring[4] != 'q')
1482 if (opP->mode != DREG
1483 && opP->mode != IMMED
1484 && opP->mode != ABSL)
1489 if (opP->mode != IMMED)
1491 else if (opP->disp.exp.X_op != O_constant
1492 || opP->disp.exp.X_add_number < 1
1493 || opP->disp.exp.X_add_number > 8)
1495 else if (! m68k_quick
1496 && (strncmp (instring, "add", 3) == 0
1497 || strncmp (instring, "sub", 3) == 0)
1498 && instring[3] != 'q')
1503 if (opP->mode != DREG && opP->mode != AREG)
1508 if (opP->mode != AINDR
1509 && (opP->mode != BASE
1511 && opP->reg != ZADDR0)
1512 || opP->disp.exp.X_op != O_absent
1513 || ((opP->index.reg < DATA0
1514 || opP->index.reg > DATA7)
1515 && (opP->index.reg < ADDR0
1516 || opP->index.reg > ADDR7))
1517 || opP->index.size != SIZE_UNSPEC
1518 || opP->index.scale != 1))
1523 if (opP->mode != CONTROL
1524 || ! (opP->reg == FPI
1526 || opP->reg == FPC))
1531 if (opP->mode != CONTROL || opP->reg != SR)
1536 if (opP->mode != IMMED)
1538 else if (opP->disp.exp.X_op != O_constant
1539 || opP->disp.exp.X_add_number < 0
1540 || opP->disp.exp.X_add_number > 7)
1545 if (opP->mode != CONTROL || opP->reg != USP)
1549 /* JF these are out of order. We could put them
1550 in order if we were willing to put up with
1551 bunches of #ifdef m68851s in the code.
1553 Don't forget that you need these operands
1554 to use 68030 MMU instructions. */
1556 /* Memory addressing mode used by pflushr */
1558 if (opP->mode == CONTROL
1559 || opP->mode == FPREG
1560 || opP->mode == DREG
1561 || opP->mode == AREG
1562 || opP->mode == REGLST)
1564 /* We should accept immediate operands, but they
1565 supposedly have to be quad word, and we don't
1566 handle that. I would like to see what a Motorola
1567 assembler does before doing something here. */
1568 if (opP->mode == IMMED)
1573 if (opP->mode != CONTROL
1574 || (opP->reg != SFC && opP->reg != DFC))
1579 if (opP->mode != CONTROL || opP->reg != TC)
1584 if (opP->mode != CONTROL || opP->reg != AC)
1589 if (opP->mode != CONTROL
1592 && opP->reg != SCC))
1597 if (opP->mode != CONTROL
1603 if (opP->mode != CONTROL
1606 && opP->reg != CRP))
1611 if (opP->mode != CONTROL
1612 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1613 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1618 if (opP->mode != CONTROL || opP->reg != PSR)
1623 if (opP->mode != CONTROL || opP->reg != PCSR)
1628 if (opP->mode != CONTROL
1635 } /* not a cache specifier. */
1639 if (opP->mode != ABSL)
1645 } /* switch on type of operand */
1649 } /* for each operand */
1650 } /* if immediately wrong */
1657 opcode = opcode->m_next;
1662 && !(ok_arch & current_architecture))
1667 "invalid instruction for this architecture; needs ");
1668 cp = buf + strlen (buf);
1672 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1675 strcpy (cp, "mmu (68030 or 68851)");
1678 strcpy (cp, "68020 or higher");
1681 strcpy (cp, "68000 or higher");
1684 strcpy (cp, "68010 or higher");
1688 int got_one = 0, idx;
1689 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1692 if ((archs[idx].arch & ok_arch)
1693 && ! archs[idx].alias)
1697 strcpy (cp, " or ");
1701 strcpy (cp, archs[idx].name);
1707 cp = xmalloc (strlen (buf) + 1);
1712 the_ins.error = "operands mismatch";
1714 } /* Fell off the end */
1719 /* now assemble it */
1721 the_ins.args = opcode->m_operands;
1722 the_ins.numargs = opcode->m_opnum;
1723 the_ins.numo = opcode->m_codenum;
1724 the_ins.opcode[0] = getone (opcode);
1725 the_ins.opcode[1] = gettwo (opcode);
1727 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1729 /* This switch is a doozy.
1730 Watch the first step; its a big one! */
1757 tmpreg = 0x3c; /* 7.4 */
1758 if (strchr ("bwl", s[1]))
1759 nextword = get_num (&opP->disp, 80);
1761 nextword = get_num (&opP->disp, 0);
1762 if (isvar (&opP->disp))
1763 add_fix (s[1], &opP->disp, 0, 0);
1767 if (!isbyte (nextword))
1768 opP->error = "operand out of range";
1773 if (!isword (nextword))
1774 opP->error = "operand out of range";
1779 if (!issword (nextword))
1780 opP->error = "operand out of range";
1785 addword (nextword >> 16);
1812 /* We gotta put out some float */
1813 if (op (&opP->disp) != O_big)
1818 /* Can other cases happen here? */
1819 if (op (&opP->disp) != O_constant)
1822 val = (valueT) offs (&opP->disp);
1826 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1827 val >>= LITTLENUM_NUMBER_OF_BITS;
1831 offs (&opP->disp) = gencnt;
1833 if (offs (&opP->disp) > 0)
1835 if (offs (&opP->disp) > baseo)
1837 as_warn ("Bignum too big for %c format; truncated",
1839 offs (&opP->disp) = baseo;
1841 baseo -= offs (&opP->disp);
1844 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1845 offs (&opP->disp)--;
1850 gen_to_words (words, baseo, (long) outro);
1851 for (wordp = words; baseo--; wordp++)
1855 tmpreg = opP->reg - DATA; /* 0.dreg */
1858 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1861 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1864 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1867 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1871 nextword = get_num (&opP->disp, 80);
1874 && ! isvar (&opP->disp)
1877 opP->disp.exp.X_op = O_symbol;
1878 #ifndef BFD_ASSEMBLER
1879 opP->disp.exp.X_add_symbol = &abs_symbol;
1881 opP->disp.exp.X_add_symbol =
1882 section_symbol (absolute_section);
1886 /* Force into index mode. Hope this works */
1888 /* We do the first bit for 32-bit displacements, and the
1889 second bit for 16 bit ones. It is possible that we
1890 should make the default be WORD instead of LONG, but
1891 I think that'd break GCC, so we put up with a little
1892 inefficiency for the sake of working output. */
1894 if (!issword (nextword)
1895 || (isvar (&opP->disp)
1896 && ((opP->disp.size == SIZE_UNSPEC
1897 && flag_short_refs == 0
1898 && cpu_of_arch (current_architecture) >= m68020)
1899 || opP->disp.size == SIZE_LONG)))
1901 if (cpu_of_arch (current_architecture) < m68020)
1903 "displacement too large for this architecture; needs 68020 or higher";
1905 tmpreg = 0x3B; /* 7.3 */
1907 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1908 if (isvar (&opP->disp))
1912 if (opP->disp.size == SIZE_LONG
1914 /* If the displacement needs pic
1915 relocation it cannot be relaxed. */
1916 || opP->disp.pic_reloc != pic_none
1921 add_fix ('l', &opP->disp, 1, 2);
1925 add_frag (adds (&opP->disp),
1927 TAB (PCLEA, SZ_UNDEF));
1934 add_fix ('l', &opP->disp, 0, 0);
1939 addword (nextword >> 16);
1944 tmpreg = 0x3A; /* 7.2 */
1946 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1948 if (isvar (&opP->disp))
1952 add_fix ('w', &opP->disp, 1, 0);
1955 add_fix ('w', &opP->disp, 0, 0);
1965 baseo = get_num (&opP->disp, 80);
1966 if (opP->mode == POST || opP->mode == PRE)
1967 outro = get_num (&opP->odisp, 80);
1968 /* Figure out the `addressing mode'.
1969 Also turn on the BASE_DISABLE bit, if needed. */
1970 if (opP->reg == PC || opP->reg == ZPC)
1972 tmpreg = 0x3b; /* 7.3 */
1973 if (opP->reg == ZPC)
1976 else if (opP->reg == 0)
1979 tmpreg = 0x30; /* 6.garbage */
1981 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1984 tmpreg = 0x30 + opP->reg - ZADDR0;
1987 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1989 siz1 = opP->disp.size;
1990 if (opP->mode == POST || opP->mode == PRE)
1991 siz2 = opP->odisp.size;
1995 /* Index register stuff */
1996 if (opP->index.reg != 0
1997 && opP->index.reg >= DATA
1998 && opP->index.reg <= ADDR7)
2000 nextword |= (opP->index.reg - DATA) << 12;
2002 if (opP->index.size == SIZE_LONG
2003 || (opP->index.size == SIZE_UNSPEC
2004 && m68k_index_width_default == SIZE_LONG))
2007 if ((opP->index.scale != 1
2008 && cpu_of_arch (current_architecture) < m68020)
2009 || (opP->index.scale == 8
2010 && current_architecture == mcf5200))
2013 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2016 switch (opP->index.scale)
2033 GET US OUT OF HERE! */
2035 /* Must be INDEX, with an index register. Address
2036 register cannot be ZERO-PC, and either :b was
2037 forced, or we know it will fit. For a 68000 or
2038 68010, force this mode anyways, because the
2039 larger modes aren't supported. */
2040 if (opP->mode == BASE
2041 && ((opP->reg >= ADDR0
2042 && opP->reg <= ADDR7)
2045 if (siz1 == SIZE_BYTE
2046 || cpu_of_arch (current_architecture) < m68020
2047 || (siz1 == SIZE_UNSPEC
2048 && ! isvar (&opP->disp)
2049 && issbyte (baseo)))
2051 nextword += baseo & 0xff;
2053 if (isvar (&opP->disp))
2055 /* Do a byte relocation. If it doesn't
2056 fit (possible on m68000) let the
2057 fixup processing complain later. */
2059 add_fix ('B', &opP->disp, 1, 1);
2061 add_fix ('B', &opP->disp, 0, 0);
2063 else if (siz1 != SIZE_BYTE)
2065 if (siz1 != SIZE_UNSPEC)
2066 as_warn ("Forcing byte displacement");
2067 if (! issbyte (baseo))
2068 opP->error = "byte displacement out of range";
2073 else if (siz1 == SIZE_UNSPEC
2075 && isvar (&opP->disp)
2076 && subs (&opP->disp) == NULL
2078 /* If the displacement needs pic
2079 relocation it cannot be relaxed. */
2080 && opP->disp.pic_reloc == pic_none
2084 /* The code in md_convert_frag_1 needs to be
2085 able to adjust nextword. Call frag_grow
2086 to ensure that we have enough space in
2087 the frag obstack to make all the bytes
2090 nextword += baseo & 0xff;
2092 add_frag (adds (&opP->disp), offs (&opP->disp),
2093 TAB (PCINDEX, SZ_UNDEF));
2101 nextword |= 0x40; /* No index reg */
2102 if (opP->index.reg >= ZDATA0
2103 && opP->index.reg <= ZDATA7)
2104 nextword |= (opP->index.reg - ZDATA0) << 12;
2105 else if (opP->index.reg >= ZADDR0
2106 || opP->index.reg <= ZADDR7)
2107 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2110 /* It isn't simple. */
2112 if (cpu_of_arch (current_architecture) < m68020)
2114 "invalid operand mode for this architecture; needs 68020 or higher";
2117 /* If the guy specified a width, we assume that it is
2118 wide enough. Maybe it isn't. If so, we lose. */
2122 if (isvar (&opP->disp)
2124 : ! issword (baseo))
2129 else if (! isvar (&opP->disp) && baseo == 0)
2138 as_warn (":b not permitted; defaulting to :w");
2148 /* Figure out innner displacement stuff */
2149 if (opP->mode == POST || opP->mode == PRE)
2151 if (cpu_of_arch (current_architecture) & cpu32)
2152 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2156 if (isvar (&opP->odisp)
2158 : ! issword (outro))
2163 else if (! isvar (&opP->odisp) && outro == 0)
2172 as_warn (":b not permitted; defaulting to :w");
2181 if (opP->mode == POST
2182 && (nextword & 0x40) == 0)
2187 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2189 if (opP->reg == PC || opP->reg == ZPC)
2190 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2192 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2194 if (siz1 == SIZE_LONG)
2195 addword (baseo >> 16);
2196 if (siz1 != SIZE_UNSPEC)
2199 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2200 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2201 if (siz2 == SIZE_LONG)
2202 addword (outro >> 16);
2203 if (siz2 != SIZE_UNSPEC)
2209 nextword = get_num (&opP->disp, 80);
2210 switch (opP->disp.size)
2215 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2217 tmpreg = 0x38; /* 7.0 */
2221 /* Don't generate pc relative code on 68010 and
2223 if (isvar (&opP->disp)
2224 && !subs (&opP->disp)
2225 && adds (&opP->disp)
2227 /* If the displacement needs pic relocation it
2228 cannot be relaxed. */
2229 && opP->disp.pic_reloc == pic_none
2231 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2232 && cpu_of_arch (current_architecture) >= m68020
2234 && !strchr ("~%&$?", s[0]))
2236 tmpreg = 0x3A; /* 7.2 */
2237 add_frag (adds (&opP->disp),
2239 TAB (PCREL, SZ_UNDEF));
2242 /* Fall through into long */
2244 if (isvar (&opP->disp))
2245 add_fix ('l', &opP->disp, 0, 0);
2247 tmpreg = 0x39;/* 7.1 mode */
2248 addword (nextword >> 16);
2252 case SIZE_WORD: /* Word */
2253 if (isvar (&opP->disp))
2254 add_fix ('w', &opP->disp, 0, 0);
2256 tmpreg = 0x38;/* 7.0 mode */
2264 as_bad ("unknown/incorrect operand");
2267 install_gen_operand (s[1], tmpreg);
2273 { /* JF: I hate floating point! */
2288 tmpreg = get_num (&opP->disp, tmpreg);
2289 if (isvar (&opP->disp))
2290 add_fix (s[1], &opP->disp, 0, 0);
2293 case 'b': /* Danger: These do no check for
2294 certain types of overflow.
2296 if (!isbyte (tmpreg))
2297 opP->error = "out of range";
2298 insop (tmpreg, opcode);
2299 if (isvar (&opP->disp))
2300 the_ins.reloc[the_ins.nrel - 1].n =
2301 (opcode->m_codenum) * 2 + 1;
2304 if (!issbyte (tmpreg))
2305 opP->error = "out of range";
2306 opcode->m_opcode |= tmpreg;
2307 if (isvar (&opP->disp))
2308 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2311 if (!isword (tmpreg))
2312 opP->error = "out of range";
2313 insop (tmpreg, opcode);
2314 if (isvar (&opP->disp))
2315 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2318 if (!issword (tmpreg))
2319 opP->error = "out of range";
2320 insop (tmpreg, opcode);
2321 if (isvar (&opP->disp))
2322 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2325 /* Because of the way insop works, we put these two out
2327 insop (tmpreg, opcode);
2328 insop (tmpreg >> 16, opcode);
2329 if (isvar (&opP->disp))
2330 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2336 install_operand (s[1], tmpreg);
2347 install_operand (s[1], opP->reg - ADDR);
2351 tmpreg = get_num (&opP->disp, 80);
2355 /* The pc_fix argument winds up in fx_pcrel_adjust,
2356 which is a char, and may therefore be unsigned. We
2357 want to pass -1, but we pass 64 instead, and convert
2358 back in md_pcrel_from. */
2359 add_fix ('B', &opP->disp, 1, 64);
2362 add_fix ('w', &opP->disp, 1, 0);
2367 if (cpu_of_arch (current_architecture) < m68020)
2368 as_warn ("Can't use long branches on 68000/68010");
2369 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2370 add_fix ('l', &opP->disp, 1, 0);
2375 if (subs (&opP->disp)) /* We can't relax it */
2379 /* If the displacement needs pic relocation it cannot be
2381 if (opP->disp.pic_reloc != pic_none)
2385 /* This could either be a symbol, or an absolute
2386 address. No matter, the frag hacking will finger it
2387 out. Not quite: it can't switch from BRANCH to
2388 BCC68000 for the case where opnd is absolute (it
2389 needs to use the 68000 hack since no conditional abs
2391 if (((cpu_of_arch (current_architecture) < m68020)
2392 || (0 == adds (&opP->disp)))
2393 && (the_ins.opcode[0] >= 0x6200)
2394 && (the_ins.opcode[0] <= 0x6f00))
2395 add_frag (adds (&opP->disp), offs (&opP->disp),
2396 TAB (BCC68000, SZ_UNDEF));
2398 add_frag (adds (&opP->disp), offs (&opP->disp),
2399 TAB (ABRANCH, SZ_UNDEF));
2402 if (isvar (&opP->disp))
2405 /* check for DBcc instruction */
2406 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2408 /* size varies if patch */
2409 /* needed for long form */
2410 add_frag (adds (&opP->disp), offs (&opP->disp),
2411 TAB (DBCC, SZ_UNDEF));
2415 add_fix ('w', &opP->disp, 1, 0);
2419 case 'C': /* Fixed size LONG coproc branches */
2420 add_fix ('l', &opP->disp, 1, 0);
2424 case 'c': /* Var size Coprocesssor branches */
2425 if (subs (&opP->disp))
2427 add_fix ('l', &opP->disp, 1, 0);
2428 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2430 else if (adds (&opP->disp))
2431 add_frag (adds (&opP->disp), offs (&opP->disp),
2432 TAB (FBRANCH, SZ_UNDEF));
2435 /* add_frag((symbolS *) 0, offs(&opP->disp),
2436 TAB(FBRANCH,SHORT)); */
2437 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2438 add_fix ('l', &opP->disp, 1, 0);
2448 case 'C': /* Ignore it */
2451 case 'd': /* JF this is a kludge */
2452 install_operand ('s', opP->reg - ADDR);
2453 tmpreg = get_num (&opP->disp, 80);
2454 if (!issword (tmpreg))
2456 as_warn ("Expression out of range, using 0");
2463 install_operand (s[1], opP->reg - DATA);
2467 install_operand (s[1], opP->reg - FP0);
2471 tmpreg = opP->reg - COP0;
2472 install_operand (s[1], tmpreg);
2475 case 'J': /* JF foo */
2548 install_operand (s[1], tmpreg);
2552 tmpreg = get_num (&opP->disp, 55);
2553 install_operand (s[1], tmpreg & 0x7f);
2560 if (tmpreg & 0x7FF0000)
2561 as_bad ("Floating point register in register list");
2562 insop (reverse_16_bits (tmpreg), opcode);
2566 if (tmpreg & 0x700FFFF)
2567 as_bad ("Wrong register in floating-point reglist");
2568 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2576 if (tmpreg & 0x7FF0000)
2577 as_bad ("Floating point register in register list");
2578 insop (tmpreg, opcode);
2580 else if (s[1] == '8')
2582 if (tmpreg & 0x0FFFFFF)
2583 as_bad ("incorrect register in reglist");
2584 install_operand (s[1], tmpreg >> 24);
2588 if (tmpreg & 0x700FFFF)
2589 as_bad ("wrong register in floating-point reglist");
2591 install_operand (s[1], tmpreg >> 16);
2596 install_operand (s[1], get_num (&opP->disp, 60));
2600 tmpreg = ((opP->mode == DREG)
2601 ? 0x20 + opP->reg - DATA
2602 : (get_num (&opP->disp, 40) & 0x1F));
2603 install_operand (s[1], tmpreg);
2607 tmpreg = get_num (&opP->disp, 10);
2610 install_operand (s[1], tmpreg);
2614 /* This depends on the fact that ADDR registers are eight
2615 more than their corresponding DATA regs, so the result
2616 will have the ADDR_REG bit set */
2617 install_operand (s[1], opP->reg - DATA);
2621 if (opP->mode == AINDR)
2622 install_operand (s[1], opP->reg - DATA);
2624 install_operand (s[1], opP->index.reg - DATA);
2628 if (opP->reg == FPI)
2630 else if (opP->reg == FPS)
2632 else if (opP->reg == FPC)
2636 install_operand (s[1], tmpreg);
2639 case 'S': /* Ignore it */
2643 install_operand (s[1], get_num (&opP->disp, 30));
2646 case 'U': /* Ignore it */
2665 as_fatal ("failed sanity check");
2666 } /* switch on cache token */
2667 install_operand (s[1], tmpreg);
2670 /* JF: These are out of order, I fear. */
2683 install_operand (s[1], tmpreg);
2709 install_operand (s[1], tmpreg);
2713 if (opP->reg == VAL)
2732 install_operand (s[1], tmpreg);
2746 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2757 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2763 install_operand (s[1], tmpreg);
2766 know (opP->reg == PSR);
2769 know (opP->reg == PCSR);
2784 install_operand (s[1], tmpreg);
2787 tmpreg = get_num (&opP->disp, 20);
2788 install_operand (s[1], tmpreg);
2790 case '_': /* used only for move16 absolute 32-bit address */
2791 tmpreg = get_num (&opP->disp, 80);
2792 addword (tmpreg >> 16);
2793 addword (tmpreg & 0xFFFF);
2800 /* By the time whe get here (FINALLY) the_ins contains the complete
2801 instruction, ready to be emitted. . . */
2805 reverse_16_bits (in)
2811 static int mask[16] =
2813 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2814 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2816 for (n = 0; n < 16; n++)
2819 out |= mask[15 - n];
2822 } /* reverse_16_bits() */
2831 static int mask[8] =
2833 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2836 for (n = 0; n < 8; n++)
2842 } /* reverse_8_bits() */
2844 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2845 (that value is chosen in the frag_var call in md_assemble). TYPE
2846 is the subtype of the frag to be generated; its primary type is
2847 rs_machine_dependent.
2849 The TYPE parameter is also used by md_convert_frag_1 and
2850 md_estimate_size_before_relax. The appropriate type of fixup will
2851 be emitted by md_convert_frag_1.
2853 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2855 install_operand (mode, val)
2862 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2865 the_ins.opcode[0] |= val << 9;
2868 the_ins.opcode[1] |= val << 12;
2871 the_ins.opcode[1] |= val << 6;
2874 the_ins.opcode[1] |= val;
2877 the_ins.opcode[2] |= val << 12;
2880 the_ins.opcode[2] |= val << 6;
2883 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2884 three words long! */
2886 the_ins.opcode[2] |= val;
2889 the_ins.opcode[1] |= val << 7;
2892 the_ins.opcode[1] |= val << 10;
2896 the_ins.opcode[1] |= val << 5;
2901 the_ins.opcode[1] |= (val << 10) | (val << 7);
2904 the_ins.opcode[1] |= (val << 12) | val;
2907 the_ins.opcode[0] |= val = 0xff;
2910 the_ins.opcode[0] |= val << 9;
2913 the_ins.opcode[1] |= val;
2916 the_ins.opcode[1] |= val;
2917 the_ins.numo++; /* What a hack */
2920 the_ins.opcode[1] |= val << 4;
2928 the_ins.opcode[0] |= (val << 6);
2931 the_ins.opcode[1] = (val >> 16);
2932 the_ins.opcode[2] = val & 0xffff;
2936 as_fatal ("failed sanity check.");
2938 } /* install_operand() */
2941 install_gen_operand (mode, val)
2948 the_ins.opcode[0] |= val;
2951 /* This is a kludge!!! */
2952 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2961 the_ins.opcode[0] |= val;
2963 /* more stuff goes here */
2965 as_fatal ("failed sanity check.");
2967 } /* install_gen_operand() */
2970 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2971 * then deal with the bitfield hack.
2975 crack_operand (str, opP)
2977 register struct m68k_op *opP;
2979 register int parens;
2981 register char *beg_str;
2989 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2995 else if (*str == ')')
2999 opP->error = "Extra )";
3005 if (flag_mri && *str == '\'')
3006 inquote = ! inquote;
3008 if (!*str && parens)
3010 opP->error = "Missing )";
3015 if (m68k_ip_op (beg_str, opP) != 0)
3022 c = *++str; /* JF bitfield hack */
3027 as_bad ("Missing operand");
3032 /* This is the guts of the machine-dependent assembler. STR points to a
3033 machine dependent instruction. This function is supposed to emit
3034 the frags/bytes it assembles to.
3038 insert_reg (regname, regnum)
3045 #ifdef REGISTER_PREFIX
3046 if (!flag_reg_prefix_optional)
3048 buf[0] = REGISTER_PREFIX;
3049 strcpy (buf + 1, regname);
3054 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3055 &zero_address_frag));
3057 for (i = 0; regname[i]; i++)
3058 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3061 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3062 &zero_address_frag));
3071 static const struct init_entry init_table[] =
3126 /* control registers */
3127 { "sfc", SFC }, /* Source Function Code */
3129 { "dfc", DFC }, /* Destination Function Code */
3131 { "cacr", CACR }, /* Cache Control Register */
3132 { "caar", CAAR }, /* Cache Address Register */
3134 { "usp", USP }, /* User Stack Pointer */
3135 { "vbr", VBR }, /* Vector Base Register */
3136 { "msp", MSP }, /* Master Stack Pointer */
3137 { "isp", ISP }, /* Interrupt Stack Pointer */
3139 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3140 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3141 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3142 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3144 /* 68ec040 versions of same */
3145 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3146 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3147 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3148 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3150 /* mcf5200 versions of same. The ColdFire programmer's reference
3151 manual indicated that the order is 2,3,0,1, but Ken Rose
3152 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3153 { "acr0", ITT0 }, /* Access Control Unit 0 */
3154 { "acr1", ITT1 }, /* Access Control Unit 1 */
3155 { "acr2", DTT0 }, /* Access Control Unit 2 */
3156 { "acr3", DTT1 }, /* Access Control Unit 3 */
3158 { "tc", TC }, /* MMU Translation Control Register */
3161 { "mmusr", MMUSR }, /* MMU Status Register */
3162 { "srp", SRP }, /* User Root Pointer */
3163 { "urp", URP }, /* Supervisor Root Pointer */
3168 { "rombar", ROMBAR }, /* ROM Base Address Register */
3169 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3170 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3171 { "mbar", MBAR }, /* Module Base Address Register */
3172 /* end of control registers */
3206 /* 68ec030 versions of same */
3209 /* 68ec030 access control unit, identical to 030 MMU status reg */
3212 /* Suppressed data and address registers. */
3237 for (i = 0; init_table[i].name; i++)
3238 insert_reg (init_table[i].name, init_table[i].number);
3241 static int no_68851, no_68881;
3244 /* a.out machine type. Default to 68020. */
3245 int m68k_aout_machtype = 2;
3257 int shorts_this_frag;
3260 /* In MRI mode, the instruction and operands are separated by a
3261 space. Anything following the operands is a comment. The label
3262 has already been removed. */
3270 for (s = str; *s != '\0'; s++)
3272 if ((*s == ' ' || *s == '\t') && ! inquote)
3290 inquote = ! inquote;
3295 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3300 for (n = 0; n < the_ins.numargs; n++)
3301 if (the_ins.operands[n].error)
3303 er = the_ins.operands[n].error;
3309 as_bad ("%s -- statement `%s' ignored", er, str);
3313 if (the_ins.nfrag == 0)
3315 /* No frag hacking involved; just put it out */
3316 toP = frag_more (2 * the_ins.numo);
3317 fromP = &the_ins.opcode[0];
3318 for (m = the_ins.numo; m; --m)
3320 md_number_to_chars (toP, (long) (*fromP), 2);
3324 /* put out symbol-dependent info */
3325 for (m = 0; m < the_ins.nrel; m++)
3327 switch (the_ins.reloc[m].wid)
3345 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3346 the_ins.reloc[m].wid);
3349 fixP = fix_new_exp (frag_now,
3350 ((toP - frag_now->fr_literal)
3351 - the_ins.numo * 2 + the_ins.reloc[m].n),
3353 &the_ins.reloc[m].exp,
3354 the_ins.reloc[m].pcrel,
3355 get_reloc_code (n, the_ins.reloc[m].pcrel,
3356 the_ins.reloc[m].pic_reloc));
3357 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3358 if (the_ins.reloc[m].wid == 'B')
3359 fixP->fx_signed = 1;
3364 /* There's some frag hacking */
3365 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3370 wid = 2 * the_ins.fragb[n].fragoff;
3372 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3373 toP = frag_more (wid);
3375 shorts_this_frag = 0;
3376 for (m = wid / 2; m; --m)
3378 md_number_to_chars (toP, (long) (*fromP), 2);
3383 for (m = 0; m < the_ins.nrel; m++)
3385 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3387 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3390 wid = the_ins.reloc[m].wid;
3393 the_ins.reloc[m].wid = 0;
3394 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3396 fixP = fix_new_exp (frag_now,
3397 ((toP - frag_now->fr_literal)
3398 - the_ins.numo * 2 + the_ins.reloc[m].n),
3400 &the_ins.reloc[m].exp,
3401 the_ins.reloc[m].pcrel,
3402 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3403 the_ins.reloc[m].pic_reloc));
3404 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3406 (void) frag_var (rs_machine_dependent, 10, 0,
3407 (relax_substateT) (the_ins.fragb[n].fragty),
3408 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3410 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3411 shorts_this_frag = 0;
3414 toP = frag_more (n * sizeof (short));
3417 md_number_to_chars (toP, (long) (*fromP), 2);
3423 for (m = 0; m < the_ins.nrel; m++)
3427 wid = the_ins.reloc[m].wid;
3430 the_ins.reloc[m].wid = 0;
3431 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3433 fixP = fix_new_exp (frag_now,
3434 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3435 - shorts_this_frag * 2),
3437 &the_ins.reloc[m].exp,
3438 the_ins.reloc[m].pcrel,
3439 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3440 the_ins.reloc[m].pic_reloc));
3441 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3449 * md_begin -- set up hash tables with 68000 instructions.
3450 * similar to what the vax assembler does. ---phr
3452 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3453 a copy of it at runtime, adding in the information we want but isn't
3454 there. I think it'd be better to have an awk script hack the table
3455 at compile time. Or even just xstr the table and use it as-is. But
3456 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3459 register const struct m68k_opcode *ins;
3460 register struct m68k_incant *hack, *slak;
3461 register const char *retval = 0; /* empty string, or error msg text */
3462 register unsigned int i;
3467 flag_reg_prefix_optional = 1;
3469 if (! m68k_rel32_from_cmdline)
3473 op_hash = hash_new ();
3475 obstack_begin (&robyn, 4000);
3476 for (i = 0; i < m68k_numopcodes; i++)
3478 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3481 ins = &m68k_opcodes[i];
3482 /* We *could* ignore insns that don't match our arch here
3483 but just leaving them out of the hash. */
3484 slak->m_operands = ins->args;
3485 slak->m_opnum = strlen (slak->m_operands) / 2;
3486 slak->m_arch = ins->arch;
3487 slak->m_opcode = ins->opcode;
3488 /* This is kludgey */
3489 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3490 if (i + 1 != m68k_numopcodes
3491 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3493 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3498 slak = slak->m_next;
3502 retval = hash_insert (op_hash, ins->name, (char *) hack);
3504 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3507 for (i = 0; i < m68k_numaliases; i++)
3509 const char *name = m68k_opcode_aliases[i].primary;
3510 const char *alias = m68k_opcode_aliases[i].alias;
3511 PTR val = hash_find (op_hash, name);
3513 as_fatal ("Internal Error: Can't find %s in hash table", name);
3514 retval = hash_insert (op_hash, alias, val);
3516 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3519 /* In MRI mode, all unsized branches are variable sized. Normally,
3520 they are word sized. */
3523 static struct m68k_opcode_alias mri_aliases[] =
3543 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3545 const char *name = mri_aliases[i].primary;
3546 const char *alias = mri_aliases[i].alias;
3547 PTR val = hash_find (op_hash, name);
3549 as_fatal ("Internal Error: Can't find %s in hash table", name);
3550 retval = hash_jam (op_hash, alias, val);
3552 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3556 for (i = 0; i < sizeof (mklower_table); i++)
3557 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3559 for (i = 0; i < sizeof (notend_table); i++)
3561 notend_table[i] = 0;
3562 alt_notend_table[i] = 0;
3564 notend_table[','] = 1;
3565 notend_table['{'] = 1;
3566 notend_table['}'] = 1;
3567 alt_notend_table['a'] = 1;
3568 alt_notend_table['A'] = 1;
3569 alt_notend_table['d'] = 1;
3570 alt_notend_table['D'] = 1;
3571 alt_notend_table['#'] = 1;
3572 alt_notend_table['&'] = 1;
3573 alt_notend_table['f'] = 1;
3574 alt_notend_table['F'] = 1;
3575 #ifdef REGISTER_PREFIX
3576 alt_notend_table[REGISTER_PREFIX] = 1;
3579 /* We need to put '(' in alt_notend_table to handle
3580 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3582 alt_notend_table['('] = 1;
3584 /* We need to put '@' in alt_notend_table to handle
3585 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3587 alt_notend_table['@'] = 1;
3589 /* We need to put digits in alt_notend_table to handle
3590 bfextu %d0{24:1},%d0
3592 alt_notend_table['0'] = 1;
3593 alt_notend_table['1'] = 1;
3594 alt_notend_table['2'] = 1;
3595 alt_notend_table['3'] = 1;
3596 alt_notend_table['4'] = 1;
3597 alt_notend_table['5'] = 1;
3598 alt_notend_table['6'] = 1;
3599 alt_notend_table['7'] = 1;
3600 alt_notend_table['8'] = 1;
3601 alt_notend_table['9'] = 1;
3603 #ifndef MIT_SYNTAX_ONLY
3604 /* Insert pseudo ops, these have to go into the opcode table since
3605 gas expects pseudo ops to start with a dot */
3608 while (mote_pseudo_table[n].poc_name)
3610 hack = (struct m68k_incant *)
3611 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3612 hash_insert (op_hash,
3613 mote_pseudo_table[n].poc_name, (char *) hack);
3614 hack->m_operands = 0;
3624 record_alignment (text_section, 2);
3625 record_alignment (data_section, 2);
3626 record_alignment (bss_section, 2);
3631 select_control_regs ()
3633 /* Note which set of "movec" control registers is available. */
3634 switch (cpu_of_arch (current_architecture))
3637 control_regs = m68000_control_regs;
3640 control_regs = m68010_control_regs;
3644 control_regs = m68020_control_regs;
3647 control_regs = m68040_control_regs;
3650 control_regs = m68060_control_regs;
3653 control_regs = cpu32_control_regs;
3656 control_regs = mcf5200_control_regs;
3664 m68k_init_after_args ()
3666 if (cpu_of_arch (current_architecture) == 0)
3669 const char *default_cpu = TARGET_CPU;
3671 if (*default_cpu == 'm')
3673 for (i = 0; i < n_archs; i++)
3674 if (strcasecmp (default_cpu, archs[i].name) == 0)
3678 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3679 current_architecture |= m68020;
3682 current_architecture |= archs[i].arch;
3684 /* Permit m68881 specification with all cpus; those that can't work
3685 with a coprocessor could be doing emulation. */
3686 if (current_architecture & m68851)
3688 if (current_architecture & m68040)
3690 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3693 /* What other incompatibilities could we check for? */
3695 /* Toss in some default assumptions about coprocessors. */
3697 && (cpu_of_arch (current_architecture)
3698 /* Can CPU32 have a 68881 coprocessor?? */
3699 & (m68020 | m68030 | cpu32)))
3701 current_architecture |= m68881;
3704 && (cpu_of_arch (current_architecture) & m68020up) != 0
3705 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3707 current_architecture |= m68851;
3709 if (no_68881 && (current_architecture & m68881))
3710 as_bad ("options for 68881 and no-68881 both given");
3711 if (no_68851 && (current_architecture & m68851))
3712 as_bad ("options for 68851 and no-68851 both given");
3715 /* Work out the magic number. This isn't very general. */
3716 if (current_architecture & m68000)
3717 m68k_aout_machtype = 0;
3718 else if (current_architecture & m68010)
3719 m68k_aout_machtype = 1;
3720 else if (current_architecture & m68020)
3721 m68k_aout_machtype = 2;
3723 m68k_aout_machtype = 2;
3726 /* Note which set of "movec" control registers is available. */
3727 select_control_regs ();
3729 if (cpu_of_arch (current_architecture) < m68020)
3730 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3733 /* This is called if we go in or out of MRI mode because of the .mri
3737 m68k_mri_mode_change (on)
3742 if (! flag_reg_prefix_optional)
3744 flag_reg_prefix_optional = 1;
3745 #ifdef REGISTER_PREFIX
3750 if (! m68k_rel32_from_cmdline)
3755 if (! reg_prefix_optional_seen)
3757 #ifdef REGISTER_PREFIX_OPTIONAL
3758 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3760 flag_reg_prefix_optional = 0;
3762 #ifdef REGISTER_PREFIX
3767 if (! m68k_rel32_from_cmdline)
3772 /* Equal to MAX_PRECISION in atof-ieee.c */
3773 #define MAX_LITTLENUMS 6
3775 /* Turn a string in input_line_pointer into a floating point constant
3776 of type type, and store the appropriate bytes in *litP. The number
3777 of LITTLENUMS emitted is stored in *sizeP . An error message is
3778 returned, or NULL on OK. */
3781 md_atof (type, litP, sizeP)
3787 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3788 LITTLENUM_TYPE *wordP;
3820 return "Bad call to MD_ATOF()";
3822 t = atof_ieee (input_line_pointer, type, words);
3824 input_line_pointer = t;
3826 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3827 for (wordP = words; prec--;)
3829 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3830 litP += sizeof (LITTLENUM_TYPE);
3836 md_number_to_chars (buf, val, n)
3841 number_to_chars_bigendian (buf, val, n);
3845 md_apply_fix_2 (fixP, val)
3849 addressT upper_limit;
3850 offsetT lower_limit;
3852 /* This is unnecessary but it convinces the native rs6000 compiler
3853 to generate the code we want. */
3854 char *buf = fixP->fx_frag->fr_literal;
3855 buf += fixP->fx_where;
3856 /* end ibm compiler workaround */
3858 if (val & 0x80000000)
3859 val |= ~(addressT)0x7fffffff;
3866 memset (buf, 0, fixP->fx_size);
3867 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3872 switch (fixP->fx_size)
3874 /* The cast to offsetT below are necessary to make code correct for
3875 machines where ints are smaller than offsetT */
3879 lower_limit = - (offsetT) 0x80;
3882 *buf++ = (val >> 8);
3884 upper_limit = 0x7fff;
3885 lower_limit = - (offsetT) 0x8000;
3888 *buf++ = (val >> 24);
3889 *buf++ = (val >> 16);
3890 *buf++ = (val >> 8);
3892 upper_limit = 0x7fffffff;
3893 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3896 BAD_CASE (fixP->fx_size);
3899 /* Fix up a negative reloc. */
3900 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3902 fixP->fx_addsy = fixP->fx_subsy;
3903 fixP->fx_subsy = NULL;
3907 /* For non-pc-relative values, it's conceivable we might get something
3908 like "0xff" for a byte field. So extend the upper part of the range
3909 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3910 so that we can do any range checking at all. */
3911 if (! fixP->fx_pcrel && ! fixP->fx_signed)
3912 upper_limit = upper_limit * 2 + 1;
3914 if ((addressT) val > upper_limit
3915 && (val > 0 || val < lower_limit))
3916 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3918 /* A one byte PC-relative reloc means a short branch. We can't use
3919 a short branch with a value of 0 or -1, because those indicate
3920 different opcodes (branches with longer offsets). */
3922 && fixP->fx_size == 1
3923 && (fixP->fx_addsy == NULL
3924 || S_IS_DEFINED (fixP->fx_addsy))
3925 && (val == 0 || val == -1))
3926 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3929 #ifdef BFD_ASSEMBLER
3931 md_apply_fix (fixP, valp)
3935 md_apply_fix_2 (fixP, (addressT) *valp);
3939 void md_apply_fix (fixP, val)
3943 md_apply_fix_2 (fixP, (addressT) val);
3947 /* *fragP has been relaxed to its final size, and now needs to have
3948 the bytes inside it modified to conform to the new size There is UGLY
3952 md_convert_frag_1 (fragP)
3953 register fragS *fragP;
3959 /* Address in object code of the displacement. */
3960 register int object_address = fragP->fr_fix + fragP->fr_address;
3962 /* Address in gas core of the place to store the displacement. */
3963 /* This convinces the native rs6000 compiler to generate the code we
3965 register char *buffer_address = fragP->fr_literal;
3966 buffer_address += fragP->fr_fix;
3967 /* end ibm compiler workaround */
3969 /* The displacement of the address, from current location. */
3970 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3971 disp = (disp + fragP->fr_offset) - object_address;
3973 #ifdef BFD_ASSEMBLER
3974 disp += fragP->fr_symbol->sy_frag->fr_address;
3977 switch (fragP->fr_subtype)
3979 case TAB (BCC68000, BYTE):
3980 case TAB (ABRANCH, BYTE):
3981 know (issbyte (disp));
3983 as_bad ("short branch with zero offset: use :w");
3984 fragP->fr_opcode[1] = disp;
3987 case TAB (DBCC, SHORT):
3988 know (issword (disp));
3991 case TAB (BCC68000, SHORT):
3992 case TAB (ABRANCH, SHORT):
3993 know (issword (disp));
3994 fragP->fr_opcode[1] = 0x00;
3997 case TAB (ABRANCH, LONG):
3998 if (cpu_of_arch (current_architecture) < m68020)
4000 if (fragP->fr_opcode[0] == 0x61)
4003 fragP->fr_opcode[0] = 0x4E;
4004 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4018 else if (fragP->fr_opcode[0] == 0x60)
4020 fragP->fr_opcode[0] = 0x4E;
4021 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4022 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4023 fragP->fr_offset, 0, NO_RELOC);
4029 as_bad ("Long branch offset not supported.");
4034 fragP->fr_opcode[1] = (char) 0xff;
4038 case TAB (BCC68000, LONG):
4039 /* only Bcc 68000 instructions can come here */
4040 /* change bcc into b!cc/jmp absl long */
4041 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4042 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4044 /* JF: these used to be fr_opcode[2,3], but they may be in a
4045 different frag, in which case refering to them is a no-no.
4046 Only fr_opcode[0,1] are guaranteed to work. */
4047 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4048 *buffer_address++ = (char) 0xf9;
4049 fragP->fr_fix += 2; /* account for jmp instruction */
4050 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4051 fragP->fr_offset, 0, NO_RELOC);
4055 case TAB (DBCC, LONG):
4056 /* only DBcc 68000 instructions can come here */
4057 /* change dbcc into dbcc/jmp absl long */
4058 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4059 *buffer_address++ = 0x00; /* branch offset = 4 */
4060 *buffer_address++ = 0x04;
4061 *buffer_address++ = 0x60; /* put in bra pc+6 */
4062 *buffer_address++ = 0x06;
4063 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4064 *buffer_address++ = (char) 0xf9;
4066 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4067 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4068 fragP->fr_offset, 0, NO_RELOC);
4072 case TAB (FBRANCH, SHORT):
4073 know ((fragP->fr_opcode[1] & 0x40) == 0);
4076 case TAB (FBRANCH, LONG):
4077 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4080 case TAB (PCREL, SHORT):
4083 case TAB (PCREL, LONG):
4084 /* The thing to do here is force it to ABSOLUTE LONG, since
4085 PCREL is really trying to shorten an ABSOLUTE address anyway */
4086 /* JF FOO This code has not been tested */
4087 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4089 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4090 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4091 (unsigned) fragP->fr_opcode[0],
4092 (unsigned long) fragP->fr_address);
4093 fragP->fr_opcode[1] &= ~0x3F;
4094 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4098 case TAB (PCLEA, SHORT):
4099 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4100 fragP->fr_offset, 1, NO_RELOC);
4101 fragP->fr_opcode[1] &= ~0x3F;
4102 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4105 case TAB (PCLEA, LONG):
4106 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4107 fragP->fr_offset, 1, NO_RELOC);
4108 fixP->fx_pcrel_adjust = 2;
4109 /* Already set to mode 7.3; this indicates: PC indirect with
4110 suppressed index, 32-bit displacement. */
4111 *buffer_address++ = 0x01;
4112 *buffer_address++ = 0x70;
4117 case TAB (PCINDEX, BYTE):
4119 if (!issbyte (disp))
4121 as_bad ("displacement doesn't fit in one byte");
4124 assert (fragP->fr_fix >= 2);
4125 buffer_address[-2] &= ~1;
4126 buffer_address[-1] = disp;
4129 case TAB (PCINDEX, SHORT):
4131 assert (issword (disp));
4132 assert (fragP->fr_fix >= 2);
4133 buffer_address[-2] |= 0x1;
4134 buffer_address[-1] = 0x20;
4135 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4136 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4138 fixP->fx_pcrel_adjust = 2;
4141 case TAB (PCINDEX, LONG):
4143 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4144 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4146 fixP->fx_pcrel_adjust = 2;
4147 assert (fragP->fr_fix >= 2);
4148 buffer_address[-2] |= 0x1;
4149 buffer_address[-1] = 0x30;
4156 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4157 fragP->fr_fix += ext;
4161 #ifndef BFD_ASSEMBLER
4164 md_convert_frag (headers, sec, fragP)
4165 object_headers *headers;
4169 md_convert_frag_1 (fragP);
4175 md_convert_frag (abfd, sec, fragP)
4180 md_convert_frag_1 (fragP);
4184 /* Force truly undefined symbols to their maximum size, and generally set up
4185 the frag list to be relaxed
4188 md_estimate_size_before_relax (fragP, segment)
4189 register fragS *fragP;
4193 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4195 old_fix = fragP->fr_fix;
4197 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4198 switch (fragP->fr_subtype)
4201 case TAB (ABRANCH, SZ_UNDEF):
4203 if ((fragP->fr_symbol != NULL) /* Not absolute */
4204 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4206 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4209 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4211 /* On 68000, or for absolute value, switch to abs long */
4212 /* FIXME, we should check abs val, pick short or long */
4213 if (fragP->fr_opcode[0] == 0x61)
4215 fragP->fr_opcode[0] = 0x4E;
4216 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4217 fix_new (fragP, fragP->fr_fix, 4,
4218 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4222 else if (fragP->fr_opcode[0] == 0x60)
4224 fragP->fr_opcode[0] = 0x4E;
4225 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4226 fix_new (fragP, fragP->fr_fix, 4,
4227 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4233 as_warn ("Long branch offset to extern symbol not supported.");
4237 { /* Symbol is still undefined. Make it simple */
4238 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4239 fragP->fr_offset, 1, NO_RELOC);
4241 fragP->fr_opcode[1] = (char) 0xff;
4247 } /* case TAB(ABRANCH,SZ_UNDEF) */
4249 case TAB (FBRANCH, SZ_UNDEF):
4251 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4253 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4258 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4259 fragP->fr_offset, 1, NO_RELOC);
4261 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4265 } /* TAB(FBRANCH,SZ_UNDEF) */
4267 case TAB (PCREL, SZ_UNDEF):
4269 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4271 || cpu_of_arch (current_architecture) < m68020)
4273 fragP->fr_subtype = TAB (PCREL, SHORT);
4278 fragP->fr_subtype = TAB (PCREL, LONG);
4282 } /* TAB(PCREL,SZ_UNDEF) */
4284 case TAB (BCC68000, SZ_UNDEF):
4286 if ((fragP->fr_symbol != NULL)
4287 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4289 fragP->fr_subtype = TAB (BCC68000, BYTE);
4292 /* only Bcc 68000 instructions can come here */
4293 /* change bcc into b!cc/jmp absl long */
4294 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4295 if (flag_short_refs)
4297 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4298 /* JF: these were fr_opcode[2,3] */
4299 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4300 buffer_address[1] = (char) 0xf8;
4301 fragP->fr_fix += 2; /* account for jmp instruction */
4302 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4303 fragP->fr_offset, 0, NO_RELOC);
4308 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4309 /* JF: these were fr_opcode[2,3] */
4310 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4311 buffer_address[1] = (char) 0xf9;
4312 fragP->fr_fix += 2; /* account for jmp instruction */
4313 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4314 fragP->fr_offset, 0, NO_RELOC);
4319 } /* case TAB(BCC68000,SZ_UNDEF) */
4321 case TAB (DBCC, SZ_UNDEF):
4323 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4325 fragP->fr_subtype = TAB (DBCC, SHORT);
4329 /* only DBcc 68000 instructions can come here */
4330 /* change dbcc into dbcc/jmp absl long */
4331 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4332 buffer_address[0] = 0x00; /* branch offset = 4 */
4333 buffer_address[1] = 0x04;
4334 buffer_address[2] = 0x60; /* put in bra pc + ... */
4336 if (flag_short_refs)
4338 /* JF: these were fr_opcode[5-7] */
4339 buffer_address[3] = 0x04; /* plus 4 */
4340 buffer_address[4] = 0x4e; /* Put in Jump Word */
4341 buffer_address[5] = (char) 0xf8;
4342 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4343 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4344 fragP->fr_offset, 0, NO_RELOC);
4349 /* JF: these were fr_opcode[5-7] */
4350 buffer_address[3] = 0x06; /* Plus 6 */
4351 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4352 buffer_address[5] = (char) 0xf9;
4353 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4354 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4355 fragP->fr_offset, 0, NO_RELOC);
4361 } /* case TAB(DBCC,SZ_UNDEF) */
4363 case TAB (PCLEA, SZ_UNDEF):
4365 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4367 || cpu_of_arch (current_architecture) < m68020)
4369 fragP->fr_subtype = TAB (PCLEA, SHORT);
4374 fragP->fr_subtype = TAB (PCLEA, LONG);
4378 } /* TAB(PCLEA,SZ_UNDEF) */
4380 case TAB (PCINDEX, SZ_UNDEF):
4381 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4382 || cpu_of_arch (current_architecture) < m68020)
4384 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4388 fragP->fr_subtype = TAB (PCINDEX, LONG);
4397 /* now that SZ_UNDEF are taken care of, check others */
4398 switch (fragP->fr_subtype)
4400 case TAB (BCC68000, BYTE):
4401 case TAB (ABRANCH, BYTE):
4402 /* We can't do a short jump to the next instruction, so in that
4403 case we force word mode. At this point S_GET_VALUE should
4404 return the offset of the symbol within its frag. If the
4405 symbol is at the start of a frag, and it is the next frag
4406 with any data in it (usually this is just the next frag, but
4407 assembler listings may introduce empty frags), we must use
4409 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4413 for (l = fragP->fr_next;
4414 l != fragP->fr_symbol->sy_frag;
4416 if (l->fr_fix + l->fr_var != 0)
4418 if (l == fragP->fr_symbol->sy_frag)
4420 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4428 return fragP->fr_var + fragP->fr_fix - old_fix;
4431 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4432 /* the bit-field entries in the relocation_info struct plays hell
4433 with the byte-order problems of cross-assembly. So as a hack,
4434 I added this mach. dependent ri twiddler. Ugly, but it gets
4436 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4437 are symbolnum, most sig. byte first. Last byte is broken up with
4438 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4439 nibble as nuthin. (on Sun 3 at least) */
4440 /* Translate the internal relocation information into target-specific
4444 md_ri_to_chars (the_bytes, ri)
4446 struct reloc_info_generic *ri;
4449 md_number_to_chars (the_bytes, ri->r_address, 4);
4450 /* now the fun stuff */
4451 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4452 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4453 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4454 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4455 ((ri->r_extern << 4) & 0x10));
4458 #endif /* comment */
4460 #ifndef BFD_ASSEMBLER
4462 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4465 relax_addressT segment_address_in_file;
4468 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4469 * Out: GNU LD relocation length code: 0, 1, or 2.
4472 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4475 know (fixP->fx_addsy != NULL);
4477 md_number_to_chars (where,
4478 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4481 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4482 ? S_GET_TYPE (fixP->fx_addsy)
4483 : fixP->fx_addsy->sy_number);
4485 where[4] = (r_symbolnum >> 16) & 0x0ff;
4486 where[5] = (r_symbolnum >> 8) & 0x0ff;
4487 where[6] = r_symbolnum & 0x0ff;
4488 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4489 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4493 #endif /* OBJ_AOUT or OBJ_BOUT */
4495 #ifndef WORKING_DOT_WORD
4496 CONST int md_short_jump_size = 4;
4497 CONST int md_long_jump_size = 6;
4500 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4502 addressT from_addr, to_addr;
4508 offset = to_addr - (from_addr + 2);
4510 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4511 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4515 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4517 addressT from_addr, to_addr;
4523 if (cpu_of_arch (current_architecture) < m68020)
4525 offset = to_addr - S_GET_VALUE (to_symbol);
4526 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4527 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4528 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4533 offset = to_addr - (from_addr + 2);
4534 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4535 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4541 /* Different values of OK tell what its OK to return. Things that
4542 aren't OK are an error (what a shock, no?)
4545 10: Absolute 1:8 only
4546 20: Absolute 0:7 only
4547 30: absolute 0:15 only
4548 40: Absolute 0:31 only
4549 50: absolute 0:127 only
4550 55: absolute -64:63 only
4551 60: absolute -128:127 only
4552 70: absolute 0:4095 only
4559 struct m68k_exp *exp;
4562 if (exp->exp.X_op == O_absent)
4564 /* Do the same thing the VAX asm does */
4565 op (exp) = O_constant;
4571 as_warn ("expression out of range: defaulting to 1");
4575 else if (exp->exp.X_op == O_constant)
4580 if (offs (exp) < 1 || offs (exp) > 8)
4582 as_warn ("expression out of range: defaulting to 1");
4587 if (offs (exp) < 0 || offs (exp) > 7)
4591 if (offs (exp) < 0 || offs (exp) > 15)
4595 if (offs (exp) < 0 || offs (exp) > 32)
4599 if (offs (exp) < 0 || offs (exp) > 127)
4603 if (offs (exp) < -64 || offs (exp) > 63)
4607 if (offs (exp) < -128 || offs (exp) > 127)
4611 if (offs (exp) < 0 || offs (exp) > 4095)
4614 as_warn ("expression out of range: defaulting to 0");
4622 else if (exp->exp.X_op == O_big)
4624 if (offs (exp) <= 0 /* flonum */
4625 && (ok == 80 /* no bignums */
4626 || (ok > 10 /* small-int ranges including 0 ok */
4627 /* If we have a flonum zero, a zero integer should
4628 do as well (e.g., in moveq). */
4629 && generic_floating_point_number.exponent == 0
4630 && generic_floating_point_number.low[0] == 0)))
4632 /* HACK! Turn it into a long */
4633 LITTLENUM_TYPE words[6];
4635 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4636 op (exp) = O_constant;
4639 offs (exp) = words[1] | (words[0] << 16);
4643 op (exp) = O_constant;
4646 offs (exp) = (ok == 10) ? 1 : 0;
4647 as_warn ("Can't deal with expression; defaulting to %ld",
4653 if (ok >= 10 && ok <= 70)
4655 op (exp) = O_constant;
4658 offs (exp) = (ok == 10) ? 1 : 0;
4659 as_warn ("Can't deal with expression; defaulting to %ld",
4664 if (exp->size != SIZE_UNSPEC)
4672 if (!isbyte (offs (exp)))
4673 as_warn ("expression doesn't fit in BYTE");
4676 if (!isword (offs (exp)))
4677 as_warn ("expression doesn't fit in WORD");
4685 /* These are the back-ends for the various machine dependent pseudo-ops. */
4686 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4692 subseg_set (data_section, 1);
4693 demand_empty_rest_of_line ();
4700 subseg_set (data_section, 2);
4701 demand_empty_rest_of_line ();
4708 /* We don't support putting frags in the BSS segment, we fake it
4709 by marking in_bss, then looking at s_skip for clues. */
4711 subseg_set (bss_section, 0);
4712 demand_empty_rest_of_line ();
4720 register long temp_fill;
4722 temp = 1; /* JF should be 2? */
4723 temp_fill = get_absolute_expression ();
4724 if (!need_pass_2) /* Never make frag if expect extra pass. */
4725 frag_align (temp, (int) temp_fill);
4726 demand_empty_rest_of_line ();
4733 demand_empty_rest_of_line ();
4736 /* Pseudo-ops handled for MRI compatibility. */
4738 /* This function returns non-zero if the argument is a conditional
4739 pseudo-op. This is called when checking whether a pending
4740 alignment is needed. */
4743 m68k_conditional_pseudoop (pop)
4746 return (pop->poc_handler == s_mri_if
4747 || pop->poc_handler == s_mri_else);
4750 /* Handle an MRI style chip specification. */
4759 s = input_line_pointer;
4760 c = get_symbol_end ();
4761 for (i = 0; i < n_archs; i++)
4762 if (strcasecmp (s, archs[i].name) == 0)
4766 as_bad ("%s: unrecognized processor name", s);
4767 *input_line_pointer = c;
4768 ignore_rest_of_line ();
4771 *input_line_pointer = c;
4773 if (*input_line_pointer == '/')
4774 current_architecture = 0;
4776 current_architecture &= m68881 | m68851;
4777 current_architecture |= archs[i].arch;
4779 while (*input_line_pointer == '/')
4781 ++input_line_pointer;
4782 s = input_line_pointer;
4783 c = get_symbol_end ();
4784 if (strcmp (s, "68881") == 0)
4785 current_architecture |= m68881;
4786 else if (strcmp (s, "68851") == 0)
4787 current_architecture |= m68851;
4788 *input_line_pointer = c;
4791 /* Update info about available control registers. */
4792 select_control_regs ();
4795 /* The MRI CHIP pseudo-op. */
4805 stop = mri_comment_field (&stopc);
4808 mri_comment_end (stop, stopc);
4809 demand_empty_rest_of_line ();
4812 /* The MRI FOPT pseudo-op. */
4820 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4824 input_line_pointer += 3;
4825 temp = get_absolute_expression ();
4826 if (temp < 0 || temp > 7)
4827 as_bad ("bad coprocessor id");
4829 m68k_float_copnum = COP0 + temp;
4833 as_bad ("unrecognized fopt option");
4834 ignore_rest_of_line ();
4838 demand_empty_rest_of_line ();
4841 /* The structure used to handle the MRI OPT pseudo-op. */
4845 /* The name of the option. */
4848 /* If this is not NULL, just call this function. The first argument
4849 is the ARG field of this structure, the second argument is
4850 whether the option was negated. */
4851 void (*pfn) PARAMS ((int arg, int on));
4853 /* If this is not NULL, and the PFN field is NULL, set the variable
4854 this points to. Set it to the ARG field if the option was not
4855 negated, and the NOTARG field otherwise. */
4858 /* The value to pass to PFN or to assign to *PVAR. */
4861 /* The value to assign to *PVAR if the option is negated. If PFN is
4862 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4863 the option may not be negated. */
4867 /* The table used to handle the MRI OPT pseudo-op. */
4869 static void skip_to_comma PARAMS ((int, int));
4870 static void opt_nest PARAMS ((int, int));
4871 static void opt_chip PARAMS ((int, int));
4872 static void opt_list PARAMS ((int, int));
4873 static void opt_list_symbols PARAMS ((int, int));
4875 static const struct opt_action opt_table[] =
4877 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4879 /* We do relaxing, so there is little use for these options. */
4880 { "b", 0, 0, 0, 0 },
4881 { "brs", 0, 0, 0, 0 },
4882 { "brb", 0, 0, 0, 0 },
4883 { "brl", 0, 0, 0, 0 },
4884 { "brw", 0, 0, 0, 0 },
4886 { "c", 0, 0, 0, 0 },
4887 { "cex", 0, 0, 0, 0 },
4888 { "case", 0, &symbols_case_sensitive, 1, 0 },
4889 { "cl", 0, 0, 0, 0 },
4890 { "cre", 0, 0, 0, 0 },
4891 { "d", 0, &flag_keep_locals, 1, 0 },
4892 { "e", 0, 0, 0, 0 },
4893 { "f", 0, &flag_short_refs, 1, 0 },
4894 { "frs", 0, &flag_short_refs, 1, 0 },
4895 { "frl", 0, &flag_short_refs, 0, 1 },
4896 { "g", 0, 0, 0, 0 },
4897 { "i", 0, 0, 0, 0 },
4898 { "m", 0, 0, 0, 0 },
4899 { "mex", 0, 0, 0, 0 },
4900 { "mc", 0, 0, 0, 0 },
4901 { "md", 0, 0, 0, 0 },
4902 { "nest", opt_nest, 0, 0, 0 },
4903 { "next", skip_to_comma, 0, 0, 0 },
4904 { "o", 0, 0, 0, 0 },
4905 { "old", 0, 0, 0, 0 },
4906 { "op", skip_to_comma, 0, 0, 0 },
4907 { "pco", 0, 0, 0, 0 },
4908 { "p", opt_chip, 0, 0, 0 },
4909 { "pcr", 0, 0, 0, 0 },
4910 { "pcs", 0, 0, 0, 0 },
4911 { "r", 0, 0, 0, 0 },
4912 { "quick", 0, &m68k_quick, 1, 0 },
4913 { "rel32", 0, &m68k_rel32, 1, 0 },
4914 { "s", opt_list, 0, 0, 0 },
4915 { "t", opt_list_symbols, 0, 0, 0 },
4916 { "w", 0, &flag_no_warnings, 0, 1 },
4920 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4922 /* The MRI OPT pseudo-op. */
4934 const struct opt_action *o;
4939 if (*input_line_pointer == '-')
4941 ++input_line_pointer;
4944 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4946 input_line_pointer += 2;
4950 s = input_line_pointer;
4951 c = get_symbol_end ();
4953 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4955 if (strcasecmp (s, o->name) == 0)
4959 /* Restore input_line_pointer now in case the option
4961 *input_line_pointer = c;
4962 (*o->pfn) (o->arg, t);
4964 else if (o->pvar != NULL)
4966 if (! t && o->arg == o->notarg)
4967 as_bad ("option `%s' may not be negated", s);
4968 *input_line_pointer = c;
4969 *o->pvar = t ? o->arg : o->notarg;
4972 *input_line_pointer = c;
4978 as_bad ("option `%s' not recognized", s);
4979 *input_line_pointer = c;
4982 while (*input_line_pointer++ == ',');
4984 /* Move back to terminating character. */
4985 --input_line_pointer;
4986 demand_empty_rest_of_line ();
4989 /* Skip ahead to a comma. This is used for OPT options which we do
4990 not suppor tand which take arguments. */
4993 skip_to_comma (arg, on)
4997 while (*input_line_pointer != ','
4998 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4999 ++input_line_pointer;
5002 /* Handle the OPT NEST=depth option. */
5009 if (*input_line_pointer != '=')
5011 as_bad ("bad format of OPT NEST=depth");
5015 ++input_line_pointer;
5016 max_macro_nest = get_absolute_expression ();
5019 /* Handle the OPT P=chip option. */
5026 if (*input_line_pointer != '=')
5028 /* This is just OPT P, which we do not support. */
5032 ++input_line_pointer;
5036 /* Handle the OPT S option. */
5046 /* Handle the OPT T option. */
5049 opt_list_symbols (arg, on)
5054 listing |= LISTING_SYMBOLS;
5056 listing &=~ LISTING_SYMBOLS;
5059 /* Handle the MRI REG pseudo-op. */
5072 if (line_label == NULL)
5074 as_bad ("missing label");
5075 ignore_rest_of_line ();
5080 stop = mri_comment_field (&stopc);
5084 s = input_line_pointer;
5085 while (isalnum ((unsigned char) *input_line_pointer)
5086 #ifdef REGISTER_PREFIX
5087 || *input_line_pointer == REGISTER_PREFIX
5089 || *input_line_pointer == '/'
5090 || *input_line_pointer == '-')
5091 ++input_line_pointer;
5092 c = *input_line_pointer;
5093 *input_line_pointer = '\0';
5095 if (m68k_ip_op (s, &rop) != 0)
5097 if (rop.error == NULL)
5098 as_bad ("bad register list");
5100 as_bad ("bad register list: %s", rop.error);
5101 *input_line_pointer = c;
5102 ignore_rest_of_line ();
5106 *input_line_pointer = c;
5108 if (rop.mode == REGLST)
5110 else if (rop.mode == DREG)
5111 mask = 1 << (rop.reg - DATA0);
5112 else if (rop.mode == AREG)
5113 mask = 1 << (rop.reg - ADDR0 + 8);
5114 else if (rop.mode == FPREG)
5115 mask = 1 << (rop.reg - FP0 + 16);
5116 else if (rop.mode == CONTROL
5119 else if (rop.mode == CONTROL
5122 else if (rop.mode == CONTROL
5127 as_bad ("bad register list");
5128 ignore_rest_of_line ();
5132 S_SET_SEGMENT (line_label, absolute_section);
5133 S_SET_VALUE (line_label, mask);
5134 line_label->sy_frag = &zero_address_frag;
5137 mri_comment_end (stop, stopc);
5139 demand_empty_rest_of_line ();
5142 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5146 struct save_opts *next;
5148 int symbols_case_sensitive;
5156 /* FIXME: We don't save OPT S. */
5159 /* This variable holds the stack of saved options. */
5161 static struct save_opts *save_stack;
5163 /* The MRI SAVE pseudo-op. */
5169 struct save_opts *s;
5171 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5172 s->abspcadd = m68k_abspcadd;
5173 s->symbols_case_sensitive = symbols_case_sensitive;
5174 s->keep_locals = flag_keep_locals;
5175 s->short_refs = flag_short_refs;
5176 s->architecture = current_architecture;
5177 s->quick = m68k_quick;
5178 s->rel32 = m68k_rel32;
5179 s->listing = listing;
5180 s->no_warnings = flag_no_warnings;
5182 s->next = save_stack;
5185 demand_empty_rest_of_line ();
5188 /* The MRI RESTORE pseudo-op. */
5194 struct save_opts *s;
5196 if (save_stack == NULL)
5198 as_bad ("restore without save");
5199 ignore_rest_of_line ();
5204 save_stack = s->next;
5206 m68k_abspcadd = s->abspcadd;
5207 symbols_case_sensitive = s->symbols_case_sensitive;
5208 flag_keep_locals = s->keep_locals;
5209 flag_short_refs = s->short_refs;
5210 current_architecture = s->architecture;
5211 m68k_quick = s->quick;
5212 m68k_rel32 = s->rel32;
5213 listing = s->listing;
5214 flag_no_warnings = s->no_warnings;
5218 demand_empty_rest_of_line ();
5221 /* Types of MRI structured control directives. */
5223 enum mri_control_type
5231 /* This structure is used to stack the MRI structured control
5234 struct mri_control_info
5236 /* The directive within which this one is enclosed. */
5237 struct mri_control_info *outer;
5239 /* The type of directive. */
5240 enum mri_control_type type;
5242 /* Whether an ELSE has been in an IF. */
5245 /* The add or sub statement at the end of a FOR. */
5248 /* The label of the top of a FOR or REPEAT loop. */
5251 /* The label to jump to for the next iteration, or the else
5252 expression of a conditional. */
5255 /* The label to jump to to break out of the loop, or the label past
5256 the end of a conditional. */
5260 /* The stack of MRI structured control directives. */
5262 static struct mri_control_info *mri_control_stack;
5264 /* The current MRI structured control directive index number, used to
5265 generate label names. */
5267 static int mri_control_index;
5269 /* Some function prototypes. */
5271 static char *mri_control_label PARAMS ((void));
5272 static struct mri_control_info *push_mri_control
5273 PARAMS ((enum mri_control_type));
5274 static void pop_mri_control PARAMS ((void));
5275 static int parse_mri_condition PARAMS ((int *));
5276 static int parse_mri_control_operand
5277 PARAMS ((int *, char **, char **, char **, char **));
5278 static int swap_mri_condition PARAMS ((int));
5279 static int reverse_mri_condition PARAMS ((int));
5280 static void build_mri_control_operand
5281 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5282 const char *, int));
5283 static void parse_mri_control_expression
5284 PARAMS ((char *, int, const char *, const char *, int));
5286 /* Generate a new MRI label structured control directive label name. */
5289 mri_control_label ()
5293 n = (char *) xmalloc (20);
5294 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5295 ++mri_control_index;
5299 /* Create a new MRI structured control directive. */
5301 static struct mri_control_info *
5302 push_mri_control (type)
5303 enum mri_control_type type;
5305 struct mri_control_info *n;
5307 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5311 if (type == mri_if || type == mri_while)
5314 n->top = mri_control_label ();
5315 n->next = mri_control_label ();
5316 n->bottom = mri_control_label ();
5318 n->outer = mri_control_stack;
5319 mri_control_stack = n;
5324 /* Pop off the stack of MRI structured control directives. */
5329 struct mri_control_info *n;
5331 n = mri_control_stack;
5332 mri_control_stack = n->outer;
5340 /* Recognize a condition code in an MRI structured control expression. */
5343 parse_mri_condition (pcc)
5348 know (*input_line_pointer == '<');
5350 ++input_line_pointer;
5351 c1 = *input_line_pointer++;
5352 c2 = *input_line_pointer++;
5354 if (*input_line_pointer != '>')
5356 as_bad ("syntax error in structured control directive");
5360 ++input_line_pointer;
5368 *pcc = (c1 << 8) | c2;
5373 /* Parse a single operand in an MRI structured control expression. */
5376 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5393 if (*input_line_pointer == '<')
5395 /* It's just a condition code. */
5396 return parse_mri_condition (pcc);
5399 /* Look ahead for the condition code. */
5400 for (s = input_line_pointer; *s != '\0'; ++s)
5402 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5407 as_bad ("missing condition code in structured control directive");
5411 *leftstart = input_line_pointer;
5413 if (*leftstop > *leftstart
5414 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5417 input_line_pointer = s;
5418 if (! parse_mri_condition (pcc))
5421 /* Look ahead for AND or OR or end of line. */
5422 for (s = input_line_pointer; *s != '\0'; ++s)
5424 if ((strncasecmp (s, "AND", 3) == 0
5425 && (s[3] == '.' || ! is_part_of_name (s[3])))
5426 || (strncasecmp (s, "OR", 2) == 0
5427 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5431 *rightstart = input_line_pointer;
5433 if (*rightstop > *rightstart
5434 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5437 input_line_pointer = s;
5442 #define MCC(b1, b2) (((b1) << 8) | (b2))
5444 /* Swap the sense of a condition. This changes the condition so that
5445 it generates the same result when the operands are swapped. */
5448 swap_mri_condition (cc)
5453 case MCC ('h', 'i'): return MCC ('c', 's');
5454 case MCC ('l', 's'): return MCC ('c', 'c');
5455 case MCC ('c', 'c'): return MCC ('l', 's');
5456 case MCC ('c', 's'): return MCC ('h', 'i');
5457 case MCC ('p', 'l'): return MCC ('m', 'i');
5458 case MCC ('m', 'i'): return MCC ('p', 'l');
5459 case MCC ('g', 'e'): return MCC ('l', 'e');
5460 case MCC ('l', 't'): return MCC ('g', 't');
5461 case MCC ('g', 't'): return MCC ('l', 't');
5462 case MCC ('l', 'e'): return MCC ('g', 'e');
5467 /* Reverse the sense of a condition. */
5470 reverse_mri_condition (cc)
5475 case MCC ('h', 'i'): return MCC ('l', 's');
5476 case MCC ('l', 's'): return MCC ('h', 'i');
5477 case MCC ('c', 'c'): return MCC ('c', 's');
5478 case MCC ('c', 's'): return MCC ('c', 'c');
5479 case MCC ('n', 'e'): return MCC ('e', 'q');
5480 case MCC ('e', 'q'): return MCC ('n', 'e');
5481 case MCC ('v', 'c'): return MCC ('v', 's');
5482 case MCC ('v', 's'): return MCC ('v', 'c');
5483 case MCC ('p', 'l'): return MCC ('m', 'i');
5484 case MCC ('m', 'i'): return MCC ('p', 'l');
5485 case MCC ('g', 'e'): return MCC ('l', 't');
5486 case MCC ('l', 't'): return MCC ('g', 'e');
5487 case MCC ('g', 't'): return MCC ('l', 'e');
5488 case MCC ('l', 'e'): return MCC ('g', 't');
5493 /* Build an MRI structured control expression. This generates test
5494 and branch instructions. It goes to TRUELAB if the condition is
5495 true, and to FALSELAB if the condition is false. Exactly one of
5496 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5497 is the size qualifier for the expression. EXTENT is the size to
5498 use for the branch. */
5501 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5502 rightstop, truelab, falselab, extent)
5509 const char *truelab;
5510 const char *falselab;
5516 if (leftstart != NULL)
5518 struct m68k_op leftop, rightop;
5521 /* Swap the compare operands, if necessary, to produce a legal
5522 m68k compare instruction. Comparing a register operand with
5523 a non-register operand requires the register to be on the
5524 right (cmp, cmpa). Comparing an immediate value with
5525 anything requires the immediate value to be on the left
5530 (void) m68k_ip_op (leftstart, &leftop);
5535 (void) m68k_ip_op (rightstart, &rightop);
5538 if (rightop.mode == IMMED
5539 || ((leftop.mode == DREG || leftop.mode == AREG)
5540 && (rightop.mode != DREG && rightop.mode != AREG)))
5544 cc = swap_mri_condition (cc);
5546 leftstart = rightstart;
5549 leftstop = rightstop;
5554 if (truelab == NULL)
5556 cc = reverse_mri_condition (cc);
5560 if (leftstart != NULL)
5562 buf = (char *) xmalloc (20
5563 + (leftstop - leftstart)
5564 + (rightstop - rightstart));
5572 memcpy (s, leftstart, leftstop - leftstart);
5573 s += leftstop - leftstart;
5575 memcpy (s, rightstart, rightstop - rightstart);
5576 s += rightstop - rightstart;
5582 buf = (char *) xmalloc (20 + strlen (truelab));
5590 strcpy (s, truelab);
5595 /* Parse an MRI structured control expression. This generates test
5596 and branch instructions. STOP is where the expression ends. It
5597 goes to TRUELAB if the condition is true, and to FALSELAB if the
5598 condition is false. Exactly one of TRUELAB and FALSELAB will be
5599 NULL, meaning to fall through. QUAL is the size qualifier for the
5600 expression. EXTENT is the size to use for the branch. */
5603 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5606 const char *truelab;
5607 const char *falselab;
5620 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5621 &rightstart, &rightstop))
5627 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5631 if (falselab != NULL)
5634 flab = mri_control_label ();
5636 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5637 rightstop, (const char *) NULL, flab, extent);
5639 input_line_pointer += 3;
5640 if (*input_line_pointer != '.'
5641 || input_line_pointer[1] == '\0')
5645 qual = input_line_pointer[1];
5646 input_line_pointer += 2;
5649 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5650 &rightstart, &rightstop))
5656 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5657 rightstop, truelab, falselab, extent);
5659 if (falselab == NULL)
5662 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5666 if (truelab != NULL)
5669 tlab = mri_control_label ();
5671 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5672 rightstop, tlab, (const char *) NULL, extent);
5674 input_line_pointer += 2;
5675 if (*input_line_pointer != '.'
5676 || input_line_pointer[1] == '\0')
5680 qual = input_line_pointer[1];
5681 input_line_pointer += 2;
5684 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5685 &rightstart, &rightstop))
5691 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5692 rightstop, truelab, falselab, extent);
5694 if (truelab == NULL)
5699 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5700 rightstop, truelab, falselab, extent);
5704 if (input_line_pointer != stop)
5705 as_bad ("syntax error in structured control directive");
5708 /* Handle the MRI IF pseudo-op. This may be a structured control
5709 directive, or it may be a regular assembler conditional, depending
5718 struct mri_control_info *n;
5720 /* A structured control directive must end with THEN with an
5721 optional qualifier. */
5722 s = input_line_pointer;
5723 while (! is_end_of_line[(unsigned char) *s]
5724 && (! flag_mri || *s != '*'))
5727 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5730 if (s - input_line_pointer > 1
5734 if (s - input_line_pointer < 3
5735 || strncasecmp (s - 3, "THEN", 4) != 0)
5739 as_bad ("missing then");
5740 ignore_rest_of_line ();
5744 /* It's a conditional. */
5749 /* Since this might be a conditional if, this pseudo-op will be
5750 called even if we are supported to be ignoring input. Double
5751 check now. Clobber *input_line_pointer so that ignore_input
5752 thinks that this is not a special pseudo-op. */
5753 c = *input_line_pointer;
5754 *input_line_pointer = 0;
5755 if (ignore_input ())
5757 *input_line_pointer = c;
5758 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5759 ++input_line_pointer;
5760 demand_empty_rest_of_line ();
5763 *input_line_pointer = c;
5765 n = push_mri_control (mri_if);
5767 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5768 n->next, s[1] == '.' ? s[2] : '\0');
5771 input_line_pointer = s + 3;
5773 input_line_pointer = s + 1;
5777 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5778 ++input_line_pointer;
5781 demand_empty_rest_of_line ();
5784 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5785 structured IF, associate the ELSE with the IF. Otherwise, assume
5786 it is a conditional else. */
5797 && (mri_control_stack == NULL
5798 || mri_control_stack->type != mri_if
5799 || mri_control_stack->else_seen))
5805 c = *input_line_pointer;
5806 *input_line_pointer = 0;
5807 if (ignore_input ())
5809 *input_line_pointer = c;
5810 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5811 ++input_line_pointer;
5812 demand_empty_rest_of_line ();
5815 *input_line_pointer = c;
5817 if (mri_control_stack == NULL
5818 || mri_control_stack->type != mri_if
5819 || mri_control_stack->else_seen)
5821 as_bad ("else without matching if");
5822 ignore_rest_of_line ();
5826 mri_control_stack->else_seen = 1;
5828 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5831 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5835 colon (mri_control_stack->next);
5839 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5840 ++input_line_pointer;
5843 demand_empty_rest_of_line ();
5846 /* Handle the MRI ENDI pseudo-op. */
5852 if (mri_control_stack == NULL
5853 || mri_control_stack->type != mri_if)
5855 as_bad ("endi without matching if");
5856 ignore_rest_of_line ();
5860 /* ignore_input will not return true for ENDI, so we don't need to
5861 worry about checking it again here. */
5863 if (! mri_control_stack->else_seen)
5864 colon (mri_control_stack->next);
5865 colon (mri_control_stack->bottom);
5871 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5872 ++input_line_pointer;
5875 demand_empty_rest_of_line ();
5878 /* Handle the MRI BREAK pseudo-op. */
5881 s_mri_break (extent)
5884 struct mri_control_info *n;
5888 n = mri_control_stack;
5890 && n->type != mri_for
5891 && n->type != mri_repeat
5892 && n->type != mri_while)
5896 as_bad ("break outside of structured loop");
5897 ignore_rest_of_line ();
5901 buf = (char *) xmalloc (20 + strlen (n->bottom));
5904 sprintf (buf, "bra%s %s", ex, n->bottom);
5910 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5911 ++input_line_pointer;
5914 demand_empty_rest_of_line ();
5917 /* Handle the MRI NEXT pseudo-op. */
5923 struct mri_control_info *n;
5927 n = mri_control_stack;
5929 && n->type != mri_for
5930 && n->type != mri_repeat
5931 && n->type != mri_while)
5935 as_bad ("next outside of structured loop");
5936 ignore_rest_of_line ();
5940 buf = (char *) xmalloc (20 + strlen (n->next));
5943 sprintf (buf, "bra%s %s", ex, n->next);
5949 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5950 ++input_line_pointer;
5953 demand_empty_rest_of_line ();
5956 /* Handle the MRI FOR pseudo-op. */
5962 const char *varstart, *varstop;
5963 const char *initstart, *initstop;
5964 const char *endstart, *endstop;
5965 const char *bystart, *bystop;
5969 struct mri_control_info *n;
5975 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5979 varstart = input_line_pointer;
5981 /* Look for the '='. */
5982 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5983 && *input_line_pointer != '=')
5984 ++input_line_pointer;
5985 if (*input_line_pointer != '=')
5987 as_bad ("missing =");
5988 ignore_rest_of_line ();
5992 varstop = input_line_pointer;
5993 if (varstop > varstart
5994 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5997 ++input_line_pointer;
5999 initstart = input_line_pointer;
6001 /* Look for TO or DOWNTO. */
6004 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6006 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6007 && ! is_part_of_name (input_line_pointer[2]))
6009 initstop = input_line_pointer;
6010 input_line_pointer += 2;
6013 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6014 && ! is_part_of_name (input_line_pointer[6]))
6016 initstop = input_line_pointer;
6018 input_line_pointer += 6;
6021 ++input_line_pointer;
6023 if (initstop == NULL)
6025 as_bad ("missing to or downto");
6026 ignore_rest_of_line ();
6029 if (initstop > initstart
6030 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6034 endstart = input_line_pointer;
6036 /* Look for BY or DO. */
6039 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6041 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6042 && ! is_part_of_name (input_line_pointer[2]))
6044 endstop = input_line_pointer;
6046 input_line_pointer += 2;
6049 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6050 && (input_line_pointer[2] == '.'
6051 || ! is_part_of_name (input_line_pointer[2])))
6053 endstop = input_line_pointer;
6054 input_line_pointer += 2;
6057 ++input_line_pointer;
6059 if (endstop == NULL)
6061 as_bad ("missing do");
6062 ignore_rest_of_line ();
6065 if (endstop > endstart
6066 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6072 bystop = bystart + 2;
6077 bystart = input_line_pointer;
6081 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6083 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6084 && (input_line_pointer[2] == '.'
6085 || ! is_part_of_name (input_line_pointer[2])))
6087 bystop = input_line_pointer;
6088 input_line_pointer += 2;
6091 ++input_line_pointer;
6095 as_bad ("missing do");
6096 ignore_rest_of_line ();
6099 if (bystop > bystart
6100 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6104 if (*input_line_pointer != '.')
6108 extent = input_line_pointer[1];
6109 input_line_pointer += 2;
6112 /* We have fully parsed the FOR operands. Now build the loop. */
6114 n = push_mri_control (mri_for);
6116 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6127 memcpy (s, initstart, initstop - initstart);
6128 s += initstop - initstart;
6130 memcpy (s, varstart, varstop - varstart);
6131 s += varstop - varstart;
6145 memcpy (s, endstart, endstop - endstart);
6146 s += endstop - endstart;
6148 memcpy (s, varstart, varstop - varstart);
6149 s += varstop - varstart;
6157 sprintf (buf, "blt%s %s", ex, n->bottom);
6159 sprintf (buf, "bgt%s %s", ex, n->bottom);
6162 /* Put together the add or sub instruction used by ENDF. */
6172 memcpy (s, bystart, bystop - bystart);
6173 s += bystop - bystart;
6175 memcpy (s, varstart, varstop - varstart);
6176 s += varstop - varstart;
6182 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6183 ++input_line_pointer;
6186 demand_empty_rest_of_line ();
6189 /* Handle the MRI ENDF pseudo-op. */
6195 if (mri_control_stack == NULL
6196 || mri_control_stack->type != mri_for)
6198 as_bad ("endf without for");
6199 ignore_rest_of_line ();
6203 colon (mri_control_stack->next);
6205 md_assemble (mri_control_stack->incr);
6207 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6208 md_assemble (mri_control_stack->incr);
6210 free (mri_control_stack->incr);
6212 colon (mri_control_stack->bottom);
6218 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6219 ++input_line_pointer;
6222 demand_empty_rest_of_line ();
6225 /* Handle the MRI REPEAT pseudo-op. */
6228 s_mri_repeat (ignore)
6231 struct mri_control_info *n;
6233 n = push_mri_control (mri_repeat);
6237 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6238 ++input_line_pointer;
6240 demand_empty_rest_of_line ();
6243 /* Handle the MRI UNTIL pseudo-op. */
6251 if (mri_control_stack == NULL
6252 || mri_control_stack->type != mri_repeat)
6254 as_bad ("until without repeat");
6255 ignore_rest_of_line ();
6259 colon (mri_control_stack->next);
6261 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6264 parse_mri_control_expression (s, qual, (const char *) NULL,
6265 mri_control_stack->top, '\0');
6267 colon (mri_control_stack->bottom);
6269 input_line_pointer = s;
6275 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6276 ++input_line_pointer;
6279 demand_empty_rest_of_line ();
6282 /* Handle the MRI WHILE pseudo-op. */
6290 struct mri_control_info *n;
6292 s = input_line_pointer;
6293 while (! is_end_of_line[(unsigned char) *s]
6294 && (! flag_mri || *s != '*'))
6297 while (*s == ' ' || *s == '\t')
6299 if (s - input_line_pointer > 1
6302 if (s - input_line_pointer < 2
6303 || strncasecmp (s - 1, "DO", 2) != 0)
6305 as_bad ("missing do");
6306 ignore_rest_of_line ();
6310 n = push_mri_control (mri_while);
6314 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6315 s[1] == '.' ? s[2] : '\0');
6317 input_line_pointer = s + 1;
6318 if (*input_line_pointer == '.')
6319 input_line_pointer += 2;
6323 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6324 ++input_line_pointer;
6327 demand_empty_rest_of_line ();
6330 /* Handle the MRI ENDW pseudo-op. */
6338 if (mri_control_stack == NULL
6339 || mri_control_stack->type != mri_while)
6341 as_bad ("endw without while");
6342 ignore_rest_of_line ();
6346 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6347 sprintf (buf, "bra %s", mri_control_stack->next);
6351 colon (mri_control_stack->bottom);
6357 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6358 ++input_line_pointer;
6361 demand_empty_rest_of_line ();
6366 * Invocation line includes a switch not recognized by the base assembler.
6367 * See if it's a processor-specific option. These are:
6369 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6370 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6371 * Select the architecture. Instructions or features not
6372 * supported by the selected architecture cause fatal
6373 * errors. More than one may be specified. The default is
6374 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6375 * for -m68000, and -m68882 is a synonym for -m68881.
6376 * -[A]m[c]no-68851, -[A]m[c]no-68881
6377 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6378 * so don't use or document it, but that's the way the parsing
6381 * -pic Indicates PIC.
6382 * -k Indicates PIC. (Sun 3 only.)
6385 * Permit `|' to be used in expressions.
6390 CONST char *md_shortopts = "lSA:m:kQ:V";
6392 CONST char *md_shortopts = "lSA:m:k";
6395 struct option md_longopts[] = {
6396 #define OPTION_PIC (OPTION_MD_BASE)
6397 {"pic", no_argument, NULL, OPTION_PIC},
6398 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6399 {"register-prefix-optional", no_argument, NULL,
6400 OPTION_REGISTER_PREFIX_OPTIONAL},
6401 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6402 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6403 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6404 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6405 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6406 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6407 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6408 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6409 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6410 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6411 {NULL, no_argument, NULL, 0}
6413 size_t md_longopts_size = sizeof(md_longopts);
6416 md_parse_option (c, arg)
6422 case 'l': /* -l means keep external to 2 bit offset
6423 rather than 16 bit one */
6424 flag_short_refs = 1;
6427 case 'S': /* -S means that jbsr's always turn into
6429 flag_long_jumps = 1;
6435 /* intentional fall-through */
6438 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6442 const char *oarg = arg;
6448 if (arg[0] == 'c' && arg[1] == '6')
6451 for (i = 0; i < n_archs; i++)
6452 if (!strcmp (arg, archs[i].name))
6457 as_bad ("unrecognized option `%s'", oarg);
6460 arch = archs[i].arch;
6463 else if (arch == m68851)
6472 if (arg[0] == 'c' && arg[1] == '6')
6475 for (i = 0; i < n_archs; i++)
6476 if (!strcmp (arg, archs[i].name))
6478 unsigned long arch = archs[i].arch;
6479 if (cpu_of_arch (arch))
6480 /* It's a cpu spec. */
6482 current_architecture &= ~m68000up;
6483 current_architecture |= arch;
6485 else if (arch == m68881)
6487 current_architecture |= m68881;
6490 else if (arch == m68851)
6492 current_architecture |= m68851;
6502 as_bad ("unrecognized architecture specification `%s'", arg);
6511 break; /* -pic, Position Independent Code */
6513 case OPTION_REGISTER_PREFIX_OPTIONAL:
6514 flag_reg_prefix_optional = 1;
6515 reg_prefix_optional_seen = 1;
6518 /* -V: SVR4 argument to print version ID. */
6520 print_version_id ();
6523 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6524 should be emitted or not. FIXME: Not implemented. */
6528 case OPTION_BITWISE_OR:
6533 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6535 for (s = m68k_comment_chars; *s != '\0'; s++)
6539 m68k_comment_chars = n;
6543 case OPTION_BASE_SIZE_DEFAULT_16:
6544 m68k_index_width_default = SIZE_WORD;
6547 case OPTION_BASE_SIZE_DEFAULT_32:
6548 m68k_index_width_default = SIZE_LONG;
6551 case OPTION_DISP_SIZE_DEFAULT_16:
6553 m68k_rel32_from_cmdline = 1;
6556 case OPTION_DISP_SIZE_DEFAULT_32:
6558 m68k_rel32_from_cmdline = 1;
6569 md_show_usage (stream)
6574 -l use 1 word for refs to undefined symbols [default 2]\n\
6575 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6576 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6577 | -mcpu32 | -m5200\n\
6578 specify variant of 680X0 architecture [default 68020]\n\
6579 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6580 target has/lacks floating-point coprocessor\n\
6581 [default yes for 68020, 68030, and cpu32]\n");
6583 -m68851 | -mno-68851\n\
6584 target has/lacks memory-management unit coprocessor\n\
6585 [default yes for 68020 and up]\n\
6586 -pic, -k generate position independent code\n\
6587 -S turn jbsr into jsr\n\
6588 --register-prefix-optional\n\
6589 recognize register names without prefix character\n\
6590 --bitwise-or do not treat `|' as a comment character\n");
6592 --base-size-default-16 base reg without size is 16 bits\n\
6593 --base-size-default-32 base reg without size is 32 bits (default)\n\
6594 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6595 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
6600 /* TEST2: Test md_assemble() */
6601 /* Warning, this routine probably doesn't work anymore */
6605 struct m68k_it the_ins;
6613 if (!gets (buf) || !*buf)
6615 if (buf[0] == '|' || buf[1] == '.')
6617 for (cp = buf; *cp; cp++)
6622 memset (&the_ins, '\0', sizeof (the_ins));
6623 m68k_ip (&the_ins, buf);
6626 printf ("Error %s in %s\n", the_ins.error, buf);
6630 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6631 for (n = 0; n < the_ins.numo; n++)
6632 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6634 print_the_insn (&the_ins.opcode[0], stdout);
6635 (void) putchar ('\n');
6637 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6639 if (the_ins.operands[n].error)
6641 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6644 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6645 if (the_ins.operands[n].b_const)
6646 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6647 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6648 if (the_ins.operands[n].b_iadd)
6649 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6650 (void) putchar ('\n');
6662 while (*str && *str != ' ')
6664 if (str[-1] == ':' || str[1] == '=')
6671 /* Possible states for relaxation:
6673 0 0 branch offset byte (bra, etc)
6677 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6681 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6688 /* We have no need to default values of symbols. */
6692 md_undefined_symbol (name)
6698 /* Round up a section size to the appropriate boundary. */
6700 md_section_align (segment, size)
6704 return size; /* Byte alignment is fine */
6707 /* Exactly what point is a PC-relative offset relative TO?
6708 On the 68k, it is relative to the address of the first extension
6709 word. The difference between the addresses of the offset and the
6710 first extension word is stored in fx_pcrel_adjust. */
6712 md_pcrel_from (fixP)
6717 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6719 adjust = fixP->fx_pcrel_adjust;
6722 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6725 #ifndef BFD_ASSEMBLER
6728 tc_coff_symbol_emit_hook (ignore)
6734 tc_coff_sizemachdep (frag)
6737 switch (frag->fr_subtype & 0x3)
6752 /* end of tc-m68k.c */