1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
47 const char *m68k_comment_chars = "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
59 const char line_separator_chars[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 const int md_reloc_size = 8; /* Size of relocation record. */
75 /* Are we trying to generate PIC code? If so, absolute references
76 ought to be made into linkage table references or pc-relative
77 references. Not implemented. For ELF there are other means
78 to denote pic relocations. */
81 static int flag_short_refs; /* -l option. */
82 static int flag_long_jumps; /* -S option. */
83 static int flag_keep_pcrel; /* --pcrel option. */
85 #ifdef REGISTER_PREFIX_OPTIONAL
86 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
88 int flag_reg_prefix_optional;
91 /* Whether --register-prefix-optional was used on the command line. */
92 static int reg_prefix_optional_seen;
94 /* The floating point coprocessor to use by default. */
95 static enum m68k_register m68k_float_copnum = COP1;
97 /* If this is non-zero, then references to number(%pc) will be taken
98 to refer to number, rather than to %pc + number. */
99 static int m68k_abspcadd;
101 /* If this is non-zero, then the quick forms of the move, add, and sub
102 instructions are used when possible. */
103 static int m68k_quick = 1;
105 /* If this is non-zero, then if the size is not specified for a base
106 or outer displacement, the assembler assumes that the size should
108 static int m68k_rel32 = 1;
110 /* This is non-zero if m68k_rel32 was set from the command line. */
111 static int m68k_rel32_from_cmdline;
113 /* The default width to use for an index register when using a base
115 static enum m68k_size m68k_index_width_default = SIZE_LONG;
117 /* We want to warn if any text labels are misaligned. In order to get
118 the right line number, we need to record the line number for each
122 struct label_line *next;
129 /* The list of labels. */
131 static struct label_line *labels;
133 /* The current label. */
135 static struct label_line *current_label;
137 /* Pointer to list holding the opcodes sorted by name. */
138 static struct m68k_opcode const ** m68k_sorted_opcodes;
140 /* Its an arbitrary name: This means I don't approve of it.
142 static struct obstack robyn;
146 const char *m_operands;
147 unsigned long m_opcode;
151 struct m68k_incant *m_next;
154 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
155 #define gettwo(x) (((x)->m_opcode)&0xffff)
157 static const enum m68k_register m68000_control_regs[] = { 0 };
158 static const enum m68k_register m68010_control_regs[] = {
162 static const enum m68k_register m68020_control_regs[] = {
163 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
166 static const enum m68k_register m68040_control_regs[] = {
167 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
168 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
171 static const enum m68k_register m68060_control_regs[] = {
172 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
173 USP, VBR, URP, SRP, PCR,
176 static const enum m68k_register mcf_control_regs[] = {
177 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
178 RAMBAR0, RAMBAR1, MBAR,
181 static const enum m68k_register mcf5249_control_regs[] = {
182 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR1, MBAR, MBAR2,
185 static const enum m68k_register mcf528x_control_regs[] = {
186 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
189 static const enum m68k_register mcfv4e_control_regs[] = {
190 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
191 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
192 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
193 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
196 #define cpu32_control_regs m68010_control_regs
198 static const enum m68k_register *control_regs;
200 /* Internal form of a 68020 instruction. */
204 const char *args; /* List of opcode info. */
207 int numo; /* Number of shorts in opcode. */
210 struct m68k_op operands[6];
212 int nexp; /* Number of exprs in use. */
213 struct m68k_exp exprs[4];
215 int nfrag; /* Number of frags we have to produce. */
218 int fragoff; /* Where in the current opcode the frag ends. */
225 int nrel; /* Num of reloc strucs in use. */
232 /* In a pc relative address the difference between the address
233 of the offset and the address that the offset is relative
234 to. This depends on the addressing mode. Basically this
235 is the value to put in the offset field to address the
236 first byte of the offset, without regarding the special
237 significance of some values (in the branch instruction, for
241 /* Whether this expression needs special pic relocation, and if
243 enum pic_relocation pic_reloc;
246 reloc[5]; /* Five is enough??? */
249 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
250 #define float_of_arch(x) ((x) & mfloat)
251 #define mmu_of_arch(x) ((x) & mmmu)
252 #define arch_coldfire_p(x) ((x) & mcfisa_a)
253 #define arch_coldfire_fpu(x) ((x) & cfloat)
255 /* Macros for determining if cpu supports a specific addressing mode. */
256 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
258 static struct m68k_it the_ins; /* The instruction being assembled. */
260 #define op(ex) ((ex)->exp.X_op)
261 #define adds(ex) ((ex)->exp.X_add_symbol)
262 #define subs(ex) ((ex)->exp.X_op_symbol)
263 #define offs(ex) ((ex)->exp.X_add_number)
265 /* Macros for adding things to the m68k_it struct. */
266 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
268 /* Like addword, but goes BEFORE general operands. */
271 insop (int w, const struct m68k_incant *opcode)
274 for (z = the_ins.numo; z > opcode->m_codenum; --z)
275 the_ins.opcode[z] = the_ins.opcode[z - 1];
276 for (z = 0; z < the_ins.nrel; z++)
277 the_ins.reloc[z].n += 2;
278 for (z = 0; z < the_ins.nfrag; z++)
279 the_ins.fragb[z].fragoff++;
280 the_ins.opcode[opcode->m_codenum] = w;
284 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
287 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
289 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
290 ? the_ins.numo * 2 - 1
292 ? the_ins.numo * 2 + 1
293 : the_ins.numo * 2));
294 the_ins.reloc[the_ins.nrel].exp = exp->exp;
295 the_ins.reloc[the_ins.nrel].wid = width;
296 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
298 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
300 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
303 /* Cause an extra frag to be generated here, inserting up to 10 bytes
304 (that value is chosen in the frag_var call in md_assemble). TYPE
305 is the subtype of the frag to be generated; its primary type is
306 rs_machine_dependent.
308 The TYPE parameter is also used by md_convert_frag_1 and
309 md_estimate_size_before_relax. The appropriate type of fixup will
310 be emitted by md_convert_frag_1.
312 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
314 add_frag (symbolS *add, offsetT off, int type)
316 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
317 the_ins.fragb[the_ins.nfrag].fadd = add;
318 the_ins.fragb[the_ins.nfrag].foff = off;
319 the_ins.fragb[the_ins.nfrag++].fragty = type;
323 (op (ex) != O_constant && op (ex) != O_big)
325 static char *crack_operand (char *str, struct m68k_op *opP);
326 static int get_num (struct m68k_exp *exp, int ok);
327 static int reverse_16_bits (int in);
328 static int reverse_8_bits (int in);
329 static void install_gen_operand (int mode, int val);
330 static void install_operand (int mode, int val);
331 static void s_bss (int);
332 static void s_data1 (int);
333 static void s_data2 (int);
334 static void s_even (int);
335 static void s_proc (int);
336 static void s_chip (int);
337 static void s_fopt (int);
338 static void s_opt (int);
339 static void s_reg (int);
340 static void s_restore (int);
341 static void s_save (int);
342 static void s_mri_if (int);
343 static void s_mri_else (int);
344 static void s_mri_endi (int);
345 static void s_mri_break (int);
346 static void s_mri_next (int);
347 static void s_mri_for (int);
348 static void s_mri_endf (int);
349 static void s_mri_repeat (int);
350 static void s_mri_until (int);
351 static void s_mri_while (int);
352 static void s_mri_endw (int);
354 static int current_architecture;
355 static int current_chip;
365 static const struct m68k_cpu archs[] =
367 { m68000, m68000, "68000", 0 },
368 { m68010, m68010, "68010", 0 },
369 { m68020, m68020, "68020", 0 },
370 { m68030, m68030, "68030", 0 },
371 { m68040, m68040, "68040", 0 },
372 { m68060, m68060, "68060", 0 },
373 { cpu32, cpu32, "cpu32", 0 },
374 { m68881, m68881, "68881", 0 },
375 { m68851, m68851, "68851", 0 },
376 { mcfisa_a, mcf5200, "5200", 0 },
377 { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 },
378 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 },
379 { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 },
380 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 },
381 { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 },
382 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 },
383 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 },
384 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 },
385 /* Aliases (effectively, so far as gas is concerned) for the above
387 { m68020, m68020, "68k", 1 },
388 { m68000, m68000, "68008", 1 },
389 { m68000, m68000, "68302", 1 },
390 { m68000, m68000, "68306", 1 },
391 { m68000, m68000, "68307", 1 },
392 { m68000, m68000, "68322", 1 },
393 { m68000, m68000, "68356", 1 },
394 { m68000, m68000, "68ec000", 1 },
395 { m68000, m68000, "68hc000", 1 },
396 { m68000, m68000, "68hc001", 1 },
397 { m68020, m68020, "68ec020", 1 },
398 { m68030, m68030, "68ec030", 1 },
399 { m68040, m68040, "68ec040", 1 },
400 { m68060, m68060, "68ec060", 1 },
401 { cpu32, cpu32, "68330", 1 },
402 { cpu32, cpu32, "68331", 1 },
403 { cpu32, cpu32, "68332", 1 },
404 { cpu32, cpu32, "68333", 1 },
405 { cpu32, cpu32, "68334", 1 },
406 { cpu32, cpu32, "68336", 1 },
407 { cpu32, cpu32, "68340", 1 },
408 { cpu32, cpu32, "68341", 1 },
409 { cpu32, cpu32, "68349", 1 },
410 { cpu32, cpu32, "68360", 1 },
411 { m68881, m68881, "68882", 1 },
412 { mcfisa_a, mcf5200, "5202", 1 },
413 { mcfisa_a, mcf5200, "5204", 1 },
414 { mcfisa_a, mcf5200, "5206", 1 },
415 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 },
416 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 },
417 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 },
418 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 },
419 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 },
420 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 },
421 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 },
422 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 },
423 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 },
424 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 },
425 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 },
426 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 },
427 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 },
428 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 },
429 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 },
430 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 },
431 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 },
432 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 },
433 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 },
436 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
438 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
439 architecture and we have a lot of relaxation modes. */
441 /* Macros used in the relaxation code. */
442 #define TAB(x,y) (((x) << 2) + (y))
443 #define TABTYPE(x) ((x) >> 2)
445 /* Relaxation states. */
451 /* Here are all the relaxation modes we support. First we can relax ordinary
452 branches. On 68020 and higher and on CPU32 all branch instructions take
453 three forms, so on these CPUs all branches always remain as such. When we
454 have to expand to the LONG form on a 68000, though, we substitute an
455 absolute jump instead. This is a direct replacement for unconditional
456 branches and a branch over a jump for conditional branches. However, if the
457 user requires PIC and disables this with --pcrel, we can only relax between
458 BYTE and SHORT forms, punting if that isn't enough. This gives us four
459 different relaxation modes for branches: */
461 #define BRANCHBWL 0 /* Branch byte, word, or long. */
462 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
463 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
464 #define BRANCHBW 3 /* Branch byte or word. */
466 /* We also relax coprocessor branches and DBcc's. All CPUs that support
467 coprocessor branches support them in word and long forms, so we have only
468 one relaxation mode for them. DBcc's are word only on all CPUs. We can
469 relax them to the LONG form with a branch-around sequence. This sequence
470 can use a long branch (if available) or an absolute jump (if acceptable).
471 This gives us two relaxation modes. If long branches are not available and
472 absolute jumps are not acceptable, we don't relax DBcc's. */
474 #define FBRANCH 4 /* Coprocessor branch. */
475 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
476 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
478 /* That's all for instruction relaxation. However, we also relax PC-relative
479 operands. Specifically, we have three operand relaxation modes. On the
480 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
481 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
482 two. Also PC+displacement+index operands in their simple form (with a non-
483 suppressed index without memory indirection) are supported on all CPUs, but
484 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
485 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
486 form of the PC+displacement+index operand. Finally, some absolute operands
487 can be relaxed down to 16-bit PC-relative. */
489 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
490 #define PCINDEX 8 /* PC + displacement + index. */
491 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
493 /* Note that calls to frag_var need to specify the maximum expansion
494 needed; this is currently 10 bytes for DBCC. */
497 How far Forward this mode will reach:
498 How far Backward this mode will reach:
499 How many bytes this mode will add to the size of the frag
500 Which mode to go to if the offset won't fit in this one
502 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
503 relax_typeS md_relax_table[] =
505 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
506 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
510 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
511 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
515 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
516 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
520 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
525 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
526 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
530 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
531 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
535 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
536 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
540 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
541 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
545 { 125, -130, 0, TAB (PCINDEX, SHORT) },
546 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
550 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
551 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
556 /* These are the machine dependent pseudo-ops. These are included so
557 the assembler can work on the output from the SUN C compiler, which
560 /* This table describes all the machine specific pseudo-ops the assembler
561 has to support. The fields are:
562 pseudo-op name without dot
563 function to call to execute this pseudo-op
564 Integer arg to pass to the function. */
565 const pseudo_typeS md_pseudo_table[] =
567 {"data1", s_data1, 0},
568 {"data2", s_data2, 0},
571 {"skip", s_space, 0},
573 #if defined (TE_SUN3) || defined (OBJ_ELF)
574 {"align", s_align_bytes, 0},
577 {"swbeg", s_ignore, 0},
579 {"extend", float_cons, 'x'},
580 {"ldouble", float_cons, 'x'},
582 /* The following pseudo-ops are supported for MRI compatibility. */
584 {"comline", s_space, 1},
586 {"mask2", s_ignore, 0},
589 {"restore", s_restore, 0},
593 {"if.b", s_mri_if, 'b'},
594 {"if.w", s_mri_if, 'w'},
595 {"if.l", s_mri_if, 'l'},
596 {"else", s_mri_else, 0},
597 {"else.s", s_mri_else, 's'},
598 {"else.l", s_mri_else, 'l'},
599 {"endi", s_mri_endi, 0},
600 {"break", s_mri_break, 0},
601 {"break.s", s_mri_break, 's'},
602 {"break.l", s_mri_break, 'l'},
603 {"next", s_mri_next, 0},
604 {"next.s", s_mri_next, 's'},
605 {"next.l", s_mri_next, 'l'},
606 {"for", s_mri_for, 0},
607 {"for.b", s_mri_for, 'b'},
608 {"for.w", s_mri_for, 'w'},
609 {"for.l", s_mri_for, 'l'},
610 {"endf", s_mri_endf, 0},
611 {"repeat", s_mri_repeat, 0},
612 {"until", s_mri_until, 0},
613 {"until.b", s_mri_until, 'b'},
614 {"until.w", s_mri_until, 'w'},
615 {"until.l", s_mri_until, 'l'},
616 {"while", s_mri_while, 0},
617 {"while.b", s_mri_while, 'b'},
618 {"while.w", s_mri_while, 'w'},
619 {"while.l", s_mri_while, 'l'},
620 {"endw", s_mri_endw, 0},
625 /* The mote pseudo ops are put into the opcode table, since they
626 don't start with a . they look like opcodes to gas. */
628 const pseudo_typeS mote_pseudo_table[] =
641 {"xdef", s_globl, 0},
643 {"align", s_align_bytes, 0},
645 {"align", s_align_ptwo, 0},
648 {"sect", obj_coff_section, 0},
649 {"section", obj_coff_section, 0},
654 #define issbyte(x) ((x) >= -128 && (x) <= 127)
655 #define isubyte(x) ((x) >= 0 && (x) <= 255)
656 #define issword(x) ((x) >= -32768 && (x) <= 32767)
657 #define isuword(x) ((x) >= 0 && (x) <= 65535)
659 #define isbyte(x) ((x) >= -255 && (x) <= 255)
660 #define isword(x) ((x) >= -65536 && (x) <= 65535)
661 #define islong(x) (1)
663 static char notend_table[256];
664 static char alt_notend_table[256];
666 (! (notend_table[(unsigned char) *s] \
668 && alt_notend_table[(unsigned char) s[1]])))
670 /* Return a human readable string holding the list of chips that are
671 valid for a particular architecture, suppressing aliases (unless
672 there is only one of them). */
675 find_cf_chip (int architecture)
677 static char buf[1024];
678 int i, j, n_chips, n_alias;
682 cp = buf + strlen (buf);
684 for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i)
685 if (archs[i].arch & architecture)
693 as_fatal (_("no matching ColdFire architectures found"));
698 for (i = 0, j = 0; i < n_archs && j < n_chips; ++i)
699 if (archs[i].arch & architecture)
703 if ((j == n_chips - 1 && !(n_alias > 1)) || ! n_alias)
707 strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
712 strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
718 strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
722 strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf)));
729 strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
733 strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
738 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
740 #ifdef NO_PCREL_RELOCS
743 make_pcrel_absolute (fixS *fixP, long *add_number)
745 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
747 /* Rewrite the PC relative instructions to absolute address ones.
748 these are rumored to be faster, and the apollo linker refuses
749 to deal with the PC relative relocations. */
750 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
753 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
757 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */
760 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
765 as_fatal (_("Unknown PC relative instruction"));
770 #endif /* NO_PCREL_RELOCS */
773 tc_coff_fix2rtype (fixS *fixP)
775 if (fixP->fx_tcbit && fixP->fx_size == 4)
776 return R_RELLONG_NEG;
777 #ifdef NO_PCREL_RELOCS
778 know (fixP->fx_pcrel == 0);
779 return (fixP->fx_size == 1 ? R_RELBYTE
780 : fixP->fx_size == 2 ? R_DIR16
783 return (fixP->fx_pcrel
784 ? (fixP->fx_size == 1 ? R_PCRBYTE
785 : fixP->fx_size == 2 ? R_PCRWORD
787 : (fixP->fx_size == 1 ? R_RELBYTE
788 : fixP->fx_size == 2 ? R_RELWORD
797 /* Return zero if the reference to SYMBOL from within the same segment may
800 /* On an ELF system, we can't relax an externally visible symbol,
801 because it may be overridden by a shared library. However, if
802 TARGET_OS is "elf", then we presume that we are assembling for an
803 embedded system, in which case we don't have to worry about shared
804 libraries, and we can relax any external sym. */
806 #define relaxable_symbol(symbol) \
807 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
808 || S_IS_WEAK (symbol)))
810 /* Compute the relocation code for a fixup of SIZE bytes, using pc
811 relative relocation if PCREL is non-zero. PIC says whether a special
812 pic relocation was requested. */
814 static bfd_reloc_code_real_type
815 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
823 return BFD_RELOC_8_GOT_PCREL;
825 return BFD_RELOC_16_GOT_PCREL;
827 return BFD_RELOC_32_GOT_PCREL;
835 return BFD_RELOC_8_GOTOFF;
837 return BFD_RELOC_16_GOTOFF;
839 return BFD_RELOC_32_GOTOFF;
847 return BFD_RELOC_8_PLT_PCREL;
849 return BFD_RELOC_16_PLT_PCREL;
851 return BFD_RELOC_32_PLT_PCREL;
859 return BFD_RELOC_8_PLTOFF;
861 return BFD_RELOC_16_PLTOFF;
863 return BFD_RELOC_32_PLTOFF;
873 return BFD_RELOC_8_PCREL;
875 return BFD_RELOC_16_PCREL;
877 return BFD_RELOC_32_PCREL;
897 as_bad (_("Can not do %d byte pc-relative relocation"), size);
899 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
904 as_bad (_("Can not do %d byte relocation"), size);
906 as_bad (_("Can not do %d byte pic relocation"), size);
909 return BFD_RELOC_NONE;
912 /* Here we decide which fixups can be adjusted to make them relative
913 to the beginning of the section instead of the symbol. Basically
914 we need to make sure that the dynamic relocations are done
915 correctly, so in some cases we force the original symbol to be
918 tc_m68k_fix_adjustable (fixS *fixP)
920 /* Adjust_reloc_syms doesn't know about the GOT. */
921 switch (fixP->fx_r_type)
923 case BFD_RELOC_8_GOT_PCREL:
924 case BFD_RELOC_16_GOT_PCREL:
925 case BFD_RELOC_32_GOT_PCREL:
926 case BFD_RELOC_8_GOTOFF:
927 case BFD_RELOC_16_GOTOFF:
928 case BFD_RELOC_32_GOTOFF:
929 case BFD_RELOC_8_PLT_PCREL:
930 case BFD_RELOC_16_PLT_PCREL:
931 case BFD_RELOC_32_PLT_PCREL:
932 case BFD_RELOC_8_PLTOFF:
933 case BFD_RELOC_16_PLTOFF:
934 case BFD_RELOC_32_PLTOFF:
937 case BFD_RELOC_VTABLE_INHERIT:
938 case BFD_RELOC_VTABLE_ENTRY:
948 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
950 #define relaxable_symbol(symbol) 1
957 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
960 bfd_reloc_code_real_type code;
962 /* If the tcbit is set, then this was a fixup of a negative value
963 that was never resolved. We do not have a reloc to handle this,
964 so just return. We assume that other code will have detected this
965 situation and produced a helpful error message, so we just tell the
966 user that the reloc cannot be produced. */
970 as_bad_where (fixp->fx_file, fixp->fx_line,
971 _("Unable to produce reloc against symbol '%s'"),
972 S_GET_NAME (fixp->fx_addsy));
976 if (fixp->fx_r_type != BFD_RELOC_NONE)
978 code = fixp->fx_r_type;
980 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
981 that fixup_segment converted a non-PC relative reloc into a
982 PC relative reloc. In such a case, we need to convert the
989 code = BFD_RELOC_8_PCREL;
992 code = BFD_RELOC_16_PCREL;
995 code = BFD_RELOC_32_PCREL;
997 case BFD_RELOC_8_PCREL:
998 case BFD_RELOC_16_PCREL:
999 case BFD_RELOC_32_PCREL:
1000 case BFD_RELOC_8_GOT_PCREL:
1001 case BFD_RELOC_16_GOT_PCREL:
1002 case BFD_RELOC_32_GOT_PCREL:
1003 case BFD_RELOC_8_GOTOFF:
1004 case BFD_RELOC_16_GOTOFF:
1005 case BFD_RELOC_32_GOTOFF:
1006 case BFD_RELOC_8_PLT_PCREL:
1007 case BFD_RELOC_16_PLT_PCREL:
1008 case BFD_RELOC_32_PLT_PCREL:
1009 case BFD_RELOC_8_PLTOFF:
1010 case BFD_RELOC_16_PLTOFF:
1011 case BFD_RELOC_32_PLTOFF:
1014 as_bad_where (fixp->fx_file, fixp->fx_line,
1015 _("Cannot make %s relocation PC relative"),
1016 bfd_get_reloc_code_name (code));
1022 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1023 switch (F (fixp->fx_size, fixp->fx_pcrel))
1025 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1026 MAP (1, 0, BFD_RELOC_8);
1027 MAP (2, 0, BFD_RELOC_16);
1028 MAP (4, 0, BFD_RELOC_32);
1029 MAP (1, 1, BFD_RELOC_8_PCREL);
1030 MAP (2, 1, BFD_RELOC_16_PCREL);
1031 MAP (4, 1, BFD_RELOC_32_PCREL);
1039 reloc = (arelent *) xmalloc (sizeof (arelent));
1040 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1041 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1042 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1045 reloc->addend = fixp->fx_addnumber;
1049 if (!fixp->fx_pcrel)
1050 reloc->addend = fixp->fx_addnumber;
1052 reloc->addend = (section->vma
1053 /* Explicit sign extension in case char is
1055 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1056 + fixp->fx_addnumber
1057 + md_pcrel_from (fixp));
1060 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1061 assert (reloc->howto != 0);
1066 #endif /* BFD_ASSEMBLER */
1068 /* Handle of the OPCODE hash table. NULL means any use before
1069 m68k_ip_begin() will crash. */
1070 static struct hash_control *op_hash;
1072 /* Assemble an m68k instruction. */
1075 m68k_ip (char *instring)
1078 register struct m68k_op *opP;
1079 register const struct m68k_incant *opcode;
1080 register const char *s;
1081 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1082 char *pdot, *pdotmove;
1083 enum m68k_size siz1, siz2;
1087 LITTLENUM_TYPE words[6];
1088 LITTLENUM_TYPE *wordp;
1089 unsigned long ok_arch = 0;
1091 if (*instring == ' ')
1092 instring++; /* Skip leading whitespace. */
1094 /* Scan up to end of operation-code, which MUST end in end-of-string
1095 or exactly 1 space. */
1097 for (p = instring; *p != '\0'; p++)
1107 the_ins.error = _("No operator");
1111 /* p now points to the end of the opcode name, probably whitespace.
1112 Make sure the name is null terminated by clobbering the
1113 whitespace, look it up in the hash table, then fix it back.
1114 Remove a dot, first, since the opcode tables have none. */
1117 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1118 *pdotmove = pdotmove[1];
1124 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1129 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1130 *pdotmove = pdotmove[-1];
1137 the_ins.error = _("Unknown operator");
1141 /* Found a legitimate opcode, start matching operands. */
1145 if (opcode->m_operands == 0)
1147 char *old = input_line_pointer;
1149 input_line_pointer = p;
1150 /* Ahh - it's a motorola style psuedo op. */
1151 mote_pseudo_table[opcode->m_opnum].poc_handler
1152 (mote_pseudo_table[opcode->m_opnum].poc_val);
1153 input_line_pointer = old;
1159 if (flag_mri && opcode->m_opnum == 0)
1161 /* In MRI mode, random garbage is allowed after an instruction
1162 which accepts no operands. */
1163 the_ins.args = opcode->m_operands;
1164 the_ins.numargs = opcode->m_opnum;
1165 the_ins.numo = opcode->m_codenum;
1166 the_ins.opcode[0] = getone (opcode);
1167 the_ins.opcode[1] = gettwo (opcode);
1171 for (opP = &the_ins.operands[0]; *p; opP++)
1173 p = crack_operand (p, opP);
1177 the_ins.error = opP->error;
1182 opsfound = opP - &the_ins.operands[0];
1184 /* This ugly hack is to support the floating pt opcodes in their
1185 standard form. Essentially, we fake a first enty of type COP#1 */
1186 if (opcode->m_operands[0] == 'I')
1190 for (n = opsfound; n > 0; --n)
1191 the_ins.operands[n] = the_ins.operands[n - 1];
1193 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1194 the_ins.operands[0].mode = CONTROL;
1195 the_ins.operands[0].reg = m68k_float_copnum;
1199 /* We've got the operands. Find an opcode that'll accept them. */
1202 /* If we didn't get the right number of ops, or we have no
1203 common model with this pattern then reject this pattern. */
1205 ok_arch |= opcode->m_arch;
1206 if (opsfound != opcode->m_opnum
1207 || ((opcode->m_arch & current_architecture) == 0))
1211 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1215 /* Warning: this switch is huge! */
1216 /* I've tried to organize the cases into this order:
1217 non-alpha first, then alpha by letter. Lower-case
1218 goes directly before uppercase counterpart. */
1219 /* Code with multiple case ...: gets sorted by the lowest
1220 case ... it belongs to. I hope this makes sense. */
1326 if (opP->reg == PC || opP->reg == ZPC)
1343 if (opP->reg == PC || opP->reg == ZPC)
1362 if (opP->reg == PC || opP->reg == ZPC)
1372 if (opP->mode != IMMED)
1374 else if (s[1] == 'b'
1375 && ! isvar (&opP->disp)
1376 && (opP->disp.exp.X_op != O_constant
1377 || ! isbyte (opP->disp.exp.X_add_number)))
1379 else if (s[1] == 'B'
1380 && ! isvar (&opP->disp)
1381 && (opP->disp.exp.X_op != O_constant
1382 || ! issbyte (opP->disp.exp.X_add_number)))
1384 else if (s[1] == 'w'
1385 && ! isvar (&opP->disp)
1386 && (opP->disp.exp.X_op != O_constant
1387 || ! isword (opP->disp.exp.X_add_number)))
1389 else if (s[1] == 'W'
1390 && ! isvar (&opP->disp)
1391 && (opP->disp.exp.X_op != O_constant
1392 || ! issword (opP->disp.exp.X_add_number)))
1398 if (opP->mode != IMMED)
1403 if (opP->mode == AREG
1404 || opP->mode == CONTROL
1405 || opP->mode == FPREG
1406 || opP->mode == IMMED
1407 || opP->mode == REGLST
1408 || (opP->mode != ABSL
1410 || opP->reg == ZPC)))
1415 if (opP->mode == CONTROL
1416 || opP->mode == FPREG
1417 || opP->mode == REGLST
1418 || opP->mode == IMMED
1419 || (opP->mode != ABSL
1421 || opP->reg == ZPC)))
1449 if (opP->mode == CONTROL
1450 || opP->mode == FPREG
1451 || opP->mode == REGLST)
1456 if (opP->mode != AINC)
1461 if (opP->mode != ADEC)
1511 if (opP->reg == PC || opP->reg == ZPC)
1532 case '~': /* For now! (JF FOO is this right?) */
1554 if (opP->mode != CONTROL
1555 || (opP->reg != TT0 && opP->reg != TT1))
1560 if (opP->mode != AREG)
1565 if (opP->mode != AINDR)
1570 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1571 && (opP->mode != DISP
1573 || opP->reg > ADDR7))
1578 if (opP->mode != ABSL
1580 && strncmp (instring, "jbsr", 4) == 0))
1603 if (opP->mode != CONTROL || opP->reg != CCR)
1608 if (opP->mode != DISP
1610 || opP->reg > ADDR7)
1615 if (opP->mode != DREG)
1620 if (opP->reg != ACC)
1625 if (opP->reg != ACC && opP->reg != ACC1
1626 && opP->reg != ACC2 && opP->reg != ACC3)
1631 if (opP->mode != FPREG)
1636 if (opP->reg != MACSR)
1641 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1646 if (opP->reg != MASK)
1651 if (opP->mode != CONTROL
1658 if (opP->mode != LSH && opP->mode != RSH)
1663 if (opP->mode != CONTROL
1665 || opP->reg > last_movec_reg)
1669 const enum m68k_register *rp;
1670 for (rp = control_regs; *rp; rp++)
1671 if (*rp == opP->reg)
1679 if (opP->mode != IMMED)
1685 if (opP->mode == DREG
1686 || opP->mode == AREG
1687 || opP->mode == FPREG)
1696 opP->mask = 1 << (opP->reg - DATA0);
1699 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1702 opP->mask = 1 << (opP->reg - FP0 + 16);
1710 else if (opP->mode == CONTROL)
1719 opP->mask = 1 << 24;
1722 opP->mask = 1 << 25;
1725 opP->mask = 1 << 26;
1734 else if (opP->mode != REGLST)
1736 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1738 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1743 if (opP->mode != IMMED)
1745 else if (opP->disp.exp.X_op != O_constant
1746 || ! issbyte (opP->disp.exp.X_add_number))
1748 else if (! m68k_quick
1749 && instring[3] != 'q'
1750 && instring[4] != 'q')
1755 if (opP->mode != DREG
1756 && opP->mode != IMMED
1757 && opP->mode != ABSL)
1762 if (opP->mode != IMMED)
1764 else if (opP->disp.exp.X_op != O_constant
1765 || opP->disp.exp.X_add_number < 1
1766 || opP->disp.exp.X_add_number > 8)
1768 else if (! m68k_quick
1769 && (strncmp (instring, "add", 3) == 0
1770 || strncmp (instring, "sub", 3) == 0)
1771 && instring[3] != 'q')
1776 if (opP->mode != DREG && opP->mode != AREG)
1781 if (opP->mode != AINDR
1782 && (opP->mode != BASE
1784 && opP->reg != ZADDR0)
1785 || opP->disp.exp.X_op != O_absent
1786 || ((opP->index.reg < DATA0
1787 || opP->index.reg > DATA7)
1788 && (opP->index.reg < ADDR0
1789 || opP->index.reg > ADDR7))
1790 || opP->index.size != SIZE_UNSPEC
1791 || opP->index.scale != 1))
1796 if (opP->mode != CONTROL
1797 || ! (opP->reg == FPI
1799 || opP->reg == FPC))
1804 if (opP->mode != CONTROL || opP->reg != SR)
1809 if (opP->mode != IMMED)
1811 else if (opP->disp.exp.X_op != O_constant
1812 || opP->disp.exp.X_add_number < 0
1813 || opP->disp.exp.X_add_number > 7)
1818 if (opP->mode != CONTROL || opP->reg != USP)
1823 if (opP->mode != IMMED)
1825 else if (opP->disp.exp.X_op != O_constant
1826 || opP->disp.exp.X_add_number < -1
1827 || opP->disp.exp.X_add_number > 7
1828 || opP->disp.exp.X_add_number == 0)
1832 /* JF these are out of order. We could put them
1833 in order if we were willing to put up with
1834 bunches of #ifdef m68851s in the code.
1836 Don't forget that you need these operands
1837 to use 68030 MMU instructions. */
1839 /* Memory addressing mode used by pflushr. */
1841 if (opP->mode == CONTROL
1842 || opP->mode == FPREG
1843 || opP->mode == DREG
1844 || opP->mode == AREG
1845 || opP->mode == REGLST)
1847 /* We should accept immediate operands, but they
1848 supposedly have to be quad word, and we don't
1849 handle that. I would like to see what a Motorola
1850 assembler does before doing something here. */
1851 if (opP->mode == IMMED)
1856 if (opP->mode != CONTROL
1857 || (opP->reg != SFC && opP->reg != DFC))
1862 if (opP->mode != CONTROL || opP->reg != TC)
1867 if (opP->mode != CONTROL || opP->reg != AC)
1872 if (opP->mode != CONTROL
1875 && opP->reg != SCC))
1880 if (opP->mode != CONTROL
1886 if (opP->mode != CONTROL
1889 && opP->reg != CRP))
1913 if (opP->mode != CONTROL
1914 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1915 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1920 if (opP->mode != CONTROL || opP->reg != PSR)
1925 if (opP->mode != CONTROL || opP->reg != PCSR)
1930 if (opP->mode != CONTROL
1939 if (opP->mode != ABSL)
1944 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1946 /* FIXME: kludge instead of fixing parser:
1947 upper/lower registers are *not* CONTROL
1948 registers, but ordinary ones. */
1949 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1950 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1957 if (!(opP->mode == AINDR
1958 || (opP->mode == DISP
1959 && !(opP->reg == PC || opP->reg == ZPC))))
1964 if (!(opP->mode == AINDR || opP->mode == DISP))
1980 opcode = opcode->m_next;
1985 && !(ok_arch & current_architecture))
1990 _("invalid instruction for this architecture; needs "),
1992 cp = buf + strlen (buf);
1996 strncpy (cp, _("ColdFire ISA_A"),
1997 sizeof (buf) - (cp - buf));
1999 strncpy (cp, find_cf_chip (ok_arch),
2000 sizeof (buf) - (cp - buf));
2004 strncpy (cp, _("ColdFire hardware divide"),
2005 sizeof (buf) - (cp - buf));
2007 strncpy (cp, find_cf_chip (ok_arch),
2008 sizeof (buf) - (cp - buf));
2012 strncpy (cp, _("ColdFire ISA_A+"),
2013 sizeof (buf) - (cp - buf));
2015 strncpy (cp, find_cf_chip (ok_arch),
2016 sizeof (buf) - (cp - buf));
2020 strncpy (cp, _("ColdFire ISA_B"),
2021 sizeof (buf) - (cp - buf));
2023 strncpy (cp, find_cf_chip (ok_arch),
2024 sizeof (buf) - (cp - buf));
2028 strncpy (cp, _("ColdFire fpu"), sizeof (buf) - (cp - buf));
2030 strncpy (cp, find_cf_chip (ok_arch),
2031 sizeof (buf) - (cp - buf));
2035 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
2038 strcpy (cp, _("mmu (68030 or 68851)"));
2041 strcpy (cp, _("68020 or higher"));
2044 strcpy (cp, _("68000 or higher"));
2047 strcpy (cp, _("68010 or higher"));
2051 int got_one = 0, idx;
2053 for (idx = 0; idx < n_archs; idx++)
2055 if ((archs[idx].arch & ok_arch)
2056 && ! archs[idx].alias)
2060 strcpy (cp, " or ");
2064 strcpy (cp, archs[idx].name);
2070 cp = xmalloc (strlen (buf) + 1);
2075 the_ins.error = _("operands mismatch");
2082 /* Now assemble it. */
2083 the_ins.args = opcode->m_operands;
2084 the_ins.numargs = opcode->m_opnum;
2085 the_ins.numo = opcode->m_codenum;
2086 the_ins.opcode[0] = getone (opcode);
2087 the_ins.opcode[1] = gettwo (opcode);
2089 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2091 /* This switch is a doozy.
2092 Watch the first step; its a big one! */
2125 tmpreg = 0x3c; /* 7.4 */
2126 if (strchr ("bwl", s[1]))
2127 nextword = get_num (&opP->disp, 90);
2129 nextword = get_num (&opP->disp, 0);
2130 if (isvar (&opP->disp))
2131 add_fix (s[1], &opP->disp, 0, 0);
2135 if (!isbyte (nextword))
2136 opP->error = _("operand out of range");
2141 if (!isword (nextword))
2142 opP->error = _("operand out of range");
2147 if (!issword (nextword))
2148 opP->error = _("operand out of range");
2153 addword (nextword >> 16);
2180 /* We gotta put out some float. */
2181 if (op (&opP->disp) != O_big)
2186 /* Can other cases happen here? */
2187 if (op (&opP->disp) != O_constant)
2190 val = (valueT) offs (&opP->disp);
2194 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2195 val >>= LITTLENUM_NUMBER_OF_BITS;
2199 offs (&opP->disp) = gencnt;
2201 if (offs (&opP->disp) > 0)
2203 if (offs (&opP->disp) > baseo)
2205 as_warn (_("Bignum too big for %c format; truncated"),
2207 offs (&opP->disp) = baseo;
2209 baseo -= offs (&opP->disp);
2212 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2213 offs (&opP->disp)--;
2218 gen_to_words (words, baseo, (long) outro);
2219 for (wordp = words; baseo--; wordp++)
2223 tmpreg = opP->reg - DATA; /* 0.dreg */
2226 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2229 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2232 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2235 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2239 nextword = get_num (&opP->disp, 90);
2241 /* Convert mode 5 addressing with a zero offset into
2242 mode 2 addressing to reduce the instruction size by a
2244 if (! isvar (&opP->disp)
2246 && (opP->disp.size == SIZE_UNSPEC)
2247 && (opP->reg >= ADDR0)
2248 && (opP->reg <= ADDR7))
2250 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2255 && ! isvar (&opP->disp)
2258 opP->disp.exp.X_op = O_symbol;
2259 #ifndef BFD_ASSEMBLER
2260 opP->disp.exp.X_add_symbol = &abs_symbol;
2262 opP->disp.exp.X_add_symbol =
2263 section_symbol (absolute_section);
2267 /* Force into index mode. Hope this works. */
2269 /* We do the first bit for 32-bit displacements, and the
2270 second bit for 16 bit ones. It is possible that we
2271 should make the default be WORD instead of LONG, but
2272 I think that'd break GCC, so we put up with a little
2273 inefficiency for the sake of working output. */
2275 if (!issword (nextword)
2276 || (isvar (&opP->disp)
2277 && ((opP->disp.size == SIZE_UNSPEC
2278 && flag_short_refs == 0
2279 && cpu_of_arch (current_architecture) >= m68020
2280 && ! arch_coldfire_p (current_architecture))
2281 || opP->disp.size == SIZE_LONG)))
2283 if (cpu_of_arch (current_architecture) < m68020
2284 || arch_coldfire_p (current_architecture))
2286 _("displacement too large for this architecture; needs 68020 or higher");
2288 tmpreg = 0x3B; /* 7.3 */
2290 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2291 if (isvar (&opP->disp))
2295 if (opP->disp.size == SIZE_LONG
2297 /* If the displacement needs pic
2298 relocation it cannot be relaxed. */
2299 || opP->disp.pic_reloc != pic_none
2304 add_fix ('l', &opP->disp, 1, 2);
2308 add_frag (adds (&opP->disp),
2310 TAB (PCREL1632, SZ_UNDEF));
2317 add_fix ('l', &opP->disp, 0, 0);
2322 addword (nextword >> 16);
2327 tmpreg = 0x3A; /* 7.2 */
2329 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2331 if (isvar (&opP->disp))
2335 add_fix ('w', &opP->disp, 1, 0);
2338 add_fix ('w', &opP->disp, 0, 0);
2348 baseo = get_num (&opP->disp, 90);
2349 if (opP->mode == POST || opP->mode == PRE)
2350 outro = get_num (&opP->odisp, 90);
2351 /* Figure out the `addressing mode'.
2352 Also turn on the BASE_DISABLE bit, if needed. */
2353 if (opP->reg == PC || opP->reg == ZPC)
2355 tmpreg = 0x3b; /* 7.3 */
2356 if (opP->reg == ZPC)
2359 else if (opP->reg == 0)
2362 tmpreg = 0x30; /* 6.garbage */
2364 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2367 tmpreg = 0x30 + opP->reg - ZADDR0;
2370 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2372 siz1 = opP->disp.size;
2373 if (opP->mode == POST || opP->mode == PRE)
2374 siz2 = opP->odisp.size;
2378 /* Index register stuff. */
2379 if (opP->index.reg != 0
2380 && opP->index.reg >= DATA
2381 && opP->index.reg <= ADDR7)
2383 nextword |= (opP->index.reg - DATA) << 12;
2385 if (opP->index.size == SIZE_LONG
2386 || (opP->index.size == SIZE_UNSPEC
2387 && m68k_index_width_default == SIZE_LONG))
2390 if ((opP->index.scale != 1
2391 && cpu_of_arch (current_architecture) < m68020)
2392 || (opP->index.scale == 8
2393 && (arch_coldfire_p (current_architecture)
2394 && !arch_coldfire_fpu (current_architecture))))
2397 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2400 if (arch_coldfire_p (current_architecture)
2401 && opP->index.size == SIZE_WORD)
2402 opP->error = _("invalid index size for coldfire");
2404 switch (opP->index.scale)
2421 GET US OUT OF HERE! */
2423 /* Must be INDEX, with an index register. Address
2424 register cannot be ZERO-PC, and either :b was
2425 forced, or we know it will fit. For a 68000 or
2426 68010, force this mode anyways, because the
2427 larger modes aren't supported. */
2428 if (opP->mode == BASE
2429 && ((opP->reg >= ADDR0
2430 && opP->reg <= ADDR7)
2433 if (siz1 == SIZE_BYTE
2434 || cpu_of_arch (current_architecture) < m68020
2435 || arch_coldfire_p (current_architecture)
2436 || (siz1 == SIZE_UNSPEC
2437 && ! isvar (&opP->disp)
2438 && issbyte (baseo)))
2440 nextword += baseo & 0xff;
2442 if (isvar (&opP->disp))
2444 /* Do a byte relocation. If it doesn't
2445 fit (possible on m68000) let the
2446 fixup processing complain later. */
2448 add_fix ('B', &opP->disp, 1, 1);
2450 add_fix ('B', &opP->disp, 0, 0);
2452 else if (siz1 != SIZE_BYTE)
2454 if (siz1 != SIZE_UNSPEC)
2455 as_warn (_("Forcing byte displacement"));
2456 if (! issbyte (baseo))
2457 opP->error = _("byte displacement out of range");
2462 else if (siz1 == SIZE_UNSPEC
2464 && isvar (&opP->disp)
2465 && subs (&opP->disp) == NULL
2467 /* If the displacement needs pic
2468 relocation it cannot be relaxed. */
2469 && opP->disp.pic_reloc == pic_none
2473 /* The code in md_convert_frag_1 needs to be
2474 able to adjust nextword. Call frag_grow
2475 to ensure that we have enough space in
2476 the frag obstack to make all the bytes
2479 nextword += baseo & 0xff;
2481 add_frag (adds (&opP->disp), offs (&opP->disp),
2482 TAB (PCINDEX, SZ_UNDEF));
2490 nextword |= 0x40; /* No index reg. */
2491 if (opP->index.reg >= ZDATA0
2492 && opP->index.reg <= ZDATA7)
2493 nextword |= (opP->index.reg - ZDATA0) << 12;
2494 else if (opP->index.reg >= ZADDR0
2495 || opP->index.reg <= ZADDR7)
2496 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2499 /* It isn't simple. */
2501 if (cpu_of_arch (current_architecture) < m68020
2502 || arch_coldfire_p (current_architecture))
2504 _("invalid operand mode for this architecture; needs 68020 or higher");
2507 /* If the guy specified a width, we assume that it is
2508 wide enough. Maybe it isn't. If so, we lose. */
2512 if (isvar (&opP->disp)
2514 : ! issword (baseo))
2519 else if (! isvar (&opP->disp) && baseo == 0)
2528 as_warn (_(":b not permitted; defaulting to :w"));
2538 /* Figure out inner displacement stuff. */
2539 if (opP->mode == POST || opP->mode == PRE)
2541 if (cpu_of_arch (current_architecture) & cpu32)
2542 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2546 if (isvar (&opP->odisp)
2548 : ! issword (outro))
2553 else if (! isvar (&opP->odisp) && outro == 0)
2562 as_warn (_(":b not permitted; defaulting to :w"));
2571 if (opP->mode == POST
2572 && (nextword & 0x40) == 0)
2577 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2579 if (opP->reg == PC || opP->reg == ZPC)
2580 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2582 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2584 if (siz1 == SIZE_LONG)
2585 addword (baseo >> 16);
2586 if (siz1 != SIZE_UNSPEC)
2589 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2590 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2591 if (siz2 == SIZE_LONG)
2592 addword (outro >> 16);
2593 if (siz2 != SIZE_UNSPEC)
2599 nextword = get_num (&opP->disp, 90);
2600 switch (opP->disp.size)
2605 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2607 tmpreg = 0x38; /* 7.0 */
2611 if (isvar (&opP->disp)
2612 && !subs (&opP->disp)
2613 && adds (&opP->disp)
2615 /* If the displacement needs pic relocation it
2616 cannot be relaxed. */
2617 && opP->disp.pic_reloc == pic_none
2620 && !strchr ("~%&$?", s[0]))
2622 tmpreg = 0x3A; /* 7.2 */
2623 add_frag (adds (&opP->disp),
2625 TAB (ABSTOPCREL, SZ_UNDEF));
2628 /* Fall through into long. */
2630 if (isvar (&opP->disp))
2631 add_fix ('l', &opP->disp, 0, 0);
2633 tmpreg = 0x39;/* 7.1 mode */
2634 addword (nextword >> 16);
2639 as_bad (_("unsupported byte value; use a different suffix"));
2643 if (isvar (&opP->disp))
2644 add_fix ('w', &opP->disp, 0, 0);
2646 tmpreg = 0x38;/* 7.0 mode */
2654 as_bad (_("unknown/incorrect operand"));
2658 /* If s[0] is '4', then this is for the mac instructions
2659 that can have a trailing_ampersand set. If so, set 0x100
2660 bit on tmpreg so install_gen_operand can check for it and
2661 set the appropriate bit (word2, bit 5). */
2664 if (opP->trailing_ampersand)
2667 install_gen_operand (s[1], tmpreg);
2673 { /* JF: I hate floating point! */
2688 tmpreg = get_num (&opP->disp, tmpreg);
2689 if (isvar (&opP->disp))
2690 add_fix (s[1], &opP->disp, 0, 0);
2693 case 'b': /* Danger: These do no check for
2694 certain types of overflow.
2696 if (!isbyte (tmpreg))
2697 opP->error = _("out of range");
2698 insop (tmpreg, opcode);
2699 if (isvar (&opP->disp))
2700 the_ins.reloc[the_ins.nrel - 1].n =
2701 (opcode->m_codenum) * 2 + 1;
2704 if (!issbyte (tmpreg))
2705 opP->error = _("out of range");
2706 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2707 if (isvar (&opP->disp))
2708 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2711 if (!isword (tmpreg))
2712 opP->error = _("out of range");
2713 insop (tmpreg, opcode);
2714 if (isvar (&opP->disp))
2715 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2718 if (!issword (tmpreg))
2719 opP->error = _("out of range");
2720 insop (tmpreg, opcode);
2721 if (isvar (&opP->disp))
2722 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2725 /* Because of the way insop works, we put these two out
2727 insop (tmpreg, opcode);
2728 insop (tmpreg >> 16, opcode);
2729 if (isvar (&opP->disp))
2730 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2737 install_operand (s[1], tmpreg);
2748 install_operand (s[1], opP->reg - ADDR);
2752 tmpreg = get_num (&opP->disp, 90);
2756 add_fix ('B', &opP->disp, 1, -1);
2759 add_fix ('w', &opP->disp, 1, 0);
2764 if (! HAVE_LONG_BRANCH (current_architecture))
2765 as_warn (_("Can't use long branches on 68000/68010/5200"));
2766 the_ins.opcode[0] |= 0xff;
2767 add_fix ('l', &opP->disp, 1, 0);
2772 if (subs (&opP->disp)) /* We can't relax it. */
2776 /* If the displacement needs pic relocation it cannot be
2778 if (opP->disp.pic_reloc != pic_none)
2781 /* This could either be a symbol, or an absolute
2782 address. If it's an absolute address, turn it into
2783 an absolute jump right here and keep it out of the
2785 if (adds (&opP->disp) == 0)
2787 if (the_ins.opcode[0] == 0x6000) /* jbra */
2788 the_ins.opcode[0] = 0x4EF9;
2789 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2790 the_ins.opcode[0] = 0x4EB9;
2793 the_ins.opcode[0] ^= 0x0100;
2794 the_ins.opcode[0] |= 0x0006;
2797 add_fix ('l', &opP->disp, 0, 0);
2803 /* Now we know it's going into the relaxer. Now figure
2804 out which mode. We try in this order of preference:
2805 long branch, absolute jump, byte/word branches only. */
2806 if (HAVE_LONG_BRANCH (current_architecture))
2807 add_frag (adds (&opP->disp), offs (&opP->disp),
2808 TAB (BRANCHBWL, SZ_UNDEF));
2809 else if (! flag_keep_pcrel)
2811 if ((the_ins.opcode[0] == 0x6000)
2812 || (the_ins.opcode[0] == 0x6100))
2813 add_frag (adds (&opP->disp), offs (&opP->disp),
2814 TAB (BRABSJUNC, SZ_UNDEF));
2816 add_frag (adds (&opP->disp), offs (&opP->disp),
2817 TAB (BRABSJCOND, SZ_UNDEF));
2820 add_frag (adds (&opP->disp), offs (&opP->disp),
2821 TAB (BRANCHBW, SZ_UNDEF));
2824 if (isvar (&opP->disp))
2826 /* Check for DBcc instructions. We can relax them,
2827 but only if we have long branches and/or absolute
2829 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2830 && (HAVE_LONG_BRANCH (current_architecture)
2831 || (! flag_keep_pcrel)))
2833 if (HAVE_LONG_BRANCH (current_architecture))
2834 add_frag (adds (&opP->disp), offs (&opP->disp),
2835 TAB (DBCCLBR, SZ_UNDEF));
2837 add_frag (adds (&opP->disp), offs (&opP->disp),
2838 TAB (DBCCABSJ, SZ_UNDEF));
2841 add_fix ('w', &opP->disp, 1, 0);
2845 case 'C': /* Fixed size LONG coproc branches. */
2846 add_fix ('l', &opP->disp, 1, 0);
2850 case 'c': /* Var size Coprocesssor branches. */
2851 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2853 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2854 add_fix ('l', &opP->disp, 1, 0);
2859 add_frag (adds (&opP->disp), offs (&opP->disp),
2860 TAB (FBRANCH, SZ_UNDEF));
2867 case 'C': /* Ignore it. */
2870 case 'd': /* JF this is a kludge. */
2871 install_operand ('s', opP->reg - ADDR);
2872 tmpreg = get_num (&opP->disp, 90);
2873 if (!issword (tmpreg))
2875 as_warn (_("Expression out of range, using 0"));
2882 install_operand (s[1], opP->reg - DATA);
2885 case 'e': /* EMAC ACCx, reg/reg. */
2886 install_operand (s[1], opP->reg - ACC);
2889 case 'E': /* Ignore it. */
2893 install_operand (s[1], opP->reg - FP0);
2896 case 'g': /* EMAC ACCEXTx. */
2897 install_operand (s[1], opP->reg - ACCEXT01);
2900 case 'G': /* Ignore it. */
2905 tmpreg = opP->reg - COP0;
2906 install_operand (s[1], tmpreg);
2909 case 'i': /* MAC/EMAC scale factor. */
2910 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2913 case 'J': /* JF foo. */
3043 install_operand (s[1], tmpreg);
3047 tmpreg = get_num (&opP->disp, 55);
3048 install_operand (s[1], tmpreg & 0x7f);
3055 if (tmpreg & 0x7FF0000)
3056 as_bad (_("Floating point register in register list"));
3057 insop (reverse_16_bits (tmpreg), opcode);
3061 if (tmpreg & 0x700FFFF)
3062 as_bad (_("Wrong register in floating-point reglist"));
3063 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3071 if (tmpreg & 0x7FF0000)
3072 as_bad (_("Floating point register in register list"));
3073 insop (tmpreg, opcode);
3075 else if (s[1] == '8')
3077 if (tmpreg & 0x0FFFFFF)
3078 as_bad (_("incorrect register in reglist"));
3079 install_operand (s[1], tmpreg >> 24);
3083 if (tmpreg & 0x700FFFF)
3084 as_bad (_("wrong register in floating-point reglist"));
3086 install_operand (s[1], tmpreg >> 16);
3091 install_operand (s[1], get_num (&opP->disp, 60));
3095 tmpreg = ((opP->mode == DREG)
3096 ? 0x20 + (int) (opP->reg - DATA)
3097 : (get_num (&opP->disp, 40) & 0x1F));
3098 install_operand (s[1], tmpreg);
3102 tmpreg = get_num (&opP->disp, 10);
3105 install_operand (s[1], tmpreg);
3109 /* This depends on the fact that ADDR registers are eight
3110 more than their corresponding DATA regs, so the result
3111 will have the ADDR_REG bit set. */
3112 install_operand (s[1], opP->reg - DATA);
3116 if (opP->mode == AINDR)
3117 install_operand (s[1], opP->reg - DATA);
3119 install_operand (s[1], opP->index.reg - DATA);
3123 if (opP->reg == FPI)
3125 else if (opP->reg == FPS)
3127 else if (opP->reg == FPC)
3131 install_operand (s[1], tmpreg);
3134 case 'S': /* Ignore it. */
3138 install_operand (s[1], get_num (&opP->disp, 30));
3141 case 'U': /* Ignore it. */
3160 as_fatal (_("failed sanity check"));
3161 } /* switch on cache token. */
3162 install_operand (s[1], tmpreg);
3165 /* JF: These are out of order, I fear. */
3178 install_operand (s[1], tmpreg);
3204 install_operand (s[1], tmpreg);
3208 if (opP->reg == VAL)
3227 install_operand (s[1], tmpreg);
3241 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3252 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3258 install_operand (s[1], tmpreg);
3261 know (opP->reg == PSR);
3264 know (opP->reg == PCSR);
3279 install_operand (s[1], tmpreg);
3282 tmpreg = get_num (&opP->disp, 20);
3283 install_operand (s[1], tmpreg);
3285 case '_': /* used only for move16 absolute 32-bit address. */
3286 if (isvar (&opP->disp))
3287 add_fix ('l', &opP->disp, 0, 0);
3288 tmpreg = get_num (&opP->disp, 90);
3289 addword (tmpreg >> 16);
3290 addword (tmpreg & 0xFFFF);
3293 install_operand (s[1], opP->reg - DATA0L);
3294 opP->reg -= (DATA0L);
3295 opP->reg &= 0x0F; /* remove upper/lower bit. */
3298 tmpreg = get_num (&opP->disp, 80);
3301 install_operand (s[1], tmpreg);
3308 /* By the time whe get here (FINALLY) the_ins contains the complete
3309 instruction, ready to be emitted. . . */
3313 reverse_16_bits (int in)
3318 static int mask[16] =
3320 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3321 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3323 for (n = 0; n < 16; n++)
3326 out |= mask[15 - n];
3329 } /* reverse_16_bits() */
3332 reverse_8_bits (int in)
3337 static int mask[8] =
3339 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3342 for (n = 0; n < 8; n++)
3348 } /* reverse_8_bits() */
3350 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3351 (that value is chosen in the frag_var call in md_assemble). TYPE
3352 is the subtype of the frag to be generated; its primary type is
3353 rs_machine_dependent.
3355 The TYPE parameter is also used by md_convert_frag_1 and
3356 md_estimate_size_before_relax. The appropriate type of fixup will
3357 be emitted by md_convert_frag_1.
3359 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3361 install_operand (int mode, int val)
3366 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3369 the_ins.opcode[0] |= val << 9;
3372 the_ins.opcode[1] |= val << 12;
3375 the_ins.opcode[1] |= val << 6;
3378 the_ins.opcode[1] |= val;
3381 the_ins.opcode[2] |= val << 12;
3384 the_ins.opcode[2] |= val << 6;
3387 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3388 three words long! */
3390 the_ins.opcode[2] |= val;
3393 the_ins.opcode[1] |= val << 7;
3396 the_ins.opcode[1] |= val << 10;
3400 the_ins.opcode[1] |= val << 5;
3405 the_ins.opcode[1] |= (val << 10) | (val << 7);
3408 the_ins.opcode[1] |= (val << 12) | val;
3411 the_ins.opcode[0] |= val = 0xff;
3414 the_ins.opcode[0] |= val << 9;
3417 the_ins.opcode[1] |= val;
3420 the_ins.opcode[1] |= val;
3421 the_ins.numo++; /* What a hack. */
3424 the_ins.opcode[1] |= val << 4;
3432 the_ins.opcode[0] |= (val << 6);
3435 the_ins.opcode[1] = (val >> 16);
3436 the_ins.opcode[2] = val & 0xffff;
3439 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3440 the_ins.opcode[0] |= ((val & 0x7) << 9);
3441 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3443 case 'n': /* MAC/EMAC Rx on !load. */
3444 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3445 the_ins.opcode[0] |= ((val & 0x7) << 9);
3446 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3448 case 'o': /* MAC/EMAC Rx on load. */
3449 the_ins.opcode[1] |= val << 12;
3450 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3452 case 'M': /* MAC/EMAC Ry on !load. */
3453 the_ins.opcode[0] |= (val & 0xF);
3454 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3456 case 'N': /* MAC/EMAC Ry on load. */
3457 the_ins.opcode[1] |= (val & 0xF);
3458 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3461 the_ins.opcode[1] |= ((val != 1) << 10);
3464 the_ins.opcode[0] |= ((val & 0x3) << 9);
3467 the_ins.opcode[0] |= ((val & 0x3) << 0);
3469 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3470 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3471 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3473 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3474 the_ins.opcode[0] |= ((val & 0x1) << 7);
3475 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3478 the_ins.opcode[1] |= ((val & 0x3) << 9);
3481 the_ins.opcode[0] |= (val & 0x1) <<10;
3485 as_fatal (_("failed sanity check."));
3490 install_gen_operand (int mode, int val)
3494 case '/': /* Special for mask loads for mac/msac insns with
3495 possible mask; trailing_ampersend set in bit 8. */
3496 the_ins.opcode[0] |= (val & 0x3f);
3497 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3500 the_ins.opcode[0] |= val;
3503 /* This is a kludge!!! */
3504 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3513 the_ins.opcode[0] |= val;
3515 /* more stuff goes here. */
3517 as_fatal (_("failed sanity check."));
3521 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3522 then deal with the bitfield hack. */
3525 crack_operand (char *str, struct m68k_op *opP)
3527 register int parens;
3529 register char *beg_str;
3537 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3543 else if (*str == ')')
3547 opP->error = _("Extra )");
3553 if (flag_mri && *str == '\'')
3554 inquote = ! inquote;
3556 if (!*str && parens)
3558 opP->error = _("Missing )");
3563 if (m68k_ip_op (beg_str, opP) != 0)
3570 c = *++str; /* JF bitfield hack. */
3575 as_bad (_("Missing operand"));
3578 /* Detect MRI REG symbols and convert them to REGLSTs. */
3579 if (opP->mode == CONTROL && (int)opP->reg < 0)
3582 opP->mask = ~(int)opP->reg;
3589 /* This is the guts of the machine-dependent assembler. STR points to a
3590 machine dependent instruction. This function is supposed to emit
3591 the frags/bytes it assembles to.
3595 insert_reg (const char *regname, int regnum)
3600 #ifdef REGISTER_PREFIX
3601 if (!flag_reg_prefix_optional)
3603 buf[0] = REGISTER_PREFIX;
3604 strcpy (buf + 1, regname);
3609 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3610 &zero_address_frag));
3612 for (i = 0; regname[i]; i++)
3613 buf[i] = TOUPPER (regname[i]);
3616 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3617 &zero_address_frag));
3626 static const struct init_entry init_table[] =
3686 { "accext01", ACCEXT01 },
3687 { "accext23", ACCEXT23 },
3691 /* Control registers. */
3692 { "sfc", SFC }, /* Source Function Code. */
3694 { "dfc", DFC }, /* Destination Function Code. */
3696 { "cacr", CACR }, /* Cache Control Register. */
3697 { "caar", CAAR }, /* Cache Address Register. */
3699 { "usp", USP }, /* User Stack Pointer. */
3700 { "vbr", VBR }, /* Vector Base Register. */
3701 { "msp", MSP }, /* Master Stack Pointer. */
3702 { "isp", ISP }, /* Interrupt Stack Pointer. */
3704 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3705 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3706 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3707 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3709 /* 68ec040 versions of same */
3710 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3711 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3712 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3713 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3715 /* mcf5200 versions of same. The ColdFire programmer's reference
3716 manual indicated that the order is 2,3,0,1, but Ken Rose
3717 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3718 { "acr0", ACR0 }, /* Access Control Unit 0. */
3719 { "acr1", ACR1 }, /* Access Control Unit 1. */
3720 { "acr2", ACR2 }, /* Access Control Unit 2. */
3721 { "acr3", ACR3 }, /* Access Control Unit 3. */
3723 { "tc", TC }, /* MMU Translation Control Register. */
3726 { "mmusr", MMUSR }, /* MMU Status Register. */
3727 { "srp", SRP }, /* User Root Pointer. */
3728 { "urp", URP }, /* Supervisor Root Pointer. */
3733 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3734 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3735 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3736 { "mbar", MBAR }, /* Module Base Address Register. */
3738 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3739 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3740 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3741 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3742 { "mpcr", MPCR }, /* mcfv4e registers. */
3743 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3744 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3745 { "asid", TC }, /* mcfv4e registers. */
3746 { "mmubar", BUSCR }, /* mcfv4e registers. */
3747 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3748 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3749 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3750 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3751 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3752 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3753 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3754 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3755 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3756 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3757 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3758 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3760 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3761 { "rambar", RAMBAR }, /* mcf528x registers. */
3763 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3764 /* End of control registers. */
3798 /* 68ec030 versions of same. */
3801 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3804 /* Suppressed data and address registers. */
3822 /* Upper and lower data and address registers, used by macw and msacw. */
3863 init_regtable (void)
3866 for (i = 0; init_table[i].name; i++)
3867 insert_reg (init_table[i].name, init_table[i].number);
3870 static int no_68851, no_68881;
3873 /* a.out machine type. Default to 68020. */
3874 int m68k_aout_machtype = 2;
3878 md_assemble (char *str)
3885 int shorts_this_frag;
3888 /* In MRI mode, the instruction and operands are separated by a
3889 space. Anything following the operands is a comment. The label
3890 has already been removed. */
3898 for (s = str; *s != '\0'; s++)
3900 if ((*s == ' ' || *s == '\t') && ! inquote)
3918 inquote = ! inquote;
3923 memset (&the_ins, '\0', sizeof (the_ins));
3928 for (n = 0; n < the_ins.numargs; n++)
3929 if (the_ins.operands[n].error)
3931 er = the_ins.operands[n].error;
3937 as_bad (_("%s -- statement `%s' ignored"), er, str);
3941 /* If there is a current label, record that it marks an instruction. */
3942 if (current_label != NULL)
3944 current_label->text = 1;
3945 current_label = NULL;
3949 /* Tie dwarf2 debug info to the address at the start of the insn. */
3950 dwarf2_emit_insn (0);
3953 if (the_ins.nfrag == 0)
3955 /* No frag hacking involved; just put it out. */
3956 toP = frag_more (2 * the_ins.numo);
3957 fromP = &the_ins.opcode[0];
3958 for (m = the_ins.numo; m; --m)
3960 md_number_to_chars (toP, (long) (*fromP), 2);
3964 /* Put out symbol-dependent info. */
3965 for (m = 0; m < the_ins.nrel; m++)
3967 switch (the_ins.reloc[m].wid)
3986 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3987 the_ins.reloc[m].wid);
3990 fixP = fix_new_exp (frag_now,
3991 ((toP - frag_now->fr_literal)
3992 - the_ins.numo * 2 + the_ins.reloc[m].n),
3994 &the_ins.reloc[m].exp,
3995 the_ins.reloc[m].pcrel,
3996 get_reloc_code (n, the_ins.reloc[m].pcrel,
3997 the_ins.reloc[m].pic_reloc));
3998 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3999 if (the_ins.reloc[m].wid == 'B')
4000 fixP->fx_signed = 1;
4005 /* There's some frag hacking. */
4007 /* Calculate the max frag size. */
4010 wid = 2 * the_ins.fragb[0].fragoff;
4011 for (n = 1; n < the_ins.nfrag; n++)
4012 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4013 /* frag_var part. */
4015 /* Make sure the whole insn fits in one chunk, in particular that
4016 the var part is attached, as we access one byte before the
4017 variable frag for byte branches. */
4021 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4026 wid = 2 * the_ins.fragb[n].fragoff;
4028 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4029 toP = frag_more (wid);
4031 shorts_this_frag = 0;
4032 for (m = wid / 2; m; --m)
4034 md_number_to_chars (toP, (long) (*fromP), 2);
4039 for (m = 0; m < the_ins.nrel; m++)
4041 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4043 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4046 wid = the_ins.reloc[m].wid;
4049 the_ins.reloc[m].wid = 0;
4050 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4052 fixP = fix_new_exp (frag_now,
4053 ((toP - frag_now->fr_literal)
4054 - the_ins.numo * 2 + the_ins.reloc[m].n),
4056 &the_ins.reloc[m].exp,
4057 the_ins.reloc[m].pcrel,
4058 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4059 the_ins.reloc[m].pic_reloc));
4060 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4062 (void) frag_var (rs_machine_dependent, 10, 0,
4063 (relax_substateT) (the_ins.fragb[n].fragty),
4064 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4066 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4067 shorts_this_frag = 0;
4070 toP = frag_more (n * 2);
4073 md_number_to_chars (toP, (long) (*fromP), 2);
4079 for (m = 0; m < the_ins.nrel; m++)
4083 wid = the_ins.reloc[m].wid;
4086 the_ins.reloc[m].wid = 0;
4087 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4089 fixP = fix_new_exp (frag_now,
4090 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4091 - shorts_this_frag * 2),
4093 &the_ins.reloc[m].exp,
4094 the_ins.reloc[m].pcrel,
4095 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4096 the_ins.reloc[m].pic_reloc));
4097 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4101 /* Comparison function used by qsort to rank the opcode entries by name. */
4104 m68k_compare_opcode (const void * v1, const void * v2)
4106 struct m68k_opcode * op1, * op2;
4109 op1 = *(struct m68k_opcode **) v1;
4110 op2 = *(struct m68k_opcode **) v2;
4112 /* Compare the two names. If different, return the comparison.
4113 If the same, return the order they are in the opcode table. */
4114 ret = strcmp (op1->name, op2->name);
4125 const struct m68k_opcode *ins;
4126 struct m68k_incant *hack, *slak;
4127 const char *retval = 0; /* Empty string, or error msg text. */
4130 /* Set up hash tables with 68000 instructions.
4131 similar to what the vax assembler does. */
4132 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4133 a copy of it at runtime, adding in the information we want but isn't
4134 there. I think it'd be better to have an awk script hack the table
4135 at compile time. Or even just xstr the table and use it as-is. But
4136 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4141 flag_reg_prefix_optional = 1;
4143 if (! m68k_rel32_from_cmdline)
4147 /* First sort the opcode table into alphabetical order to seperate
4148 the order that the assembler wants to see the opcodes from the
4149 order that the disassembler wants to see them. */
4150 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4151 if (!m68k_sorted_opcodes)
4152 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4153 m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4155 for (i = m68k_numopcodes; i--;)
4156 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4158 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4159 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4161 op_hash = hash_new ();
4163 obstack_begin (&robyn, 4000);
4164 for (i = 0; i < m68k_numopcodes; i++)
4166 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4169 ins = m68k_sorted_opcodes[i];
4171 /* We *could* ignore insns that don't match our
4172 arch here by just leaving them out of the hash. */
4173 slak->m_operands = ins->args;
4174 slak->m_opnum = strlen (slak->m_operands) / 2;
4175 slak->m_arch = ins->arch;
4176 slak->m_opcode = ins->opcode;
4177 /* This is kludgey. */
4178 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4179 if (i + 1 != m68k_numopcodes
4180 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4182 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4187 slak = slak->m_next;
4191 retval = hash_insert (op_hash, ins->name, (char *) hack);
4193 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4196 for (i = 0; i < m68k_numaliases; i++)
4198 const char *name = m68k_opcode_aliases[i].primary;
4199 const char *alias = m68k_opcode_aliases[i].alias;
4200 PTR val = hash_find (op_hash, name);
4203 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4204 retval = hash_insert (op_hash, alias, val);
4206 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4209 /* In MRI mode, all unsized branches are variable sized. Normally,
4210 they are word sized. */
4213 static struct m68k_opcode_alias mri_aliases[] =
4234 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4237 const char *name = mri_aliases[i].primary;
4238 const char *alias = mri_aliases[i].alias;
4239 PTR val = hash_find (op_hash, name);
4242 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4243 retval = hash_jam (op_hash, alias, val);
4245 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4249 for (i = 0; i < (int) sizeof (notend_table); i++)
4251 notend_table[i] = 0;
4252 alt_notend_table[i] = 0;
4255 notend_table[','] = 1;
4256 notend_table['{'] = 1;
4257 notend_table['}'] = 1;
4258 alt_notend_table['a'] = 1;
4259 alt_notend_table['A'] = 1;
4260 alt_notend_table['d'] = 1;
4261 alt_notend_table['D'] = 1;
4262 alt_notend_table['#'] = 1;
4263 alt_notend_table['&'] = 1;
4264 alt_notend_table['f'] = 1;
4265 alt_notend_table['F'] = 1;
4266 #ifdef REGISTER_PREFIX
4267 alt_notend_table[REGISTER_PREFIX] = 1;
4270 /* We need to put '(' in alt_notend_table to handle
4271 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4272 alt_notend_table['('] = 1;
4274 /* We need to put '@' in alt_notend_table to handle
4275 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4276 alt_notend_table['@'] = 1;
4278 /* We need to put digits in alt_notend_table to handle
4279 bfextu %d0{24:1},%d0 */
4280 alt_notend_table['0'] = 1;
4281 alt_notend_table['1'] = 1;
4282 alt_notend_table['2'] = 1;
4283 alt_notend_table['3'] = 1;
4284 alt_notend_table['4'] = 1;
4285 alt_notend_table['5'] = 1;
4286 alt_notend_table['6'] = 1;
4287 alt_notend_table['7'] = 1;
4288 alt_notend_table['8'] = 1;
4289 alt_notend_table['9'] = 1;
4291 #ifndef MIT_SYNTAX_ONLY
4292 /* Insert pseudo ops, these have to go into the opcode table since
4293 gas expects pseudo ops to start with a dot. */
4297 while (mote_pseudo_table[n].poc_name)
4299 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4300 hash_insert (op_hash,
4301 mote_pseudo_table[n].poc_name, (char *) hack);
4302 hack->m_operands = 0;
4312 record_alignment (text_section, 2);
4313 record_alignment (data_section, 2);
4314 record_alignment (bss_section, 2);
4319 select_control_regs (void)
4321 /* Note which set of "movec" control registers is available. */
4322 switch (current_chip)
4326 as_warn (_("architecture not yet selected: defaulting to 68020"));
4327 control_regs = m68020_control_regs;
4331 control_regs = m68000_control_regs;
4334 control_regs = m68010_control_regs;
4338 control_regs = m68020_control_regs;
4341 control_regs = m68040_control_regs;
4344 control_regs = m68060_control_regs;
4347 control_regs = cpu32_control_regs;
4353 control_regs = mcf_control_regs;
4356 control_regs = mcf5249_control_regs;
4360 control_regs = mcf528x_control_regs;
4364 control_regs = mcfv4e_control_regs;
4372 m68k_init_after_args (void)
4374 if (cpu_of_arch (current_architecture) == 0)
4377 const char *default_cpu = TARGET_CPU;
4379 if (*default_cpu == 'm')
4381 for (i = 0; i < n_archs; i++)
4382 if (strcasecmp (default_cpu, archs[i].name) == 0)
4386 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4387 current_architecture |= m68020;
4390 current_architecture |= archs[i].arch;
4392 /* Permit m68881 specification with all cpus; those that can't work
4393 with a coprocessor could be doing emulation. */
4394 if (current_architecture & m68851)
4396 if (current_architecture & m68040)
4397 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4399 /* What other incompatibilities could we check for? */
4401 /* Toss in some default assumptions about coprocessors. */
4403 && (cpu_of_arch (current_architecture)
4404 /* Can CPU32 have a 68881 coprocessor?? */
4405 & (m68020 | m68030 | cpu32)))
4406 current_architecture |= m68881;
4409 && (cpu_of_arch (current_architecture) & m68020up) != 0
4410 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4411 current_architecture |= m68851;
4413 if (no_68881 && (current_architecture & m68881))
4414 as_bad (_("options for 68881 and no-68881 both given"));
4416 if (no_68851 && (current_architecture & m68851))
4417 as_bad (_("options for 68851 and no-68851 both given"));
4420 /* Work out the magic number. This isn't very general. */
4421 if (current_architecture & m68000)
4422 m68k_aout_machtype = 0;
4423 else if (current_architecture & m68010)
4424 m68k_aout_machtype = 1;
4425 else if (current_architecture & m68020)
4426 m68k_aout_machtype = 2;
4428 m68k_aout_machtype = 2;
4431 /* Note which set of "movec" control registers is available. */
4432 select_control_regs ();
4434 if (cpu_of_arch (current_architecture) < m68020
4435 || arch_coldfire_p (current_architecture))
4436 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4439 /* This is called when a label is defined. */
4442 m68k_frob_label (symbolS *sym)
4444 struct label_line *n;
4446 n = (struct label_line *) xmalloc (sizeof *n);
4449 as_where (&n->file, &n->line);
4455 /* This is called when a value that is not an instruction is emitted. */
4458 m68k_flush_pending_output (void)
4460 current_label = NULL;
4463 /* This is called at the end of the assembly, when the final value of
4464 the label is known. We warn if this is a text symbol aligned at an
4468 m68k_frob_symbol (symbolS *sym)
4470 if (S_GET_SEGMENT (sym) == reg_section
4471 && (int) S_GET_VALUE (sym) < 0)
4473 S_SET_SEGMENT (sym, absolute_section);
4474 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4476 else if ((S_GET_VALUE (sym) & 1) != 0)
4478 struct label_line *l;
4480 for (l = labels; l != NULL; l = l->next)
4482 if (l->label == sym)
4485 as_warn_where (l->file, l->line,
4486 _("text label `%s' aligned to odd boundary"),
4494 /* This is called if we go in or out of MRI mode because of the .mri
4498 m68k_mri_mode_change (int on)
4502 if (! flag_reg_prefix_optional)
4504 flag_reg_prefix_optional = 1;
4505 #ifdef REGISTER_PREFIX
4510 if (! m68k_rel32_from_cmdline)
4515 if (! reg_prefix_optional_seen)
4517 #ifdef REGISTER_PREFIX_OPTIONAL
4518 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4520 flag_reg_prefix_optional = 0;
4522 #ifdef REGISTER_PREFIX
4527 if (! m68k_rel32_from_cmdline)
4532 /* Equal to MAX_PRECISION in atof-ieee.c. */
4533 #define MAX_LITTLENUMS 6
4535 /* Turn a string in input_line_pointer into a floating point constant
4536 of type TYPE, and store the appropriate bytes in *LITP. The number
4537 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4538 returned, or NULL on OK. */
4541 md_atof (int type, char *litP, int *sizeP)
4544 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4545 LITTLENUM_TYPE *wordP;
4576 return _("Bad call to MD_ATOF()");
4578 t = atof_ieee (input_line_pointer, type, words);
4580 input_line_pointer = t;
4582 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4583 for (wordP = words; prec--;)
4585 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4586 litP += sizeof (LITTLENUM_TYPE);
4592 md_number_to_chars (char *buf, valueT val, int n)
4594 number_to_chars_bigendian (buf, val, n);
4598 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4600 offsetT val = *valP;
4601 addressT upper_limit;
4602 offsetT lower_limit;
4604 /* This is unnecessary but it convinces the native rs6000 compiler
4605 to generate the code we want. */
4606 char *buf = fixP->fx_frag->fr_literal;
4607 buf += fixP->fx_where;
4608 /* End ibm compiler workaround. */
4610 val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
4612 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4618 memset (buf, 0, fixP->fx_size);
4619 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4621 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4622 && !S_IS_DEFINED (fixP->fx_addsy)
4623 && !S_IS_WEAK (fixP->fx_addsy))
4624 S_SET_WEAK (fixP->fx_addsy);
4629 #ifdef BFD_ASSEMBLER
4630 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4631 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4635 switch (fixP->fx_size)
4637 /* The cast to offsetT below are necessary to make code
4638 correct for machines where ints are smaller than offsetT. */
4642 lower_limit = - (offsetT) 0x80;
4645 *buf++ = (val >> 8);
4647 upper_limit = 0x7fff;
4648 lower_limit = - (offsetT) 0x8000;
4651 *buf++ = (val >> 24);
4652 *buf++ = (val >> 16);
4653 *buf++ = (val >> 8);
4655 upper_limit = 0x7fffffff;
4656 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4659 BAD_CASE (fixP->fx_size);
4662 /* Fix up a negative reloc. */
4663 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4665 fixP->fx_addsy = fixP->fx_subsy;
4666 fixP->fx_subsy = NULL;
4670 /* For non-pc-relative values, it's conceivable we might get something
4671 like "0xff" for a byte field. So extend the upper part of the range
4672 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4673 so that we can do any range checking at all. */
4674 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4675 upper_limit = upper_limit * 2 + 1;
4677 if ((addressT) val > upper_limit
4678 && (val > 0 || val < lower_limit))
4679 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4681 /* A one byte PC-relative reloc means a short branch. We can't use
4682 a short branch with a value of 0 or -1, because those indicate
4683 different opcodes (branches with longer offsets). fixup_segment
4684 in write.c may have clobbered fx_pcrel, so we need to examine the
4687 #ifdef BFD_ASSEMBLER
4688 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4691 && fixP->fx_size == 1
4692 && (fixP->fx_addsy == NULL
4693 || S_IS_DEFINED (fixP->fx_addsy))
4694 && (val == 0 || val == -1))
4695 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4698 /* *fragP has been relaxed to its final size, and now needs to have
4699 the bytes inside it modified to conform to the new size There is UGLY
4703 md_convert_frag_1 (fragS *fragP)
4708 /* Address in object code of the displacement. */
4709 register int object_address = fragP->fr_fix + fragP->fr_address;
4711 /* Address in gas core of the place to store the displacement. */
4712 /* This convinces the native rs6000 compiler to generate the code we
4714 register char *buffer_address = fragP->fr_literal;
4715 buffer_address += fragP->fr_fix;
4716 /* End ibm compiler workaround. */
4718 /* The displacement of the address, from current location. */
4719 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4720 disp = (disp + fragP->fr_offset) - object_address;
4722 switch (fragP->fr_subtype)
4724 case TAB (BRANCHBWL, BYTE):
4725 case TAB (BRABSJUNC, BYTE):
4726 case TAB (BRABSJCOND, BYTE):
4727 case TAB (BRANCHBW, BYTE):
4728 know (issbyte (disp));
4730 as_bad_where (fragP->fr_file, fragP->fr_line,
4731 _("short branch with zero offset: use :w"));
4732 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4733 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4734 fixP->fx_pcrel_adjust = -1;
4736 case TAB (BRANCHBWL, SHORT):
4737 case TAB (BRABSJUNC, SHORT):
4738 case TAB (BRABSJCOND, SHORT):
4739 case TAB (BRANCHBW, SHORT):
4740 fragP->fr_opcode[1] = 0x00;
4741 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4742 1, RELAX_RELOC_PC16);
4745 case TAB (BRANCHBWL, LONG):
4746 fragP->fr_opcode[1] = (char) 0xFF;
4747 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4748 1, RELAX_RELOC_PC32);
4751 case TAB (BRABSJUNC, LONG):
4752 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4754 if (flag_keep_pcrel)
4755 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4756 fragP->fr_opcode[0] = 0x4E;
4757 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4758 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4759 0, RELAX_RELOC_ABS32);
4762 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4764 if (flag_keep_pcrel)
4765 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4766 fragP->fr_opcode[0] = 0x4E;
4767 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4768 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4769 0, RELAX_RELOC_ABS32);
4774 /* This cannot happen, because jbsr and jbra are the only two
4775 unconditional branches. */
4779 case TAB (BRABSJCOND, LONG):
4780 if (flag_keep_pcrel)
4781 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4783 /* Only Bcc 68000 instructions can come here
4784 Change bcc into b!cc/jmp absl long. */
4785 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4786 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4788 /* JF: these used to be fr_opcode[2,3], but they may be in a
4789 different frag, in which case referring to them is a no-no.
4790 Only fr_opcode[0,1] are guaranteed to work. */
4791 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4792 *buffer_address++ = (char) 0xf9;
4793 fragP->fr_fix += 2; /* Account for jmp instruction. */
4794 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4795 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4798 case TAB (FBRANCH, SHORT):
4799 know ((fragP->fr_opcode[1] & 0x40) == 0);
4800 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4801 1, RELAX_RELOC_PC16);
4804 case TAB (FBRANCH, LONG):
4805 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4806 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4807 1, RELAX_RELOC_PC32);
4810 case TAB (DBCCLBR, SHORT):
4811 case TAB (DBCCABSJ, SHORT):
4812 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4813 1, RELAX_RELOC_PC16);
4816 case TAB (DBCCLBR, LONG):
4817 /* Only DBcc instructions can come here.
4818 Change dbcc into dbcc/bral.
4819 JF: these used to be fr_opcode[2-7], but that's wrong. */
4820 if (flag_keep_pcrel)
4821 as_fatal (_("Tried to convert DBcc to absolute jump"));
4823 *buffer_address++ = 0x00; /* Branch offset = 4. */
4824 *buffer_address++ = 0x04;
4825 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4826 *buffer_address++ = 0x06;
4827 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4828 *buffer_address++ = (char) 0xff;
4830 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4831 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4835 case TAB (DBCCABSJ, LONG):
4836 /* Only DBcc instructions can come here.
4837 Change dbcc into dbcc/jmp.
4838 JF: these used to be fr_opcode[2-7], but that's wrong. */
4839 if (flag_keep_pcrel)
4840 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4842 *buffer_address++ = 0x00; /* Branch offset = 4. */
4843 *buffer_address++ = 0x04;
4844 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4845 *buffer_address++ = 0x06;
4846 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4847 *buffer_address++ = (char) 0xf9;
4849 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4850 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4854 case TAB (PCREL1632, SHORT):
4855 fragP->fr_opcode[1] &= ~0x3F;
4856 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4857 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4858 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4861 case TAB (PCREL1632, LONG):
4862 /* Already set to mode 7.3; this indicates: PC indirect with
4863 suppressed index, 32-bit displacement. */
4864 *buffer_address++ = 0x01;
4865 *buffer_address++ = 0x70;
4867 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4868 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4869 fixP->fx_pcrel_adjust = 2;
4872 case TAB (PCINDEX, BYTE):
4873 assert (fragP->fr_fix >= 2);
4874 buffer_address[-2] &= ~1;
4875 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4876 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4877 fixP->fx_pcrel_adjust = 1;
4879 case TAB (PCINDEX, SHORT):
4880 assert (fragP->fr_fix >= 2);
4881 buffer_address[-2] |= 0x1;
4882 buffer_address[-1] = 0x20;
4883 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4884 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4885 fixP->fx_pcrel_adjust = 2;
4888 case TAB (PCINDEX, LONG):
4889 assert (fragP->fr_fix >= 2);
4890 buffer_address[-2] |= 0x1;
4891 buffer_address[-1] = 0x30;
4892 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4893 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4894 fixP->fx_pcrel_adjust = 2;
4897 case TAB (ABSTOPCREL, SHORT):
4898 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4899 1, RELAX_RELOC_PC16);
4902 case TAB (ABSTOPCREL, LONG):
4903 if (flag_keep_pcrel)
4904 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4905 /* The thing to do here is force it to ABSOLUTE LONG, since
4906 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4907 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4909 fragP->fr_opcode[1] &= ~0x3F;
4910 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4911 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4912 0, RELAX_RELOC_ABS32);
4918 #ifndef BFD_ASSEMBLER
4921 md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED,
4922 segT sec ATTRIBUTE_UNUSED,
4925 md_convert_frag_1 (fragP);
4931 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4932 segT sec ATTRIBUTE_UNUSED,
4935 md_convert_frag_1 (fragP);
4939 /* Force truly undefined symbols to their maximum size, and generally set up
4940 the frag list to be relaxed
4943 md_estimate_size_before_relax (fragS *fragP, segT segment)
4945 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4946 switch (fragP->fr_subtype)
4948 case TAB (BRANCHBWL, SZ_UNDEF):
4949 case TAB (BRABSJUNC, SZ_UNDEF):
4950 case TAB (BRABSJCOND, SZ_UNDEF):
4952 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4953 && relaxable_symbol (fragP->fr_symbol))
4955 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4957 else if (flag_short_refs)
4959 /* Symbol is undefined and we want short ref. */
4960 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4964 /* Symbol is still undefined. Make it LONG. */
4965 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4970 case TAB (BRANCHBW, SZ_UNDEF):
4972 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4973 && relaxable_symbol (fragP->fr_symbol))
4975 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4979 /* Symbol is undefined and we don't have long branches. */
4980 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4985 case TAB (FBRANCH, SZ_UNDEF):
4986 case TAB (DBCCLBR, SZ_UNDEF):
4987 case TAB (DBCCABSJ, SZ_UNDEF):
4988 case TAB (PCREL1632, SZ_UNDEF):
4990 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4991 && relaxable_symbol (fragP->fr_symbol))
4994 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4998 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5003 case TAB (PCINDEX, SZ_UNDEF):
5004 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5005 && relaxable_symbol (fragP->fr_symbol)))
5007 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5011 fragP->fr_subtype = TAB (PCINDEX, LONG);
5015 case TAB (ABSTOPCREL, SZ_UNDEF):
5017 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5018 && relaxable_symbol (fragP->fr_symbol)))
5020 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5024 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5033 /* Now that SZ_UNDEF are taken care of, check others. */
5034 switch (fragP->fr_subtype)
5036 case TAB (BRANCHBWL, BYTE):
5037 case TAB (BRABSJUNC, BYTE):
5038 case TAB (BRABSJCOND, BYTE):
5039 case TAB (BRANCHBW, BYTE):
5040 /* We can't do a short jump to the next instruction, so in that
5041 case we force word mode. If the symbol is at the start of a
5042 frag, and it is the next frag with any data in it (usually
5043 this is just the next frag, but assembler listings may
5044 introduce empty frags), we must use word mode. */
5045 if (fragP->fr_symbol)
5049 sym_frag = symbol_get_frag (fragP->fr_symbol);
5050 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5054 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5058 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5065 return md_relax_table[fragP->fr_subtype].rlx_length;
5068 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5069 /* the bit-field entries in the relocation_info struct plays hell
5070 with the byte-order problems of cross-assembly. So as a hack,
5071 I added this mach. dependent ri twiddler. Ugly, but it gets
5073 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5074 are symbolnum, most sig. byte first. Last byte is broken up with
5075 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5076 nibble as nuthin. (on Sun 3 at least) */
5077 /* Translate the internal relocation information into target-specific
5081 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5084 md_number_to_chars (the_bytes, ri->r_address, 4);
5085 /* Now the fun stuff. */
5086 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5087 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5088 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5089 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5090 | ((ri->r_length << 5) & 0x60)
5091 | ((ri->r_extern << 4) & 0x10));
5096 #ifndef BFD_ASSEMBLER
5098 tc_aout_fix_to_chars (char *where, fixS *fixP,
5099 relax_addressT segment_address_in_file)
5102 * In: length of relocation (or of address) in chars: 1, 2 or 4.
5103 * Out: GNU LD relocation length code: 0, 1, or 2.
5106 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
5109 know (fixP->fx_addsy != NULL);
5111 md_number_to_chars (where,
5112 (fixP->fx_frag->fr_address
5113 + fixP->fx_where - segment_address_in_file), 4);
5115 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5116 ? S_GET_TYPE (fixP->fx_addsy)
5117 : fixP->fx_addsy->sy_number);
5119 where[4] = (r_symbolnum >> 16) & 0x0ff;
5120 where[5] = (r_symbolnum >> 8) & 0x0ff;
5121 where[6] = r_symbolnum & 0x0ff;
5122 where[7] = (((fixP->fx_pcrel << 7) & 0x80)
5123 | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60)
5124 | ((!S_IS_DEFINED (fixP->fx_addsy) << 4) & 0x10));
5128 #endif /* OBJ_AOUT or OBJ_BOUT */
5130 #ifndef WORKING_DOT_WORD
5131 int md_short_jump_size = 4;
5132 int md_long_jump_size = 6;
5135 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5136 fragS *frag ATTRIBUTE_UNUSED,
5137 symbolS *to_symbol ATTRIBUTE_UNUSED)
5141 offset = to_addr - (from_addr + 2);
5143 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5144 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5148 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5149 fragS *frag, symbolS *to_symbol)
5153 if (!HAVE_LONG_BRANCH (current_architecture))
5155 if (flag_keep_pcrel)
5156 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5157 offset = to_addr - S_GET_VALUE (to_symbol);
5158 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5159 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5160 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5165 offset = to_addr - (from_addr + 2);
5166 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5167 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5173 /* Different values of OK tell what its OK to return. Things that
5174 aren't OK are an error (what a shock, no?)
5177 10: Absolute 1:8 only
5178 20: Absolute 0:7 only
5179 30: absolute 0:15 only
5180 40: Absolute 0:31 only
5181 50: absolute 0:127 only
5182 55: absolute -64:63 only
5183 60: absolute -128:127 only
5184 70: absolute 0:4095 only
5185 80: absolute -1, 1:7 only
5189 get_num (struct m68k_exp *exp, int ok)
5191 if (exp->exp.X_op == O_absent)
5193 /* Do the same thing the VAX asm does. */
5194 op (exp) = O_constant;
5200 as_warn (_("expression out of range: defaulting to 1"));
5204 else if (exp->exp.X_op == O_constant)
5209 if (offs (exp) < 1 || offs (exp) > 8)
5211 as_warn (_("expression out of range: defaulting to 1"));
5216 if (offs (exp) < 0 || offs (exp) > 7)
5220 if (offs (exp) < 0 || offs (exp) > 15)
5224 if (offs (exp) < 0 || offs (exp) > 32)
5228 if (offs (exp) < 0 || offs (exp) > 127)
5232 if (offs (exp) < -64 || offs (exp) > 63)
5236 if (offs (exp) < -128 || offs (exp) > 127)
5240 if (offs (exp) < 0 || offs (exp) > 4095)
5243 as_warn (_("expression out of range: defaulting to 0"));
5252 as_warn (_("expression out of range: defaulting to 1"));
5260 else if (exp->exp.X_op == O_big)
5262 if (offs (exp) <= 0 /* flonum. */
5263 && (ok == 90 /* no bignums */
5264 || (ok > 10 /* Small-int ranges including 0 ok. */
5265 /* If we have a flonum zero, a zero integer should
5266 do as well (e.g., in moveq). */
5267 && generic_floating_point_number.exponent == 0
5268 && generic_floating_point_number.low[0] == 0)))
5270 /* HACK! Turn it into a long. */
5271 LITTLENUM_TYPE words[6];
5273 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5274 op (exp) = O_constant;
5277 offs (exp) = words[1] | (words[0] << 16);
5281 op (exp) = O_constant;
5284 offs (exp) = (ok == 10) ? 1 : 0;
5285 as_warn (_("Can't deal with expression; defaulting to %ld"),
5291 if (ok >= 10 && ok <= 80)
5293 op (exp) = O_constant;
5296 offs (exp) = (ok == 10) ? 1 : 0;
5297 as_warn (_("Can't deal with expression; defaulting to %ld"),
5302 if (exp->size != SIZE_UNSPEC)
5310 if (!isbyte (offs (exp)))
5311 as_warn (_("expression doesn't fit in BYTE"));
5314 if (!isword (offs (exp)))
5315 as_warn (_("expression doesn't fit in WORD"));
5323 /* These are the back-ends for the various machine dependent pseudo-ops. */
5326 s_data1 (int ignore ATTRIBUTE_UNUSED)
5328 subseg_set (data_section, 1);
5329 demand_empty_rest_of_line ();
5333 s_data2 (int ignore ATTRIBUTE_UNUSED)
5335 subseg_set (data_section, 2);
5336 demand_empty_rest_of_line ();
5340 s_bss (int ignore ATTRIBUTE_UNUSED)
5342 /* We don't support putting frags in the BSS segment, we fake it
5343 by marking in_bss, then looking at s_skip for clues. */
5345 subseg_set (bss_section, 0);
5346 demand_empty_rest_of_line ();
5350 s_even (int ignore ATTRIBUTE_UNUSED)
5353 register long temp_fill;
5355 temp = 1; /* JF should be 2? */
5356 temp_fill = get_absolute_expression ();
5357 if (!need_pass_2) /* Never make frag if expect extra pass. */
5358 frag_align (temp, (int) temp_fill, 0);
5359 demand_empty_rest_of_line ();
5360 record_alignment (now_seg, temp);
5364 s_proc (int ignore ATTRIBUTE_UNUSED)
5366 demand_empty_rest_of_line ();
5369 /* Pseudo-ops handled for MRI compatibility. */
5371 /* This function returns non-zero if the argument is a conditional
5372 pseudo-op. This is called when checking whether a pending
5373 alignment is needed. */
5376 m68k_conditional_pseudoop (pseudo_typeS *pop)
5378 return (pop->poc_handler == s_mri_if
5379 || pop->poc_handler == s_mri_else);
5382 /* Handle an MRI style chip specification. */
5391 s = input_line_pointer;
5392 /* We can't use get_symbol_end since the processor names are not proper
5394 while (is_part_of_name (c = *input_line_pointer++))
5396 *--input_line_pointer = 0;
5397 for (i = 0; i < n_archs; i++)
5398 if (strcasecmp (s, archs[i].name) == 0)
5402 as_bad (_("%s: unrecognized processor name"), s);
5403 *input_line_pointer = c;
5404 ignore_rest_of_line ();
5407 *input_line_pointer = c;
5409 if (*input_line_pointer == '/')
5410 current_architecture = 0;
5412 current_architecture &= m68881 | m68851;
5413 current_architecture |= archs[i].arch;
5414 current_chip = archs[i].chip;
5416 while (*input_line_pointer == '/')
5418 ++input_line_pointer;
5419 s = input_line_pointer;
5420 /* We can't use get_symbol_end since the processor names are not
5422 while (is_part_of_name (c = *input_line_pointer++))
5424 *--input_line_pointer = 0;
5425 if (strcmp (s, "68881") == 0)
5426 current_architecture |= m68881;
5427 else if (strcmp (s, "68851") == 0)
5428 current_architecture |= m68851;
5429 *input_line_pointer = c;
5432 /* Update info about available control registers. */
5433 select_control_regs ();
5436 /* The MRI CHIP pseudo-op. */
5439 s_chip (int ignore ATTRIBUTE_UNUSED)
5445 stop = mri_comment_field (&stopc);
5448 mri_comment_end (stop, stopc);
5449 demand_empty_rest_of_line ();
5452 /* The MRI FOPT pseudo-op. */
5455 s_fopt (int ignore ATTRIBUTE_UNUSED)
5459 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5463 input_line_pointer += 3;
5464 temp = get_absolute_expression ();
5465 if (temp < 0 || temp > 7)
5466 as_bad (_("bad coprocessor id"));
5468 m68k_float_copnum = COP0 + temp;
5472 as_bad (_("unrecognized fopt option"));
5473 ignore_rest_of_line ();
5477 demand_empty_rest_of_line ();
5480 /* The structure used to handle the MRI OPT pseudo-op. */
5484 /* The name of the option. */
5487 /* If this is not NULL, just call this function. The first argument
5488 is the ARG field of this structure, the second argument is
5489 whether the option was negated. */
5490 void (*pfn) (int arg, int on);
5492 /* If this is not NULL, and the PFN field is NULL, set the variable
5493 this points to. Set it to the ARG field if the option was not
5494 negated, and the NOTARG field otherwise. */
5497 /* The value to pass to PFN or to assign to *PVAR. */
5500 /* The value to assign to *PVAR if the option is negated. If PFN is
5501 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5502 the option may not be negated. */
5506 /* The table used to handle the MRI OPT pseudo-op. */
5508 static void skip_to_comma (int, int);
5509 static void opt_nest (int, int);
5510 static void opt_chip (int, int);
5511 static void opt_list (int, int);
5512 static void opt_list_symbols (int, int);
5514 static const struct opt_action opt_table[] =
5516 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5518 /* We do relaxing, so there is little use for these options. */
5519 { "b", 0, 0, 0, 0 },
5520 { "brs", 0, 0, 0, 0 },
5521 { "brb", 0, 0, 0, 0 },
5522 { "brl", 0, 0, 0, 0 },
5523 { "brw", 0, 0, 0, 0 },
5525 { "c", 0, 0, 0, 0 },
5526 { "cex", 0, 0, 0, 0 },
5527 { "case", 0, &symbols_case_sensitive, 1, 0 },
5528 { "cl", 0, 0, 0, 0 },
5529 { "cre", 0, 0, 0, 0 },
5530 { "d", 0, &flag_keep_locals, 1, 0 },
5531 { "e", 0, 0, 0, 0 },
5532 { "f", 0, &flag_short_refs, 1, 0 },
5533 { "frs", 0, &flag_short_refs, 1, 0 },
5534 { "frl", 0, &flag_short_refs, 0, 1 },
5535 { "g", 0, 0, 0, 0 },
5536 { "i", 0, 0, 0, 0 },
5537 { "m", 0, 0, 0, 0 },
5538 { "mex", 0, 0, 0, 0 },
5539 { "mc", 0, 0, 0, 0 },
5540 { "md", 0, 0, 0, 0 },
5541 { "nest", opt_nest, 0, 0, 0 },
5542 { "next", skip_to_comma, 0, 0, 0 },
5543 { "o", 0, 0, 0, 0 },
5544 { "old", 0, 0, 0, 0 },
5545 { "op", skip_to_comma, 0, 0, 0 },
5546 { "pco", 0, 0, 0, 0 },
5547 { "p", opt_chip, 0, 0, 0 },
5548 { "pcr", 0, 0, 0, 0 },
5549 { "pcs", 0, 0, 0, 0 },
5550 { "r", 0, 0, 0, 0 },
5551 { "quick", 0, &m68k_quick, 1, 0 },
5552 { "rel32", 0, &m68k_rel32, 1, 0 },
5553 { "s", opt_list, 0, 0, 0 },
5554 { "t", opt_list_symbols, 0, 0, 0 },
5555 { "w", 0, &flag_no_warnings, 0, 1 },
5559 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5561 /* The MRI OPT pseudo-op. */
5564 s_opt (int ignore ATTRIBUTE_UNUSED)
5572 const struct opt_action *o;
5577 if (*input_line_pointer == '-')
5579 ++input_line_pointer;
5582 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5584 input_line_pointer += 2;
5588 s = input_line_pointer;
5589 c = get_symbol_end ();
5591 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5593 if (strcasecmp (s, o->name) == 0)
5597 /* Restore input_line_pointer now in case the option
5599 *input_line_pointer = c;
5600 (*o->pfn) (o->arg, t);
5602 else if (o->pvar != NULL)
5604 if (! t && o->arg == o->notarg)
5605 as_bad (_("option `%s' may not be negated"), s);
5606 *input_line_pointer = c;
5607 *o->pvar = t ? o->arg : o->notarg;
5610 *input_line_pointer = c;
5616 as_bad (_("option `%s' not recognized"), s);
5617 *input_line_pointer = c;
5620 while (*input_line_pointer++ == ',');
5622 /* Move back to terminating character. */
5623 --input_line_pointer;
5624 demand_empty_rest_of_line ();
5627 /* Skip ahead to a comma. This is used for OPT options which we do
5628 not support and which take arguments. */
5631 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5633 while (*input_line_pointer != ','
5634 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5635 ++input_line_pointer;
5638 /* Handle the OPT NEST=depth option. */
5641 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5643 if (*input_line_pointer != '=')
5645 as_bad (_("bad format of OPT NEST=depth"));
5649 ++input_line_pointer;
5650 max_macro_nest = get_absolute_expression ();
5653 /* Handle the OPT P=chip option. */
5656 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5658 if (*input_line_pointer != '=')
5660 /* This is just OPT P, which we do not support. */
5664 ++input_line_pointer;
5668 /* Handle the OPT S option. */
5671 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5676 /* Handle the OPT T option. */
5679 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5682 listing |= LISTING_SYMBOLS;
5684 listing &= ~LISTING_SYMBOLS;
5687 /* Handle the MRI REG pseudo-op. */
5690 s_reg (int ignore ATTRIBUTE_UNUSED)
5699 if (line_label == NULL)
5701 as_bad (_("missing label"));
5702 ignore_rest_of_line ();
5707 stop = mri_comment_field (&stopc);
5711 s = input_line_pointer;
5712 while (ISALNUM (*input_line_pointer)
5713 #ifdef REGISTER_PREFIX
5714 || *input_line_pointer == REGISTER_PREFIX
5716 || *input_line_pointer == '/'
5717 || *input_line_pointer == '-')
5718 ++input_line_pointer;
5719 c = *input_line_pointer;
5720 *input_line_pointer = '\0';
5722 if (m68k_ip_op (s, &rop) != 0)
5724 if (rop.error == NULL)
5725 as_bad (_("bad register list"));
5727 as_bad (_("bad register list: %s"), rop.error);
5728 *input_line_pointer = c;
5729 ignore_rest_of_line ();
5733 *input_line_pointer = c;
5735 if (rop.mode == REGLST)
5737 else if (rop.mode == DREG)
5738 mask = 1 << (rop.reg - DATA0);
5739 else if (rop.mode == AREG)
5740 mask = 1 << (rop.reg - ADDR0 + 8);
5741 else if (rop.mode == FPREG)
5742 mask = 1 << (rop.reg - FP0 + 16);
5743 else if (rop.mode == CONTROL
5746 else if (rop.mode == CONTROL
5749 else if (rop.mode == CONTROL
5754 as_bad (_("bad register list"));
5755 ignore_rest_of_line ();
5759 S_SET_SEGMENT (line_label, reg_section);
5760 S_SET_VALUE (line_label, ~mask);
5761 symbol_set_frag (line_label, &zero_address_frag);
5764 mri_comment_end (stop, stopc);
5766 demand_empty_rest_of_line ();
5769 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5773 struct save_opts *next;
5775 int symbols_case_sensitive;
5784 /* FIXME: We don't save OPT S. */
5787 /* This variable holds the stack of saved options. */
5789 static struct save_opts *save_stack;
5791 /* The MRI SAVE pseudo-op. */
5794 s_save (int ignore ATTRIBUTE_UNUSED)
5796 struct save_opts *s;
5798 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5799 s->abspcadd = m68k_abspcadd;
5800 s->symbols_case_sensitive = symbols_case_sensitive;
5801 s->keep_locals = flag_keep_locals;
5802 s->short_refs = flag_short_refs;
5803 s->architecture = current_architecture;
5804 s->chip = current_chip;
5805 s->quick = m68k_quick;
5806 s->rel32 = m68k_rel32;
5807 s->listing = listing;
5808 s->no_warnings = flag_no_warnings;
5810 s->next = save_stack;
5813 demand_empty_rest_of_line ();
5816 /* The MRI RESTORE pseudo-op. */
5819 s_restore (int ignore ATTRIBUTE_UNUSED)
5821 struct save_opts *s;
5823 if (save_stack == NULL)
5825 as_bad (_("restore without save"));
5826 ignore_rest_of_line ();
5831 save_stack = s->next;
5833 m68k_abspcadd = s->abspcadd;
5834 symbols_case_sensitive = s->symbols_case_sensitive;
5835 flag_keep_locals = s->keep_locals;
5836 flag_short_refs = s->short_refs;
5837 current_architecture = s->architecture;
5838 current_chip = s->chip;
5839 m68k_quick = s->quick;
5840 m68k_rel32 = s->rel32;
5841 listing = s->listing;
5842 flag_no_warnings = s->no_warnings;
5846 demand_empty_rest_of_line ();
5849 /* Types of MRI structured control directives. */
5851 enum mri_control_type
5859 /* This structure is used to stack the MRI structured control
5862 struct mri_control_info
5864 /* The directive within which this one is enclosed. */
5865 struct mri_control_info *outer;
5867 /* The type of directive. */
5868 enum mri_control_type type;
5870 /* Whether an ELSE has been in an IF. */
5873 /* The add or sub statement at the end of a FOR. */
5876 /* The label of the top of a FOR or REPEAT loop. */
5879 /* The label to jump to for the next iteration, or the else
5880 expression of a conditional. */
5883 /* The label to jump to to break out of the loop, or the label past
5884 the end of a conditional. */
5888 /* The stack of MRI structured control directives. */
5890 static struct mri_control_info *mri_control_stack;
5892 /* The current MRI structured control directive index number, used to
5893 generate label names. */
5895 static int mri_control_index;
5897 /* Assemble an instruction for an MRI structured control directive. */
5900 mri_assemble (char *str)
5904 /* md_assemble expects the opcode to be in lower case. */
5905 for (s = str; *s != ' ' && *s != '\0'; s++)
5911 /* Generate a new MRI label structured control directive label name. */
5914 mri_control_label (void)
5918 n = (char *) xmalloc (20);
5919 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5920 ++mri_control_index;
5924 /* Create a new MRI structured control directive. */
5926 static struct mri_control_info *
5927 push_mri_control (enum mri_control_type type)
5929 struct mri_control_info *n;
5931 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5935 if (type == mri_if || type == mri_while)
5938 n->top = mri_control_label ();
5939 n->next = mri_control_label ();
5940 n->bottom = mri_control_label ();
5942 n->outer = mri_control_stack;
5943 mri_control_stack = n;
5948 /* Pop off the stack of MRI structured control directives. */
5951 pop_mri_control (void)
5953 struct mri_control_info *n;
5955 n = mri_control_stack;
5956 mri_control_stack = n->outer;
5964 /* Recognize a condition code in an MRI structured control expression. */
5967 parse_mri_condition (int *pcc)
5971 know (*input_line_pointer == '<');
5973 ++input_line_pointer;
5974 c1 = *input_line_pointer++;
5975 c2 = *input_line_pointer++;
5977 if (*input_line_pointer != '>')
5979 as_bad (_("syntax error in structured control directive"));
5983 ++input_line_pointer;
5989 *pcc = (c1 << 8) | c2;
5994 /* Parse a single operand in an MRI structured control expression. */
5997 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5998 char **rightstart, char **rightstop)
6010 if (*input_line_pointer == '<')
6012 /* It's just a condition code. */
6013 return parse_mri_condition (pcc);
6016 /* Look ahead for the condition code. */
6017 for (s = input_line_pointer; *s != '\0'; ++s)
6019 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6024 as_bad (_("missing condition code in structured control directive"));
6028 *leftstart = input_line_pointer;
6030 if (*leftstop > *leftstart
6031 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6034 input_line_pointer = s;
6035 if (! parse_mri_condition (pcc))
6038 /* Look ahead for AND or OR or end of line. */
6039 for (s = input_line_pointer; *s != '\0'; ++s)
6041 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6042 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6044 if ((s == input_line_pointer
6047 && ((strncasecmp (s, "AND", 3) == 0
6048 && (s[3] == '.' || ! is_part_of_name (s[3])))
6049 || (strncasecmp (s, "OR", 2) == 0
6050 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6054 *rightstart = input_line_pointer;
6056 if (*rightstop > *rightstart
6057 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6060 input_line_pointer = s;
6065 #define MCC(b1, b2) (((b1) << 8) | (b2))
6067 /* Swap the sense of a condition. This changes the condition so that
6068 it generates the same result when the operands are swapped. */
6071 swap_mri_condition (int cc)
6075 case MCC ('h', 'i'): return MCC ('c', 's');
6076 case MCC ('l', 's'): return MCC ('c', 'c');
6077 /* <HS> is an alias for <CC>. */
6078 case MCC ('h', 's'):
6079 case MCC ('c', 'c'): return MCC ('l', 's');
6080 /* <LO> is an alias for <CS>. */
6081 case MCC ('l', 'o'):
6082 case MCC ('c', 's'): return MCC ('h', 'i');
6083 case MCC ('p', 'l'): return MCC ('m', 'i');
6084 case MCC ('m', 'i'): return MCC ('p', 'l');
6085 case MCC ('g', 'e'): return MCC ('l', 'e');
6086 case MCC ('l', 't'): return MCC ('g', 't');
6087 case MCC ('g', 't'): return MCC ('l', 't');
6088 case MCC ('l', 'e'): return MCC ('g', 'e');
6089 /* Issue a warning for conditions we can not swap. */
6090 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6091 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6092 case MCC ('v', 'c'):
6093 case MCC ('v', 's'):
6095 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6096 (char) (cc >> 8), (char) (cc));
6102 /* Reverse the sense of a condition. */
6105 reverse_mri_condition (int cc)
6109 case MCC ('h', 'i'): return MCC ('l', 's');
6110 case MCC ('l', 's'): return MCC ('h', 'i');
6111 /* <HS> is an alias for <CC> */
6112 case MCC ('h', 's'): return MCC ('l', 'o');
6113 case MCC ('c', 'c'): return MCC ('c', 's');
6114 /* <LO> is an alias for <CS> */
6115 case MCC ('l', 'o'): return MCC ('h', 's');
6116 case MCC ('c', 's'): return MCC ('c', 'c');
6117 case MCC ('n', 'e'): return MCC ('e', 'q');
6118 case MCC ('e', 'q'): return MCC ('n', 'e');
6119 case MCC ('v', 'c'): return MCC ('v', 's');
6120 case MCC ('v', 's'): return MCC ('v', 'c');
6121 case MCC ('p', 'l'): return MCC ('m', 'i');
6122 case MCC ('m', 'i'): return MCC ('p', 'l');
6123 case MCC ('g', 'e'): return MCC ('l', 't');
6124 case MCC ('l', 't'): return MCC ('g', 'e');
6125 case MCC ('g', 't'): return MCC ('l', 'e');
6126 case MCC ('l', 'e'): return MCC ('g', 't');
6131 /* Build an MRI structured control expression. This generates test
6132 and branch instructions. It goes to TRUELAB if the condition is
6133 true, and to FALSELAB if the condition is false. Exactly one of
6134 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6135 is the size qualifier for the expression. EXTENT is the size to
6136 use for the branch. */
6139 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6140 char *rightstart, char *rightstop,
6141 const char *truelab, const char *falselab,
6147 if (leftstart != NULL)
6149 struct m68k_op leftop, rightop;
6152 /* Swap the compare operands, if necessary, to produce a legal
6153 m68k compare instruction. Comparing a register operand with
6154 a non-register operand requires the register to be on the
6155 right (cmp, cmpa). Comparing an immediate value with
6156 anything requires the immediate value to be on the left
6161 (void) m68k_ip_op (leftstart, &leftop);
6166 (void) m68k_ip_op (rightstart, &rightop);
6169 if (rightop.mode == IMMED
6170 || ((leftop.mode == DREG || leftop.mode == AREG)
6171 && (rightop.mode != DREG && rightop.mode != AREG)))
6175 /* Correct conditional handling:
6176 if #1 <lt> d0 then ;means if (1 < d0)
6182 cmp #1,d0 if we do *not* swap the operands
6183 bgt true we need the swapped condition!
6190 leftstart = rightstart;
6193 leftstop = rightstop;
6198 cc = swap_mri_condition (cc);
6202 if (truelab == NULL)
6204 cc = reverse_mri_condition (cc);
6208 if (leftstart != NULL)
6210 buf = (char *) xmalloc (20
6211 + (leftstop - leftstart)
6212 + (rightstop - rightstart));
6218 *s++ = TOLOWER (qual);
6220 memcpy (s, leftstart, leftstop - leftstart);
6221 s += leftstop - leftstart;
6223 memcpy (s, rightstart, rightstop - rightstart);
6224 s += rightstop - rightstart;
6230 buf = (char *) xmalloc (20 + strlen (truelab));
6236 *s++ = TOLOWER (extent);
6238 strcpy (s, truelab);
6243 /* Parse an MRI structured control expression. This generates test
6244 and branch instructions. STOP is where the expression ends. It
6245 goes to TRUELAB if the condition is true, and to FALSELAB if the
6246 condition is false. Exactly one of TRUELAB and FALSELAB will be
6247 NULL, meaning to fall through. QUAL is the size qualifier for the
6248 expression. EXTENT is the size to use for the branch. */
6251 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6252 const char *falselab, int extent)
6264 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6265 &rightstart, &rightstop))
6271 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6275 if (falselab != NULL)
6278 flab = mri_control_label ();
6280 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6281 rightstop, (const char *) NULL, flab, extent);
6283 input_line_pointer += 3;
6284 if (*input_line_pointer != '.'
6285 || input_line_pointer[1] == '\0')
6289 qual = input_line_pointer[1];
6290 input_line_pointer += 2;
6293 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6294 &rightstart, &rightstop))
6300 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6301 rightstop, truelab, falselab, extent);
6303 if (falselab == NULL)
6306 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6310 if (truelab != NULL)
6313 tlab = mri_control_label ();
6315 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6316 rightstop, tlab, (const char *) NULL, extent);
6318 input_line_pointer += 2;
6319 if (*input_line_pointer != '.'
6320 || input_line_pointer[1] == '\0')
6324 qual = input_line_pointer[1];
6325 input_line_pointer += 2;
6328 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6329 &rightstart, &rightstop))
6335 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6336 rightstop, truelab, falselab, extent);
6338 if (truelab == NULL)
6343 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6344 rightstop, truelab, falselab, extent);
6348 if (input_line_pointer != stop)
6349 as_bad (_("syntax error in structured control directive"));
6352 /* Handle the MRI IF pseudo-op. This may be a structured control
6353 directive, or it may be a regular assembler conditional, depending
6361 struct mri_control_info *n;
6363 /* A structured control directive must end with THEN with an
6364 optional qualifier. */
6365 s = input_line_pointer;
6366 /* We only accept '*' as introduction of comments if preceded by white space
6367 or at first column of a line (I think this can't actually happen here?)
6368 This is important when assembling:
6369 if d0 <ne> 12(a0,d0*2) then
6370 if d0 <ne> #CONST*20 then. */
6371 while (! (is_end_of_line[(unsigned char) *s]
6374 && (s == input_line_pointer
6376 || *(s-1) == '\t'))))
6379 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6382 if (s - input_line_pointer > 1
6386 if (s - input_line_pointer < 3
6387 || strncasecmp (s - 3, "THEN", 4) != 0)
6391 as_bad (_("missing then"));
6392 ignore_rest_of_line ();
6396 /* It's a conditional. */
6401 /* Since this might be a conditional if, this pseudo-op will be
6402 called even if we are supported to be ignoring input. Double
6403 check now. Clobber *input_line_pointer so that ignore_input
6404 thinks that this is not a special pseudo-op. */
6405 c = *input_line_pointer;
6406 *input_line_pointer = 0;
6407 if (ignore_input ())
6409 *input_line_pointer = c;
6410 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6411 ++input_line_pointer;
6412 demand_empty_rest_of_line ();
6415 *input_line_pointer = c;
6417 n = push_mri_control (mri_if);
6419 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6420 n->next, s[1] == '.' ? s[2] : '\0');
6423 input_line_pointer = s + 3;
6425 input_line_pointer = s + 1;
6429 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6430 ++input_line_pointer;
6433 demand_empty_rest_of_line ();
6436 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6437 structured IF, associate the ELSE with the IF. Otherwise, assume
6438 it is a conditional else. */
6441 s_mri_else (int qual)
6448 && (mri_control_stack == NULL
6449 || mri_control_stack->type != mri_if
6450 || mri_control_stack->else_seen))
6456 c = *input_line_pointer;
6457 *input_line_pointer = 0;
6458 if (ignore_input ())
6460 *input_line_pointer = c;
6461 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6462 ++input_line_pointer;
6463 demand_empty_rest_of_line ();
6466 *input_line_pointer = c;
6468 if (mri_control_stack == NULL
6469 || mri_control_stack->type != mri_if
6470 || mri_control_stack->else_seen)
6472 as_bad (_("else without matching if"));
6473 ignore_rest_of_line ();
6477 mri_control_stack->else_seen = 1;
6479 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6480 q[0] = TOLOWER (qual);
6482 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6486 colon (mri_control_stack->next);
6490 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6491 ++input_line_pointer;
6494 demand_empty_rest_of_line ();
6497 /* Handle the MRI ENDI pseudo-op. */
6500 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6502 if (mri_control_stack == NULL
6503 || mri_control_stack->type != mri_if)
6505 as_bad (_("endi without matching if"));
6506 ignore_rest_of_line ();
6510 /* ignore_input will not return true for ENDI, so we don't need to
6511 worry about checking it again here. */
6513 if (! mri_control_stack->else_seen)
6514 colon (mri_control_stack->next);
6515 colon (mri_control_stack->bottom);
6521 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6522 ++input_line_pointer;
6525 demand_empty_rest_of_line ();
6528 /* Handle the MRI BREAK pseudo-op. */
6531 s_mri_break (int extent)
6533 struct mri_control_info *n;
6537 n = mri_control_stack;
6539 && n->type != mri_for
6540 && n->type != mri_repeat
6541 && n->type != mri_while)
6545 as_bad (_("break outside of structured loop"));
6546 ignore_rest_of_line ();
6550 buf = (char *) xmalloc (20 + strlen (n->bottom));
6551 ex[0] = TOLOWER (extent);
6553 sprintf (buf, "bra%s %s", ex, n->bottom);
6559 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6560 ++input_line_pointer;
6563 demand_empty_rest_of_line ();
6566 /* Handle the MRI NEXT pseudo-op. */
6569 s_mri_next (int extent)
6571 struct mri_control_info *n;
6575 n = mri_control_stack;
6577 && n->type != mri_for
6578 && n->type != mri_repeat
6579 && n->type != mri_while)
6583 as_bad (_("next outside of structured loop"));
6584 ignore_rest_of_line ();
6588 buf = (char *) xmalloc (20 + strlen (n->next));
6589 ex[0] = TOLOWER (extent);
6591 sprintf (buf, "bra%s %s", ex, n->next);
6597 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6598 ++input_line_pointer;
6601 demand_empty_rest_of_line ();
6604 /* Handle the MRI FOR pseudo-op. */
6607 s_mri_for (int qual)
6609 const char *varstart, *varstop;
6610 const char *initstart, *initstop;
6611 const char *endstart, *endstop;
6612 const char *bystart, *bystop;
6616 struct mri_control_info *n;
6622 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6626 varstart = input_line_pointer;
6628 /* Look for the '='. */
6629 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6630 && *input_line_pointer != '=')
6631 ++input_line_pointer;
6632 if (*input_line_pointer != '=')
6634 as_bad (_("missing ="));
6635 ignore_rest_of_line ();
6639 varstop = input_line_pointer;
6640 if (varstop > varstart
6641 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6644 ++input_line_pointer;
6646 initstart = input_line_pointer;
6648 /* Look for TO or DOWNTO. */
6651 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6653 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6654 && ! is_part_of_name (input_line_pointer[2]))
6656 initstop = input_line_pointer;
6657 input_line_pointer += 2;
6660 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6661 && ! is_part_of_name (input_line_pointer[6]))
6663 initstop = input_line_pointer;
6665 input_line_pointer += 6;
6668 ++input_line_pointer;
6670 if (initstop == NULL)
6672 as_bad (_("missing to or downto"));
6673 ignore_rest_of_line ();
6676 if (initstop > initstart
6677 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6681 endstart = input_line_pointer;
6683 /* Look for BY or DO. */
6686 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6688 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6689 && ! is_part_of_name (input_line_pointer[2]))
6691 endstop = input_line_pointer;
6693 input_line_pointer += 2;
6696 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6697 && (input_line_pointer[2] == '.'
6698 || ! is_part_of_name (input_line_pointer[2])))
6700 endstop = input_line_pointer;
6701 input_line_pointer += 2;
6704 ++input_line_pointer;
6706 if (endstop == NULL)
6708 as_bad (_("missing do"));
6709 ignore_rest_of_line ();
6712 if (endstop > endstart
6713 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6719 bystop = bystart + 2;
6724 bystart = input_line_pointer;
6728 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6730 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6731 && (input_line_pointer[2] == '.'
6732 || ! is_part_of_name (input_line_pointer[2])))
6734 bystop = input_line_pointer;
6735 input_line_pointer += 2;
6738 ++input_line_pointer;
6742 as_bad (_("missing do"));
6743 ignore_rest_of_line ();
6746 if (bystop > bystart
6747 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6751 if (*input_line_pointer != '.')
6755 extent = input_line_pointer[1];
6756 input_line_pointer += 2;
6759 /* We have fully parsed the FOR operands. Now build the loop. */
6760 n = push_mri_control (mri_for);
6762 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6764 /* Move init,var. */
6771 *s++ = TOLOWER (qual);
6773 memcpy (s, initstart, initstop - initstart);
6774 s += initstop - initstart;
6776 memcpy (s, varstart, varstop - varstart);
6777 s += varstop - varstart;
6789 *s++ = TOLOWER (qual);
6791 memcpy (s, endstart, endstop - endstart);
6792 s += endstop - endstart;
6794 memcpy (s, varstart, varstop - varstart);
6795 s += varstop - varstart;
6800 ex[0] = TOLOWER (extent);
6803 sprintf (buf, "blt%s %s", ex, n->bottom);
6805 sprintf (buf, "bgt%s %s", ex, n->bottom);
6808 /* Put together the add or sub instruction used by ENDF. */
6816 *s++ = TOLOWER (qual);
6818 memcpy (s, bystart, bystop - bystart);
6819 s += bystop - bystart;
6821 memcpy (s, varstart, varstop - varstart);
6822 s += varstop - varstart;
6828 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6829 ++input_line_pointer;
6832 demand_empty_rest_of_line ();
6835 /* Handle the MRI ENDF pseudo-op. */
6838 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6840 if (mri_control_stack == NULL
6841 || mri_control_stack->type != mri_for)
6843 as_bad (_("endf without for"));
6844 ignore_rest_of_line ();
6848 colon (mri_control_stack->next);
6850 mri_assemble (mri_control_stack->incr);
6852 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6853 mri_assemble (mri_control_stack->incr);
6855 free (mri_control_stack->incr);
6857 colon (mri_control_stack->bottom);
6863 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6864 ++input_line_pointer;
6867 demand_empty_rest_of_line ();
6870 /* Handle the MRI REPEAT pseudo-op. */
6873 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6875 struct mri_control_info *n;
6877 n = push_mri_control (mri_repeat);
6881 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6882 ++input_line_pointer;
6884 demand_empty_rest_of_line ();
6887 /* Handle the MRI UNTIL pseudo-op. */
6890 s_mri_until (int qual)
6894 if (mri_control_stack == NULL
6895 || mri_control_stack->type != mri_repeat)
6897 as_bad (_("until without repeat"));
6898 ignore_rest_of_line ();
6902 colon (mri_control_stack->next);
6904 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6907 parse_mri_control_expression (s, qual, (const char *) NULL,
6908 mri_control_stack->top, '\0');
6910 colon (mri_control_stack->bottom);
6912 input_line_pointer = s;
6918 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6919 ++input_line_pointer;
6922 demand_empty_rest_of_line ();
6925 /* Handle the MRI WHILE pseudo-op. */
6928 s_mri_while (int qual)
6932 struct mri_control_info *n;
6934 s = input_line_pointer;
6935 /* We only accept '*' as introduction of comments if preceded by white space
6936 or at first column of a line (I think this can't actually happen here?)
6937 This is important when assembling:
6938 while d0 <ne> 12(a0,d0*2) do
6939 while d0 <ne> #CONST*20 do. */
6940 while (! (is_end_of_line[(unsigned char) *s]
6943 && (s == input_line_pointer
6945 || *(s-1) == '\t'))))
6948 while (*s == ' ' || *s == '\t')
6950 if (s - input_line_pointer > 1
6953 if (s - input_line_pointer < 2
6954 || strncasecmp (s - 1, "DO", 2) != 0)
6956 as_bad (_("missing do"));
6957 ignore_rest_of_line ();
6961 n = push_mri_control (mri_while);
6965 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6966 s[1] == '.' ? s[2] : '\0');
6968 input_line_pointer = s + 1;
6969 if (*input_line_pointer == '.')
6970 input_line_pointer += 2;
6974 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6975 ++input_line_pointer;
6978 demand_empty_rest_of_line ();
6981 /* Handle the MRI ENDW pseudo-op. */
6984 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6988 if (mri_control_stack == NULL
6989 || mri_control_stack->type != mri_while)
6991 as_bad (_("endw without while"));
6992 ignore_rest_of_line ();
6996 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6997 sprintf (buf, "bra %s", mri_control_stack->next);
7001 colon (mri_control_stack->bottom);
7007 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7008 ++input_line_pointer;
7011 demand_empty_rest_of_line ();
7015 Invocation line includes a switch not recognized by the base assembler.
7016 See if it's a processor-specific option. These are:
7018 -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
7019 -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
7020 Select the architecture. Instructions or features not
7021 supported by the selected architecture cause fatal
7022 errors. More than one may be specified. The default is
7023 -m68020 -m68851 -m68881. Note that -m68008 is a synonym
7024 for -m68000, and -m68882 is a synonym for -m68881.
7025 -[A]m[c]no-68851, -[A]m[c]no-68881
7026 Don't accept 688?1 instructions. (The "c" is kind of silly,
7027 so don't use or document it, but that's the way the parsing
7031 -k Indicates PIC. (Sun 3 only.)
7033 Never turn PC-relative branches into absolute jumps.
7035 Permit `|' to be used in expressions. */
7038 const char *md_shortopts = "lSA:m:kQ:V";
7040 const char *md_shortopts = "lSA:m:k";
7043 struct option md_longopts[] = {
7044 #define OPTION_PIC (OPTION_MD_BASE)
7045 {"pic", no_argument, NULL, OPTION_PIC},
7046 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7047 {"register-prefix-optional", no_argument, NULL,
7048 OPTION_REGISTER_PREFIX_OPTIONAL},
7049 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7050 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7051 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7052 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7053 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7054 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7055 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7056 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7057 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7058 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7059 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7060 {"pcrel", no_argument, NULL, OPTION_PCREL},
7061 {NULL, no_argument, NULL, 0}
7063 size_t md_longopts_size = sizeof (md_longopts);
7066 md_parse_option (int c, char *arg)
7070 case 'l': /* -l means keep external to 2 bit offset
7071 rather than 16 bit one. */
7072 flag_short_refs = 1;
7075 case 'S': /* -S means that jbsr's always turn into
7077 flag_long_jumps = 1;
7080 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7081 branches into absolute jumps. */
7082 flag_keep_pcrel = 1;
7088 /* Intentional fall-through. */
7091 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7100 if (arg[0] == 'c' && arg[1] == '6')
7103 for (i = 0; i < n_archs; i++)
7104 if (!strcmp (arg, archs[i].name))
7109 arch = archs[i].arch;
7112 else if (arch == m68851)
7121 if (arg[0] == 'c' && arg[1] == '6')
7124 for (i = 0; i < n_archs; i++)
7125 if (!strcmp (arg, archs[i].name))
7127 unsigned long arch = archs[i].arch;
7129 if (cpu_of_arch (arch))
7130 /* It's a cpu spec. */
7132 current_architecture &= ~m68000up;
7133 current_architecture |= arch;
7134 current_chip = archs[i].chip;
7136 else if (arch == m68881)
7138 current_architecture |= m68881;
7141 else if (arch == m68851)
7143 current_architecture |= m68851;
7153 as_bad (_("unrecognized architecture specification `%s'"), arg);
7162 break; /* -pic, Position Independent Code. */
7164 case OPTION_REGISTER_PREFIX_OPTIONAL:
7165 flag_reg_prefix_optional = 1;
7166 reg_prefix_optional_seen = 1;
7169 /* -V: SVR4 argument to print version ID. */
7171 print_version_id ();
7174 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7175 should be emitted or not. FIXME: Not implemented. */
7179 case OPTION_BITWISE_OR:
7184 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7186 for (s = m68k_comment_chars; *s != '\0'; s++)
7190 m68k_comment_chars = n;
7194 case OPTION_BASE_SIZE_DEFAULT_16:
7195 m68k_index_width_default = SIZE_WORD;
7198 case OPTION_BASE_SIZE_DEFAULT_32:
7199 m68k_index_width_default = SIZE_LONG;
7202 case OPTION_DISP_SIZE_DEFAULT_16:
7204 m68k_rel32_from_cmdline = 1;
7207 case OPTION_DISP_SIZE_DEFAULT_32:
7209 m68k_rel32_from_cmdline = 1;
7220 md_show_usage (FILE *stream)
7222 const char *default_cpu = TARGET_CPU;
7224 unsigned int default_arch;
7226 /* Get the canonical name for the default target CPU. */
7227 if (*default_cpu == 'm')
7229 for (i = 0; i < n_archs; i++)
7231 if (strcasecmp (default_cpu, archs[i].name) == 0)
7233 default_arch = archs[i].arch;
7234 for (i = 0; i < n_archs; i++)
7236 if (archs[i].arch == default_arch
7239 default_cpu = archs[i].name;
7246 fprintf (stream, _("\
7248 -l use 1 word for refs to undefined symbols [default 2]\n\
7249 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7250 -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
7251 -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
7252 -m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
7253 specify variant of 680X0 architecture [default %s]\n\
7254 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7255 target has/lacks floating-point coprocessor\n\
7256 [default yes for 68020, 68030, and cpu32]\n"),
7258 fprintf (stream, _("\
7259 -m68851 | -mno-68851\n\
7260 target has/lacks memory-management unit coprocessor\n\
7261 [default yes for 68020 and up]\n\
7262 -pic, -k generate position independent code\n\
7263 -S turn jbsr into jsr\n\
7264 --pcrel never turn PC-relative branches into absolute jumps\n\
7265 --register-prefix-optional\n\
7266 recognize register names without prefix character\n\
7267 --bitwise-or do not treat `|' as a comment character\n"));
7268 fprintf (stream, _("\
7269 --base-size-default-16 base reg without size is 16 bits\n\
7270 --base-size-default-32 base reg without size is 32 bits (default)\n\
7271 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7272 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7277 /* TEST2: Test md_assemble() */
7278 /* Warning, this routine probably doesn't work anymore. */
7282 struct m68k_it the_ins;
7290 if (!gets (buf) || !*buf)
7292 if (buf[0] == '|' || buf[1] == '.')
7294 for (cp = buf; *cp; cp++)
7299 memset (&the_ins, '\0', sizeof (the_ins));
7300 m68k_ip (&the_ins, buf);
7303 printf (_("Error %s in %s\n"), the_ins.error, buf);
7307 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7308 for (n = 0; n < the_ins.numo; n++)
7309 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7311 print_the_insn (&the_ins.opcode[0], stdout);
7312 (void) putchar ('\n');
7314 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7316 if (the_ins.operands[n].error)
7318 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7321 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7322 the_ins.operands[n].reg);
7323 if (the_ins.operands[n].b_const)
7324 printf ("Constant: '%.*s', ",
7325 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7326 the_ins.operands[n].b_const);
7327 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7328 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7329 if (the_ins.operands[n].b_iadd)
7330 printf ("Iadd: '%.*s',",
7331 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7332 the_ins.operands[n].b_iadd);
7341 is_label (char *str)
7345 while (*str && *str != ' ')
7347 if (str[-1] == ':' || str[1] == '=')
7354 /* Possible states for relaxation:
7356 0 0 branch offset byte (bra, etc)
7360 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7364 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7371 /* We have no need to default values of symbols. */
7374 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7379 /* Round up a section size to the appropriate boundary. */
7381 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7384 #ifdef BFD_ASSEMBLER
7385 /* For a.out, force the section size to be aligned. If we don't do
7386 this, BFD will align it for us, but it will not write out the
7387 final bytes of the section. This may be a bug in BFD, but it is
7388 easier to fix it here since that is how the other a.out targets
7392 align = bfd_get_section_alignment (stdoutput, segment);
7393 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7400 /* Exactly what point is a PC-relative offset relative TO?
7401 On the 68k, it is relative to the address of the first extension
7402 word. The difference between the addresses of the offset and the
7403 first extension word is stored in fx_pcrel_adjust. */
7405 md_pcrel_from (fixS *fixP)
7409 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7410 sign extend the value here. */
7411 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7414 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7417 #ifndef BFD_ASSEMBLER
7421 tc_coff_symbol_emit_hook (symbolS *ignore ATTRIBUTE_UNUSED)
7426 tc_coff_sizemachdep (fragS *frag)
7428 switch (frag->fr_subtype & 0x3)
7447 m68k_elf_final_processing (void)
7449 /* Set file-specific flags if this is a cpu32 processor. */
7450 if (cpu_of_arch (current_architecture) & cpu32)
7451 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7452 else if ((cpu_of_arch (current_architecture) & m68000up)
7453 && !(cpu_of_arch (current_architecture) & m68020up))
7454 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
7459 tc_m68k_regname_to_dw2regnum (const char *regname)
7461 unsigned int regnum;
7462 static const char *const regnames[] =
7464 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7465 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7466 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7470 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7471 if (strcmp (regname, regnames[regnum]) == 0)
7478 tc_m68k_frame_initial_instructions (void)
7480 static int sp_regno = -1;
7483 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7485 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7486 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);