1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
30 /* This array holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful */
32 #if defined (OBJ_ELF) || defined (TE_DELTA)
33 const char comment_chars[] = "|#";
35 const char comment_chars[] = "|";
38 /* This array holds the chars that only start a comment at the beginning of
39 a line. If the line seems to have the form '# 123 filename'
40 .line and .file directives will appear in the pre-processed output */
41 /* Note that input_file.c hand checks for '#' at the beginning of the
42 first line of the input file. This is because the compiler outputs
43 #NO_APP at the beginning of its output. */
44 /* Also note that comments like this one will always work. */
45 const char line_comment_chars[] = "#";
47 const char line_separator_chars[] = "";
49 /* Chars that can be used to separate mant from exp in floating point nums */
50 CONST char EXP_CHARS[] = "eE";
52 /* Chars that mean this number is a floating point constant, as
53 in "0f12.456" or "0d1.2345e12". */
55 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
57 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
58 changed in read.c . Ideally it shouldn't have to know about it at all,
59 but nothing is ideal around here. */
61 const int md_reloc_size = 8; /* Size of relocation record */
63 /* Are we trying to generate PIC code? If so, absolute references
64 ought to be made into linkage table references or pc-relative
68 static int flag_short_refs; /* -l option */
69 static int flag_long_jumps; /* -S option */
71 #ifdef REGISTER_PREFIX_OPTIONAL
72 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
74 int flag_reg_prefix_optional;
77 /* The floating point coprocessor to use by default. */
78 static enum m68k_register m68k_float_copnum = COP1;
80 /* If this is non-zero, then references to number(%pc) will be taken
81 to refer to number, rather than to %pc + number. */
82 static int m68k_abspcadd;
84 /* If this is non-zero, then the quick forms of the move, add, and sub
85 instructions are used when possible. */
86 static int m68k_quick = 1;
88 /* If this is non-zero, then if the size is not specified for a base
89 or outer displacement, the assembler assumes that the size should
91 static int m68k_rel32 = 1;
93 /* Its an arbitrary name: This means I don't approve of it */
94 /* See flames below */
95 static struct obstack robyn;
97 #define TAB(x,y) (((x)<<2)+(y))
98 #define TABTYPE(xy) ((xy) >> 2)
104 /* Case `g' except when BCC68000 is applicable. */
106 /* Coprocessor branches. */
108 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
109 supported on all cpus. Widens to 32-bit absolute. */
111 /* For inserting an extra jmp instruction with long offset on 68000,
112 for expanding conditional branches. (Not bsr or bra.) Since the
113 68000 doesn't support 32-bit displacements for conditional
114 branches, we fake it by reversing the condition and branching
115 around a jmp with an absolute long operand. */
117 /* For the DBcc "instructions". If the displacement requires 32 bits,
118 the branch-around-a-jump game is played here too. */
120 /* Not currently used? */
122 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
128 const char *m_operands;
129 unsigned long m_opcode;
133 struct m68k_incant *m_next;
136 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
137 #define gettwo(x) (((x)->m_opcode)&0xffff)
139 static const enum m68k_register m68000_control_regs[] = { 0 };
140 static const enum m68k_register m68010_control_regs[] = {
144 static const enum m68k_register m68020_control_regs[] = {
145 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
148 static const enum m68k_register m68040_control_regs[] = {
149 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
150 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
153 static const enum m68k_register m68060_control_regs[] = {
154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
155 USP, VBR, URP, SRP, PCR,
158 #define cpu32_control_regs m68010_control_regs
160 static const enum m68k_register *control_regs;
162 /* internal form of a 68020 instruction */
166 const char *args; /* list of opcode info */
169 int numo; /* Number of shorts in opcode */
172 struct m68k_op operands[6];
174 int nexp; /* number of exprs in use */
175 struct m68k_exp exprs[4];
177 int nfrag; /* Number of frags we have to produce */
180 int fragoff; /* Where in the current opcode the frag ends */
187 int nrel; /* Num of reloc strucs in use */
194 /* In a pc relative address the difference between the address
195 of the offset and the address that the offset is relative
196 to. This depends on the addressing mode. Basically this
197 is the value to put in the offset field to address the
198 first byte of the offset, without regarding the special
199 significance of some values (in the branch instruction, for
203 reloc[5]; /* Five is enough??? */
206 #define cpu_of_arch(x) ((x) & m68000up)
207 #define float_of_arch(x) ((x) & mfloat)
208 #define mmu_of_arch(x) ((x) & mmmu)
210 static struct m68k_it the_ins; /* the instruction being assembled */
212 #define op(ex) ((ex)->exp.X_op)
213 #define adds(ex) ((ex)->exp.X_add_symbol)
214 #define subs(ex) ((ex)->exp.X_op_symbol)
215 #define offs(ex) ((ex)->exp.X_add_number)
217 /* Macros for adding things to the m68k_it struct */
219 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
221 /* Like addword, but goes BEFORE general operands */
225 struct m68k_incant *opcode;
228 for(z=the_ins.numo;z>opcode->m_codenum;--z)
229 the_ins.opcode[z]=the_ins.opcode[z-1];
230 for(z=0;z<the_ins.nrel;z++)
231 the_ins.reloc[z].n+=2;
232 for (z = 0; z < the_ins.nfrag; z++)
233 the_ins.fragb[z].fragoff++;
234 the_ins.opcode[opcode->m_codenum]=w;
238 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
241 add_fix (width, exp, pc_rel, pc_fix)
243 struct m68k_exp *exp;
247 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
251 : (the_ins.numo*2)));
252 the_ins.reloc[the_ins.nrel].exp = exp->exp;
253 the_ins.reloc[the_ins.nrel].wid = width;
254 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
255 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
258 /* Cause an extra frag to be generated here, inserting up to 10 bytes
259 (that value is chosen in the frag_var call in md_assemble). TYPE
260 is the subtype of the frag to be generated; its primary type is
261 rs_machine_dependent.
263 The TYPE parameter is also used by md_convert_frag_1 and
264 md_estimate_size_before_relax. The appropriate type of fixup will
265 be emitted by md_convert_frag_1.
267 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
269 add_frag(add,off,type)
274 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
275 the_ins.fragb[the_ins.nfrag].fadd=add;
276 the_ins.fragb[the_ins.nfrag].foff=off;
277 the_ins.fragb[the_ins.nfrag++].fragty=type;
281 (op (ex) != O_constant && op (ex) != O_big)
283 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
284 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
285 static int reverse_16_bits PARAMS ((int in));
286 static int reverse_8_bits PARAMS ((int in));
287 static void install_gen_operand PARAMS ((int mode, int val));
288 static void install_operand PARAMS ((int mode, int val));
289 static void s_bss PARAMS ((int));
290 static void s_data1 PARAMS ((int));
291 static void s_data2 PARAMS ((int));
292 static void s_even PARAMS ((int));
293 static void s_proc PARAMS ((int));
294 static void mri_chip PARAMS ((void));
295 static void s_chip PARAMS ((int));
296 static void s_fopt PARAMS ((int));
297 static void s_opt PARAMS ((int));
298 static void s_reg PARAMS ((int));
299 static void s_restore PARAMS ((int));
300 static void s_save PARAMS ((int));
301 static void s_mri_if PARAMS ((int));
302 static void s_mri_else PARAMS ((int));
303 static void s_mri_endi PARAMS ((int));
304 static void s_mri_break PARAMS ((int));
305 static void s_mri_next PARAMS ((int));
306 static void s_mri_for PARAMS ((int));
307 static void s_mri_endf PARAMS ((int));
308 static void s_mri_repeat PARAMS ((int));
309 static void s_mri_until PARAMS ((int));
310 static void s_mri_while PARAMS ((int));
311 static void s_mri_endw PARAMS ((int));
313 static int current_architecture;
321 static const struct m68k_cpu archs[] = {
322 { m68000, "68000", 0 },
323 { m68010, "68010", 0 },
324 { m68020, "68020", 0 },
325 { m68030, "68030", 0 },
326 { m68040, "68040", 0 },
327 { m68060, "68060", 0 },
328 { cpu32, "cpu32", 0 },
329 { m68881, "68881", 0 },
330 { m68851, "68851", 0 },
331 /* Aliases (effectively, so far as gas is concerned) for the above
333 { m68020, "68k", 1 },
334 { m68000, "68302", 1 },
335 { m68000, "68008", 1 },
336 { m68000, "68ec000", 1 },
337 { m68000, "68hc000", 1 },
338 { m68000, "68hc001", 1 },
339 { m68020, "68ec020", 1 },
340 { m68030, "68ec030", 1 },
341 { m68040, "68ec040", 1 },
342 { cpu32, "68330", 1 },
343 { cpu32, "68331", 1 },
344 { cpu32, "68332", 1 },
345 { cpu32, "68333", 1 },
346 { cpu32, "68340", 1 },
347 { cpu32, "68360", 1 },
348 { m68881, "68882", 1 },
351 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
353 /* BCC68000 is for patching in an extra jmp instruction for long offsets
354 on the 68000. The 68000 doesn't support long branches with branchs */
356 /* This table desribes how you change sizes for the various types of variable
357 size expressions. This version only supports two kinds. */
359 /* Note that calls to frag_var need to specify the maximum expansion
360 needed; this is currently 10 bytes for DBCC. */
363 How far Forward this mode will reach:
364 How far Backward this mode will reach:
365 How many bytes this mode will add to the size of the frag
366 Which mode to go to if the offset won't fit in this one
368 relax_typeS md_relax_table[] =
370 {1, 1, 0, 0}, /* First entries aren't used */
371 {1, 1, 0, 0}, /* For no good reason except */
372 {1, 1, 0, 0}, /* that the VAX doesn't either */
375 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
376 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
380 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
381 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
385 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
386 {(32767), (-32768), 2, TAB (PCREL, LONG)},
390 {(127), (-128), 0, TAB (BCC68000, SHORT)},
391 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
392 {0, 0, 6, 0}, /* jmp long space */
395 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
396 {(32767), (-32768), 2, TAB (DBCC, LONG)},
397 {0, 0, 10, 0}, /* bra/jmp long space */
400 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
401 {32767, -32768, 2, TAB (PCLEA, LONG)},
405 /* For, e.g., jmp pcrel indexed. */
406 {125, -130, 0, TAB (PCINDEX, SHORT)},
407 {32765, -32770, 2, TAB (PCINDEX, LONG)},
412 /* These are the machine dependent pseudo-ops. These are included so
413 the assembler can work on the output from the SUN C compiler, which
417 /* This table describes all the machine specific pseudo-ops the assembler
418 has to support. The fields are:
419 pseudo-op name without dot
420 function to call to execute this pseudo-op
421 Integer arg to pass to the function
423 const pseudo_typeS md_pseudo_table[] =
425 {"data1", s_data1, 0},
426 {"data2", s_data2, 0},
429 {"skip", s_space, 0},
432 {"align", s_align_bytes, 0},
435 {"swbeg", s_ignore, 0},
437 {"extend", float_cons, 'x'},
438 {"ldouble", float_cons, 'x'},
440 /* The following pseudo-ops are supported for MRI compatibility. */
442 {"comline", s_space, 1},
444 {"mask2", s_ignore, 0},
447 {"restore", s_restore, 0},
451 {"if.b", s_mri_if, 'b'},
452 {"if.w", s_mri_if, 'w'},
453 {"if.l", s_mri_if, 'l'},
454 {"else", s_mri_else, 0},
455 {"else.s", s_mri_else, 's'},
456 {"else.l", s_mri_else, 'l'},
457 {"endi", s_mri_endi, 0},
458 {"break", s_mri_break, 0},
459 {"break.s", s_mri_break, 's'},
460 {"break.l", s_mri_break, 'l'},
461 {"next", s_mri_next, 0},
462 {"next.s", s_mri_next, 's'},
463 {"next.l", s_mri_next, 'l'},
464 {"for", s_mri_for, 0},
465 {"for.b", s_mri_for, 'b'},
466 {"for.w", s_mri_for, 'w'},
467 {"for.l", s_mri_for, 'l'},
468 {"endf", s_mri_endf, 0},
469 {"repeat", s_mri_repeat, 0},
470 {"until", s_mri_until, 0},
471 {"until.b", s_mri_until, 'b'},
472 {"until.w", s_mri_until, 'w'},
473 {"until.l", s_mri_until, 'l'},
474 {"while", s_mri_while, 0},
475 {"while.b", s_mri_while, 'b'},
476 {"while.w", s_mri_while, 'w'},
477 {"while.l", s_mri_while, 'l'},
478 {"endw", s_mri_endw, 0},
484 /* The mote pseudo ops are put into the opcode table, since they
485 don't start with a . they look like opcodes to gas.
487 extern void obj_coff_section ();
489 CONST pseudo_typeS mote_pseudo_table[] =
502 {"xdef", s_globl, 0},
503 {"align", s_align_ptwo, 0},
505 {"sect", obj_coff_section, 0},
506 {"section", obj_coff_section, 0},
511 #define issbyte(x) ((x)>=-128 && (x)<=127)
512 #define isubyte(x) ((x)>=0 && (x)<=255)
513 #define issword(x) ((x)>=-32768 && (x)<=32767)
514 #define isuword(x) ((x)>=0 && (x)<=65535)
516 #define isbyte(x) ((x)>= -255 && (x)<=255)
517 #define isword(x) ((x)>=-65536 && (x)<=65535)
518 #define islong(x) (1)
520 extern char *input_line_pointer;
522 static char mklower_table[256];
523 #define mklower(c) (mklower_table[(unsigned char)(c)])
524 static char notend_table[256];
525 static char alt_notend_table[256];
527 (! (notend_table[(unsigned char) *s] \
529 && alt_notend_table[(unsigned char) s[1]])))
531 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
533 #ifdef NO_PCREL_RELOCS
536 make_pcrel_absolute(fixP, add_number)
540 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
542 /* rewrite the PC relative instructions to absolute address ones.
543 * these are rumoured to be faster, and the apollo linker refuses
544 * to deal with the PC relative relocations.
546 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
551 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
557 as_fatal ("Unknown PC relative instruction");
562 #endif /* NO_PCREL_RELOCS */
565 tc_coff_fix2rtype (fixP)
568 if (fixP->fx_tcbit && fixP->fx_size == 4)
569 return R_RELLONG_NEG;
570 #ifdef NO_PCREL_RELOCS
571 know (fixP->fx_pcrel == 0);
572 return (fixP->fx_size == 1 ? R_RELBYTE
573 : fixP->fx_size == 2 ? R_DIR16
576 return (fixP->fx_pcrel ?
577 (fixP->fx_size == 1 ? R_PCRBYTE :
578 fixP->fx_size == 2 ? R_PCRWORD :
580 (fixP->fx_size == 1 ? R_RELBYTE :
581 fixP->fx_size == 2 ? R_RELWORD :
591 tc_gen_reloc (section, fixp)
596 bfd_reloc_code_real_type code;
601 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
602 switch (F (fixp->fx_size, fixp->fx_pcrel))
604 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
605 MAP (1, 0, BFD_RELOC_8);
606 MAP (2, 0, BFD_RELOC_16);
607 MAP (4, 0, BFD_RELOC_32);
608 MAP (1, 1, BFD_RELOC_8_PCREL);
609 MAP (2, 1, BFD_RELOC_16_PCREL);
610 MAP (4, 1, BFD_RELOC_32_PCREL);
615 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
617 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
618 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
620 reloc->addend = fixp->fx_addnumber;
624 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
625 assert (reloc->howto != 0);
630 #endif /* BFD_ASSEMBLER */
632 /* Handle of the OPCODE hash table. NULL means any use before
633 m68k_ip_begin() will crash. */
634 static struct hash_control *op_hash;
636 /* Assemble an m68k instruction. */
643 register struct m68k_op *opP;
644 register struct m68k_incant *opcode;
645 register const char *s;
646 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
647 char *pdot, *pdotmove;
648 enum m68k_size siz1, siz2;
652 char *crack_operand ();
653 LITTLENUM_TYPE words[6];
654 LITTLENUM_TYPE *wordp;
655 unsigned long ok_arch = 0;
657 if (*instring == ' ')
658 instring++; /* skip leading whitespace */
660 /* Scan up to end of operation-code, which MUST end in end-of-string
661 or exactly 1 space. */
663 for (p = instring; *p != '\0'; p++)
673 the_ins.error = "No operator";
677 /* p now points to the end of the opcode name, probably whitespace.
678 Make sure the name is null terminated by clobbering the
679 whitespace, look it up in the hash table, then fix it back.
680 Remove a dot, first, since the opcode tables have none. */
683 for (pdotmove = pdot; pdotmove < p; pdotmove++)
684 *pdotmove = pdotmove[1];
690 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
695 for (pdotmove = p; pdotmove > pdot; pdotmove--)
696 *pdotmove = pdotmove[-1];
703 the_ins.error = "Unknown operator";
707 /* found a legitimate opcode, start matching operands */
711 if (opcode->m_operands == 0)
713 char *old = input_line_pointer;
715 input_line_pointer = p;
716 /* Ahh - it's a motorola style psuedo op */
717 mote_pseudo_table[opcode->m_opnum].poc_handler
718 (mote_pseudo_table[opcode->m_opnum].poc_val);
719 input_line_pointer = old;
725 if (flag_mri && opcode->m_opnum == 0)
727 /* In MRI mode, random garbage is allowed after an instruction
728 which accepts no operands. */
729 the_ins.args = opcode->m_operands;
730 the_ins.numargs = opcode->m_opnum;
731 the_ins.numo = opcode->m_codenum;
732 the_ins.opcode[0] = getone (opcode);
733 the_ins.opcode[1] = gettwo (opcode);
737 for (opP = &the_ins.operands[0]; *p; opP++)
739 p = crack_operand (p, opP);
743 the_ins.error = opP->error;
748 opsfound = opP - &the_ins.operands[0];
750 /* This ugly hack is to support the floating pt opcodes in their
751 standard form. Essentially, we fake a first enty of type COP#1 */
752 if (opcode->m_operands[0] == 'I')
756 for (n = opsfound; n > 0; --n)
757 the_ins.operands[n] = the_ins.operands[n - 1];
759 memset ((char *) (&the_ins.operands[0]), '\0',
760 sizeof (the_ins.operands[0]));
761 the_ins.operands[0].mode = CONTROL;
762 the_ins.operands[0].reg = m68k_float_copnum;
766 /* We've got the operands. Find an opcode that'll accept them */
769 /* If we didn't get the right number of ops, or we have no
770 common model with this pattern then reject this pattern. */
772 if (opsfound != opcode->m_opnum
773 || ((opcode->m_arch & current_architecture) == 0))
776 ok_arch |= opcode->m_arch;
780 for (s = opcode->m_operands, opP = &the_ins.operands[0];
784 /* Warning: this switch is huge! */
785 /* I've tried to organize the cases into this order:
786 non-alpha first, then alpha by letter. Lower-case
787 goes directly before uppercase counterpart. */
788 /* Code with multiple case ...: gets sorted by the lowest
789 case ... it belongs to. I hope this makes sense. */
829 if (opP->mode != IMMED)
832 && ! isvar (&opP->disp)
833 && (opP->disp.exp.X_op != O_constant
834 || ! isbyte (opP->disp.exp.X_add_number)))
837 && ! isvar (&opP->disp)
838 && (opP->disp.exp.X_op != O_constant
839 || ! isword (opP->disp.exp.X_add_number)))
842 && ! isvar (&opP->disp)
843 && (opP->disp.exp.X_op != O_constant
844 || ! issword (opP->disp.exp.X_add_number)))
850 if (opP->mode != IMMED)
855 if (opP->mode == AREG
856 || opP->mode == CONTROL
857 || opP->mode == FPREG
858 || opP->mode == IMMED
859 || opP->mode == REGLST
860 || (opP->mode != ABSL
862 || opP->reg == ZPC)))
867 if (opP->mode == CONTROL
868 || opP->mode == FPREG
869 || opP->mode == REGLST
870 || opP->mode == IMMED
871 || (opP->mode != ABSL
873 || opP->reg == ZPC)))
901 if (opP->mode == CONTROL
902 || opP->mode == FPREG
903 || opP->mode == REGLST)
908 if (opP->mode != AINC)
913 if (opP->mode != ADEC)
963 if (opP->reg == PC || opP->reg == ZPC)
984 case '~': /* For now! (JF FOO is this right?) */
1006 if (opP->mode != CONTROL
1007 || (opP->reg != TT0 && opP->reg != TT1))
1012 if (opP->mode != AREG)
1017 if (opP->mode != AINDR)
1022 if (opP->mode != ABSL
1024 && strncmp (instring, "jbsr", 4) == 0))
1029 if (opP->mode != CONTROL || opP->reg != CCR)
1034 if (opP->mode != DISP
1036 || opP->reg > ADDR7)
1041 if (opP->mode != DREG)
1046 if (opP->mode != FPREG)
1051 if (opP->mode != CONTROL
1058 if (opP->mode != CONTROL
1060 || opP->reg > last_movec_reg)
1064 const enum m68k_register *rp;
1065 for (rp = control_regs; *rp; rp++)
1066 if (*rp == opP->reg)
1074 if (opP->mode != IMMED)
1080 if (opP->mode == DREG
1081 || opP->mode == AREG
1082 || opP->mode == FPREG)
1091 opP->mask = 1 << (opP->reg - DATA0);
1094 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1097 opP->mask = 1 << (opP->reg - FP0 + 16);
1105 else if (opP->mode == CONTROL)
1114 opP->mask = 1 << 24;
1117 opP->mask = 1 << 25;
1120 opP->mask = 1 << 26;
1129 else if (opP->mode == ABSL
1130 && opP->disp.size == SIZE_UNSPEC
1131 && opP->disp.exp.X_op == O_constant)
1133 /* This is what the MRI REG pseudo-op generates. */
1135 opP->mask = opP->disp.exp.X_add_number;
1137 else if (opP->mode != REGLST)
1139 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1141 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1146 if (opP->mode != IMMED)
1148 else if (opP->disp.exp.X_op != O_constant
1149 || ! issbyte (opP->disp.exp.X_add_number))
1151 else if (! m68k_quick
1152 && instring[3] != 'q'
1153 && instring[4] != 'q')
1158 if (opP->mode != DREG && opP->mode != IMMED)
1163 if (opP->mode != IMMED)
1165 else if (opP->disp.exp.X_op != O_constant
1166 || opP->disp.exp.X_add_number < 1
1167 || opP->disp.exp.X_add_number > 8)
1169 else if (! m68k_quick
1170 && (strncmp (instring, "add", 3) == 0
1171 || strncmp (instring, "sub", 3) == 0)
1172 && instring[3] != 'q')
1177 if (opP->mode != DREG && opP->mode != AREG)
1182 if (opP->mode != AINDR
1183 && (opP->mode != BASE
1185 && opP->reg != ZADDR0)
1186 || opP->disp.exp.X_op != O_absent
1187 || ((opP->index.reg < DATA0
1188 || opP->index.reg > DATA7)
1189 && (opP->index.reg < ADDR0
1190 || opP->index.reg > ADDR7))
1191 || opP->index.size != SIZE_UNSPEC
1192 || opP->index.scale != 1))
1197 if (opP->mode != CONTROL
1198 || ! (opP->reg == FPI
1200 || opP->reg == FPC))
1205 if (opP->mode != CONTROL || opP->reg != SR)
1210 if (opP->mode != IMMED)
1212 else if (opP->disp.exp.X_op != O_constant
1213 || opP->disp.exp.X_add_number < 0
1214 || opP->disp.exp.X_add_number > 7)
1219 if (opP->mode != CONTROL || opP->reg != USP)
1223 /* JF these are out of order. We could put them
1224 in order if we were willing to put up with
1225 bunches of #ifdef m68851s in the code.
1227 Don't forget that you need these operands
1228 to use 68030 MMU instructions. */
1230 /* Memory addressing mode used by pflushr */
1232 if (opP->mode == CONTROL
1233 || opP->mode == FPREG
1234 || opP->mode == DREG
1235 || opP->mode == AREG
1236 || opP->mode == REGLST)
1238 /* We should accept immediate operands, but they
1239 supposedly have to be quad word, and we don't
1240 handle that. I would like to see what a Motorola
1241 assembler does before doing something here. */
1242 if (opP->mode == IMMED)
1247 if (opP->mode != CONTROL
1248 || (opP->reg != SFC && opP->reg != DFC))
1253 if (opP->mode != CONTROL || opP->reg != TC)
1258 if (opP->mode != CONTROL || opP->reg != AC)
1263 if (opP->mode != CONTROL
1266 && opP->reg != SCC))
1271 if (opP->mode != CONTROL
1277 if (opP->mode != CONTROL
1280 && opP->reg != CRP))
1285 if (opP->mode != CONTROL
1286 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1287 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1292 if (opP->mode != CONTROL || opP->reg != PSR)
1297 if (opP->mode != CONTROL || opP->reg != PCSR)
1302 if (opP->mode != CONTROL
1309 } /* not a cache specifier. */
1313 if (opP->mode != ABSL)
1319 } /* switch on type of operand */
1323 } /* for each operand */
1324 } /* if immediately wrong */
1331 opcode = opcode->m_next;
1336 && !(ok_arch & current_architecture))
1341 "invalid instruction for this architecture; needs ");
1342 cp = buf + strlen (buf);
1346 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1349 strcpy (cp, "mmu (68030 or 68851)");
1352 strcpy (cp, "68020 or higher");
1355 strcpy (cp, "68000 or higher");
1358 strcpy (cp, "68010 or higher");
1362 int got_one = 0, idx;
1363 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1366 if ((archs[idx].arch & ok_arch)
1367 && ! archs[idx].alias)
1371 strcpy (cp, " or ");
1375 strcpy (cp, archs[idx].name);
1387 the_ins.error = "operands mismatch";
1389 } /* Fell off the end */
1394 /* now assemble it */
1396 the_ins.args = opcode->m_operands;
1397 the_ins.numargs = opcode->m_opnum;
1398 the_ins.numo = opcode->m_codenum;
1399 the_ins.opcode[0] = getone (opcode);
1400 the_ins.opcode[1] = gettwo (opcode);
1402 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1404 /* This switch is a doozy.
1405 Watch the first step; its a big one! */
1426 tmpreg = 0x3c; /* 7.4 */
1427 if (strchr ("bwl", s[1]))
1428 nextword = get_num (&opP->disp, 80);
1430 nextword = get_num (&opP->disp, 0);
1431 if (isvar (&opP->disp))
1432 add_fix (s[1], &opP->disp, 0, 0);
1436 if (!isbyte (nextword))
1437 opP->error = "operand out of range";
1442 if (!isword (nextword))
1443 opP->error = "operand out of range";
1448 if (!issword (nextword))
1449 opP->error = "operand out of range";
1454 addword (nextword >> 16);
1481 /* We gotta put out some float */
1482 if (op (&opP->disp) != O_big)
1487 /* Can other cases happen here? */
1488 if (op (&opP->disp) != O_constant)
1491 val = (valueT) offs (&opP->disp);
1495 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1496 val >>= LITTLENUM_NUMBER_OF_BITS;
1500 offs (&opP->disp) = gencnt;
1502 if (offs (&opP->disp) > 0)
1504 if (offs (&opP->disp) > baseo)
1506 as_warn ("Bignum too big for %c format; truncated",
1508 offs (&opP->disp) = baseo;
1510 baseo -= offs (&opP->disp);
1513 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1514 offs (&opP->disp)--;
1519 gen_to_words (words, baseo, (long) outro);
1520 for (wordp = words; baseo--; wordp++)
1524 tmpreg = opP->reg - DATA; /* 0.dreg */
1527 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1530 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1533 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1536 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1540 nextword = get_num (&opP->disp, 80);
1543 && ! isvar (&opP->disp)
1546 opP->disp.exp.X_op = O_symbol;
1547 #ifndef BFD_ASSEMBLER
1548 opP->disp.exp.X_add_symbol = &abs_symbol;
1550 opP->disp.exp.X_add_symbol =
1551 section_symbol (absolute_section);
1555 /* Force into index mode. Hope this works */
1557 /* We do the first bit for 32-bit displacements, and the
1558 second bit for 16 bit ones. It is possible that we
1559 should make the default be WORD instead of LONG, but
1560 I think that'd break GCC, so we put up with a little
1561 inefficiency for the sake of working output. */
1563 if (!issword (nextword)
1564 || (isvar (&opP->disp)
1565 && ((opP->disp.size == SIZE_UNSPEC
1566 && flag_short_refs == 0
1567 && cpu_of_arch (current_architecture) >= m68020)
1568 || opP->disp.size == SIZE_LONG)))
1571 tmpreg = 0x3B; /* 7.3 */
1573 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1574 if (isvar (&opP->disp))
1580 add_fix ('l', &opP->disp, 1, 2);
1581 addword (0), addword (0);
1583 add_frag (adds (&opP->disp),
1585 TAB (PCLEA, SZ_UNDEF));
1592 add_fix ('l', &opP->disp, 0, 0);
1597 addword (nextword >> 16);
1602 tmpreg = 0x3A; /* 7.2 */
1604 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1606 if (isvar (&opP->disp))
1610 add_fix ('w', &opP->disp, 1, 0);
1613 add_fix ('w', &opP->disp, 0, 0);
1623 baseo = get_num (&opP->disp, 80);
1624 if (opP->mode == POST || opP->mode == PRE)
1625 outro = get_num (&opP->odisp, 80);
1626 /* Figure out the `addressing mode'.
1627 Also turn on the BASE_DISABLE bit, if needed. */
1628 if (opP->reg == PC || opP->reg == ZPC)
1630 tmpreg = 0x3b; /* 7.3 */
1631 if (opP->reg == ZPC)
1634 else if (opP->reg == 0)
1637 tmpreg = 0x30; /* 6.garbage */
1639 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1642 tmpreg = 0x30 + opP->reg - ZADDR0;
1645 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1647 siz1 = opP->disp.size;
1648 if (opP->mode == POST || opP->mode == PRE)
1649 siz2 = opP->odisp.size;
1653 /* Index register stuff */
1654 if (opP->index.reg != 0
1655 && opP->index.reg >= DATA
1656 && opP->index.reg <= ADDR7)
1658 nextword |= (opP->index.reg - DATA) << 12;
1660 if (opP->index.size == SIZE_UNSPEC
1661 || opP->index.size == SIZE_LONG)
1664 if (cpu_of_arch (current_architecture) < m68020)
1666 if (opP->index.scale != 1)
1669 "scale factor invalid on this architecture; needs 68020 or higher";
1673 switch (opP->index.scale)
1690 GET US OUT OF HERE! */
1692 /* Must be INDEX, with an index register. Address
1693 register cannot be ZERO-PC, and either :b was
1694 forced, or we know it will fit. For a 68000 or
1695 68010, force this mode anyways, because the
1696 larger modes aren't supported. */
1697 if (opP->mode == BASE
1698 && ((opP->reg >= ADDR0
1699 && opP->reg <= ADDR7)
1702 if (siz1 == SIZE_BYTE
1703 || cpu_of_arch (current_architecture) < m68020
1704 || (siz1 == SIZE_UNSPEC
1705 && ! isvar (&opP->disp)
1706 && issbyte (baseo)))
1708 nextword += baseo & 0xff;
1710 if (isvar (&opP->disp))
1712 /* Do a byte relocation. If it doesn't
1713 fit (possible on m68000) let the
1714 fixup processing complain later. */
1716 add_fix ('B', &opP->disp, 1, 1);
1718 add_fix ('B', &opP->disp, 0, 0);
1720 else if (siz1 != SIZE_BYTE)
1722 if (siz1 != SIZE_UNSPEC)
1723 as_warn ("Forcing byte displacement");
1724 if (! issbyte (baseo))
1725 opP->error = "byte displacement out of range";
1730 else if (siz1 == SIZE_UNSPEC
1732 && isvar (&opP->disp)
1733 && subs (&opP->disp) == NULL)
1735 nextword += baseo & 0xff;
1737 add_frag (adds (&opP->disp), offs (&opP->disp),
1738 TAB (PCINDEX, SZ_UNDEF));
1746 nextword |= 0x40; /* No index reg */
1747 if (opP->index.reg >= ZDATA0
1748 && opP->index.reg <= ZDATA7)
1749 nextword |= (opP->index.reg - ZDATA0) << 12;
1750 else if (opP->index.reg >= ZADDR0
1751 || opP->index.reg <= ZADDR7)
1752 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1755 /* It isn't simple. */
1757 if (cpu_of_arch (current_architecture) < m68020)
1759 "invalid operand mode for this architecture; needs 68020 or higher";
1762 /* If the guy specified a width, we assume that it is
1763 wide enough. Maybe it isn't. If so, we lose. */
1767 if (isvar (&opP->disp)
1769 : ! issword (baseo))
1774 else if (! isvar (&opP->disp) && baseo == 0)
1783 as_warn (":b not permitted; defaulting to :w");
1793 /* Figure out innner displacement stuff */
1794 if (opP->mode == POST || opP->mode == PRE)
1799 if (isvar (&opP->odisp)
1801 : ! issword (outro))
1806 else if (! isvar (&opP->odisp) && outro == 0)
1815 as_warn (":b not permitted; defaulting to :w");
1824 if (opP->mode == POST
1825 && (nextword & 0x40) == 0)
1830 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
1832 if (opP->reg == PC || opP->reg == ZPC)
1833 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
1835 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
1837 if (siz1 == SIZE_LONG)
1838 addword (baseo >> 16);
1839 if (siz1 != SIZE_UNSPEC)
1842 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1843 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1844 if (siz2 == SIZE_LONG)
1845 addword (outro >> 16);
1846 if (siz2 != SIZE_UNSPEC)
1852 nextword = get_num (&opP->disp, 80);
1853 switch (opP->disp.size)
1858 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
1860 tmpreg = 0x38; /* 7.0 */
1864 /* Don't generate pc relative code on 68010 and
1866 if (isvar (&opP->disp)
1867 && !subs (&opP->disp)
1868 && adds (&opP->disp)
1869 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
1870 && cpu_of_arch (current_architecture) >= m68020
1872 && !strchr ("~%&$?", s[0]))
1874 tmpreg = 0x3A; /* 7.2 */
1875 add_frag (adds (&opP->disp),
1877 TAB (PCREL, SZ_UNDEF));
1880 /* Fall through into long */
1882 if (isvar (&opP->disp))
1883 add_fix ('l', &opP->disp, 0, 0);
1885 tmpreg = 0x39;/* 7.1 mode */
1886 addword (nextword >> 16);
1890 case SIZE_WORD: /* Word */
1891 if (isvar (&opP->disp))
1892 add_fix ('w', &opP->disp, 0, 0);
1894 tmpreg = 0x38;/* 7.0 mode */
1902 as_bad ("unknown/incorrect operand");
1905 install_gen_operand (s[1], tmpreg);
1911 { /* JF: I hate floating point! */
1926 tmpreg = get_num (&opP->disp, tmpreg);
1927 if (isvar (&opP->disp))
1928 add_fix (s[1], &opP->disp, 0, 0);
1931 case 'b': /* Danger: These do no check for
1932 certain types of overflow.
1934 if (!isbyte (tmpreg))
1935 opP->error = "out of range";
1936 insop (tmpreg, opcode);
1937 if (isvar (&opP->disp))
1938 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1941 if (!isword (tmpreg))
1942 opP->error = "out of range";
1943 insop (tmpreg, opcode);
1944 if (isvar (&opP->disp))
1945 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1948 if (!issword (tmpreg))
1949 opP->error = "out of range";
1950 insop (tmpreg, opcode);
1951 if (isvar (&opP->disp))
1952 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1955 /* Because of the way insop works, we put these two out
1957 insop (tmpreg, opcode);
1958 insop (tmpreg >> 16, opcode);
1959 if (isvar (&opP->disp))
1960 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1966 install_operand (s[1], tmpreg);
1977 install_operand (s[1], opP->reg - ADDR);
1981 tmpreg = get_num (&opP->disp, 80);
1985 /* The pc_fix argument winds up in fx_pcrel_adjust,
1986 which is a char, and may therefore be unsigned. We
1987 want to pass -1, but we pass 64 instead, and convert
1988 back in md_pcrel_from. */
1989 add_fix ('B', &opP->disp, 1, 64);
1992 add_fix ('w', &opP->disp, 1, 0);
1997 if (cpu_of_arch (current_architecture) < m68020)
1998 as_warn ("Can't use long branches on 68000/68010");
1999 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2000 add_fix ('l', &opP->disp, 1, 0);
2005 if (subs (&opP->disp)) /* We can't relax it */
2008 /* This could either be a symbol, or an absolute
2009 address. No matter, the frag hacking will finger it
2010 out. Not quite: it can't switch from BRANCH to
2011 BCC68000 for the case where opnd is absolute (it
2012 needs to use the 68000 hack since no conditional abs
2014 if (((cpu_of_arch (current_architecture) < m68020)
2015 || (0 == adds (&opP->disp)))
2016 && (the_ins.opcode[0] >= 0x6200)
2017 && (the_ins.opcode[0] <= 0x6f00))
2018 add_frag (adds (&opP->disp), offs (&opP->disp),
2019 TAB (BCC68000, SZ_UNDEF));
2021 add_frag (adds (&opP->disp), offs (&opP->disp),
2022 TAB (ABRANCH, SZ_UNDEF));
2025 if (isvar (&opP->disp))
2028 /* check for DBcc instruction */
2029 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2031 /* size varies if patch */
2032 /* needed for long form */
2033 add_frag (adds (&opP->disp), offs (&opP->disp),
2034 TAB (DBCC, SZ_UNDEF));
2038 add_fix ('w', &opP->disp, 1, 0);
2042 case 'C': /* Fixed size LONG coproc branches */
2043 add_fix ('l', &opP->disp, 1, 0);
2047 case 'c': /* Var size Coprocesssor branches */
2048 if (subs (&opP->disp))
2050 add_fix ('l', &opP->disp, 1, 0);
2051 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2053 else if (adds (&opP->disp))
2054 add_frag (adds (&opP->disp), offs (&opP->disp),
2055 TAB (FBRANCH, SZ_UNDEF));
2058 /* add_frag((symbolS *) 0, offs(&opP->disp),
2059 TAB(FBRANCH,SHORT)); */
2060 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2061 add_fix ('l', &opP->disp, 1, 0);
2071 case 'C': /* Ignore it */
2074 case 'd': /* JF this is a kludge */
2075 install_operand ('s', opP->reg - ADDR);
2076 tmpreg = get_num (&opP->disp, 80);
2077 if (!issword (tmpreg))
2079 as_warn ("Expression out of range, using 0");
2086 install_operand (s[1], opP->reg - DATA);
2090 install_operand (s[1], opP->reg - FP0);
2094 tmpreg = opP->reg - COP0;
2095 install_operand (s[1], tmpreg);
2098 case 'J': /* JF foo */
2159 install_operand (s[1], tmpreg);
2163 tmpreg = get_num (&opP->disp, 55);
2164 install_operand (s[1], tmpreg & 0x7f);
2171 if (tmpreg & 0x7FF0000)
2172 as_bad ("Floating point register in register list");
2173 insop (reverse_16_bits (tmpreg), opcode);
2177 if (tmpreg & 0x700FFFF)
2178 as_bad ("Wrong register in floating-point reglist");
2179 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2187 if (tmpreg & 0x7FF0000)
2188 as_bad ("Floating point register in register list");
2189 insop (tmpreg, opcode);
2191 else if (s[1] == '8')
2193 if (tmpreg & 0x0FFFFFF)
2194 as_bad ("incorrect register in reglist");
2195 install_operand (s[1], tmpreg >> 24);
2199 if (tmpreg & 0x700FFFF)
2200 as_bad ("wrong register in floating-point reglist");
2202 install_operand (s[1], tmpreg >> 16);
2207 install_operand (s[1], get_num (&opP->disp, 60));
2211 tmpreg = ((opP->mode == DREG)
2212 ? 0x20 + opP->reg - DATA
2213 : (get_num (&opP->disp, 40) & 0x1F));
2214 install_operand (s[1], tmpreg);
2218 tmpreg = get_num (&opP->disp, 10);
2221 install_operand (s[1], tmpreg);
2225 /* This depends on the fact that ADDR registers are eight
2226 more than their corresponding DATA regs, so the result
2227 will have the ADDR_REG bit set */
2228 install_operand (s[1], opP->reg - DATA);
2232 if (opP->mode == AINDR)
2233 install_operand (s[1], opP->reg - DATA);
2235 install_operand (s[1], opP->index.reg - DATA);
2239 if (opP->reg == FPI)
2241 else if (opP->reg == FPS)
2243 else if (opP->reg == FPC)
2247 install_operand (s[1], tmpreg);
2250 case 'S': /* Ignore it */
2254 install_operand (s[1], get_num (&opP->disp, 30));
2257 case 'U': /* Ignore it */
2276 as_fatal ("failed sanity check");
2277 } /* switch on cache token */
2278 install_operand (s[1], tmpreg);
2281 /* JF: These are out of order, I fear. */
2294 install_operand (s[1], tmpreg);
2320 install_operand (s[1], tmpreg);
2324 if (opP->reg == VAL)
2343 install_operand (s[1], tmpreg);
2357 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2368 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2374 install_operand (s[1], tmpreg);
2377 know (opP->reg == PSR);
2380 know (opP->reg == PCSR);
2395 install_operand (s[1], tmpreg);
2398 tmpreg = get_num (&opP->disp, 20);
2399 install_operand (s[1], tmpreg);
2401 case '_': /* used only for move16 absolute 32-bit address */
2402 tmpreg = get_num (&opP->disp, 80);
2403 addword (tmpreg >> 16);
2404 addword (tmpreg & 0xFFFF);
2411 /* By the time whe get here (FINALLY) the_ins contains the complete
2412 instruction, ready to be emitted. . . */
2416 reverse_16_bits (in)
2422 static int mask[16] =
2424 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2425 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2427 for (n = 0; n < 16; n++)
2430 out |= mask[15 - n];
2433 } /* reverse_16_bits() */
2442 static int mask[8] =
2444 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2447 for (n = 0; n < 8; n++)
2453 } /* reverse_8_bits() */
2455 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2456 (that value is chosen in the frag_var call in md_assemble). TYPE
2457 is the subtype of the frag to be generated; its primary type is
2458 rs_machine_dependent.
2460 The TYPE parameter is also used by md_convert_frag_1 and
2461 md_estimate_size_before_relax. The appropriate type of fixup will
2462 be emitted by md_convert_frag_1.
2464 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2466 install_operand (mode, val)
2473 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2476 the_ins.opcode[0] |= val << 9;
2479 the_ins.opcode[1] |= val << 12;
2482 the_ins.opcode[1] |= val << 6;
2485 the_ins.opcode[1] |= val;
2488 the_ins.opcode[2] |= val << 12;
2491 the_ins.opcode[2] |= val << 6;
2494 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2495 three words long! */
2497 the_ins.opcode[2] |= val;
2500 the_ins.opcode[1] |= val << 7;
2503 the_ins.opcode[1] |= val << 10;
2507 the_ins.opcode[1] |= val << 5;
2512 the_ins.opcode[1] |= (val << 10) | (val << 7);
2515 the_ins.opcode[1] |= (val << 12) | val;
2518 the_ins.opcode[0] |= val = 0xff;
2521 the_ins.opcode[0] |= val << 9;
2524 the_ins.opcode[1] |= val;
2527 the_ins.opcode[1] |= val;
2528 the_ins.numo++; /* What a hack */
2531 the_ins.opcode[1] |= val << 4;
2539 the_ins.opcode[0] |= (val << 6);
2542 the_ins.opcode[1] = (val >> 16);
2543 the_ins.opcode[2] = val & 0xffff;
2547 as_fatal ("failed sanity check.");
2549 } /* install_operand() */
2552 install_gen_operand (mode, val)
2559 the_ins.opcode[0] |= val;
2562 /* This is a kludge!!! */
2563 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2572 the_ins.opcode[0] |= val;
2574 /* more stuff goes here */
2576 as_fatal ("failed sanity check.");
2578 } /* install_gen_operand() */
2581 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2582 * then deal with the bitfield hack.
2586 crack_operand (str, opP)
2588 register struct m68k_op *opP;
2590 register int parens;
2592 register char *beg_str;
2600 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2606 else if (*str == ')')
2610 opP->error = "Extra )";
2616 if (flag_mri && *str == '\'')
2617 inquote = ! inquote;
2619 if (!*str && parens)
2621 opP->error = "Missing )";
2626 if (m68k_ip_op (beg_str, opP) != 0)
2633 c = *++str; /* JF bitfield hack */
2638 as_bad ("Missing operand");
2643 /* This is the guts of the machine-dependent assembler. STR points to a
2644 machine dependent instruction. This function is supposed to emit
2645 the frags/bytes it assembles to.
2649 insert_reg (regname, regnum)
2656 #ifdef REGISTER_PREFIX
2657 if (!flag_reg_prefix_optional)
2659 buf[0] = REGISTER_PREFIX;
2660 strcpy (buf + 1, regname);
2665 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2666 &zero_address_frag));
2668 for (i = 0; regname[i]; i++)
2669 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2672 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2673 &zero_address_frag));
2682 static const struct init_entry init_table[] =
2792 /* 68ec030 versions of same */
2795 /* 68ec030 access control unit, identical to 030 MMU status reg */
2798 /* Suppressed data and address registers. */
2823 for (i = 0; init_table[i].name; i++)
2824 insert_reg (init_table[i].name, init_table[i].number);
2827 static int no_68851, no_68881;
2830 /* a.out machine type. Default to 68020. */
2831 int m68k_aout_machtype = 2;
2843 int shorts_this_frag;
2846 /* In MRI mode, the instruction and operands are separated by a
2847 space. Anything following the operands is a comment. The label
2848 has already been removed. */
2856 for (s = str; *s != '\0'; s++)
2858 if ((*s == ' ' || *s == '\t') && ! inquote)
2876 inquote = ! inquote;
2881 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
2886 for (n = 0; n < the_ins.numargs; n++)
2887 if (the_ins.operands[n].error)
2889 er = the_ins.operands[n].error;
2895 as_bad ("%s -- statement `%s' ignored", er, str);
2899 if (the_ins.nfrag == 0)
2901 /* No frag hacking involved; just put it out */
2902 toP = frag_more (2 * the_ins.numo);
2903 fromP = &the_ins.opcode[0];
2904 for (m = the_ins.numo; m; --m)
2906 md_number_to_chars (toP, (long) (*fromP), 2);
2910 /* put out symbol-dependent info */
2911 for (m = 0; m < the_ins.nrel; m++)
2913 switch (the_ins.reloc[m].wid)
2931 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2932 the_ins.reloc[m].wid);
2935 fixP = fix_new_exp (frag_now,
2936 ((toP - frag_now->fr_literal)
2937 - the_ins.numo * 2 + the_ins.reloc[m].n),
2939 &the_ins.reloc[m].exp,
2940 the_ins.reloc[m].pcrel,
2942 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2947 /* There's some frag hacking */
2948 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2953 wid = 2 * the_ins.fragb[n].fragoff;
2955 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2956 toP = frag_more (wid);
2958 shorts_this_frag = 0;
2959 for (m = wid / 2; m; --m)
2961 md_number_to_chars (toP, (long) (*fromP), 2);
2966 for (m = 0; m < the_ins.nrel; m++)
2968 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
2970 the_ins.reloc[m].n -= 2 * shorts_this_frag;
2973 wid = the_ins.reloc[m].wid;
2976 the_ins.reloc[m].wid = 0;
2977 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2979 fixP = fix_new_exp (frag_now,
2980 ((toP - frag_now->fr_literal)
2981 - the_ins.numo * 2 + the_ins.reloc[m].n),
2983 &the_ins.reloc[m].exp,
2984 the_ins.reloc[m].pcrel,
2986 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2988 (void) frag_var (rs_machine_dependent, 10, 0,
2989 (relax_substateT) (the_ins.fragb[n].fragty),
2990 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
2992 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2993 shorts_this_frag = 0;
2996 toP = frag_more (n * sizeof (short));
2999 md_number_to_chars (toP, (long) (*fromP), 2);
3005 for (m = 0; m < the_ins.nrel; m++)
3009 wid = the_ins.reloc[m].wid;
3012 the_ins.reloc[m].wid = 0;
3013 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3015 fixP = fix_new_exp (frag_now,
3016 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3017 - shorts_this_frag * 2),
3019 &the_ins.reloc[m].exp,
3020 the_ins.reloc[m].pcrel,
3022 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3030 * md_begin -- set up hash tables with 68000 instructions.
3031 * similar to what the vax assembler does. ---phr
3033 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3034 a copy of it at runtime, adding in the information we want but isn't
3035 there. I think it'd be better to have an awk script hack the table
3036 at compile time. Or even just xstr the table and use it as-is. But
3037 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3040 register const struct m68k_opcode *ins;
3041 register struct m68k_incant *hack, *slak;
3042 register const char *retval = 0; /* empty string, or error msg text */
3043 register unsigned int i;
3048 flag_reg_prefix_optional = 1;
3053 op_hash = hash_new ();
3055 obstack_begin (&robyn, 4000);
3056 for (i = 0; i < m68k_numopcodes; i++)
3058 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3061 ins = &m68k_opcodes[i];
3062 /* We *could* ignore insns that don't match our arch here
3063 but just leaving them out of the hash. */
3064 slak->m_operands = ins->args;
3065 slak->m_opnum = strlen (slak->m_operands) / 2;
3066 slak->m_arch = ins->arch;
3067 slak->m_opcode = ins->opcode;
3068 /* This is kludgey */
3069 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3070 if (i + 1 != m68k_numopcodes
3071 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3073 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3078 slak = slak->m_next;
3082 retval = hash_insert (op_hash, ins->name, (char *) hack);
3084 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3087 for (i = 0; i < m68k_numaliases; i++)
3089 const char *name = m68k_opcode_aliases[i].primary;
3090 const char *alias = m68k_opcode_aliases[i].alias;
3091 PTR val = hash_find (op_hash, name);
3093 as_fatal ("Internal Error: Can't find %s in hash table", name);
3094 retval = hash_insert (op_hash, alias, val);
3096 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3099 /* In MRI mode, all unsized branches are variable sized. Normally,
3100 they are word sized. */
3103 static struct m68k_opcode_alias mri_aliases[] =
3123 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3125 const char *name = mri_aliases[i].primary;
3126 const char *alias = mri_aliases[i].alias;
3127 PTR val = hash_find (op_hash, name);
3129 as_fatal ("Internal Error: Can't find %s in hash table", name);
3130 retval = hash_jam (op_hash, alias, val);
3132 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3136 for (i = 0; i < sizeof (mklower_table); i++)
3137 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3139 for (i = 0; i < sizeof (notend_table); i++)
3141 notend_table[i] = 0;
3142 alt_notend_table[i] = 0;
3144 notend_table[','] = 1;
3145 notend_table['{'] = 1;
3146 notend_table['}'] = 1;
3147 alt_notend_table['a'] = 1;
3148 alt_notend_table['A'] = 1;
3149 alt_notend_table['d'] = 1;
3150 alt_notend_table['D'] = 1;
3151 alt_notend_table['#'] = 1;
3152 alt_notend_table['&'] = 1;
3153 alt_notend_table['f'] = 1;
3154 alt_notend_table['F'] = 1;
3155 #ifdef REGISTER_PREFIX
3156 alt_notend_table[REGISTER_PREFIX] = 1;
3159 /* We need to put '(' in alt_notend_table to handle
3160 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3162 alt_notend_table['('] = 1;
3164 /* We need to put '@' in alt_notend_table to handle
3165 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3167 alt_notend_table['@'] = 1;
3169 #ifndef MIT_SYNTAX_ONLY
3170 /* Insert pseudo ops, these have to go into the opcode table since
3171 gas expects pseudo ops to start with a dot */
3174 while (mote_pseudo_table[n].poc_name)
3176 hack = (struct m68k_incant *)
3177 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3178 hash_insert (op_hash,
3179 mote_pseudo_table[n].poc_name, (char *) hack);
3180 hack->m_operands = 0;
3191 m68k_init_after_args ()
3193 if (cpu_of_arch (current_architecture) == 0)
3196 const char *default_cpu = TARGET_CPU;
3198 if (*default_cpu == 'm')
3200 for (i = 0; i < n_archs; i++)
3201 if (strcasecmp (default_cpu, archs[i].name) == 0)
3205 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3206 current_architecture |= m68020;
3209 current_architecture |= archs[i].arch;
3211 /* Permit m68881 specification with all cpus; those that can't work
3212 with a coprocessor could be doing emulation. */
3213 if (current_architecture & m68851)
3215 if (current_architecture & m68040)
3217 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3220 /* What other incompatibilities could we check for? */
3222 /* Toss in some default assumptions about coprocessors. */
3224 && (cpu_of_arch (current_architecture)
3225 /* Can CPU32 have a 68881 coprocessor?? */
3226 & (m68020 | m68030 | cpu32)))
3228 current_architecture |= m68881;
3231 && (cpu_of_arch (current_architecture) & m68020up) != 0
3232 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3234 current_architecture |= m68851;
3236 if (no_68881 && (current_architecture & m68881))
3237 as_bad ("options for 68881 and no-68881 both given");
3238 if (no_68851 && (current_architecture & m68851))
3239 as_bad ("options for 68851 and no-68851 both given");
3242 /* Work out the magic number. This isn't very general. */
3243 if (current_architecture & m68000)
3244 m68k_aout_machtype = 0;
3245 else if (current_architecture & m68010)
3246 m68k_aout_machtype = 1;
3247 else if (current_architecture & m68020)
3248 m68k_aout_machtype = 2;
3250 m68k_aout_machtype = 2;
3253 /* Note which set of "movec" control registers is available. */
3254 switch (cpu_of_arch (current_architecture))
3257 control_regs = m68000_control_regs;
3260 control_regs = m68010_control_regs;
3264 control_regs = m68020_control_regs;
3267 control_regs = m68040_control_regs;
3270 control_regs = m68060_control_regs;
3273 control_regs = cpu32_control_regs;
3279 if (cpu_of_arch (current_architecture) < m68020)
3280 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3283 /* Equal to MAX_PRECISION in atof-ieee.c */
3284 #define MAX_LITTLENUMS 6
3286 /* Turn a string in input_line_pointer into a floating point constant
3287 of type type, and store the appropriate bytes in *litP. The number
3288 of LITTLENUMS emitted is stored in *sizeP . An error message is
3289 returned, or NULL on OK. */
3292 md_atof (type, litP, sizeP)
3298 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3299 LITTLENUM_TYPE *wordP;
3331 return "Bad call to MD_ATOF()";
3333 t = atof_ieee (input_line_pointer, type, words);
3335 input_line_pointer = t;
3337 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3338 for (wordP = words; prec--;)
3340 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3341 litP += sizeof (LITTLENUM_TYPE);
3347 md_number_to_chars (buf, val, n)
3352 number_to_chars_bigendian (buf, val, n);
3356 md_apply_fix_2 (fixP, val)
3360 addressT upper_limit;
3361 offsetT lower_limit;
3363 /* This is unnecessary but it convinces the native rs6000 compiler
3364 to generate the code we want. */
3365 char *buf = fixP->fx_frag->fr_literal;
3366 buf += fixP->fx_where;
3367 /* end ibm compiler workaround */
3369 if (val & 0x80000000)
3370 val |= ~(addressT)0x7fffffff;
3374 switch (fixP->fx_size)
3376 /* The cast to offsetT below are necessary to make code correct for
3377 machines where ints are smaller than offsetT */
3381 lower_limit = - (offsetT) 0x80;
3384 *buf++ = (val >> 8);
3386 upper_limit = 0x7fff;
3387 lower_limit = - (offsetT) 0x8000;
3390 *buf++ = (val >> 24);
3391 *buf++ = (val >> 16);
3392 *buf++ = (val >> 8);
3394 upper_limit = 0x7fffffff;
3395 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3398 BAD_CASE (fixP->fx_size);
3401 /* Fix up a negative reloc. */
3402 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3404 fixP->fx_addsy = fixP->fx_subsy;
3405 fixP->fx_subsy = NULL;
3409 /* For non-pc-relative values, it's conceivable we might get something
3410 like "0xff" for a byte field. So extend the upper part of the range
3411 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3412 so that we can do any range checking at all. */
3413 if (!fixP->fx_pcrel)
3414 upper_limit = upper_limit * 2 + 1;
3416 if ((addressT) val > upper_limit
3417 && (val > 0 || val < lower_limit))
3418 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3420 /* A one byte PC-relative reloc means a short branch. We can't use
3421 a short branch with a value of 0 or -1, because those indicate
3422 different opcodes (branches with longer offsets). */
3424 && fixP->fx_size == 1
3425 && (fixP->fx_addsy == NULL
3426 || S_IS_DEFINED (fixP->fx_addsy))
3427 && (val == 0 || val == -1))
3428 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3431 #ifdef BFD_ASSEMBLER
3433 md_apply_fix (fixP, valp)
3437 md_apply_fix_2 (fixP, (addressT) *valp);
3441 void md_apply_fix (fixP, val)
3445 md_apply_fix_2 (fixP, (addressT) val);
3449 /* *fragP has been relaxed to its final size, and now needs to have
3450 the bytes inside it modified to conform to the new size There is UGLY
3454 md_convert_frag_1 (fragP)
3455 register fragS *fragP;
3461 /* Address in object code of the displacement. */
3462 register int object_address = fragP->fr_fix + fragP->fr_address;
3464 /* Address in gas core of the place to store the displacement. */
3465 /* This convinces the native rs6000 compiler to generate the code we
3467 register char *buffer_address = fragP->fr_literal;
3468 buffer_address += fragP->fr_fix;
3469 /* end ibm compiler workaround */
3471 /* The displacement of the address, from current location. */
3472 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3473 disp = (disp + fragP->fr_offset) - object_address;
3475 #ifdef BFD_ASSEMBLER
3476 disp += fragP->fr_symbol->sy_frag->fr_address;
3479 switch (fragP->fr_subtype)
3481 case TAB (BCC68000, BYTE):
3482 case TAB (ABRANCH, BYTE):
3483 know (issbyte (disp));
3485 as_bad ("short branch with zero offset: use :w");
3486 fragP->fr_opcode[1] = disp;
3489 case TAB (DBCC, SHORT):
3490 know (issword (disp));
3493 case TAB (BCC68000, SHORT):
3494 case TAB (ABRANCH, SHORT):
3495 know (issword (disp));
3496 fragP->fr_opcode[1] = 0x00;
3499 case TAB (ABRANCH, LONG):
3500 if (cpu_of_arch (current_architecture) < m68020)
3502 if (fragP->fr_opcode[0] == 0x61)
3505 fragP->fr_opcode[0] = 0x4E;
3506 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3520 else if (fragP->fr_opcode[0] == 0x60)
3522 fragP->fr_opcode[0] = 0x4E;
3523 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3524 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3525 fragP->fr_offset, 0, NO_RELOC);
3531 as_bad ("Long branch offset not supported.");
3536 fragP->fr_opcode[1] = (char) 0xff;
3540 case TAB (BCC68000, LONG):
3541 /* only Bcc 68000 instructions can come here */
3542 /* change bcc into b!cc/jmp absl long */
3543 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3544 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3546 /* JF: these used to be fr_opcode[2,3], but they may be in a
3547 different frag, in which case refering to them is a no-no.
3548 Only fr_opcode[0,1] are guaranteed to work. */
3549 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3550 *buffer_address++ = (char) 0xf9;
3551 fragP->fr_fix += 2; /* account for jmp instruction */
3552 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3553 fragP->fr_offset, 0, NO_RELOC);
3557 case TAB (DBCC, LONG):
3558 /* only DBcc 68000 instructions can come here */
3559 /* change dbcc into dbcc/jmp absl long */
3560 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3561 *buffer_address++ = 0x00; /* branch offset = 4 */
3562 *buffer_address++ = 0x04;
3563 *buffer_address++ = 0x60; /* put in bra pc+6 */
3564 *buffer_address++ = 0x06;
3565 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3566 *buffer_address++ = (char) 0xf9;
3568 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3569 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3570 fragP->fr_offset, 0, NO_RELOC);
3574 case TAB (FBRANCH, SHORT):
3575 know ((fragP->fr_opcode[1] & 0x40) == 0);
3578 case TAB (FBRANCH, LONG):
3579 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3582 case TAB (PCREL, SHORT):
3585 case TAB (PCREL, LONG):
3586 /* The thing to do here is force it to ABSOLUTE LONG, since
3587 PCREL is really trying to shorten an ABSOLUTE address anyway */
3588 /* JF FOO This code has not been tested */
3589 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3591 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3592 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3593 (unsigned) fragP->fr_opcode[0],
3594 (unsigned long) fragP->fr_address);
3595 fragP->fr_opcode[1] &= ~0x3F;
3596 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3600 case TAB (PCLEA, SHORT):
3601 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3602 fragP->fr_offset, 1, NO_RELOC);
3603 fragP->fr_opcode[1] &= ~0x3F;
3604 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3607 case TAB (PCLEA, LONG):
3608 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3609 fragP->fr_offset, 1, NO_RELOC);
3610 fixP->fx_pcrel_adjust = 2;
3611 /* Already set to mode 7.3; this indicates: PC indirect with
3612 suppressed index, 32-bit displacement. */
3613 *buffer_address++ = 0x01;
3614 *buffer_address++ = 0x70;
3619 case TAB (PCINDEX, BYTE):
3621 if (!issbyte (disp))
3623 as_bad ("displacement doesn't fit in one byte");
3626 assert (fragP->fr_fix >= 2);
3627 buffer_address[-2] &= ~1;
3628 buffer_address[-1] = disp;
3631 case TAB (PCINDEX, SHORT):
3633 assert (issword (disp));
3634 assert (fragP->fr_fix >= 2);
3635 buffer_address[-2] |= 0x1;
3636 buffer_address[-1] = 0x20;
3637 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3638 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3640 fixP->fx_pcrel_adjust = 2;
3643 case TAB (PCINDEX, LONG):
3645 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3646 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3648 fixP->fx_pcrel_adjust = 2;
3649 assert (fragP->fr_fix >= 2);
3650 buffer_address[-2] |= 0x1;
3651 buffer_address[-1] = 0x30;
3658 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3659 fragP->fr_fix += ext;
3663 #ifndef BFD_ASSEMBLER
3666 md_convert_frag (headers, sec, fragP)
3667 object_headers *headers;
3671 md_convert_frag_1 (fragP);
3677 md_convert_frag (abfd, sec, fragP)
3682 md_convert_frag_1 (fragP);
3686 /* Force truly undefined symbols to their maximum size, and generally set up
3687 the frag list to be relaxed
3690 md_estimate_size_before_relax (fragP, segment)
3691 register fragS *fragP;
3695 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3697 old_fix = fragP->fr_fix;
3699 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3700 switch (fragP->fr_subtype)
3703 case TAB (ABRANCH, SZ_UNDEF):
3705 if ((fragP->fr_symbol != NULL) /* Not absolute */
3706 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3708 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3711 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3713 /* On 68000, or for absolute value, switch to abs long */
3714 /* FIXME, we should check abs val, pick short or long */
3715 if (fragP->fr_opcode[0] == 0x61)
3717 fragP->fr_opcode[0] = 0x4E;
3718 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3719 fix_new (fragP, fragP->fr_fix, 4,
3720 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3724 else if (fragP->fr_opcode[0] == 0x60)
3726 fragP->fr_opcode[0] = 0x4E;
3727 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3728 fix_new (fragP, fragP->fr_fix, 4,
3729 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3735 as_warn ("Long branch offset to extern symbol not supported.");
3739 { /* Symbol is still undefined. Make it simple */
3740 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3741 fragP->fr_offset, 1, NO_RELOC);
3743 fragP->fr_opcode[1] = (char) 0xff;
3749 } /* case TAB(ABRANCH,SZ_UNDEF) */
3751 case TAB (FBRANCH, SZ_UNDEF):
3753 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3755 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3760 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3761 fragP->fr_offset, 1, NO_RELOC);
3763 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3767 } /* TAB(FBRANCH,SZ_UNDEF) */
3769 case TAB (PCREL, SZ_UNDEF):
3771 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3773 || cpu_of_arch (current_architecture) < m68020)
3775 fragP->fr_subtype = TAB (PCREL, SHORT);
3780 fragP->fr_subtype = TAB (PCREL, LONG);
3784 } /* TAB(PCREL,SZ_UNDEF) */
3786 case TAB (BCC68000, SZ_UNDEF):
3788 if ((fragP->fr_symbol != NULL)
3789 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3791 fragP->fr_subtype = TAB (BCC68000, BYTE);
3794 /* only Bcc 68000 instructions can come here */
3795 /* change bcc into b!cc/jmp absl long */
3796 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3797 if (flag_short_refs)
3799 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3800 /* JF: these were fr_opcode[2,3] */
3801 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3802 buffer_address[1] = (char) 0xf8;
3803 fragP->fr_fix += 2; /* account for jmp instruction */
3804 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3805 fragP->fr_offset, 0, NO_RELOC);
3810 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3811 /* JF: these were fr_opcode[2,3] */
3812 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3813 buffer_address[1] = (char) 0xf9;
3814 fragP->fr_fix += 2; /* account for jmp instruction */
3815 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3816 fragP->fr_offset, 0, NO_RELOC);
3821 } /* case TAB(BCC68000,SZ_UNDEF) */
3823 case TAB (DBCC, SZ_UNDEF):
3825 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3827 fragP->fr_subtype = TAB (DBCC, SHORT);
3831 /* only DBcc 68000 instructions can come here */
3832 /* change dbcc into dbcc/jmp absl long */
3833 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3834 buffer_address[0] = 0x00; /* branch offset = 4 */
3835 buffer_address[1] = 0x04;
3836 buffer_address[2] = 0x60; /* put in bra pc + ... */
3838 if (flag_short_refs)
3840 /* JF: these were fr_opcode[5-7] */
3841 buffer_address[3] = 0x04; /* plus 4 */
3842 buffer_address[4] = 0x4e; /* Put in Jump Word */
3843 buffer_address[5] = (char) 0xf8;
3844 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3845 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3846 fragP->fr_offset, 0, NO_RELOC);
3851 /* JF: these were fr_opcode[5-7] */
3852 buffer_address[3] = 0x06; /* Plus 6 */
3853 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3854 buffer_address[5] = (char) 0xf9;
3855 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3856 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3857 fragP->fr_offset, 0, NO_RELOC);
3863 } /* case TAB(DBCC,SZ_UNDEF) */
3865 case TAB (PCLEA, SZ_UNDEF):
3867 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3869 || cpu_of_arch (current_architecture) < m68020)
3871 fragP->fr_subtype = TAB (PCLEA, SHORT);
3876 fragP->fr_subtype = TAB (PCLEA, LONG);
3880 } /* TAB(PCLEA,SZ_UNDEF) */
3882 case TAB (PCINDEX, SZ_UNDEF):
3883 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3884 || cpu_of_arch (current_architecture) < m68020)
3886 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3890 fragP->fr_subtype = TAB (PCINDEX, LONG);
3899 /* now that SZ_UNDEF are taken care of, check others */
3900 switch (fragP->fr_subtype)
3902 case TAB (BCC68000, BYTE):
3903 case TAB (ABRANCH, BYTE):
3904 /* We can't do a short jump to the next instruction,
3905 so we force word mode. */
3906 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3907 fragP->fr_symbol->sy_frag == fragP->fr_next)
3909 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3916 return fragP->fr_var + fragP->fr_fix - old_fix;
3919 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3920 /* the bit-field entries in the relocation_info struct plays hell
3921 with the byte-order problems of cross-assembly. So as a hack,
3922 I added this mach. dependent ri twiddler. Ugly, but it gets
3924 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3925 are symbolnum, most sig. byte first. Last byte is broken up with
3926 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3927 nibble as nuthin. (on Sun 3 at least) */
3928 /* Translate the internal relocation information into target-specific
3932 md_ri_to_chars (the_bytes, ri)
3934 struct reloc_info_generic *ri;
3937 md_number_to_chars (the_bytes, ri->r_address, 4);
3938 /* now the fun stuff */
3939 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3940 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3941 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3942 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3943 ((ri->r_extern << 4) & 0x10));
3946 #endif /* comment */
3948 #ifndef BFD_ASSEMBLER
3950 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3953 relax_addressT segment_address_in_file;
3956 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3957 * Out: GNU LD relocation length code: 0, 1, or 2.
3960 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3963 know (fixP->fx_addsy != NULL);
3965 md_number_to_chars (where,
3966 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3969 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3970 ? S_GET_TYPE (fixP->fx_addsy)
3971 : fixP->fx_addsy->sy_number);
3973 where[4] = (r_symbolnum >> 16) & 0x0ff;
3974 where[5] = (r_symbolnum >> 8) & 0x0ff;
3975 where[6] = r_symbolnum & 0x0ff;
3976 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3977 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
3981 #endif /* OBJ_AOUT or OBJ_BOUT */
3983 #ifndef WORKING_DOT_WORD
3984 CONST int md_short_jump_size = 4;
3985 CONST int md_long_jump_size = 6;
3988 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3990 addressT from_addr, to_addr;
3996 offset = to_addr - (from_addr + 2);
3998 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3999 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4003 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4005 addressT from_addr, to_addr;
4011 if (cpu_of_arch (current_architecture) < m68020)
4013 offset = to_addr - S_GET_VALUE (to_symbol);
4014 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4015 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4016 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4021 offset = to_addr - (from_addr + 2);
4022 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4023 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4029 /* Different values of OK tell what its OK to return. Things that
4030 aren't OK are an error (what a shock, no?)
4033 10: Absolute 1:8 only
4034 20: Absolute 0:7 only
4035 30: absolute 0:15 only
4036 40: Absolute 0:31 only
4037 50: absolute 0:127 only
4038 55: absolute -64:63 only
4039 60: absolute -128:127 only
4040 70: absolute 0:4095 only
4047 struct m68k_exp *exp;
4050 if (exp->exp.X_op == O_absent)
4052 /* Do the same thing the VAX asm does */
4053 op (exp) = O_constant;
4059 as_warn ("expression out of range: defaulting to 1");
4063 else if (exp->exp.X_op == O_constant)
4068 if (offs (exp) < 1 || offs (exp) > 8)
4070 as_warn ("expression out of range: defaulting to 1");
4075 if (offs (exp) < 0 || offs (exp) > 7)
4079 if (offs (exp) < 0 || offs (exp) > 15)
4083 if (offs (exp) < 0 || offs (exp) > 32)
4087 if (offs (exp) < 0 || offs (exp) > 127)
4091 if (offs (exp) < -64 || offs (exp) > 63)
4095 if (offs (exp) < -128 || offs (exp) > 127)
4099 if (offs (exp) < 0 || offs (exp) > 4095)
4102 as_warn ("expression out of range: defaulting to 0");
4110 else if (exp->exp.X_op == O_big)
4112 if (offs (exp) <= 0 /* flonum */
4113 && (ok == 80 /* no bignums */
4114 || (ok > 10 /* small-int ranges including 0 ok */
4115 /* If we have a flonum zero, a zero integer should
4116 do as well (e.g., in moveq). */
4117 && generic_floating_point_number.exponent == 0
4118 && generic_floating_point_number.low[0] == 0)))
4120 /* HACK! Turn it into a long */
4121 LITTLENUM_TYPE words[6];
4123 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4124 op (exp) = O_constant;
4127 offs (exp) = words[1] | (words[0] << 16);
4131 op (exp) = O_constant;
4134 offs (exp) = (ok == 10) ? 1 : 0;
4135 as_warn ("Can't deal with expression; defaulting to %ld",
4141 if (ok >= 10 && ok <= 70)
4143 op (exp) = O_constant;
4146 offs (exp) = (ok == 10) ? 1 : 0;
4147 as_warn ("Can't deal with expression; defaulting to %ld",
4152 if (exp->size != SIZE_UNSPEC)
4160 if (!isbyte (offs (exp)))
4161 as_warn ("expression doesn't fit in BYTE");
4164 if (!isword (offs (exp)))
4165 as_warn ("expression doesn't fit in WORD");
4173 /* These are the back-ends for the various machine dependent pseudo-ops. */
4174 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4180 subseg_set (data_section, 1);
4181 demand_empty_rest_of_line ();
4188 subseg_set (data_section, 2);
4189 demand_empty_rest_of_line ();
4196 /* We don't support putting frags in the BSS segment, we fake it
4197 by marking in_bss, then looking at s_skip for clues. */
4199 subseg_set (bss_section, 0);
4200 demand_empty_rest_of_line ();
4208 register long temp_fill;
4210 temp = 1; /* JF should be 2? */
4211 temp_fill = get_absolute_expression ();
4212 if (!need_pass_2) /* Never make frag if expect extra pass. */
4213 frag_align (temp, (int) temp_fill);
4214 demand_empty_rest_of_line ();
4221 demand_empty_rest_of_line ();
4224 /* Pseudo-ops handled for MRI compatibility. */
4226 /* Handle an MRI style chip specification. */
4235 s = input_line_pointer;
4236 c = get_symbol_end ();
4237 for (i = 0; i < n_archs; i++)
4238 if (strcasecmp (s, archs[i].name) == 0)
4242 as_bad ("%s: unrecognized processor name", s);
4243 *input_line_pointer = c;
4244 ignore_rest_of_line ();
4247 *input_line_pointer = c;
4249 if (*input_line_pointer == '/')
4250 current_architecture = 0;
4252 current_architecture &= m68881 | m68851;
4253 current_architecture |= archs[i].arch;
4255 while (*input_line_pointer == '/')
4257 ++input_line_pointer;
4258 s = input_line_pointer;
4259 c = get_symbol_end ();
4260 if (strcmp (s, "68881") == 0)
4261 current_architecture |= m68881;
4262 else if (strcmp (s, "68851") == 0)
4263 current_architecture |= m68851;
4264 *input_line_pointer = c;
4268 /* The MRI CHIP pseudo-op. */
4278 stop = mri_comment_field (&stopc);
4281 mri_comment_end (stop, stopc);
4282 demand_empty_rest_of_line ();
4285 /* The MRI FOPT pseudo-op. */
4293 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4297 input_line_pointer += 3;
4298 temp = get_absolute_expression ();
4299 if (temp < 0 || temp > 7)
4300 as_bad ("bad coprocessor id");
4302 m68k_float_copnum = COP0 + temp;
4306 as_bad ("unrecognized fopt option");
4307 ignore_rest_of_line ();
4311 demand_empty_rest_of_line ();
4314 /* The structure used to handle the MRI OPT pseudo-op. */
4318 /* The name of the option. */
4321 /* If this is not NULL, just call this function. The first argument
4322 is the ARG field of this structure, the second argument is
4323 whether the option was negated. */
4324 void (*pfn) PARAMS ((int arg, int on));
4326 /* If this is not NULL, and the PFN field is NULL, set the variable
4327 this points to. Set it to the ARG field if the option was not
4328 negated, and the NOTARG field otherwise. */
4331 /* The value to pass to PFN or to assign to *PVAR. */
4334 /* The value to assign to *PVAR if the option is negated. If PFN is
4335 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4336 the option may not be negated. */
4340 /* The table used to handle the MRI OPT pseudo-op. */
4342 static void skip_to_comma PARAMS ((int, int));
4343 static void opt_nest PARAMS ((int, int));
4344 static void opt_chip PARAMS ((int, int));
4345 static void opt_list PARAMS ((int, int));
4346 static void opt_list_symbols PARAMS ((int, int));
4348 static const struct opt_action opt_table[] =
4350 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4352 /* We do relaxing, so there is little use for these options. */
4353 { "b", 0, 0, 0, 0 },
4354 { "brs", 0, 0, 0, 0 },
4355 { "brb", 0, 0, 0, 0 },
4356 { "brl", 0, 0, 0, 0 },
4357 { "brw", 0, 0, 0, 0 },
4359 { "c", 0, 0, 0, 0 },
4360 { "cex", 0, 0, 0, 0 },
4361 { "case", 0, &symbols_case_sensitive, 1, 0 },
4362 { "cl", 0, 0, 0, 0 },
4363 { "cre", 0, 0, 0, 0 },
4364 { "d", 0, &flag_keep_locals, 1, 0 },
4365 { "e", 0, 0, 0, 0 },
4366 { "f", 0, &flag_short_refs, 1, 0 },
4367 { "frs", 0, &flag_short_refs, 1, 0 },
4368 { "frl", 0, &flag_short_refs, 0, 1 },
4369 { "g", 0, 0, 0, 0 },
4370 { "i", 0, 0, 0, 0 },
4371 { "m", 0, 0, 0, 0 },
4372 { "mex", 0, 0, 0, 0 },
4373 { "mc", 0, 0, 0, 0 },
4374 { "md", 0, 0, 0, 0 },
4375 { "nest", opt_nest, 0, 0, 0 },
4376 { "next", skip_to_comma, 0, 0, 0 },
4377 { "o", 0, 0, 0, 0 },
4378 { "old", 0, 0, 0, 0 },
4379 { "op", skip_to_comma, 0, 0, 0 },
4380 { "pco", 0, 0, 0, 0 },
4381 { "p", opt_chip, 0, 0, 0 },
4382 { "pcr", 0, 0, 0, 0 },
4383 { "pcs", 0, 0, 0, 0 },
4384 { "r", 0, 0, 0, 0 },
4385 { "quick", 0, &m68k_quick, 1, 0 },
4386 { "rel32", 0, &m68k_rel32, 1, 0 },
4387 { "s", opt_list, 0, 0, 0 },
4388 { "t", opt_list_symbols, 0, 0, 0 },
4389 { "w", 0, &flag_no_warnings, 0, 1 },
4393 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4395 /* The MRI OPT pseudo-op. */
4407 const struct opt_action *o;
4412 if (*input_line_pointer == '-')
4414 ++input_line_pointer;
4417 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4419 input_line_pointer += 2;
4423 s = input_line_pointer;
4424 c = get_symbol_end ();
4426 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4428 if (strcasecmp (s, o->name) == 0)
4432 /* Restore input_line_pointer now in case the option
4434 *input_line_pointer = c;
4435 (*o->pfn) (o->arg, t);
4437 else if (o->pvar != NULL)
4439 if (! t && o->arg == o->notarg)
4440 as_bad ("option `%s' may not be negated", s);
4441 *input_line_pointer = c;
4442 *o->pvar = t ? o->arg : o->notarg;
4445 *input_line_pointer = c;
4451 as_bad ("option `%s' not recognized", s);
4452 *input_line_pointer = c;
4455 while (*input_line_pointer++ == ',');
4457 /* Move back to terminating character. */
4458 --input_line_pointer;
4459 demand_empty_rest_of_line ();
4462 /* Skip ahead to a comma. This is used for OPT options which we do
4463 not suppor tand which take arguments. */
4466 skip_to_comma (arg, on)
4470 while (*input_line_pointer != ','
4471 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4472 ++input_line_pointer;
4475 /* Handle the OPT NEST=depth option. */
4482 if (*input_line_pointer != '=')
4484 as_bad ("bad format of OPT NEST=depth");
4488 ++input_line_pointer;
4489 max_macro_nest = get_absolute_expression ();
4492 /* Handle the OPT P=chip option. */
4499 if (*input_line_pointer != '=')
4501 /* This is just OPT P, which we do not support. */
4505 ++input_line_pointer;
4509 /* Handle the OPT S option. */
4519 /* Handle the OPT T option. */
4522 opt_list_symbols (arg, on)
4527 listing |= LISTING_SYMBOLS;
4529 listing &=~ LISTING_SYMBOLS;
4532 /* Handle the MRI REG pseudo-op. */
4545 if (line_label == NULL)
4547 as_bad ("missing label");
4548 ignore_rest_of_line ();
4553 stop = mri_comment_field (&stopc);
4557 s = input_line_pointer;
4558 while (isalnum ((unsigned char) *input_line_pointer)
4559 #ifdef REGISTER_PREFIX
4560 || *input_line_pointer == REGISTER_PREFIX
4562 || *input_line_pointer == '/'
4563 || *input_line_pointer == '-')
4564 ++input_line_pointer;
4565 c = *input_line_pointer;
4566 *input_line_pointer = '\0';
4568 if (m68k_ip_op (s, &rop) != 0)
4570 if (rop.error == NULL)
4571 as_bad ("bad register list");
4573 as_bad ("bad register list: %s", rop.error);
4574 *input_line_pointer = c;
4575 ignore_rest_of_line ();
4579 *input_line_pointer = c;
4581 if (rop.mode == REGLST)
4583 else if (rop.mode == DREG)
4584 mask = 1 << (rop.reg - DATA0);
4585 else if (rop.mode == AREG)
4586 mask = 1 << (rop.reg - ADDR0 + 8);
4587 else if (rop.mode == FPREG)
4588 mask = 1 << (rop.reg - FP0 + 16);
4589 else if (rop.mode == CONTROL
4592 else if (rop.mode == CONTROL
4595 else if (rop.mode == CONTROL
4600 as_bad ("bad register list");
4601 ignore_rest_of_line ();
4605 S_SET_SEGMENT (line_label, absolute_section);
4606 S_SET_VALUE (line_label, mask);
4607 line_label->sy_frag = &zero_address_frag;
4610 mri_comment_end (stop, stopc);
4612 demand_empty_rest_of_line ();
4615 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4619 struct save_opts *next;
4621 int symbols_case_sensitive;
4629 /* FIXME: We don't save OPT S. */
4632 /* This variable holds the stack of saved options. */
4634 static struct save_opts *save_stack;
4636 /* The MRI SAVE pseudo-op. */
4642 struct save_opts *s;
4644 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4645 s->abspcadd = m68k_abspcadd;
4646 s->symbols_case_sensitive = symbols_case_sensitive;
4647 s->keep_locals = flag_keep_locals;
4648 s->short_refs = flag_short_refs;
4649 s->architecture = current_architecture;
4650 s->quick = m68k_quick;
4651 s->rel32 = m68k_rel32;
4652 s->listing = listing;
4653 s->no_warnings = flag_no_warnings;
4655 s->next = save_stack;
4658 demand_empty_rest_of_line ();
4661 /* The MRI RESTORE pseudo-op. */
4667 struct save_opts *s;
4669 if (save_stack == NULL)
4671 as_bad ("restore without save");
4672 ignore_rest_of_line ();
4677 save_stack = s->next;
4679 m68k_abspcadd = s->abspcadd;
4680 symbols_case_sensitive = s->symbols_case_sensitive;
4681 flag_keep_locals = s->keep_locals;
4682 flag_short_refs = s->short_refs;
4683 current_architecture = s->architecture;
4684 m68k_quick = s->quick;
4685 m68k_rel32 = s->rel32;
4686 listing = s->listing;
4687 flag_no_warnings = s->no_warnings;
4691 demand_empty_rest_of_line ();
4694 /* Types of MRI structured control directives. */
4696 enum mri_control_type
4704 /* This structure is used to stack the MRI structured control
4707 struct mri_control_info
4709 /* The directive within which this one is enclosed. */
4710 struct mri_control_info *outer;
4712 /* The type of directive. */
4713 enum mri_control_type type;
4715 /* Whether an ELSE has been in an IF. */
4718 /* The add or sub statement at the end of a FOR. */
4721 /* The label of the top of a FOR or REPEAT loop. */
4724 /* The label to jump to for the next iteration, or the else
4725 expression of a conditional. */
4728 /* The label to jump to to break out of the loop, or the label past
4729 the end of a conditional. */
4733 /* The stack of MRI structured control directives. */
4735 static struct mri_control_info *mri_control_stack;
4737 /* The current MRI structured control directive index number, used to
4738 generate label names. */
4740 static int mri_control_index;
4742 /* Some function prototypes. */
4744 static char *mri_control_label PARAMS ((void));
4745 static struct mri_control_info *push_mri_control
4746 PARAMS ((enum mri_control_type));
4747 static void pop_mri_control PARAMS ((void));
4748 static int parse_mri_condition PARAMS ((int *));
4749 static int parse_mri_control_operand
4750 PARAMS ((int *, char **, char **, char **, char **));
4751 static int swap_mri_condition PARAMS ((int));
4752 static int reverse_mri_condition PARAMS ((int));
4753 static void build_mri_control_operand
4754 PARAMS ((int, int, char *, char *, char *, char *, const char *,
4755 const char *, int));
4756 static void parse_mri_control_expression
4757 PARAMS ((char *, int, const char *, const char *, int));
4759 /* Generate a new MRI label structured control directive label name. */
4762 mri_control_label ()
4766 n = (char *) xmalloc (20);
4767 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
4768 ++mri_control_index;
4772 /* Create a new MRI structured control directive. */
4774 static struct mri_control_info *
4775 push_mri_control (type)
4776 enum mri_control_type type;
4778 struct mri_control_info *n;
4780 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
4784 if (type == mri_if || type == mri_while)
4787 n->top = mri_control_label ();
4788 n->next = mri_control_label ();
4789 n->bottom = mri_control_label ();
4791 n->outer = mri_control_stack;
4792 mri_control_stack = n;
4797 /* Pop off the stack of MRI structured control directives. */
4802 struct mri_control_info *n;
4804 n = mri_control_stack;
4805 mri_control_stack = n->outer;
4813 /* Recognize a condition code in an MRI structured control expression. */
4816 parse_mri_condition (pcc)
4821 know (*input_line_pointer == '<');
4823 ++input_line_pointer;
4824 c1 = *input_line_pointer++;
4825 c2 = *input_line_pointer++;
4827 if (*input_line_pointer != '>')
4829 as_bad ("syntax error in structured control directive");
4833 ++input_line_pointer;
4841 *pcc = (c1 << 8) | c2;
4846 /* Parse a single operand in an MRI structured control expression. */
4849 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
4866 if (*input_line_pointer == '<')
4868 /* It's just a condition code. */
4869 return parse_mri_condition (pcc);
4872 /* Look ahead for the condition code. */
4873 for (s = input_line_pointer; *s != '\0'; ++s)
4875 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
4880 as_bad ("missing condition code in structured control directive");
4884 *leftstart = input_line_pointer;
4886 if (*leftstop > *leftstart
4887 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
4890 input_line_pointer = s;
4891 if (! parse_mri_condition (pcc))
4894 /* Look ahead for AND or OR or end of line. */
4895 for (s = input_line_pointer; *s != '\0'; ++s)
4897 if ((strncasecmp (s, "AND", 3) == 0
4898 && (s[3] == '.' || ! is_part_of_name (s[3])))
4899 || (strncasecmp (s, "OR", 2) == 0
4900 && (s[2] == '.' || ! is_part_of_name (s[2]))))
4904 *rightstart = input_line_pointer;
4906 if (*rightstop > *rightstart
4907 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
4910 input_line_pointer = s;
4915 #define MCC(b1, b2) (((b1) << 8) | (b2))
4917 /* Swap the sense of a condition. This changes the condition so that
4918 it generates the same result when the operands are swapped. */
4921 swap_mri_condition (cc)
4926 case MCC ('h', 'i'): return MCC ('c', 's');
4927 case MCC ('l', 's'): return MCC ('c', 'c');
4928 case MCC ('c', 'c'): return MCC ('l', 's');
4929 case MCC ('c', 's'): return MCC ('h', 'i');
4930 case MCC ('p', 'l'): return MCC ('m', 'i');
4931 case MCC ('m', 'i'): return MCC ('p', 'l');
4932 case MCC ('g', 'e'): return MCC ('l', 'e');
4933 case MCC ('l', 't'): return MCC ('g', 't');
4934 case MCC ('g', 't'): return MCC ('l', 't');
4935 case MCC ('l', 'e'): return MCC ('g', 'e');
4940 /* Reverse the sense of a condition. */
4943 reverse_mri_condition (cc)
4948 case MCC ('h', 'i'): return MCC ('l', 's');
4949 case MCC ('l', 's'): return MCC ('h', 'i');
4950 case MCC ('c', 'c'): return MCC ('c', 's');
4951 case MCC ('c', 's'): return MCC ('c', 'c');
4952 case MCC ('n', 'e'): return MCC ('e', 'q');
4953 case MCC ('e', 'q'): return MCC ('n', 'e');
4954 case MCC ('v', 'c'): return MCC ('v', 's');
4955 case MCC ('v', 's'): return MCC ('v', 'c');
4956 case MCC ('p', 'l'): return MCC ('m', 'i');
4957 case MCC ('m', 'i'): return MCC ('p', 'l');
4958 case MCC ('g', 'e'): return MCC ('l', 't');
4959 case MCC ('l', 't'): return MCC ('g', 'e');
4960 case MCC ('g', 't'): return MCC ('l', 'e');
4961 case MCC ('l', 'e'): return MCC ('g', 't');
4966 /* Build an MRI structured control expression. This generates test
4967 and branch instructions. It goes to TRUELAB if the condition is
4968 true, and to FALSELAB if the condition is false. Exactly one of
4969 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
4970 is the size qualifier for the expression. EXTENT is the size to
4971 use for the branch. */
4974 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
4975 rightstop, truelab, falselab, extent)
4982 const char *truelab;
4983 const char *falselab;
4989 if (leftstart != NULL)
4991 struct m68k_op leftop, rightop;
4994 /* Swap the compare operands, if necessary, to produce a legal
4995 m68k compare instruction. Comparing a register operand with
4996 a non-register operand requires the register to be on the
4997 right (cmp, cmpa). Comparing an immediate value with
4998 anything requires the immediate value to be on the left
5003 (void) m68k_ip_op (leftstart, &leftop);
5008 (void) m68k_ip_op (rightstart, &rightop);
5011 if (rightop.mode == IMMED
5012 || ((leftop.mode == DREG || leftop.mode == AREG)
5013 && (rightop.mode != DREG && rightop.mode != AREG)))
5017 cc = swap_mri_condition (cc);
5019 leftstart = rightstart;
5022 leftstop = rightstop;
5027 if (truelab == NULL)
5029 cc = reverse_mri_condition (cc);
5033 if (leftstart != NULL)
5035 buf = (char *) xmalloc (20
5036 + (leftstop - leftstart)
5037 + (rightstop - rightstart));
5045 memcpy (s, leftstart, leftstop - leftstart);
5046 s += leftstop - leftstart;
5048 memcpy (s, rightstart, rightstop - rightstart);
5049 s += rightstop - rightstart;
5055 buf = (char *) xmalloc (20 + strlen (truelab));
5063 strcpy (s, truelab);
5068 /* Parse an MRI structured control expression. This generates test
5069 and branch instructions. STOP is where the expression ends. It
5070 goes to TRUELAB if the condition is true, and to FALSELAB if the
5071 condition is false. Exactly one of TRUELAB and FALSELAB will be
5072 NULL, meaning to fall through. QUAL is the size qualifier for the
5073 expression. EXTENT is the size to use for the branch. */
5076 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5079 const char *truelab;
5080 const char *falselab;
5093 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5094 &rightstart, &rightstop))
5100 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5104 if (falselab != NULL)
5107 flab = mri_control_label ();
5109 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5110 rightstop, (const char *) NULL, flab, extent);
5112 input_line_pointer += 3;
5113 if (*input_line_pointer != '.'
5114 || input_line_pointer[1] == '\0')
5118 qual = input_line_pointer[1];
5119 input_line_pointer += 2;
5122 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5123 &rightstart, &rightstop))
5129 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5130 rightstop, truelab, falselab, extent);
5132 if (falselab == NULL)
5135 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5139 if (truelab != NULL)
5142 tlab = mri_control_label ();
5144 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5145 rightstop, tlab, (const char *) NULL, extent);
5147 input_line_pointer += 2;
5148 if (*input_line_pointer != '.'
5149 || input_line_pointer[1] == '\0')
5153 qual = input_line_pointer[1];
5154 input_line_pointer += 2;
5157 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5158 &rightstart, &rightstop))
5164 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5165 rightstop, truelab, falselab, extent);
5167 if (truelab == NULL)
5172 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5173 rightstop, truelab, falselab, extent);
5177 if (input_line_pointer != stop)
5178 as_bad ("syntax error in structured control directive");
5181 /* Handle the MRI IF pseudo-op. This may be a structured control
5182 directive, or it may be a regular assembler conditional, depending
5191 struct mri_control_info *n;
5193 /* A structured control directive must end with THEN with an
5194 optional qualifier. */
5195 s = input_line_pointer;
5196 while (! is_end_of_line[(unsigned char) *s]
5197 && (! flag_mri || *s != '*'))
5200 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5203 if (s - input_line_pointer > 1
5207 if (s - input_line_pointer < 3
5208 || strncasecmp (s - 3, "THEN", 4) != 0)
5212 as_bad ("missing then");
5213 ignore_rest_of_line ();
5217 /* It's a conditional. */
5222 /* Since this might be a conditional if, this pseudo-op will be
5223 called even if we are supported to be ignoring input. Double
5224 check now. Clobber *input_line_pointer so that ignore_input
5225 thinks that this is not a special pseudo-op. */
5226 c = *input_line_pointer;
5227 *input_line_pointer = 0;
5228 if (ignore_input ())
5230 *input_line_pointer = c;
5231 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5232 ++input_line_pointer;
5233 demand_empty_rest_of_line ();
5236 *input_line_pointer = c;
5238 n = push_mri_control (mri_if);
5240 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5241 n->next, s[1] == '.' ? s[2] : '\0');
5244 input_line_pointer = s + 3;
5246 input_line_pointer = s + 1;
5250 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5251 ++input_line_pointer;
5254 demand_empty_rest_of_line ();
5257 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5258 structured IF, associate the ELSE with the IF. Otherwise, assume
5259 it is a conditional else. */
5270 && (mri_control_stack == NULL
5271 || mri_control_stack->type != mri_if
5272 || mri_control_stack->else_seen))
5278 c = *input_line_pointer;
5279 *input_line_pointer = 0;
5280 if (ignore_input ())
5282 *input_line_pointer = c;
5283 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5284 ++input_line_pointer;
5285 demand_empty_rest_of_line ();
5288 *input_line_pointer = c;
5290 if (mri_control_stack == NULL
5291 || mri_control_stack->type != mri_if
5292 || mri_control_stack->else_seen)
5294 as_bad ("else without matching if");
5295 ignore_rest_of_line ();
5299 mri_control_stack->else_seen = 1;
5301 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5304 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5308 colon (mri_control_stack->next);
5312 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5313 ++input_line_pointer;
5316 demand_empty_rest_of_line ();
5319 /* Handle the MRI ENDI pseudo-op. */
5325 if (mri_control_stack == NULL
5326 || mri_control_stack->type != mri_if)
5328 as_bad ("endi without matching if");
5329 ignore_rest_of_line ();
5333 /* ignore_input will not return true for ENDI, so we don't need to
5334 worry about checking it again here. */
5336 if (! mri_control_stack->else_seen)
5337 colon (mri_control_stack->next);
5338 colon (mri_control_stack->bottom);
5344 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5345 ++input_line_pointer;
5348 demand_empty_rest_of_line ();
5351 /* Handle the MRI BREAK pseudo-op. */
5354 s_mri_break (extent)
5357 struct mri_control_info *n;
5361 n = mri_control_stack;
5363 && n->type != mri_for
5364 && n->type != mri_repeat
5365 && n->type != mri_while)
5369 as_bad ("break outside of structured loop");
5370 ignore_rest_of_line ();
5374 buf = (char *) xmalloc (20 + strlen (n->bottom));
5377 sprintf (buf, "bra%s %s", ex, n->bottom);
5383 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5384 ++input_line_pointer;
5387 demand_empty_rest_of_line ();
5390 /* Handle the MRI NEXT pseudo-op. */
5396 struct mri_control_info *n;
5400 n = mri_control_stack;
5402 && n->type != mri_for
5403 && n->type != mri_repeat
5404 && n->type != mri_while)
5408 as_bad ("next outside of structured loop");
5409 ignore_rest_of_line ();
5413 buf = (char *) xmalloc (20 + strlen (n->next));
5416 sprintf (buf, "bra%s %s", ex, n->next);
5422 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5423 ++input_line_pointer;
5426 demand_empty_rest_of_line ();
5429 /* Handle the MRI FOR pseudo-op. */
5435 const char *varstart, *varstop;
5436 const char *initstart, *initstop;
5437 const char *endstart, *endstop;
5438 const char *bystart, *bystop;
5442 struct mri_control_info *n;
5448 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5452 varstart = input_line_pointer;
5454 /* Look for the '='. */
5455 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5456 && *input_line_pointer != '=')
5457 ++input_line_pointer;
5458 if (*input_line_pointer != '=')
5460 as_bad ("missing =");
5461 ignore_rest_of_line ();
5465 varstop = input_line_pointer;
5466 if (varstop > varstart
5467 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5470 ++input_line_pointer;
5472 initstart = input_line_pointer;
5474 /* Look for TO or DOWNTO. */
5477 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5479 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5480 && ! is_part_of_name (input_line_pointer[2]))
5482 initstop = input_line_pointer;
5483 input_line_pointer += 2;
5486 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5487 && ! is_part_of_name (input_line_pointer[6]))
5489 initstop = input_line_pointer;
5491 input_line_pointer += 6;
5494 ++input_line_pointer;
5496 if (initstop == NULL)
5498 as_bad ("missing to or downto");
5499 ignore_rest_of_line ();
5502 if (initstop > initstart
5503 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5507 endstart = input_line_pointer;
5509 /* Look for BY or DO. */
5512 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5514 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5515 && ! is_part_of_name (input_line_pointer[2]))
5517 endstop = input_line_pointer;
5519 input_line_pointer += 2;
5522 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5523 && (input_line_pointer[2] == '.'
5524 || ! is_part_of_name (input_line_pointer[2])))
5526 endstop = input_line_pointer;
5527 input_line_pointer += 2;
5530 ++input_line_pointer;
5532 if (endstop == NULL)
5534 as_bad ("missing do");
5535 ignore_rest_of_line ();
5538 if (endstop > endstart
5539 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5545 bystop = bystart + 2;
5550 bystart = input_line_pointer;
5554 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5556 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5557 && (input_line_pointer[2] == '.'
5558 || ! is_part_of_name (input_line_pointer[2])))
5560 bystop = input_line_pointer;
5561 input_line_pointer += 2;
5564 ++input_line_pointer;
5568 as_bad ("missing do");
5569 ignore_rest_of_line ();
5572 if (bystop > bystart
5573 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5577 if (*input_line_pointer != '.')
5581 extent = input_line_pointer[1];
5582 input_line_pointer += 2;
5585 /* We have fully parsed the FOR operands. Now build the loop. */
5587 n = push_mri_control (mri_for);
5589 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5600 memcpy (s, initstart, initstop - initstart);
5601 s += initstop - initstart;
5603 memcpy (s, varstart, varstop - varstart);
5604 s += varstop - varstart;
5618 memcpy (s, endstart, endstop - endstart);
5619 s += endstop - endstart;
5621 memcpy (s, varstart, varstop - varstart);
5622 s += varstop - varstart;
5630 sprintf (buf, "blt%s %s", ex, n->bottom);
5632 sprintf (buf, "bgt%s %s", ex, n->bottom);
5635 /* Put together the add or sub instruction used by ENDF. */
5645 memcpy (s, bystart, bystop - bystart);
5646 s += bystop - bystart;
5648 memcpy (s, varstart, varstop - varstart);
5649 s += varstop - varstart;
5655 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5656 ++input_line_pointer;
5659 demand_empty_rest_of_line ();
5662 /* Handle the MRI ENDF pseudo-op. */
5668 if (mri_control_stack == NULL
5669 || mri_control_stack->type != mri_for)
5671 as_bad ("endf without for");
5672 ignore_rest_of_line ();
5676 colon (mri_control_stack->next);
5678 md_assemble (mri_control_stack->incr);
5680 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
5681 md_assemble (mri_control_stack->incr);
5683 free (mri_control_stack->incr);
5685 colon (mri_control_stack->bottom);
5691 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5692 ++input_line_pointer;
5695 demand_empty_rest_of_line ();
5698 /* Handle the MRI REPEAT pseudo-op. */
5701 s_mri_repeat (ignore)
5704 struct mri_control_info *n;
5706 n = push_mri_control (mri_repeat);
5710 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5711 ++input_line_pointer;
5713 demand_empty_rest_of_line ();
5716 /* Handle the MRI UNTIL pseudo-op. */
5724 if (mri_control_stack == NULL
5725 || mri_control_stack->type != mri_repeat)
5727 as_bad ("until without repeat");
5728 ignore_rest_of_line ();
5732 colon (mri_control_stack->next);
5734 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
5737 parse_mri_control_expression (s, qual, (const char *) NULL,
5738 mri_control_stack->top, '\0');
5740 colon (mri_control_stack->bottom);
5742 input_line_pointer = s;
5748 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5749 ++input_line_pointer;
5752 demand_empty_rest_of_line ();
5755 /* Handle the MRI WHILE pseudo-op. */
5763 struct mri_control_info *n;
5765 s = input_line_pointer;
5766 while (! is_end_of_line[(unsigned char) *s]
5767 && (! flag_mri || *s != '*'))
5770 while (*s == ' ' || *s == '\t')
5772 if (s - input_line_pointer > 1
5775 if (s - input_line_pointer < 2
5776 || strncasecmp (s - 1, "DO", 2) != 0)
5778 as_bad ("missing do");
5779 ignore_rest_of_line ();
5783 n = push_mri_control (mri_while);
5787 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
5788 s[1] == '.' ? s[2] : '\0');
5790 input_line_pointer = s + 1;
5791 if (*input_line_pointer == '.')
5792 input_line_pointer += 2;
5796 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5797 ++input_line_pointer;
5800 demand_empty_rest_of_line ();
5803 /* Handle the MRI ENDW pseudo-op. */
5811 if (mri_control_stack == NULL
5812 || mri_control_stack->type != mri_while)
5814 as_bad ("endw without while");
5815 ignore_rest_of_line ();
5819 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
5820 sprintf (buf, "bra %s", mri_control_stack->next);
5824 colon (mri_control_stack->bottom);
5830 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5831 ++input_line_pointer;
5834 demand_empty_rest_of_line ();
5839 * Invocation line includes a switch not recognized by the base assembler.
5840 * See if it's a processor-specific option. These are:
5842 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
5843 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
5844 * Select the architecture. Instructions or features not
5845 * supported by the selected architecture cause fatal
5846 * errors. More than one may be specified. The default is
5847 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
5848 * for -m68000, and -m68882 is a synonym for -m68881.
5849 * -[A]m[c]no-68851, -[A]m[c]no-68881
5850 * Don't accept 688?1 instructions. (The "c" is kind of silly,
5851 * so don't use or document it, but that's the way the parsing
5854 * -pic Indicates PIC.
5855 * -k Indicates PIC. (Sun 3 only.)
5860 CONST char *md_shortopts = "lSA:m:kQ:V";
5862 CONST char *md_shortopts = "lSA:m:k";
5865 struct option md_longopts[] = {
5866 #define OPTION_PIC (OPTION_MD_BASE)
5867 {"pic", no_argument, NULL, OPTION_PIC},
5868 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
5869 {"register-prefix-optional", no_argument, NULL,
5870 OPTION_REGISTER_PREFIX_OPTIONAL},
5871 {NULL, no_argument, NULL, 0}
5873 size_t md_longopts_size = sizeof(md_longopts);
5876 md_parse_option (c, arg)
5882 case 'l': /* -l means keep external to 2 bit offset
5883 rather than 16 bit one */
5884 flag_short_refs = 1;
5887 case 'S': /* -S means that jbsr's always turn into
5889 flag_long_jumps = 1;
5895 /* intentional fall-through */
5898 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
5902 const char *oarg = arg;
5908 if (arg[0] == 'c' && arg[1] == '6')
5911 for (i = 0; i < n_archs; i++)
5912 if (!strcmp (arg, archs[i].name))
5917 as_bad ("unrecognized option `%s'", oarg);
5920 arch = archs[i].arch;
5923 else if (arch == m68851)
5932 if (arg[0] == 'c' && arg[1] == '6')
5935 for (i = 0; i < n_archs; i++)
5936 if (!strcmp (arg, archs[i].name))
5938 unsigned long arch = archs[i].arch;
5939 if (cpu_of_arch (arch))
5940 /* It's a cpu spec. */
5942 current_architecture &= ~m68000up;
5943 current_architecture |= arch;
5945 else if (arch == m68881)
5947 current_architecture |= m68881;
5950 else if (arch == m68851)
5952 current_architecture |= m68851;
5962 as_bad ("unrecognized architecture specification `%s'", arg);
5971 break; /* -pic, Position Independent Code */
5973 case OPTION_REGISTER_PREFIX_OPTIONAL:
5974 flag_reg_prefix_optional = 1;
5989 md_show_usage (stream)
5994 -l use 1 word for refs to undefined symbols [default 2]\n\
5995 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
5996 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
5998 specify variant of 680X0 architecture [default 68020]\n\
5999 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6000 target has/lacks floating-point coprocessor\n\
6001 [default yes for 68020, 68030, and cpu32]\n");
6003 -m68851 | -mno-68851\n\
6004 target has/lacks memory-management unit coprocessor\n\
6005 [default yes for 68020 and up]\n\
6006 -pic, -k generate position independent code\n\
6007 -S turn jbsr into jsr\n\
6008 --register-prefix-optional\n\
6009 recognize register names without prefix character\n");
6014 /* TEST2: Test md_assemble() */
6015 /* Warning, this routine probably doesn't work anymore */
6019 struct m68k_it the_ins;
6027 if (!gets (buf) || !*buf)
6029 if (buf[0] == '|' || buf[1] == '.')
6031 for (cp = buf; *cp; cp++)
6036 memset (&the_ins, '\0', sizeof (the_ins));
6037 m68k_ip (&the_ins, buf);
6040 printf ("Error %s in %s\n", the_ins.error, buf);
6044 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6045 for (n = 0; n < the_ins.numo; n++)
6046 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6048 print_the_insn (&the_ins.opcode[0], stdout);
6049 (void) putchar ('\n');
6051 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6053 if (the_ins.operands[n].error)
6055 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6058 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6059 if (the_ins.operands[n].b_const)
6060 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6061 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6062 if (the_ins.operands[n].b_iadd)
6063 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6064 (void) putchar ('\n');
6076 while (*str && *str != ' ')
6078 if (str[-1] == ':' || str[1] == '=')
6085 /* Possible states for relaxation:
6087 0 0 branch offset byte (bra, etc)
6091 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6095 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6102 /* We have no need to default values of symbols. */
6106 md_undefined_symbol (name)
6112 /* Round up a section size to the appropriate boundary. */
6114 md_section_align (segment, size)
6118 return size; /* Byte alignment is fine */
6121 /* Exactly what point is a PC-relative offset relative TO?
6122 On the 68k, it is relative to the address of the first extension
6123 word. The difference between the addresses of the offset and the
6124 first extension word is stored in fx_pcrel_adjust. */
6126 md_pcrel_from (fixP)
6131 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6133 adjust = fixP->fx_pcrel_adjust;
6136 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6139 #ifndef BFD_ASSEMBLER
6142 tc_coff_symbol_emit_hook (ignore)
6148 tc_coff_sizemachdep (frag)
6151 switch (frag->fr_subtype & 0x3)
6166 /* end of tc-m68k.c */