1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 #include "safe-ctype.h"
27 #include "dwarf2dbg.h"
28 #include "dw2gencfi.h"
30 #include "opcode/m68k.h"
31 #include "m68k-parse.h"
42 static void m68k_elf_cons (int);
45 /* This string holds the chars that always start a comment. If the
46 pre-processor is disabled, these aren't very useful. The macro
47 tc_comment_chars points to this. We use this, rather than the
48 usual comment_chars, so that the --bitwise-or option will work. */
49 #if defined (TE_SVR4) || defined (TE_DELTA)
50 const char *m68k_comment_chars = "|#";
52 const char *m68k_comment_chars = "|";
55 /* This array holds the chars that only start a comment at the beginning of
56 a line. If the line seems to have the form '# 123 filename'
57 .line and .file directives will appear in the pre-processed output */
58 /* Note that input_file.c hand checks for '#' at the beginning of the
59 first line of the input file. This is because the compiler outputs
60 #NO_APP at the beginning of its output. */
61 /* Also note that comments like this one will always work. */
62 const char line_comment_chars[] = "#*";
64 const char line_separator_chars[] = ";";
66 /* Chars that can be used to separate mant from exp in floating point nums. */
67 const char EXP_CHARS[] = "eE";
69 /* Chars that mean this number is a floating point constant, as
70 in "0f12.456" or "0d1.2345e12". */
72 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
74 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
75 changed in read.c . Ideally it shouldn't have to know about it at all,
76 but nothing is ideal around here. */
78 /* Are we trying to generate PIC code? If so, absolute references
79 ought to be made into linkage table references or pc-relative
80 references. Not implemented. For ELF there are other means
81 to denote pic relocations. */
84 static int flag_short_refs; /* -l option. */
85 static int flag_long_jumps; /* -S option. */
86 static int flag_keep_pcrel; /* --pcrel option. */
88 #ifdef REGISTER_PREFIX_OPTIONAL
89 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
91 int flag_reg_prefix_optional;
94 /* Whether --register-prefix-optional was used on the command line. */
95 static int reg_prefix_optional_seen;
97 /* The floating point coprocessor to use by default. */
98 static enum m68k_register m68k_float_copnum = COP1;
100 /* If this is non-zero, then references to number(%pc) will be taken
101 to refer to number, rather than to %pc + number. */
102 static int m68k_abspcadd;
104 /* If this is non-zero, then the quick forms of the move, add, and sub
105 instructions are used when possible. */
106 static int m68k_quick = 1;
108 /* If this is non-zero, then if the size is not specified for a base
109 or outer displacement, the assembler assumes that the size should
111 static int m68k_rel32 = 1;
113 /* This is non-zero if m68k_rel32 was set from the command line. */
114 static int m68k_rel32_from_cmdline;
116 /* The default width to use for an index register when using a base
118 static enum m68k_size m68k_index_width_default = SIZE_LONG;
120 /* We want to warn if any text labels are misaligned. In order to get
121 the right line number, we need to record the line number for each
125 struct label_line *next;
132 /* The list of labels. */
134 static struct label_line *labels;
136 /* The current label. */
138 static struct label_line *current_label;
140 /* Pointer to list holding the opcodes sorted by name. */
141 static struct m68k_opcode const ** m68k_sorted_opcodes;
143 /* Its an arbitrary name: This means I don't approve of it.
145 static struct obstack robyn;
149 const char *m_operands;
150 unsigned long m_opcode;
154 struct m68k_incant *m_next;
157 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
158 #define gettwo(x) (((x)->m_opcode)&0xffff)
160 static const enum m68k_register m68000_ctrl[] = { 0 };
161 static const enum m68k_register m68010_ctrl[] = {
165 static const enum m68k_register m68020_ctrl[] = {
166 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
169 static const enum m68k_register m68040_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
171 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
174 static const enum m68k_register m68060_ctrl[] = {
175 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
176 USP, VBR, URP, SRP, PCR,
179 static const enum m68k_register mcf_ctrl[] = {
180 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
181 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
184 static const enum m68k_register mcf51_ctrl[] = {
188 static const enum m68k_register mcf5206_ctrl[] = {
189 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
192 static const enum m68k_register mcf5208_ctrl[] = {
193 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
196 static const enum m68k_register mcf5210a_ctrl[] = {
197 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
200 static const enum m68k_register mcf5213_ctrl[] = {
201 VBR, RAMBAR, RAMBAR1, FLASHBAR,
204 static const enum m68k_register mcf5216_ctrl[] = {
205 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
208 static const enum m68k_register mcf5221x_ctrl[] = {
209 VBR, FLASHBAR, RAMBAR, RAMBAR1,
212 static const enum m68k_register mcf52223_ctrl[] = {
213 VBR, FLASHBAR, RAMBAR, RAMBAR1,
216 static const enum m68k_register mcf52235_ctrl[] = {
217 VBR, FLASHBAR, RAMBAR, RAMBAR1,
220 static const enum m68k_register mcf5225_ctrl[] = {
221 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
224 static const enum m68k_register mcf52259_ctrl[] = {
225 VBR, FLASHBAR, RAMBAR, RAMBAR1,
228 static const enum m68k_register mcf52277_ctrl[] = {
229 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
232 static const enum m68k_register mcf5235_ctrl[] = {
233 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
236 static const enum m68k_register mcf5249_ctrl[] = {
237 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
240 static const enum m68k_register mcf5250_ctrl[] = {
244 static const enum m68k_register mcf5253_ctrl[] = {
245 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
248 static const enum m68k_register mcf5271_ctrl[] = {
249 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
252 static const enum m68k_register mcf5272_ctrl[] = {
253 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
256 static const enum m68k_register mcf5275_ctrl[] = {
257 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
260 static const enum m68k_register mcf5282_ctrl[] = {
261 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
264 static const enum m68k_register mcf53017_ctrl[] = {
265 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
268 static const enum m68k_register mcf5307_ctrl[] = {
269 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
272 static const enum m68k_register mcf5329_ctrl[] = {
273 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
276 static const enum m68k_register mcf5373_ctrl[] = {
277 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
280 static const enum m68k_register mcfv4e_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
284 MPCR /* Multiprocessor Control register */,
285 EDRAMBAR /* Embedded DRAM Base Address Register */,
286 /* Permutation control registers. */
287 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
288 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
290 TC /* ASID */, BUSCR /* MMUBAR */,
291 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
292 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
293 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
296 static const enum m68k_register mcf5407_ctrl[] = {
297 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
298 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
301 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
302 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
305 static const enum m68k_register mcf54418_ctrl[] = {
306 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
309 TC /* ASID */, BUSCR /* MMUBAR */,
310 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
311 RAMBAR /* RAMBAR1 */,
314 static const enum m68k_register mcf54455_ctrl[] = {
315 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
318 TC /* ASID */, BUSCR /* MMUBAR */,
319 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
320 RAMBAR /* RAMBAR1 */,
323 static const enum m68k_register mcf5475_ctrl[] = {
324 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
325 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
327 TC /* ASID */, BUSCR /* MMUBAR */,
328 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
329 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
332 static const enum m68k_register mcf5485_ctrl[] = {
333 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
334 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
336 TC /* ASID */, BUSCR /* MMUBAR */,
337 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
338 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
341 static const enum m68k_register fido_ctrl[] = {
342 SFC, DFC, USP, VBR, CAC, MBO,
345 #define cpu32_ctrl m68010_ctrl
347 static const enum m68k_register *control_regs;
349 /* Internal form of a 68020 instruction. */
353 const char *args; /* List of opcode info. */
356 int numo; /* Number of shorts in opcode. */
359 struct m68k_op operands[6];
361 int nexp; /* Number of exprs in use. */
362 struct m68k_exp exprs[4];
364 int nfrag; /* Number of frags we have to produce. */
367 int fragoff; /* Where in the current opcode the frag ends. */
374 int nrel; /* Num of reloc strucs in use. */
381 /* In a pc relative address the difference between the address
382 of the offset and the address that the offset is relative
383 to. This depends on the addressing mode. Basically this
384 is the value to put in the offset field to address the
385 first byte of the offset, without regarding the special
386 significance of some values (in the branch instruction, for
390 /* Whether this expression needs special pic relocation, and if
392 enum pic_relocation pic_reloc;
395 reloc[5]; /* Five is enough??? */
398 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
399 #define float_of_arch(x) ((x) & mfloat)
400 #define mmu_of_arch(x) ((x) & mmmu)
401 #define arch_coldfire_p(x) ((x) & mcfisa_a)
402 #define arch_coldfire_fpu(x) ((x) & cfloat)
404 /* Macros for determining if cpu supports a specific addressing mode. */
405 #define HAVE_LONG_DISP(x) \
406 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
407 #define HAVE_LONG_CALL(x) \
408 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
409 #define HAVE_LONG_COND(x) \
410 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
411 #define HAVE_LONG_BRANCH(x) \
412 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
413 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
415 static struct m68k_it the_ins; /* The instruction being assembled. */
417 #define op(ex) ((ex)->exp.X_op)
418 #define adds(ex) ((ex)->exp.X_add_symbol)
419 #define subs(ex) ((ex)->exp.X_op_symbol)
420 #define offs(ex) ((ex)->exp.X_add_number)
422 /* Macros for adding things to the m68k_it struct. */
423 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
425 /* Like addword, but goes BEFORE general operands. */
428 insop (int w, const struct m68k_incant *opcode)
431 for (z = the_ins.numo; z > opcode->m_codenum; --z)
432 the_ins.opcode[z] = the_ins.opcode[z - 1];
433 for (z = 0; z < the_ins.nrel; z++)
434 the_ins.reloc[z].n += 2;
435 for (z = 0; z < the_ins.nfrag; z++)
436 the_ins.fragb[z].fragoff++;
437 the_ins.opcode[opcode->m_codenum] = w;
441 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
444 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
446 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
447 ? the_ins.numo * 2 - 1
449 ? the_ins.numo * 2 + 1
450 : the_ins.numo * 2));
451 the_ins.reloc[the_ins.nrel].exp = exp->exp;
452 the_ins.reloc[the_ins.nrel].wid = width;
453 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
455 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
457 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
460 /* Cause an extra frag to be generated here, inserting up to 10 bytes
461 (that value is chosen in the frag_var call in md_assemble). TYPE
462 is the subtype of the frag to be generated; its primary type is
463 rs_machine_dependent.
465 The TYPE parameter is also used by md_convert_frag_1 and
466 md_estimate_size_before_relax. The appropriate type of fixup will
467 be emitted by md_convert_frag_1.
469 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
471 add_frag (symbolS *add, offsetT off, int type)
473 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
474 the_ins.fragb[the_ins.nfrag].fadd = add;
475 the_ins.fragb[the_ins.nfrag].foff = off;
476 the_ins.fragb[the_ins.nfrag++].fragty = type;
480 (op (ex) != O_constant && op (ex) != O_big)
482 static char *crack_operand (char *str, struct m68k_op *opP);
483 static int get_num (struct m68k_exp *exp, int ok);
484 static int reverse_16_bits (int in);
485 static int reverse_8_bits (int in);
486 static void install_gen_operand (int mode, int val);
487 static void install_operand (int mode, int val);
488 static void s_bss (int);
489 static void s_data1 (int);
490 static void s_data2 (int);
491 static void s_even (int);
492 static void s_proc (int);
493 static void s_chip (int);
494 static void s_fopt (int);
495 static void s_opt (int);
496 static void s_reg (int);
497 static void s_restore (int);
498 static void s_save (int);
499 static void s_mri_if (int);
500 static void s_mri_else (int);
501 static void s_mri_endi (int);
502 static void s_mri_break (int);
503 static void s_mri_next (int);
504 static void s_mri_for (int);
505 static void s_mri_endf (int);
506 static void s_mri_repeat (int);
507 static void s_mri_until (int);
508 static void s_mri_while (int);
509 static void s_mri_endw (int);
510 static void s_m68k_cpu (int);
511 static void s_m68k_arch (int);
515 unsigned long arch; /* Architecture features. */
516 const enum m68k_register *control_regs; /* Control regs on chip */
517 const char *name; /* Name */
518 int alias; /* Alias for a cannonical name. If 1, then
519 succeeds canonical name, if -1 then
520 succeeds canonical name, if <-1 ||>1 this is a
521 deprecated name, and the next/previous name
525 /* We hold flags for features explicitly enabled and explicitly
527 static int current_architecture;
528 static int not_current_architecture;
529 static const struct m68k_cpu *selected_arch;
530 static const struct m68k_cpu *selected_cpu;
531 static int initialized;
533 /* Architecture models. */
534 static const struct m68k_cpu m68k_archs[] =
536 {m68000, m68000_ctrl, "68000", 0},
537 {m68010, m68010_ctrl, "68010", 0},
538 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
539 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
540 {m68040, m68040_ctrl, "68040", 0},
541 {m68060, m68060_ctrl, "68060", 0},
542 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
543 {fido_a, fido_ctrl, "fidoa", 0},
544 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
545 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
546 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
547 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
548 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
549 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
553 /* For -mno-mac we want to turn off all types of mac. */
554 static const unsigned no_mac = mcfmac | mcfemac;
556 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
558 static const struct m68k_cpu m68k_extensions[] =
560 {m68851, NULL, "68851", -1},
561 {m68881, NULL, "68881", -1},
562 {m68881, NULL, "68882", -1},
564 {cfloat|m68881, NULL, "float", 0},
566 {mcfhwdiv, NULL, "div", 1},
567 {mcfusp, NULL, "usp", 1},
568 {mcfmac, (void *)&no_mac, "mac", 1},
569 {mcfemac, NULL, "emac", 1},
575 static const struct m68k_cpu m68k_cpus[] =
577 {m68000, m68000_ctrl, "68000", 0},
578 {m68000, m68000_ctrl, "68ec000", 1},
579 {m68000, m68000_ctrl, "68hc000", 1},
580 {m68000, m68000_ctrl, "68hc001", 1},
581 {m68000, m68000_ctrl, "68008", 1},
582 {m68000, m68000_ctrl, "68302", 1},
583 {m68000, m68000_ctrl, "68306", 1},
584 {m68000, m68000_ctrl, "68307", 1},
585 {m68000, m68000_ctrl, "68322", 1},
586 {m68000, m68000_ctrl, "68356", 1},
587 {m68010, m68010_ctrl, "68010", 0},
588 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
589 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
590 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
591 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
592 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
593 {m68040, m68040_ctrl, "68040", 0},
594 {m68040, m68040_ctrl, "68ec040", 1},
595 {m68060, m68060_ctrl, "68060", 0},
596 {m68060, m68060_ctrl, "68ec060", 1},
598 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
599 {cpu32|m68881, cpu32_ctrl, "68330", 1},
600 {cpu32|m68881, cpu32_ctrl, "68331", 1},
601 {cpu32|m68881, cpu32_ctrl, "68332", 1},
602 {cpu32|m68881, cpu32_ctrl, "68333", 1},
603 {cpu32|m68881, cpu32_ctrl, "68334", 1},
604 {cpu32|m68881, cpu32_ctrl, "68336", 1},
605 {cpu32|m68881, cpu32_ctrl, "68340", 1},
606 {cpu32|m68881, cpu32_ctrl, "68341", 1},
607 {cpu32|m68881, cpu32_ctrl, "68349", 1},
608 {cpu32|m68881, cpu32_ctrl, "68360", 1},
610 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
611 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
612 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
613 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
614 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
615 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
617 {mcfisa_a, mcf_ctrl, "5200", 0},
618 {mcfisa_a, mcf_ctrl, "5202", 1},
619 {mcfisa_a, mcf_ctrl, "5204", 1},
620 {mcfisa_a, mcf5206_ctrl, "5206", 1},
622 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
624 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
651 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
654 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
660 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
661 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
662 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
664 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
665 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
666 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
667 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
669 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
674 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
679 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
682 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
684 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
687 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
689 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
692 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
694 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
695 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
696 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
697 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
699 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
700 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
701 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
703 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
705 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
706 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1},
707 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1},
708 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1},
709 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0},
711 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
712 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
713 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
714 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
715 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
716 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
718 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
719 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
720 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
721 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
722 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
723 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
726 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
727 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
728 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
729 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
730 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
731 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
732 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
734 {fido_a, fido_ctrl, "fidoa", 0},
735 {fido_a, fido_ctrl, "fido", 1},
740 static const struct m68k_cpu *m68k_lookup_cpu
741 (const char *, const struct m68k_cpu *, int, int *);
742 static int m68k_set_arch (const char *, int, int);
743 static int m68k_set_cpu (const char *, int, int);
744 static int m68k_set_extension (const char *, int, int);
745 static void m68k_init_arch (void);
747 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
748 architecture and we have a lot of relaxation modes. */
750 /* Macros used in the relaxation code. */
751 #define TAB(x,y) (((x) << 2) + (y))
752 #define TABTYPE(x) ((x) >> 2)
754 /* Relaxation states. */
760 /* Here are all the relaxation modes we support. First we can relax ordinary
761 branches. On 68020 and higher and on CPU32 all branch instructions take
762 three forms, so on these CPUs all branches always remain as such. When we
763 have to expand to the LONG form on a 68000, though, we substitute an
764 absolute jump instead. This is a direct replacement for unconditional
765 branches and a branch over a jump for conditional branches. However, if the
766 user requires PIC and disables this with --pcrel, we can only relax between
767 BYTE and SHORT forms, punting if that isn't enough. This gives us four
768 different relaxation modes for branches: */
770 #define BRANCHBWL 0 /* Branch byte, word, or long. */
771 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
772 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
773 #define BRANCHBW 3 /* Branch byte or word. */
775 /* We also relax coprocessor branches and DBcc's. All CPUs that support
776 coprocessor branches support them in word and long forms, so we have only
777 one relaxation mode for them. DBcc's are word only on all CPUs. We can
778 relax them to the LONG form with a branch-around sequence. This sequence
779 can use a long branch (if available) or an absolute jump (if acceptable).
780 This gives us two relaxation modes. If long branches are not available and
781 absolute jumps are not acceptable, we don't relax DBcc's. */
783 #define FBRANCH 4 /* Coprocessor branch. */
784 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
785 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
787 /* That's all for instruction relaxation. However, we also relax PC-relative
788 operands. Specifically, we have three operand relaxation modes. On the
789 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
790 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
791 two. Also PC+displacement+index operands in their simple form (with a non-
792 suppressed index without memory indirection) are supported on all CPUs, but
793 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
794 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
795 form of the PC+displacement+index operand. Finally, some absolute operands
796 can be relaxed down to 16-bit PC-relative. */
798 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
799 #define PCINDEX 8 /* PC + displacement + index. */
800 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
802 /* This relaxation is required for branches where there is no long
803 branch and we are in pcrel mode. We generate a bne/beq pair. */
804 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
807 /* Note that calls to frag_var need to specify the maximum expansion
808 needed; this is currently 12 bytes for bne/beq pair. */
809 #define FRAG_VAR_SIZE 12
812 How far Forward this mode will reach:
813 How far Backward this mode will reach:
814 How many bytes this mode will add to the size of the frag
815 Which mode to go to if the offset won't fit in this one
817 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
818 relax_typeS md_relax_table[] =
820 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
821 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
825 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
826 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
830 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
831 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
835 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
840 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
841 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
845 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
846 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
850 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
851 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
855 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
856 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
860 { 125, -130, 0, TAB (PCINDEX, SHORT) },
861 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
865 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
866 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
870 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
871 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
876 /* These are the machine dependent pseudo-ops. These are included so
877 the assembler can work on the output from the SUN C compiler, which
880 /* This table describes all the machine specific pseudo-ops the assembler
881 has to support. The fields are:
882 pseudo-op name without dot
883 function to call to execute this pseudo-op
884 Integer arg to pass to the function. */
885 const pseudo_typeS md_pseudo_table[] =
887 {"data1", s_data1, 0},
888 {"data2", s_data2, 0},
891 {"skip", s_space, 0},
893 #if defined (TE_SUN3) || defined (OBJ_ELF)
894 {"align", s_align_bytes, 0},
897 {"swbeg", s_ignore, 0},
898 {"long", m68k_elf_cons, 4},
900 {"extend", float_cons, 'x'},
901 {"ldouble", float_cons, 'x'},
903 {"arch", s_m68k_arch, 0},
904 {"cpu", s_m68k_cpu, 0},
906 /* The following pseudo-ops are supported for MRI compatibility. */
908 {"comline", s_space, 1},
910 {"mask2", s_ignore, 0},
913 {"restore", s_restore, 0},
917 {"if.b", s_mri_if, 'b'},
918 {"if.w", s_mri_if, 'w'},
919 {"if.l", s_mri_if, 'l'},
920 {"else", s_mri_else, 0},
921 {"else.s", s_mri_else, 's'},
922 {"else.l", s_mri_else, 'l'},
923 {"endi", s_mri_endi, 0},
924 {"break", s_mri_break, 0},
925 {"break.s", s_mri_break, 's'},
926 {"break.l", s_mri_break, 'l'},
927 {"next", s_mri_next, 0},
928 {"next.s", s_mri_next, 's'},
929 {"next.l", s_mri_next, 'l'},
930 {"for", s_mri_for, 0},
931 {"for.b", s_mri_for, 'b'},
932 {"for.w", s_mri_for, 'w'},
933 {"for.l", s_mri_for, 'l'},
934 {"endf", s_mri_endf, 0},
935 {"repeat", s_mri_repeat, 0},
936 {"until", s_mri_until, 0},
937 {"until.b", s_mri_until, 'b'},
938 {"until.w", s_mri_until, 'w'},
939 {"until.l", s_mri_until, 'l'},
940 {"while", s_mri_while, 0},
941 {"while.b", s_mri_while, 'b'},
942 {"while.w", s_mri_while, 'w'},
943 {"while.l", s_mri_while, 'l'},
944 {"endw", s_mri_endw, 0},
949 /* The mote pseudo ops are put into the opcode table, since they
950 don't start with a . they look like opcodes to gas. */
952 const pseudo_typeS mote_pseudo_table[] =
965 {"xdef", s_globl, 0},
967 {"align", s_align_bytes, 0},
969 {"align", s_align_ptwo, 0},
972 {"sect", obj_coff_section, 0},
973 {"section", obj_coff_section, 0},
978 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
979 gives identical results to a 32-bit host. */
980 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
981 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
983 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
984 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
985 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
986 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
988 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
989 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
990 #define islong(x) (1)
992 static char notend_table[256];
993 static char alt_notend_table[256];
995 (! (notend_table[(unsigned char) *s] \
997 && alt_notend_table[(unsigned char) s[1]])))
1001 /* Return zero if the reference to SYMBOL from within the same segment may
1004 /* On an ELF system, we can't relax an externally visible symbol,
1005 because it may be overridden by a shared library. However, if
1006 TARGET_OS is "elf", then we presume that we are assembling for an
1007 embedded system, in which case we don't have to worry about shared
1008 libraries, and we can relax any external sym. */
1010 #define relaxable_symbol(symbol) \
1011 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
1012 || S_IS_WEAK (symbol)))
1014 /* Compute the relocation code for a fixup of SIZE bytes, using pc
1015 relative relocation if PCREL is non-zero. PIC says whether a special
1016 pic relocation was requested. */
1018 static bfd_reloc_code_real_type
1019 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
1027 return BFD_RELOC_8_GOT_PCREL;
1029 return BFD_RELOC_16_GOT_PCREL;
1031 return BFD_RELOC_32_GOT_PCREL;
1039 return BFD_RELOC_8_GOTOFF;
1041 return BFD_RELOC_16_GOTOFF;
1043 return BFD_RELOC_32_GOTOFF;
1051 return BFD_RELOC_8_PLT_PCREL;
1053 return BFD_RELOC_16_PLT_PCREL;
1055 return BFD_RELOC_32_PLT_PCREL;
1063 return BFD_RELOC_8_PLTOFF;
1065 return BFD_RELOC_16_PLTOFF;
1067 return BFD_RELOC_32_PLTOFF;
1075 return BFD_RELOC_68K_TLS_GD8;
1077 return BFD_RELOC_68K_TLS_GD16;
1079 return BFD_RELOC_68K_TLS_GD32;
1087 return BFD_RELOC_68K_TLS_LDM8;
1089 return BFD_RELOC_68K_TLS_LDM16;
1091 return BFD_RELOC_68K_TLS_LDM32;
1099 return BFD_RELOC_68K_TLS_LDO8;
1101 return BFD_RELOC_68K_TLS_LDO16;
1103 return BFD_RELOC_68K_TLS_LDO32;
1111 return BFD_RELOC_68K_TLS_IE8;
1113 return BFD_RELOC_68K_TLS_IE16;
1115 return BFD_RELOC_68K_TLS_IE32;
1123 return BFD_RELOC_68K_TLS_LE8;
1125 return BFD_RELOC_68K_TLS_LE16;
1127 return BFD_RELOC_68K_TLS_LE32;
1137 return BFD_RELOC_8_PCREL;
1139 return BFD_RELOC_16_PCREL;
1141 return BFD_RELOC_32_PCREL;
1151 return BFD_RELOC_16;
1153 return BFD_RELOC_32;
1160 if (pic == pic_none)
1161 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1163 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1167 if (pic == pic_none)
1168 as_bad (_("Can not do %d byte relocation"), size);
1170 as_bad (_("Can not do %d byte pic relocation"), size);
1173 return BFD_RELOC_NONE;
1176 /* Here we decide which fixups can be adjusted to make them relative
1177 to the beginning of the section instead of the symbol. Basically
1178 we need to make sure that the dynamic relocations are done
1179 correctly, so in some cases we force the original symbol to be
1182 tc_m68k_fix_adjustable (fixS *fixP)
1184 /* Adjust_reloc_syms doesn't know about the GOT. */
1185 switch (fixP->fx_r_type)
1187 case BFD_RELOC_8_GOT_PCREL:
1188 case BFD_RELOC_16_GOT_PCREL:
1189 case BFD_RELOC_32_GOT_PCREL:
1190 case BFD_RELOC_8_GOTOFF:
1191 case BFD_RELOC_16_GOTOFF:
1192 case BFD_RELOC_32_GOTOFF:
1193 case BFD_RELOC_8_PLT_PCREL:
1194 case BFD_RELOC_16_PLT_PCREL:
1195 case BFD_RELOC_32_PLT_PCREL:
1196 case BFD_RELOC_8_PLTOFF:
1197 case BFD_RELOC_16_PLTOFF:
1198 case BFD_RELOC_32_PLTOFF:
1199 case BFD_RELOC_68K_TLS_GD32:
1200 case BFD_RELOC_68K_TLS_GD16:
1201 case BFD_RELOC_68K_TLS_GD8:
1202 case BFD_RELOC_68K_TLS_LDM32:
1203 case BFD_RELOC_68K_TLS_LDM16:
1204 case BFD_RELOC_68K_TLS_LDM8:
1205 case BFD_RELOC_68K_TLS_LDO32:
1206 case BFD_RELOC_68K_TLS_LDO16:
1207 case BFD_RELOC_68K_TLS_LDO8:
1208 case BFD_RELOC_68K_TLS_IE32:
1209 case BFD_RELOC_68K_TLS_IE16:
1210 case BFD_RELOC_68K_TLS_IE8:
1211 case BFD_RELOC_68K_TLS_LE32:
1212 case BFD_RELOC_68K_TLS_LE16:
1213 case BFD_RELOC_68K_TLS_LE8:
1216 case BFD_RELOC_VTABLE_INHERIT:
1217 case BFD_RELOC_VTABLE_ENTRY:
1225 #else /* !OBJ_ELF */
1227 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1229 /* PR gas/3041 Weak symbols are not relaxable
1230 because they must be treated as extern. */
1231 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1233 #endif /* OBJ_ELF */
1236 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1239 bfd_reloc_code_real_type code;
1241 /* If the tcbit is set, then this was a fixup of a negative value
1242 that was never resolved. We do not have a reloc to handle this,
1243 so just return. We assume that other code will have detected this
1244 situation and produced a helpful error message, so we just tell the
1245 user that the reloc cannot be produced. */
1249 as_bad_where (fixp->fx_file, fixp->fx_line,
1250 _("Unable to produce reloc against symbol '%s'"),
1251 S_GET_NAME (fixp->fx_addsy));
1255 if (fixp->fx_r_type != BFD_RELOC_NONE)
1257 code = fixp->fx_r_type;
1259 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1260 that fixup_segment converted a non-PC relative reloc into a
1261 PC relative reloc. In such a case, we need to convert the
1268 code = BFD_RELOC_8_PCREL;
1271 code = BFD_RELOC_16_PCREL;
1274 code = BFD_RELOC_32_PCREL;
1276 case BFD_RELOC_8_PCREL:
1277 case BFD_RELOC_16_PCREL:
1278 case BFD_RELOC_32_PCREL:
1279 case BFD_RELOC_8_GOT_PCREL:
1280 case BFD_RELOC_16_GOT_PCREL:
1281 case BFD_RELOC_32_GOT_PCREL:
1282 case BFD_RELOC_8_GOTOFF:
1283 case BFD_RELOC_16_GOTOFF:
1284 case BFD_RELOC_32_GOTOFF:
1285 case BFD_RELOC_8_PLT_PCREL:
1286 case BFD_RELOC_16_PLT_PCREL:
1287 case BFD_RELOC_32_PLT_PCREL:
1288 case BFD_RELOC_8_PLTOFF:
1289 case BFD_RELOC_16_PLTOFF:
1290 case BFD_RELOC_32_PLTOFF:
1291 case BFD_RELOC_68K_TLS_GD32:
1292 case BFD_RELOC_68K_TLS_GD16:
1293 case BFD_RELOC_68K_TLS_GD8:
1294 case BFD_RELOC_68K_TLS_LDM32:
1295 case BFD_RELOC_68K_TLS_LDM16:
1296 case BFD_RELOC_68K_TLS_LDM8:
1297 case BFD_RELOC_68K_TLS_LDO32:
1298 case BFD_RELOC_68K_TLS_LDO16:
1299 case BFD_RELOC_68K_TLS_LDO8:
1300 case BFD_RELOC_68K_TLS_IE32:
1301 case BFD_RELOC_68K_TLS_IE16:
1302 case BFD_RELOC_68K_TLS_IE8:
1303 case BFD_RELOC_68K_TLS_LE32:
1304 case BFD_RELOC_68K_TLS_LE16:
1305 case BFD_RELOC_68K_TLS_LE8:
1308 as_bad_where (fixp->fx_file, fixp->fx_line,
1309 _("Cannot make %s relocation PC relative"),
1310 bfd_get_reloc_code_name (code));
1316 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1317 switch (F (fixp->fx_size, fixp->fx_pcrel))
1319 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1320 MAP (1, 0, BFD_RELOC_8);
1321 MAP (2, 0, BFD_RELOC_16);
1322 MAP (4, 0, BFD_RELOC_32);
1323 MAP (1, 1, BFD_RELOC_8_PCREL);
1324 MAP (2, 1, BFD_RELOC_16_PCREL);
1325 MAP (4, 1, BFD_RELOC_32_PCREL);
1333 reloc = (arelent *) xmalloc (sizeof (arelent));
1334 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1335 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1336 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1339 reloc->addend = fixp->fx_addnumber;
1340 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1342 && S_IS_WEAK (fixp->fx_addsy)
1343 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1345 /* PR gas/3041 References to weak symbols must be treated as extern
1346 in order to be overridable by the linker, even if they are defined
1347 in the same object file. So the original addend must be written
1348 "as is" into the output section without further processing.
1349 The addend value must be hacked here in order to force
1350 bfd_install_relocation() to write the original value into the
1352 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol
1353 value has already been added to the addend in fixup_segment(). We
1355 2) bfd_install_relocation() will incorrectly treat this symbol as
1356 resolved, so it will write the symbol value plus its addend and
1357 section VMA. As a workaround we can tweak the addend value here in
1358 order to get the original value in the section after the call to
1359 bfd_install_relocation(). */
1360 reloc->addend = fixp->fx_addnumber
1361 /* Fix because of MD_APPLY_SYM_VALUE() */
1362 - S_GET_VALUE (fixp->fx_addsy)
1363 /* Fix for bfd_install_relocation() */
1364 - (S_GET_VALUE (fixp->fx_addsy)
1365 + S_GET_SEGMENT (fixp->fx_addsy)->vma);
1370 if (!fixp->fx_pcrel)
1371 reloc->addend = fixp->fx_addnumber;
1373 reloc->addend = (section->vma
1374 /* Explicit sign extension in case char is
1376 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1377 + fixp->fx_addnumber
1378 + md_pcrel_from (fixp));
1381 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1382 gas_assert (reloc->howto != 0);
1387 /* Handle of the OPCODE hash table. NULL means any use before
1388 m68k_ip_begin() will crash. */
1389 static struct hash_control *op_hash;
1391 /* Assemble an m68k instruction. */
1394 m68k_ip (char *instring)
1397 register struct m68k_op *opP;
1398 register const struct m68k_incant *opcode;
1399 register const char *s;
1400 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1401 char *pdot, *pdotmove;
1402 enum m68k_size siz1, siz2;
1406 struct m68k_op operands_backup[6];
1407 LITTLENUM_TYPE words[6];
1408 LITTLENUM_TYPE *wordp;
1409 unsigned long ok_arch = 0;
1411 if (*instring == ' ')
1412 instring++; /* Skip leading whitespace. */
1414 /* Scan up to end of operation-code, which MUST end in end-of-string
1415 or exactly 1 space. */
1417 for (p = instring; *p != '\0'; p++)
1427 the_ins.error = _("No operator");
1431 /* p now points to the end of the opcode name, probably whitespace.
1432 Make sure the name is null terminated by clobbering the
1433 whitespace, look it up in the hash table, then fix it back.
1434 Remove a dot, first, since the opcode tables have none. */
1437 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1438 *pdotmove = pdotmove[1];
1444 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1449 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1450 *pdotmove = pdotmove[-1];
1457 the_ins.error = _("Unknown operator");
1461 /* Found a legitimate opcode, start matching operands. */
1465 if (opcode->m_operands == 0)
1467 char *old = input_line_pointer;
1469 input_line_pointer = p;
1470 /* Ahh - it's a motorola style psuedo op. */
1471 mote_pseudo_table[opcode->m_opnum].poc_handler
1472 (mote_pseudo_table[opcode->m_opnum].poc_val);
1473 input_line_pointer = old;
1479 if (flag_mri && opcode->m_opnum == 0)
1481 /* In MRI mode, random garbage is allowed after an instruction
1482 which accepts no operands. */
1483 the_ins.args = opcode->m_operands;
1484 the_ins.numargs = opcode->m_opnum;
1485 the_ins.numo = opcode->m_codenum;
1486 the_ins.opcode[0] = getone (opcode);
1487 the_ins.opcode[1] = gettwo (opcode);
1491 for (opP = &the_ins.operands[0]; *p; opP++)
1493 p = crack_operand (p, opP);
1497 the_ins.error = opP->error;
1502 opsfound = opP - &the_ins.operands[0];
1504 /* This ugly hack is to support the floating pt opcodes in their
1505 standard form. Essentially, we fake a first enty of type COP#1 */
1506 if (opcode->m_operands[0] == 'I')
1510 for (n = opsfound; n > 0; --n)
1511 the_ins.operands[n] = the_ins.operands[n - 1];
1513 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1514 the_ins.operands[0].mode = CONTROL;
1515 the_ins.operands[0].reg = m68k_float_copnum;
1519 /* We've got the operands. Find an opcode that'll accept them. */
1522 /* If we didn't get the right number of ops, or we have no
1523 common model with this pattern then reject this pattern. */
1525 ok_arch |= opcode->m_arch;
1526 if (opsfound != opcode->m_opnum
1527 || ((opcode->m_arch & current_architecture) == 0))
1533 /* Make a copy of the operands of this insn so that
1534 we can modify them safely, should we want to. */
1535 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1536 for (i = 0; i < opsfound; i++)
1537 operands_backup[i] = the_ins.operands[i];
1539 for (s = opcode->m_operands, opP = &operands_backup[0];
1543 /* Warning: this switch is huge! */
1544 /* I've tried to organize the cases into this order:
1545 non-alpha first, then alpha by letter. Lower-case
1546 goes directly before uppercase counterpart. */
1547 /* Code with multiple case ...: gets sorted by the lowest
1548 case ... it belongs to. I hope this makes sense. */
1654 if (opP->reg == PC || opP->reg == ZPC)
1671 if (opP->reg == PC || opP->reg == ZPC)
1690 if (opP->reg == PC || opP->reg == ZPC)
1700 if (opP->mode != IMMED)
1702 else if (s[1] == 'b'
1703 && ! isvar (&opP->disp)
1704 && (opP->disp.exp.X_op != O_constant
1705 || ! isbyte (opP->disp.exp.X_add_number)))
1707 else if (s[1] == 'B'
1708 && ! isvar (&opP->disp)
1709 && (opP->disp.exp.X_op != O_constant
1710 || ! issbyte (opP->disp.exp.X_add_number)))
1712 else if (s[1] == 'w'
1713 && ! isvar (&opP->disp)
1714 && (opP->disp.exp.X_op != O_constant
1715 || ! isword (opP->disp.exp.X_add_number)))
1717 else if (s[1] == 'W'
1718 && ! isvar (&opP->disp)
1719 && (opP->disp.exp.X_op != O_constant
1720 || ! issword (opP->disp.exp.X_add_number)))
1726 if (opP->mode != IMMED)
1731 if (opP->mode == AREG
1732 || opP->mode == CONTROL
1733 || opP->mode == FPREG
1734 || opP->mode == IMMED
1735 || opP->mode == REGLST
1736 || (opP->mode != ABSL
1738 || opP->reg == ZPC)))
1743 if (opP->mode == CONTROL
1744 || opP->mode == FPREG
1745 || opP->mode == REGLST
1746 || opP->mode == IMMED
1747 || (opP->mode != ABSL
1749 || opP->reg == ZPC)))
1777 if (opP->mode == CONTROL
1778 || opP->mode == FPREG
1779 || opP->mode == REGLST)
1784 if (opP->mode != AINC)
1789 if (opP->mode != ADEC)
1839 if (opP->reg == PC || opP->reg == ZPC)
1860 case '~': /* For now! (JF FOO is this right?) */
1882 if (opP->mode != CONTROL
1883 || (opP->reg != TT0 && opP->reg != TT1))
1888 if (opP->mode != AREG)
1893 if (opP->mode != AINDR)
1898 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1899 && (opP->mode != DISP
1901 || opP->reg > ADDR7))
1906 if (opP->mode != ABSL
1908 && strncmp (instring, "jbsr", 4) == 0))
1931 if (opP->mode != CONTROL || opP->reg != CCR)
1936 if (opP->mode != DISP
1938 || opP->reg > ADDR7)
1943 if (opP->mode != DREG)
1948 if (opP->reg != ACC)
1953 if (opP->reg != ACC && opP->reg != ACC1
1954 && opP->reg != ACC2 && opP->reg != ACC3)
1959 if (opP->mode != FPREG)
1964 if (opP->reg != MACSR)
1969 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1974 if (opP->reg != MASK)
1979 if (opP->mode != CONTROL
1986 if (opP->mode != LSH && opP->mode != RSH)
1991 if (opP->mode != CONTROL
1993 || opP->reg > last_movec_reg
1998 const enum m68k_register *rp;
2000 for (rp = control_regs; *rp; rp++)
2002 if (*rp == opP->reg)
2004 /* In most CPUs RAMBAR refers to control reg
2005 c05 (RAMBAR1), but a few CPUs have it
2006 refer to c04 (RAMBAR0). */
2007 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
2009 opP->reg = RAMBAR_ALT;
2019 if (opP->mode != IMMED)
2025 if (opP->mode == DREG
2026 || opP->mode == AREG
2027 || opP->mode == FPREG)
2036 opP->mask = 1 << (opP->reg - DATA0);
2039 opP->mask = 1 << (opP->reg - ADDR0 + 8);
2042 opP->mask = 1 << (opP->reg - FP0 + 16);
2050 else if (opP->mode == CONTROL)
2059 opP->mask = 1 << 24;
2062 opP->mask = 1 << 25;
2065 opP->mask = 1 << 26;
2074 else if (opP->mode != REGLST)
2076 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2078 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2083 if (opP->mode != IMMED)
2085 else if (opP->disp.exp.X_op != O_constant
2086 || ! issbyte (opP->disp.exp.X_add_number))
2088 else if (! m68k_quick
2089 && instring[3] != 'q'
2090 && instring[4] != 'q')
2095 if (opP->mode != DREG
2096 && opP->mode != IMMED
2097 && opP->mode != ABSL)
2102 if (opP->mode != IMMED)
2104 else if (opP->disp.exp.X_op != O_constant
2105 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2107 else if (! m68k_quick
2108 && (strncmp (instring, "add", 3) == 0
2109 || strncmp (instring, "sub", 3) == 0)
2110 && instring[3] != 'q')
2115 if (opP->mode != DREG && opP->mode != AREG)
2120 if (opP->mode != AINDR
2121 && (opP->mode != BASE
2123 && opP->reg != ZADDR0)
2124 || opP->disp.exp.X_op != O_absent
2125 || ((opP->index.reg < DATA0
2126 || opP->index.reg > DATA7)
2127 && (opP->index.reg < ADDR0
2128 || opP->index.reg > ADDR7))
2129 || opP->index.size != SIZE_UNSPEC
2130 || opP->index.scale != 1))
2135 if (opP->mode != CONTROL
2136 || ! (opP->reg == FPI
2138 || opP->reg == FPC))
2143 if (opP->mode != CONTROL || opP->reg != SR)
2148 if (opP->mode != IMMED)
2150 else if (opP->disp.exp.X_op != O_constant
2151 || TRUNC (opP->disp.exp.X_add_number) > 7)
2156 if (opP->mode != CONTROL || opP->reg != USP)
2161 if (opP->mode != IMMED)
2163 else if (opP->disp.exp.X_op != O_constant
2164 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2165 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
2170 if (opP->mode != IMMED)
2172 else if (opP->disp.exp.X_op != O_constant
2173 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2178 if (opP->mode != IMMED)
2180 else if (opP->disp.exp.X_op != O_constant
2181 || TRUNC (opP->disp.exp.X_add_number) > 511)
2185 /* JF these are out of order. We could put them
2186 in order if we were willing to put up with
2187 bunches of #ifdef m68851s in the code.
2189 Don't forget that you need these operands
2190 to use 68030 MMU instructions. */
2192 /* Memory addressing mode used by pflushr. */
2194 if (opP->mode == CONTROL
2195 || opP->mode == FPREG
2196 || opP->mode == DREG
2197 || opP->mode == AREG
2198 || opP->mode == REGLST)
2200 /* We should accept immediate operands, but they
2201 supposedly have to be quad word, and we don't
2202 handle that. I would like to see what a Motorola
2203 assembler does before doing something here. */
2204 if (opP->mode == IMMED)
2209 if (opP->mode != CONTROL
2210 || (opP->reg != SFC && opP->reg != DFC))
2215 if (opP->mode != CONTROL || opP->reg != TC)
2220 if (opP->mode != CONTROL || opP->reg != AC)
2225 if (opP->mode != CONTROL
2228 && opP->reg != SCC))
2233 if (opP->mode != CONTROL
2239 if (opP->mode != CONTROL
2242 && opP->reg != CRP))
2266 if (opP->mode != CONTROL
2267 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2268 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2273 if (opP->mode != CONTROL || opP->reg != PSR)
2278 if (opP->mode != CONTROL || opP->reg != PCSR)
2283 if (opP->mode != CONTROL
2292 if (opP->mode != ABSL)
2297 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2299 /* FIXME: kludge instead of fixing parser:
2300 upper/lower registers are *not* CONTROL
2301 registers, but ordinary ones. */
2302 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2303 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2310 if (!(opP->mode == AINDR
2311 || (opP->mode == DISP
2312 && !(opP->reg == PC || opP->reg == ZPC))))
2317 if (!(opP->mode == AINDR || opP->mode == DISP))
2329 /* Since we have found the correct instruction, copy
2330 in the modifications that we may have made. */
2332 for (i = 0; i < opsfound; i++)
2333 the_ins.operands[i] = operands_backup[i];
2339 opcode = opcode->m_next;
2344 && !(ok_arch & current_architecture))
2346 const struct m68k_cpu *cpu;
2349 char *buf = xmalloc (space + 1);
2353 the_ins.error = buf;
2354 /* Make sure there's a NUL at the end of the buffer -- strncpy
2355 won't write one when it runs out of buffer. */
2357 #define APPEND(STRING) \
2358 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2360 APPEND (_("invalid instruction for this architecture; needs "));
2364 APPEND ("ColdFire ISA_A");
2367 APPEND ("ColdFire ");
2368 APPEND (_("hardware divide"));
2371 APPEND ("ColdFire ISA_A+");
2374 APPEND ("ColdFire ISA_B");
2377 APPEND ("ColdFire ISA_C");
2380 APPEND ("ColdFire fpu");
2383 APPEND ("M68K fpu");
2386 APPEND ("M68K mmu");
2390 APPEND (_("or higher"));
2394 APPEND (_("or higher"));
2398 APPEND (_("or higher"));
2406 for (cpu = m68k_cpus; cpu->name; cpu++)
2407 if (!cpu->alias && (cpu->arch & ok_arch))
2409 const struct m68k_cpu *alias;
2410 int seen_master = 0;
2416 for (alias = cpu; alias != m68k_cpus; alias--)
2417 if (alias[-1].alias >= 0)
2419 for (; !seen_master || alias->alias > 0; alias++)
2429 APPEND (alias->name);
2442 /* We ran out of space, so replace the end of the list
2447 strcpy (buf, " ...");
2451 the_ins.error = _("operands mismatch");
2458 /* Now assemble it. */
2459 the_ins.args = opcode->m_operands;
2460 the_ins.numargs = opcode->m_opnum;
2461 the_ins.numo = opcode->m_codenum;
2462 the_ins.opcode[0] = getone (opcode);
2463 the_ins.opcode[1] = gettwo (opcode);
2465 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2470 /* This switch is a doozy.
2471 Watch the first step; its a big one! */
2504 tmpreg = 0x3c; /* 7.4 */
2505 if (strchr ("bwl", s[1]))
2506 nextword = get_num (&opP->disp, 90);
2508 nextword = get_num (&opP->disp, 0);
2509 if (isvar (&opP->disp))
2510 add_fix (s[1], &opP->disp, 0, 0);
2514 if (!isbyte (nextword))
2515 opP->error = _("operand out of range");
2520 if (!isword (nextword))
2521 opP->error = _("operand out of range");
2526 if (!issword (nextword))
2527 opP->error = _("operand out of range");
2532 addword (nextword >> 16);
2559 /* We gotta put out some float. */
2560 if (op (&opP->disp) != O_big)
2565 /* Can other cases happen here? */
2566 if (op (&opP->disp) != O_constant)
2569 val = (valueT) offs (&opP->disp);
2573 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2574 val >>= LITTLENUM_NUMBER_OF_BITS;
2578 offs (&opP->disp) = gencnt;
2580 if (offs (&opP->disp) > 0)
2582 if (offs (&opP->disp) > baseo)
2584 as_warn (_("Bignum too big for %c format; truncated"),
2586 offs (&opP->disp) = baseo;
2588 baseo -= offs (&opP->disp);
2591 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2592 offs (&opP->disp)--;
2597 gen_to_words (words, baseo, (long) outro);
2598 for (wordp = words; baseo--; wordp++)
2602 tmpreg = opP->reg - DATA; /* 0.dreg */
2605 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2608 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2611 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2614 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2618 nextword = get_num (&opP->disp, 90);
2620 /* Convert mode 5 addressing with a zero offset into
2621 mode 2 addressing to reduce the instruction size by a
2623 if (! isvar (&opP->disp)
2625 && (opP->disp.size == SIZE_UNSPEC)
2626 && (opP->reg >= ADDR0)
2627 && (opP->reg <= ADDR7))
2629 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2634 && ! isvar (&opP->disp)
2637 opP->disp.exp.X_op = O_symbol;
2638 opP->disp.exp.X_add_symbol =
2639 section_symbol (absolute_section);
2642 /* Force into index mode. Hope this works. */
2644 /* We do the first bit for 32-bit displacements, and the
2645 second bit for 16 bit ones. It is possible that we
2646 should make the default be WORD instead of LONG, but
2647 I think that'd break GCC, so we put up with a little
2648 inefficiency for the sake of working output. */
2650 if (!issword (nextword)
2651 || (isvar (&opP->disp)
2652 && ((opP->disp.size == SIZE_UNSPEC
2653 && flag_short_refs == 0
2654 && cpu_of_arch (current_architecture) >= m68020
2655 && ! arch_coldfire_p (current_architecture))
2656 || opP->disp.size == SIZE_LONG)))
2658 if (cpu_of_arch (current_architecture) < m68020
2659 || arch_coldfire_p (current_architecture))
2661 _("displacement too large for this architecture; needs 68020 or higher");
2663 tmpreg = 0x3B; /* 7.3 */
2665 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2666 if (isvar (&opP->disp))
2670 if (opP->disp.size == SIZE_LONG
2672 /* If the displacement needs pic
2673 relocation it cannot be relaxed. */
2674 || opP->disp.pic_reloc != pic_none
2679 add_fix ('l', &opP->disp, 1, 2);
2683 add_frag (adds (&opP->disp),
2684 SEXT (offs (&opP->disp)),
2685 TAB (PCREL1632, SZ_UNDEF));
2692 add_fix ('l', &opP->disp, 0, 0);
2697 addword (nextword >> 16);
2702 tmpreg = 0x3A; /* 7.2 */
2704 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2706 if (isvar (&opP->disp))
2710 add_fix ('w', &opP->disp, 1, 0);
2713 add_fix ('w', &opP->disp, 0, 0);
2723 baseo = get_num (&opP->disp, 90);
2724 if (opP->mode == POST || opP->mode == PRE)
2725 outro = get_num (&opP->odisp, 90);
2726 /* Figure out the `addressing mode'.
2727 Also turn on the BASE_DISABLE bit, if needed. */
2728 if (opP->reg == PC || opP->reg == ZPC)
2730 tmpreg = 0x3b; /* 7.3 */
2731 if (opP->reg == ZPC)
2734 else if (opP->reg == 0)
2737 tmpreg = 0x30; /* 6.garbage */
2739 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2742 tmpreg = 0x30 + opP->reg - ZADDR0;
2745 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2747 siz1 = opP->disp.size;
2748 if (opP->mode == POST || opP->mode == PRE)
2749 siz2 = opP->odisp.size;
2753 /* Index register stuff. */
2754 if (opP->index.reg != 0
2755 && opP->index.reg >= DATA
2756 && opP->index.reg <= ADDR7)
2758 nextword |= (opP->index.reg - DATA) << 12;
2760 if (opP->index.size == SIZE_LONG
2761 || (opP->index.size == SIZE_UNSPEC
2762 && m68k_index_width_default == SIZE_LONG))
2765 if ((opP->index.scale != 1
2766 && cpu_of_arch (current_architecture) < m68020)
2767 || (opP->index.scale == 8
2768 && (arch_coldfire_p (current_architecture)
2769 && !arch_coldfire_fpu (current_architecture))))
2772 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2775 if (arch_coldfire_p (current_architecture)
2776 && opP->index.size == SIZE_WORD)
2777 opP->error = _("invalid index size for coldfire");
2779 switch (opP->index.scale)
2796 GET US OUT OF HERE! */
2798 /* Must be INDEX, with an index register. Address
2799 register cannot be ZERO-PC, and either :b was
2800 forced, or we know it will fit. For a 68000 or
2801 68010, force this mode anyways, because the
2802 larger modes aren't supported. */
2803 if (opP->mode == BASE
2804 && ((opP->reg >= ADDR0
2805 && opP->reg <= ADDR7)
2808 if (siz1 == SIZE_BYTE
2809 || cpu_of_arch (current_architecture) < m68020
2810 || arch_coldfire_p (current_architecture)
2811 || (siz1 == SIZE_UNSPEC
2812 && ! isvar (&opP->disp)
2813 && issbyte (baseo)))
2815 nextword += baseo & 0xff;
2817 if (isvar (&opP->disp))
2819 /* Do a byte relocation. If it doesn't
2820 fit (possible on m68000) let the
2821 fixup processing complain later. */
2823 add_fix ('B', &opP->disp, 1, 1);
2825 add_fix ('B', &opP->disp, 0, 0);
2827 else if (siz1 != SIZE_BYTE)
2829 if (siz1 != SIZE_UNSPEC)
2830 as_warn (_("Forcing byte displacement"));
2831 if (! issbyte (baseo))
2832 opP->error = _("byte displacement out of range");
2837 else if (siz1 == SIZE_UNSPEC
2839 && isvar (&opP->disp)
2840 && subs (&opP->disp) == NULL
2842 /* If the displacement needs pic
2843 relocation it cannot be relaxed. */
2844 && opP->disp.pic_reloc == pic_none
2848 /* The code in md_convert_frag_1 needs to be
2849 able to adjust nextword. Call frag_grow
2850 to ensure that we have enough space in
2851 the frag obstack to make all the bytes
2854 nextword += baseo & 0xff;
2856 add_frag (adds (&opP->disp),
2857 SEXT (offs (&opP->disp)),
2858 TAB (PCINDEX, SZ_UNDEF));
2866 nextword |= 0x40; /* No index reg. */
2867 if (opP->index.reg >= ZDATA0
2868 && opP->index.reg <= ZDATA7)
2869 nextword |= (opP->index.reg - ZDATA0) << 12;
2870 else if (opP->index.reg >= ZADDR0
2871 || opP->index.reg <= ZADDR7)
2872 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2875 /* It isn't simple. */
2877 if (cpu_of_arch (current_architecture) < m68020
2878 || arch_coldfire_p (current_architecture))
2880 _("invalid operand mode for this architecture; needs 68020 or higher");
2883 /* If the guy specified a width, we assume that it is
2884 wide enough. Maybe it isn't. If so, we lose. */
2888 if (isvar (&opP->disp)
2890 : ! issword (baseo))
2895 else if (! isvar (&opP->disp) && baseo == 0)
2904 as_warn (_(":b not permitted; defaulting to :w"));
2914 /* Figure out inner displacement stuff. */
2915 if (opP->mode == POST || opP->mode == PRE)
2917 if (cpu_of_arch (current_architecture) & cpu32)
2918 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2922 if (isvar (&opP->odisp)
2924 : ! issword (outro))
2929 else if (! isvar (&opP->odisp) && outro == 0)
2938 as_warn (_(":b not permitted; defaulting to :w"));
2947 if (opP->mode == POST
2948 && (nextword & 0x40) == 0)
2953 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2955 if (opP->reg == PC || opP->reg == ZPC)
2956 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2958 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2960 if (siz1 == SIZE_LONG)
2961 addword (baseo >> 16);
2962 if (siz1 != SIZE_UNSPEC)
2965 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2966 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2967 if (siz2 == SIZE_LONG)
2968 addword (outro >> 16);
2969 if (siz2 != SIZE_UNSPEC)
2975 nextword = get_num (&opP->disp, 90);
2976 switch (opP->disp.size)
2981 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2983 tmpreg = 0x38; /* 7.0 */
2987 if (isvar (&opP->disp)
2988 && !subs (&opP->disp)
2989 && adds (&opP->disp)
2991 /* If the displacement needs pic relocation it
2992 cannot be relaxed. */
2993 && opP->disp.pic_reloc == pic_none
2996 && !strchr ("~%&$?", s[0]))
2998 tmpreg = 0x3A; /* 7.2 */
2999 add_frag (adds (&opP->disp),
3000 SEXT (offs (&opP->disp)),
3001 TAB (ABSTOPCREL, SZ_UNDEF));
3004 /* Fall through into long. */
3006 if (isvar (&opP->disp))
3007 add_fix ('l', &opP->disp, 0, 0);
3009 tmpreg = 0x39;/* 7.1 mode */
3010 addword (nextword >> 16);
3015 as_bad (_("unsupported byte value; use a different suffix"));
3019 if (isvar (&opP->disp))
3020 add_fix ('w', &opP->disp, 0, 0);
3022 tmpreg = 0x38;/* 7.0 mode */
3030 as_bad (_("unknown/incorrect operand"));
3034 /* If s[0] is '4', then this is for the mac instructions
3035 that can have a trailing_ampersand set. If so, set 0x100
3036 bit on tmpreg so install_gen_operand can check for it and
3037 set the appropriate bit (word2, bit 5). */
3040 if (opP->trailing_ampersand)
3043 install_gen_operand (s[1], tmpreg);
3049 { /* JF: I hate floating point! */
3064 tmpreg = get_num (&opP->disp, tmpreg);
3065 if (isvar (&opP->disp))
3066 add_fix (s[1], &opP->disp, 0, 0);
3069 case 'b': /* Danger: These do no check for
3070 certain types of overflow.
3072 if (!isbyte (tmpreg))
3073 opP->error = _("out of range");
3074 insop (tmpreg, opcode);
3075 if (isvar (&opP->disp))
3076 the_ins.reloc[the_ins.nrel - 1].n =
3077 (opcode->m_codenum) * 2 + 1;
3080 if (!issbyte (tmpreg))
3081 opP->error = _("out of range");
3082 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3083 if (isvar (&opP->disp))
3084 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3087 if (!isword (tmpreg))
3088 opP->error = _("out of range");
3089 insop (tmpreg, opcode);
3090 if (isvar (&opP->disp))
3091 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3094 if (!issword (tmpreg))
3095 opP->error = _("out of range");
3096 insop (tmpreg, opcode);
3097 if (isvar (&opP->disp))
3098 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3101 /* Because of the way insop works, we put these two out
3103 insop (tmpreg, opcode);
3104 insop (tmpreg >> 16, opcode);
3105 if (isvar (&opP->disp))
3106 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3113 install_operand (s[1], tmpreg);
3124 install_operand (s[1], opP->reg - ADDR);
3128 tmpreg = get_num (&opP->disp, 90);
3133 add_fix ('B', &opP->disp, 1, -1);
3136 add_fix ('w', &opP->disp, 1, 0);
3141 the_ins.opcode[0] |= 0xff;
3142 add_fix ('l', &opP->disp, 1, 0);
3146 case 'g': /* Conditional branch */
3147 have_disp = HAVE_LONG_CALL (current_architecture);
3150 case 'b': /* Unconditional branch */
3151 have_disp = HAVE_LONG_BRANCH (current_architecture);
3152 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
3155 case 's': /* Unconditional subroutine */
3156 have_disp = HAVE_LONG_CALL (current_architecture);
3159 if (subs (&opP->disp) /* We can't relax it. */
3161 /* If the displacement needs pic relocation it cannot be
3163 || opP->disp.pic_reloc != pic_none
3168 as_warn (_("Can't use long branches on this architecture"));
3172 /* This could either be a symbol, or an absolute
3173 address. If it's an absolute address, turn it into
3174 an absolute jump right here and keep it out of the
3176 if (adds (&opP->disp) == 0)
3178 if (the_ins.opcode[0] == 0x6000) /* jbra */
3179 the_ins.opcode[0] = 0x4EF9;
3180 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
3181 the_ins.opcode[0] = 0x4EB9;
3184 the_ins.opcode[0] ^= 0x0100;
3185 the_ins.opcode[0] |= 0x0006;
3188 add_fix ('l', &opP->disp, 0, 0);
3194 /* Now we know it's going into the relaxer. Now figure
3195 out which mode. We try in this order of preference:
3196 long branch, absolute jump, byte/word branches only. */
3198 add_frag (adds (&opP->disp),
3199 SEXT (offs (&opP->disp)),
3200 TAB (BRANCHBWL, SZ_UNDEF));
3201 else if (! flag_keep_pcrel)
3203 if ((the_ins.opcode[0] == 0x6000)
3204 || (the_ins.opcode[0] == 0x6100))
3205 add_frag (adds (&opP->disp),
3206 SEXT (offs (&opP->disp)),
3207 TAB (BRABSJUNC, SZ_UNDEF));
3209 add_frag (adds (&opP->disp),
3210 SEXT (offs (&opP->disp)),
3211 TAB (BRABSJCOND, SZ_UNDEF));
3214 add_frag (adds (&opP->disp),
3215 SEXT (offs (&opP->disp)),
3216 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3217 : TAB (BRANCHBW, SZ_UNDEF)));
3220 if (isvar (&opP->disp))
3222 /* Check for DBcc instructions. We can relax them,
3223 but only if we have long branches and/or absolute
3225 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3226 && (HAVE_LONG_BRANCH (current_architecture)
3227 || ! flag_keep_pcrel))
3229 if (HAVE_LONG_BRANCH (current_architecture))
3230 add_frag (adds (&opP->disp),
3231 SEXT (offs (&opP->disp)),
3232 TAB (DBCCLBR, SZ_UNDEF));
3234 add_frag (adds (&opP->disp),
3235 SEXT (offs (&opP->disp)),
3236 TAB (DBCCABSJ, SZ_UNDEF));
3239 add_fix ('w', &opP->disp, 1, 0);
3243 case 'C': /* Fixed size LONG coproc branches. */
3244 add_fix ('l', &opP->disp, 1, 0);
3248 case 'c': /* Var size Coprocesssor branches. */
3249 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3251 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3252 add_fix ('l', &opP->disp, 1, 0);
3257 add_frag (adds (&opP->disp),
3258 SEXT (offs (&opP->disp)),
3259 TAB (FBRANCH, SZ_UNDEF));
3266 case 'C': /* Ignore it. */
3269 case 'd': /* JF this is a kludge. */
3270 install_operand ('s', opP->reg - ADDR);
3271 tmpreg = get_num (&opP->disp, 90);
3272 if (!issword (tmpreg))
3274 as_warn (_("Expression out of range, using 0"));
3281 install_operand (s[1], opP->reg - DATA);
3284 case 'e': /* EMAC ACCx, reg/reg. */
3285 install_operand (s[1], opP->reg - ACC);
3288 case 'E': /* Ignore it. */
3292 install_operand (s[1], opP->reg - FP0);
3295 case 'g': /* EMAC ACCEXTx. */
3296 install_operand (s[1], opP->reg - ACCEXT01);
3299 case 'G': /* Ignore it. */
3304 tmpreg = opP->reg - COP0;
3305 install_operand (s[1], tmpreg);
3308 case 'i': /* MAC/EMAC scale factor. */
3309 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3312 case 'J': /* JF foo. */
3355 tmpreg = 0x00c + (opP->reg - ACR4);
3462 install_operand (s[1], tmpreg);
3466 tmpreg = get_num (&opP->disp, 55);
3467 install_operand (s[1], tmpreg & 0x7f);
3474 if (tmpreg & 0x7FF0000)
3475 as_bad (_("Floating point register in register list"));
3476 insop (reverse_16_bits (tmpreg), opcode);
3480 if (tmpreg & 0x700FFFF)
3481 as_bad (_("Wrong register in floating-point reglist"));
3482 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3490 if (tmpreg & 0x7FF0000)
3491 as_bad (_("Floating point register in register list"));
3492 insop (tmpreg, opcode);
3494 else if (s[1] == '8')
3496 if (tmpreg & 0x0FFFFFF)
3497 as_bad (_("incorrect register in reglist"));
3498 install_operand (s[1], tmpreg >> 24);
3502 if (tmpreg & 0x700FFFF)
3503 as_bad (_("wrong register in floating-point reglist"));
3505 install_operand (s[1], tmpreg >> 16);
3510 install_operand (s[1], get_num (&opP->disp, 60));
3514 tmpreg = ((opP->mode == DREG)
3515 ? 0x20 + (int) (opP->reg - DATA)
3516 : (get_num (&opP->disp, 40) & 0x1F));
3517 install_operand (s[1], tmpreg);
3521 tmpreg = get_num (&opP->disp, 10);
3524 install_operand (s[1], tmpreg);
3528 /* This depends on the fact that ADDR registers are eight
3529 more than their corresponding DATA regs, so the result
3530 will have the ADDR_REG bit set. */
3531 install_operand (s[1], opP->reg - DATA);
3535 if (opP->mode == AINDR)
3536 install_operand (s[1], opP->reg - DATA);
3538 install_operand (s[1], opP->index.reg - DATA);
3542 if (opP->reg == FPI)
3544 else if (opP->reg == FPS)
3546 else if (opP->reg == FPC)
3550 install_operand (s[1], tmpreg);
3553 case 'S': /* Ignore it. */
3557 install_operand (s[1], get_num (&opP->disp, 30));
3560 case 'U': /* Ignore it. */
3579 as_fatal (_("failed sanity check"));
3580 } /* switch on cache token. */
3581 install_operand (s[1], tmpreg);
3584 /* JF: These are out of order, I fear. */
3597 install_operand (s[1], tmpreg);
3623 install_operand (s[1], tmpreg);
3627 if (opP->reg == VAL)
3646 install_operand (s[1], tmpreg);
3660 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3671 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3677 install_operand (s[1], tmpreg);
3680 know (opP->reg == PSR);
3683 know (opP->reg == PCSR);
3698 install_operand (s[1], tmpreg);
3701 tmpreg = get_num (&opP->disp, 20);
3702 install_operand (s[1], tmpreg);
3704 case '_': /* used only for move16 absolute 32-bit address. */
3705 if (isvar (&opP->disp))
3706 add_fix ('l', &opP->disp, 0, 0);
3707 tmpreg = get_num (&opP->disp, 90);
3708 addword (tmpreg >> 16);
3709 addword (tmpreg & 0xFFFF);
3712 install_operand (s[1], opP->reg - DATA0L);
3713 opP->reg -= (DATA0L);
3714 opP->reg &= 0x0F; /* remove upper/lower bit. */
3717 tmpreg = get_num (&opP->disp, 80);
3720 install_operand (s[1], tmpreg);
3723 tmpreg = get_num (&opP->disp, 10);
3724 install_operand (s[1], tmpreg - 1);
3727 tmpreg = get_num (&opP->disp, 65);
3728 install_operand (s[1], tmpreg);
3735 /* By the time whe get here (FINALLY) the_ins contains the complete
3736 instruction, ready to be emitted. . . */
3740 reverse_16_bits (int in)
3745 static int mask[16] =
3747 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3748 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3750 for (n = 0; n < 16; n++)
3753 out |= mask[15 - n];
3756 } /* reverse_16_bits() */
3759 reverse_8_bits (int in)
3764 static int mask[8] =
3766 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3769 for (n = 0; n < 8; n++)
3775 } /* reverse_8_bits() */
3777 /* Cause an extra frag to be generated here, inserting up to
3778 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3779 generated; its primary type is rs_machine_dependent.
3781 The TYPE parameter is also used by md_convert_frag_1 and
3782 md_estimate_size_before_relax. The appropriate type of fixup will
3783 be emitted by md_convert_frag_1.
3785 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3787 install_operand (int mode, int val)
3792 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3795 the_ins.opcode[0] |= val << 9;
3798 the_ins.opcode[1] |= val << 9;
3801 the_ins.opcode[1] |= val << 12;
3804 the_ins.opcode[1] |= val << 6;
3807 the_ins.opcode[1] |= val;
3810 the_ins.opcode[2] |= val << 12;
3813 the_ins.opcode[2] |= val << 6;
3816 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3817 three words long! */
3819 the_ins.opcode[2] |= val;
3822 the_ins.opcode[1] |= val << 7;
3825 the_ins.opcode[1] |= val << 10;
3829 the_ins.opcode[1] |= val << 5;
3834 the_ins.opcode[1] |= (val << 10) | (val << 7);
3837 the_ins.opcode[1] |= (val << 12) | val;
3840 the_ins.opcode[0] |= val = 0xff;
3843 the_ins.opcode[0] |= val << 9;
3846 the_ins.opcode[1] |= val;
3849 the_ins.opcode[1] |= val;
3850 the_ins.numo++; /* What a hack. */
3853 the_ins.opcode[1] |= val << 4;
3861 the_ins.opcode[0] |= (val << 6);
3864 the_ins.opcode[1] = (val >> 16);
3865 the_ins.opcode[2] = val & 0xffff;
3868 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3869 the_ins.opcode[0] |= ((val & 0x7) << 9);
3870 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3872 case 'n': /* MAC/EMAC Rx on !load. */
3873 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3874 the_ins.opcode[0] |= ((val & 0x7) << 9);
3875 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3877 case 'o': /* MAC/EMAC Rx on load. */
3878 the_ins.opcode[1] |= val << 12;
3879 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3881 case 'M': /* MAC/EMAC Ry on !load. */
3882 the_ins.opcode[0] |= (val & 0xF);
3883 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3885 case 'N': /* MAC/EMAC Ry on load. */
3886 the_ins.opcode[1] |= (val & 0xF);
3887 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3890 the_ins.opcode[1] |= ((val != 1) << 10);
3893 the_ins.opcode[0] |= ((val & 0x3) << 9);
3896 the_ins.opcode[0] |= ((val & 0x3) << 0);
3898 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3899 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3900 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3902 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3903 the_ins.opcode[0] |= ((val & 0x1) << 7);
3904 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3907 the_ins.opcode[1] |= ((val & 0x3) << 9);
3910 the_ins.opcode[0] |= (val & 0x1) <<10;
3914 as_fatal (_("failed sanity check."));
3919 install_gen_operand (int mode, int val)
3923 case '/': /* Special for mask loads for mac/msac insns with
3924 possible mask; trailing_ampersend set in bit 8. */
3925 the_ins.opcode[0] |= (val & 0x3f);
3926 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3929 the_ins.opcode[0] |= val;
3932 /* This is a kludge!!! */
3933 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3942 the_ins.opcode[0] |= val;
3944 /* more stuff goes here. */
3946 as_fatal (_("failed sanity check."));
3950 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3951 then deal with the bitfield hack. */
3954 crack_operand (char *str, struct m68k_op *opP)
3956 register int parens;
3958 register char *beg_str;
3966 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3972 else if (*str == ')')
3976 opP->error = _("Extra )");
3982 if (flag_mri && *str == '\'')
3983 inquote = ! inquote;
3985 if (!*str && parens)
3987 opP->error = _("Missing )");
3992 if (m68k_ip_op (beg_str, opP) != 0)
3999 c = *++str; /* JF bitfield hack. */
4004 as_bad (_("Missing operand"));
4007 /* Detect MRI REG symbols and convert them to REGLSTs. */
4008 if (opP->mode == CONTROL && (int)opP->reg < 0)
4011 opP->mask = ~(int)opP->reg;
4018 /* This is the guts of the machine-dependent assembler. STR points to a
4019 machine dependent instruction. This function is supposed to emit
4020 the frags/bytes it assembles to.
4024 insert_reg (const char *regname, int regnum)
4029 #ifdef REGISTER_PREFIX
4030 if (!flag_reg_prefix_optional)
4032 buf[0] = REGISTER_PREFIX;
4033 strcpy (buf + 1, regname);
4038 symbol_table_insert (symbol_new (regname, reg_section, regnum,
4039 &zero_address_frag));
4041 for (i = 0; regname[i]; i++)
4042 buf[i] = TOUPPER (regname[i]);
4045 symbol_table_insert (symbol_new (buf, reg_section, regnum,
4046 &zero_address_frag));
4055 static const struct init_entry init_table[] =
4115 { "accext01", ACCEXT01 },
4116 { "accext23", ACCEXT23 },
4120 /* Control registers. */
4121 { "sfc", SFC }, /* Source Function Code. */
4123 { "dfc", DFC }, /* Destination Function Code. */
4125 { "cacr", CACR }, /* Cache Control Register. */
4126 { "caar", CAAR }, /* Cache Address Register. */
4127 { "cpucr", CPUCR }, /* CPU Control Register. */
4129 { "usp", USP }, /* User Stack Pointer. */
4130 { "vbr", VBR }, /* Vector Base Register. */
4131 { "msp", MSP }, /* Master Stack Pointer. */
4132 { "isp", ISP }, /* Interrupt Stack Pointer. */
4134 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4135 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4136 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4137 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
4139 /* 68ec040 versions of same */
4140 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4141 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4142 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4143 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
4145 /* Coldfire versions of same. The ColdFire programmer's reference
4146 manual indicated that the order is 2,3,0,1, but Ken Rose
4147 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
4148 { "acr0", ACR0 }, /* Access Control Unit 0. */
4149 { "acr1", ACR1 }, /* Access Control Unit 1. */
4150 { "acr2", ACR2 }, /* Access Control Unit 2. */
4151 { "acr3", ACR3 }, /* Access Control Unit 3. */
4152 { "acr4", ACR4 }, /* Access Control Unit 4. */
4153 { "acr5", ACR5 }, /* Access Control Unit 5. */
4154 { "acr6", ACR6 }, /* Access Control Unit 6. */
4155 { "acr7", ACR7 }, /* Access Control Unit 7. */
4157 { "tc", TC }, /* MMU Translation Control Register. */
4161 { "mmusr", MMUSR }, /* MMU Status Register. */
4162 { "srp", SRP }, /* User Root Pointer. */
4163 { "urp", URP }, /* Supervisor Root Pointer. */
4166 { "mmubar", MMUBAR },
4169 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4170 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4171 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4172 { "mbar", MBAR }, /* Module Base Address Register. */
4174 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4175 { "mbar1", MBAR1 }, /* mcfv4e registers. */
4176 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
4177 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4178 { "mpcr", MPCR }, /* mcfv4e registers. */
4179 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4180 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4181 { "asid", TC }, /* mcfv4e registers. */
4182 { "mmubar", BUSCR }, /* mcfv4e registers. */
4183 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4184 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4185 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4186 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4187 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4188 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4189 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4190 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4191 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4192 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4193 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4194 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4196 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4197 { "rambar", RAMBAR }, /* mcf528x registers. */
4199 { "mbar2", MBAR2 }, /* mcf5249 registers. */
4201 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */
4203 { "cac", CAC }, /* fido registers. */
4204 { "mbb", MBO }, /* fido registers (obsolete). */
4205 { "mbo", MBO }, /* fido registers. */
4206 /* End of control registers. */
4240 /* 68ec030 versions of same. */
4243 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4246 /* Suppressed data and address registers. */
4264 /* Upper and lower data and address registers, used by macw and msacw. */
4305 init_regtable (void)
4308 for (i = 0; init_table[i].name; i++)
4309 insert_reg (init_table[i].name, init_table[i].number);
4313 md_assemble (char *str)
4320 int shorts_this_frag;
4323 if (!selected_cpu && !selected_arch)
4325 /* We've not selected an architecture yet. Set the default
4326 now. We do this lazily so that an initial .cpu or .arch directive
4328 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4329 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4334 /* In MRI mode, the instruction and operands are separated by a
4335 space. Anything following the operands is a comment. The label
4336 has already been removed. */
4344 for (s = str; *s != '\0'; s++)
4346 if ((*s == ' ' || *s == '\t') && ! inquote)
4364 inquote = ! inquote;
4369 memset (&the_ins, '\0', sizeof (the_ins));
4374 for (n = 0; n < the_ins.numargs; n++)
4375 if (the_ins.operands[n].error)
4377 er = the_ins.operands[n].error;
4383 as_bad (_("%s -- statement `%s' ignored"), er, str);
4387 /* If there is a current label, record that it marks an instruction. */
4388 if (current_label != NULL)
4390 current_label->text = 1;
4391 current_label = NULL;
4395 /* Tie dwarf2 debug info to the address at the start of the insn. */
4396 dwarf2_emit_insn (0);
4399 if (the_ins.nfrag == 0)
4401 /* No frag hacking involved; just put it out. */
4402 toP = frag_more (2 * the_ins.numo);
4403 fromP = &the_ins.opcode[0];
4404 for (m = the_ins.numo; m; --m)
4406 md_number_to_chars (toP, (long) (*fromP), 2);
4410 /* Put out symbol-dependent info. */
4411 for (m = 0; m < the_ins.nrel; m++)
4413 switch (the_ins.reloc[m].wid)
4432 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4433 the_ins.reloc[m].wid);
4436 fixP = fix_new_exp (frag_now,
4437 ((toP - frag_now->fr_literal)
4438 - the_ins.numo * 2 + the_ins.reloc[m].n),
4440 &the_ins.reloc[m].exp,
4441 the_ins.reloc[m].pcrel,
4442 get_reloc_code (n, the_ins.reloc[m].pcrel,
4443 the_ins.reloc[m].pic_reloc));
4444 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4445 if (the_ins.reloc[m].wid == 'B')
4446 fixP->fx_signed = 1;
4451 /* There's some frag hacking. */
4453 /* Calculate the max frag size. */
4456 wid = 2 * the_ins.fragb[0].fragoff;
4457 for (n = 1; n < the_ins.nfrag; n++)
4458 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4459 /* frag_var part. */
4460 wid += FRAG_VAR_SIZE;
4461 /* Make sure the whole insn fits in one chunk, in particular that
4462 the var part is attached, as we access one byte before the
4463 variable frag for byte branches. */
4467 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4472 wid = 2 * the_ins.fragb[n].fragoff;
4474 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4475 toP = frag_more (wid);
4477 shorts_this_frag = 0;
4478 for (m = wid / 2; m; --m)
4480 md_number_to_chars (toP, (long) (*fromP), 2);
4485 for (m = 0; m < the_ins.nrel; m++)
4487 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4489 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4492 wid = the_ins.reloc[m].wid;
4495 the_ins.reloc[m].wid = 0;
4496 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4498 fixP = fix_new_exp (frag_now,
4499 ((toP - frag_now->fr_literal)
4500 - the_ins.numo * 2 + the_ins.reloc[m].n),
4502 &the_ins.reloc[m].exp,
4503 the_ins.reloc[m].pcrel,
4504 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4505 the_ins.reloc[m].pic_reloc));
4506 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4508 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4509 (relax_substateT) (the_ins.fragb[n].fragty),
4510 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4512 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4513 shorts_this_frag = 0;
4516 toP = frag_more (n * 2);
4519 md_number_to_chars (toP, (long) (*fromP), 2);
4525 for (m = 0; m < the_ins.nrel; m++)
4529 wid = the_ins.reloc[m].wid;
4532 the_ins.reloc[m].wid = 0;
4533 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4535 fixP = fix_new_exp (frag_now,
4536 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4537 - shorts_this_frag * 2),
4539 &the_ins.reloc[m].exp,
4540 the_ins.reloc[m].pcrel,
4541 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4542 the_ins.reloc[m].pic_reloc));
4543 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4547 /* Comparison function used by qsort to rank the opcode entries by name. */
4550 m68k_compare_opcode (const void * v1, const void * v2)
4552 struct m68k_opcode * op1, * op2;
4558 op1 = *(struct m68k_opcode **) v1;
4559 op2 = *(struct m68k_opcode **) v2;
4561 /* Compare the two names. If different, return the comparison.
4562 If the same, return the order they are in the opcode table. */
4563 ret = strcmp (op1->name, op2->name);
4574 const struct m68k_opcode *ins;
4575 struct m68k_incant *hack, *slak;
4576 const char *retval = 0; /* Empty string, or error msg text. */
4579 /* Set up hash tables with 68000 instructions.
4580 similar to what the vax assembler does. */
4581 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4582 a copy of it at runtime, adding in the information we want but isn't
4583 there. I think it'd be better to have an awk script hack the table
4584 at compile time. Or even just xstr the table and use it as-is. But
4585 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4590 flag_reg_prefix_optional = 1;
4592 if (! m68k_rel32_from_cmdline)
4596 /* First sort the opcode table into alphabetical order to seperate
4597 the order that the assembler wants to see the opcodes from the
4598 order that the disassembler wants to see them. */
4599 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4600 if (!m68k_sorted_opcodes)
4601 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4602 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4604 for (i = m68k_numopcodes; i--;)
4605 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4607 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4608 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4610 op_hash = hash_new ();
4612 obstack_begin (&robyn, 4000);
4613 for (i = 0; i < m68k_numopcodes; i++)
4615 hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4618 ins = m68k_sorted_opcodes[i];
4620 /* We must enter all insns into the table, because .arch and
4621 .cpu directives can change things. */
4622 slak->m_operands = ins->args;
4623 slak->m_arch = ins->arch;
4624 slak->m_opcode = ins->opcode;
4626 /* In most cases we can determine the number of opcode words
4627 by checking the second word of the mask. Unfortunately
4628 some instructions have 2 opcode words, but no fixed bits
4629 in the second word. A leading dot in the operands
4630 string also indicates 2 opcodes. */
4631 if (*slak->m_operands == '.')
4634 slak->m_codenum = 2;
4636 else if (ins->match & 0xffffL)
4637 slak->m_codenum = 2;
4639 slak->m_codenum = 1;
4640 slak->m_opnum = strlen (slak->m_operands) / 2;
4642 if (i + 1 != m68k_numopcodes
4643 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4645 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4650 slak = slak->m_next;
4654 retval = hash_insert (op_hash, ins->name, (char *) hack);
4656 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4659 for (i = 0; i < m68k_numaliases; i++)
4661 const char *name = m68k_opcode_aliases[i].primary;
4662 const char *alias = m68k_opcode_aliases[i].alias;
4663 void *val = hash_find (op_hash, name);
4666 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4667 retval = hash_insert (op_hash, alias, val);
4669 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4672 /* In MRI mode, all unsized branches are variable sized. Normally,
4673 they are word sized. */
4676 static struct m68k_opcode_alias mri_aliases[] =
4697 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4700 const char *name = mri_aliases[i].primary;
4701 const char *alias = mri_aliases[i].alias;
4702 void *val = hash_find (op_hash, name);
4705 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4706 retval = hash_jam (op_hash, alias, val);
4708 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4712 for (i = 0; i < (int) sizeof (notend_table); i++)
4714 notend_table[i] = 0;
4715 alt_notend_table[i] = 0;
4718 notend_table[','] = 1;
4719 notend_table['{'] = 1;
4720 notend_table['}'] = 1;
4721 alt_notend_table['a'] = 1;
4722 alt_notend_table['A'] = 1;
4723 alt_notend_table['d'] = 1;
4724 alt_notend_table['D'] = 1;
4725 alt_notend_table['#'] = 1;
4726 alt_notend_table['&'] = 1;
4727 alt_notend_table['f'] = 1;
4728 alt_notend_table['F'] = 1;
4729 #ifdef REGISTER_PREFIX
4730 alt_notend_table[REGISTER_PREFIX] = 1;
4733 /* We need to put '(' in alt_notend_table to handle
4734 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4735 alt_notend_table['('] = 1;
4737 /* We need to put '@' in alt_notend_table to handle
4738 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4739 alt_notend_table['@'] = 1;
4741 /* We need to put digits in alt_notend_table to handle
4742 bfextu %d0{24:1},%d0 */
4743 alt_notend_table['0'] = 1;
4744 alt_notend_table['1'] = 1;
4745 alt_notend_table['2'] = 1;
4746 alt_notend_table['3'] = 1;
4747 alt_notend_table['4'] = 1;
4748 alt_notend_table['5'] = 1;
4749 alt_notend_table['6'] = 1;
4750 alt_notend_table['7'] = 1;
4751 alt_notend_table['8'] = 1;
4752 alt_notend_table['9'] = 1;
4754 #ifndef MIT_SYNTAX_ONLY
4755 /* Insert pseudo ops, these have to go into the opcode table since
4756 gas expects pseudo ops to start with a dot. */
4760 while (mote_pseudo_table[n].poc_name)
4762 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4763 hash_insert (op_hash,
4764 mote_pseudo_table[n].poc_name, (char *) hack);
4765 hack->m_operands = 0;
4775 record_alignment (text_section, 2);
4776 record_alignment (data_section, 2);
4777 record_alignment (bss_section, 2);
4782 /* This is called when a label is defined. */
4785 m68k_frob_label (symbolS *sym)
4787 struct label_line *n;
4789 n = (struct label_line *) xmalloc (sizeof *n);
4792 as_where (&n->file, &n->line);
4798 dwarf2_emit_label (sym);
4802 /* This is called when a value that is not an instruction is emitted. */
4805 m68k_flush_pending_output (void)
4807 current_label = NULL;
4810 /* This is called at the end of the assembly, when the final value of
4811 the label is known. We warn if this is a text symbol aligned at an
4815 m68k_frob_symbol (symbolS *sym)
4817 if (S_GET_SEGMENT (sym) == reg_section
4818 && (int) S_GET_VALUE (sym) < 0)
4820 S_SET_SEGMENT (sym, absolute_section);
4821 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4823 else if ((S_GET_VALUE (sym) & 1) != 0)
4825 struct label_line *l;
4827 for (l = labels; l != NULL; l = l->next)
4829 if (l->label == sym)
4832 as_warn_where (l->file, l->line,
4833 _("text label `%s' aligned to odd boundary"),
4841 /* This is called if we go in or out of MRI mode because of the .mri
4845 m68k_mri_mode_change (int on)
4849 if (! flag_reg_prefix_optional)
4851 flag_reg_prefix_optional = 1;
4852 #ifdef REGISTER_PREFIX
4857 if (! m68k_rel32_from_cmdline)
4862 if (! reg_prefix_optional_seen)
4864 #ifdef REGISTER_PREFIX_OPTIONAL
4865 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4867 flag_reg_prefix_optional = 0;
4869 #ifdef REGISTER_PREFIX
4874 if (! m68k_rel32_from_cmdline)
4880 md_atof (int type, char *litP, int *sizeP)
4882 return ieee_md_atof (type, litP, sizeP, TRUE);
4886 md_number_to_chars (char *buf, valueT val, int n)
4888 number_to_chars_bigendian (buf, val, n);
4892 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4894 offsetT val = *valP;
4895 addressT upper_limit;
4896 offsetT lower_limit;
4898 /* This is unnecessary but it convinces the native rs6000 compiler
4899 to generate the code we want. */
4900 char *buf = fixP->fx_frag->fr_literal;
4901 buf += fixP->fx_where;
4902 /* End ibm compiler workaround. */
4906 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4912 memset (buf, 0, fixP->fx_size);
4913 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4915 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4916 && !S_IS_DEFINED (fixP->fx_addsy)
4917 && !S_IS_WEAK (fixP->fx_addsy))
4918 S_SET_WEAK (fixP->fx_addsy);
4920 switch (fixP->fx_r_type)
4922 case BFD_RELOC_68K_TLS_GD32:
4923 case BFD_RELOC_68K_TLS_GD16:
4924 case BFD_RELOC_68K_TLS_GD8:
4925 case BFD_RELOC_68K_TLS_LDM32:
4926 case BFD_RELOC_68K_TLS_LDM16:
4927 case BFD_RELOC_68K_TLS_LDM8:
4928 case BFD_RELOC_68K_TLS_LDO32:
4929 case BFD_RELOC_68K_TLS_LDO16:
4930 case BFD_RELOC_68K_TLS_LDO8:
4931 case BFD_RELOC_68K_TLS_IE32:
4932 case BFD_RELOC_68K_TLS_IE16:
4933 case BFD_RELOC_68K_TLS_IE8:
4934 case BFD_RELOC_68K_TLS_LE32:
4935 case BFD_RELOC_68K_TLS_LE16:
4936 case BFD_RELOC_68K_TLS_LE8:
4937 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4946 #elif defined(OBJ_AOUT)
4947 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4948 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4950 memset (buf, 0, fixP->fx_size);
4951 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4956 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4957 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4960 switch (fixP->fx_size)
4962 /* The cast to offsetT below are necessary to make code
4963 correct for machines where ints are smaller than offsetT. */
4967 lower_limit = - (offsetT) 0x80;
4970 *buf++ = (val >> 8);
4972 upper_limit = 0x7fff;
4973 lower_limit = - (offsetT) 0x8000;
4976 *buf++ = (val >> 24);
4977 *buf++ = (val >> 16);
4978 *buf++ = (val >> 8);
4980 upper_limit = 0x7fffffff;
4981 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4984 BAD_CASE (fixP->fx_size);
4987 /* Fix up a negative reloc. */
4988 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4990 fixP->fx_addsy = fixP->fx_subsy;
4991 fixP->fx_subsy = NULL;
4995 /* For non-pc-relative values, it's conceivable we might get something
4996 like "0xff" for a byte field. So extend the upper part of the range
4997 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4998 so that we can do any range checking at all. */
4999 if (! fixP->fx_pcrel && ! fixP->fx_signed)
5000 upper_limit = upper_limit * 2 + 1;
5002 if ((addressT) val > upper_limit
5003 && (val > 0 || val < lower_limit))
5004 as_bad_where (fixP->fx_file, fixP->fx_line,
5005 _("value %ld out of range"), (long)val);
5007 /* A one byte PC-relative reloc means a short branch. We can't use
5008 a short branch with a value of 0 or -1, because those indicate
5009 different opcodes (branches with longer offsets). fixup_segment
5010 in write.c may have clobbered fx_pcrel, so we need to examine the
5013 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5014 && fixP->fx_size == 1
5015 && (fixP->fx_addsy == NULL
5016 || S_IS_DEFINED (fixP->fx_addsy))
5017 && (val == 0 || val == -1))
5018 as_bad_where (fixP->fx_file, fixP->fx_line,
5019 _("invalid byte branch offset"));
5022 /* *fragP has been relaxed to its final size, and now needs to have
5023 the bytes inside it modified to conform to the new size There is UGLY
5027 md_convert_frag_1 (fragS *fragP)
5032 /* Address in object code of the displacement. */
5033 register int object_address = fragP->fr_fix + fragP->fr_address;
5035 /* Address in gas core of the place to store the displacement. */
5036 /* This convinces the native rs6000 compiler to generate the code we
5038 register char *buffer_address = fragP->fr_literal;
5039 buffer_address += fragP->fr_fix;
5040 /* End ibm compiler workaround. */
5042 /* The displacement of the address, from current location. */
5043 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
5044 disp = (disp + fragP->fr_offset) - object_address;
5046 switch (fragP->fr_subtype)
5048 case TAB (BRANCHBWL, BYTE):
5049 case TAB (BRABSJUNC, BYTE):
5050 case TAB (BRABSJCOND, BYTE):
5051 case TAB (BRANCHBW, BYTE):
5052 case TAB (BRANCHBWPL, BYTE):
5053 know (issbyte (disp));
5055 as_bad_where (fragP->fr_file, fragP->fr_line,
5056 _("short branch with zero offset: use :w"));
5057 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5058 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5059 fixP->fx_pcrel_adjust = -1;
5061 case TAB (BRANCHBWL, SHORT):
5062 case TAB (BRABSJUNC, SHORT):
5063 case TAB (BRABSJCOND, SHORT):
5064 case TAB (BRANCHBW, SHORT):
5065 case TAB (BRANCHBWPL, SHORT):
5066 fragP->fr_opcode[1] = 0x00;
5067 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5068 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5071 case TAB (BRANCHBWL, LONG):
5072 fragP->fr_opcode[1] = (char) 0xFF;
5073 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5074 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5077 case TAB (BRANCHBWPL, LONG):
5078 /* Here we are converting an unconditional branch into a pair of
5079 conditional branches, in order to get the range. */
5080 fragP->fr_opcode[0] = 0x66; /* bne */
5081 fragP->fr_opcode[1] = 0xFF;
5082 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5083 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5084 fixP->fx_file = fragP->fr_file;
5085 fixP->fx_line = fragP->fr_line;
5086 fragP->fr_fix += 4; /* Skip first offset */
5087 buffer_address += 4;
5088 *buffer_address++ = 0x67; /* beq */
5089 *buffer_address++ = 0xff;
5090 fragP->fr_fix += 2; /* Skip second branch opcode */
5091 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5092 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5095 case TAB (BRABSJUNC, LONG):
5096 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
5098 if (flag_keep_pcrel)
5099 as_bad_where (fragP->fr_file, fragP->fr_line,
5100 _("Conversion of PC relative BSR to absolute JSR"));
5101 fragP->fr_opcode[0] = 0x4E;
5102 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
5103 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5104 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5107 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5109 if (flag_keep_pcrel)
5110 as_bad_where (fragP->fr_file, fragP->fr_line,
5111 _("Conversion of PC relative branch to absolute jump"));
5112 fragP->fr_opcode[0] = 0x4E;
5113 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
5114 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5115 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5120 /* This cannot happen, because jbsr and jbra are the only two
5121 unconditional branches. */
5125 case TAB (BRABSJCOND, LONG):
5126 if (flag_keep_pcrel)
5127 as_bad_where (fragP->fr_file, fragP->fr_line,
5128 _("Conversion of PC relative conditional branch to absolute jump"));
5130 /* Only Bcc 68000 instructions can come here
5131 Change bcc into b!cc/jmp absl long. */
5132 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5133 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
5135 /* JF: these used to be fr_opcode[2,3], but they may be in a
5136 different frag, in which case referring to them is a no-no.
5137 Only fr_opcode[0,1] are guaranteed to work. */
5138 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5139 *buffer_address++ = (char) 0xf9;
5140 fragP->fr_fix += 2; /* Account for jmp instruction. */
5141 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5142 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5145 case TAB (FBRANCH, SHORT):
5146 know ((fragP->fr_opcode[1] & 0x40) == 0);
5147 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5148 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5151 case TAB (FBRANCH, LONG):
5152 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
5153 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5154 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5157 case TAB (DBCCLBR, SHORT):
5158 case TAB (DBCCABSJ, SHORT):
5159 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5160 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5163 case TAB (DBCCLBR, LONG):
5164 /* Only DBcc instructions can come here.
5165 Change dbcc into dbcc/bral.
5166 JF: these used to be fr_opcode[2-7], but that's wrong. */
5167 if (flag_keep_pcrel)
5168 as_bad_where (fragP->fr_file, fragP->fr_line,
5169 _("Conversion of DBcc to absolute jump"));
5171 *buffer_address++ = 0x00; /* Branch offset = 4. */
5172 *buffer_address++ = 0x04;
5173 *buffer_address++ = 0x60; /* Put in bra pc+6. */
5174 *buffer_address++ = 0x06;
5175 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5176 *buffer_address++ = (char) 0xff;
5178 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5179 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5180 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5183 case TAB (DBCCABSJ, LONG):
5184 /* Only DBcc instructions can come here.
5185 Change dbcc into dbcc/jmp.
5186 JF: these used to be fr_opcode[2-7], but that's wrong. */
5187 if (flag_keep_pcrel)
5188 as_bad_where (fragP->fr_file, fragP->fr_line,
5189 _("Conversion of PC relative conditional branch to absolute jump"));
5191 *buffer_address++ = 0x00; /* Branch offset = 4. */
5192 *buffer_address++ = 0x04;
5193 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
5194 *buffer_address++ = 0x06;
5195 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
5196 *buffer_address++ = (char) 0xf9;
5198 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5199 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5200 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5203 case TAB (PCREL1632, SHORT):
5204 fragP->fr_opcode[1] &= ~0x3F;
5205 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5206 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5207 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5210 case TAB (PCREL1632, LONG):
5211 /* Already set to mode 7.3; this indicates: PC indirect with
5212 suppressed index, 32-bit displacement. */
5213 *buffer_address++ = 0x01;
5214 *buffer_address++ = 0x70;
5216 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5217 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5218 fixP->fx_pcrel_adjust = 2;
5221 case TAB (PCINDEX, BYTE):
5222 gas_assert (fragP->fr_fix >= 2);
5223 buffer_address[-2] &= ~1;
5224 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5225 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5226 fixP->fx_pcrel_adjust = 1;
5228 case TAB (PCINDEX, SHORT):
5229 gas_assert (fragP->fr_fix >= 2);
5230 buffer_address[-2] |= 0x1;
5231 buffer_address[-1] = 0x20;
5232 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5233 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5234 fixP->fx_pcrel_adjust = 2;
5237 case TAB (PCINDEX, LONG):
5238 gas_assert (fragP->fr_fix >= 2);
5239 buffer_address[-2] |= 0x1;
5240 buffer_address[-1] = 0x30;
5241 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5242 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5243 fixP->fx_pcrel_adjust = 2;
5246 case TAB (ABSTOPCREL, SHORT):
5247 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5248 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5251 case TAB (ABSTOPCREL, LONG):
5252 if (flag_keep_pcrel)
5253 as_bad_where (fragP->fr_file, fragP->fr_line,
5254 _("Conversion of PC relative displacement to absolute"));
5255 /* The thing to do here is force it to ABSOLUTE LONG, since
5256 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5257 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5259 fragP->fr_opcode[1] &= ~0x3F;
5260 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5261 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5262 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5268 fixP->fx_file = fragP->fr_file;
5269 fixP->fx_line = fragP->fr_line;
5274 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5275 segT sec ATTRIBUTE_UNUSED,
5278 md_convert_frag_1 (fragP);
5281 /* Force truly undefined symbols to their maximum size, and generally set up
5282 the frag list to be relaxed
5285 md_estimate_size_before_relax (fragS *fragP, segT segment)
5287 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5288 switch (fragP->fr_subtype)
5290 case TAB (BRANCHBWL, SZ_UNDEF):
5291 case TAB (BRANCHBWPL, SZ_UNDEF):
5292 case TAB (BRABSJUNC, SZ_UNDEF):
5293 case TAB (BRABSJCOND, SZ_UNDEF):
5295 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5296 && relaxable_symbol (fragP->fr_symbol))
5298 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5300 else if (flag_short_refs)
5302 /* Symbol is undefined and we want short ref. */
5303 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5307 /* Symbol is still undefined. Make it LONG. */
5308 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5313 case TAB (BRANCHBW, SZ_UNDEF):
5315 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5316 && relaxable_symbol (fragP->fr_symbol))
5318 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5322 /* Symbol is undefined and we don't have long branches. */
5323 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5328 case TAB (FBRANCH, SZ_UNDEF):
5329 case TAB (DBCCLBR, SZ_UNDEF):
5330 case TAB (DBCCABSJ, SZ_UNDEF):
5331 case TAB (PCREL1632, SZ_UNDEF):
5333 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5334 && relaxable_symbol (fragP->fr_symbol))
5337 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5341 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5346 case TAB (PCINDEX, SZ_UNDEF):
5347 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5348 && relaxable_symbol (fragP->fr_symbol)))
5350 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5354 fragP->fr_subtype = TAB (PCINDEX, LONG);
5358 case TAB (ABSTOPCREL, SZ_UNDEF):
5360 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5361 && relaxable_symbol (fragP->fr_symbol)))
5363 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5367 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5376 /* Now that SZ_UNDEF are taken care of, check others. */
5377 switch (fragP->fr_subtype)
5379 case TAB (BRANCHBWL, BYTE):
5380 case TAB (BRABSJUNC, BYTE):
5381 case TAB (BRABSJCOND, BYTE):
5382 case TAB (BRANCHBW, BYTE):
5383 /* We can't do a short jump to the next instruction, so in that
5384 case we force word mode. If the symbol is at the start of a
5385 frag, and it is the next frag with any data in it (usually
5386 this is just the next frag, but assembler listings may
5387 introduce empty frags), we must use word mode. */
5388 if (fragP->fr_symbol)
5392 sym_frag = symbol_get_frag (fragP->fr_symbol);
5393 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5397 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5401 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5408 return md_relax_table[fragP->fr_subtype].rlx_length;
5411 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5412 /* the bit-field entries in the relocation_info struct plays hell
5413 with the byte-order problems of cross-assembly. So as a hack,
5414 I added this mach. dependent ri twiddler. Ugly, but it gets
5416 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5417 are symbolnum, most sig. byte first. Last byte is broken up with
5418 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5419 nibble as nuthin. (on Sun 3 at least) */
5420 /* Translate the internal relocation information into target-specific
5424 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5427 md_number_to_chars (the_bytes, ri->r_address, 4);
5428 /* Now the fun stuff. */
5429 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5430 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5431 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5432 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5433 | ((ri->r_length << 5) & 0x60)
5434 | ((ri->r_extern << 4) & 0x10));
5439 #endif /* OBJ_AOUT or OBJ_BOUT */
5441 #ifndef WORKING_DOT_WORD
5442 int md_short_jump_size = 4;
5443 int md_long_jump_size = 6;
5446 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5447 fragS *frag ATTRIBUTE_UNUSED,
5448 symbolS *to_symbol ATTRIBUTE_UNUSED)
5452 offset = to_addr - (from_addr + 2);
5454 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5455 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5459 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5460 fragS *frag, symbolS *to_symbol)
5464 if (!HAVE_LONG_BRANCH (current_architecture))
5466 if (flag_keep_pcrel)
5467 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5468 offset = to_addr - S_GET_VALUE (to_symbol);
5469 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5470 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5471 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5476 offset = to_addr - (from_addr + 2);
5477 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5478 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5484 /* Different values of OK tell what its OK to return. Things that
5485 aren't OK are an error (what a shock, no?)
5488 10: Absolute 1:8 only
5489 20: Absolute 0:7 only
5490 30: absolute 0:15 only
5491 40: Absolute 0:31 only
5492 50: absolute 0:127 only
5493 55: absolute -64:63 only
5494 60: absolute -128:127 only
5495 65: absolute 0:511 only
5496 70: absolute 0:4095 only
5497 80: absolute -1, 1:7 only
5501 get_num (struct m68k_exp *exp, int ok)
5503 if (exp->exp.X_op == O_absent)
5505 /* Do the same thing the VAX asm does. */
5506 op (exp) = O_constant;
5512 as_warn (_("expression out of range: defaulting to 1"));
5516 else if (exp->exp.X_op == O_constant)
5521 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5523 as_warn (_("expression out of range: defaulting to 1"));
5528 if ((valueT) TRUNC (offs (exp)) > 7)
5532 if ((valueT) TRUNC (offs (exp)) > 15)
5536 if ((valueT) TRUNC (offs (exp)) > 32)
5540 if ((valueT) TRUNC (offs (exp)) > 127)
5544 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5548 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5552 if ((valueT) TRUNC (offs (exp)) > 511)
5556 if ((valueT) TRUNC (offs (exp)) > 4095)
5559 as_warn (_("expression out of range: defaulting to 0"));
5564 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5565 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5567 as_warn (_("expression out of range: defaulting to 1"));
5575 else if (exp->exp.X_op == O_big)
5577 if (offs (exp) <= 0 /* flonum. */
5578 && (ok == 90 /* no bignums */
5579 || (ok > 10 /* Small-int ranges including 0 ok. */
5580 /* If we have a flonum zero, a zero integer should
5581 do as well (e.g., in moveq). */
5582 && generic_floating_point_number.exponent == 0
5583 && generic_floating_point_number.low[0] == 0)))
5585 /* HACK! Turn it into a long. */
5586 LITTLENUM_TYPE words[6];
5588 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5589 op (exp) = O_constant;
5592 offs (exp) = words[1] | (words[0] << 16);
5596 op (exp) = O_constant;
5599 offs (exp) = (ok == 10) ? 1 : 0;
5600 as_warn (_("Can't deal with expression; defaulting to %ld"),
5606 if (ok >= 10 && ok <= 80)
5608 op (exp) = O_constant;
5611 offs (exp) = (ok == 10) ? 1 : 0;
5612 as_warn (_("Can't deal with expression; defaulting to %ld"),
5617 if (exp->size != SIZE_UNSPEC)
5625 if (!isbyte (offs (exp)))
5626 as_warn (_("expression doesn't fit in BYTE"));
5629 if (!isword (offs (exp)))
5630 as_warn (_("expression doesn't fit in WORD"));
5638 /* These are the back-ends for the various machine dependent pseudo-ops. */
5641 s_data1 (int ignore ATTRIBUTE_UNUSED)
5643 subseg_set (data_section, 1);
5644 demand_empty_rest_of_line ();
5648 s_data2 (int ignore ATTRIBUTE_UNUSED)
5650 subseg_set (data_section, 2);
5651 demand_empty_rest_of_line ();
5655 s_bss (int ignore ATTRIBUTE_UNUSED)
5657 /* We don't support putting frags in the BSS segment, we fake it
5658 by marking in_bss, then looking at s_skip for clues. */
5660 subseg_set (bss_section, 0);
5661 demand_empty_rest_of_line ();
5665 s_even (int ignore ATTRIBUTE_UNUSED)
5668 register long temp_fill;
5670 temp = 1; /* JF should be 2? */
5671 temp_fill = get_absolute_expression ();
5672 if (!need_pass_2) /* Never make frag if expect extra pass. */
5673 frag_align (temp, (int) temp_fill, 0);
5674 demand_empty_rest_of_line ();
5675 record_alignment (now_seg, temp);
5679 s_proc (int ignore ATTRIBUTE_UNUSED)
5681 demand_empty_rest_of_line ();
5684 /* Pseudo-ops handled for MRI compatibility. */
5686 /* This function returns non-zero if the argument is a conditional
5687 pseudo-op. This is called when checking whether a pending
5688 alignment is needed. */
5691 m68k_conditional_pseudoop (pseudo_typeS *pop)
5693 return (pop->poc_handler == s_mri_if
5694 || pop->poc_handler == s_mri_else);
5697 /* Handle an MRI style chip specification. */
5706 s = input_line_pointer;
5707 /* We can't use get_symbol_end since the processor names are not proper
5709 while (is_part_of_name (c = *input_line_pointer++))
5711 *--input_line_pointer = 0;
5712 for (i = 0; m68k_cpus[i].name; i++)
5713 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5715 if (!m68k_cpus[i].name)
5717 as_bad (_("%s: unrecognized processor name"), s);
5718 *input_line_pointer = c;
5719 ignore_rest_of_line ();
5722 *input_line_pointer = c;
5724 if (*input_line_pointer == '/')
5725 current_architecture = 0;
5727 current_architecture &= m68881 | m68851;
5728 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5729 control_regs = m68k_cpus[i].control_regs;
5731 while (*input_line_pointer == '/')
5733 ++input_line_pointer;
5734 s = input_line_pointer;
5735 /* We can't use get_symbol_end since the processor names are not
5737 while (is_part_of_name (c = *input_line_pointer++))
5739 *--input_line_pointer = 0;
5740 if (strcmp (s, "68881") == 0)
5741 current_architecture |= m68881;
5742 else if (strcmp (s, "68851") == 0)
5743 current_architecture |= m68851;
5744 *input_line_pointer = c;
5748 /* The MRI CHIP pseudo-op. */
5751 s_chip (int ignore ATTRIBUTE_UNUSED)
5757 stop = mri_comment_field (&stopc);
5760 mri_comment_end (stop, stopc);
5761 demand_empty_rest_of_line ();
5764 /* The MRI FOPT pseudo-op. */
5767 s_fopt (int ignore ATTRIBUTE_UNUSED)
5771 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5775 input_line_pointer += 3;
5776 temp = get_absolute_expression ();
5777 if (temp < 0 || temp > 7)
5778 as_bad (_("bad coprocessor id"));
5780 m68k_float_copnum = COP0 + temp;
5784 as_bad (_("unrecognized fopt option"));
5785 ignore_rest_of_line ();
5789 demand_empty_rest_of_line ();
5792 /* The structure used to handle the MRI OPT pseudo-op. */
5796 /* The name of the option. */
5799 /* If this is not NULL, just call this function. The first argument
5800 is the ARG field of this structure, the second argument is
5801 whether the option was negated. */
5802 void (*pfn) (int arg, int on);
5804 /* If this is not NULL, and the PFN field is NULL, set the variable
5805 this points to. Set it to the ARG field if the option was not
5806 negated, and the NOTARG field otherwise. */
5809 /* The value to pass to PFN or to assign to *PVAR. */
5812 /* The value to assign to *PVAR if the option is negated. If PFN is
5813 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5814 the option may not be negated. */
5818 /* The table used to handle the MRI OPT pseudo-op. */
5820 static void skip_to_comma (int, int);
5821 static void opt_nest (int, int);
5822 static void opt_chip (int, int);
5823 static void opt_list (int, int);
5824 static void opt_list_symbols (int, int);
5826 static const struct opt_action opt_table[] =
5828 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5830 /* We do relaxing, so there is little use for these options. */
5831 { "b", 0, 0, 0, 0 },
5832 { "brs", 0, 0, 0, 0 },
5833 { "brb", 0, 0, 0, 0 },
5834 { "brl", 0, 0, 0, 0 },
5835 { "brw", 0, 0, 0, 0 },
5837 { "c", 0, 0, 0, 0 },
5838 { "cex", 0, 0, 0, 0 },
5839 { "case", 0, &symbols_case_sensitive, 1, 0 },
5840 { "cl", 0, 0, 0, 0 },
5841 { "cre", 0, 0, 0, 0 },
5842 { "d", 0, &flag_keep_locals, 1, 0 },
5843 { "e", 0, 0, 0, 0 },
5844 { "f", 0, &flag_short_refs, 1, 0 },
5845 { "frs", 0, &flag_short_refs, 1, 0 },
5846 { "frl", 0, &flag_short_refs, 0, 1 },
5847 { "g", 0, 0, 0, 0 },
5848 { "i", 0, 0, 0, 0 },
5849 { "m", 0, 0, 0, 0 },
5850 { "mex", 0, 0, 0, 0 },
5851 { "mc", 0, 0, 0, 0 },
5852 { "md", 0, 0, 0, 0 },
5853 { "nest", opt_nest, 0, 0, 0 },
5854 { "next", skip_to_comma, 0, 0, 0 },
5855 { "o", 0, 0, 0, 0 },
5856 { "old", 0, 0, 0, 0 },
5857 { "op", skip_to_comma, 0, 0, 0 },
5858 { "pco", 0, 0, 0, 0 },
5859 { "p", opt_chip, 0, 0, 0 },
5860 { "pcr", 0, 0, 0, 0 },
5861 { "pcs", 0, 0, 0, 0 },
5862 { "r", 0, 0, 0, 0 },
5863 { "quick", 0, &m68k_quick, 1, 0 },
5864 { "rel32", 0, &m68k_rel32, 1, 0 },
5865 { "s", opt_list, 0, 0, 0 },
5866 { "t", opt_list_symbols, 0, 0, 0 },
5867 { "w", 0, &flag_no_warnings, 0, 1 },
5871 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5873 /* The MRI OPT pseudo-op. */
5876 s_opt (int ignore ATTRIBUTE_UNUSED)
5884 const struct opt_action *o;
5889 if (*input_line_pointer == '-')
5891 ++input_line_pointer;
5894 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5896 input_line_pointer += 2;
5900 s = input_line_pointer;
5901 c = get_symbol_end ();
5903 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5905 if (strcasecmp (s, o->name) == 0)
5909 /* Restore input_line_pointer now in case the option
5911 *input_line_pointer = c;
5912 (*o->pfn) (o->arg, t);
5914 else if (o->pvar != NULL)
5916 if (! t && o->arg == o->notarg)
5917 as_bad (_("option `%s' may not be negated"), s);
5918 *input_line_pointer = c;
5919 *o->pvar = t ? o->arg : o->notarg;
5922 *input_line_pointer = c;
5928 as_bad (_("option `%s' not recognized"), s);
5929 *input_line_pointer = c;
5932 while (*input_line_pointer++ == ',');
5934 /* Move back to terminating character. */
5935 --input_line_pointer;
5936 demand_empty_rest_of_line ();
5939 /* Skip ahead to a comma. This is used for OPT options which we do
5940 not support and which take arguments. */
5943 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5945 while (*input_line_pointer != ','
5946 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5947 ++input_line_pointer;
5950 /* Handle the OPT NEST=depth option. */
5953 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5955 if (*input_line_pointer != '=')
5957 as_bad (_("bad format of OPT NEST=depth"));
5961 ++input_line_pointer;
5962 max_macro_nest = get_absolute_expression ();
5965 /* Handle the OPT P=chip option. */
5968 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5970 if (*input_line_pointer != '=')
5972 /* This is just OPT P, which we do not support. */
5976 ++input_line_pointer;
5980 /* Handle the OPT S option. */
5983 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5988 /* Handle the OPT T option. */
5991 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5994 listing |= LISTING_SYMBOLS;
5996 listing &= ~LISTING_SYMBOLS;
5999 /* Handle the MRI REG pseudo-op. */
6002 s_reg (int ignore ATTRIBUTE_UNUSED)
6011 if (line_label == NULL)
6013 as_bad (_("missing label"));
6014 ignore_rest_of_line ();
6019 stop = mri_comment_field (&stopc);
6023 s = input_line_pointer;
6024 while (ISALNUM (*input_line_pointer)
6025 #ifdef REGISTER_PREFIX
6026 || *input_line_pointer == REGISTER_PREFIX
6028 || *input_line_pointer == '/'
6029 || *input_line_pointer == '-')
6030 ++input_line_pointer;
6031 c = *input_line_pointer;
6032 *input_line_pointer = '\0';
6034 if (m68k_ip_op (s, &rop) != 0)
6036 if (rop.error == NULL)
6037 as_bad (_("bad register list"));
6039 as_bad (_("bad register list: %s"), rop.error);
6040 *input_line_pointer = c;
6041 ignore_rest_of_line ();
6045 *input_line_pointer = c;
6047 if (rop.mode == REGLST)
6049 else if (rop.mode == DREG)
6050 mask = 1 << (rop.reg - DATA0);
6051 else if (rop.mode == AREG)
6052 mask = 1 << (rop.reg - ADDR0 + 8);
6053 else if (rop.mode == FPREG)
6054 mask = 1 << (rop.reg - FP0 + 16);
6055 else if (rop.mode == CONTROL
6058 else if (rop.mode == CONTROL
6061 else if (rop.mode == CONTROL
6066 as_bad (_("bad register list"));
6067 ignore_rest_of_line ();
6071 S_SET_SEGMENT (line_label, reg_section);
6072 S_SET_VALUE (line_label, ~mask);
6073 symbol_set_frag (line_label, &zero_address_frag);
6076 mri_comment_end (stop, stopc);
6078 demand_empty_rest_of_line ();
6081 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
6085 struct save_opts *next;
6087 int symbols_case_sensitive;
6091 const enum m68k_register *control_regs;
6096 /* FIXME: We don't save OPT S. */
6099 /* This variable holds the stack of saved options. */
6101 static struct save_opts *save_stack;
6103 /* The MRI SAVE pseudo-op. */
6106 s_save (int ignore ATTRIBUTE_UNUSED)
6108 struct save_opts *s;
6110 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
6111 s->abspcadd = m68k_abspcadd;
6112 s->symbols_case_sensitive = symbols_case_sensitive;
6113 s->keep_locals = flag_keep_locals;
6114 s->short_refs = flag_short_refs;
6115 s->architecture = current_architecture;
6116 s->control_regs = control_regs;
6117 s->quick = m68k_quick;
6118 s->rel32 = m68k_rel32;
6119 s->listing = listing;
6120 s->no_warnings = flag_no_warnings;
6122 s->next = save_stack;
6125 demand_empty_rest_of_line ();
6128 /* The MRI RESTORE pseudo-op. */
6131 s_restore (int ignore ATTRIBUTE_UNUSED)
6133 struct save_opts *s;
6135 if (save_stack == NULL)
6137 as_bad (_("restore without save"));
6138 ignore_rest_of_line ();
6143 save_stack = s->next;
6145 m68k_abspcadd = s->abspcadd;
6146 symbols_case_sensitive = s->symbols_case_sensitive;
6147 flag_keep_locals = s->keep_locals;
6148 flag_short_refs = s->short_refs;
6149 current_architecture = s->architecture;
6150 control_regs = s->control_regs;
6151 m68k_quick = s->quick;
6152 m68k_rel32 = s->rel32;
6153 listing = s->listing;
6154 flag_no_warnings = s->no_warnings;
6158 demand_empty_rest_of_line ();
6161 /* Types of MRI structured control directives. */
6163 enum mri_control_type
6171 /* This structure is used to stack the MRI structured control
6174 struct mri_control_info
6176 /* The directive within which this one is enclosed. */
6177 struct mri_control_info *outer;
6179 /* The type of directive. */
6180 enum mri_control_type type;
6182 /* Whether an ELSE has been in an IF. */
6185 /* The add or sub statement at the end of a FOR. */
6188 /* The label of the top of a FOR or REPEAT loop. */
6191 /* The label to jump to for the next iteration, or the else
6192 expression of a conditional. */
6195 /* The label to jump to to break out of the loop, or the label past
6196 the end of a conditional. */
6200 /* The stack of MRI structured control directives. */
6202 static struct mri_control_info *mri_control_stack;
6204 /* The current MRI structured control directive index number, used to
6205 generate label names. */
6207 static int mri_control_index;
6209 /* Assemble an instruction for an MRI structured control directive. */
6212 mri_assemble (char *str)
6216 /* md_assemble expects the opcode to be in lower case. */
6217 for (s = str; *s != ' ' && *s != '\0'; s++)
6223 /* Generate a new MRI label structured control directive label name. */
6226 mri_control_label (void)
6230 n = (char *) xmalloc (20);
6231 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6232 ++mri_control_index;
6236 /* Create a new MRI structured control directive. */
6238 static struct mri_control_info *
6239 push_mri_control (enum mri_control_type type)
6241 struct mri_control_info *n;
6243 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6247 if (type == mri_if || type == mri_while)
6250 n->top = mri_control_label ();
6251 n->next = mri_control_label ();
6252 n->bottom = mri_control_label ();
6254 n->outer = mri_control_stack;
6255 mri_control_stack = n;
6260 /* Pop off the stack of MRI structured control directives. */
6263 pop_mri_control (void)
6265 struct mri_control_info *n;
6267 n = mri_control_stack;
6268 mri_control_stack = n->outer;
6276 /* Recognize a condition code in an MRI structured control expression. */
6279 parse_mri_condition (int *pcc)
6283 know (*input_line_pointer == '<');
6285 ++input_line_pointer;
6286 c1 = *input_line_pointer++;
6287 c2 = *input_line_pointer++;
6289 if (*input_line_pointer != '>')
6291 as_bad (_("syntax error in structured control directive"));
6295 ++input_line_pointer;
6301 *pcc = (c1 << 8) | c2;
6306 /* Parse a single operand in an MRI structured control expression. */
6309 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6310 char **rightstart, char **rightstop)
6322 if (*input_line_pointer == '<')
6324 /* It's just a condition code. */
6325 return parse_mri_condition (pcc);
6328 /* Look ahead for the condition code. */
6329 for (s = input_line_pointer; *s != '\0'; ++s)
6331 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6336 as_bad (_("missing condition code in structured control directive"));
6340 *leftstart = input_line_pointer;
6342 if (*leftstop > *leftstart
6343 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6346 input_line_pointer = s;
6347 if (! parse_mri_condition (pcc))
6350 /* Look ahead for AND or OR or end of line. */
6351 for (s = input_line_pointer; *s != '\0'; ++s)
6353 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6354 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6356 if ((s == input_line_pointer
6359 && ((strncasecmp (s, "AND", 3) == 0
6360 && (s[3] == '.' || ! is_part_of_name (s[3])))
6361 || (strncasecmp (s, "OR", 2) == 0
6362 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6366 *rightstart = input_line_pointer;
6368 if (*rightstop > *rightstart
6369 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6372 input_line_pointer = s;
6377 #define MCC(b1, b2) (((b1) << 8) | (b2))
6379 /* Swap the sense of a condition. This changes the condition so that
6380 it generates the same result when the operands are swapped. */
6383 swap_mri_condition (int cc)
6387 case MCC ('h', 'i'): return MCC ('c', 's');
6388 case MCC ('l', 's'): return MCC ('c', 'c');
6389 /* <HS> is an alias for <CC>. */
6390 case MCC ('h', 's'):
6391 case MCC ('c', 'c'): return MCC ('l', 's');
6392 /* <LO> is an alias for <CS>. */
6393 case MCC ('l', 'o'):
6394 case MCC ('c', 's'): return MCC ('h', 'i');
6395 case MCC ('p', 'l'): return MCC ('m', 'i');
6396 case MCC ('m', 'i'): return MCC ('p', 'l');
6397 case MCC ('g', 'e'): return MCC ('l', 'e');
6398 case MCC ('l', 't'): return MCC ('g', 't');
6399 case MCC ('g', 't'): return MCC ('l', 't');
6400 case MCC ('l', 'e'): return MCC ('g', 'e');
6401 /* Issue a warning for conditions we can not swap. */
6402 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6403 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6404 case MCC ('v', 'c'):
6405 case MCC ('v', 's'):
6407 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6408 (char) (cc >> 8), (char) (cc));
6414 /* Reverse the sense of a condition. */
6417 reverse_mri_condition (int cc)
6421 case MCC ('h', 'i'): return MCC ('l', 's');
6422 case MCC ('l', 's'): return MCC ('h', 'i');
6423 /* <HS> is an alias for <CC> */
6424 case MCC ('h', 's'): return MCC ('l', 'o');
6425 case MCC ('c', 'c'): return MCC ('c', 's');
6426 /* <LO> is an alias for <CS> */
6427 case MCC ('l', 'o'): return MCC ('h', 's');
6428 case MCC ('c', 's'): return MCC ('c', 'c');
6429 case MCC ('n', 'e'): return MCC ('e', 'q');
6430 case MCC ('e', 'q'): return MCC ('n', 'e');
6431 case MCC ('v', 'c'): return MCC ('v', 's');
6432 case MCC ('v', 's'): return MCC ('v', 'c');
6433 case MCC ('p', 'l'): return MCC ('m', 'i');
6434 case MCC ('m', 'i'): return MCC ('p', 'l');
6435 case MCC ('g', 'e'): return MCC ('l', 't');
6436 case MCC ('l', 't'): return MCC ('g', 'e');
6437 case MCC ('g', 't'): return MCC ('l', 'e');
6438 case MCC ('l', 'e'): return MCC ('g', 't');
6443 /* Build an MRI structured control expression. This generates test
6444 and branch instructions. It goes to TRUELAB if the condition is
6445 true, and to FALSELAB if the condition is false. Exactly one of
6446 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6447 is the size qualifier for the expression. EXTENT is the size to
6448 use for the branch. */
6451 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6452 char *rightstart, char *rightstop,
6453 const char *truelab, const char *falselab,
6459 if (leftstart != NULL)
6461 struct m68k_op leftop, rightop;
6464 /* Swap the compare operands, if necessary, to produce a legal
6465 m68k compare instruction. Comparing a register operand with
6466 a non-register operand requires the register to be on the
6467 right (cmp, cmpa). Comparing an immediate value with
6468 anything requires the immediate value to be on the left
6473 (void) m68k_ip_op (leftstart, &leftop);
6478 (void) m68k_ip_op (rightstart, &rightop);
6481 if (rightop.mode == IMMED
6482 || ((leftop.mode == DREG || leftop.mode == AREG)
6483 && (rightop.mode != DREG && rightop.mode != AREG)))
6487 /* Correct conditional handling:
6488 if #1 <lt> d0 then ;means if (1 < d0)
6494 cmp #1,d0 if we do *not* swap the operands
6495 bgt true we need the swapped condition!
6502 leftstart = rightstart;
6505 leftstop = rightstop;
6510 cc = swap_mri_condition (cc);
6514 if (truelab == NULL)
6516 cc = reverse_mri_condition (cc);
6520 if (leftstart != NULL)
6522 buf = (char *) xmalloc (20
6523 + (leftstop - leftstart)
6524 + (rightstop - rightstart));
6530 *s++ = TOLOWER (qual);
6532 memcpy (s, leftstart, leftstop - leftstart);
6533 s += leftstop - leftstart;
6535 memcpy (s, rightstart, rightstop - rightstart);
6536 s += rightstop - rightstart;
6542 buf = (char *) xmalloc (20 + strlen (truelab));
6548 *s++ = TOLOWER (extent);
6550 strcpy (s, truelab);
6555 /* Parse an MRI structured control expression. This generates test
6556 and branch instructions. STOP is where the expression ends. It
6557 goes to TRUELAB if the condition is true, and to FALSELAB if the
6558 condition is false. Exactly one of TRUELAB and FALSELAB will be
6559 NULL, meaning to fall through. QUAL is the size qualifier for the
6560 expression. EXTENT is the size to use for the branch. */
6563 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6564 const char *falselab, int extent)
6576 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6577 &rightstart, &rightstop))
6583 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6587 if (falselab != NULL)
6590 flab = mri_control_label ();
6592 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6593 rightstop, (const char *) NULL, flab, extent);
6595 input_line_pointer += 3;
6596 if (*input_line_pointer != '.'
6597 || input_line_pointer[1] == '\0')
6601 qual = input_line_pointer[1];
6602 input_line_pointer += 2;
6605 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6606 &rightstart, &rightstop))
6612 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6613 rightstop, truelab, falselab, extent);
6615 if (falselab == NULL)
6618 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6622 if (truelab != NULL)
6625 tlab = mri_control_label ();
6627 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6628 rightstop, tlab, (const char *) NULL, extent);
6630 input_line_pointer += 2;
6631 if (*input_line_pointer != '.'
6632 || input_line_pointer[1] == '\0')
6636 qual = input_line_pointer[1];
6637 input_line_pointer += 2;
6640 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6641 &rightstart, &rightstop))
6647 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6648 rightstop, truelab, falselab, extent);
6650 if (truelab == NULL)
6655 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6656 rightstop, truelab, falselab, extent);
6660 if (input_line_pointer != stop)
6661 as_bad (_("syntax error in structured control directive"));
6664 /* Handle the MRI IF pseudo-op. This may be a structured control
6665 directive, or it may be a regular assembler conditional, depending
6673 struct mri_control_info *n;
6675 /* A structured control directive must end with THEN with an
6676 optional qualifier. */
6677 s = input_line_pointer;
6678 /* We only accept '*' as introduction of comments if preceded by white space
6679 or at first column of a line (I think this can't actually happen here?)
6680 This is important when assembling:
6681 if d0 <ne> 12(a0,d0*2) then
6682 if d0 <ne> #CONST*20 then. */
6683 while (! (is_end_of_line[(unsigned char) *s]
6686 && (s == input_line_pointer
6688 || *(s-1) == '\t'))))
6691 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6694 if (s - input_line_pointer > 1
6698 if (s - input_line_pointer < 3
6699 || strncasecmp (s - 3, "THEN", 4) != 0)
6703 as_bad (_("missing then"));
6704 ignore_rest_of_line ();
6708 /* It's a conditional. */
6713 /* Since this might be a conditional if, this pseudo-op will be
6714 called even if we are supported to be ignoring input. Double
6715 check now. Clobber *input_line_pointer so that ignore_input
6716 thinks that this is not a special pseudo-op. */
6717 c = *input_line_pointer;
6718 *input_line_pointer = 0;
6719 if (ignore_input ())
6721 *input_line_pointer = c;
6722 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6723 ++input_line_pointer;
6724 demand_empty_rest_of_line ();
6727 *input_line_pointer = c;
6729 n = push_mri_control (mri_if);
6731 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6732 n->next, s[1] == '.' ? s[2] : '\0');
6735 input_line_pointer = s + 3;
6737 input_line_pointer = s + 1;
6741 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6742 ++input_line_pointer;
6745 demand_empty_rest_of_line ();
6748 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6749 structured IF, associate the ELSE with the IF. Otherwise, assume
6750 it is a conditional else. */
6753 s_mri_else (int qual)
6760 && (mri_control_stack == NULL
6761 || mri_control_stack->type != mri_if
6762 || mri_control_stack->else_seen))
6768 c = *input_line_pointer;
6769 *input_line_pointer = 0;
6770 if (ignore_input ())
6772 *input_line_pointer = c;
6773 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6774 ++input_line_pointer;
6775 demand_empty_rest_of_line ();
6778 *input_line_pointer = c;
6780 if (mri_control_stack == NULL
6781 || mri_control_stack->type != mri_if
6782 || mri_control_stack->else_seen)
6784 as_bad (_("else without matching if"));
6785 ignore_rest_of_line ();
6789 mri_control_stack->else_seen = 1;
6791 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6792 q[0] = TOLOWER (qual);
6794 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6798 colon (mri_control_stack->next);
6802 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6803 ++input_line_pointer;
6806 demand_empty_rest_of_line ();
6809 /* Handle the MRI ENDI pseudo-op. */
6812 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6814 if (mri_control_stack == NULL
6815 || mri_control_stack->type != mri_if)
6817 as_bad (_("endi without matching if"));
6818 ignore_rest_of_line ();
6822 /* ignore_input will not return true for ENDI, so we don't need to
6823 worry about checking it again here. */
6825 if (! mri_control_stack->else_seen)
6826 colon (mri_control_stack->next);
6827 colon (mri_control_stack->bottom);
6833 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6834 ++input_line_pointer;
6837 demand_empty_rest_of_line ();
6840 /* Handle the MRI BREAK pseudo-op. */
6843 s_mri_break (int extent)
6845 struct mri_control_info *n;
6849 n = mri_control_stack;
6851 && n->type != mri_for
6852 && n->type != mri_repeat
6853 && n->type != mri_while)
6857 as_bad (_("break outside of structured loop"));
6858 ignore_rest_of_line ();
6862 buf = (char *) xmalloc (20 + strlen (n->bottom));
6863 ex[0] = TOLOWER (extent);
6865 sprintf (buf, "bra%s %s", ex, n->bottom);
6871 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6872 ++input_line_pointer;
6875 demand_empty_rest_of_line ();
6878 /* Handle the MRI NEXT pseudo-op. */
6881 s_mri_next (int extent)
6883 struct mri_control_info *n;
6887 n = mri_control_stack;
6889 && n->type != mri_for
6890 && n->type != mri_repeat
6891 && n->type != mri_while)
6895 as_bad (_("next outside of structured loop"));
6896 ignore_rest_of_line ();
6900 buf = (char *) xmalloc (20 + strlen (n->next));
6901 ex[0] = TOLOWER (extent);
6903 sprintf (buf, "bra%s %s", ex, n->next);
6909 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6910 ++input_line_pointer;
6913 demand_empty_rest_of_line ();
6916 /* Handle the MRI FOR pseudo-op. */
6919 s_mri_for (int qual)
6921 const char *varstart, *varstop;
6922 const char *initstart, *initstop;
6923 const char *endstart, *endstop;
6924 const char *bystart, *bystop;
6928 struct mri_control_info *n;
6934 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6938 varstart = input_line_pointer;
6940 /* Look for the '='. */
6941 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6942 && *input_line_pointer != '=')
6943 ++input_line_pointer;
6944 if (*input_line_pointer != '=')
6946 as_bad (_("missing ="));
6947 ignore_rest_of_line ();
6951 varstop = input_line_pointer;
6952 if (varstop > varstart
6953 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6956 ++input_line_pointer;
6958 initstart = input_line_pointer;
6960 /* Look for TO or DOWNTO. */
6963 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6965 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6966 && ! is_part_of_name (input_line_pointer[2]))
6968 initstop = input_line_pointer;
6969 input_line_pointer += 2;
6972 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6973 && ! is_part_of_name (input_line_pointer[6]))
6975 initstop = input_line_pointer;
6977 input_line_pointer += 6;
6980 ++input_line_pointer;
6982 if (initstop == NULL)
6984 as_bad (_("missing to or downto"));
6985 ignore_rest_of_line ();
6988 if (initstop > initstart
6989 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6993 endstart = input_line_pointer;
6995 /* Look for BY or DO. */
6998 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7000 if (strncasecmp (input_line_pointer, "BY", 2) == 0
7001 && ! is_part_of_name (input_line_pointer[2]))
7003 endstop = input_line_pointer;
7005 input_line_pointer += 2;
7008 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7009 && (input_line_pointer[2] == '.'
7010 || ! is_part_of_name (input_line_pointer[2])))
7012 endstop = input_line_pointer;
7013 input_line_pointer += 2;
7016 ++input_line_pointer;
7018 if (endstop == NULL)
7020 as_bad (_("missing do"));
7021 ignore_rest_of_line ();
7024 if (endstop > endstart
7025 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
7031 bystop = bystart + 2;
7036 bystart = input_line_pointer;
7040 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7042 if (strncasecmp (input_line_pointer, "DO", 2) == 0
7043 && (input_line_pointer[2] == '.'
7044 || ! is_part_of_name (input_line_pointer[2])))
7046 bystop = input_line_pointer;
7047 input_line_pointer += 2;
7050 ++input_line_pointer;
7054 as_bad (_("missing do"));
7055 ignore_rest_of_line ();
7058 if (bystop > bystart
7059 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
7063 if (*input_line_pointer != '.')
7067 extent = input_line_pointer[1];
7068 input_line_pointer += 2;
7071 /* We have fully parsed the FOR operands. Now build the loop. */
7072 n = push_mri_control (mri_for);
7074 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
7076 /* Move init,var. */
7083 *s++ = TOLOWER (qual);
7085 memcpy (s, initstart, initstop - initstart);
7086 s += initstop - initstart;
7088 memcpy (s, varstart, varstop - varstart);
7089 s += varstop - varstart;
7101 *s++ = TOLOWER (qual);
7103 memcpy (s, endstart, endstop - endstart);
7104 s += endstop - endstart;
7106 memcpy (s, varstart, varstop - varstart);
7107 s += varstop - varstart;
7112 ex[0] = TOLOWER (extent);
7115 sprintf (buf, "blt%s %s", ex, n->bottom);
7117 sprintf (buf, "bgt%s %s", ex, n->bottom);
7120 /* Put together the add or sub instruction used by ENDF. */
7128 *s++ = TOLOWER (qual);
7130 memcpy (s, bystart, bystop - bystart);
7131 s += bystop - bystart;
7133 memcpy (s, varstart, varstop - varstart);
7134 s += varstop - varstart;
7140 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7141 ++input_line_pointer;
7144 demand_empty_rest_of_line ();
7147 /* Handle the MRI ENDF pseudo-op. */
7150 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
7152 if (mri_control_stack == NULL
7153 || mri_control_stack->type != mri_for)
7155 as_bad (_("endf without for"));
7156 ignore_rest_of_line ();
7160 colon (mri_control_stack->next);
7162 mri_assemble (mri_control_stack->incr);
7164 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7165 mri_assemble (mri_control_stack->incr);
7167 free (mri_control_stack->incr);
7169 colon (mri_control_stack->bottom);
7175 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7176 ++input_line_pointer;
7179 demand_empty_rest_of_line ();
7182 /* Handle the MRI REPEAT pseudo-op. */
7185 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
7187 struct mri_control_info *n;
7189 n = push_mri_control (mri_repeat);
7193 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7194 ++input_line_pointer;
7196 demand_empty_rest_of_line ();
7199 /* Handle the MRI UNTIL pseudo-op. */
7202 s_mri_until (int qual)
7206 if (mri_control_stack == NULL
7207 || mri_control_stack->type != mri_repeat)
7209 as_bad (_("until without repeat"));
7210 ignore_rest_of_line ();
7214 colon (mri_control_stack->next);
7216 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7219 parse_mri_control_expression (s, qual, (const char *) NULL,
7220 mri_control_stack->top, '\0');
7222 colon (mri_control_stack->bottom);
7224 input_line_pointer = s;
7230 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7231 ++input_line_pointer;
7234 demand_empty_rest_of_line ();
7237 /* Handle the MRI WHILE pseudo-op. */
7240 s_mri_while (int qual)
7244 struct mri_control_info *n;
7246 s = input_line_pointer;
7247 /* We only accept '*' as introduction of comments if preceded by white space
7248 or at first column of a line (I think this can't actually happen here?)
7249 This is important when assembling:
7250 while d0 <ne> 12(a0,d0*2) do
7251 while d0 <ne> #CONST*20 do. */
7252 while (! (is_end_of_line[(unsigned char) *s]
7255 && (s == input_line_pointer
7257 || *(s-1) == '\t'))))
7260 while (*s == ' ' || *s == '\t')
7262 if (s - input_line_pointer > 1
7265 if (s - input_line_pointer < 2
7266 || strncasecmp (s - 1, "DO", 2) != 0)
7268 as_bad (_("missing do"));
7269 ignore_rest_of_line ();
7273 n = push_mri_control (mri_while);
7277 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7278 s[1] == '.' ? s[2] : '\0');
7280 input_line_pointer = s + 1;
7281 if (*input_line_pointer == '.')
7282 input_line_pointer += 2;
7286 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7287 ++input_line_pointer;
7290 demand_empty_rest_of_line ();
7293 /* Handle the MRI ENDW pseudo-op. */
7296 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7300 if (mri_control_stack == NULL
7301 || mri_control_stack->type != mri_while)
7303 as_bad (_("endw without while"));
7304 ignore_rest_of_line ();
7308 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7309 sprintf (buf, "bra %s", mri_control_stack->next);
7313 colon (mri_control_stack->bottom);
7319 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7320 ++input_line_pointer;
7323 demand_empty_rest_of_line ();
7326 /* Parse a .cpu directive. */
7329 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7336 as_bad (_("already assembled instructions"));
7337 ignore_rest_of_line ();
7341 name = input_line_pointer;
7342 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7343 input_line_pointer++;
7344 saved_char = *input_line_pointer;
7345 *input_line_pointer = 0;
7347 m68k_set_cpu (name, 1, 0);
7349 *input_line_pointer = saved_char;
7350 demand_empty_rest_of_line ();
7354 /* Parse a .arch directive. */
7357 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7364 as_bad (_("already assembled instructions"));
7365 ignore_rest_of_line ();
7369 name = input_line_pointer;
7370 while (*input_line_pointer && *input_line_pointer != ','
7371 && !ISSPACE (*input_line_pointer))
7372 input_line_pointer++;
7373 saved_char = *input_line_pointer;
7374 *input_line_pointer = 0;
7376 if (m68k_set_arch (name, 1, 0))
7378 /* Scan extensions. */
7381 *input_line_pointer++ = saved_char;
7382 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7384 name = input_line_pointer;
7385 while (*input_line_pointer && *input_line_pointer != ','
7386 && !ISSPACE (*input_line_pointer))
7387 input_line_pointer++;
7388 saved_char = *input_line_pointer;
7389 *input_line_pointer = 0;
7391 while (m68k_set_extension (name, 1, 0));
7394 *input_line_pointer = saved_char;
7395 demand_empty_rest_of_line ();
7399 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7400 if none is found, the caller is responsible for emitting an error
7401 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7402 cpu name, if it begins with a '6' (possibly skipping an intervening
7403 'c'. We also allow a 'c' in the same place. if NEGATED is
7404 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7405 the option is indeed negated. */
7407 static const struct m68k_cpu *
7408 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7409 int allow_m, int *negated)
7411 /* allow negated value? */
7416 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7423 /* Remove 'm' or 'mc' prefix from 68k variants. */
7430 else if (arg[1] == 'c' && arg[2] == '6')
7434 else if (arg[0] == 'c' && arg[1] == '6')
7437 for (; table->name; table++)
7438 if (!strcmp (arg, table->name))
7440 if (table->alias < -1 || table->alias > 1)
7441 as_bad (_("`%s' is deprecated, use `%s'"),
7442 table->name, table[table->alias < 0 ? 1 : -1].name);
7448 /* Set the cpu, issuing errors if it is unrecognized. */
7451 m68k_set_cpu (char const *name, int allow_m, int silent)
7453 const struct m68k_cpu *cpu;
7455 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7460 as_bad (_("cpu `%s' unrecognized"), name);
7467 /* Set the architecture, issuing errors if it is unrecognized. */
7470 m68k_set_arch (char const *name, int allow_m, int silent)
7472 const struct m68k_cpu *arch;
7474 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7479 as_bad (_("architecture `%s' unrecognized"), name);
7482 selected_arch = arch;
7486 /* Set the architecture extension, issuing errors if it is
7487 unrecognized, or invalid */
7490 m68k_set_extension (char const *name, int allow_m, int silent)
7493 const struct m68k_cpu *ext;
7495 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7500 as_bad (_("extension `%s' unrecognized"), name);
7505 not_current_architecture |= (ext->control_regs
7506 ? *(unsigned *)ext->control_regs: ext->arch);
7508 current_architecture |= ext->arch;
7513 Invocation line includes a switch not recognized by the base assembler.
7517 const char *md_shortopts = "lSA:m:kQ:V";
7519 const char *md_shortopts = "lSA:m:k";
7522 struct option md_longopts[] = {
7523 #define OPTION_PIC (OPTION_MD_BASE)
7524 {"pic", no_argument, NULL, OPTION_PIC},
7525 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7526 {"register-prefix-optional", no_argument, NULL,
7527 OPTION_REGISTER_PREFIX_OPTIONAL},
7528 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7529 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7530 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7531 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7532 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7533 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7534 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7535 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7536 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7537 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7538 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7539 {"pcrel", no_argument, NULL, OPTION_PCREL},
7540 {NULL, no_argument, NULL, 0}
7542 size_t md_longopts_size = sizeof (md_longopts);
7545 md_parse_option (int c, char *arg)
7549 case 'l': /* -l means keep external to 2 bit offset
7550 rather than 16 bit one. */
7551 flag_short_refs = 1;
7554 case 'S': /* -S means that jbsr's always turn into
7556 flag_long_jumps = 1;
7559 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7560 branches into absolute jumps. */
7561 flag_keep_pcrel = 1;
7567 break; /* -pic, Position Independent Code. */
7569 case OPTION_REGISTER_PREFIX_OPTIONAL:
7570 flag_reg_prefix_optional = 1;
7571 reg_prefix_optional_seen = 1;
7574 /* -V: SVR4 argument to print version ID. */
7576 print_version_id ();
7579 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7580 should be emitted or not. FIXME: Not implemented. */
7584 case OPTION_BITWISE_OR:
7589 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7591 for (s = m68k_comment_chars; *s != '\0'; s++)
7595 m68k_comment_chars = n;
7599 case OPTION_BASE_SIZE_DEFAULT_16:
7600 m68k_index_width_default = SIZE_WORD;
7603 case OPTION_BASE_SIZE_DEFAULT_32:
7604 m68k_index_width_default = SIZE_LONG;
7607 case OPTION_DISP_SIZE_DEFAULT_16:
7609 m68k_rel32_from_cmdline = 1;
7612 case OPTION_DISP_SIZE_DEFAULT_32:
7614 m68k_rel32_from_cmdline = 1;
7619 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7622 /* Intentional fall-through. */
7624 if (!strncmp (arg, "arch=", 5))
7625 m68k_set_arch (arg + 5, 1, 0);
7626 else if (!strncmp (arg, "cpu=", 4))
7627 m68k_set_cpu (arg + 4, 1, 0);
7628 else if (m68k_set_extension (arg, 0, 1))
7630 else if (m68k_set_arch (arg, 0, 1))
7632 else if (m68k_set_cpu (arg, 0, 1))
7645 /* Setup tables from the selected arch and/or cpu */
7648 m68k_init_arch (void)
7650 if (not_current_architecture & current_architecture)
7652 as_bad (_("architecture features both enabled and disabled"));
7653 not_current_architecture &= ~current_architecture;
7657 current_architecture |= selected_arch->arch;
7658 control_regs = selected_arch->control_regs;
7661 current_architecture |= selected_cpu->arch;
7663 current_architecture &= ~not_current_architecture;
7665 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7667 /* Determine which float is really meant. */
7668 if (current_architecture & (m68k_mask & ~m68881))
7669 current_architecture ^= cfloat;
7671 current_architecture ^= m68881;
7676 control_regs = selected_cpu->control_regs;
7677 if (current_architecture & ~selected_cpu->arch)
7679 as_bad (_("selected processor does not have all features of selected architecture"));
7680 current_architecture
7681 = selected_cpu->arch & ~not_current_architecture;
7685 if ((current_architecture & m68k_mask)
7686 && (current_architecture & ~m68k_mask))
7688 as_bad (_ ("m68k and cf features both selected"));
7689 if (current_architecture & m68k_mask)
7690 current_architecture &= m68k_mask;
7692 current_architecture &= ~m68k_mask;
7695 /* Permit m68881 specification with all cpus; those that can't work
7696 with a coprocessor could be doing emulation. */
7697 if (current_architecture & m68851)
7699 if (current_architecture & m68040)
7700 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7702 /* What other incompatibilities could we check for? */
7704 if (cpu_of_arch (current_architecture) < m68020
7705 || arch_coldfire_p (current_architecture))
7706 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7712 md_show_usage (FILE *stream)
7714 const char *default_cpu = TARGET_CPU;
7716 unsigned int default_arch;
7718 /* Get the canonical name for the default target CPU. */
7719 if (*default_cpu == 'm')
7721 for (i = 0; m68k_cpus[i].name; i++)
7723 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7725 default_arch = m68k_cpus[i].arch;
7726 while (m68k_cpus[i].alias > 0)
7728 while (m68k_cpus[i].alias < 0)
7730 default_cpu = m68k_cpus[i].name;
7734 fprintf (stream, _("\
7735 -march=<arch> set architecture\n\
7736 -mcpu=<cpu> set cpu [default %s]\n\
7738 for (i = 0; m68k_extensions[i].name; i++)
7739 fprintf (stream, _("\
7740 -m[no-]%-16s enable/disable%s architecture extension\n\
7741 "), m68k_extensions[i].name,
7742 m68k_extensions[i].alias > 0 ? " ColdFire"
7743 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7745 fprintf (stream, _("\
7746 -l use 1 word for refs to undefined symbols [default 2]\n\
7747 -pic, -k generate position independent code\n\
7748 -S turn jbsr into jsr\n\
7749 --pcrel never turn PC-relative branches into absolute jumps\n\
7750 --register-prefix-optional\n\
7751 recognize register names without prefix character\n\
7752 --bitwise-or do not treat `|' as a comment character\n\
7753 --base-size-default-16 base reg without size is 16 bits\n\
7754 --base-size-default-32 base reg without size is 32 bits (default)\n\
7755 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7756 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7759 fprintf (stream, _("Architecture variants are: "));
7760 for (i = 0; m68k_archs[i].name; i++)
7763 fprintf (stream, " | ");
7764 fprintf (stream, "%s", m68k_archs[i].name);
7766 fprintf (stream, "\n");
7768 fprintf (stream, _("Processor variants are: "));
7769 for (i = 0; m68k_cpus[i].name; i++)
7772 fprintf (stream, " | ");
7773 fprintf (stream, "%s", m68k_cpus[i].name);
7775 fprintf (stream, _("\n"));
7780 /* TEST2: Test md_assemble() */
7781 /* Warning, this routine probably doesn't work anymore. */
7785 struct m68k_it the_ins;
7793 if (!gets (buf) || !*buf)
7795 if (buf[0] == '|' || buf[1] == '.')
7797 for (cp = buf; *cp; cp++)
7802 memset (&the_ins, '\0', sizeof (the_ins));
7803 m68k_ip (&the_ins, buf);
7806 printf (_("Error %s in %s\n"), the_ins.error, buf);
7810 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7811 for (n = 0; n < the_ins.numo; n++)
7812 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7814 print_the_insn (&the_ins.opcode[0], stdout);
7815 (void) putchar ('\n');
7817 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7819 if (the_ins.operands[n].error)
7821 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7824 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7825 the_ins.operands[n].reg);
7826 if (the_ins.operands[n].b_const)
7827 printf ("Constant: '%.*s', ",
7828 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7829 the_ins.operands[n].b_const);
7830 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7831 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7832 if (the_ins.operands[n].b_iadd)
7833 printf ("Iadd: '%.*s',",
7834 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7835 the_ins.operands[n].b_iadd);
7844 is_label (char *str)
7848 while (*str && *str != ' ')
7850 if (str[-1] == ':' || str[1] == '=')
7857 /* Possible states for relaxation:
7859 0 0 branch offset byte (bra, etc)
7863 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7867 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7874 /* We have no need to default values of symbols. */
7877 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7882 /* Round up a section size to the appropriate boundary. */
7884 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7887 /* For a.out, force the section size to be aligned. If we don't do
7888 this, BFD will align it for us, but it will not write out the
7889 final bytes of the section. This may be a bug in BFD, but it is
7890 easier to fix it here since that is how the other a.out targets
7894 align = bfd_get_section_alignment (stdoutput, segment);
7895 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7901 /* Exactly what point is a PC-relative offset relative TO?
7902 On the 68k, it is relative to the address of the first extension
7903 word. The difference between the addresses of the offset and the
7904 first extension word is stored in fx_pcrel_adjust. */
7906 md_pcrel_from (fixS *fixP)
7910 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7911 sign extend the value here. */
7912 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7915 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7920 m68k_elf_final_processing (void)
7924 if (arch_coldfire_fpu (current_architecture))
7925 flags |= EF_M68K_CFV4E;
7926 /* Set file-specific flags if this is a cpu32 processor. */
7927 if (cpu_of_arch (current_architecture) & cpu32)
7928 flags |= EF_M68K_CPU32;
7929 else if (cpu_of_arch (current_architecture) & fido_a)
7930 flags |= EF_M68K_FIDO;
7931 else if ((cpu_of_arch (current_architecture) & m68000up)
7932 && !(cpu_of_arch (current_architecture) & m68020up))
7933 flags |= EF_M68K_M68000;
7935 if (current_architecture & mcfisa_a)
7937 static const unsigned isa_features[][2] =
7939 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7940 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7941 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7942 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7943 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7944 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7945 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7948 static const unsigned mac_features[][2] =
7950 {EF_M68K_CF_MAC, mcfmac},
7951 {EF_M68K_CF_EMAC, mcfemac},
7957 pattern = (current_architecture
7958 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7959 for (ix = 0; isa_features[ix][1]; ix++)
7961 if (pattern == isa_features[ix][1])
7963 flags |= isa_features[ix][0];
7967 if (!isa_features[ix][1])
7970 as_warn (_("Not a defined coldfire architecture"));
7974 if (current_architecture & cfloat)
7975 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7977 pattern = current_architecture & (mcfmac|mcfemac);
7980 for (ix = 0; mac_features[ix][1]; ix++)
7982 if (pattern == mac_features[ix][1])
7984 flags |= mac_features[ix][0];
7988 if (!mac_features[ix][1])
7993 elf_elfheader (stdoutput)->e_flags |= flags;
7996 /* Parse @TLSLDO and return the desired relocation. */
7997 static bfd_reloc_code_real_type
7998 m68k_elf_suffix (char **str_p, expressionS *exp_p)
8007 return BFD_RELOC_UNUSED;
8009 for (ch = *str, str2 = ident;
8010 (str2 < ident + sizeof (ident) - 1
8011 && (ISALNUM (ch) || ch == '@'));
8020 if (strncmp (ident, "TLSLDO", 6) == 0
8023 /* Now check for identifier@suffix+constant. */
8024 if (*str == '-' || *str == '+')
8026 char *orig_line = input_line_pointer;
8027 expressionS new_exp;
8029 input_line_pointer = str;
8030 expression (&new_exp);
8031 if (new_exp.X_op == O_constant)
8033 exp_p->X_add_number += new_exp.X_add_number;
8034 str = input_line_pointer;
8037 if (&input_line_pointer != str_p)
8038 input_line_pointer = orig_line;
8042 return BFD_RELOC_68K_TLS_LDO32;
8045 return BFD_RELOC_UNUSED;
8048 /* Handles .long <tls_symbol>+0x8000 debug info.
8049 Clobbers input_line_pointer, checks end-of-line.
8050 Adapted from tc-ppc.c:ppc_elf_cons. */
8052 m68k_elf_cons (int nbytes /* 4=.long */)
8054 if (is_it_end_of_statement ())
8056 demand_empty_rest_of_line ();
8063 bfd_reloc_code_real_type reloc;
8066 if (exp.X_op == O_symbol
8067 && *input_line_pointer == '@'
8068 && (reloc = m68k_elf_suffix (&input_line_pointer,
8069 &exp)) != BFD_RELOC_UNUSED)
8071 reloc_howto_type *reloc_howto;
8074 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
8075 size = bfd_get_reloc_size (reloc_howto);
8079 as_bad (_("%s relocations do not fit in %d bytes\n"),
8080 reloc_howto->name, nbytes);
8087 p = frag_more (nbytes);
8089 if (target_big_endian)
8090 offset = nbytes - size;
8091 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8096 emit_expr (&exp, (unsigned int) nbytes);
8098 while (*input_line_pointer++ == ',');
8100 /* Put terminator back into stream. */
8101 input_line_pointer--;
8102 demand_empty_rest_of_line ();
8107 tc_m68k_regname_to_dw2regnum (char *regname)
8109 unsigned int regnum;
8110 static const char *const regnames[] =
8112 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8113 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8114 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8118 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
8119 if (strcmp (regname, regnames[regnum]) == 0)
8126 tc_m68k_frame_initial_instructions (void)
8128 static int sp_regno = -1;
8131 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
8133 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
8134 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);