1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
47 const char *m68k_comment_chars = "|";
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
59 const char line_separator_chars[] = ";";
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
86 int flag_reg_prefix_optional;
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
106 static int m68k_rel32 = 1;
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
111 /* The default width to use for an index register when using a base
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
120 struct label_line *next;
127 /* The list of labels. */
129 static struct label_line *labels;
131 /* The current label. */
133 static struct label_line *current_label;
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
138 /* Its an arbitrary name: This means I don't approve of it.
140 static struct obstack robyn;
144 const char *m_operands;
145 unsigned long m_opcode;
149 struct m68k_incant *m_next;
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
179 static const enum m68k_register mcf5206_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
183 static const enum m68k_register mcf5208_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
187 static const enum m68k_register mcf5210a_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
191 static const enum m68k_register mcf5213_ctrl[] = {
192 VBR, RAMBAR, RAMBAR1, FLASHBAR,
195 static const enum m68k_register mcf5216_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
199 static const enum m68k_register mcf52235_ctrl[] = {
200 VBR, FLASHBAR, RAMBAR, RAMBAR1,
203 static const enum m68k_register mcf5225_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
207 static const enum m68k_register mcf5235_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
211 static const enum m68k_register mcf5249_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
215 static const enum m68k_register mcf5250_ctrl[] = {
219 static const enum m68k_register mcf5271_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
223 static const enum m68k_register mcf5272_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
227 static const enum m68k_register mcf5275_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
231 static const enum m68k_register mcf5282_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
235 static const enum m68k_register mcf5307_ctrl[] = {
236 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
239 static const enum m68k_register mcf5329_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
243 static const enum m68k_register mcf5373_ctrl[] = {
244 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
247 static const enum m68k_register mcfv4e_ctrl[] = {
248 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
249 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
251 MPCR /* Multiprocessor Control register */,
252 EDRAMBAR /* Embedded DRAM Base Address Register */,
253 /* Permutation control registers. */
254 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
255 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
257 TC /* ASID */, BUSCR /* MMUBAR */,
258 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
259 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
260 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
263 static const enum m68k_register mcf5475_ctrl[] = {
264 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
265 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
267 TC /* ASID */, BUSCR /* MMUBAR */,
268 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
269 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
272 static const enum m68k_register mcf5485_ctrl[] = {
273 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
274 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
276 TC /* ASID */, BUSCR /* MMUBAR */,
277 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
278 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
281 static const enum m68k_register fido_ctrl[] = {
282 SFC, DFC, USP, VBR, CAC, MBB,
285 #define cpu32_ctrl m68010_ctrl
287 static const enum m68k_register *control_regs;
289 /* Internal form of a 68020 instruction. */
293 const char *args; /* List of opcode info. */
296 int numo; /* Number of shorts in opcode. */
299 struct m68k_op operands[6];
301 int nexp; /* Number of exprs in use. */
302 struct m68k_exp exprs[4];
304 int nfrag; /* Number of frags we have to produce. */
307 int fragoff; /* Where in the current opcode the frag ends. */
314 int nrel; /* Num of reloc strucs in use. */
321 /* In a pc relative address the difference between the address
322 of the offset and the address that the offset is relative
323 to. This depends on the addressing mode. Basically this
324 is the value to put in the offset field to address the
325 first byte of the offset, without regarding the special
326 significance of some values (in the branch instruction, for
330 /* Whether this expression needs special pic relocation, and if
332 enum pic_relocation pic_reloc;
335 reloc[5]; /* Five is enough??? */
338 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
339 #define float_of_arch(x) ((x) & mfloat)
340 #define mmu_of_arch(x) ((x) & mmmu)
341 #define arch_coldfire_p(x) ((x) & mcfisa_a)
342 #define arch_coldfire_fpu(x) ((x) & cfloat)
344 /* Macros for determining if cpu supports a specific addressing mode. */
345 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
347 static struct m68k_it the_ins; /* The instruction being assembled. */
349 #define op(ex) ((ex)->exp.X_op)
350 #define adds(ex) ((ex)->exp.X_add_symbol)
351 #define subs(ex) ((ex)->exp.X_op_symbol)
352 #define offs(ex) ((ex)->exp.X_add_number)
354 /* Macros for adding things to the m68k_it struct. */
355 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
357 /* Like addword, but goes BEFORE general operands. */
360 insop (int w, const struct m68k_incant *opcode)
363 for (z = the_ins.numo; z > opcode->m_codenum; --z)
364 the_ins.opcode[z] = the_ins.opcode[z - 1];
365 for (z = 0; z < the_ins.nrel; z++)
366 the_ins.reloc[z].n += 2;
367 for (z = 0; z < the_ins.nfrag; z++)
368 the_ins.fragb[z].fragoff++;
369 the_ins.opcode[opcode->m_codenum] = w;
373 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
376 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
378 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
379 ? the_ins.numo * 2 - 1
381 ? the_ins.numo * 2 + 1
382 : the_ins.numo * 2));
383 the_ins.reloc[the_ins.nrel].exp = exp->exp;
384 the_ins.reloc[the_ins.nrel].wid = width;
385 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
387 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
389 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
392 /* Cause an extra frag to be generated here, inserting up to 10 bytes
393 (that value is chosen in the frag_var call in md_assemble). TYPE
394 is the subtype of the frag to be generated; its primary type is
395 rs_machine_dependent.
397 The TYPE parameter is also used by md_convert_frag_1 and
398 md_estimate_size_before_relax. The appropriate type of fixup will
399 be emitted by md_convert_frag_1.
401 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
403 add_frag (symbolS *add, offsetT off, int type)
405 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
406 the_ins.fragb[the_ins.nfrag].fadd = add;
407 the_ins.fragb[the_ins.nfrag].foff = off;
408 the_ins.fragb[the_ins.nfrag++].fragty = type;
412 (op (ex) != O_constant && op (ex) != O_big)
414 static char *crack_operand (char *str, struct m68k_op *opP);
415 static int get_num (struct m68k_exp *exp, int ok);
416 static int reverse_16_bits (int in);
417 static int reverse_8_bits (int in);
418 static void install_gen_operand (int mode, int val);
419 static void install_operand (int mode, int val);
420 static void s_bss (int);
421 static void s_data1 (int);
422 static void s_data2 (int);
423 static void s_even (int);
424 static void s_proc (int);
425 static void s_chip (int);
426 static void s_fopt (int);
427 static void s_opt (int);
428 static void s_reg (int);
429 static void s_restore (int);
430 static void s_save (int);
431 static void s_mri_if (int);
432 static void s_mri_else (int);
433 static void s_mri_endi (int);
434 static void s_mri_break (int);
435 static void s_mri_next (int);
436 static void s_mri_for (int);
437 static void s_mri_endf (int);
438 static void s_mri_repeat (int);
439 static void s_mri_until (int);
440 static void s_mri_while (int);
441 static void s_mri_endw (int);
442 static void s_m68k_cpu (int);
443 static void s_m68k_arch (int);
447 unsigned long arch; /* Architecture features. */
448 const enum m68k_register *control_regs; /* Control regs on chip */
449 const char *name; /* Name */
450 int alias; /* Alias for a cannonical name. If 1, then
451 succeeds canonical name, if -1 then
452 succeeds canonical name, if <-1 ||>1 this is a
453 deprecated name, and the next/previous name
457 /* We hold flags for features explicitly enabled and explicitly
459 static int current_architecture;
460 static int not_current_architecture;
461 static const struct m68k_cpu *selected_arch;
462 static const struct m68k_cpu *selected_cpu;
463 static int initialized;
465 /* Architecture models. */
466 static const struct m68k_cpu m68k_archs[] =
468 {m68000, m68000_ctrl, "68000", 0},
469 {m68010, m68010_ctrl, "68010", 0},
470 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
471 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
472 {m68040, m68040_ctrl, "68040", 0},
473 {m68060, m68060_ctrl, "68060", 0},
474 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
475 {fido_a, fido_ctrl, "fidoa", 0},
476 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
477 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
478 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
479 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
480 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
484 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
486 static const struct m68k_cpu m68k_extensions[] =
488 {m68851, NULL, "68851", -1},
489 {m68881, NULL, "68881", -1},
490 {m68881, NULL, "68882", -1},
492 {cfloat|m68881, NULL, "float", 0},
494 {mcfhwdiv, NULL, "div", 1},
495 {mcfusp, NULL, "usp", 1},
496 {mcfmac, NULL, "mac", 1},
497 {mcfemac, NULL, "emac", 1},
503 static const struct m68k_cpu m68k_cpus[] =
505 {m68000, m68000_ctrl, "68000", 0},
506 {m68000, m68000_ctrl, "68ec000", 1},
507 {m68000, m68000_ctrl, "68hc000", 1},
508 {m68000, m68000_ctrl, "68hc001", 1},
509 {m68000, m68000_ctrl, "68008", 1},
510 {m68000, m68000_ctrl, "68302", 1},
511 {m68000, m68000_ctrl, "68306", 1},
512 {m68000, m68000_ctrl, "68307", 1},
513 {m68000, m68000_ctrl, "68322", 1},
514 {m68000, m68000_ctrl, "68356", 1},
515 {m68010, m68010_ctrl, "68010", 0},
516 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
517 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
518 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
519 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
520 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
521 {m68040, m68040_ctrl, "68040", 0},
522 {m68040, m68040_ctrl, "68ec040", 1},
523 {m68060, m68060_ctrl, "68060", 0},
524 {m68060, m68060_ctrl, "68ec060", 1},
526 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
527 {cpu32|m68881, cpu32_ctrl, "68330", 1},
528 {cpu32|m68881, cpu32_ctrl, "68331", 1},
529 {cpu32|m68881, cpu32_ctrl, "68332", 1},
530 {cpu32|m68881, cpu32_ctrl, "68333", 1},
531 {cpu32|m68881, cpu32_ctrl, "68334", 1},
532 {cpu32|m68881, cpu32_ctrl, "68336", 1},
533 {cpu32|m68881, cpu32_ctrl, "68340", 1},
534 {cpu32|m68881, cpu32_ctrl, "68341", 1},
535 {cpu32|m68881, cpu32_ctrl, "68349", 1},
536 {cpu32|m68881, cpu32_ctrl, "68360", 1},
538 {mcfisa_a, mcf_ctrl, "5200", 0},
539 {mcfisa_a, mcf_ctrl, "5202", 1},
540 {mcfisa_a, mcf_ctrl, "5204", 1},
541 {mcfisa_a, mcf5206_ctrl, "5206", 1},
543 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
545 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
546 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
548 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
549 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
551 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
552 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
553 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
555 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
556 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
557 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
559 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
560 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
561 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
562 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
564 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
565 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
567 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
568 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
569 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
570 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
571 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
573 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
574 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
579 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
581 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
589 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
591 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
600 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
602 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
603 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
604 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
605 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
606 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
607 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
608 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
610 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
611 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
612 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
613 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
614 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
615 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
616 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
618 {fido_a, fido_ctrl, "fidoa", 0},
619 {fido_a, fido_ctrl, "fido", 1},
624 static const struct m68k_cpu *m68k_lookup_cpu
625 (const char *, const struct m68k_cpu *, int, int *);
626 static int m68k_set_arch (const char *, int, int);
627 static int m68k_set_cpu (const char *, int, int);
628 static int m68k_set_extension (const char *, int, int);
629 static void m68k_init_arch (void);
631 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
632 architecture and we have a lot of relaxation modes. */
634 /* Macros used in the relaxation code. */
635 #define TAB(x,y) (((x) << 2) + (y))
636 #define TABTYPE(x) ((x) >> 2)
638 /* Relaxation states. */
644 /* Here are all the relaxation modes we support. First we can relax ordinary
645 branches. On 68020 and higher and on CPU32 all branch instructions take
646 three forms, so on these CPUs all branches always remain as such. When we
647 have to expand to the LONG form on a 68000, though, we substitute an
648 absolute jump instead. This is a direct replacement for unconditional
649 branches and a branch over a jump for conditional branches. However, if the
650 user requires PIC and disables this with --pcrel, we can only relax between
651 BYTE and SHORT forms, punting if that isn't enough. This gives us four
652 different relaxation modes for branches: */
654 #define BRANCHBWL 0 /* Branch byte, word, or long. */
655 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
656 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
657 #define BRANCHBW 3 /* Branch byte or word. */
659 /* We also relax coprocessor branches and DBcc's. All CPUs that support
660 coprocessor branches support them in word and long forms, so we have only
661 one relaxation mode for them. DBcc's are word only on all CPUs. We can
662 relax them to the LONG form with a branch-around sequence. This sequence
663 can use a long branch (if available) or an absolute jump (if acceptable).
664 This gives us two relaxation modes. If long branches are not available and
665 absolute jumps are not acceptable, we don't relax DBcc's. */
667 #define FBRANCH 4 /* Coprocessor branch. */
668 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
669 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
671 /* That's all for instruction relaxation. However, we also relax PC-relative
672 operands. Specifically, we have three operand relaxation modes. On the
673 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
674 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
675 two. Also PC+displacement+index operands in their simple form (with a non-
676 suppressed index without memory indirection) are supported on all CPUs, but
677 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
678 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
679 form of the PC+displacement+index operand. Finally, some absolute operands
680 can be relaxed down to 16-bit PC-relative. */
682 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
683 #define PCINDEX 8 /* PC + displacement + index. */
684 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
686 /* Note that calls to frag_var need to specify the maximum expansion
687 needed; this is currently 10 bytes for DBCC. */
690 How far Forward this mode will reach:
691 How far Backward this mode will reach:
692 How many bytes this mode will add to the size of the frag
693 Which mode to go to if the offset won't fit in this one
695 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
696 relax_typeS md_relax_table[] =
698 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
699 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
703 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
704 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
708 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
709 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
713 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
718 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
719 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
723 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
724 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
728 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
729 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
733 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
734 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
738 { 125, -130, 0, TAB (PCINDEX, SHORT) },
739 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
743 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
744 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
749 /* These are the machine dependent pseudo-ops. These are included so
750 the assembler can work on the output from the SUN C compiler, which
753 /* This table describes all the machine specific pseudo-ops the assembler
754 has to support. The fields are:
755 pseudo-op name without dot
756 function to call to execute this pseudo-op
757 Integer arg to pass to the function. */
758 const pseudo_typeS md_pseudo_table[] =
760 {"data1", s_data1, 0},
761 {"data2", s_data2, 0},
764 {"skip", s_space, 0},
766 #if defined (TE_SUN3) || defined (OBJ_ELF)
767 {"align", s_align_bytes, 0},
770 {"swbeg", s_ignore, 0},
772 {"extend", float_cons, 'x'},
773 {"ldouble", float_cons, 'x'},
775 {"arch", s_m68k_arch, 0},
776 {"cpu", s_m68k_cpu, 0},
778 /* The following pseudo-ops are supported for MRI compatibility. */
780 {"comline", s_space, 1},
782 {"mask2", s_ignore, 0},
785 {"restore", s_restore, 0},
789 {"if.b", s_mri_if, 'b'},
790 {"if.w", s_mri_if, 'w'},
791 {"if.l", s_mri_if, 'l'},
792 {"else", s_mri_else, 0},
793 {"else.s", s_mri_else, 's'},
794 {"else.l", s_mri_else, 'l'},
795 {"endi", s_mri_endi, 0},
796 {"break", s_mri_break, 0},
797 {"break.s", s_mri_break, 's'},
798 {"break.l", s_mri_break, 'l'},
799 {"next", s_mri_next, 0},
800 {"next.s", s_mri_next, 's'},
801 {"next.l", s_mri_next, 'l'},
802 {"for", s_mri_for, 0},
803 {"for.b", s_mri_for, 'b'},
804 {"for.w", s_mri_for, 'w'},
805 {"for.l", s_mri_for, 'l'},
806 {"endf", s_mri_endf, 0},
807 {"repeat", s_mri_repeat, 0},
808 {"until", s_mri_until, 0},
809 {"until.b", s_mri_until, 'b'},
810 {"until.w", s_mri_until, 'w'},
811 {"until.l", s_mri_until, 'l'},
812 {"while", s_mri_while, 0},
813 {"while.b", s_mri_while, 'b'},
814 {"while.w", s_mri_while, 'w'},
815 {"while.l", s_mri_while, 'l'},
816 {"endw", s_mri_endw, 0},
821 /* The mote pseudo ops are put into the opcode table, since they
822 don't start with a . they look like opcodes to gas. */
824 const pseudo_typeS mote_pseudo_table[] =
837 {"xdef", s_globl, 0},
839 {"align", s_align_bytes, 0},
841 {"align", s_align_ptwo, 0},
844 {"sect", obj_coff_section, 0},
845 {"section", obj_coff_section, 0},
850 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
851 gives identical results to a 32-bit host. */
852 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
853 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
855 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
856 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
857 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
858 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
860 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
861 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
862 #define islong(x) (1)
864 static char notend_table[256];
865 static char alt_notend_table[256];
867 (! (notend_table[(unsigned char) *s] \
869 && alt_notend_table[(unsigned char) s[1]])))
873 /* Return zero if the reference to SYMBOL from within the same segment may
876 /* On an ELF system, we can't relax an externally visible symbol,
877 because it may be overridden by a shared library. However, if
878 TARGET_OS is "elf", then we presume that we are assembling for an
879 embedded system, in which case we don't have to worry about shared
880 libraries, and we can relax any external sym. */
882 #define relaxable_symbol(symbol) \
883 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
884 || S_IS_WEAK (symbol)))
886 /* Compute the relocation code for a fixup of SIZE bytes, using pc
887 relative relocation if PCREL is non-zero. PIC says whether a special
888 pic relocation was requested. */
890 static bfd_reloc_code_real_type
891 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
899 return BFD_RELOC_8_GOT_PCREL;
901 return BFD_RELOC_16_GOT_PCREL;
903 return BFD_RELOC_32_GOT_PCREL;
911 return BFD_RELOC_8_GOTOFF;
913 return BFD_RELOC_16_GOTOFF;
915 return BFD_RELOC_32_GOTOFF;
923 return BFD_RELOC_8_PLT_PCREL;
925 return BFD_RELOC_16_PLT_PCREL;
927 return BFD_RELOC_32_PLT_PCREL;
935 return BFD_RELOC_8_PLTOFF;
937 return BFD_RELOC_16_PLTOFF;
939 return BFD_RELOC_32_PLTOFF;
949 return BFD_RELOC_8_PCREL;
951 return BFD_RELOC_16_PCREL;
953 return BFD_RELOC_32_PCREL;
973 as_bad (_("Can not do %d byte pc-relative relocation"), size);
975 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
980 as_bad (_("Can not do %d byte relocation"), size);
982 as_bad (_("Can not do %d byte pic relocation"), size);
985 return BFD_RELOC_NONE;
988 /* Here we decide which fixups can be adjusted to make them relative
989 to the beginning of the section instead of the symbol. Basically
990 we need to make sure that the dynamic relocations are done
991 correctly, so in some cases we force the original symbol to be
994 tc_m68k_fix_adjustable (fixS *fixP)
996 /* Adjust_reloc_syms doesn't know about the GOT. */
997 switch (fixP->fx_r_type)
999 case BFD_RELOC_8_GOT_PCREL:
1000 case BFD_RELOC_16_GOT_PCREL:
1001 case BFD_RELOC_32_GOT_PCREL:
1002 case BFD_RELOC_8_GOTOFF:
1003 case BFD_RELOC_16_GOTOFF:
1004 case BFD_RELOC_32_GOTOFF:
1005 case BFD_RELOC_8_PLT_PCREL:
1006 case BFD_RELOC_16_PLT_PCREL:
1007 case BFD_RELOC_32_PLT_PCREL:
1008 case BFD_RELOC_8_PLTOFF:
1009 case BFD_RELOC_16_PLTOFF:
1010 case BFD_RELOC_32_PLTOFF:
1013 case BFD_RELOC_VTABLE_INHERIT:
1014 case BFD_RELOC_VTABLE_ENTRY:
1022 #else /* !OBJ_ELF */
1024 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1026 #define relaxable_symbol(symbol) 1
1028 #endif /* OBJ_ELF */
1031 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1034 bfd_reloc_code_real_type code;
1036 /* If the tcbit is set, then this was a fixup of a negative value
1037 that was never resolved. We do not have a reloc to handle this,
1038 so just return. We assume that other code will have detected this
1039 situation and produced a helpful error message, so we just tell the
1040 user that the reloc cannot be produced. */
1044 as_bad_where (fixp->fx_file, fixp->fx_line,
1045 _("Unable to produce reloc against symbol '%s'"),
1046 S_GET_NAME (fixp->fx_addsy));
1050 if (fixp->fx_r_type != BFD_RELOC_NONE)
1052 code = fixp->fx_r_type;
1054 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1055 that fixup_segment converted a non-PC relative reloc into a
1056 PC relative reloc. In such a case, we need to convert the
1063 code = BFD_RELOC_8_PCREL;
1066 code = BFD_RELOC_16_PCREL;
1069 code = BFD_RELOC_32_PCREL;
1071 case BFD_RELOC_8_PCREL:
1072 case BFD_RELOC_16_PCREL:
1073 case BFD_RELOC_32_PCREL:
1074 case BFD_RELOC_8_GOT_PCREL:
1075 case BFD_RELOC_16_GOT_PCREL:
1076 case BFD_RELOC_32_GOT_PCREL:
1077 case BFD_RELOC_8_GOTOFF:
1078 case BFD_RELOC_16_GOTOFF:
1079 case BFD_RELOC_32_GOTOFF:
1080 case BFD_RELOC_8_PLT_PCREL:
1081 case BFD_RELOC_16_PLT_PCREL:
1082 case BFD_RELOC_32_PLT_PCREL:
1083 case BFD_RELOC_8_PLTOFF:
1084 case BFD_RELOC_16_PLTOFF:
1085 case BFD_RELOC_32_PLTOFF:
1088 as_bad_where (fixp->fx_file, fixp->fx_line,
1089 _("Cannot make %s relocation PC relative"),
1090 bfd_get_reloc_code_name (code));
1096 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1097 switch (F (fixp->fx_size, fixp->fx_pcrel))
1099 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1100 MAP (1, 0, BFD_RELOC_8);
1101 MAP (2, 0, BFD_RELOC_16);
1102 MAP (4, 0, BFD_RELOC_32);
1103 MAP (1, 1, BFD_RELOC_8_PCREL);
1104 MAP (2, 1, BFD_RELOC_16_PCREL);
1105 MAP (4, 1, BFD_RELOC_32_PCREL);
1113 reloc = (arelent *) xmalloc (sizeof (arelent));
1114 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1115 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1116 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1119 reloc->addend = fixp->fx_addnumber;
1123 if (!fixp->fx_pcrel)
1124 reloc->addend = fixp->fx_addnumber;
1126 reloc->addend = (section->vma
1127 /* Explicit sign extension in case char is
1129 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1130 + fixp->fx_addnumber
1131 + md_pcrel_from (fixp));
1134 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1135 assert (reloc->howto != 0);
1140 /* Handle of the OPCODE hash table. NULL means any use before
1141 m68k_ip_begin() will crash. */
1142 static struct hash_control *op_hash;
1144 /* Assemble an m68k instruction. */
1147 m68k_ip (char *instring)
1150 register struct m68k_op *opP;
1151 register const struct m68k_incant *opcode;
1152 register const char *s;
1153 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1154 char *pdot, *pdotmove;
1155 enum m68k_size siz1, siz2;
1159 struct m68k_op operands_backup[6];
1160 LITTLENUM_TYPE words[6];
1161 LITTLENUM_TYPE *wordp;
1162 unsigned long ok_arch = 0;
1164 if (*instring == ' ')
1165 instring++; /* Skip leading whitespace. */
1167 /* Scan up to end of operation-code, which MUST end in end-of-string
1168 or exactly 1 space. */
1170 for (p = instring; *p != '\0'; p++)
1180 the_ins.error = _("No operator");
1184 /* p now points to the end of the opcode name, probably whitespace.
1185 Make sure the name is null terminated by clobbering the
1186 whitespace, look it up in the hash table, then fix it back.
1187 Remove a dot, first, since the opcode tables have none. */
1190 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1191 *pdotmove = pdotmove[1];
1197 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1202 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1203 *pdotmove = pdotmove[-1];
1210 the_ins.error = _("Unknown operator");
1214 /* Found a legitimate opcode, start matching operands. */
1218 if (opcode->m_operands == 0)
1220 char *old = input_line_pointer;
1222 input_line_pointer = p;
1223 /* Ahh - it's a motorola style psuedo op. */
1224 mote_pseudo_table[opcode->m_opnum].poc_handler
1225 (mote_pseudo_table[opcode->m_opnum].poc_val);
1226 input_line_pointer = old;
1232 if (flag_mri && opcode->m_opnum == 0)
1234 /* In MRI mode, random garbage is allowed after an instruction
1235 which accepts no operands. */
1236 the_ins.args = opcode->m_operands;
1237 the_ins.numargs = opcode->m_opnum;
1238 the_ins.numo = opcode->m_codenum;
1239 the_ins.opcode[0] = getone (opcode);
1240 the_ins.opcode[1] = gettwo (opcode);
1244 for (opP = &the_ins.operands[0]; *p; opP++)
1246 p = crack_operand (p, opP);
1250 the_ins.error = opP->error;
1255 opsfound = opP - &the_ins.operands[0];
1257 /* This ugly hack is to support the floating pt opcodes in their
1258 standard form. Essentially, we fake a first enty of type COP#1 */
1259 if (opcode->m_operands[0] == 'I')
1263 for (n = opsfound; n > 0; --n)
1264 the_ins.operands[n] = the_ins.operands[n - 1];
1266 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1267 the_ins.operands[0].mode = CONTROL;
1268 the_ins.operands[0].reg = m68k_float_copnum;
1272 /* We've got the operands. Find an opcode that'll accept them. */
1275 /* If we didn't get the right number of ops, or we have no
1276 common model with this pattern then reject this pattern. */
1278 ok_arch |= opcode->m_arch;
1279 if (opsfound != opcode->m_opnum
1280 || ((opcode->m_arch & current_architecture) == 0))
1286 /* Make a copy of the operands of this insn so that
1287 we can modify them safely, should we want to. */
1288 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1289 for (i = 0; i < opsfound; i++)
1290 operands_backup[i] = the_ins.operands[i];
1292 for (s = opcode->m_operands, opP = &operands_backup[0];
1296 /* Warning: this switch is huge! */
1297 /* I've tried to organize the cases into this order:
1298 non-alpha first, then alpha by letter. Lower-case
1299 goes directly before uppercase counterpart. */
1300 /* Code with multiple case ...: gets sorted by the lowest
1301 case ... it belongs to. I hope this makes sense. */
1407 if (opP->reg == PC || opP->reg == ZPC)
1424 if (opP->reg == PC || opP->reg == ZPC)
1443 if (opP->reg == PC || opP->reg == ZPC)
1453 if (opP->mode != IMMED)
1455 else if (s[1] == 'b'
1456 && ! isvar (&opP->disp)
1457 && (opP->disp.exp.X_op != O_constant
1458 || ! isbyte (opP->disp.exp.X_add_number)))
1460 else if (s[1] == 'B'
1461 && ! isvar (&opP->disp)
1462 && (opP->disp.exp.X_op != O_constant
1463 || ! issbyte (opP->disp.exp.X_add_number)))
1465 else if (s[1] == 'w'
1466 && ! isvar (&opP->disp)
1467 && (opP->disp.exp.X_op != O_constant
1468 || ! isword (opP->disp.exp.X_add_number)))
1470 else if (s[1] == 'W'
1471 && ! isvar (&opP->disp)
1472 && (opP->disp.exp.X_op != O_constant
1473 || ! issword (opP->disp.exp.X_add_number)))
1479 if (opP->mode != IMMED)
1484 if (opP->mode == AREG
1485 || opP->mode == CONTROL
1486 || opP->mode == FPREG
1487 || opP->mode == IMMED
1488 || opP->mode == REGLST
1489 || (opP->mode != ABSL
1491 || opP->reg == ZPC)))
1496 if (opP->mode == CONTROL
1497 || opP->mode == FPREG
1498 || opP->mode == REGLST
1499 || opP->mode == IMMED
1500 || (opP->mode != ABSL
1502 || opP->reg == ZPC)))
1530 if (opP->mode == CONTROL
1531 || opP->mode == FPREG
1532 || opP->mode == REGLST)
1537 if (opP->mode != AINC)
1542 if (opP->mode != ADEC)
1592 if (opP->reg == PC || opP->reg == ZPC)
1613 case '~': /* For now! (JF FOO is this right?) */
1635 if (opP->mode != CONTROL
1636 || (opP->reg != TT0 && opP->reg != TT1))
1641 if (opP->mode != AREG)
1646 if (opP->mode != AINDR)
1651 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1652 && (opP->mode != DISP
1654 || opP->reg > ADDR7))
1659 if (opP->mode != ABSL
1661 && strncmp (instring, "jbsr", 4) == 0))
1684 if (opP->mode != CONTROL || opP->reg != CCR)
1689 if (opP->mode != DISP
1691 || opP->reg > ADDR7)
1696 if (opP->mode != DREG)
1701 if (opP->reg != ACC)
1706 if (opP->reg != ACC && opP->reg != ACC1
1707 && opP->reg != ACC2 && opP->reg != ACC3)
1712 if (opP->mode != FPREG)
1717 if (opP->reg != MACSR)
1722 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1727 if (opP->reg != MASK)
1732 if (opP->mode != CONTROL
1739 if (opP->mode != LSH && opP->mode != RSH)
1744 if (opP->mode != CONTROL
1746 || opP->reg > last_movec_reg
1751 const enum m68k_register *rp;
1753 for (rp = control_regs; *rp; rp++)
1755 if (*rp == opP->reg)
1757 /* In most CPUs RAMBAR refers to control reg
1758 c05 (RAMBAR1), but a few CPUs have it
1759 refer to c04 (RAMBAR0). */
1760 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1762 opP->reg = RAMBAR_ALT;
1772 if (opP->mode != IMMED)
1778 if (opP->mode == DREG
1779 || opP->mode == AREG
1780 || opP->mode == FPREG)
1789 opP->mask = 1 << (opP->reg - DATA0);
1792 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1795 opP->mask = 1 << (opP->reg - FP0 + 16);
1803 else if (opP->mode == CONTROL)
1812 opP->mask = 1 << 24;
1815 opP->mask = 1 << 25;
1818 opP->mask = 1 << 26;
1827 else if (opP->mode != REGLST)
1829 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1831 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1836 if (opP->mode != IMMED)
1838 else if (opP->disp.exp.X_op != O_constant
1839 || ! issbyte (opP->disp.exp.X_add_number))
1841 else if (! m68k_quick
1842 && instring[3] != 'q'
1843 && instring[4] != 'q')
1848 if (opP->mode != DREG
1849 && opP->mode != IMMED
1850 && opP->mode != ABSL)
1855 if (opP->mode != IMMED)
1857 else if (opP->disp.exp.X_op != O_constant
1858 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1860 else if (! m68k_quick
1861 && (strncmp (instring, "add", 3) == 0
1862 || strncmp (instring, "sub", 3) == 0)
1863 && instring[3] != 'q')
1868 if (opP->mode != DREG && opP->mode != AREG)
1873 if (opP->mode != AINDR
1874 && (opP->mode != BASE
1876 && opP->reg != ZADDR0)
1877 || opP->disp.exp.X_op != O_absent
1878 || ((opP->index.reg < DATA0
1879 || opP->index.reg > DATA7)
1880 && (opP->index.reg < ADDR0
1881 || opP->index.reg > ADDR7))
1882 || opP->index.size != SIZE_UNSPEC
1883 || opP->index.scale != 1))
1888 if (opP->mode != CONTROL
1889 || ! (opP->reg == FPI
1891 || opP->reg == FPC))
1896 if (opP->mode != CONTROL || opP->reg != SR)
1901 if (opP->mode != IMMED)
1903 else if (opP->disp.exp.X_op != O_constant
1904 || TRUNC (opP->disp.exp.X_add_number) > 7)
1909 if (opP->mode != CONTROL || opP->reg != USP)
1914 if (opP->mode != IMMED)
1916 else if (opP->disp.exp.X_op != O_constant
1917 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1918 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1922 /* JF these are out of order. We could put them
1923 in order if we were willing to put up with
1924 bunches of #ifdef m68851s in the code.
1926 Don't forget that you need these operands
1927 to use 68030 MMU instructions. */
1929 /* Memory addressing mode used by pflushr. */
1931 if (opP->mode == CONTROL
1932 || opP->mode == FPREG
1933 || opP->mode == DREG
1934 || opP->mode == AREG
1935 || opP->mode == REGLST)
1937 /* We should accept immediate operands, but they
1938 supposedly have to be quad word, and we don't
1939 handle that. I would like to see what a Motorola
1940 assembler does before doing something here. */
1941 if (opP->mode == IMMED)
1946 if (opP->mode != CONTROL
1947 || (opP->reg != SFC && opP->reg != DFC))
1952 if (opP->mode != CONTROL || opP->reg != TC)
1957 if (opP->mode != CONTROL || opP->reg != AC)
1962 if (opP->mode != CONTROL
1965 && opP->reg != SCC))
1970 if (opP->mode != CONTROL
1976 if (opP->mode != CONTROL
1979 && opP->reg != CRP))
2003 if (opP->mode != CONTROL
2004 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2005 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2010 if (opP->mode != CONTROL || opP->reg != PSR)
2015 if (opP->mode != CONTROL || opP->reg != PCSR)
2020 if (opP->mode != CONTROL
2029 if (opP->mode != ABSL)
2034 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2036 /* FIXME: kludge instead of fixing parser:
2037 upper/lower registers are *not* CONTROL
2038 registers, but ordinary ones. */
2039 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2040 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2047 if (!(opP->mode == AINDR
2048 || (opP->mode == DISP
2049 && !(opP->reg == PC || opP->reg == ZPC))))
2054 if (!(opP->mode == AINDR || opP->mode == DISP))
2066 /* Since we have found the correct instruction, copy
2067 in the modifications that we may have made. */
2069 for (i = 0; i < opsfound; i++)
2070 the_ins.operands[i] = operands_backup[i];
2076 opcode = opcode->m_next;
2081 && !(ok_arch & current_architecture))
2083 const struct m68k_cpu *cpu;
2086 char *buf = xmalloc (space + 1);
2090 the_ins.error = buf;
2091 /* Make sure there's a NUL at the end of the buffer -- strncpy
2092 won't write one when it runs out of buffer */
2094 #define APPEND(STRING) \
2095 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2097 APPEND (_("invalid instruction for this architecture; needs "));
2101 APPEND (_("ColdFire ISA_A"));
2104 APPEND (_("ColdFire hardware divide"));
2107 APPEND (_("ColdFire ISA_A+"));
2110 APPEND (_("ColdFire ISA_B"));
2113 APPEND (_("ColdFire fpu"));
2116 APPEND (_("M68K fpu"));
2119 APPEND (_("M68K mmu"));
2122 APPEND (_("68020 or higher"));
2125 APPEND (_("68000 or higher"));
2128 APPEND (_("68010 or higher"));
2136 for (cpu = m68k_cpus; cpu->name; cpu++)
2137 if (!cpu->alias && (cpu->arch & ok_arch))
2139 const struct m68k_cpu *alias;
2140 int seen_master = 0;
2146 for (alias = cpu; alias != m68k_cpus; alias--)
2147 if (alias[-1].alias >= 0)
2149 for (; !seen_master || alias->alias > 0; alias++)
2159 APPEND (alias->name);
2172 /* we ran out of space, so replace the end of the list
2177 strcpy (buf, " ...");
2181 the_ins.error = _("operands mismatch");
2188 /* Now assemble it. */
2189 the_ins.args = opcode->m_operands;
2190 the_ins.numargs = opcode->m_opnum;
2191 the_ins.numo = opcode->m_codenum;
2192 the_ins.opcode[0] = getone (opcode);
2193 the_ins.opcode[1] = gettwo (opcode);
2195 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2197 /* This switch is a doozy.
2198 Watch the first step; its a big one! */
2231 tmpreg = 0x3c; /* 7.4 */
2232 if (strchr ("bwl", s[1]))
2233 nextword = get_num (&opP->disp, 90);
2235 nextword = get_num (&opP->disp, 0);
2236 if (isvar (&opP->disp))
2237 add_fix (s[1], &opP->disp, 0, 0);
2241 if (!isbyte (nextword))
2242 opP->error = _("operand out of range");
2247 if (!isword (nextword))
2248 opP->error = _("operand out of range");
2253 if (!issword (nextword))
2254 opP->error = _("operand out of range");
2259 addword (nextword >> 16);
2286 /* We gotta put out some float. */
2287 if (op (&opP->disp) != O_big)
2292 /* Can other cases happen here? */
2293 if (op (&opP->disp) != O_constant)
2296 val = (valueT) offs (&opP->disp);
2300 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2301 val >>= LITTLENUM_NUMBER_OF_BITS;
2305 offs (&opP->disp) = gencnt;
2307 if (offs (&opP->disp) > 0)
2309 if (offs (&opP->disp) > baseo)
2311 as_warn (_("Bignum too big for %c format; truncated"),
2313 offs (&opP->disp) = baseo;
2315 baseo -= offs (&opP->disp);
2318 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2319 offs (&opP->disp)--;
2324 gen_to_words (words, baseo, (long) outro);
2325 for (wordp = words; baseo--; wordp++)
2329 tmpreg = opP->reg - DATA; /* 0.dreg */
2332 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2335 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2338 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2341 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2345 nextword = get_num (&opP->disp, 90);
2347 /* Convert mode 5 addressing with a zero offset into
2348 mode 2 addressing to reduce the instruction size by a
2350 if (! isvar (&opP->disp)
2352 && (opP->disp.size == SIZE_UNSPEC)
2353 && (opP->reg >= ADDR0)
2354 && (opP->reg <= ADDR7))
2356 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2361 && ! isvar (&opP->disp)
2364 opP->disp.exp.X_op = O_symbol;
2365 opP->disp.exp.X_add_symbol =
2366 section_symbol (absolute_section);
2369 /* Force into index mode. Hope this works. */
2371 /* We do the first bit for 32-bit displacements, and the
2372 second bit for 16 bit ones. It is possible that we
2373 should make the default be WORD instead of LONG, but
2374 I think that'd break GCC, so we put up with a little
2375 inefficiency for the sake of working output. */
2377 if (!issword (nextword)
2378 || (isvar (&opP->disp)
2379 && ((opP->disp.size == SIZE_UNSPEC
2380 && flag_short_refs == 0
2381 && cpu_of_arch (current_architecture) >= m68020
2382 && ! arch_coldfire_p (current_architecture))
2383 || opP->disp.size == SIZE_LONG)))
2385 if (cpu_of_arch (current_architecture) < m68020
2386 || arch_coldfire_p (current_architecture))
2388 _("displacement too large for this architecture; needs 68020 or higher");
2390 tmpreg = 0x3B; /* 7.3 */
2392 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2393 if (isvar (&opP->disp))
2397 if (opP->disp.size == SIZE_LONG
2399 /* If the displacement needs pic
2400 relocation it cannot be relaxed. */
2401 || opP->disp.pic_reloc != pic_none
2406 add_fix ('l', &opP->disp, 1, 2);
2410 add_frag (adds (&opP->disp),
2411 SEXT (offs (&opP->disp)),
2412 TAB (PCREL1632, SZ_UNDEF));
2419 add_fix ('l', &opP->disp, 0, 0);
2424 addword (nextword >> 16);
2429 tmpreg = 0x3A; /* 7.2 */
2431 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2433 if (isvar (&opP->disp))
2437 add_fix ('w', &opP->disp, 1, 0);
2440 add_fix ('w', &opP->disp, 0, 0);
2450 baseo = get_num (&opP->disp, 90);
2451 if (opP->mode == POST || opP->mode == PRE)
2452 outro = get_num (&opP->odisp, 90);
2453 /* Figure out the `addressing mode'.
2454 Also turn on the BASE_DISABLE bit, if needed. */
2455 if (opP->reg == PC || opP->reg == ZPC)
2457 tmpreg = 0x3b; /* 7.3 */
2458 if (opP->reg == ZPC)
2461 else if (opP->reg == 0)
2464 tmpreg = 0x30; /* 6.garbage */
2466 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2469 tmpreg = 0x30 + opP->reg - ZADDR0;
2472 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2474 siz1 = opP->disp.size;
2475 if (opP->mode == POST || opP->mode == PRE)
2476 siz2 = opP->odisp.size;
2480 /* Index register stuff. */
2481 if (opP->index.reg != 0
2482 && opP->index.reg >= DATA
2483 && opP->index.reg <= ADDR7)
2485 nextword |= (opP->index.reg - DATA) << 12;
2487 if (opP->index.size == SIZE_LONG
2488 || (opP->index.size == SIZE_UNSPEC
2489 && m68k_index_width_default == SIZE_LONG))
2492 if ((opP->index.scale != 1
2493 && cpu_of_arch (current_architecture) < m68020)
2494 || (opP->index.scale == 8
2495 && (arch_coldfire_p (current_architecture)
2496 && !arch_coldfire_fpu (current_architecture))))
2499 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2502 if (arch_coldfire_p (current_architecture)
2503 && opP->index.size == SIZE_WORD)
2504 opP->error = _("invalid index size for coldfire");
2506 switch (opP->index.scale)
2523 GET US OUT OF HERE! */
2525 /* Must be INDEX, with an index register. Address
2526 register cannot be ZERO-PC, and either :b was
2527 forced, or we know it will fit. For a 68000 or
2528 68010, force this mode anyways, because the
2529 larger modes aren't supported. */
2530 if (opP->mode == BASE
2531 && ((opP->reg >= ADDR0
2532 && opP->reg <= ADDR7)
2535 if (siz1 == SIZE_BYTE
2536 || cpu_of_arch (current_architecture) < m68020
2537 || arch_coldfire_p (current_architecture)
2538 || (siz1 == SIZE_UNSPEC
2539 && ! isvar (&opP->disp)
2540 && issbyte (baseo)))
2542 nextword += baseo & 0xff;
2544 if (isvar (&opP->disp))
2546 /* Do a byte relocation. If it doesn't
2547 fit (possible on m68000) let the
2548 fixup processing complain later. */
2550 add_fix ('B', &opP->disp, 1, 1);
2552 add_fix ('B', &opP->disp, 0, 0);
2554 else if (siz1 != SIZE_BYTE)
2556 if (siz1 != SIZE_UNSPEC)
2557 as_warn (_("Forcing byte displacement"));
2558 if (! issbyte (baseo))
2559 opP->error = _("byte displacement out of range");
2564 else if (siz1 == SIZE_UNSPEC
2566 && isvar (&opP->disp)
2567 && subs (&opP->disp) == NULL
2569 /* If the displacement needs pic
2570 relocation it cannot be relaxed. */
2571 && opP->disp.pic_reloc == pic_none
2575 /* The code in md_convert_frag_1 needs to be
2576 able to adjust nextword. Call frag_grow
2577 to ensure that we have enough space in
2578 the frag obstack to make all the bytes
2581 nextword += baseo & 0xff;
2583 add_frag (adds (&opP->disp),
2584 SEXT (offs (&opP->disp)),
2585 TAB (PCINDEX, SZ_UNDEF));
2593 nextword |= 0x40; /* No index reg. */
2594 if (opP->index.reg >= ZDATA0
2595 && opP->index.reg <= ZDATA7)
2596 nextword |= (opP->index.reg - ZDATA0) << 12;
2597 else if (opP->index.reg >= ZADDR0
2598 || opP->index.reg <= ZADDR7)
2599 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2602 /* It isn't simple. */
2604 if (cpu_of_arch (current_architecture) < m68020
2605 || arch_coldfire_p (current_architecture))
2607 _("invalid operand mode for this architecture; needs 68020 or higher");
2610 /* If the guy specified a width, we assume that it is
2611 wide enough. Maybe it isn't. If so, we lose. */
2615 if (isvar (&opP->disp)
2617 : ! issword (baseo))
2622 else if (! isvar (&opP->disp) && baseo == 0)
2631 as_warn (_(":b not permitted; defaulting to :w"));
2641 /* Figure out inner displacement stuff. */
2642 if (opP->mode == POST || opP->mode == PRE)
2644 if (cpu_of_arch (current_architecture) & cpu32)
2645 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2649 if (isvar (&opP->odisp)
2651 : ! issword (outro))
2656 else if (! isvar (&opP->odisp) && outro == 0)
2665 as_warn (_(":b not permitted; defaulting to :w"));
2674 if (opP->mode == POST
2675 && (nextword & 0x40) == 0)
2680 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2682 if (opP->reg == PC || opP->reg == ZPC)
2683 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2685 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2687 if (siz1 == SIZE_LONG)
2688 addword (baseo >> 16);
2689 if (siz1 != SIZE_UNSPEC)
2692 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2693 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2694 if (siz2 == SIZE_LONG)
2695 addword (outro >> 16);
2696 if (siz2 != SIZE_UNSPEC)
2702 nextword = get_num (&opP->disp, 90);
2703 switch (opP->disp.size)
2708 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2710 tmpreg = 0x38; /* 7.0 */
2714 if (isvar (&opP->disp)
2715 && !subs (&opP->disp)
2716 && adds (&opP->disp)
2718 /* If the displacement needs pic relocation it
2719 cannot be relaxed. */
2720 && opP->disp.pic_reloc == pic_none
2723 && !strchr ("~%&$?", s[0]))
2725 tmpreg = 0x3A; /* 7.2 */
2726 add_frag (adds (&opP->disp),
2727 SEXT (offs (&opP->disp)),
2728 TAB (ABSTOPCREL, SZ_UNDEF));
2731 /* Fall through into long. */
2733 if (isvar (&opP->disp))
2734 add_fix ('l', &opP->disp, 0, 0);
2736 tmpreg = 0x39;/* 7.1 mode */
2737 addword (nextword >> 16);
2742 as_bad (_("unsupported byte value; use a different suffix"));
2746 if (isvar (&opP->disp))
2747 add_fix ('w', &opP->disp, 0, 0);
2749 tmpreg = 0x38;/* 7.0 mode */
2757 as_bad (_("unknown/incorrect operand"));
2761 /* If s[0] is '4', then this is for the mac instructions
2762 that can have a trailing_ampersand set. If so, set 0x100
2763 bit on tmpreg so install_gen_operand can check for it and
2764 set the appropriate bit (word2, bit 5). */
2767 if (opP->trailing_ampersand)
2770 install_gen_operand (s[1], tmpreg);
2776 { /* JF: I hate floating point! */
2791 tmpreg = get_num (&opP->disp, tmpreg);
2792 if (isvar (&opP->disp))
2793 add_fix (s[1], &opP->disp, 0, 0);
2796 case 'b': /* Danger: These do no check for
2797 certain types of overflow.
2799 if (!isbyte (tmpreg))
2800 opP->error = _("out of range");
2801 insop (tmpreg, opcode);
2802 if (isvar (&opP->disp))
2803 the_ins.reloc[the_ins.nrel - 1].n =
2804 (opcode->m_codenum) * 2 + 1;
2807 if (!issbyte (tmpreg))
2808 opP->error = _("out of range");
2809 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2810 if (isvar (&opP->disp))
2811 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2814 if (!isword (tmpreg))
2815 opP->error = _("out of range");
2816 insop (tmpreg, opcode);
2817 if (isvar (&opP->disp))
2818 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2821 if (!issword (tmpreg))
2822 opP->error = _("out of range");
2823 insop (tmpreg, opcode);
2824 if (isvar (&opP->disp))
2825 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2828 /* Because of the way insop works, we put these two out
2830 insop (tmpreg, opcode);
2831 insop (tmpreg >> 16, opcode);
2832 if (isvar (&opP->disp))
2833 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2840 install_operand (s[1], tmpreg);
2851 install_operand (s[1], opP->reg - ADDR);
2855 tmpreg = get_num (&opP->disp, 90);
2859 add_fix ('B', &opP->disp, 1, -1);
2862 add_fix ('w', &opP->disp, 1, 0);
2867 if (! HAVE_LONG_BRANCH (current_architecture))
2868 as_warn (_("Can't use long branches on 68000/68010/5200"));
2869 the_ins.opcode[0] |= 0xff;
2870 add_fix ('l', &opP->disp, 1, 0);
2875 if (subs (&opP->disp)) /* We can't relax it. */
2879 /* If the displacement needs pic relocation it cannot be
2881 if (opP->disp.pic_reloc != pic_none)
2884 /* This could either be a symbol, or an absolute
2885 address. If it's an absolute address, turn it into
2886 an absolute jump right here and keep it out of the
2888 if (adds (&opP->disp) == 0)
2890 if (the_ins.opcode[0] == 0x6000) /* jbra */
2891 the_ins.opcode[0] = 0x4EF9;
2892 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2893 the_ins.opcode[0] = 0x4EB9;
2896 the_ins.opcode[0] ^= 0x0100;
2897 the_ins.opcode[0] |= 0x0006;
2900 add_fix ('l', &opP->disp, 0, 0);
2906 /* Now we know it's going into the relaxer. Now figure
2907 out which mode. We try in this order of preference:
2908 long branch, absolute jump, byte/word branches only. */
2909 if (HAVE_LONG_BRANCH (current_architecture))
2910 add_frag (adds (&opP->disp),
2911 SEXT (offs (&opP->disp)),
2912 TAB (BRANCHBWL, SZ_UNDEF));
2913 else if (! flag_keep_pcrel)
2915 if ((the_ins.opcode[0] == 0x6000)
2916 || (the_ins.opcode[0] == 0x6100))
2917 add_frag (adds (&opP->disp),
2918 SEXT (offs (&opP->disp)),
2919 TAB (BRABSJUNC, SZ_UNDEF));
2921 add_frag (adds (&opP->disp),
2922 SEXT (offs (&opP->disp)),
2923 TAB (BRABSJCOND, SZ_UNDEF));
2926 add_frag (adds (&opP->disp),
2927 SEXT (offs (&opP->disp)),
2928 TAB (BRANCHBW, SZ_UNDEF));
2931 if (isvar (&opP->disp))
2933 /* Check for DBcc instructions. We can relax them,
2934 but only if we have long branches and/or absolute
2936 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2937 && (HAVE_LONG_BRANCH (current_architecture)
2938 || (! flag_keep_pcrel)))
2940 if (HAVE_LONG_BRANCH (current_architecture))
2941 add_frag (adds (&opP->disp),
2942 SEXT (offs (&opP->disp)),
2943 TAB (DBCCLBR, SZ_UNDEF));
2945 add_frag (adds (&opP->disp),
2946 SEXT (offs (&opP->disp)),
2947 TAB (DBCCABSJ, SZ_UNDEF));
2950 add_fix ('w', &opP->disp, 1, 0);
2954 case 'C': /* Fixed size LONG coproc branches. */
2955 add_fix ('l', &opP->disp, 1, 0);
2959 case 'c': /* Var size Coprocesssor branches. */
2960 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2962 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2963 add_fix ('l', &opP->disp, 1, 0);
2968 add_frag (adds (&opP->disp),
2969 SEXT (offs (&opP->disp)),
2970 TAB (FBRANCH, SZ_UNDEF));
2977 case 'C': /* Ignore it. */
2980 case 'd': /* JF this is a kludge. */
2981 install_operand ('s', opP->reg - ADDR);
2982 tmpreg = get_num (&opP->disp, 90);
2983 if (!issword (tmpreg))
2985 as_warn (_("Expression out of range, using 0"));
2992 install_operand (s[1], opP->reg - DATA);
2995 case 'e': /* EMAC ACCx, reg/reg. */
2996 install_operand (s[1], opP->reg - ACC);
2999 case 'E': /* Ignore it. */
3003 install_operand (s[1], opP->reg - FP0);
3006 case 'g': /* EMAC ACCEXTx. */
3007 install_operand (s[1], opP->reg - ACCEXT01);
3010 case 'G': /* Ignore it. */
3015 tmpreg = opP->reg - COP0;
3016 install_operand (s[1], tmpreg);
3019 case 'i': /* MAC/EMAC scale factor. */
3020 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3023 case 'J': /* JF foo. */
3163 install_operand (s[1], tmpreg);
3167 tmpreg = get_num (&opP->disp, 55);
3168 install_operand (s[1], tmpreg & 0x7f);
3175 if (tmpreg & 0x7FF0000)
3176 as_bad (_("Floating point register in register list"));
3177 insop (reverse_16_bits (tmpreg), opcode);
3181 if (tmpreg & 0x700FFFF)
3182 as_bad (_("Wrong register in floating-point reglist"));
3183 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3191 if (tmpreg & 0x7FF0000)
3192 as_bad (_("Floating point register in register list"));
3193 insop (tmpreg, opcode);
3195 else if (s[1] == '8')
3197 if (tmpreg & 0x0FFFFFF)
3198 as_bad (_("incorrect register in reglist"));
3199 install_operand (s[1], tmpreg >> 24);
3203 if (tmpreg & 0x700FFFF)
3204 as_bad (_("wrong register in floating-point reglist"));
3206 install_operand (s[1], tmpreg >> 16);
3211 install_operand (s[1], get_num (&opP->disp, 60));
3215 tmpreg = ((opP->mode == DREG)
3216 ? 0x20 + (int) (opP->reg - DATA)
3217 : (get_num (&opP->disp, 40) & 0x1F));
3218 install_operand (s[1], tmpreg);
3222 tmpreg = get_num (&opP->disp, 10);
3225 install_operand (s[1], tmpreg);
3229 /* This depends on the fact that ADDR registers are eight
3230 more than their corresponding DATA regs, so the result
3231 will have the ADDR_REG bit set. */
3232 install_operand (s[1], opP->reg - DATA);
3236 if (opP->mode == AINDR)
3237 install_operand (s[1], opP->reg - DATA);
3239 install_operand (s[1], opP->index.reg - DATA);
3243 if (opP->reg == FPI)
3245 else if (opP->reg == FPS)
3247 else if (opP->reg == FPC)
3251 install_operand (s[1], tmpreg);
3254 case 'S': /* Ignore it. */
3258 install_operand (s[1], get_num (&opP->disp, 30));
3261 case 'U': /* Ignore it. */
3280 as_fatal (_("failed sanity check"));
3281 } /* switch on cache token. */
3282 install_operand (s[1], tmpreg);
3285 /* JF: These are out of order, I fear. */
3298 install_operand (s[1], tmpreg);
3324 install_operand (s[1], tmpreg);
3328 if (opP->reg == VAL)
3347 install_operand (s[1], tmpreg);
3361 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3372 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3378 install_operand (s[1], tmpreg);
3381 know (opP->reg == PSR);
3384 know (opP->reg == PCSR);
3399 install_operand (s[1], tmpreg);
3402 tmpreg = get_num (&opP->disp, 20);
3403 install_operand (s[1], tmpreg);
3405 case '_': /* used only for move16 absolute 32-bit address. */
3406 if (isvar (&opP->disp))
3407 add_fix ('l', &opP->disp, 0, 0);
3408 tmpreg = get_num (&opP->disp, 90);
3409 addword (tmpreg >> 16);
3410 addword (tmpreg & 0xFFFF);
3413 install_operand (s[1], opP->reg - DATA0L);
3414 opP->reg -= (DATA0L);
3415 opP->reg &= 0x0F; /* remove upper/lower bit. */
3418 tmpreg = get_num (&opP->disp, 80);
3421 install_operand (s[1], tmpreg);
3428 /* By the time whe get here (FINALLY) the_ins contains the complete
3429 instruction, ready to be emitted. . . */
3433 reverse_16_bits (int in)
3438 static int mask[16] =
3440 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3441 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3443 for (n = 0; n < 16; n++)
3446 out |= mask[15 - n];
3449 } /* reverse_16_bits() */
3452 reverse_8_bits (int in)
3457 static int mask[8] =
3459 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3462 for (n = 0; n < 8; n++)
3468 } /* reverse_8_bits() */
3470 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3471 (that value is chosen in the frag_var call in md_assemble). TYPE
3472 is the subtype of the frag to be generated; its primary type is
3473 rs_machine_dependent.
3475 The TYPE parameter is also used by md_convert_frag_1 and
3476 md_estimate_size_before_relax. The appropriate type of fixup will
3477 be emitted by md_convert_frag_1.
3479 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3481 install_operand (int mode, int val)
3486 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3489 the_ins.opcode[0] |= val << 9;
3492 the_ins.opcode[1] |= val << 12;
3495 the_ins.opcode[1] |= val << 6;
3498 the_ins.opcode[1] |= val;
3501 the_ins.opcode[2] |= val << 12;
3504 the_ins.opcode[2] |= val << 6;
3507 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3508 three words long! */
3510 the_ins.opcode[2] |= val;
3513 the_ins.opcode[1] |= val << 7;
3516 the_ins.opcode[1] |= val << 10;
3520 the_ins.opcode[1] |= val << 5;
3525 the_ins.opcode[1] |= (val << 10) | (val << 7);
3528 the_ins.opcode[1] |= (val << 12) | val;
3531 the_ins.opcode[0] |= val = 0xff;
3534 the_ins.opcode[0] |= val << 9;
3537 the_ins.opcode[1] |= val;
3540 the_ins.opcode[1] |= val;
3541 the_ins.numo++; /* What a hack. */
3544 the_ins.opcode[1] |= val << 4;
3552 the_ins.opcode[0] |= (val << 6);
3555 the_ins.opcode[1] = (val >> 16);
3556 the_ins.opcode[2] = val & 0xffff;
3559 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3560 the_ins.opcode[0] |= ((val & 0x7) << 9);
3561 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3563 case 'n': /* MAC/EMAC Rx on !load. */
3564 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3565 the_ins.opcode[0] |= ((val & 0x7) << 9);
3566 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3568 case 'o': /* MAC/EMAC Rx on load. */
3569 the_ins.opcode[1] |= val << 12;
3570 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3572 case 'M': /* MAC/EMAC Ry on !load. */
3573 the_ins.opcode[0] |= (val & 0xF);
3574 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3576 case 'N': /* MAC/EMAC Ry on load. */
3577 the_ins.opcode[1] |= (val & 0xF);
3578 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3581 the_ins.opcode[1] |= ((val != 1) << 10);
3584 the_ins.opcode[0] |= ((val & 0x3) << 9);
3587 the_ins.opcode[0] |= ((val & 0x3) << 0);
3589 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3590 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3591 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3593 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3594 the_ins.opcode[0] |= ((val & 0x1) << 7);
3595 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3598 the_ins.opcode[1] |= ((val & 0x3) << 9);
3601 the_ins.opcode[0] |= (val & 0x1) <<10;
3605 as_fatal (_("failed sanity check."));
3610 install_gen_operand (int mode, int val)
3614 case '/': /* Special for mask loads for mac/msac insns with
3615 possible mask; trailing_ampersend set in bit 8. */
3616 the_ins.opcode[0] |= (val & 0x3f);
3617 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3620 the_ins.opcode[0] |= val;
3623 /* This is a kludge!!! */
3624 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3633 the_ins.opcode[0] |= val;
3635 /* more stuff goes here. */
3637 as_fatal (_("failed sanity check."));
3641 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3642 then deal with the bitfield hack. */
3645 crack_operand (char *str, struct m68k_op *opP)
3647 register int parens;
3649 register char *beg_str;
3657 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3663 else if (*str == ')')
3667 opP->error = _("Extra )");
3673 if (flag_mri && *str == '\'')
3674 inquote = ! inquote;
3676 if (!*str && parens)
3678 opP->error = _("Missing )");
3683 if (m68k_ip_op (beg_str, opP) != 0)
3690 c = *++str; /* JF bitfield hack. */
3695 as_bad (_("Missing operand"));
3698 /* Detect MRI REG symbols and convert them to REGLSTs. */
3699 if (opP->mode == CONTROL && (int)opP->reg < 0)
3702 opP->mask = ~(int)opP->reg;
3709 /* This is the guts of the machine-dependent assembler. STR points to a
3710 machine dependent instruction. This function is supposed to emit
3711 the frags/bytes it assembles to.
3715 insert_reg (const char *regname, int regnum)
3720 #ifdef REGISTER_PREFIX
3721 if (!flag_reg_prefix_optional)
3723 buf[0] = REGISTER_PREFIX;
3724 strcpy (buf + 1, regname);
3729 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3730 &zero_address_frag));
3732 for (i = 0; regname[i]; i++)
3733 buf[i] = TOUPPER (regname[i]);
3736 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3737 &zero_address_frag));
3746 static const struct init_entry init_table[] =
3806 { "accext01", ACCEXT01 },
3807 { "accext23", ACCEXT23 },
3811 /* Control registers. */
3812 { "sfc", SFC }, /* Source Function Code. */
3814 { "dfc", DFC }, /* Destination Function Code. */
3816 { "cacr", CACR }, /* Cache Control Register. */
3817 { "caar", CAAR }, /* Cache Address Register. */
3819 { "usp", USP }, /* User Stack Pointer. */
3820 { "vbr", VBR }, /* Vector Base Register. */
3821 { "msp", MSP }, /* Master Stack Pointer. */
3822 { "isp", ISP }, /* Interrupt Stack Pointer. */
3824 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3825 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3826 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3827 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3829 /* 68ec040 versions of same */
3830 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3831 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3832 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3833 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3835 /* Coldfire versions of same. The ColdFire programmer's reference
3836 manual indicated that the order is 2,3,0,1, but Ken Rose
3837 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3838 { "acr0", ACR0 }, /* Access Control Unit 0. */
3839 { "acr1", ACR1 }, /* Access Control Unit 1. */
3840 { "acr2", ACR2 }, /* Access Control Unit 2. */
3841 { "acr3", ACR3 }, /* Access Control Unit 3. */
3843 { "tc", TC }, /* MMU Translation Control Register. */
3847 { "mmusr", MMUSR }, /* MMU Status Register. */
3848 { "srp", SRP }, /* User Root Pointer. */
3849 { "urp", URP }, /* Supervisor Root Pointer. */
3852 { "mmubar", MMUBAR },
3855 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3856 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3857 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3858 { "mbar", MBAR }, /* Module Base Address Register. */
3860 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3861 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3862 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3863 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3864 { "mpcr", MPCR }, /* mcfv4e registers. */
3865 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3866 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3867 { "asid", TC }, /* mcfv4e registers. */
3868 { "mmubar", BUSCR }, /* mcfv4e registers. */
3869 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3870 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3871 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3872 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3873 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3874 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3875 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3876 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3877 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3878 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3879 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3880 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3882 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3883 { "rambar", RAMBAR }, /* mcf528x registers. */
3885 { "mbar2", MBAR2 }, /* mcf5249 registers. */
3887 { "cac", CAC }, /* fido registers. */
3888 { "mbb", MBB }, /* fido registers. */
3889 /* End of control registers. */
3923 /* 68ec030 versions of same. */
3926 /* 68ec030 access control unit, identical to 030 MMU status reg. */
3929 /* Suppressed data and address registers. */
3947 /* Upper and lower data and address registers, used by macw and msacw. */
3988 init_regtable (void)
3991 for (i = 0; init_table[i].name; i++)
3992 insert_reg (init_table[i].name, init_table[i].number);
3996 md_assemble (char *str)
4003 int shorts_this_frag;
4006 if (!selected_cpu && !selected_arch)
4008 /* We've not selected an architecture yet. Set the default
4009 now. We do this lazily so that an initial .cpu or .arch directive
4011 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4012 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4017 /* In MRI mode, the instruction and operands are separated by a
4018 space. Anything following the operands is a comment. The label
4019 has already been removed. */
4027 for (s = str; *s != '\0'; s++)
4029 if ((*s == ' ' || *s == '\t') && ! inquote)
4047 inquote = ! inquote;
4052 memset (&the_ins, '\0', sizeof (the_ins));
4057 for (n = 0; n < the_ins.numargs; n++)
4058 if (the_ins.operands[n].error)
4060 er = the_ins.operands[n].error;
4066 as_bad (_("%s -- statement `%s' ignored"), er, str);
4070 /* If there is a current label, record that it marks an instruction. */
4071 if (current_label != NULL)
4073 current_label->text = 1;
4074 current_label = NULL;
4078 /* Tie dwarf2 debug info to the address at the start of the insn. */
4079 dwarf2_emit_insn (0);
4082 if (the_ins.nfrag == 0)
4084 /* No frag hacking involved; just put it out. */
4085 toP = frag_more (2 * the_ins.numo);
4086 fromP = &the_ins.opcode[0];
4087 for (m = the_ins.numo; m; --m)
4089 md_number_to_chars (toP, (long) (*fromP), 2);
4093 /* Put out symbol-dependent info. */
4094 for (m = 0; m < the_ins.nrel; m++)
4096 switch (the_ins.reloc[m].wid)
4115 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4116 the_ins.reloc[m].wid);
4119 fixP = fix_new_exp (frag_now,
4120 ((toP - frag_now->fr_literal)
4121 - the_ins.numo * 2 + the_ins.reloc[m].n),
4123 &the_ins.reloc[m].exp,
4124 the_ins.reloc[m].pcrel,
4125 get_reloc_code (n, the_ins.reloc[m].pcrel,
4126 the_ins.reloc[m].pic_reloc));
4127 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4128 if (the_ins.reloc[m].wid == 'B')
4129 fixP->fx_signed = 1;
4134 /* There's some frag hacking. */
4136 /* Calculate the max frag size. */
4139 wid = 2 * the_ins.fragb[0].fragoff;
4140 for (n = 1; n < the_ins.nfrag; n++)
4141 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4142 /* frag_var part. */
4144 /* Make sure the whole insn fits in one chunk, in particular that
4145 the var part is attached, as we access one byte before the
4146 variable frag for byte branches. */
4150 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4155 wid = 2 * the_ins.fragb[n].fragoff;
4157 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4158 toP = frag_more (wid);
4160 shorts_this_frag = 0;
4161 for (m = wid / 2; m; --m)
4163 md_number_to_chars (toP, (long) (*fromP), 2);
4168 for (m = 0; m < the_ins.nrel; m++)
4170 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4172 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4175 wid = the_ins.reloc[m].wid;
4178 the_ins.reloc[m].wid = 0;
4179 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4181 fixP = fix_new_exp (frag_now,
4182 ((toP - frag_now->fr_literal)
4183 - the_ins.numo * 2 + the_ins.reloc[m].n),
4185 &the_ins.reloc[m].exp,
4186 the_ins.reloc[m].pcrel,
4187 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4188 the_ins.reloc[m].pic_reloc));
4189 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4191 (void) frag_var (rs_machine_dependent, 10, 0,
4192 (relax_substateT) (the_ins.fragb[n].fragty),
4193 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4195 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4196 shorts_this_frag = 0;
4199 toP = frag_more (n * 2);
4202 md_number_to_chars (toP, (long) (*fromP), 2);
4208 for (m = 0; m < the_ins.nrel; m++)
4212 wid = the_ins.reloc[m].wid;
4215 the_ins.reloc[m].wid = 0;
4216 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4218 fixP = fix_new_exp (frag_now,
4219 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4220 - shorts_this_frag * 2),
4222 &the_ins.reloc[m].exp,
4223 the_ins.reloc[m].pcrel,
4224 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4225 the_ins.reloc[m].pic_reloc));
4226 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4230 /* Comparison function used by qsort to rank the opcode entries by name. */
4233 m68k_compare_opcode (const void * v1, const void * v2)
4235 struct m68k_opcode * op1, * op2;
4241 op1 = *(struct m68k_opcode **) v1;
4242 op2 = *(struct m68k_opcode **) v2;
4244 /* Compare the two names. If different, return the comparison.
4245 If the same, return the order they are in the opcode table. */
4246 ret = strcmp (op1->name, op2->name);
4257 const struct m68k_opcode *ins;
4258 struct m68k_incant *hack, *slak;
4259 const char *retval = 0; /* Empty string, or error msg text. */
4262 /* Set up hash tables with 68000 instructions.
4263 similar to what the vax assembler does. */
4264 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4265 a copy of it at runtime, adding in the information we want but isn't
4266 there. I think it'd be better to have an awk script hack the table
4267 at compile time. Or even just xstr the table and use it as-is. But
4268 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4273 flag_reg_prefix_optional = 1;
4275 if (! m68k_rel32_from_cmdline)
4279 /* First sort the opcode table into alphabetical order to seperate
4280 the order that the assembler wants to see the opcodes from the
4281 order that the disassembler wants to see them. */
4282 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4283 if (!m68k_sorted_opcodes)
4284 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4285 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4287 for (i = m68k_numopcodes; i--;)
4288 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4290 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4291 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4293 op_hash = hash_new ();
4295 obstack_begin (&robyn, 4000);
4296 for (i = 0; i < m68k_numopcodes; i++)
4298 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4301 ins = m68k_sorted_opcodes[i];
4303 /* We *could* ignore insns that don't match our
4304 arch here by just leaving them out of the hash. */
4305 slak->m_operands = ins->args;
4306 slak->m_opnum = strlen (slak->m_operands) / 2;
4307 slak->m_arch = ins->arch;
4308 slak->m_opcode = ins->opcode;
4309 /* This is kludgey. */
4310 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4311 if (i + 1 != m68k_numopcodes
4312 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4314 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4319 slak = slak->m_next;
4323 retval = hash_insert (op_hash, ins->name, (char *) hack);
4325 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4328 for (i = 0; i < m68k_numaliases; i++)
4330 const char *name = m68k_opcode_aliases[i].primary;
4331 const char *alias = m68k_opcode_aliases[i].alias;
4332 PTR val = hash_find (op_hash, name);
4335 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4336 retval = hash_insert (op_hash, alias, val);
4338 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4341 /* In MRI mode, all unsized branches are variable sized. Normally,
4342 they are word sized. */
4345 static struct m68k_opcode_alias mri_aliases[] =
4366 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4369 const char *name = mri_aliases[i].primary;
4370 const char *alias = mri_aliases[i].alias;
4371 PTR val = hash_find (op_hash, name);
4374 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4375 retval = hash_jam (op_hash, alias, val);
4377 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4381 for (i = 0; i < (int) sizeof (notend_table); i++)
4383 notend_table[i] = 0;
4384 alt_notend_table[i] = 0;
4387 notend_table[','] = 1;
4388 notend_table['{'] = 1;
4389 notend_table['}'] = 1;
4390 alt_notend_table['a'] = 1;
4391 alt_notend_table['A'] = 1;
4392 alt_notend_table['d'] = 1;
4393 alt_notend_table['D'] = 1;
4394 alt_notend_table['#'] = 1;
4395 alt_notend_table['&'] = 1;
4396 alt_notend_table['f'] = 1;
4397 alt_notend_table['F'] = 1;
4398 #ifdef REGISTER_PREFIX
4399 alt_notend_table[REGISTER_PREFIX] = 1;
4402 /* We need to put '(' in alt_notend_table to handle
4403 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4404 alt_notend_table['('] = 1;
4406 /* We need to put '@' in alt_notend_table to handle
4407 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4408 alt_notend_table['@'] = 1;
4410 /* We need to put digits in alt_notend_table to handle
4411 bfextu %d0{24:1},%d0 */
4412 alt_notend_table['0'] = 1;
4413 alt_notend_table['1'] = 1;
4414 alt_notend_table['2'] = 1;
4415 alt_notend_table['3'] = 1;
4416 alt_notend_table['4'] = 1;
4417 alt_notend_table['5'] = 1;
4418 alt_notend_table['6'] = 1;
4419 alt_notend_table['7'] = 1;
4420 alt_notend_table['8'] = 1;
4421 alt_notend_table['9'] = 1;
4423 #ifndef MIT_SYNTAX_ONLY
4424 /* Insert pseudo ops, these have to go into the opcode table since
4425 gas expects pseudo ops to start with a dot. */
4429 while (mote_pseudo_table[n].poc_name)
4431 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4432 hash_insert (op_hash,
4433 mote_pseudo_table[n].poc_name, (char *) hack);
4434 hack->m_operands = 0;
4444 record_alignment (text_section, 2);
4445 record_alignment (data_section, 2);
4446 record_alignment (bss_section, 2);
4451 /* This is called when a label is defined. */
4454 m68k_frob_label (symbolS *sym)
4456 struct label_line *n;
4458 n = (struct label_line *) xmalloc (sizeof *n);
4461 as_where (&n->file, &n->line);
4467 dwarf2_emit_label (sym);
4471 /* This is called when a value that is not an instruction is emitted. */
4474 m68k_flush_pending_output (void)
4476 current_label = NULL;
4479 /* This is called at the end of the assembly, when the final value of
4480 the label is known. We warn if this is a text symbol aligned at an
4484 m68k_frob_symbol (symbolS *sym)
4486 if (S_GET_SEGMENT (sym) == reg_section
4487 && (int) S_GET_VALUE (sym) < 0)
4489 S_SET_SEGMENT (sym, absolute_section);
4490 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4492 else if ((S_GET_VALUE (sym) & 1) != 0)
4494 struct label_line *l;
4496 for (l = labels; l != NULL; l = l->next)
4498 if (l->label == sym)
4501 as_warn_where (l->file, l->line,
4502 _("text label `%s' aligned to odd boundary"),
4510 /* This is called if we go in or out of MRI mode because of the .mri
4514 m68k_mri_mode_change (int on)
4518 if (! flag_reg_prefix_optional)
4520 flag_reg_prefix_optional = 1;
4521 #ifdef REGISTER_PREFIX
4526 if (! m68k_rel32_from_cmdline)
4531 if (! reg_prefix_optional_seen)
4533 #ifdef REGISTER_PREFIX_OPTIONAL
4534 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4536 flag_reg_prefix_optional = 0;
4538 #ifdef REGISTER_PREFIX
4543 if (! m68k_rel32_from_cmdline)
4548 /* Equal to MAX_PRECISION in atof-ieee.c. */
4549 #define MAX_LITTLENUMS 6
4551 /* Turn a string in input_line_pointer into a floating point constant
4552 of type TYPE, and store the appropriate bytes in *LITP. The number
4553 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4554 returned, or NULL on OK. */
4557 md_atof (int type, char *litP, int *sizeP)
4560 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4561 LITTLENUM_TYPE *wordP;
4592 return _("Bad call to MD_ATOF()");
4594 t = atof_ieee (input_line_pointer, type, words);
4596 input_line_pointer = t;
4598 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4599 for (wordP = words; prec--;)
4601 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4602 litP += sizeof (LITTLENUM_TYPE);
4608 md_number_to_chars (char *buf, valueT val, int n)
4610 number_to_chars_bigendian (buf, val, n);
4614 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4616 offsetT val = *valP;
4617 addressT upper_limit;
4618 offsetT lower_limit;
4620 /* This is unnecessary but it convinces the native rs6000 compiler
4621 to generate the code we want. */
4622 char *buf = fixP->fx_frag->fr_literal;
4623 buf += fixP->fx_where;
4624 /* End ibm compiler workaround. */
4628 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4634 memset (buf, 0, fixP->fx_size);
4635 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4637 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4638 && !S_IS_DEFINED (fixP->fx_addsy)
4639 && !S_IS_WEAK (fixP->fx_addsy))
4640 S_SET_WEAK (fixP->fx_addsy);
4645 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4646 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4649 switch (fixP->fx_size)
4651 /* The cast to offsetT below are necessary to make code
4652 correct for machines where ints are smaller than offsetT. */
4656 lower_limit = - (offsetT) 0x80;
4659 *buf++ = (val >> 8);
4661 upper_limit = 0x7fff;
4662 lower_limit = - (offsetT) 0x8000;
4665 *buf++ = (val >> 24);
4666 *buf++ = (val >> 16);
4667 *buf++ = (val >> 8);
4669 upper_limit = 0x7fffffff;
4670 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4673 BAD_CASE (fixP->fx_size);
4676 /* Fix up a negative reloc. */
4677 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4679 fixP->fx_addsy = fixP->fx_subsy;
4680 fixP->fx_subsy = NULL;
4684 /* For non-pc-relative values, it's conceivable we might get something
4685 like "0xff" for a byte field. So extend the upper part of the range
4686 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4687 so that we can do any range checking at all. */
4688 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4689 upper_limit = upper_limit * 2 + 1;
4691 if ((addressT) val > upper_limit
4692 && (val > 0 || val < lower_limit))
4693 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4695 /* A one byte PC-relative reloc means a short branch. We can't use
4696 a short branch with a value of 0 or -1, because those indicate
4697 different opcodes (branches with longer offsets). fixup_segment
4698 in write.c may have clobbered fx_pcrel, so we need to examine the
4701 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4702 && fixP->fx_size == 1
4703 && (fixP->fx_addsy == NULL
4704 || S_IS_DEFINED (fixP->fx_addsy))
4705 && (val == 0 || val == -1))
4706 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4709 /* *fragP has been relaxed to its final size, and now needs to have
4710 the bytes inside it modified to conform to the new size There is UGLY
4714 md_convert_frag_1 (fragS *fragP)
4719 /* Address in object code of the displacement. */
4720 register int object_address = fragP->fr_fix + fragP->fr_address;
4722 /* Address in gas core of the place to store the displacement. */
4723 /* This convinces the native rs6000 compiler to generate the code we
4725 register char *buffer_address = fragP->fr_literal;
4726 buffer_address += fragP->fr_fix;
4727 /* End ibm compiler workaround. */
4729 /* The displacement of the address, from current location. */
4730 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4731 disp = (disp + fragP->fr_offset) - object_address;
4733 switch (fragP->fr_subtype)
4735 case TAB (BRANCHBWL, BYTE):
4736 case TAB (BRABSJUNC, BYTE):
4737 case TAB (BRABSJCOND, BYTE):
4738 case TAB (BRANCHBW, BYTE):
4739 know (issbyte (disp));
4741 as_bad_where (fragP->fr_file, fragP->fr_line,
4742 _("short branch with zero offset: use :w"));
4743 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4744 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4745 fixP->fx_pcrel_adjust = -1;
4747 case TAB (BRANCHBWL, SHORT):
4748 case TAB (BRABSJUNC, SHORT):
4749 case TAB (BRABSJCOND, SHORT):
4750 case TAB (BRANCHBW, SHORT):
4751 fragP->fr_opcode[1] = 0x00;
4752 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4753 1, RELAX_RELOC_PC16);
4756 case TAB (BRANCHBWL, LONG):
4757 fragP->fr_opcode[1] = (char) 0xFF;
4758 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4759 1, RELAX_RELOC_PC32);
4762 case TAB (BRABSJUNC, LONG):
4763 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4765 if (flag_keep_pcrel)
4766 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
4767 fragP->fr_opcode[0] = 0x4E;
4768 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4769 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4770 0, RELAX_RELOC_ABS32);
4773 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4775 if (flag_keep_pcrel)
4776 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
4777 fragP->fr_opcode[0] = 0x4E;
4778 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4779 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4780 0, RELAX_RELOC_ABS32);
4785 /* This cannot happen, because jbsr and jbra are the only two
4786 unconditional branches. */
4790 case TAB (BRABSJCOND, LONG):
4791 if (flag_keep_pcrel)
4792 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4794 /* Only Bcc 68000 instructions can come here
4795 Change bcc into b!cc/jmp absl long. */
4796 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4797 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4799 /* JF: these used to be fr_opcode[2,3], but they may be in a
4800 different frag, in which case referring to them is a no-no.
4801 Only fr_opcode[0,1] are guaranteed to work. */
4802 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4803 *buffer_address++ = (char) 0xf9;
4804 fragP->fr_fix += 2; /* Account for jmp instruction. */
4805 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4806 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4809 case TAB (FBRANCH, SHORT):
4810 know ((fragP->fr_opcode[1] & 0x40) == 0);
4811 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4812 1, RELAX_RELOC_PC16);
4815 case TAB (FBRANCH, LONG):
4816 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4817 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4818 1, RELAX_RELOC_PC32);
4821 case TAB (DBCCLBR, SHORT):
4822 case TAB (DBCCABSJ, SHORT):
4823 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4824 1, RELAX_RELOC_PC16);
4827 case TAB (DBCCLBR, LONG):
4828 /* Only DBcc instructions can come here.
4829 Change dbcc into dbcc/bral.
4830 JF: these used to be fr_opcode[2-7], but that's wrong. */
4831 if (flag_keep_pcrel)
4832 as_fatal (_("Tried to convert DBcc to absolute jump"));
4834 *buffer_address++ = 0x00; /* Branch offset = 4. */
4835 *buffer_address++ = 0x04;
4836 *buffer_address++ = 0x60; /* Put in bra pc+6. */
4837 *buffer_address++ = 0x06;
4838 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4839 *buffer_address++ = (char) 0xff;
4841 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4842 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4846 case TAB (DBCCABSJ, LONG):
4847 /* Only DBcc instructions can come here.
4848 Change dbcc into dbcc/jmp.
4849 JF: these used to be fr_opcode[2-7], but that's wrong. */
4850 if (flag_keep_pcrel)
4851 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4853 *buffer_address++ = 0x00; /* Branch offset = 4. */
4854 *buffer_address++ = 0x04;
4855 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
4856 *buffer_address++ = 0x06;
4857 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4858 *buffer_address++ = (char) 0xf9;
4860 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
4861 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4865 case TAB (PCREL1632, SHORT):
4866 fragP->fr_opcode[1] &= ~0x3F;
4867 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4868 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4869 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4872 case TAB (PCREL1632, LONG):
4873 /* Already set to mode 7.3; this indicates: PC indirect with
4874 suppressed index, 32-bit displacement. */
4875 *buffer_address++ = 0x01;
4876 *buffer_address++ = 0x70;
4878 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4879 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4880 fixP->fx_pcrel_adjust = 2;
4883 case TAB (PCINDEX, BYTE):
4884 assert (fragP->fr_fix >= 2);
4885 buffer_address[-2] &= ~1;
4886 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4887 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4888 fixP->fx_pcrel_adjust = 1;
4890 case TAB (PCINDEX, SHORT):
4891 assert (fragP->fr_fix >= 2);
4892 buffer_address[-2] |= 0x1;
4893 buffer_address[-1] = 0x20;
4894 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4895 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4896 fixP->fx_pcrel_adjust = 2;
4899 case TAB (PCINDEX, LONG):
4900 assert (fragP->fr_fix >= 2);
4901 buffer_address[-2] |= 0x1;
4902 buffer_address[-1] = 0x30;
4903 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4904 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4905 fixP->fx_pcrel_adjust = 2;
4908 case TAB (ABSTOPCREL, SHORT):
4909 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4910 1, RELAX_RELOC_PC16);
4913 case TAB (ABSTOPCREL, LONG):
4914 if (flag_keep_pcrel)
4915 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
4916 /* The thing to do here is force it to ABSOLUTE LONG, since
4917 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
4918 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4920 fragP->fr_opcode[1] &= ~0x3F;
4921 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4922 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4923 0, RELAX_RELOC_ABS32);
4930 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4931 segT sec ATTRIBUTE_UNUSED,
4934 md_convert_frag_1 (fragP);
4937 /* Force truly undefined symbols to their maximum size, and generally set up
4938 the frag list to be relaxed
4941 md_estimate_size_before_relax (fragS *fragP, segT segment)
4943 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4944 switch (fragP->fr_subtype)
4946 case TAB (BRANCHBWL, SZ_UNDEF):
4947 case TAB (BRABSJUNC, SZ_UNDEF):
4948 case TAB (BRABSJCOND, SZ_UNDEF):
4950 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4951 && relaxable_symbol (fragP->fr_symbol))
4953 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4955 else if (flag_short_refs)
4957 /* Symbol is undefined and we want short ref. */
4958 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4962 /* Symbol is still undefined. Make it LONG. */
4963 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4968 case TAB (BRANCHBW, SZ_UNDEF):
4970 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4971 && relaxable_symbol (fragP->fr_symbol))
4973 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4977 /* Symbol is undefined and we don't have long branches. */
4978 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4983 case TAB (FBRANCH, SZ_UNDEF):
4984 case TAB (DBCCLBR, SZ_UNDEF):
4985 case TAB (DBCCABSJ, SZ_UNDEF):
4986 case TAB (PCREL1632, SZ_UNDEF):
4988 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4989 && relaxable_symbol (fragP->fr_symbol))
4992 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4996 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5001 case TAB (PCINDEX, SZ_UNDEF):
5002 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5003 && relaxable_symbol (fragP->fr_symbol)))
5005 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5009 fragP->fr_subtype = TAB (PCINDEX, LONG);
5013 case TAB (ABSTOPCREL, SZ_UNDEF):
5015 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5016 && relaxable_symbol (fragP->fr_symbol)))
5018 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5022 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5031 /* Now that SZ_UNDEF are taken care of, check others. */
5032 switch (fragP->fr_subtype)
5034 case TAB (BRANCHBWL, BYTE):
5035 case TAB (BRABSJUNC, BYTE):
5036 case TAB (BRABSJCOND, BYTE):
5037 case TAB (BRANCHBW, BYTE):
5038 /* We can't do a short jump to the next instruction, so in that
5039 case we force word mode. If the symbol is at the start of a
5040 frag, and it is the next frag with any data in it (usually
5041 this is just the next frag, but assembler listings may
5042 introduce empty frags), we must use word mode. */
5043 if (fragP->fr_symbol)
5047 sym_frag = symbol_get_frag (fragP->fr_symbol);
5048 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5052 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5056 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5063 return md_relax_table[fragP->fr_subtype].rlx_length;
5066 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5067 /* the bit-field entries in the relocation_info struct plays hell
5068 with the byte-order problems of cross-assembly. So as a hack,
5069 I added this mach. dependent ri twiddler. Ugly, but it gets
5071 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5072 are symbolnum, most sig. byte first. Last byte is broken up with
5073 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5074 nibble as nuthin. (on Sun 3 at least) */
5075 /* Translate the internal relocation information into target-specific
5079 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5082 md_number_to_chars (the_bytes, ri->r_address, 4);
5083 /* Now the fun stuff. */
5084 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5085 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5086 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5087 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5088 | ((ri->r_length << 5) & 0x60)
5089 | ((ri->r_extern << 4) & 0x10));
5094 #endif /* OBJ_AOUT or OBJ_BOUT */
5096 #ifndef WORKING_DOT_WORD
5097 int md_short_jump_size = 4;
5098 int md_long_jump_size = 6;
5101 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5102 fragS *frag ATTRIBUTE_UNUSED,
5103 symbolS *to_symbol ATTRIBUTE_UNUSED)
5107 offset = to_addr - (from_addr + 2);
5109 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5110 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5114 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5115 fragS *frag, symbolS *to_symbol)
5119 if (!HAVE_LONG_BRANCH (current_architecture))
5121 if (flag_keep_pcrel)
5122 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5123 offset = to_addr - S_GET_VALUE (to_symbol);
5124 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5125 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5126 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5131 offset = to_addr - (from_addr + 2);
5132 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5133 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5139 /* Different values of OK tell what its OK to return. Things that
5140 aren't OK are an error (what a shock, no?)
5143 10: Absolute 1:8 only
5144 20: Absolute 0:7 only
5145 30: absolute 0:15 only
5146 40: Absolute 0:31 only
5147 50: absolute 0:127 only
5148 55: absolute -64:63 only
5149 60: absolute -128:127 only
5150 70: absolute 0:4095 only
5151 80: absolute -1, 1:7 only
5155 get_num (struct m68k_exp *exp, int ok)
5157 if (exp->exp.X_op == O_absent)
5159 /* Do the same thing the VAX asm does. */
5160 op (exp) = O_constant;
5166 as_warn (_("expression out of range: defaulting to 1"));
5170 else if (exp->exp.X_op == O_constant)
5175 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5177 as_warn (_("expression out of range: defaulting to 1"));
5182 if ((valueT) TRUNC (offs (exp)) > 7)
5186 if ((valueT) TRUNC (offs (exp)) > 15)
5190 if ((valueT) TRUNC (offs (exp)) > 32)
5194 if ((valueT) TRUNC (offs (exp)) > 127)
5198 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5202 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5206 if ((valueT) TRUNC (offs (exp)) > 4095)
5209 as_warn (_("expression out of range: defaulting to 0"));
5214 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5215 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5217 as_warn (_("expression out of range: defaulting to 1"));
5225 else if (exp->exp.X_op == O_big)
5227 if (offs (exp) <= 0 /* flonum. */
5228 && (ok == 90 /* no bignums */
5229 || (ok > 10 /* Small-int ranges including 0 ok. */
5230 /* If we have a flonum zero, a zero integer should
5231 do as well (e.g., in moveq). */
5232 && generic_floating_point_number.exponent == 0
5233 && generic_floating_point_number.low[0] == 0)))
5235 /* HACK! Turn it into a long. */
5236 LITTLENUM_TYPE words[6];
5238 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5239 op (exp) = O_constant;
5242 offs (exp) = words[1] | (words[0] << 16);
5246 op (exp) = O_constant;
5249 offs (exp) = (ok == 10) ? 1 : 0;
5250 as_warn (_("Can't deal with expression; defaulting to %ld"),
5256 if (ok >= 10 && ok <= 80)
5258 op (exp) = O_constant;
5261 offs (exp) = (ok == 10) ? 1 : 0;
5262 as_warn (_("Can't deal with expression; defaulting to %ld"),
5267 if (exp->size != SIZE_UNSPEC)
5275 if (!isbyte (offs (exp)))
5276 as_warn (_("expression doesn't fit in BYTE"));
5279 if (!isword (offs (exp)))
5280 as_warn (_("expression doesn't fit in WORD"));
5288 /* These are the back-ends for the various machine dependent pseudo-ops. */
5291 s_data1 (int ignore ATTRIBUTE_UNUSED)
5293 subseg_set (data_section, 1);
5294 demand_empty_rest_of_line ();
5298 s_data2 (int ignore ATTRIBUTE_UNUSED)
5300 subseg_set (data_section, 2);
5301 demand_empty_rest_of_line ();
5305 s_bss (int ignore ATTRIBUTE_UNUSED)
5307 /* We don't support putting frags in the BSS segment, we fake it
5308 by marking in_bss, then looking at s_skip for clues. */
5310 subseg_set (bss_section, 0);
5311 demand_empty_rest_of_line ();
5315 s_even (int ignore ATTRIBUTE_UNUSED)
5318 register long temp_fill;
5320 temp = 1; /* JF should be 2? */
5321 temp_fill = get_absolute_expression ();
5322 if (!need_pass_2) /* Never make frag if expect extra pass. */
5323 frag_align (temp, (int) temp_fill, 0);
5324 demand_empty_rest_of_line ();
5325 record_alignment (now_seg, temp);
5329 s_proc (int ignore ATTRIBUTE_UNUSED)
5331 demand_empty_rest_of_line ();
5334 /* Pseudo-ops handled for MRI compatibility. */
5336 /* This function returns non-zero if the argument is a conditional
5337 pseudo-op. This is called when checking whether a pending
5338 alignment is needed. */
5341 m68k_conditional_pseudoop (pseudo_typeS *pop)
5343 return (pop->poc_handler == s_mri_if
5344 || pop->poc_handler == s_mri_else);
5347 /* Handle an MRI style chip specification. */
5356 s = input_line_pointer;
5357 /* We can't use get_symbol_end since the processor names are not proper
5359 while (is_part_of_name (c = *input_line_pointer++))
5361 *--input_line_pointer = 0;
5362 for (i = 0; m68k_cpus[i].name; i++)
5363 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5365 if (!m68k_cpus[i].name)
5367 as_bad (_("%s: unrecognized processor name"), s);
5368 *input_line_pointer = c;
5369 ignore_rest_of_line ();
5372 *input_line_pointer = c;
5374 if (*input_line_pointer == '/')
5375 current_architecture = 0;
5377 current_architecture &= m68881 | m68851;
5378 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5379 control_regs = m68k_cpus[i].control_regs;
5381 while (*input_line_pointer == '/')
5383 ++input_line_pointer;
5384 s = input_line_pointer;
5385 /* We can't use get_symbol_end since the processor names are not
5387 while (is_part_of_name (c = *input_line_pointer++))
5389 *--input_line_pointer = 0;
5390 if (strcmp (s, "68881") == 0)
5391 current_architecture |= m68881;
5392 else if (strcmp (s, "68851") == 0)
5393 current_architecture |= m68851;
5394 *input_line_pointer = c;
5398 /* The MRI CHIP pseudo-op. */
5401 s_chip (int ignore ATTRIBUTE_UNUSED)
5407 stop = mri_comment_field (&stopc);
5410 mri_comment_end (stop, stopc);
5411 demand_empty_rest_of_line ();
5414 /* The MRI FOPT pseudo-op. */
5417 s_fopt (int ignore ATTRIBUTE_UNUSED)
5421 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5425 input_line_pointer += 3;
5426 temp = get_absolute_expression ();
5427 if (temp < 0 || temp > 7)
5428 as_bad (_("bad coprocessor id"));
5430 m68k_float_copnum = COP0 + temp;
5434 as_bad (_("unrecognized fopt option"));
5435 ignore_rest_of_line ();
5439 demand_empty_rest_of_line ();
5442 /* The structure used to handle the MRI OPT pseudo-op. */
5446 /* The name of the option. */
5449 /* If this is not NULL, just call this function. The first argument
5450 is the ARG field of this structure, the second argument is
5451 whether the option was negated. */
5452 void (*pfn) (int arg, int on);
5454 /* If this is not NULL, and the PFN field is NULL, set the variable
5455 this points to. Set it to the ARG field if the option was not
5456 negated, and the NOTARG field otherwise. */
5459 /* The value to pass to PFN or to assign to *PVAR. */
5462 /* The value to assign to *PVAR if the option is negated. If PFN is
5463 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5464 the option may not be negated. */
5468 /* The table used to handle the MRI OPT pseudo-op. */
5470 static void skip_to_comma (int, int);
5471 static void opt_nest (int, int);
5472 static void opt_chip (int, int);
5473 static void opt_list (int, int);
5474 static void opt_list_symbols (int, int);
5476 static const struct opt_action opt_table[] =
5478 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5480 /* We do relaxing, so there is little use for these options. */
5481 { "b", 0, 0, 0, 0 },
5482 { "brs", 0, 0, 0, 0 },
5483 { "brb", 0, 0, 0, 0 },
5484 { "brl", 0, 0, 0, 0 },
5485 { "brw", 0, 0, 0, 0 },
5487 { "c", 0, 0, 0, 0 },
5488 { "cex", 0, 0, 0, 0 },
5489 { "case", 0, &symbols_case_sensitive, 1, 0 },
5490 { "cl", 0, 0, 0, 0 },
5491 { "cre", 0, 0, 0, 0 },
5492 { "d", 0, &flag_keep_locals, 1, 0 },
5493 { "e", 0, 0, 0, 0 },
5494 { "f", 0, &flag_short_refs, 1, 0 },
5495 { "frs", 0, &flag_short_refs, 1, 0 },
5496 { "frl", 0, &flag_short_refs, 0, 1 },
5497 { "g", 0, 0, 0, 0 },
5498 { "i", 0, 0, 0, 0 },
5499 { "m", 0, 0, 0, 0 },
5500 { "mex", 0, 0, 0, 0 },
5501 { "mc", 0, 0, 0, 0 },
5502 { "md", 0, 0, 0, 0 },
5503 { "nest", opt_nest, 0, 0, 0 },
5504 { "next", skip_to_comma, 0, 0, 0 },
5505 { "o", 0, 0, 0, 0 },
5506 { "old", 0, 0, 0, 0 },
5507 { "op", skip_to_comma, 0, 0, 0 },
5508 { "pco", 0, 0, 0, 0 },
5509 { "p", opt_chip, 0, 0, 0 },
5510 { "pcr", 0, 0, 0, 0 },
5511 { "pcs", 0, 0, 0, 0 },
5512 { "r", 0, 0, 0, 0 },
5513 { "quick", 0, &m68k_quick, 1, 0 },
5514 { "rel32", 0, &m68k_rel32, 1, 0 },
5515 { "s", opt_list, 0, 0, 0 },
5516 { "t", opt_list_symbols, 0, 0, 0 },
5517 { "w", 0, &flag_no_warnings, 0, 1 },
5521 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5523 /* The MRI OPT pseudo-op. */
5526 s_opt (int ignore ATTRIBUTE_UNUSED)
5534 const struct opt_action *o;
5539 if (*input_line_pointer == '-')
5541 ++input_line_pointer;
5544 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5546 input_line_pointer += 2;
5550 s = input_line_pointer;
5551 c = get_symbol_end ();
5553 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5555 if (strcasecmp (s, o->name) == 0)
5559 /* Restore input_line_pointer now in case the option
5561 *input_line_pointer = c;
5562 (*o->pfn) (o->arg, t);
5564 else if (o->pvar != NULL)
5566 if (! t && o->arg == o->notarg)
5567 as_bad (_("option `%s' may not be negated"), s);
5568 *input_line_pointer = c;
5569 *o->pvar = t ? o->arg : o->notarg;
5572 *input_line_pointer = c;
5578 as_bad (_("option `%s' not recognized"), s);
5579 *input_line_pointer = c;
5582 while (*input_line_pointer++ == ',');
5584 /* Move back to terminating character. */
5585 --input_line_pointer;
5586 demand_empty_rest_of_line ();
5589 /* Skip ahead to a comma. This is used for OPT options which we do
5590 not support and which take arguments. */
5593 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5595 while (*input_line_pointer != ','
5596 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5597 ++input_line_pointer;
5600 /* Handle the OPT NEST=depth option. */
5603 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5605 if (*input_line_pointer != '=')
5607 as_bad (_("bad format of OPT NEST=depth"));
5611 ++input_line_pointer;
5612 max_macro_nest = get_absolute_expression ();
5615 /* Handle the OPT P=chip option. */
5618 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5620 if (*input_line_pointer != '=')
5622 /* This is just OPT P, which we do not support. */
5626 ++input_line_pointer;
5630 /* Handle the OPT S option. */
5633 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5638 /* Handle the OPT T option. */
5641 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5644 listing |= LISTING_SYMBOLS;
5646 listing &= ~LISTING_SYMBOLS;
5649 /* Handle the MRI REG pseudo-op. */
5652 s_reg (int ignore ATTRIBUTE_UNUSED)
5661 if (line_label == NULL)
5663 as_bad (_("missing label"));
5664 ignore_rest_of_line ();
5669 stop = mri_comment_field (&stopc);
5673 s = input_line_pointer;
5674 while (ISALNUM (*input_line_pointer)
5675 #ifdef REGISTER_PREFIX
5676 || *input_line_pointer == REGISTER_PREFIX
5678 || *input_line_pointer == '/'
5679 || *input_line_pointer == '-')
5680 ++input_line_pointer;
5681 c = *input_line_pointer;
5682 *input_line_pointer = '\0';
5684 if (m68k_ip_op (s, &rop) != 0)
5686 if (rop.error == NULL)
5687 as_bad (_("bad register list"));
5689 as_bad (_("bad register list: %s"), rop.error);
5690 *input_line_pointer = c;
5691 ignore_rest_of_line ();
5695 *input_line_pointer = c;
5697 if (rop.mode == REGLST)
5699 else if (rop.mode == DREG)
5700 mask = 1 << (rop.reg - DATA0);
5701 else if (rop.mode == AREG)
5702 mask = 1 << (rop.reg - ADDR0 + 8);
5703 else if (rop.mode == FPREG)
5704 mask = 1 << (rop.reg - FP0 + 16);
5705 else if (rop.mode == CONTROL
5708 else if (rop.mode == CONTROL
5711 else if (rop.mode == CONTROL
5716 as_bad (_("bad register list"));
5717 ignore_rest_of_line ();
5721 S_SET_SEGMENT (line_label, reg_section);
5722 S_SET_VALUE (line_label, ~mask);
5723 symbol_set_frag (line_label, &zero_address_frag);
5726 mri_comment_end (stop, stopc);
5728 demand_empty_rest_of_line ();
5731 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5735 struct save_opts *next;
5737 int symbols_case_sensitive;
5741 const enum m68k_register *control_regs;
5746 /* FIXME: We don't save OPT S. */
5749 /* This variable holds the stack of saved options. */
5751 static struct save_opts *save_stack;
5753 /* The MRI SAVE pseudo-op. */
5756 s_save (int ignore ATTRIBUTE_UNUSED)
5758 struct save_opts *s;
5760 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5761 s->abspcadd = m68k_abspcadd;
5762 s->symbols_case_sensitive = symbols_case_sensitive;
5763 s->keep_locals = flag_keep_locals;
5764 s->short_refs = flag_short_refs;
5765 s->architecture = current_architecture;
5766 s->control_regs = control_regs;
5767 s->quick = m68k_quick;
5768 s->rel32 = m68k_rel32;
5769 s->listing = listing;
5770 s->no_warnings = flag_no_warnings;
5772 s->next = save_stack;
5775 demand_empty_rest_of_line ();
5778 /* The MRI RESTORE pseudo-op. */
5781 s_restore (int ignore ATTRIBUTE_UNUSED)
5783 struct save_opts *s;
5785 if (save_stack == NULL)
5787 as_bad (_("restore without save"));
5788 ignore_rest_of_line ();
5793 save_stack = s->next;
5795 m68k_abspcadd = s->abspcadd;
5796 symbols_case_sensitive = s->symbols_case_sensitive;
5797 flag_keep_locals = s->keep_locals;
5798 flag_short_refs = s->short_refs;
5799 current_architecture = s->architecture;
5800 control_regs = s->control_regs;
5801 m68k_quick = s->quick;
5802 m68k_rel32 = s->rel32;
5803 listing = s->listing;
5804 flag_no_warnings = s->no_warnings;
5808 demand_empty_rest_of_line ();
5811 /* Types of MRI structured control directives. */
5813 enum mri_control_type
5821 /* This structure is used to stack the MRI structured control
5824 struct mri_control_info
5826 /* The directive within which this one is enclosed. */
5827 struct mri_control_info *outer;
5829 /* The type of directive. */
5830 enum mri_control_type type;
5832 /* Whether an ELSE has been in an IF. */
5835 /* The add or sub statement at the end of a FOR. */
5838 /* The label of the top of a FOR or REPEAT loop. */
5841 /* The label to jump to for the next iteration, or the else
5842 expression of a conditional. */
5845 /* The label to jump to to break out of the loop, or the label past
5846 the end of a conditional. */
5850 /* The stack of MRI structured control directives. */
5852 static struct mri_control_info *mri_control_stack;
5854 /* The current MRI structured control directive index number, used to
5855 generate label names. */
5857 static int mri_control_index;
5859 /* Assemble an instruction for an MRI structured control directive. */
5862 mri_assemble (char *str)
5866 /* md_assemble expects the opcode to be in lower case. */
5867 for (s = str; *s != ' ' && *s != '\0'; s++)
5873 /* Generate a new MRI label structured control directive label name. */
5876 mri_control_label (void)
5880 n = (char *) xmalloc (20);
5881 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5882 ++mri_control_index;
5886 /* Create a new MRI structured control directive. */
5888 static struct mri_control_info *
5889 push_mri_control (enum mri_control_type type)
5891 struct mri_control_info *n;
5893 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5897 if (type == mri_if || type == mri_while)
5900 n->top = mri_control_label ();
5901 n->next = mri_control_label ();
5902 n->bottom = mri_control_label ();
5904 n->outer = mri_control_stack;
5905 mri_control_stack = n;
5910 /* Pop off the stack of MRI structured control directives. */
5913 pop_mri_control (void)
5915 struct mri_control_info *n;
5917 n = mri_control_stack;
5918 mri_control_stack = n->outer;
5926 /* Recognize a condition code in an MRI structured control expression. */
5929 parse_mri_condition (int *pcc)
5933 know (*input_line_pointer == '<');
5935 ++input_line_pointer;
5936 c1 = *input_line_pointer++;
5937 c2 = *input_line_pointer++;
5939 if (*input_line_pointer != '>')
5941 as_bad (_("syntax error in structured control directive"));
5945 ++input_line_pointer;
5951 *pcc = (c1 << 8) | c2;
5956 /* Parse a single operand in an MRI structured control expression. */
5959 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5960 char **rightstart, char **rightstop)
5972 if (*input_line_pointer == '<')
5974 /* It's just a condition code. */
5975 return parse_mri_condition (pcc);
5978 /* Look ahead for the condition code. */
5979 for (s = input_line_pointer; *s != '\0'; ++s)
5981 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5986 as_bad (_("missing condition code in structured control directive"));
5990 *leftstart = input_line_pointer;
5992 if (*leftstop > *leftstart
5993 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5996 input_line_pointer = s;
5997 if (! parse_mri_condition (pcc))
6000 /* Look ahead for AND or OR or end of line. */
6001 for (s = input_line_pointer; *s != '\0'; ++s)
6003 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6004 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6006 if ((s == input_line_pointer
6009 && ((strncasecmp (s, "AND", 3) == 0
6010 && (s[3] == '.' || ! is_part_of_name (s[3])))
6011 || (strncasecmp (s, "OR", 2) == 0
6012 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6016 *rightstart = input_line_pointer;
6018 if (*rightstop > *rightstart
6019 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6022 input_line_pointer = s;
6027 #define MCC(b1, b2) (((b1) << 8) | (b2))
6029 /* Swap the sense of a condition. This changes the condition so that
6030 it generates the same result when the operands are swapped. */
6033 swap_mri_condition (int cc)
6037 case MCC ('h', 'i'): return MCC ('c', 's');
6038 case MCC ('l', 's'): return MCC ('c', 'c');
6039 /* <HS> is an alias for <CC>. */
6040 case MCC ('h', 's'):
6041 case MCC ('c', 'c'): return MCC ('l', 's');
6042 /* <LO> is an alias for <CS>. */
6043 case MCC ('l', 'o'):
6044 case MCC ('c', 's'): return MCC ('h', 'i');
6045 case MCC ('p', 'l'): return MCC ('m', 'i');
6046 case MCC ('m', 'i'): return MCC ('p', 'l');
6047 case MCC ('g', 'e'): return MCC ('l', 'e');
6048 case MCC ('l', 't'): return MCC ('g', 't');
6049 case MCC ('g', 't'): return MCC ('l', 't');
6050 case MCC ('l', 'e'): return MCC ('g', 'e');
6051 /* Issue a warning for conditions we can not swap. */
6052 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6053 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6054 case MCC ('v', 'c'):
6055 case MCC ('v', 's'):
6057 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6058 (char) (cc >> 8), (char) (cc));
6064 /* Reverse the sense of a condition. */
6067 reverse_mri_condition (int cc)
6071 case MCC ('h', 'i'): return MCC ('l', 's');
6072 case MCC ('l', 's'): return MCC ('h', 'i');
6073 /* <HS> is an alias for <CC> */
6074 case MCC ('h', 's'): return MCC ('l', 'o');
6075 case MCC ('c', 'c'): return MCC ('c', 's');
6076 /* <LO> is an alias for <CS> */
6077 case MCC ('l', 'o'): return MCC ('h', 's');
6078 case MCC ('c', 's'): return MCC ('c', 'c');
6079 case MCC ('n', 'e'): return MCC ('e', 'q');
6080 case MCC ('e', 'q'): return MCC ('n', 'e');
6081 case MCC ('v', 'c'): return MCC ('v', 's');
6082 case MCC ('v', 's'): return MCC ('v', 'c');
6083 case MCC ('p', 'l'): return MCC ('m', 'i');
6084 case MCC ('m', 'i'): return MCC ('p', 'l');
6085 case MCC ('g', 'e'): return MCC ('l', 't');
6086 case MCC ('l', 't'): return MCC ('g', 'e');
6087 case MCC ('g', 't'): return MCC ('l', 'e');
6088 case MCC ('l', 'e'): return MCC ('g', 't');
6093 /* Build an MRI structured control expression. This generates test
6094 and branch instructions. It goes to TRUELAB if the condition is
6095 true, and to FALSELAB if the condition is false. Exactly one of
6096 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6097 is the size qualifier for the expression. EXTENT is the size to
6098 use for the branch. */
6101 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6102 char *rightstart, char *rightstop,
6103 const char *truelab, const char *falselab,
6109 if (leftstart != NULL)
6111 struct m68k_op leftop, rightop;
6114 /* Swap the compare operands, if necessary, to produce a legal
6115 m68k compare instruction. Comparing a register operand with
6116 a non-register operand requires the register to be on the
6117 right (cmp, cmpa). Comparing an immediate value with
6118 anything requires the immediate value to be on the left
6123 (void) m68k_ip_op (leftstart, &leftop);
6128 (void) m68k_ip_op (rightstart, &rightop);
6131 if (rightop.mode == IMMED
6132 || ((leftop.mode == DREG || leftop.mode == AREG)
6133 && (rightop.mode != DREG && rightop.mode != AREG)))
6137 /* Correct conditional handling:
6138 if #1 <lt> d0 then ;means if (1 < d0)
6144 cmp #1,d0 if we do *not* swap the operands
6145 bgt true we need the swapped condition!
6152 leftstart = rightstart;
6155 leftstop = rightstop;
6160 cc = swap_mri_condition (cc);
6164 if (truelab == NULL)
6166 cc = reverse_mri_condition (cc);
6170 if (leftstart != NULL)
6172 buf = (char *) xmalloc (20
6173 + (leftstop - leftstart)
6174 + (rightstop - rightstart));
6180 *s++ = TOLOWER (qual);
6182 memcpy (s, leftstart, leftstop - leftstart);
6183 s += leftstop - leftstart;
6185 memcpy (s, rightstart, rightstop - rightstart);
6186 s += rightstop - rightstart;
6192 buf = (char *) xmalloc (20 + strlen (truelab));
6198 *s++ = TOLOWER (extent);
6200 strcpy (s, truelab);
6205 /* Parse an MRI structured control expression. This generates test
6206 and branch instructions. STOP is where the expression ends. It
6207 goes to TRUELAB if the condition is true, and to FALSELAB if the
6208 condition is false. Exactly one of TRUELAB and FALSELAB will be
6209 NULL, meaning to fall through. QUAL is the size qualifier for the
6210 expression. EXTENT is the size to use for the branch. */
6213 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6214 const char *falselab, int extent)
6226 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6227 &rightstart, &rightstop))
6233 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6237 if (falselab != NULL)
6240 flab = mri_control_label ();
6242 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6243 rightstop, (const char *) NULL, flab, extent);
6245 input_line_pointer += 3;
6246 if (*input_line_pointer != '.'
6247 || input_line_pointer[1] == '\0')
6251 qual = input_line_pointer[1];
6252 input_line_pointer += 2;
6255 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6256 &rightstart, &rightstop))
6262 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6263 rightstop, truelab, falselab, extent);
6265 if (falselab == NULL)
6268 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6272 if (truelab != NULL)
6275 tlab = mri_control_label ();
6277 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6278 rightstop, tlab, (const char *) NULL, extent);
6280 input_line_pointer += 2;
6281 if (*input_line_pointer != '.'
6282 || input_line_pointer[1] == '\0')
6286 qual = input_line_pointer[1];
6287 input_line_pointer += 2;
6290 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6291 &rightstart, &rightstop))
6297 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6298 rightstop, truelab, falselab, extent);
6300 if (truelab == NULL)
6305 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6306 rightstop, truelab, falselab, extent);
6310 if (input_line_pointer != stop)
6311 as_bad (_("syntax error in structured control directive"));
6314 /* Handle the MRI IF pseudo-op. This may be a structured control
6315 directive, or it may be a regular assembler conditional, depending
6323 struct mri_control_info *n;
6325 /* A structured control directive must end with THEN with an
6326 optional qualifier. */
6327 s = input_line_pointer;
6328 /* We only accept '*' as introduction of comments if preceded by white space
6329 or at first column of a line (I think this can't actually happen here?)
6330 This is important when assembling:
6331 if d0 <ne> 12(a0,d0*2) then
6332 if d0 <ne> #CONST*20 then. */
6333 while (! (is_end_of_line[(unsigned char) *s]
6336 && (s == input_line_pointer
6338 || *(s-1) == '\t'))))
6341 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6344 if (s - input_line_pointer > 1
6348 if (s - input_line_pointer < 3
6349 || strncasecmp (s - 3, "THEN", 4) != 0)
6353 as_bad (_("missing then"));
6354 ignore_rest_of_line ();
6358 /* It's a conditional. */
6363 /* Since this might be a conditional if, this pseudo-op will be
6364 called even if we are supported to be ignoring input. Double
6365 check now. Clobber *input_line_pointer so that ignore_input
6366 thinks that this is not a special pseudo-op. */
6367 c = *input_line_pointer;
6368 *input_line_pointer = 0;
6369 if (ignore_input ())
6371 *input_line_pointer = c;
6372 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6373 ++input_line_pointer;
6374 demand_empty_rest_of_line ();
6377 *input_line_pointer = c;
6379 n = push_mri_control (mri_if);
6381 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6382 n->next, s[1] == '.' ? s[2] : '\0');
6385 input_line_pointer = s + 3;
6387 input_line_pointer = s + 1;
6391 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6392 ++input_line_pointer;
6395 demand_empty_rest_of_line ();
6398 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6399 structured IF, associate the ELSE with the IF. Otherwise, assume
6400 it is a conditional else. */
6403 s_mri_else (int qual)
6410 && (mri_control_stack == NULL
6411 || mri_control_stack->type != mri_if
6412 || mri_control_stack->else_seen))
6418 c = *input_line_pointer;
6419 *input_line_pointer = 0;
6420 if (ignore_input ())
6422 *input_line_pointer = c;
6423 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6424 ++input_line_pointer;
6425 demand_empty_rest_of_line ();
6428 *input_line_pointer = c;
6430 if (mri_control_stack == NULL
6431 || mri_control_stack->type != mri_if
6432 || mri_control_stack->else_seen)
6434 as_bad (_("else without matching if"));
6435 ignore_rest_of_line ();
6439 mri_control_stack->else_seen = 1;
6441 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6442 q[0] = TOLOWER (qual);
6444 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6448 colon (mri_control_stack->next);
6452 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6453 ++input_line_pointer;
6456 demand_empty_rest_of_line ();
6459 /* Handle the MRI ENDI pseudo-op. */
6462 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6464 if (mri_control_stack == NULL
6465 || mri_control_stack->type != mri_if)
6467 as_bad (_("endi without matching if"));
6468 ignore_rest_of_line ();
6472 /* ignore_input will not return true for ENDI, so we don't need to
6473 worry about checking it again here. */
6475 if (! mri_control_stack->else_seen)
6476 colon (mri_control_stack->next);
6477 colon (mri_control_stack->bottom);
6483 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6484 ++input_line_pointer;
6487 demand_empty_rest_of_line ();
6490 /* Handle the MRI BREAK pseudo-op. */
6493 s_mri_break (int extent)
6495 struct mri_control_info *n;
6499 n = mri_control_stack;
6501 && n->type != mri_for
6502 && n->type != mri_repeat
6503 && n->type != mri_while)
6507 as_bad (_("break outside of structured loop"));
6508 ignore_rest_of_line ();
6512 buf = (char *) xmalloc (20 + strlen (n->bottom));
6513 ex[0] = TOLOWER (extent);
6515 sprintf (buf, "bra%s %s", ex, n->bottom);
6521 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6522 ++input_line_pointer;
6525 demand_empty_rest_of_line ();
6528 /* Handle the MRI NEXT pseudo-op. */
6531 s_mri_next (int extent)
6533 struct mri_control_info *n;
6537 n = mri_control_stack;
6539 && n->type != mri_for
6540 && n->type != mri_repeat
6541 && n->type != mri_while)
6545 as_bad (_("next outside of structured loop"));
6546 ignore_rest_of_line ();
6550 buf = (char *) xmalloc (20 + strlen (n->next));
6551 ex[0] = TOLOWER (extent);
6553 sprintf (buf, "bra%s %s", ex, n->next);
6559 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6560 ++input_line_pointer;
6563 demand_empty_rest_of_line ();
6566 /* Handle the MRI FOR pseudo-op. */
6569 s_mri_for (int qual)
6571 const char *varstart, *varstop;
6572 const char *initstart, *initstop;
6573 const char *endstart, *endstop;
6574 const char *bystart, *bystop;
6578 struct mri_control_info *n;
6584 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6588 varstart = input_line_pointer;
6590 /* Look for the '='. */
6591 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6592 && *input_line_pointer != '=')
6593 ++input_line_pointer;
6594 if (*input_line_pointer != '=')
6596 as_bad (_("missing ="));
6597 ignore_rest_of_line ();
6601 varstop = input_line_pointer;
6602 if (varstop > varstart
6603 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6606 ++input_line_pointer;
6608 initstart = input_line_pointer;
6610 /* Look for TO or DOWNTO. */
6613 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6615 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6616 && ! is_part_of_name (input_line_pointer[2]))
6618 initstop = input_line_pointer;
6619 input_line_pointer += 2;
6622 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6623 && ! is_part_of_name (input_line_pointer[6]))
6625 initstop = input_line_pointer;
6627 input_line_pointer += 6;
6630 ++input_line_pointer;
6632 if (initstop == NULL)
6634 as_bad (_("missing to or downto"));
6635 ignore_rest_of_line ();
6638 if (initstop > initstart
6639 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6643 endstart = input_line_pointer;
6645 /* Look for BY or DO. */
6648 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6650 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6651 && ! is_part_of_name (input_line_pointer[2]))
6653 endstop = input_line_pointer;
6655 input_line_pointer += 2;
6658 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6659 && (input_line_pointer[2] == '.'
6660 || ! is_part_of_name (input_line_pointer[2])))
6662 endstop = input_line_pointer;
6663 input_line_pointer += 2;
6666 ++input_line_pointer;
6668 if (endstop == NULL)
6670 as_bad (_("missing do"));
6671 ignore_rest_of_line ();
6674 if (endstop > endstart
6675 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6681 bystop = bystart + 2;
6686 bystart = input_line_pointer;
6690 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6692 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6693 && (input_line_pointer[2] == '.'
6694 || ! is_part_of_name (input_line_pointer[2])))
6696 bystop = input_line_pointer;
6697 input_line_pointer += 2;
6700 ++input_line_pointer;
6704 as_bad (_("missing do"));
6705 ignore_rest_of_line ();
6708 if (bystop > bystart
6709 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6713 if (*input_line_pointer != '.')
6717 extent = input_line_pointer[1];
6718 input_line_pointer += 2;
6721 /* We have fully parsed the FOR operands. Now build the loop. */
6722 n = push_mri_control (mri_for);
6724 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6726 /* Move init,var. */
6733 *s++ = TOLOWER (qual);
6735 memcpy (s, initstart, initstop - initstart);
6736 s += initstop - initstart;
6738 memcpy (s, varstart, varstop - varstart);
6739 s += varstop - varstart;
6751 *s++ = TOLOWER (qual);
6753 memcpy (s, endstart, endstop - endstart);
6754 s += endstop - endstart;
6756 memcpy (s, varstart, varstop - varstart);
6757 s += varstop - varstart;
6762 ex[0] = TOLOWER (extent);
6765 sprintf (buf, "blt%s %s", ex, n->bottom);
6767 sprintf (buf, "bgt%s %s", ex, n->bottom);
6770 /* Put together the add or sub instruction used by ENDF. */
6778 *s++ = TOLOWER (qual);
6780 memcpy (s, bystart, bystop - bystart);
6781 s += bystop - bystart;
6783 memcpy (s, varstart, varstop - varstart);
6784 s += varstop - varstart;
6790 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6791 ++input_line_pointer;
6794 demand_empty_rest_of_line ();
6797 /* Handle the MRI ENDF pseudo-op. */
6800 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6802 if (mri_control_stack == NULL
6803 || mri_control_stack->type != mri_for)
6805 as_bad (_("endf without for"));
6806 ignore_rest_of_line ();
6810 colon (mri_control_stack->next);
6812 mri_assemble (mri_control_stack->incr);
6814 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6815 mri_assemble (mri_control_stack->incr);
6817 free (mri_control_stack->incr);
6819 colon (mri_control_stack->bottom);
6825 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6826 ++input_line_pointer;
6829 demand_empty_rest_of_line ();
6832 /* Handle the MRI REPEAT pseudo-op. */
6835 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
6837 struct mri_control_info *n;
6839 n = push_mri_control (mri_repeat);
6843 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6844 ++input_line_pointer;
6846 demand_empty_rest_of_line ();
6849 /* Handle the MRI UNTIL pseudo-op. */
6852 s_mri_until (int qual)
6856 if (mri_control_stack == NULL
6857 || mri_control_stack->type != mri_repeat)
6859 as_bad (_("until without repeat"));
6860 ignore_rest_of_line ();
6864 colon (mri_control_stack->next);
6866 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6869 parse_mri_control_expression (s, qual, (const char *) NULL,
6870 mri_control_stack->top, '\0');
6872 colon (mri_control_stack->bottom);
6874 input_line_pointer = s;
6880 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6881 ++input_line_pointer;
6884 demand_empty_rest_of_line ();
6887 /* Handle the MRI WHILE pseudo-op. */
6890 s_mri_while (int qual)
6894 struct mri_control_info *n;
6896 s = input_line_pointer;
6897 /* We only accept '*' as introduction of comments if preceded by white space
6898 or at first column of a line (I think this can't actually happen here?)
6899 This is important when assembling:
6900 while d0 <ne> 12(a0,d0*2) do
6901 while d0 <ne> #CONST*20 do. */
6902 while (! (is_end_of_line[(unsigned char) *s]
6905 && (s == input_line_pointer
6907 || *(s-1) == '\t'))))
6910 while (*s == ' ' || *s == '\t')
6912 if (s - input_line_pointer > 1
6915 if (s - input_line_pointer < 2
6916 || strncasecmp (s - 1, "DO", 2) != 0)
6918 as_bad (_("missing do"));
6919 ignore_rest_of_line ();
6923 n = push_mri_control (mri_while);
6927 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6928 s[1] == '.' ? s[2] : '\0');
6930 input_line_pointer = s + 1;
6931 if (*input_line_pointer == '.')
6932 input_line_pointer += 2;
6936 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6937 ++input_line_pointer;
6940 demand_empty_rest_of_line ();
6943 /* Handle the MRI ENDW pseudo-op. */
6946 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
6950 if (mri_control_stack == NULL
6951 || mri_control_stack->type != mri_while)
6953 as_bad (_("endw without while"));
6954 ignore_rest_of_line ();
6958 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6959 sprintf (buf, "bra %s", mri_control_stack->next);
6963 colon (mri_control_stack->bottom);
6969 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6970 ++input_line_pointer;
6973 demand_empty_rest_of_line ();
6976 /* Parse a .cpu directive. */
6979 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6986 as_bad (_("already assembled instructions"));
6987 ignore_rest_of_line ();
6991 name = input_line_pointer;
6992 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6993 input_line_pointer++;
6994 saved_char = *input_line_pointer;
6995 *input_line_pointer = 0;
6997 m68k_set_cpu (name, 1, 0);
6999 *input_line_pointer = saved_char;
7000 demand_empty_rest_of_line ();
7004 /* Parse a .arch directive. */
7007 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7014 as_bad (_("already assembled instructions"));
7015 ignore_rest_of_line ();
7019 name = input_line_pointer;
7020 while (*input_line_pointer && *input_line_pointer != ','
7021 && !ISSPACE (*input_line_pointer))
7022 input_line_pointer++;
7023 saved_char = *input_line_pointer;
7024 *input_line_pointer = 0;
7026 if (m68k_set_arch (name, 1, 0))
7028 /* Scan extensions. */
7031 *input_line_pointer++ = saved_char;
7032 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7034 name = input_line_pointer;
7035 while (*input_line_pointer && *input_line_pointer != ','
7036 && !ISSPACE (*input_line_pointer))
7037 input_line_pointer++;
7038 saved_char = *input_line_pointer;
7039 *input_line_pointer = 0;
7041 while (m68k_set_extension (name, 1, 0));
7044 *input_line_pointer = saved_char;
7045 demand_empty_rest_of_line ();
7049 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7050 if none is found, the caller is responsible for emitting an error
7051 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7052 cpu name, if it begins with a '6' (possibly skipping an intervening
7053 'c'. We also allow a 'c' in the same place. if NEGATED is
7054 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7055 the option is indeed negated. */
7057 static const struct m68k_cpu *
7058 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7059 int allow_m, int *negated)
7061 /* allow negated value? */
7066 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7073 /* Remove 'm' or 'mc' prefix from 68k variants. */
7080 else if (arg[1] == 'c' && arg[2] == '6')
7084 else if (arg[0] == 'c' && arg[1] == '6')
7087 for (; table->name; table++)
7088 if (!strcmp (arg, table->name))
7090 if (table->alias < -1 || table->alias > 1)
7091 as_bad (_("`%s' is deprecated, use `%s'"),
7092 table->name, table[table->alias < 0 ? 1 : -1].name);
7098 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7101 m68k_set_cpu (char const *name, int allow_m, int silent)
7103 const struct m68k_cpu *cpu;
7105 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7110 as_bad (_("cpu `%s' unrecognized"), name);
7114 if (selected_cpu && selected_cpu != cpu)
7116 as_bad (_("already selected `%s' processor"),
7117 selected_cpu->name);
7124 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7127 m68k_set_arch (char const *name, int allow_m, int silent)
7129 const struct m68k_cpu *arch;
7131 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7136 as_bad (_("architecture `%s' unrecognized"), name);
7140 if (selected_arch && selected_arch != arch)
7142 as_bad (_("already selected `%s' architecture"),
7143 selected_arch->name);
7147 selected_arch = arch;
7151 /* Set the architecture extension, issuing errors if it is
7152 unrecognized, or invalid */
7155 m68k_set_extension (char const *name, int allow_m, int silent)
7158 const struct m68k_cpu *ext;
7160 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7165 as_bad (_("extension `%s' unrecognized"), name);
7170 not_current_architecture |= ext->arch;
7172 current_architecture |= ext->arch;
7177 Invocation line includes a switch not recognized by the base assembler.
7181 const char *md_shortopts = "lSA:m:kQ:V";
7183 const char *md_shortopts = "lSA:m:k";
7186 struct option md_longopts[] = {
7187 #define OPTION_PIC (OPTION_MD_BASE)
7188 {"pic", no_argument, NULL, OPTION_PIC},
7189 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7190 {"register-prefix-optional", no_argument, NULL,
7191 OPTION_REGISTER_PREFIX_OPTIONAL},
7192 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7193 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7194 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7195 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7196 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7197 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7198 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7199 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7200 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7201 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7202 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7203 {"pcrel", no_argument, NULL, OPTION_PCREL},
7204 {NULL, no_argument, NULL, 0}
7206 size_t md_longopts_size = sizeof (md_longopts);
7209 md_parse_option (int c, char *arg)
7213 case 'l': /* -l means keep external to 2 bit offset
7214 rather than 16 bit one. */
7215 flag_short_refs = 1;
7218 case 'S': /* -S means that jbsr's always turn into
7220 flag_long_jumps = 1;
7223 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7224 branches into absolute jumps. */
7225 flag_keep_pcrel = 1;
7231 break; /* -pic, Position Independent Code. */
7233 case OPTION_REGISTER_PREFIX_OPTIONAL:
7234 flag_reg_prefix_optional = 1;
7235 reg_prefix_optional_seen = 1;
7238 /* -V: SVR4 argument to print version ID. */
7240 print_version_id ();
7243 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7244 should be emitted or not. FIXME: Not implemented. */
7248 case OPTION_BITWISE_OR:
7253 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7255 for (s = m68k_comment_chars; *s != '\0'; s++)
7259 m68k_comment_chars = n;
7263 case OPTION_BASE_SIZE_DEFAULT_16:
7264 m68k_index_width_default = SIZE_WORD;
7267 case OPTION_BASE_SIZE_DEFAULT_32:
7268 m68k_index_width_default = SIZE_LONG;
7271 case OPTION_DISP_SIZE_DEFAULT_16:
7273 m68k_rel32_from_cmdline = 1;
7276 case OPTION_DISP_SIZE_DEFAULT_32:
7278 m68k_rel32_from_cmdline = 1;
7283 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7286 /* Intentional fall-through. */
7288 if (!strncmp (arg, "arch=", 5))
7289 m68k_set_arch (arg + 5, 1, 0);
7290 else if (!strncmp (arg, "cpu=", 4))
7291 m68k_set_cpu (arg + 4, 1, 0);
7292 else if (m68k_set_extension (arg, 0, 1))
7294 else if (m68k_set_arch (arg, 0, 1))
7296 else if (m68k_set_cpu (arg, 0, 1))
7309 /* Setup tables from the selected arch and/or cpu */
7312 m68k_init_arch (void)
7314 if (not_current_architecture & current_architecture)
7316 as_bad (_("architecture features both enabled and disabled"));
7317 not_current_architecture &= ~current_architecture;
7321 current_architecture |= selected_arch->arch;
7322 control_regs = selected_arch->control_regs;
7325 current_architecture |= selected_cpu->arch;
7327 current_architecture &= ~not_current_architecture;
7329 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7331 /* Determine which float is really meant. */
7332 if (current_architecture & (m68k_mask & ~m68881))
7333 current_architecture ^= cfloat;
7335 current_architecture ^= m68881;
7340 control_regs = selected_cpu->control_regs;
7341 if (current_architecture & ~selected_cpu->arch)
7343 as_bad (_("selected processor does not have all features of selected architecture"));
7344 current_architecture
7345 = selected_cpu->arch & ~not_current_architecture;
7349 if ((current_architecture & m68k_mask)
7350 && (current_architecture & ~m68k_mask))
7352 as_bad (_ ("m68k and cf features both selected"));
7353 if (current_architecture & m68k_mask)
7354 current_architecture &= m68k_mask;
7356 current_architecture &= ~m68k_mask;
7359 /* Permit m68881 specification with all cpus; those that can't work
7360 with a coprocessor could be doing emulation. */
7361 if (current_architecture & m68851)
7363 if (current_architecture & m68040)
7364 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7366 /* What other incompatibilities could we check for? */
7368 if (cpu_of_arch (current_architecture) < m68020
7369 || arch_coldfire_p (current_architecture))
7370 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7376 md_show_usage (FILE *stream)
7378 const char *default_cpu = TARGET_CPU;
7380 unsigned int default_arch;
7382 /* Get the canonical name for the default target CPU. */
7383 if (*default_cpu == 'm')
7385 for (i = 0; m68k_cpus[i].name; i++)
7387 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7389 default_arch = m68k_cpus[i].arch;
7390 while (m68k_cpus[i].alias > 0)
7392 while (m68k_cpus[i].alias < 0)
7394 default_cpu = m68k_cpus[i].name;
7398 fprintf (stream, _("\
7399 -march=<arch> set architecture\n\
7400 -mcpu=<cpu> set cpu [default %s]\n\
7402 for (i = 0; m68k_extensions[i].name; i++)
7403 fprintf (stream, _("\
7404 -m[no-]%-16s enable/disable%s architecture extension\n\
7405 "), m68k_extensions[i].name,
7406 m68k_extensions[i].alias > 0 ? " ColdFire"
7407 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7409 fprintf (stream, _("\
7410 -l use 1 word for refs to undefined symbols [default 2]\n\
7411 -pic, -k generate position independent code\n\
7412 -S turn jbsr into jsr\n\
7413 --pcrel never turn PC-relative branches into absolute jumps\n\
7414 --register-prefix-optional\n\
7415 recognize register names without prefix character\n\
7416 --bitwise-or do not treat `|' as a comment character\n\
7417 --base-size-default-16 base reg without size is 16 bits\n\
7418 --base-size-default-32 base reg without size is 32 bits (default)\n\
7419 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7420 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7423 fprintf (stream, _("Architecture variants are: "));
7424 for (i = 0; m68k_archs[i].name; i++)
7427 fprintf (stream, " | ");
7428 fprintf (stream, m68k_archs[i].name);
7430 fprintf (stream, "\n");
7432 fprintf (stream, _("Processor variants are: "));
7433 for (i = 0; m68k_cpus[i].name; i++)
7436 fprintf (stream, " | ");
7437 fprintf (stream, m68k_cpus[i].name);
7439 fprintf (stream, _("\n"));
7444 /* TEST2: Test md_assemble() */
7445 /* Warning, this routine probably doesn't work anymore. */
7449 struct m68k_it the_ins;
7457 if (!gets (buf) || !*buf)
7459 if (buf[0] == '|' || buf[1] == '.')
7461 for (cp = buf; *cp; cp++)
7466 memset (&the_ins, '\0', sizeof (the_ins));
7467 m68k_ip (&the_ins, buf);
7470 printf (_("Error %s in %s\n"), the_ins.error, buf);
7474 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7475 for (n = 0; n < the_ins.numo; n++)
7476 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7478 print_the_insn (&the_ins.opcode[0], stdout);
7479 (void) putchar ('\n');
7481 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7483 if (the_ins.operands[n].error)
7485 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7488 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7489 the_ins.operands[n].reg);
7490 if (the_ins.operands[n].b_const)
7491 printf ("Constant: '%.*s', ",
7492 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7493 the_ins.operands[n].b_const);
7494 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7495 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7496 if (the_ins.operands[n].b_iadd)
7497 printf ("Iadd: '%.*s',",
7498 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7499 the_ins.operands[n].b_iadd);
7508 is_label (char *str)
7512 while (*str && *str != ' ')
7514 if (str[-1] == ':' || str[1] == '=')
7521 /* Possible states for relaxation:
7523 0 0 branch offset byte (bra, etc)
7527 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7531 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7538 /* We have no need to default values of symbols. */
7541 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7546 /* Round up a section size to the appropriate boundary. */
7548 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7551 /* For a.out, force the section size to be aligned. If we don't do
7552 this, BFD will align it for us, but it will not write out the
7553 final bytes of the section. This may be a bug in BFD, but it is
7554 easier to fix it here since that is how the other a.out targets
7558 align = bfd_get_section_alignment (stdoutput, segment);
7559 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7565 /* Exactly what point is a PC-relative offset relative TO?
7566 On the 68k, it is relative to the address of the first extension
7567 word. The difference between the addresses of the offset and the
7568 first extension word is stored in fx_pcrel_adjust. */
7570 md_pcrel_from (fixS *fixP)
7574 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7575 sign extend the value here. */
7576 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7579 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7584 m68k_elf_final_processing (void)
7588 if (arch_coldfire_fpu (current_architecture))
7589 flags |= EF_M68K_CFV4E;
7590 /* Set file-specific flags if this is a cpu32 processor. */
7591 if (cpu_of_arch (current_architecture) & cpu32)
7592 flags |= EF_M68K_CPU32;
7593 else if (cpu_of_arch (current_architecture) & fido_a)
7594 flags |= EF_M68K_FIDO;
7595 else if ((cpu_of_arch (current_architecture) & m68000up)
7596 && !(cpu_of_arch (current_architecture) & m68020up))
7597 flags |= EF_M68K_M68000;
7599 if (current_architecture & mcfisa_a)
7601 static const unsigned isa_features[][2] =
7603 {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
7604 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7605 {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7606 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7607 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7610 static const unsigned mac_features[][2] =
7612 {EF_M68K_CF_MAC, mcfmac},
7613 {EF_M68K_CF_EMAC, mcfemac},
7619 pattern = (current_architecture
7620 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7621 for (ix = 0; isa_features[ix][1]; ix++)
7623 if (pattern == isa_features[ix][1])
7625 flags |= isa_features[ix][0];
7629 if (!isa_features[ix][1])
7632 as_warn (_("Not a defined coldfire architecture"));
7636 if (current_architecture & cfloat)
7637 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7639 pattern = current_architecture & (mcfmac|mcfemac);
7642 for (ix = 0; mac_features[ix][1]; ix++)
7644 if (pattern == mac_features[ix][1])
7646 flags |= mac_features[ix][0];
7650 if (!mac_features[ix][1])
7655 elf_elfheader (stdoutput)->e_flags |= flags;
7660 tc_m68k_regname_to_dw2regnum (char *regname)
7662 unsigned int regnum;
7663 static const char *const regnames[] =
7665 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7666 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7667 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7671 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7672 if (strcmp (regname, regnames[regnum]) == 0)
7679 tc_m68k_frame_initial_instructions (void)
7681 static int sp_regno = -1;
7684 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7686 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7687 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);