1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
29 /* This array holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful */
32 CONST char comment_chars[] = "|#";
34 CONST char comment_chars[] = "|";
37 /* This array holds the chars that only start a comment at the beginning of
38 a line. If the line seems to have the form '# 123 filename'
39 .line and .file directives will appear in the pre-processed output */
40 /* Note that input_file.c hand checks for '#' at the beginning of the
41 first line of the input file. This is because the compiler outputs
42 #NO_APP at the beginning of its output. */
43 /* Also note that comments like this one will always work. */
44 CONST char line_comment_chars[] = "#";
46 CONST char line_separator_chars[] = "";
48 /* Chars that can be used to separate mant from exp in floating point nums */
49 CONST char EXP_CHARS[] = "eE";
51 /* Chars that mean this number is a floating point constant, as
52 in "0f12.456" or "0d1.2345e12". */
54 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
56 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
57 changed in read.c . Ideally it shouldn't have to know about it at all,
58 but nothing is ideal around here. */
60 const int md_reloc_size = 8; /* Size of relocation record */
62 /* Are we trying to generate PIC code? If so, absolute references
63 ought to be made into linkage table references or pc-relative
67 static int flag_short_refs; /* -l option */
68 static int flag_long_jumps; /* -S option */
70 #ifdef REGISTER_PREFIX_OPTIONAL
71 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73 int flag_reg_prefix_optional;
76 /* The floating point coprocessor to use by default. */
77 static enum m68k_register m68k_float_copnum = COP1;
79 /* If this is non-zero, then references to number(%pc) will be taken
80 to refer to number, rather than to %pc + number. */
81 static int m68k_abspcadd;
83 /* If this is non-zero, then the quick forms of the move, add, and sub
84 instructions are used when possible. */
85 static int m68k_quick = 1;
87 /* If this is non-zero, then if the size is not specified for a base
88 or outer displacement, the assembler assumes that the size should
90 static int m68k_rel32 = 1;
92 /* Its an arbitrary name: This means I don't approve of it */
93 /* See flames below */
94 static struct obstack robyn;
96 #define TAB(x,y) (((x)<<2)+(y))
97 #define TABTYPE(xy) ((xy) >> 2)
103 /* Case `g' except when BCC68000 is applicable. */
105 /* Coprocessor branches. */
107 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
108 supported on all cpus. Widens to 32-bit absolute. */
110 /* For inserting an extra jmp instruction with long offset on 68000,
111 for expanding conditional branches. (Not bsr or bra.) Since the
112 68000 doesn't support 32-bit displacements for conditional
113 branches, we fake it by reversing the condition and branching
114 around a jmp with an absolute long operand. */
116 /* For the DBcc "instructions". If the displacement requires 32 bits,
117 the branch-around-a-jump game is played here too. */
119 /* Not currently used? */
121 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
127 const char *m_operands;
128 unsigned long m_opcode;
132 struct m68k_incant *m_next;
135 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
136 #define gettwo(x) (((x)->m_opcode)&0xffff)
138 static const enum m68k_register m68000_control_regs[] = { 0 };
139 static const enum m68k_register m68010_control_regs[] = {
143 static const enum m68k_register m68020_control_regs[] = {
144 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
147 static const enum m68k_register m68040_control_regs[] = {
148 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
149 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
152 static const enum m68k_register m68060_control_regs[] = {
153 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
154 USP, VBR, URP, SRP, PCR,
157 #define cpu32_control_regs m68010_control_regs
159 static const enum m68k_register *control_regs;
161 /* internal form of a 68020 instruction */
165 const char *args; /* list of opcode info */
168 int numo; /* Number of shorts in opcode */
171 struct m68k_op operands[6];
173 int nexp; /* number of exprs in use */
174 struct m68k_exp exprs[4];
176 int nfrag; /* Number of frags we have to produce */
179 int fragoff; /* Where in the current opcode the frag ends */
186 int nrel; /* Num of reloc strucs in use */
193 /* In a pc relative address the difference between the address
194 of the offset and the address that the offset is relative
195 to. This depends on the addressing mode. Basically this
196 is the value to put in the offset field to address the
197 first byte of the offset, without regarding the special
198 significance of some values (in the branch instruction, for
202 reloc[5]; /* Five is enough??? */
205 #define cpu_of_arch(x) ((x) & m68000up)
206 #define float_of_arch(x) ((x) & mfloat)
207 #define mmu_of_arch(x) ((x) & mmmu)
209 static struct m68k_it the_ins; /* the instruction being assembled */
211 #define op(ex) ((ex)->exp.X_op)
212 #define adds(ex) ((ex)->exp.X_add_symbol)
213 #define subs(ex) ((ex)->exp.X_op_symbol)
214 #define offs(ex) ((ex)->exp.X_add_number)
216 /* Macros for adding things to the m68k_it struct */
218 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
220 /* Like addword, but goes BEFORE general operands */
224 struct m68k_incant *opcode;
227 for(z=the_ins.numo;z>opcode->m_codenum;--z)
228 the_ins.opcode[z]=the_ins.opcode[z-1];
229 for(z=0;z<the_ins.nrel;z++)
230 the_ins.reloc[z].n+=2;
231 for (z = 0; z < the_ins.nfrag; z++)
232 the_ins.fragb[z].fragoff++;
233 the_ins.opcode[opcode->m_codenum]=w;
237 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
240 add_fix (width, exp, pc_rel, pc_fix)
242 struct m68k_exp *exp;
246 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
250 : (the_ins.numo*2)));
251 the_ins.reloc[the_ins.nrel].exp = exp->exp;
252 the_ins.reloc[the_ins.nrel].wid = width;
253 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
254 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
257 /* Cause an extra frag to be generated here, inserting up to 10 bytes
258 (that value is chosen in the frag_var call in md_assemble). TYPE
259 is the subtype of the frag to be generated; its primary type is
260 rs_machine_dependent.
262 The TYPE parameter is also used by md_convert_frag_1 and
263 md_estimate_size_before_relax. The appropriate type of fixup will
264 be emitted by md_convert_frag_1.
266 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
268 add_frag(add,off,type)
273 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
274 the_ins.fragb[the_ins.nfrag].fadd=add;
275 the_ins.fragb[the_ins.nfrag].foff=off;
276 the_ins.fragb[the_ins.nfrag++].fragty=type;
280 (op (ex) != O_constant && op (ex) != O_big)
282 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
283 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
284 static int reverse_16_bits PARAMS ((int in));
285 static int reverse_8_bits PARAMS ((int in));
286 static void install_gen_operand PARAMS ((int mode, int val));
287 static void install_operand PARAMS ((int mode, int val));
288 static void s_bss PARAMS ((int));
289 static void s_data1 PARAMS ((int));
290 static void s_data2 PARAMS ((int));
291 static void s_even PARAMS ((int));
292 static void s_proc PARAMS ((int));
293 static void mri_chip PARAMS ((void));
294 static void s_chip PARAMS ((int));
295 static void s_fopt PARAMS ((int));
296 static void s_opt PARAMS ((int));
297 static void s_reg PARAMS ((int));
299 static int current_architecture;
306 static const struct m68k_cpu archs[] = {
316 /* Aliases (effectively, so far as gas is concerned) for the above
321 { m68000, "68ec000" },
322 { m68000, "68hc000" },
323 { m68000, "68hc001" },
324 { m68020, "68ec020" },
325 { m68030, "68ec030" },
326 { m68040, "68ec040" },
336 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
338 /* BCC68000 is for patching in an extra jmp instruction for long offsets
339 on the 68000. The 68000 doesn't support long branches with branchs */
341 /* This table desribes how you change sizes for the various types of variable
342 size expressions. This version only supports two kinds. */
344 /* Note that calls to frag_var need to specify the maximum expansion
345 needed; this is currently 10 bytes for DBCC. */
348 How far Forward this mode will reach:
349 How far Backward this mode will reach:
350 How many bytes this mode will add to the size of the frag
351 Which mode to go to if the offset won't fit in this one
353 relax_typeS md_relax_table[] =
355 {1, 1, 0, 0}, /* First entries aren't used */
356 {1, 1, 0, 0}, /* For no good reason except */
357 {1, 1, 0, 0}, /* that the VAX doesn't either */
360 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
361 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
365 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
366 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
370 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
371 {(32767), (-32768), 2, TAB (PCREL, LONG)},
375 {(127), (-128), 0, TAB (BCC68000, SHORT)},
376 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
377 {0, 0, 6, 0}, /* jmp long space */
380 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
381 {(32767), (-32768), 2, TAB (DBCC, LONG)},
382 {0, 0, 10, 0}, /* bra/jmp long space */
385 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
386 {32767, -32768, 2, TAB (PCLEA, LONG)},
390 /* For, e.g., jmp pcrel indexed. */
391 {125, -130, 0, TAB (PCINDEX, SHORT)},
392 {32765, -32770, 2, TAB (PCINDEX, LONG)},
397 /* These are the machine dependent pseudo-ops. These are included so
398 the assembler can work on the output from the SUN C compiler, which
402 /* This table describes all the machine specific pseudo-ops the assembler
403 has to support. The fields are:
404 pseudo-op name without dot
405 function to call to execute this pseudo-op
406 Integer arg to pass to the function
408 CONST pseudo_typeS md_pseudo_table[] =
410 {"data1", s_data1, 0},
411 {"data2", s_data2, 0},
414 {"skip", s_space, 0},
417 {"align", s_align_bytes, 0},
420 {"swbeg", s_ignore, 0},
423 /* The following pseudo-ops are supported for MRI compatibility. */
425 {"comline", s_space, 1},
427 {"mask2", s_ignore, 0},
435 /* The mote pseudo ops are put into the opcode table, since they
436 don't start with a . they look like opcodes to gas.
438 extern void obj_coff_section ();
440 CONST pseudo_typeS mote_pseudo_table[] =
453 {"xdef", s_globl, 0},
454 {"align", s_align_ptwo, 0},
456 {"sect", obj_coff_section, 0},
457 {"section", obj_coff_section, 0},
462 #define issbyte(x) ((x)>=-128 && (x)<=127)
463 #define isubyte(x) ((x)>=0 && (x)<=255)
464 #define issword(x) ((x)>=-32768 && (x)<=32767)
465 #define isuword(x) ((x)>=0 && (x)<=65535)
467 #define isbyte(x) ((x)>= -255 && (x)<=255)
468 #define isword(x) ((x)>=-32768 && (x)<=65535)
469 #define islong(x) (1)
471 extern char *input_line_pointer;
473 static char mklower_table[256];
474 #define mklower(c) (mklower_table[(unsigned char)(c)])
475 static char notend_table[256];
476 static char alt_notend_table[256];
478 (! (notend_table[(unsigned char) *s] \
480 && alt_notend_table[(unsigned char) s[1]])))
482 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
484 #ifdef NO_PCREL_RELOCS
487 make_pcrel_absolute(fixP, add_number)
491 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
493 /* rewrite the PC relative instructions to absolute address ones.
494 * these are rumoured to be faster, and the apollo linker refuses
495 * to deal with the PC relative relocations.
497 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
502 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
508 as_fatal ("Unknown PC relative instruction");
513 #endif /* NO_PCREL_RELOCS */
516 tc_coff_fix2rtype (fixP)
519 #ifdef NO_PCREL_RELOCS
520 know (fixP->fx_pcrel == 0);
521 return (fixP->fx_size == 1 ? R_RELBYTE
522 : fixP->fx_size == 2 ? R_DIR16
525 return (fixP->fx_pcrel ?
526 (fixP->fx_size == 1 ? R_PCRBYTE :
527 fixP->fx_size == 2 ? R_PCRWORD :
529 (fixP->fx_size == 1 ? R_RELBYTE :
530 fixP->fx_size == 2 ? R_RELWORD :
540 tc_gen_reloc (section, fixp)
545 bfd_reloc_code_real_type code;
547 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
548 switch (F (fixp->fx_size, fixp->fx_pcrel))
550 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
551 MAP (1, 0, BFD_RELOC_8);
552 MAP (2, 0, BFD_RELOC_16);
553 MAP (4, 0, BFD_RELOC_32);
554 MAP (1, 1, BFD_RELOC_8_PCREL);
555 MAP (2, 1, BFD_RELOC_16_PCREL);
556 MAP (4, 1, BFD_RELOC_32_PCREL);
561 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
563 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
564 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
566 reloc->addend = fixp->fx_addnumber;
570 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
571 assert (reloc->howto != 0);
576 #endif /* BFD_ASSEMBLER */
578 /* Handle of the OPCODE hash table. NULL means any use before
579 m68k_ip_begin() will crash. */
580 static struct hash_control *op_hash;
582 /* Assemble an m68k instruction. */
589 register struct m68k_op *opP;
590 register struct m68k_incant *opcode;
591 register const char *s;
592 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
593 char *pdot, *pdotmove;
594 enum m68k_size siz1, siz2;
598 char *crack_operand ();
599 LITTLENUM_TYPE words[6];
600 LITTLENUM_TYPE *wordp;
601 unsigned long ok_arch = 0;
603 if (*instring == ' ')
604 instring++; /* skip leading whitespace */
606 /* Scan up to end of operation-code, which MUST end in end-of-string
607 or exactly 1 space. */
609 for (p = instring; *p != '\0'; p++)
619 the_ins.error = "No operator";
623 /* p now points to the end of the opcode name, probably whitespace.
624 Make sure the name is null terminated by clobbering the
625 whitespace, look it up in the hash table, then fix it back.
626 Remove a dot, first, since the opcode tables have none. */
629 for (pdotmove = pdot; pdotmove < p; pdotmove++)
630 *pdotmove = pdotmove[1];
636 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
641 for (pdotmove = p; pdotmove > pdot; pdotmove--)
642 *pdotmove = pdotmove[-1];
649 the_ins.error = "Unknown operator";
653 /* found a legitimate opcode, start matching operands */
657 if (opcode->m_operands == 0)
659 char *old = input_line_pointer;
661 input_line_pointer = p;
662 /* Ahh - it's a motorola style psuedo op */
663 mote_pseudo_table[opcode->m_opnum].poc_handler
664 (mote_pseudo_table[opcode->m_opnum].poc_val);
665 input_line_pointer = old;
671 for (opP = &the_ins.operands[0]; *p; opP++)
673 p = crack_operand (p, opP);
677 the_ins.error = opP->error;
682 opsfound = opP - &the_ins.operands[0];
684 /* This ugly hack is to support the floating pt opcodes in their
685 standard form. Essentially, we fake a first enty of type COP#1 */
686 if (opcode->m_operands[0] == 'I')
690 for (n = opsfound; n > 0; --n)
691 the_ins.operands[n] = the_ins.operands[n - 1];
693 memset ((char *) (&the_ins.operands[0]), '\0',
694 sizeof (the_ins.operands[0]));
695 the_ins.operands[0].mode = CONTROL;
696 the_ins.operands[0].reg = m68k_float_copnum;
700 /* We've got the operands. Find an opcode that'll accept them */
703 /* If we didn't get the right number of ops, or we have no
704 common model with this pattern then reject this pattern. */
706 if (opsfound != opcode->m_opnum
707 || ((opcode->m_arch & current_architecture) == 0))
710 ok_arch |= opcode->m_arch;
714 for (s = opcode->m_operands, opP = &the_ins.operands[0];
718 /* Warning: this switch is huge! */
719 /* I've tried to organize the cases into this order:
720 non-alpha first, then alpha by letter. Lower-case
721 goes directly before uppercase counterpart. */
722 /* Code with multiple case ...: gets sorted by the lowest
723 case ... it belongs to. I hope this makes sense. */
763 if (opP->mode != IMMED)
766 && ! isvar (&opP->disp)
767 && ! expr8 (&opP->disp))
770 && ! isvar (&opP->disp)
771 && ! expr16 (&opP->disp))
777 if (opP->mode != IMMED)
782 if (opP->mode == AREG
783 || opP->mode == CONTROL
784 || opP->mode == FPREG
785 || opP->mode == IMMED
786 || opP->mode == REGLST
787 || (opP->mode != ABSL
789 || opP->reg == ZPC)))
794 if (opP->mode == CONTROL
795 || opP->mode == FPREG
796 || opP->mode == REGLST
797 || (opP->mode != ABSL
798 && opP->mode != IMMED
800 || opP->reg == ZPC)))
828 if (opP->mode == CONTROL
829 || opP->mode == FPREG
830 || opP->mode == REGLST)
835 if (opP->mode != AINC)
840 if (opP->mode != ADEC)
890 if (opP->reg == PC || opP->reg == ZPC)
911 case '~': /* For now! (JF FOO is this right?) */
933 if (opP->mode != CONTROL
934 || (opP->reg != TT0 && opP->reg != TT1))
939 if (opP->mode != AREG)
944 if (opP->mode != AINDR)
949 if (opP->mode != ABSL
951 && strncmp (instring, "jbsr", 4) == 0))
956 if (opP->mode != CONTROL || opP->reg != CCR)
961 if (opP->mode != DISP
968 if (opP->mode != DREG)
973 if (opP->mode != FPREG)
978 if (opP->mode != CONTROL
985 if (opP->mode != CONTROL
987 || opP->reg > last_movec_reg)
991 const enum m68k_register *rp;
992 for (rp = control_regs; *rp; rp++)
1001 if (opP->mode != IMMED)
1007 if (opP->mode == DREG
1008 || opP->mode == AREG
1009 || opP->mode == FPREG)
1018 opP->mask = 1 << (opP->reg - DATA0);
1021 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1024 opP->mask = 1 << (opP->reg - FP0 + 16);
1032 else if (opP->mode == CONTROL)
1041 opP->mask = 1 << 24;
1044 opP->mask = 1 << 25;
1047 opP->mask = 1 << 26;
1056 else if (opP->mode == ABSL
1057 && opP->disp.size == SIZE_UNSPEC
1058 && opP->disp.exp.X_op == O_constant)
1060 /* This is what the MRI REG pseudo-op generates. */
1062 opP->mask = opP->disp.exp.X_add_number;
1064 else if (opP->mode != REGLST)
1066 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1068 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1073 if (opP->mode != IMMED)
1075 else if (! expr8 (&opP->disp))
1077 else if (! m68k_quick
1078 && instring[3] != 'q'
1079 && instring[4] != 'q')
1084 if (opP->mode != DREG && opP->mode != IMMED)
1089 if (opP->mode != IMMED)
1091 else if (! expr8 (&opP->disp)
1092 || opP->disp.exp.X_add_number < 1
1093 || opP->disp.exp.X_add_number > 8)
1095 else if (! m68k_quick
1096 && (strncmp (instring, "add", 3) == 0
1097 || strncmp (instring, "sub", 3) == 0)
1098 && instring[3] != 'q')
1103 if (opP->mode != DREG && opP->mode != AREG)
1108 if (opP->mode != AINDR
1109 && (opP->mode != BASE
1111 && opP->reg != ZADDR0)
1112 || opP->disp.exp.X_op != O_absent
1113 || ((opP->index.reg < DATA0
1114 || opP->index.reg > DATA7)
1115 && (opP->index.reg < ADDR0
1116 || opP->index.reg > ADDR7))
1117 || opP->index.size != SIZE_UNSPEC
1118 || opP->index.scale != 1))
1123 if (opP->mode != CONTROL
1124 || ! (opP->reg == FPI
1126 || opP->reg == FPC))
1131 if (opP->mode != CONTROL || opP->reg != SR)
1136 if (opP->mode != IMMED)
1138 else if (! expr8 (&opP->disp)
1139 || opP->disp.exp.X_add_number < 0
1140 || opP->disp.exp.X_add_number > 7)
1145 if (opP->mode != CONTROL || opP->reg != USP)
1149 /* JF these are out of order. We could put them
1150 in order if we were willing to put up with
1151 bunches of #ifdef m68851s in the code.
1153 Don't forget that you need these operands
1154 to use 68030 MMU instructions. */
1156 /* Memory addressing mode used by pflushr */
1158 if (opP->mode == CONTROL
1159 || opP->mode == FPREG
1160 || opP->mode == DREG
1161 || opP->mode == AREG
1162 || opP->mode == REGLST)
1167 if (opP->mode != CONTROL
1168 || (opP->reg != SFC && opP->reg != DFC))
1173 if (opP->mode != CONTROL
1183 if (opP->mode != CONTROL
1189 if (opP->mode != CONTROL
1192 && opP->reg != CRP))
1197 if (opP->mode != CONTROL
1198 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1199 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1204 if (opP->mode != CONTROL || opP->reg != PSR)
1209 if (opP->mode != CONTROL || opP->reg != PCSR)
1214 if (opP->mode != CONTROL
1221 } /* not a cache specifier. */
1225 if (opP->mode != ABSL)
1231 } /* switch on type of operand */
1235 } /* for each operand */
1236 } /* if immediately wrong */
1243 opcode = opcode->m_next;
1248 && !(ok_arch & current_architecture))
1253 "invalid instruction for this architecture; needs ");
1254 cp = buf + strlen (buf);
1258 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1261 strcpy (cp, "mmu (68030 or 68851)");
1264 strcpy (cp, "68020 or higher");
1267 strcpy (cp, "68000 or higher");
1270 strcpy (cp, "68010 or higher");
1274 int got_one = 0, idx;
1275 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1278 if (archs[idx].arch & ok_arch)
1282 strcpy (cp, " or ");
1286 strcpy (cp, archs[idx].name);
1298 the_ins.error = "operands mismatch";
1300 } /* Fell off the end */
1305 /* now assemble it */
1307 the_ins.args = opcode->m_operands;
1308 the_ins.numargs = opcode->m_opnum;
1309 the_ins.numo = opcode->m_codenum;
1310 the_ins.opcode[0] = getone (opcode);
1311 the_ins.opcode[1] = gettwo (opcode);
1313 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1315 /* This switch is a doozy.
1316 Watch the first step; its a big one! */
1337 tmpreg = 0x3c; /* 7.4 */
1338 if (strchr ("bwl", s[1]))
1339 nextword = get_num (&opP->disp, 80);
1341 nextword = get_num (&opP->disp, 0);
1342 if (isvar (&opP->disp))
1343 add_fix (s[1], &opP->disp, 0, 0);
1347 if (!isbyte (nextword))
1348 opP->error = "operand out of range";
1353 if (!isword (nextword))
1354 opP->error = "operand out of range";
1359 addword (nextword >> 16);
1386 /* We gotta put out some float */
1387 if (op (&opP->disp) != O_big)
1392 /* Can other cases happen here? */
1393 if (op (&opP->disp) != O_constant)
1396 val = (valueT) offs (&opP->disp);
1400 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1401 val >>= LITTLENUM_NUMBER_OF_BITS;
1405 offs (&opP->disp) = gencnt;
1407 if (offs (&opP->disp) > 0)
1409 if (offs (&opP->disp) > baseo)
1411 as_warn ("Bignum too big for %c format; truncated",
1413 offs (&opP->disp) = baseo;
1415 baseo -= offs (&opP->disp);
1418 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1419 offs (&opP->disp)--;
1424 gen_to_words (words, baseo, (long) outro);
1425 for (wordp = words; baseo--; wordp++)
1429 tmpreg = opP->reg - DATA; /* 0.dreg */
1432 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1435 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1438 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1441 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1445 nextword = get_num (&opP->disp, 80);
1448 && ! isvar (&opP->disp)
1451 opP->disp.exp.X_op = O_symbol;
1452 #ifndef BFD_ASSEMBLER
1453 opP->disp.exp.X_add_symbol = &abs_symbol;
1455 opP->disp.exp.X_add_symbol =
1456 section_symbol (absolute_section);
1460 /* Force into index mode. Hope this works */
1462 /* We do the first bit for 32-bit displacements, and the
1463 second bit for 16 bit ones. It is possible that we
1464 should make the default be WORD instead of LONG, but
1465 I think that'd break GCC, so we put up with a little
1466 inefficiency for the sake of working output. */
1468 if (!issword (nextword)
1469 || (isvar (&opP->disp)
1470 && ((opP->disp.size == SIZE_UNSPEC
1471 && flag_short_refs == 0
1472 && cpu_of_arch (current_architecture) >= m68020)
1473 || opP->disp.size == SIZE_LONG)))
1476 tmpreg = 0x3B; /* 7.3 */
1478 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1479 if (isvar (&opP->disp))
1485 add_fix ('l', &opP->disp, 1, 2);
1486 addword (0), addword (0);
1488 add_frag (adds (&opP->disp),
1490 TAB (PCLEA, SZ_UNDEF));
1497 add_fix ('l', &opP->disp, 0, 0);
1502 addword (nextword >> 16);
1507 tmpreg = 0x3A; /* 7.2 */
1509 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1511 if (isvar (&opP->disp))
1515 add_fix ('w', &opP->disp, 1, 0);
1518 add_fix ('w', &opP->disp, 0, 0);
1528 baseo = get_num (&opP->disp, 80);
1529 if (opP->mode == POST || opP->mode == PRE)
1530 outro = get_num (&opP->odisp, 80);
1531 /* Figure out the `addressing mode'.
1532 Also turn on the BASE_DISABLE bit, if needed. */
1533 if (opP->reg == PC || opP->reg == ZPC)
1535 tmpreg = 0x3b; /* 7.3 */
1536 if (opP->reg == ZPC)
1539 else if (opP->reg == 0)
1542 tmpreg = 0x30; /* 6.garbage */
1544 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1547 tmpreg = 0x30 + opP->reg - ZADDR0;
1550 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1552 siz1 = opP->disp.size;
1553 if (opP->mode == POST || opP->mode == PRE)
1554 siz2 = opP->odisp.size;
1558 /* Index register stuff */
1559 if (opP->index.reg != 0
1560 && opP->index.reg >= DATA
1561 && opP->index.reg <= ADDR7)
1563 nextword |= (opP->index.reg - DATA) << 12;
1565 if (opP->index.size == SIZE_UNSPEC
1566 || opP->index.size == SIZE_LONG)
1569 if (cpu_of_arch (current_architecture) < m68020)
1571 if (opP->index.scale != 1)
1574 "scale factor invalid on this architecture; needs 68020 or higher";
1578 switch (opP->index.scale)
1595 GET US OUT OF HERE! */
1597 /* Must be INDEX, with an index register. Address
1598 register cannot be ZERO-PC, and either :b was
1599 forced, or we know it will fit. For a 68000 or
1600 68010, force this mode anyways, because the
1601 larger modes aren't supported. */
1602 if (opP->mode == BASE
1603 && ((opP->reg >= ADDR0
1604 && opP->reg <= ADDR7)
1607 if (siz1 == SIZE_BYTE
1608 || cpu_of_arch (current_architecture) < m68020
1609 || (siz1 == SIZE_UNSPEC
1610 && ! isvar (&opP->disp)
1611 && issbyte (baseo)))
1613 nextword += baseo & 0xff;
1615 if (isvar (&opP->disp))
1617 /* Do a byte relocation. If it doesn't
1618 fit (possible on m68000) let the
1619 fixup processing complain later. */
1621 add_fix ('B', &opP->disp, 1, 1);
1623 add_fix ('B', &opP->disp, 0, 0);
1625 else if (siz1 != SIZE_BYTE)
1627 if (siz1 != SIZE_UNSPEC)
1628 as_warn ("Forcing byte displacement");
1629 if (! issbyte (baseo))
1630 opP->error = "byte displacement out of range";
1635 else if (siz1 == SIZE_UNSPEC
1637 && isvar (&opP->disp)
1638 && subs (&opP->disp) == NULL)
1640 nextword += baseo & 0xff;
1642 add_frag (adds (&opP->disp), offs (&opP->disp),
1643 TAB (PCINDEX, SZ_UNDEF));
1651 nextword |= 0x40; /* No index reg */
1652 if (opP->index.reg >= ZDATA0
1653 && opP->index.reg <= ZDATA7)
1654 nextword |= (opP->index.reg - ZDATA0) << 12;
1655 else if (opP->index.reg >= ZADDR0
1656 || opP->index.reg <= ZADDR7)
1657 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1660 /* It isn't simple. */
1662 if (cpu_of_arch (current_architecture) < m68020)
1664 "invalid operand mode for this architecture; needs 68020 or higher";
1667 /* If the guy specified a width, we assume that it is
1668 wide enough. Maybe it isn't. If so, we lose. */
1672 if (isvar (&opP->disp)
1674 : ! issword (baseo))
1679 else if (! isvar (&opP->disp) && baseo == 0)
1688 as_warn (":b not permitted; defaulting to :w");
1698 /* Figure out innner displacement stuff */
1699 if (opP->mode == POST || opP->mode == PRE)
1704 if (isvar (&opP->odisp)
1706 : ! issword (outro))
1711 else if (! isvar (&opP->disp) && outro == 0)
1720 as_warn (":b not permitted; defaulting to :w");
1729 if (opP->mode == POST)
1734 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
1736 if (opP->reg == PC || opP->reg == ZPC)
1737 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
1739 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
1741 if (siz1 == SIZE_LONG)
1742 addword (baseo >> 16);
1743 if (siz1 != SIZE_UNSPEC)
1746 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1747 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1748 if (siz2 == SIZE_LONG)
1749 addword (outro >> 16);
1750 if (siz2 != SIZE_UNSPEC)
1756 nextword = get_num (&opP->disp, 80);
1757 switch (opP->disp.size)
1762 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
1764 tmpreg = 0x38; /* 7.0 */
1768 /* Don't generate pc relative code on 68010 and
1770 if (isvar (&opP->disp)
1771 && !subs (&opP->disp)
1772 && adds (&opP->disp)
1773 && (S_GET_SEGMENT (adds (&opP->disp)) == text_section)
1774 && now_seg == text_section
1775 && cpu_of_arch (current_architecture) >= m68020
1777 && !strchr ("~%&$?", s[0]))
1779 tmpreg = 0x3A; /* 7.2 */
1780 add_frag (adds (&opP->disp),
1782 TAB (PCREL, SZ_UNDEF));
1785 /* Fall through into long */
1787 if (isvar (&opP->disp))
1788 add_fix ('l', &opP->disp, 0, 0);
1790 tmpreg = 0x39;/* 7.1 mode */
1791 addword (nextword >> 16);
1795 case SIZE_WORD: /* Word */
1796 if (isvar (&opP->disp))
1797 add_fix ('w', &opP->disp, 0, 0);
1799 tmpreg = 0x38;/* 7.0 mode */
1807 as_bad ("unknown/incorrect operand");
1810 install_gen_operand (s[1], tmpreg);
1816 { /* JF: I hate floating point! */
1831 tmpreg = get_num (&opP->disp, tmpreg);
1832 if (isvar (&opP->disp))
1833 add_fix (s[1], &opP->disp, 0, 0);
1836 case 'b': /* Danger: These do no check for
1837 certain types of overflow.
1839 if (!isbyte (tmpreg))
1840 opP->error = "out of range";
1841 insop (tmpreg, opcode);
1842 if (isvar (&opP->disp))
1843 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1846 if (!isword (tmpreg))
1847 opP->error = "out of range";
1848 insop (tmpreg, opcode);
1849 if (isvar (&opP->disp))
1850 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1853 /* Because of the way insop works, we put these two out
1855 insop (tmpreg, opcode);
1856 insop (tmpreg >> 16, opcode);
1857 if (isvar (&opP->disp))
1858 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1864 install_operand (s[1], tmpreg);
1875 install_operand (s[1], opP->reg - ADDR);
1879 tmpreg = get_num (&opP->disp, 80);
1883 add_fix ('B', &opP->disp, 1, -1);
1886 add_fix ('w', &opP->disp, 1, 0);
1891 if (cpu_of_arch (current_architecture) < m68020)
1892 as_warn ("Can't use long branches on 68000/68010");
1893 the_ins.opcode[the_ins.numo - 1] |= 0xff;
1894 add_fix ('l', &opP->disp, 1, 0);
1899 if (subs (&opP->disp)) /* We can't relax it */
1902 /* This could either be a symbol, or an absolute
1903 address. No matter, the frag hacking will finger it
1904 out. Not quite: it can't switch from BRANCH to
1905 BCC68000 for the case where opnd is absolute (it
1906 needs to use the 68000 hack since no conditional abs
1908 if (((cpu_of_arch (current_architecture) < m68020)
1909 || (0 == adds (&opP->disp)))
1910 && (the_ins.opcode[0] >= 0x6200)
1911 && (the_ins.opcode[0] <= 0x6f00))
1912 add_frag (adds (&opP->disp), offs (&opP->disp),
1913 TAB (BCC68000, SZ_UNDEF));
1915 add_frag (adds (&opP->disp), offs (&opP->disp),
1916 TAB (ABRANCH, SZ_UNDEF));
1919 if (isvar (&opP->disp))
1922 /* check for DBcc instruction */
1923 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
1925 /* size varies if patch */
1926 /* needed for long form */
1927 add_frag (adds (&opP->disp), offs (&opP->disp),
1928 TAB (DBCC, SZ_UNDEF));
1932 add_fix ('w', &opP->disp, 1, 0);
1936 case 'C': /* Fixed size LONG coproc branches */
1937 add_fix ('l', &opP->disp, 1, 0);
1941 case 'c': /* Var size Coprocesssor branches */
1942 if (subs (&opP->disp))
1944 add_fix ('l', &opP->disp, 1, 0);
1945 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
1947 else if (adds (&opP->disp))
1948 add_frag (adds (&opP->disp), offs (&opP->disp),
1949 TAB (FBRANCH, SZ_UNDEF));
1952 /* add_frag((symbolS *) 0, offs(&opP->disp),
1953 TAB(FBRANCH,SHORT)); */
1954 the_ins.opcode[the_ins.numo - 1] |= 0x40;
1955 add_fix ('l', &opP->disp, 1, 0);
1965 case 'C': /* Ignore it */
1968 case 'd': /* JF this is a kludge */
1969 install_operand ('s', opP->reg - ADDR);
1970 tmpreg = get_num (&opP->disp, 80);
1971 if (!issword (tmpreg))
1973 as_warn ("Expression out of range, using 0");
1980 install_operand (s[1], opP->reg - DATA);
1984 install_operand (s[1], opP->reg - FP0);
1988 tmpreg = opP->reg - COP0;
1989 install_operand (s[1], tmpreg);
1992 case 'J': /* JF foo */
2053 install_operand (s[1], tmpreg);
2057 tmpreg = get_num (&opP->disp, 55);
2058 install_operand (s[1], tmpreg & 0x7f);
2065 if (tmpreg & 0x7FF0000)
2066 as_bad ("Floating point register in register list");
2067 insop (reverse_16_bits (tmpreg), opcode);
2071 if (tmpreg & 0x700FFFF)
2072 as_bad ("Wrong register in floating-point reglist");
2073 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2081 if (tmpreg & 0x7FF0000)
2082 as_bad ("Floating point register in register list");
2083 insop (tmpreg, opcode);
2085 else if (s[1] == '8')
2087 if (tmpreg & 0x0FFFFFF)
2088 as_bad ("incorrect register in reglist");
2089 install_operand (s[1], tmpreg >> 24);
2093 if (tmpreg & 0x700FFFF)
2094 as_bad ("wrong register in floating-point reglist");
2096 install_operand (s[1], tmpreg >> 16);
2101 install_operand (s[1], get_num (&opP->disp, 60));
2105 tmpreg = ((opP->mode == DREG)
2106 ? 0x20 + opP->reg - DATA
2107 : (get_num (&opP->disp, 40) & 0x1F));
2108 install_operand (s[1], tmpreg);
2112 tmpreg = get_num (&opP->disp, 10);
2115 install_operand (s[1], tmpreg);
2119 /* This depends on the fact that ADDR registers are eight
2120 more than their corresponding DATA regs, so the result
2121 will have the ADDR_REG bit set */
2122 install_operand (s[1], opP->reg - DATA);
2126 if (opP->mode == AINDR)
2127 install_operand (s[1], opP->reg - DATA);
2129 install_operand (s[1], opP->index.reg - DATA);
2133 if (opP->reg == FPI)
2135 else if (opP->reg == FPS)
2137 else if (opP->reg == FPC)
2141 install_operand (s[1], tmpreg);
2144 case 'S': /* Ignore it */
2148 install_operand (s[1], get_num (&opP->disp, 30));
2151 case 'U': /* Ignore it */
2170 as_fatal ("failed sanity check");
2171 } /* switch on cache token */
2172 install_operand (s[1], tmpreg);
2175 /* JF: These are out of order, I fear. */
2188 install_operand (s[1], tmpreg);
2212 install_operand (s[1], tmpreg);
2216 if (opP->reg == VAL)
2235 install_operand (s[1], tmpreg);
2249 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2260 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2266 install_operand (s[1], tmpreg);
2269 know (opP->reg == PSR);
2272 know (opP->reg == PCSR);
2287 install_operand (s[1], tmpreg);
2290 tmpreg = get_num (&opP->disp, 20);
2291 install_operand (s[1], tmpreg);
2293 case '_': /* used only for move16 absolute 32-bit address */
2294 tmpreg = get_num (&opP->disp, 80);
2295 addword (tmpreg >> 16);
2296 addword (tmpreg & 0xFFFF);
2303 /* By the time whe get here (FINALLY) the_ins contains the complete
2304 instruction, ready to be emitted. . . */
2308 reverse_16_bits (in)
2314 static int mask[16] =
2316 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2317 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2319 for (n = 0; n < 16; n++)
2322 out |= mask[15 - n];
2325 } /* reverse_16_bits() */
2334 static int mask[8] =
2336 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2339 for (n = 0; n < 8; n++)
2345 } /* reverse_8_bits() */
2347 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2348 (that value is chosen in the frag_var call in md_assemble). TYPE
2349 is the subtype of the frag to be generated; its primary type is
2350 rs_machine_dependent.
2352 The TYPE parameter is also used by md_convert_frag_1 and
2353 md_estimate_size_before_relax. The appropriate type of fixup will
2354 be emitted by md_convert_frag_1.
2356 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2358 install_operand (mode, val)
2365 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2368 the_ins.opcode[0] |= val << 9;
2371 the_ins.opcode[1] |= val << 12;
2374 the_ins.opcode[1] |= val << 6;
2377 the_ins.opcode[1] |= val;
2380 the_ins.opcode[2] |= val << 12;
2383 the_ins.opcode[2] |= val << 6;
2386 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2387 three words long! */
2389 the_ins.opcode[2] |= val;
2392 the_ins.opcode[1] |= val << 7;
2395 the_ins.opcode[1] |= val << 10;
2399 the_ins.opcode[1] |= val << 5;
2404 the_ins.opcode[1] |= (val << 10) | (val << 7);
2407 the_ins.opcode[1] |= (val << 12) | val;
2410 the_ins.opcode[0] |= val = 0xff;
2413 the_ins.opcode[0] |= val << 9;
2416 the_ins.opcode[1] |= val;
2419 the_ins.opcode[1] |= val;
2420 the_ins.numo++; /* What a hack */
2423 the_ins.opcode[1] |= val << 4;
2430 the_ins.opcode[0] |= (val << 6);
2433 the_ins.opcode[1] = (val >> 16);
2434 the_ins.opcode[2] = val & 0xffff;
2438 as_fatal ("failed sanity check.");
2440 } /* install_operand() */
2443 install_gen_operand (mode, val)
2450 the_ins.opcode[0] |= val;
2453 /* This is a kludge!!! */
2454 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2463 the_ins.opcode[0] |= val;
2465 /* more stuff goes here */
2467 as_fatal ("failed sanity check.");
2469 } /* install_gen_operand() */
2472 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2473 * then deal with the bitfield hack.
2477 crack_operand (str, opP)
2479 register struct m68k_op *opP;
2481 register int parens;
2483 register char *beg_str;
2490 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
2494 else if (*str == ')')
2498 opP->error = "Extra )";
2504 if (!*str && parens)
2506 opP->error = "Missing )";
2511 if (m68k_ip_op (beg_str, opP) != 0)
2518 c = *++str; /* JF bitfield hack */
2523 as_bad ("Missing operand");
2528 /* This is the guts of the machine-dependent assembler. STR points to a
2529 machine dependent instruction. This function is supposed to emit
2530 the frags/bytes it assembles to.
2534 insert_reg (regname, regnum)
2541 #ifdef REGISTER_PREFIX
2542 if (!flag_reg_prefix_optional)
2544 buf[0] = REGISTER_PREFIX;
2545 strcpy (buf + 1, regname);
2550 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2551 &zero_address_frag));
2553 for (i = 0; regname[i]; i++)
2554 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2557 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2558 &zero_address_frag));
2567 static const struct init_entry init_table[] =
2677 /* 68ec030 versions of same */
2680 /* 68ec030 access control unit, identical to 030 MMU status reg */
2683 /* Suppressed data and address registers. */
2708 for (i = 0; init_table[i].name; i++)
2709 insert_reg (init_table[i].name, init_table[i].number);
2712 static int no_68851, no_68881;
2715 /* a.out machine type. Default to 68020. */
2716 int m68k_aout_machtype = 2;
2728 int shorts_this_frag;
2731 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
2736 for (n = 0; n < the_ins.numargs; n++)
2737 if (the_ins.operands[n].error)
2739 er = the_ins.operands[n].error;
2745 as_bad ("%s -- statement `%s' ignored", er, str);
2749 if (the_ins.nfrag == 0)
2751 /* No frag hacking involved; just put it out */
2752 toP = frag_more (2 * the_ins.numo);
2753 fromP = &the_ins.opcode[0];
2754 for (m = the_ins.numo; m; --m)
2756 md_number_to_chars (toP, (long) (*fromP), 2);
2760 /* put out symbol-dependent info */
2761 for (m = 0; m < the_ins.nrel; m++)
2763 switch (the_ins.reloc[m].wid)
2781 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2782 the_ins.reloc[m].wid);
2785 fixP = fix_new_exp (frag_now,
2786 ((toP - frag_now->fr_literal)
2787 - the_ins.numo * 2 + the_ins.reloc[m].n),
2789 &the_ins.reloc[m].exp,
2790 the_ins.reloc[m].pcrel,
2792 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2797 /* There's some frag hacking */
2798 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2803 wid = 2 * the_ins.fragb[n].fragoff;
2805 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2806 toP = frag_more (wid);
2808 shorts_this_frag = 0;
2809 for (m = wid / 2; m; --m)
2811 md_number_to_chars (toP, (long) (*fromP), 2);
2816 for (m = 0; m < the_ins.nrel; m++)
2818 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
2820 the_ins.reloc[m].n -= 2 * shorts_this_frag;
2823 wid = the_ins.reloc[m].wid;
2826 the_ins.reloc[m].wid = 0;
2827 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2829 fixP = fix_new_exp (frag_now,
2830 ((toP - frag_now->fr_literal)
2831 - the_ins.numo * 2 + the_ins.reloc[m].n),
2833 &the_ins.reloc[m].exp,
2834 the_ins.reloc[m].pcrel,
2836 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2838 (void) frag_var (rs_machine_dependent, 10, 0,
2839 (relax_substateT) (the_ins.fragb[n].fragty),
2840 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
2842 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2843 shorts_this_frag = 0;
2846 toP = frag_more (n * sizeof (short));
2849 md_number_to_chars (toP, (long) (*fromP), 2);
2855 for (m = 0; m < the_ins.nrel; m++)
2859 wid = the_ins.reloc[m].wid;
2862 the_ins.reloc[m].wid = 0;
2863 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2865 fixP = fix_new_exp (frag_now,
2866 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
2867 - shorts_this_frag * 2),
2869 &the_ins.reloc[m].exp,
2870 the_ins.reloc[m].pcrel,
2872 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2880 * md_begin -- set up hash tables with 68000 instructions.
2881 * similar to what the vax assembler does. ---phr
2883 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2884 a copy of it at runtime, adding in the information we want but isn't
2885 there. I think it'd be better to have an awk script hack the table
2886 at compile time. Or even just xstr the table and use it as-is. But
2887 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2890 register const struct m68k_opcode *ins;
2891 register struct m68k_incant *hack, *slak;
2892 register const char *retval = 0; /* empty string, or error msg text */
2893 register unsigned int i;
2898 flag_reg_prefix_optional = 1;
2903 op_hash = hash_new ();
2905 obstack_begin (&robyn, 4000);
2906 for (i = 0; i < m68k_numopcodes; i++)
2908 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
2911 ins = &m68k_opcodes[i];
2912 /* We *could* ignore insns that don't match our arch here
2913 but just leaving them out of the hash. */
2914 slak->m_operands = ins->args;
2915 slak->m_opnum = strlen (slak->m_operands) / 2;
2916 slak->m_arch = ins->arch;
2917 slak->m_opcode = ins->opcode;
2918 /* This is kludgey */
2919 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
2920 if (i + 1 != m68k_numopcodes
2921 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
2923 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
2928 slak = slak->m_next;
2932 retval = hash_insert (op_hash, ins->name, (char *) hack);
2934 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
2937 for (i = 0; i < m68k_numaliases; i++)
2939 const char *name = m68k_opcode_aliases[i].primary;
2940 const char *alias = m68k_opcode_aliases[i].alias;
2941 PTR val = hash_find (op_hash, name);
2943 as_fatal ("Internal Error: Can't find %s in hash table", name);
2944 retval = hash_insert (op_hash, alias, val);
2946 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
2949 /* In MRI mode, all unsized branches are variable sized. Normally,
2950 they are word sized. */
2953 static struct m68k_opcode_alias mri_aliases[] =
2973 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
2975 const char *name = mri_aliases[i].primary;
2976 const char *alias = mri_aliases[i].alias;
2977 PTR val = hash_find (op_hash, name);
2979 as_fatal ("Internal Error: Can't find %s in hash table", name);
2980 retval = hash_jam (op_hash, alias, val);
2982 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
2986 for (i = 0; i < sizeof (mklower_table); i++)
2987 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
2989 for (i = 0; i < sizeof (notend_table); i++)
2991 notend_table[i] = 0;
2992 alt_notend_table[i] = 0;
2994 notend_table[','] = 1;
2995 notend_table['{'] = 1;
2996 notend_table['}'] = 1;
2997 alt_notend_table['a'] = 1;
2998 alt_notend_table['A'] = 1;
2999 alt_notend_table['d'] = 1;
3000 alt_notend_table['D'] = 1;
3001 alt_notend_table['#'] = 1;
3002 alt_notend_table['&'] = 1;
3003 alt_notend_table['f'] = 1;
3004 alt_notend_table['F'] = 1;
3005 #ifdef REGISTER_PREFIX
3006 alt_notend_table[REGISTER_PREFIX] = 1;
3009 /* We need to put '(' in alt_notend_table to handle
3010 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3012 alt_notend_table['('] = 1;
3014 /* We need to put '@' in alt_notend_table to handle
3015 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3017 alt_notend_table['@'] = 1;
3019 #ifndef MIT_SYNTAX_ONLY
3020 /* Insert pseudo ops, these have to go into the opcode table since
3021 gas expects pseudo ops to start with a dot */
3024 while (mote_pseudo_table[n].poc_name)
3026 hack = (struct m68k_incant *)
3027 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3028 hash_insert (op_hash,
3029 mote_pseudo_table[n].poc_name, (char *) hack);
3030 hack->m_operands = 0;
3041 m68k_init_after_args ()
3043 if (cpu_of_arch (current_architecture) == 0)
3046 const char *default_cpu = TARGET_CPU;
3048 if (*default_cpu == 'm')
3050 for (i = 0; i < n_archs; i++)
3051 if (strcasecmp (default_cpu, archs[i].name) == 0)
3055 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3056 current_architecture |= m68020;
3059 current_architecture |= archs[i].arch;
3061 /* Permit m68881 specification with all cpus; those that can't work
3062 with a coprocessor could be doing emulation. */
3063 if (current_architecture & m68851)
3065 if (current_architecture & m68040)
3067 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3070 /* What other incompatibilities could we check for? */
3072 /* Toss in some default assumptions about coprocessors. */
3074 && (cpu_of_arch (current_architecture)
3075 /* Can CPU32 have a 68881 coprocessor?? */
3076 & (m68020 | m68030 | cpu32)))
3078 current_architecture |= m68881;
3081 && (cpu_of_arch (current_architecture) & m68020up) != 0
3082 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3084 current_architecture |= m68851;
3086 if (no_68881 && (current_architecture & m68881))
3087 as_bad ("options for 68881 and no-68881 both given");
3088 if (no_68851 && (current_architecture & m68851))
3089 as_bad ("options for 68851 and no-68851 both given");
3092 /* Work out the magic number. This isn't very general. */
3093 if (current_architecture & m68000)
3094 m68k_aout_machtype = 0;
3095 else if (current_architecture & m68010)
3096 m68k_aout_machtype = 1;
3097 else if (current_architecture & m68020)
3098 m68k_aout_machtype = 2;
3100 m68k_aout_machtype = 2;
3103 /* Note which set of "movec" control registers is available. */
3104 switch (cpu_of_arch (current_architecture))
3107 control_regs = m68000_control_regs;
3110 control_regs = m68010_control_regs;
3114 control_regs = m68020_control_regs;
3117 control_regs = m68040_control_regs;
3120 control_regs = m68060_control_regs;
3123 control_regs = cpu32_control_regs;
3129 if (cpu_of_arch (current_architecture) < m68020)
3130 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3133 /* Equal to MAX_PRECISION in atof-ieee.c */
3134 #define MAX_LITTLENUMS 6
3136 /* Turn a string in input_line_pointer into a floating point constant
3137 of type type, and store the appropriate bytes in *litP. The number
3138 of LITTLENUMS emitted is stored in *sizeP . An error message is
3139 returned, or NULL on OK. */
3142 md_atof (type, litP, sizeP)
3148 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3149 LITTLENUM_TYPE *wordP;
3181 return "Bad call to MD_ATOF()";
3183 t = atof_ieee (input_line_pointer, type, words);
3185 input_line_pointer = t;
3187 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3188 for (wordP = words; prec--;)
3190 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3191 litP += sizeof (LITTLENUM_TYPE);
3197 md_number_to_chars (buf, val, n)
3202 number_to_chars_bigendian (buf, val, n);
3206 md_apply_fix_2 (fixP, val)
3210 addressT upper_limit;
3211 offsetT lower_limit;
3213 /* This is unnecessary but it convinces the native rs6000 compiler
3214 to generate the code we want. */
3215 char *buf = fixP->fx_frag->fr_literal;
3216 buf += fixP->fx_where;
3217 /* end ibm compiler workaround */
3219 if (val & 0x80000000)
3220 val |= ~(addressT)0x7fffffff;
3224 switch (fixP->fx_size)
3226 /* The cast to offsetT below are necessary to make code correct for
3227 machines where ints are smaller than offsetT */
3231 lower_limit = - (offsetT) 0x80;
3234 *buf++ = (val >> 8);
3236 upper_limit = 0x7fff;
3237 lower_limit = - (offsetT) 0x8000;
3240 *buf++ = (val >> 24);
3241 *buf++ = (val >> 16);
3242 *buf++ = (val >> 8);
3244 upper_limit = 0x7fffffff;
3245 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3248 BAD_CASE (fixP->fx_size);
3251 /* For non-pc-relative values, it's conceivable we might get something
3252 like "0xff" for a byte field. So extend the upper part of the range
3253 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3254 so that we can do any range checking at all. */
3255 if (!fixP->fx_pcrel)
3256 upper_limit = upper_limit * 2 + 1;
3258 if ((addressT) val > upper_limit
3259 && (val > 0 || val < lower_limit))
3260 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3262 /* A one byte PC-relative reloc means a short branch. We can't use
3263 a short branch with a value of 0 or -1, because those indicate
3264 different opcodes (branches with longer offsets). */
3266 && fixP->fx_size == 1
3267 && (fixP->fx_addsy == NULL
3268 || S_IS_DEFINED (fixP->fx_addsy))
3269 && (val == 0 || val == -1))
3270 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3273 #ifdef BFD_ASSEMBLER
3275 md_apply_fix (fixP, valp)
3279 md_apply_fix_2 (fixP, (addressT) *valp);
3283 void md_apply_fix (fixP, val)
3287 md_apply_fix_2 (fixP, (addressT) val);
3291 /* *fragP has been relaxed to its final size, and now needs to have
3292 the bytes inside it modified to conform to the new size There is UGLY
3296 md_convert_frag_1 (fragP)
3297 register fragS *fragP;
3303 /* Address in object code of the displacement. */
3304 register int object_address = fragP->fr_fix + fragP->fr_address;
3306 /* Address in gas core of the place to store the displacement. */
3307 /* This convinces the native rs6000 compiler to generate the code we
3309 register char *buffer_address = fragP->fr_literal;
3310 buffer_address += fragP->fr_fix;
3311 /* end ibm compiler workaround */
3313 /* The displacement of the address, from current location. */
3314 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3315 disp = (disp + fragP->fr_offset) - object_address;
3317 #ifdef BFD_ASSEMBLER
3318 disp += fragP->fr_symbol->sy_frag->fr_address;
3321 switch (fragP->fr_subtype)
3323 case TAB (BCC68000, BYTE):
3324 case TAB (ABRANCH, BYTE):
3325 know (issbyte (disp));
3327 as_bad ("short branch with zero offset: use :w");
3328 fragP->fr_opcode[1] = disp;
3331 case TAB (DBCC, SHORT):
3332 know (issword (disp));
3335 case TAB (BCC68000, SHORT):
3336 case TAB (ABRANCH, SHORT):
3337 know (issword (disp));
3338 fragP->fr_opcode[1] = 0x00;
3341 case TAB (ABRANCH, LONG):
3342 if (cpu_of_arch (current_architecture) < m68020)
3344 if (fragP->fr_opcode[0] == 0x61)
3347 fragP->fr_opcode[0] = 0x4E;
3348 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3349 subseg_change (text_section, 0); /* @@ */
3363 else if (fragP->fr_opcode[0] == 0x60)
3365 fragP->fr_opcode[0] = 0x4E;
3366 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3367 subseg_change (text_section, 0); /* @@ */
3368 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3369 fragP->fr_offset, 0, NO_RELOC);
3375 as_bad ("Long branch offset not supported.");
3380 fragP->fr_opcode[1] = (char) 0xff;
3384 case TAB (BCC68000, LONG):
3385 /* only Bcc 68000 instructions can come here */
3386 /* change bcc into b!cc/jmp absl long */
3387 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3388 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3390 /* JF: these used to be fr_opcode[2,3], but they may be in a
3391 different frag, in which case refering to them is a no-no.
3392 Only fr_opcode[0,1] are guaranteed to work. */
3393 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3394 *buffer_address++ = (char) 0xf9;
3395 fragP->fr_fix += 2; /* account for jmp instruction */
3396 subseg_change (text_section, 0);
3397 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3398 fragP->fr_offset, 0, NO_RELOC);
3402 case TAB (DBCC, LONG):
3403 /* only DBcc 68000 instructions can come here */
3404 /* change dbcc into dbcc/jmp absl long */
3405 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3406 *buffer_address++ = 0x00; /* branch offset = 4 */
3407 *buffer_address++ = 0x04;
3408 *buffer_address++ = 0x60; /* put in bra pc+6 */
3409 *buffer_address++ = 0x06;
3410 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3411 *buffer_address++ = (char) 0xf9;
3413 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3414 subseg_change (text_section, 0);
3415 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3416 fragP->fr_offset, 0, NO_RELOC);
3420 case TAB (FBRANCH, SHORT):
3421 know ((fragP->fr_opcode[1] & 0x40) == 0);
3424 case TAB (FBRANCH, LONG):
3425 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3428 case TAB (PCREL, SHORT):
3431 case TAB (PCREL, LONG):
3432 /* The thing to do here is force it to ABSOLUTE LONG, since
3433 PCREL is really trying to shorten an ABSOLUTE address anyway */
3434 /* JF FOO This code has not been tested */
3435 subseg_change (text_section, 0);
3436 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3438 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3439 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3440 (unsigned) fragP->fr_opcode[0],
3441 (unsigned long) fragP->fr_address);
3442 fragP->fr_opcode[1] &= ~0x3F;
3443 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3447 case TAB (PCLEA, SHORT):
3448 subseg_change (text_section, 0);
3449 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3450 fragP->fr_offset, 1, NO_RELOC);
3451 fragP->fr_opcode[1] &= ~0x3F;
3452 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3455 case TAB (PCLEA, LONG):
3456 subseg_change (text_section, 0);
3457 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3458 fragP->fr_offset, 1, NO_RELOC);
3459 fixP->fx_pcrel_adjust = 2;
3460 /* Already set to mode 7.3; this indicates: PC indirect with
3461 suppressed index, 32-bit displacement. */
3462 *buffer_address++ = 0x01;
3463 *buffer_address++ = 0x70;
3468 case TAB (PCINDEX, BYTE):
3470 if (!issbyte (disp))
3472 as_bad ("displacement doesn't fit in one byte");
3475 assert (fragP->fr_fix >= 2);
3476 buffer_address[-2] &= ~1;
3477 buffer_address[-1] = disp;
3480 case TAB (PCINDEX, SHORT):
3481 subseg_change (text_section, 0);
3483 assert (issword (disp));
3484 assert (fragP->fr_fix >= 2);
3485 buffer_address[-2] |= 0x1;
3486 buffer_address[-1] = 0x20;
3487 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3488 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3490 fixP->fx_pcrel_adjust = 2;
3493 case TAB (PCINDEX, LONG):
3494 subseg_change (text_section, 0);
3496 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3497 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3499 fixP->fx_pcrel_adjust = 2;
3500 assert (fragP->fr_fix >= 2);
3501 buffer_address[-2] |= 0x1;
3502 buffer_address[-1] = 0x30;
3509 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3510 fragP->fr_fix += ext;
3514 #ifndef BFD_ASSEMBLER
3517 md_convert_frag (headers, sec, fragP)
3518 object_headers *headers;
3522 md_convert_frag_1 (fragP);
3528 md_convert_frag (abfd, sec, fragP)
3533 md_convert_frag_1 (fragP);
3537 /* Force truly undefined symbols to their maximum size, and generally set up
3538 the frag list to be relaxed
3541 md_estimate_size_before_relax (fragP, segment)
3542 register fragS *fragP;
3546 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3548 old_fix = fragP->fr_fix;
3550 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3551 switch (fragP->fr_subtype)
3554 case TAB (ABRANCH, SZ_UNDEF):
3556 if ((fragP->fr_symbol != NULL) /* Not absolute */
3557 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3559 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3562 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3564 /* On 68000, or for absolute value, switch to abs long */
3565 /* FIXME, we should check abs val, pick short or long */
3566 if (fragP->fr_opcode[0] == 0x61)
3568 fragP->fr_opcode[0] = 0x4E;
3569 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3570 subseg_change (text_section, 0);
3571 fix_new (fragP, fragP->fr_fix, 4,
3572 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3576 else if (fragP->fr_opcode[0] == 0x60)
3578 fragP->fr_opcode[0] = 0x4E;
3579 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3580 subseg_change (text_section, 0);
3581 fix_new (fragP, fragP->fr_fix, 4,
3582 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3588 as_warn ("Long branch offset to extern symbol not supported.");
3592 { /* Symbol is still undefined. Make it simple */
3593 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3594 fragP->fr_offset, 1, NO_RELOC);
3596 fragP->fr_opcode[1] = (char) 0xff;
3602 } /* case TAB(ABRANCH,SZ_UNDEF) */
3604 case TAB (FBRANCH, SZ_UNDEF):
3606 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3608 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3613 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3614 fragP->fr_offset, 1, NO_RELOC);
3616 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3620 } /* TAB(FBRANCH,SZ_UNDEF) */
3622 case TAB (PCREL, SZ_UNDEF):
3624 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3626 || cpu_of_arch (current_architecture) < m68020)
3628 fragP->fr_subtype = TAB (PCREL, SHORT);
3633 fragP->fr_subtype = TAB (PCREL, LONG);
3637 } /* TAB(PCREL,SZ_UNDEF) */
3639 case TAB (BCC68000, SZ_UNDEF):
3641 if ((fragP->fr_symbol != NULL)
3642 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3644 fragP->fr_subtype = TAB (BCC68000, BYTE);
3647 /* only Bcc 68000 instructions can come here */
3648 /* change bcc into b!cc/jmp absl long */
3649 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3650 if (flag_short_refs)
3652 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3653 /* JF: these were fr_opcode[2,3] */
3654 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3655 buffer_address[1] = (char) 0xf8;
3656 fragP->fr_fix += 2; /* account for jmp instruction */
3657 subseg_change (text_section, 0);
3658 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3659 fragP->fr_offset, 0, NO_RELOC);
3664 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3665 /* JF: these were fr_opcode[2,3] */
3666 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3667 buffer_address[1] = (char) 0xf9;
3668 fragP->fr_fix += 2; /* account for jmp instruction */
3669 subseg_change (text_section, 0);
3670 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3671 fragP->fr_offset, 0, NO_RELOC);
3676 } /* case TAB(BCC68000,SZ_UNDEF) */
3678 case TAB (DBCC, SZ_UNDEF):
3680 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3682 fragP->fr_subtype = TAB (DBCC, SHORT);
3686 /* only DBcc 68000 instructions can come here */
3687 /* change dbcc into dbcc/jmp absl long */
3688 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3689 buffer_address[0] = 0x00; /* branch offset = 4 */
3690 buffer_address[1] = 0x04;
3691 buffer_address[2] = 0x60; /* put in bra pc + ... */
3693 if (flag_short_refs)
3695 /* JF: these were fr_opcode[5-7] */
3696 buffer_address[3] = 0x04; /* plus 4 */
3697 buffer_address[4] = 0x4e; /* Put in Jump Word */
3698 buffer_address[5] = (char) 0xf8;
3699 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3700 subseg_change (text_section, 0);
3701 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3702 fragP->fr_offset, 0, NO_RELOC);
3707 /* JF: these were fr_opcode[5-7] */
3708 buffer_address[3] = 0x06; /* Plus 6 */
3709 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3710 buffer_address[5] = (char) 0xf9;
3711 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3712 subseg_change (text_section, 0);
3713 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3714 fragP->fr_offset, 0, NO_RELOC);
3720 } /* case TAB(DBCC,SZ_UNDEF) */
3722 case TAB (PCLEA, SZ_UNDEF):
3724 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3726 || cpu_of_arch (current_architecture) < m68020)
3728 fragP->fr_subtype = TAB (PCLEA, SHORT);
3733 fragP->fr_subtype = TAB (PCLEA, LONG);
3737 } /* TAB(PCLEA,SZ_UNDEF) */
3739 case TAB (PCINDEX, SZ_UNDEF):
3740 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3741 || cpu_of_arch (current_architecture) < m68020)
3743 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3747 fragP->fr_subtype = TAB (PCINDEX, LONG);
3756 /* now that SZ_UNDEF are taken care of, check others */
3757 switch (fragP->fr_subtype)
3759 case TAB (BCC68000, BYTE):
3760 case TAB (ABRANCH, BYTE):
3761 /* We can't do a short jump to the next instruction,
3762 so we force word mode. */
3763 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3764 fragP->fr_symbol->sy_frag == fragP->fr_next)
3766 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3773 return fragP->fr_var + fragP->fr_fix - old_fix;
3776 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3777 /* the bit-field entries in the relocation_info struct plays hell
3778 with the byte-order problems of cross-assembly. So as a hack,
3779 I added this mach. dependent ri twiddler. Ugly, but it gets
3781 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3782 are symbolnum, most sig. byte first. Last byte is broken up with
3783 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3784 nibble as nuthin. (on Sun 3 at least) */
3785 /* Translate the internal relocation information into target-specific
3789 md_ri_to_chars (the_bytes, ri)
3791 struct reloc_info_generic *ri;
3794 md_number_to_chars (the_bytes, ri->r_address, 4);
3795 /* now the fun stuff */
3796 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3797 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3798 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3799 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3800 ((ri->r_extern << 4) & 0x10));
3803 #endif /* comment */
3805 #ifndef BFD_ASSEMBLER
3807 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3810 relax_addressT segment_address_in_file;
3813 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3814 * Out: GNU LD relocation length code: 0, 1, or 2.
3817 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3820 know (fixP->fx_addsy != NULL);
3822 md_number_to_chars (where,
3823 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3826 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3827 ? S_GET_TYPE (fixP->fx_addsy)
3828 : fixP->fx_addsy->sy_number);
3830 where[4] = (r_symbolnum >> 16) & 0x0ff;
3831 where[5] = (r_symbolnum >> 8) & 0x0ff;
3832 where[6] = r_symbolnum & 0x0ff;
3833 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3834 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
3838 #endif /* OBJ_AOUT or OBJ_BOUT */
3840 #ifndef WORKING_DOT_WORD
3841 CONST int md_short_jump_size = 4;
3842 CONST int md_long_jump_size = 6;
3845 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3847 addressT from_addr, to_addr;
3853 offset = to_addr - (from_addr + 2);
3855 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3856 md_number_to_chars (ptr + 2, (valueT) offset, 2);
3860 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3862 addressT from_addr, to_addr;
3868 if (cpu_of_arch (current_architecture) < m68020)
3870 offset = to_addr - S_GET_VALUE (to_symbol);
3871 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
3872 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3873 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
3878 offset = to_addr - (from_addr + 2);
3879 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
3880 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3886 /* Different values of OK tell what its OK to return. Things that
3887 aren't OK are an error (what a shock, no?)
3890 10: Absolute 1:8 only
3891 20: Absolute 0:7 only
3892 30: absolute 0:15 only
3893 40: Absolute 0:31 only
3894 50: absolute 0:127 only
3895 55: absolute -64:63 only
3896 60: absolute -128:127 only
3897 70: absolute 0:4095 only
3904 struct m68k_exp *exp;
3907 if (exp->exp.X_op == O_absent)
3909 /* Do the same thing the VAX asm does */
3910 op (exp) = O_constant;
3916 as_warn ("expression out of range: defaulting to 1");
3920 else if (exp->exp.X_op == O_constant)
3925 if (offs (exp) < 1 || offs (exp) > 8)
3927 as_warn ("expression out of range: defaulting to 1");
3932 if (offs (exp) < 0 || offs (exp) > 7)
3936 if (offs (exp) < 0 || offs (exp) > 15)
3940 if (offs (exp) < 0 || offs (exp) > 32)
3944 if (offs (exp) < 0 || offs (exp) > 127)
3948 if (offs (exp) < -64 || offs (exp) > 63)
3952 if (offs (exp) < -128 || offs (exp) > 127)
3956 if (offs (exp) < 0 || offs (exp) > 4095)
3959 as_warn ("expression out of range: defaulting to 0");
3967 else if (exp->exp.X_op == O_big)
3969 if (offs (exp) <= 0 /* flonum */
3970 && (ok == 80 /* no bignums */
3971 || (ok > 10 /* small-int ranges including 0 ok */
3972 /* If we have a flonum zero, a zero integer should
3973 do as well (e.g., in moveq). */
3974 && generic_floating_point_number.exponent == 0
3975 && generic_floating_point_number.low[0] == 0)))
3977 /* HACK! Turn it into a long */
3978 LITTLENUM_TYPE words[6];
3980 gen_to_words (words, 2, 8L); /* These numbers are magic! */
3981 op (exp) = O_constant;
3984 offs (exp) = words[1] | (words[0] << 16);
3988 op (exp) = O_constant;
3991 offs (exp) = (ok == 10) ? 1 : 0;
3992 as_warn ("Can't deal with expression; defaulting to %ld",
3998 if (ok >= 10 && ok <= 70)
4000 op (exp) = O_constant;
4003 offs (exp) = (ok == 10) ? 1 : 0;
4004 as_warn ("Can't deal with expression; defaulting to %ld",
4009 if (exp->size != SIZE_UNSPEC)
4017 if (!isbyte (offs (exp)))
4018 as_warn ("expression doesn't fit in BYTE");
4021 if (!isword (offs (exp)))
4022 as_warn ("expression doesn't fit in WORD");
4030 /* These are the back-ends for the various machine dependent pseudo-ops. */
4031 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4037 subseg_set (data_section, 1);
4038 demand_empty_rest_of_line ();
4045 subseg_set (data_section, 2);
4046 demand_empty_rest_of_line ();
4053 /* We don't support putting frags in the BSS segment, we fake it
4054 by marking in_bss, then looking at s_skip for clues. */
4056 subseg_set (bss_section, 0);
4057 demand_empty_rest_of_line ();
4065 register long temp_fill;
4067 temp = 1; /* JF should be 2? */
4068 temp_fill = get_absolute_expression ();
4069 if (!need_pass_2) /* Never make frag if expect extra pass. */
4070 frag_align (temp, (int) temp_fill);
4071 demand_empty_rest_of_line ();
4078 demand_empty_rest_of_line ();
4081 /* Pseudo-ops handled for MRI compatibility. */
4083 /* Handle an MRI style chip specification. */
4092 s = input_line_pointer;
4093 c = get_symbol_end ();
4094 for (i = 0; i < n_archs; i++)
4095 if (strcasecmp (s, archs[i].name) == 0)
4099 as_bad ("%s: unrecognized processor name", s);
4100 *input_line_pointer = c;
4101 ignore_rest_of_line ();
4104 *input_line_pointer = c;
4106 if (*input_line_pointer == '/')
4107 current_architecture = 0;
4109 current_architecture &= m68881 | m68851;
4110 current_architecture |= archs[i].arch;
4112 while (*input_line_pointer == '/')
4114 ++input_line_pointer;
4115 s = input_line_pointer;
4116 c = get_symbol_end ();
4117 if (strcmp (s, "68881") == 0)
4118 current_architecture |= m68881;
4119 else if (strcmp (s, "68851") == 0)
4120 current_architecture |= m68851;
4121 *input_line_pointer = c;
4125 /* The MRI CHIP pseudo-op. */
4132 demand_empty_rest_of_line ();
4135 /* The MRI FOPT pseudo-op. */
4143 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4147 input_line_pointer += 3;
4148 temp = get_absolute_expression ();
4149 if (temp < 0 || temp > 7)
4150 as_bad ("bad coprocessor id");
4152 m68k_float_copnum = COP0 + temp;
4156 as_bad ("unrecognized fopt option");
4157 ignore_rest_of_line ();
4161 demand_empty_rest_of_line ();
4164 /* The structure used to handle the MRI OPT pseudo-op. */
4168 /* The name of the option. */
4171 /* If this is not NULL, just call this function. The first argument
4172 is the ARG field of this structure, the second argument is
4173 whether the option was negated. */
4174 void (*pfn) PARAMS ((int arg, int on));
4176 /* If this is not NULL, and the PFN field is NULL, set the variable
4177 this points to. Set it to the ARG field if the option was not
4178 negated, and the NOTARG field otherwise. */
4181 /* The value to pass to PFN or to assign to *PVAR. */
4184 /* The value to assign to *PVAR if the option is negated. If PFN is
4185 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4186 the option may not be negated. */
4190 /* The table used to handle the MRI OPT pseudo-op. */
4192 static void skip_to_comma PARAMS ((int, int));
4193 static void opt_chip PARAMS ((int, int));
4194 static void opt_list PARAMS ((int, int));
4195 static void opt_list_symbols PARAMS ((int, int));
4197 static const struct opt_action opt_table[] =
4199 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4201 /* We do relaxing, so there is little use for these options. */
4202 { "b", 0, 0, 0, 0 },
4203 { "brs", 0, 0, 0, 0 },
4204 { "brb", 0, 0, 0, 0 },
4205 { "brl", 0, 0, 0, 0 },
4206 { "brw", 0, 0, 0, 0 },
4208 { "c", 0, 0, 0, 0 },
4209 { "cex", 0, 0, 0, 0 },
4210 { "case", 0, &symbols_case_sensitive, 1, 0 },
4211 { "cl", 0, 0, 0, 0 },
4212 { "cre", 0, 0, 0, 0 },
4213 { "d", 0, &flag_keep_locals, 1, 0 },
4214 { "e", 0, 0, 0, 0 },
4215 { "f", 0, &flag_short_refs, 1, 0 },
4216 { "frs", 0, &flag_short_refs, 1, 0 },
4217 { "frl", 0, &flag_short_refs, 0, 1 },
4218 { "g", 0, 0, 0, 0 },
4219 { "i", 0, 0, 0, 0 },
4220 { "m", 0, 0, 0, 0 },
4221 { "mex", 0, 0, 0, 0 },
4222 { "mc", 0, 0, 0, 0 },
4223 { "md", 0, 0, 0, 0 },
4224 { "next", skip_to_comma, 0, 0, 0 },
4225 { "o", 0, 0, 0, 0 },
4226 { "old", 0, 0, 0, 0 },
4227 { "op", skip_to_comma, 0, 0, 0 },
4228 { "pco", 0, 0, 0, 0 },
4229 { "p", opt_chip, 0, 0, 0 },
4230 { "pcr", 0, 0, 0, 0 },
4231 { "pcs", 0, 0, 0, 0 },
4232 { "r", 0, 0, 0, 0 },
4233 { "quick", 0, &m68k_quick, 1, 0 },
4234 { "rel32", 0, &m68k_rel32, 1, 0 },
4235 { "s", opt_list, 0, 0, 0 },
4236 { "t", opt_list_symbols, 0, 0, 0 },
4237 { "w", 0, &flag_no_warnings, 0, 1 },
4241 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4243 /* The MRI OPT pseudo-op. */
4255 const struct opt_action *o;
4260 if (*input_line_pointer == '-')
4262 ++input_line_pointer;
4265 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4267 input_line_pointer += 2;
4271 s = input_line_pointer;
4272 c = get_symbol_end ();
4274 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4276 if (strcasecmp (s, o->name) == 0)
4280 /* Restore input_line_pointer now in case the option
4282 *input_line_pointer = c;
4283 (*o->pfn) (o->arg, t);
4285 else if (o->pvar != NULL)
4287 if (! t && o->arg == o->notarg)
4288 as_bad ("option `%s' may not be negated", s);
4289 *input_line_pointer = c;
4290 *o->pvar = t ? o->arg : o->notarg;
4297 as_bad ("option `%s' not recognized", s);
4298 *input_line_pointer = c;
4301 while (*input_line_pointer++ == ',');
4303 /* Move back to terminating character. */
4304 --input_line_pointer;
4305 demand_empty_rest_of_line ();
4308 /* Skip ahead to a comma. This is used for OPT options which we do
4309 not suppor tand which take arguments. */
4312 skip_to_comma (arg, on)
4316 while (*input_line_pointer != ','
4317 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4318 ++input_line_pointer;
4321 /* Handle the OPT P=chip option. */
4328 if (*input_line_pointer != '=')
4330 /* This is just OPT P, which we do not support. */
4334 ++input_line_pointer;
4338 /* Handle the OPT S option. */
4348 /* Handle the OPT T option. */
4351 opt_list_symbols (arg, on)
4356 listing |= LISTING_SYMBOLS;
4358 listing &=~ LISTING_SYMBOLS;
4361 /* Handle the MRI REG pseudo-op. */
4372 if (mri_line_label == NULL)
4374 as_bad ("missing label");
4375 ignore_rest_of_line ();
4381 s = input_line_pointer;
4382 while (isalnum ((unsigned char) *input_line_pointer)
4383 #ifdef REGISTER_PREFIX
4384 || *input_line_pointer == REGISTER_PREFIX
4386 || *input_line_pointer == '/'
4387 || *input_line_pointer == '-')
4388 ++input_line_pointer;
4389 c = *input_line_pointer;
4390 *input_line_pointer = '\0';
4392 if (m68k_ip_op (s, &op) != 0)
4394 if (op.error == NULL)
4395 as_bad ("bad register list");
4397 as_bad ("bad register list: %s", op.error);
4398 *input_line_pointer = c;
4399 ignore_rest_of_line ();
4403 *input_line_pointer = c;
4405 if (op.mode == REGLST)
4407 else if (op.mode == DREG)
4408 mask = 1 << (op.reg - DATA0);
4409 else if (op.mode == AREG)
4410 mask = 1 << (op.reg - ADDR0 + 8);
4411 else if (op.mode == FPREG)
4412 mask = 1 << (op.reg - FP0 + 16);
4413 else if (op.mode == CONTROL
4416 else if (op.mode == CONTROL
4419 else if (op.mode == CONTROL
4424 as_bad ("bad register list");
4425 ignore_rest_of_line ();
4429 S_SET_SEGMENT (mri_line_label, absolute_section);
4430 S_SET_VALUE (mri_line_label, mask);
4431 mri_line_label->sy_frag = &zero_address_frag;
4433 demand_empty_rest_of_line ();
4438 * Invocation line includes a switch not recognized by the base assembler.
4439 * See if it's a processor-specific option. These are:
4441 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4442 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4443 * Select the architecture. Instructions or features not
4444 * supported by the selected architecture cause fatal
4445 * errors. More than one may be specified. The default is
4446 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4447 * for -m68000, and -m68882 is a synonym for -m68881.
4448 * -[A]m[c]no-68851, -[A]m[c]no-68881
4449 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4450 * so don't use or document it, but that's the way the parsing
4453 * -pic Indicates PIC.
4454 * -k Indicates PIC. (Sun 3 only.)
4459 CONST char *md_shortopts = "lSA:m:kQ:V";
4461 CONST char *md_shortopts = "lSA:m:k";
4464 struct option md_longopts[] = {
4465 #define OPTION_PIC (OPTION_MD_BASE)
4466 {"pic", no_argument, NULL, OPTION_PIC},
4467 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
4468 {"register-prefix-optional", no_argument, NULL,
4469 OPTION_REGISTER_PREFIX_OPTIONAL},
4470 {NULL, no_argument, NULL, 0}
4472 size_t md_longopts_size = sizeof(md_longopts);
4475 md_parse_option (c, arg)
4481 case 'l': /* -l means keep external to 2 bit offset
4482 rather than 16 bit one */
4483 flag_short_refs = 1;
4486 case 'S': /* -S means that jbsr's always turn into
4488 flag_long_jumps = 1;
4494 /* intentional fall-through */
4497 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
4501 const char *oarg = arg;
4507 if (arg[0] == 'c' && arg[1] == '6')
4510 for (i = 0; i < n_archs; i++)
4511 if (!strcmp (arg, archs[i].name))
4516 as_bad ("unrecognized option `%s'", oarg);
4519 arch = archs[i].arch;
4522 else if (arch == m68851)
4531 if (arg[0] == 'c' && arg[1] == '6')
4534 for (i = 0; i < n_archs; i++)
4535 if (!strcmp (arg, archs[i].name))
4537 unsigned long arch = archs[i].arch;
4538 if (cpu_of_arch (arch))
4539 /* It's a cpu spec. */
4541 current_architecture &= ~m68000up;
4542 current_architecture |= arch;
4544 else if (arch == m68881)
4546 current_architecture |= m68881;
4549 else if (arch == m68851)
4551 current_architecture |= m68851;
4561 as_bad ("unrecognized architecture specification `%s'", arg);
4570 break; /* -pic, Position Independent Code */
4572 case OPTION_REGISTER_PREFIX_OPTIONAL:
4573 flag_reg_prefix_optional = 1;
4588 md_show_usage (stream)
4593 -l use 1 word for refs to undefined symbols [default 2]\n\
4594 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
4595 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
4597 specify variant of 680X0 architecture [default 68020]\n\
4598 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
4599 target has/lacks floating-point coprocessor\n\
4600 [default yes for 68020, 68030, and cpu32]\n\
4601 -m68851 | -mno-68851\n\
4602 target has/lacks memory-management unit coprocessor\n\
4603 [default yes for 68020 and up]\n\
4604 -pic, -k generate position independent code\n\
4605 -S turn jbsr into jsr\n\
4606 --register-prefix-optional\n\
4607 recognize register names without prefix character\n");
4612 /* TEST2: Test md_assemble() */
4613 /* Warning, this routine probably doesn't work anymore */
4617 struct m68k_it the_ins;
4625 if (!gets (buf) || !*buf)
4627 if (buf[0] == '|' || buf[1] == '.')
4629 for (cp = buf; *cp; cp++)
4634 memset (&the_ins, '\0', sizeof (the_ins));
4635 m68k_ip (&the_ins, buf);
4638 printf ("Error %s in %s\n", the_ins.error, buf);
4642 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
4643 for (n = 0; n < the_ins.numo; n++)
4644 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
4646 print_the_insn (&the_ins.opcode[0], stdout);
4647 (void) putchar ('\n');
4649 for (n = 0; n < strlen (the_ins.args) / 2; n++)
4651 if (the_ins.operands[n].error)
4653 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
4656 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
4657 if (the_ins.operands[n].b_const)
4658 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
4659 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
4660 if (the_ins.operands[n].b_iadd)
4661 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
4662 (void) putchar ('\n');
4674 while (*str && *str != ' ')
4676 if (str[-1] == ':' || str[1] == '=')
4683 /* Possible states for relaxation:
4685 0 0 branch offset byte (bra, etc)
4689 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4693 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4700 /* We have no need to default values of symbols. */
4704 md_undefined_symbol (name)
4710 /* Round up a section size to the appropriate boundary. */
4712 md_section_align (segment, size)
4716 return size; /* Byte alignment is fine */
4719 /* Exactly what point is a PC-relative offset relative TO?
4720 On the 68k, it is relative to the address of the first extension
4721 word. The difference between the addresses of the offset and the
4722 first extension word is stored in fx_pcrel_adjust. */
4724 md_pcrel_from (fixP)
4727 return (fixP->fx_where + fixP->fx_frag->fr_address - fixP->fx_pcrel_adjust);
4730 #ifndef BFD_ASSEMBLER
4733 tc_coff_symbol_emit_hook (ignore)
4739 tc_coff_sizemachdep (frag)
4742 switch (frag->fr_subtype & 0x3)
4757 /* end of tc-m68k.c */