1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
29 /* This array holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful */
32 CONST char comment_chars[] = "|#";
34 CONST char comment_chars[] = "|";
37 /* This array holds the chars that only start a comment at the beginning of
38 a line. If the line seems to have the form '# 123 filename'
39 .line and .file directives will appear in the pre-processed output */
40 /* Note that input_file.c hand checks for '#' at the beginning of the
41 first line of the input file. This is because the compiler outputs
42 #NO_APP at the beginning of its output. */
43 /* Also note that comments like this one will always work. */
44 CONST char line_comment_chars[] = "#";
46 CONST char line_separator_chars[] = "";
48 /* Chars that can be used to separate mant from exp in floating point nums */
49 CONST char EXP_CHARS[] = "eE";
51 /* Chars that mean this number is a floating point constant, as
52 in "0f12.456" or "0d1.2345e12". */
54 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
56 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
57 changed in read.c . Ideally it shouldn't have to know about it at all,
58 but nothing is ideal around here. */
60 const int md_reloc_size = 8; /* Size of relocation record */
62 /* Are we trying to generate PIC code? If so, absolute references
63 ought to be made into linkage table references or pc-relative
67 static int flag_short_refs; /* -l option */
68 static int flag_long_jumps; /* -S option */
70 #ifdef REGISTER_PREFIX_OPTIONAL
71 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73 int flag_reg_prefix_optional;
76 /* Its an arbitrary name: This means I don't approve of it */
77 /* See flames below */
78 static struct obstack robyn;
80 #define TAB(x,y) (((x)<<2)+(y))
81 #define TABTYPE(xy) ((xy) >> 2)
87 /* Case `g' except when BCC68000 is applicable. */
89 /* Coprocessor branches. */
91 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
92 supported on all cpus. Widens to 32-bit absolute. */
94 /* For inserting an extra jmp instruction with long offset on 68000,
95 for expanding conditional branches. (Not bsr or bra.) Since the
96 68000 doesn't support 32-bit displacements for conditional
97 branches, we fake it by reversing the condition and branching
98 around a jmp with an absolute long operand. */
100 /* For the DBcc "instructions". If the displacement requires 32 bits,
101 the branch-around-a-jump game is played here too. */
103 /* Not currently used? */
105 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
111 const char *m_operands;
112 unsigned long m_opcode;
116 struct m68k_incant *m_next;
119 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
120 #define gettwo(x) (((x)->m_opcode)&0xffff)
122 static const enum m68k_register m68000_control_regs[] = { 0 };
123 static const enum m68k_register m68010_control_regs[] = {
127 static const enum m68k_register m68020_control_regs[] = {
128 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
131 static const enum m68k_register m68040_control_regs[] = {
132 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
133 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
136 static const enum m68k_register m68060_control_regs[] = {
137 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
138 USP, VBR, URP, SRP, PCR,
141 #define cpu32_control_regs m68010_control_regs
143 static const enum m68k_register *control_regs;
145 /* internal form of a 68020 instruction */
149 const char *args; /* list of opcode info */
152 int numo; /* Number of shorts in opcode */
155 struct m68k_op operands[6];
157 int nexp; /* number of exprs in use */
158 struct m68k_exp exprs[4];
160 int nfrag; /* Number of frags we have to produce */
163 int fragoff; /* Where in the current opcode the frag ends */
170 int nrel; /* Num of reloc strucs in use */
177 /* In a pc relative address the difference between the address
178 of the offset and the address that the offset is relative
179 to. This depends on the addressing mode. Basically this
180 is the value to put in the offset field to address the
181 first byte of the offset, without regarding the special
182 significance of some values (in the branch instruction, for
186 reloc[5]; /* Five is enough??? */
189 #define cpu_of_arch(x) ((x) & m68000up)
190 #define float_of_arch(x) ((x) & mfloat)
191 #define mmu_of_arch(x) ((x) & mmmu)
193 static struct m68k_it the_ins; /* the instruction being assembled */
195 #define op(ex) ((ex)->exp.X_op)
196 #define adds(ex) ((ex)->exp.X_add_symbol)
197 #define subs(ex) ((ex)->exp.X_op_symbol)
198 #define offs(ex) ((ex)->exp.X_add_number)
200 /* Macros for adding things to the m68k_it struct */
202 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
204 /* Like addword, but goes BEFORE general operands */
208 struct m68k_incant *opcode;
211 for(z=the_ins.numo;z>opcode->m_codenum;--z)
212 the_ins.opcode[z]=the_ins.opcode[z-1];
213 for(z=0;z<the_ins.nrel;z++)
214 the_ins.reloc[z].n+=2;
215 for (z = 0; z < the_ins.nfrag; z++)
216 the_ins.fragb[z].fragoff++;
217 the_ins.opcode[opcode->m_codenum]=w;
221 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
224 add_fix (width, exp, pc_rel, pc_fix)
226 struct m68k_exp *exp;
230 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
234 : (the_ins.numo*2)));
235 the_ins.reloc[the_ins.nrel].exp = exp->exp;
236 the_ins.reloc[the_ins.nrel].wid = width;
237 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
238 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
241 /* Cause an extra frag to be generated here, inserting up to 10 bytes
242 (that value is chosen in the frag_var call in md_assemble). TYPE
243 is the subtype of the frag to be generated; its primary type is
244 rs_machine_dependent.
246 The TYPE parameter is also used by md_convert_frag_1 and
247 md_estimate_size_before_relax. The appropriate type of fixup will
248 be emitted by md_convert_frag_1.
250 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
252 add_frag(add,off,type)
257 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
258 the_ins.fragb[the_ins.nfrag].fadd=add;
259 the_ins.fragb[the_ins.nfrag].foff=off;
260 the_ins.fragb[the_ins.nfrag++].fragty=type;
264 (op (ex) != O_constant && op (ex) != O_big)
266 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
267 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
268 static int reverse_16_bits PARAMS ((int in));
269 static int reverse_8_bits PARAMS ((int in));
270 static void install_gen_operand PARAMS ((int mode, int val));
271 static void install_operand PARAMS ((int mode, int val));
272 static void s_bss PARAMS ((int));
273 static void s_data1 PARAMS ((int));
274 static void s_data2 PARAMS ((int));
275 static void s_even PARAMS ((int));
276 static void s_proc PARAMS ((int));
277 static void mri_chip PARAMS ((void));
278 static void s_chip PARAMS ((int));
280 static int current_architecture;
287 static const struct m68k_cpu archs[] = {
297 /* Aliases (effectively, so far as gas is concerned) for the above
302 { m68000, "68ec000" },
303 { m68000, "68hc000" },
304 { m68000, "68hc001" },
305 { m68020, "68ec020" },
306 { m68030, "68ec030" },
307 { m68040, "68ec040" },
317 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
319 /* BCC68000 is for patching in an extra jmp instruction for long offsets
320 on the 68000. The 68000 doesn't support long branches with branchs */
322 /* This table desribes how you change sizes for the various types of variable
323 size expressions. This version only supports two kinds. */
325 /* Note that calls to frag_var need to specify the maximum expansion
326 needed; this is currently 10 bytes for DBCC. */
329 How far Forward this mode will reach:
330 How far Backward this mode will reach:
331 How many bytes this mode will add to the size of the frag
332 Which mode to go to if the offset won't fit in this one
334 relax_typeS md_relax_table[] =
336 {1, 1, 0, 0}, /* First entries aren't used */
337 {1, 1, 0, 0}, /* For no good reason except */
338 {1, 1, 0, 0}, /* that the VAX doesn't either */
341 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
342 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
346 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
347 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
351 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
352 {(32767), (-32768), 2, TAB (PCREL, LONG)},
356 {(127), (-128), 0, TAB (BCC68000, SHORT)},
357 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
358 {0, 0, 6, 0}, /* jmp long space */
361 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
362 {(32767), (-32768), 2, TAB (DBCC, LONG)},
363 {0, 0, 10, 0}, /* bra/jmp long space */
366 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
367 {32767, -32768, 2, TAB (PCLEA, LONG)},
371 /* For, e.g., jmp pcrel indexed. */
372 {125, -130, 0, TAB (PCINDEX, SHORT)},
373 {32765, -32770, 2, TAB (PCINDEX, LONG)},
378 /* These are the machine dependent pseudo-ops. These are included so
379 the assembler can work on the output from the SUN C compiler, which
383 /* This table describes all the machine specific pseudo-ops the assembler
384 has to support. The fields are:
385 pseudo-op name without dot
386 function to call to execute this pseudo-op
387 Integer arg to pass to the function
389 CONST pseudo_typeS md_pseudo_table[] =
391 {"data1", s_data1, 0},
392 {"data2", s_data2, 0},
395 {"skip", s_space, 0},
398 {"align", s_align_bytes, 0},
401 {"swbeg", s_ignore, 0},
404 /* The following pseudo-ops are supported for MRI compatibility. */
406 {"comline", s_space, 1},
412 /* The mote pseudo ops are put into the opcode table, since they
413 don't start with a . they look like opcodes to gas.
415 extern void obj_coff_section ();
417 CONST pseudo_typeS mote_pseudo_table[] =
430 {"xdef", s_globl, 0},
431 {"align", s_align_ptwo, 0},
433 {"sect", obj_coff_section, 0},
434 {"section", obj_coff_section, 0},
439 #define issbyte(x) ((x)>=-128 && (x)<=127)
440 #define isubyte(x) ((x)>=0 && (x)<=255)
441 #define issword(x) ((x)>=-32768 && (x)<=32767)
442 #define isuword(x) ((x)>=0 && (x)<=65535)
444 #define isbyte(x) ((x)>= -255 && (x)<=255)
445 #define isword(x) ((x)>=-32768 && (x)<=65535)
446 #define islong(x) (1)
448 extern char *input_line_pointer;
450 static char mklower_table[256];
451 #define mklower(c) (mklower_table[(unsigned char)(c)])
452 static char notend_table[256];
453 static char alt_notend_table[256];
455 (! (notend_table[(unsigned char) *s] \
457 && alt_notend_table[(unsigned char) s[1]])))
459 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
461 #ifdef NO_PCREL_RELOCS
464 make_pcrel_absolute(fixP, add_number)
468 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
470 /* rewrite the PC relative instructions to absolute address ones.
471 * these are rumoured to be faster, and the apollo linker refuses
472 * to deal with the PC relative relocations.
474 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
479 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
485 as_fatal ("Unknown PC relative instruction");
490 #endif /* NO_PCREL_RELOCS */
493 tc_coff_fix2rtype (fixP)
496 #ifdef NO_PCREL_RELOCS
497 know (fixP->fx_pcrel == 0);
498 return (fixP->fx_size == 1 ? R_RELBYTE
499 : fixP->fx_size == 2 ? R_DIR16
502 return (fixP->fx_pcrel ?
503 (fixP->fx_size == 1 ? R_PCRBYTE :
504 fixP->fx_size == 2 ? R_PCRWORD :
506 (fixP->fx_size == 1 ? R_RELBYTE :
507 fixP->fx_size == 2 ? R_RELWORD :
517 tc_gen_reloc (section, fixp)
522 bfd_reloc_code_real_type code;
524 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
525 switch (F (fixp->fx_size, fixp->fx_pcrel))
527 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
528 MAP (1, 0, BFD_RELOC_8);
529 MAP (2, 0, BFD_RELOC_16);
530 MAP (4, 0, BFD_RELOC_32);
531 MAP (1, 1, BFD_RELOC_8_PCREL);
532 MAP (2, 1, BFD_RELOC_16_PCREL);
533 MAP (4, 1, BFD_RELOC_32_PCREL);
538 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
540 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
541 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
543 reloc->addend = fixp->fx_addnumber;
547 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
548 assert (reloc->howto != 0);
553 #endif /* BFD_ASSEMBLER */
555 /* Handle of the OPCODE hash table. NULL means any use before
556 m68k_ip_begin() will crash. */
557 static struct hash_control *op_hash;
559 /* Assemble an m68k instruction. */
566 register struct m68k_op *opP;
567 register struct m68k_incant *opcode;
568 register const char *s;
569 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
570 char *pdot, *pdotmove;
571 enum m68k_size siz1, siz2;
575 char *crack_operand ();
576 LITTLENUM_TYPE words[6];
577 LITTLENUM_TYPE *wordp;
578 unsigned long ok_arch = 0;
580 if (*instring == ' ')
581 instring++; /* skip leading whitespace */
583 /* Scan up to end of operation-code, which MUST end in end-of-string
584 or exactly 1 space. */
586 for (p = instring; *p != '\0'; p++)
596 the_ins.error = "No operator";
600 /* p now points to the end of the opcode name, probably whitespace.
601 Make sure the name is null terminated by clobbering the
602 whitespace, look it up in the hash table, then fix it back.
603 Remove a dot, first, since the opcode tables have none. */
606 for (pdotmove = pdot; pdotmove < p; pdotmove++)
607 *pdotmove = pdotmove[1];
613 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
618 for (pdotmove = p; pdotmove > pdot; pdotmove--)
619 *pdotmove = pdotmove[-1];
626 the_ins.error = "Unknown operator";
630 /* found a legitimate opcode, start matching operands */
634 if (opcode->m_operands == 0)
636 char *old = input_line_pointer;
638 input_line_pointer = p;
639 /* Ahh - it's a motorola style psuedo op */
640 mote_pseudo_table[opcode->m_opnum].poc_handler
641 (mote_pseudo_table[opcode->m_opnum].poc_val);
642 input_line_pointer = old;
648 for (opP = &the_ins.operands[0]; *p; opP++)
650 p = crack_operand (p, opP);
654 the_ins.error = opP->error;
659 opsfound = opP - &the_ins.operands[0];
661 /* This ugly hack is to support the floating pt opcodes in their
662 standard form. Essentially, we fake a first enty of type COP#1 */
663 if (opcode->m_operands[0] == 'I')
667 for (n = opsfound; n > 0; --n)
668 the_ins.operands[n] = the_ins.operands[n - 1];
670 memset ((char *) (&the_ins.operands[0]), '\0',
671 sizeof (the_ins.operands[0]));
672 the_ins.operands[0].mode = CONTROL;
673 the_ins.operands[0].reg = COPNUM; /* COP #1 */
677 /* We've got the operands. Find an opcode that'll accept them */
680 /* If we didn't get the right number of ops, or we have no
681 common model with this pattern then reject this pattern. */
683 if (opsfound != opcode->m_opnum
684 || ((opcode->m_arch & current_architecture) == 0))
687 ok_arch |= opcode->m_arch;
691 for (s = opcode->m_operands, opP = &the_ins.operands[0];
695 /* Warning: this switch is huge! */
696 /* I've tried to organize the cases into this order:
697 non-alpha first, then alpha by letter. Lower-case
698 goes directly before uppercase counterpart. */
699 /* Code with multiple case ...: gets sorted by the lowest
700 case ... it belongs to. I hope this makes sense. */
740 if (opP->mode != IMMED)
743 && ! isvar (&opP->disp)
744 && ! expr8 (&opP->disp))
747 && ! isvar (&opP->disp)
748 && ! expr16 (&opP->disp))
754 if (opP->mode != IMMED)
759 if (opP->mode == AREG
760 || opP->mode == CONTROL
761 || opP->mode == FPREG
762 || opP->mode == IMMED
763 || opP->mode == REGLST
764 || (opP->mode != ABSL
766 || opP->reg == ZPC)))
771 if (opP->mode == CONTROL
772 || opP->mode == FPREG
773 || opP->mode == REGLST
774 || (opP->mode != ABSL
775 && opP->mode != IMMED
777 || opP->reg == ZPC)))
805 if (opP->mode == CONTROL
806 || opP->mode == FPREG
807 || opP->mode == REGLST)
812 if (opP->mode != AINC)
817 if (opP->mode != ADEC)
867 if (opP->reg == PC || opP->reg == ZPC)
888 case '~': /* For now! (JF FOO is this right?) */
910 if (opP->mode != CONTROL
911 || (opP->reg != TT0 && opP->reg != TT1))
916 if (opP->mode != AREG)
921 if (opP->mode != AINDR)
926 if (opP->mode != ABSL
928 && strncmp (instring, "jbsr", 4) == 0))
933 if (opP->mode != CONTROL || opP->reg != CCR)
938 if (opP->mode != DISP
945 if (opP->mode != DREG)
950 if (opP->mode != FPREG)
955 if (opP->mode != CONTROL
957 || opP->reg >= COPNUM + 7)
962 if (opP->mode != CONTROL
964 || opP->reg > last_movec_reg)
968 const enum m68k_register *rp;
969 for (rp = control_regs; *rp; rp++)
978 if (opP->mode != IMMED)
984 if (opP->mode == DREG
986 || opP->mode == FPREG)
995 opP->mask = 1 << (opP->reg - DATA0);
998 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1001 opP->mask = 1 << (opP->reg - FP0 + 16);
1009 else if (opP->mode == CONTROL)
1018 opP->mask = 1 << 24;
1021 opP->mask = 1 << 25;
1024 opP->mask = 1 << 26;
1033 else if (opP->mode != REGLST)
1035 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1037 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1042 if (opP->mode != IMMED)
1044 else if (! expr8 (&opP->disp))
1049 if (opP->mode != DREG && opP->mode != IMMED)
1054 if (opP->mode != IMMED)
1056 else if (! expr8 (&opP->disp)
1057 || opP->disp.exp.X_add_number < 1
1058 || opP->disp.exp.X_add_number > 8)
1063 if (opP->mode != DREG && opP->mode != AREG)
1068 if (opP->mode != AINDR
1069 && (opP->mode != BASE
1071 && opP->reg != ZADDR0)
1072 || opP->disp.exp.X_op != O_absent
1073 || ((opP->index.reg < DATA0
1074 || opP->index.reg > DATA7)
1075 && (opP->index.reg < ADDR0
1076 || opP->index.reg > ADDR7))
1077 || opP->index.size != SIZE_UNSPEC
1078 || opP->index.scale != 1))
1083 if (opP->mode != CONTROL
1084 || ! (opP->reg == FPI
1086 || opP->reg == FPC))
1091 if (opP->mode != CONTROL || opP->reg != SR)
1096 if (opP->mode != IMMED)
1098 else if (! expr8 (&opP->disp)
1099 || opP->disp.exp.X_add_number < 0
1100 || opP->disp.exp.X_add_number > 7)
1105 if (opP->mode != CONTROL || opP->reg != USP)
1109 /* JF these are out of order. We could put them
1110 in order if we were willing to put up with
1111 bunches of #ifdef m68851s in the code.
1113 Don't forget that you need these operands
1114 to use 68030 MMU instructions. */
1116 /* Memory addressing mode used by pflushr */
1118 if (opP->mode == CONTROL
1119 || opP->mode == FPREG
1120 || opP->mode == DREG
1121 || opP->mode == AREG
1122 || opP->mode == REGLST)
1127 if (opP->mode != CONTROL
1128 || (opP->reg != SFC && opP->reg != DFC))
1133 if (opP->mode != CONTROL
1143 if (opP->mode != CONTROL
1149 if (opP->mode != CONTROL
1152 && opP->reg != CRP))
1157 if (opP->mode != CONTROL
1158 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1159 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1164 if (opP->mode != CONTROL || opP->reg != PSR)
1169 if (opP->mode != CONTROL || opP->reg != PCSR)
1174 if (opP->mode != CONTROL
1181 } /* not a cache specifier. */
1185 if (opP->mode != ABSL)
1191 } /* switch on type of operand */
1195 } /* for each operand */
1196 } /* if immediately wrong */
1203 opcode = opcode->m_next;
1208 && !(ok_arch & current_architecture))
1213 "invalid instruction for this architecture; needs ");
1214 cp = buf + strlen (buf);
1218 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1221 strcpy (cp, "mmu (68030 or 68851)");
1224 strcpy (cp, "68020 or higher");
1227 strcpy (cp, "68000 or higher");
1230 strcpy (cp, "68010 or higher");
1234 int got_one = 0, idx;
1235 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1238 if (archs[idx].arch & ok_arch)
1242 strcpy (cp, " or ");
1246 strcpy (cp, archs[idx].name);
1258 the_ins.error = "operands mismatch";
1260 } /* Fell off the end */
1265 /* now assemble it */
1267 the_ins.args = opcode->m_operands;
1268 the_ins.numargs = opcode->m_opnum;
1269 the_ins.numo = opcode->m_codenum;
1270 the_ins.opcode[0] = getone (opcode);
1271 the_ins.opcode[1] = gettwo (opcode);
1273 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1275 /* This switch is a doozy.
1276 Watch the first step; its a big one! */
1297 tmpreg = 0x3c; /* 7.4 */
1298 if (strchr ("bwl", s[1]))
1299 nextword = get_num (&opP->disp, 80);
1301 nextword = get_num (&opP->disp, 0);
1302 if (isvar (&opP->disp))
1303 add_fix (s[1], &opP->disp, 0, 0);
1307 if (!isbyte (nextword))
1308 opP->error = "operand out of range";
1313 if (!isword (nextword))
1314 opP->error = "operand out of range";
1319 addword (nextword >> 16);
1346 /* We gotta put out some float */
1347 if (op (&opP->disp) != O_big)
1352 /* Can other cases happen here? */
1353 if (op (&opP->disp) != O_constant)
1356 val = (valueT) offs (&opP->disp);
1360 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1361 val >>= LITTLENUM_NUMBER_OF_BITS;
1365 offs (&opP->disp) = gencnt;
1367 if (offs (&opP->disp) > 0)
1369 if (offs (&opP->disp) > baseo)
1371 as_warn ("Bignum too big for %c format; truncated",
1373 offs (&opP->disp) = baseo;
1375 baseo -= offs (&opP->disp);
1378 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1379 offs (&opP->disp)--;
1384 gen_to_words (words, baseo, (long) outro);
1385 for (wordp = words; baseo--; wordp++)
1389 tmpreg = opP->reg - DATA; /* 0.dreg */
1392 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1395 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1398 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1401 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1405 nextword = get_num (&opP->disp, 80);
1406 /* Force into index mode. Hope this works */
1408 /* We do the first bit for 32-bit displacements, and the
1409 second bit for 16 bit ones. It is possible that we
1410 should make the default be WORD instead of LONG, but
1411 I think that'd break GCC, so we put up with a little
1412 inefficiency for the sake of working output. */
1414 if (!issword (nextword)
1415 || (isvar (&opP->disp)
1416 && ((opP->disp.size == SIZE_UNSPEC
1417 && flag_short_refs == 0
1418 && cpu_of_arch (current_architecture) >= m68020)
1419 || opP->disp.size == SIZE_LONG)))
1422 tmpreg = 0x3B; /* 7.3 */
1424 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1425 if (isvar (&opP->disp))
1431 add_fix ('l', &opP->disp, 1, 2);
1432 addword (0), addword (0);
1434 add_frag (adds (&opP->disp),
1436 TAB (PCLEA, SZ_UNDEF));
1443 add_fix ('l', &opP->disp, 0, 0);
1448 addword (nextword >> 16);
1453 tmpreg = 0x3A; /* 7.2 */
1455 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1457 if (isvar (&opP->disp))
1461 add_fix ('w', &opP->disp, 1, 0);
1464 add_fix ('w', &opP->disp, 0, 0);
1474 baseo = get_num (&opP->disp, 80);
1475 if (opP->mode == POST || opP->mode == PRE)
1476 outro = get_num (&opP->odisp, 80);
1477 /* Figure out the `addressing mode'.
1478 Also turn on the BASE_DISABLE bit, if needed. */
1479 if (opP->reg == PC || opP->reg == ZPC)
1481 tmpreg = 0x3b; /* 7.3 */
1482 if (opP->reg == ZPC)
1485 else if (opP->reg == 0)
1488 tmpreg = 0x30; /* 6.garbage */
1490 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1493 tmpreg = 0x30 + opP->reg - ZADDR0;
1496 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1498 siz1 = opP->disp.size;
1499 if (opP->mode == POST || opP->mode == PRE)
1500 siz2 = opP->odisp.size;
1504 /* Index register stuff */
1505 if (opP->index.reg != 0
1506 && opP->index.reg >= DATA
1507 && opP->index.reg <= ADDR7)
1509 nextword |= (opP->index.reg - DATA) << 12;
1511 if (opP->index.size == SIZE_UNSPEC
1512 || opP->index.size == SIZE_LONG)
1515 if (cpu_of_arch (current_architecture) < m68020)
1517 if (opP->index.scale != 1)
1520 "scale factor invalid on this architecture; needs 68020 or higher";
1524 switch (opP->index.scale)
1541 GET US OUT OF HERE! */
1543 /* Must be INDEX, with an index register. Address
1544 register cannot be ZERO-PC, and either :b was
1545 forced, or we know it will fit. For a 68000 or
1546 68010, force this mode anyways, because the
1547 larger modes aren't supported. */
1548 if (opP->mode == BASE
1549 && ((opP->reg >= ADDR0
1550 && opP->reg <= ADDR7)
1553 if (siz1 == SIZE_BYTE
1554 || cpu_of_arch (current_architecture) < m68020
1555 || (siz1 == SIZE_UNSPEC
1556 && ! isvar (&opP->disp)
1557 && issbyte (baseo)))
1559 nextword += baseo & 0xff;
1561 if (isvar (&opP->disp))
1563 /* Do a byte relocation. If it doesn't
1564 fit (possible on m68000) let the
1565 fixup processing complain later. */
1567 add_fix ('B', &opP->disp, 1, 1);
1569 add_fix ('B', &opP->disp, 0, 0);
1571 else if (siz1 != SIZE_BYTE)
1573 if (siz1 != SIZE_UNSPEC)
1574 as_warn ("Forcing byte displacement");
1575 if (! issbyte (baseo))
1576 opP->error = "byte displacement out of range";
1581 else if (siz1 == SIZE_UNSPEC
1583 && isvar (&opP->disp)
1584 && subs (&opP->disp) == NULL)
1586 nextword += baseo & 0xff;
1588 add_frag (adds (&opP->disp), offs (&opP->disp),
1589 TAB (PCINDEX, SZ_UNDEF));
1597 nextword |= 0x40; /* No index reg */
1598 if (opP->index.reg >= ZDATA0
1599 && opP->index.reg <= ZDATA7)
1600 nextword |= (opP->index.reg - ZDATA0) << 12;
1601 else if (opP->index.reg >= ZADDR0
1602 || opP->index.reg <= ZADDR7)
1603 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1606 /* It isn't simple. */
1608 if (cpu_of_arch (current_architecture) < m68020)
1610 "invalid operand mode for this architecture; needs 68020 or higher";
1613 /* If the guy specified a width, we assume that it is
1614 wide enough. Maybe it isn't. If so, we lose. */
1618 if (isvar (&opP->disp) || !issword (baseo))
1623 else if (baseo == 0)
1632 as_warn (":b not permitted; defaulting to :w");
1642 /* Figure out innner displacement stuff */
1643 if (opP->mode == POST || opP->mode == PRE)
1648 if (isvar (&opP->odisp) || !issword (outro))
1653 else if (outro == 0)
1662 as_warn (":b not permitted; defaulting to :w");
1671 if (opP->mode == POST)
1676 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
1678 if (opP->reg == PC || opP->reg == ZPC)
1679 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
1681 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
1683 if (siz1 == SIZE_LONG)
1684 addword (baseo >> 16);
1685 if (siz1 != SIZE_UNSPEC)
1688 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1689 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1690 if (siz2 == SIZE_LONG)
1691 addword (outro >> 16);
1692 if (siz2 != SIZE_UNSPEC)
1698 nextword = get_num (&opP->disp, 80);
1699 switch (opP->disp.size)
1704 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
1706 tmpreg = 0x38; /* 7.0 */
1710 /* Don't generate pc relative code on 68010 and
1712 if (isvar (&opP->disp)
1713 && !subs (&opP->disp)
1714 && adds (&opP->disp)
1715 && (S_GET_SEGMENT (adds (&opP->disp)) == text_section)
1716 && now_seg == text_section
1717 && cpu_of_arch (current_architecture) >= m68020
1719 && !strchr ("~%&$?", s[0]))
1721 tmpreg = 0x3A; /* 7.2 */
1722 add_frag (adds (&opP->disp),
1724 TAB (PCREL, SZ_UNDEF));
1727 /* Fall through into long */
1729 if (isvar (&opP->disp))
1730 add_fix ('l', &opP->disp, 0, 0);
1732 tmpreg = 0x39;/* 7.1 mode */
1733 addword (nextword >> 16);
1737 case SIZE_WORD: /* Word */
1738 if (isvar (&opP->disp))
1739 add_fix ('w', &opP->disp, 0, 0);
1741 tmpreg = 0x38;/* 7.0 mode */
1749 as_bad ("unknown/incorrect operand");
1752 install_gen_operand (s[1], tmpreg);
1758 { /* JF: I hate floating point! */
1773 tmpreg = get_num (&opP->disp, tmpreg);
1774 if (isvar (&opP->disp))
1775 add_fix (s[1], &opP->disp, 0, 0);
1778 case 'b': /* Danger: These do no check for
1779 certain types of overflow.
1781 if (!isbyte (tmpreg))
1782 opP->error = "out of range";
1783 insop (tmpreg, opcode);
1784 if (isvar (&opP->disp))
1785 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1788 if (!isword (tmpreg))
1789 opP->error = "out of range";
1790 insop (tmpreg, opcode);
1791 if (isvar (&opP->disp))
1792 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1795 /* Because of the way insop works, we put these two out
1797 insop (tmpreg, opcode);
1798 insop (tmpreg >> 16, opcode);
1799 if (isvar (&opP->disp))
1800 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1806 install_operand (s[1], tmpreg);
1817 install_operand (s[1], opP->reg - ADDR);
1821 tmpreg = get_num (&opP->disp, 80);
1825 add_fix ('B', &opP->disp, 1, -1);
1828 add_fix ('w', &opP->disp, 1, 0);
1833 if (cpu_of_arch (current_architecture) < m68020)
1834 as_warn ("Can't use long branches on 68000/68010");
1835 the_ins.opcode[the_ins.numo - 1] |= 0xff;
1836 add_fix ('l', &opP->disp, 1, 0);
1841 if (subs (&opP->disp)) /* We can't relax it */
1844 /* This could either be a symbol, or an absolute
1845 address. No matter, the frag hacking will finger it
1846 out. Not quite: it can't switch from BRANCH to
1847 BCC68000 for the case where opnd is absolute (it
1848 needs to use the 68000 hack since no conditional abs
1850 if (((cpu_of_arch (current_architecture) < m68020)
1851 || (0 == adds (&opP->disp)))
1852 && (the_ins.opcode[0] >= 0x6200)
1853 && (the_ins.opcode[0] <= 0x6f00))
1854 add_frag (adds (&opP->disp), offs (&opP->disp),
1855 TAB (BCC68000, SZ_UNDEF));
1857 add_frag (adds (&opP->disp), offs (&opP->disp),
1858 TAB (ABRANCH, SZ_UNDEF));
1861 if (isvar (&opP->disp))
1864 /* check for DBcc instruction */
1865 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
1867 /* size varies if patch */
1868 /* needed for long form */
1869 add_frag (adds (&opP->disp), offs (&opP->disp),
1870 TAB (DBCC, SZ_UNDEF));
1874 add_fix ('w', &opP->disp, 1, 0);
1878 case 'C': /* Fixed size LONG coproc branches */
1879 add_fix ('l', &opP->disp, 1, 0);
1883 case 'c': /* Var size Coprocesssor branches */
1884 if (subs (&opP->disp))
1886 add_fix ('l', &opP->disp, 1, 0);
1887 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
1889 else if (adds (&opP->disp))
1890 add_frag (adds (&opP->disp), offs (&opP->disp),
1891 TAB (FBRANCH, SZ_UNDEF));
1894 /* add_frag((symbolS *) 0, offs(&opP->disp),
1895 TAB(FBRANCH,SHORT)); */
1896 the_ins.opcode[the_ins.numo - 1] |= 0x40;
1897 add_fix ('l', &opP->disp, 1, 0);
1907 case 'C': /* Ignore it */
1910 case 'd': /* JF this is a kludge */
1911 install_operand ('s', opP->reg - ADDR);
1912 tmpreg = get_num (&opP->disp, 80);
1913 if (!issword (tmpreg))
1915 as_warn ("Expression out of range, using 0");
1922 install_operand (s[1], opP->reg - DATA);
1926 install_operand (s[1], opP->reg - FP0);
1930 tmpreg = 1 + opP->reg - COPNUM;
1933 install_operand (s[1], tmpreg);
1936 case 'J': /* JF foo */
1997 install_operand (s[1], tmpreg);
2001 tmpreg = get_num (&opP->disp, 55);
2002 install_operand (s[1], tmpreg & 0x7f);
2009 if (tmpreg & 0x7FF0000)
2010 as_bad ("Floating point register in register list");
2011 insop (reverse_16_bits (tmpreg), opcode);
2015 if (tmpreg & 0x700FFFF)
2016 as_bad ("Wrong register in floating-point reglist");
2017 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2025 if (tmpreg & 0x7FF0000)
2026 as_bad ("Floating point register in register list");
2027 insop (tmpreg, opcode);
2029 else if (s[1] == '8')
2031 if (tmpreg & 0x0FFFFFF)
2032 as_bad ("incorrect register in reglist");
2033 install_operand (s[1], tmpreg >> 24);
2037 if (tmpreg & 0x700FFFF)
2038 as_bad ("wrong register in floating-point reglist");
2040 install_operand (s[1], tmpreg >> 16);
2045 install_operand (s[1], get_num (&opP->disp, 60));
2049 tmpreg = ((opP->mode == DREG)
2050 ? 0x20 + opP->reg - DATA
2051 : (get_num (&opP->disp, 40) & 0x1F));
2052 install_operand (s[1], tmpreg);
2056 tmpreg = get_num (&opP->disp, 10);
2059 install_operand (s[1], tmpreg);
2063 /* This depends on the fact that ADDR registers are eight
2064 more than their corresponding DATA regs, so the result
2065 will have the ADDR_REG bit set */
2066 install_operand (s[1], opP->reg - DATA);
2070 if (opP->mode == AINDR)
2071 install_operand (s[1], opP->reg - DATA);
2073 install_operand (s[1], opP->index.reg - DATA);
2077 if (opP->reg == FPI)
2079 else if (opP->reg == FPS)
2081 else if (opP->reg == FPC)
2085 install_operand (s[1], tmpreg);
2088 case 'S': /* Ignore it */
2092 install_operand (s[1], get_num (&opP->disp, 30));
2095 case 'U': /* Ignore it */
2114 as_fatal ("failed sanity check");
2115 } /* switch on cache token */
2116 install_operand (s[1], tmpreg);
2119 /* JF: These are out of order, I fear. */
2132 install_operand (s[1], tmpreg);
2156 install_operand (s[1], tmpreg);
2160 if (opP->reg == VAL)
2179 install_operand (s[1], tmpreg);
2193 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2204 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2210 install_operand (s[1], tmpreg);
2213 know (opP->reg == PSR);
2216 know (opP->reg == PCSR);
2231 install_operand (s[1], tmpreg);
2234 tmpreg = get_num (&opP->disp, 20);
2235 install_operand (s[1], tmpreg);
2237 case '_': /* used only for move16 absolute 32-bit address */
2238 tmpreg = get_num (&opP->disp, 80);
2239 addword (tmpreg >> 16);
2240 addword (tmpreg & 0xFFFF);
2247 /* By the time whe get here (FINALLY) the_ins contains the complete
2248 instruction, ready to be emitted. . . */
2252 reverse_16_bits (in)
2258 static int mask[16] =
2260 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2261 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2263 for (n = 0; n < 16; n++)
2266 out |= mask[15 - n];
2269 } /* reverse_16_bits() */
2278 static int mask[8] =
2280 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2283 for (n = 0; n < 8; n++)
2289 } /* reverse_8_bits() */
2291 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2292 (that value is chosen in the frag_var call in md_assemble). TYPE
2293 is the subtype of the frag to be generated; its primary type is
2294 rs_machine_dependent.
2296 The TYPE parameter is also used by md_convert_frag_1 and
2297 md_estimate_size_before_relax. The appropriate type of fixup will
2298 be emitted by md_convert_frag_1.
2300 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2302 install_operand (mode, val)
2309 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2312 the_ins.opcode[0] |= val << 9;
2315 the_ins.opcode[1] |= val << 12;
2318 the_ins.opcode[1] |= val << 6;
2321 the_ins.opcode[1] |= val;
2324 the_ins.opcode[2] |= val << 12;
2327 the_ins.opcode[2] |= val << 6;
2330 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2331 three words long! */
2333 the_ins.opcode[2] |= val;
2336 the_ins.opcode[1] |= val << 7;
2339 the_ins.opcode[1] |= val << 10;
2343 the_ins.opcode[1] |= val << 5;
2348 the_ins.opcode[1] |= (val << 10) | (val << 7);
2351 the_ins.opcode[1] |= (val << 12) | val;
2354 the_ins.opcode[0] |= val = 0xff;
2357 the_ins.opcode[0] |= val << 9;
2360 the_ins.opcode[1] |= val;
2363 the_ins.opcode[1] |= val;
2364 the_ins.numo++; /* What a hack */
2367 the_ins.opcode[1] |= val << 4;
2374 the_ins.opcode[0] |= (val << 6);
2377 the_ins.opcode[1] = (val >> 16);
2378 the_ins.opcode[2] = val & 0xffff;
2382 as_fatal ("failed sanity check.");
2384 } /* install_operand() */
2387 install_gen_operand (mode, val)
2394 the_ins.opcode[0] |= val;
2397 /* This is a kludge!!! */
2398 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2407 the_ins.opcode[0] |= val;
2409 /* more stuff goes here */
2411 as_fatal ("failed sanity check.");
2413 } /* install_gen_operand() */
2416 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2417 * then deal with the bitfield hack.
2421 crack_operand (str, opP)
2423 register struct m68k_op *opP;
2425 register int parens;
2427 register char *beg_str;
2434 for (parens = 0; *str && (parens > 0 || notend (str)); str++)
2438 else if (*str == ')')
2442 opP->error = "Extra )";
2448 if (!*str && parens)
2450 opP->error = "Missing )";
2455 if (m68k_ip_op (beg_str, opP) != 0)
2462 c = *++str; /* JF bitfield hack */
2467 as_bad ("Missing operand");
2472 /* This is the guts of the machine-dependent assembler. STR points to a
2473 machine dependent instruction. This function is supposed to emit
2474 the frags/bytes it assembles to.
2478 insert_reg (regname, regnum)
2485 #ifdef REGISTER_PREFIX
2486 if (!flag_reg_prefix_optional)
2488 buf[0] = REGISTER_PREFIX;
2489 strcpy (buf + 1, regname);
2494 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2495 &zero_address_frag));
2497 for (i = 0; regname[i]; i++)
2498 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2501 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2502 &zero_address_frag));
2511 static const struct init_entry init_table[] =
2621 /* 68ec030 versions of same */
2624 /* 68ec030 access control unit, identical to 030 MMU status reg */
2627 /* Suppressed data and address registers. */
2652 for (i = 0; init_table[i].name; i++)
2653 insert_reg (init_table[i].name, init_table[i].number);
2656 static int no_68851, no_68881;
2659 /* a.out machine type. Default to 68020. */
2660 int m68k_aout_machtype = 2;
2672 int shorts_this_frag;
2675 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
2680 for (n = 0; n < the_ins.numargs; n++)
2681 if (the_ins.operands[n].error)
2683 er = the_ins.operands[n].error;
2689 as_bad ("%s -- statement `%s' ignored", er, str);
2693 if (the_ins.nfrag == 0)
2695 /* No frag hacking involved; just put it out */
2696 toP = frag_more (2 * the_ins.numo);
2697 fromP = &the_ins.opcode[0];
2698 for (m = the_ins.numo; m; --m)
2700 md_number_to_chars (toP, (long) (*fromP), 2);
2704 /* put out symbol-dependent info */
2705 for (m = 0; m < the_ins.nrel; m++)
2707 switch (the_ins.reloc[m].wid)
2725 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2726 the_ins.reloc[m].wid);
2729 fixP = fix_new_exp (frag_now,
2730 ((toP - frag_now->fr_literal)
2731 - the_ins.numo * 2 + the_ins.reloc[m].n),
2733 &the_ins.reloc[m].exp,
2734 the_ins.reloc[m].pcrel,
2736 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2741 /* There's some frag hacking */
2742 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2747 wid = 2 * the_ins.fragb[n].fragoff;
2749 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2750 toP = frag_more (wid);
2752 shorts_this_frag = 0;
2753 for (m = wid / 2; m; --m)
2755 md_number_to_chars (toP, (long) (*fromP), 2);
2760 for (m = 0; m < the_ins.nrel; m++)
2762 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
2764 the_ins.reloc[m].n -= 2 * shorts_this_frag;
2767 wid = the_ins.reloc[m].wid;
2770 the_ins.reloc[m].wid = 0;
2771 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2773 fixP = fix_new_exp (frag_now,
2774 ((toP - frag_now->fr_literal)
2775 - the_ins.numo * 2 + the_ins.reloc[m].n),
2777 &the_ins.reloc[m].exp,
2778 the_ins.reloc[m].pcrel,
2780 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2782 (void) frag_var (rs_machine_dependent, 10, 0,
2783 (relax_substateT) (the_ins.fragb[n].fragty),
2784 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
2786 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2787 shorts_this_frag = 0;
2790 toP = frag_more (n * sizeof (short));
2793 md_number_to_chars (toP, (long) (*fromP), 2);
2799 for (m = 0; m < the_ins.nrel; m++)
2803 wid = the_ins.reloc[m].wid;
2806 the_ins.reloc[m].wid = 0;
2807 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2809 fixP = fix_new_exp (frag_now,
2810 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
2811 - shorts_this_frag * 2),
2813 &the_ins.reloc[m].exp,
2814 the_ins.reloc[m].pcrel,
2816 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2824 * md_begin -- set up hash tables with 68000 instructions.
2825 * similar to what the vax assembler does. ---phr
2827 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2828 a copy of it at runtime, adding in the information we want but isn't
2829 there. I think it'd be better to have an awk script hack the table
2830 at compile time. Or even just xstr the table and use it as-is. But
2831 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2834 register const struct m68k_opcode *ins;
2835 register struct m68k_incant *hack, *slak;
2836 register const char *retval = 0; /* empty string, or error msg text */
2837 register unsigned int i;
2841 flag_reg_prefix_optional = 1;
2843 op_hash = hash_new ();
2845 obstack_begin (&robyn, 4000);
2846 for (i = 0; i < m68k_numopcodes; i++)
2848 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
2851 ins = &m68k_opcodes[i];
2852 /* We *could* ignore insns that don't match our arch here
2853 but just leaving them out of the hash. */
2854 slak->m_operands = ins->args;
2855 slak->m_opnum = strlen (slak->m_operands) / 2;
2856 slak->m_arch = ins->arch;
2857 slak->m_opcode = ins->opcode;
2858 /* This is kludgey */
2859 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
2860 if (i + 1 != m68k_numopcodes
2861 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
2863 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
2868 slak = slak->m_next;
2872 retval = hash_insert (op_hash, ins->name, (char *) hack);
2874 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
2877 for (i = 0; i < m68k_numaliases; i++)
2879 const char *name = m68k_opcode_aliases[i].primary;
2880 const char *alias = m68k_opcode_aliases[i].alias;
2881 PTR val = hash_find (op_hash, name);
2883 as_fatal ("Internal Error: Can't find %s in hash table", name);
2884 retval = hash_insert (op_hash, alias, val);
2886 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
2889 for (i = 0; i < sizeof (mklower_table); i++)
2890 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
2892 for (i = 0; i < sizeof (notend_table); i++)
2894 notend_table[i] = 0;
2895 alt_notend_table[i] = 0;
2897 notend_table[','] = 1;
2898 notend_table['{'] = 1;
2899 notend_table['}'] = 1;
2900 alt_notend_table['a'] = 1;
2901 alt_notend_table['A'] = 1;
2902 alt_notend_table['d'] = 1;
2903 alt_notend_table['D'] = 1;
2904 alt_notend_table['#'] = 1;
2905 alt_notend_table['&'] = 1;
2906 alt_notend_table['f'] = 1;
2907 alt_notend_table['F'] = 1;
2908 #ifdef REGISTER_PREFIX
2909 alt_notend_table[REGISTER_PREFIX] = 1;
2912 /* We need to put '(' in alt_notend_table to handle
2913 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
2915 alt_notend_table['('] = 1;
2917 /* We need to put '@' in alt_notend_table to handle
2918 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
2920 alt_notend_table['@'] = 1;
2922 #ifndef MIT_SYNTAX_ONLY
2923 /* Insert pseudo ops, these have to go into the opcode table since
2924 gas expects pseudo ops to start with a dot */
2927 while (mote_pseudo_table[n].poc_name)
2929 hack = (struct m68k_incant *)
2930 obstack_alloc (&robyn, sizeof (struct m68k_incant));
2931 hash_insert (op_hash,
2932 mote_pseudo_table[n].poc_name, (char *) hack);
2933 hack->m_operands = 0;
2944 m68k_init_after_args ()
2946 if (cpu_of_arch (current_architecture) == 0)
2949 const char *default_cpu = TARGET_CPU;
2951 if (*default_cpu == 'm')
2953 for (i = 0; i < n_archs; i++)
2954 if (strcasecmp (default_cpu, archs[i].name) == 0)
2958 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
2959 current_architecture |= m68020;
2962 current_architecture |= archs[i].arch;
2964 /* Permit m68881 specification with all cpus; those that can't work
2965 with a coprocessor could be doing emulation. */
2966 if (current_architecture & m68851)
2968 if (current_architecture & m68040)
2970 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
2973 /* What other incompatibilities could we check for? */
2975 /* Toss in some default assumptions about coprocessors. */
2977 && (cpu_of_arch (current_architecture)
2978 /* Can CPU32 have a 68881 coprocessor?? */
2979 & (m68020 | m68030 | cpu32)))
2981 current_architecture |= m68881;
2984 && (cpu_of_arch (current_architecture) & m68020up) != 0
2985 && (cpu_of_arch (current_architecture) & m68040up) == 0)
2987 current_architecture |= m68851;
2989 if (no_68881 && (current_architecture & m68881))
2990 as_bad ("options for 68881 and no-68881 both given");
2991 if (no_68851 && (current_architecture & m68851))
2992 as_bad ("options for 68851 and no-68851 both given");
2995 /* Work out the magic number. This isn't very general. */
2996 if (current_architecture & m68000)
2997 m68k_aout_machtype = 0;
2998 else if (current_architecture & m68010)
2999 m68k_aout_machtype = 1;
3000 else if (current_architecture & m68020)
3001 m68k_aout_machtype = 2;
3003 m68k_aout_machtype = 2;
3006 /* Note which set of "movec" control registers is available. */
3007 switch (cpu_of_arch (current_architecture))
3010 control_regs = m68000_control_regs;
3013 control_regs = m68010_control_regs;
3017 control_regs = m68020_control_regs;
3020 control_regs = m68040_control_regs;
3023 control_regs = m68060_control_regs;
3026 control_regs = cpu32_control_regs;
3032 if (cpu_of_arch (current_architecture) < m68020)
3033 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3036 /* Equal to MAX_PRECISION in atof-ieee.c */
3037 #define MAX_LITTLENUMS 6
3039 /* Turn a string in input_line_pointer into a floating point constant
3040 of type type, and store the appropriate bytes in *litP. The number
3041 of LITTLENUMS emitted is stored in *sizeP . An error message is
3042 returned, or NULL on OK. */
3045 md_atof (type, litP, sizeP)
3051 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3052 LITTLENUM_TYPE *wordP;
3084 return "Bad call to MD_ATOF()";
3086 t = atof_ieee (input_line_pointer, type, words);
3088 input_line_pointer = t;
3090 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3091 for (wordP = words; prec--;)
3093 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3094 litP += sizeof (LITTLENUM_TYPE);
3100 md_number_to_chars (buf, val, n)
3105 number_to_chars_bigendian (buf, val, n);
3109 md_apply_fix_2 (fixP, val)
3113 addressT upper_limit;
3114 offsetT lower_limit;
3116 /* This is unnecessary but it convinces the native rs6000 compiler
3117 to generate the code we want. */
3118 char *buf = fixP->fx_frag->fr_literal;
3119 buf += fixP->fx_where;
3120 /* end ibm compiler workaround */
3122 if (val & 0x80000000)
3123 val |= ~(addressT)0x7fffffff;
3127 switch (fixP->fx_size)
3129 /* The cast to offsetT below are necessary to make code correct for
3130 machines where ints are smaller than offsetT */
3134 lower_limit = - (offsetT) 0x80;
3137 *buf++ = (val >> 8);
3139 upper_limit = 0x7fff;
3140 lower_limit = - (offsetT) 0x8000;
3143 *buf++ = (val >> 24);
3144 *buf++ = (val >> 16);
3145 *buf++ = (val >> 8);
3147 upper_limit = 0x7fffffff;
3148 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3151 BAD_CASE (fixP->fx_size);
3154 /* For non-pc-relative values, it's conceivable we might get something
3155 like "0xff" for a byte field. So extend the upper part of the range
3156 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3157 so that we can do any range checking at all. */
3158 if (!fixP->fx_pcrel)
3159 upper_limit = upper_limit * 2 + 1;
3161 if ((addressT) val > upper_limit
3162 && (val > 0 || val < lower_limit))
3163 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3165 /* A one byte PC-relative reloc means a short branch. We can't use
3166 a short branch with a value of 0 or -1, because those indicate
3167 different opcodes (branches with longer offsets). */
3169 && fixP->fx_size == 1
3170 && (fixP->fx_addsy == NULL
3171 || S_IS_DEFINED (fixP->fx_addsy))
3172 && (val == 0 || val == -1))
3173 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3176 #ifdef BFD_ASSEMBLER
3178 md_apply_fix (fixP, valp)
3182 md_apply_fix_2 (fixP, (addressT) *valp);
3186 void md_apply_fix (fixP, val)
3190 md_apply_fix_2 (fixP, (addressT) val);
3194 /* *fragP has been relaxed to its final size, and now needs to have
3195 the bytes inside it modified to conform to the new size There is UGLY
3199 md_convert_frag_1 (fragP)
3200 register fragS *fragP;
3206 /* Address in object code of the displacement. */
3207 register int object_address = fragP->fr_fix + fragP->fr_address;
3209 /* Address in gas core of the place to store the displacement. */
3210 /* This convinces the native rs6000 compiler to generate the code we
3212 register char *buffer_address = fragP->fr_literal;
3213 buffer_address += fragP->fr_fix;
3214 /* end ibm compiler workaround */
3216 /* The displacement of the address, from current location. */
3217 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3218 disp = (disp + fragP->fr_offset) - object_address;
3220 #ifdef BFD_ASSEMBLER
3221 disp += fragP->fr_symbol->sy_frag->fr_address;
3224 switch (fragP->fr_subtype)
3226 case TAB (BCC68000, BYTE):
3227 case TAB (ABRANCH, BYTE):
3228 know (issbyte (disp));
3230 as_bad ("short branch with zero offset: use :w");
3231 fragP->fr_opcode[1] = disp;
3234 case TAB (DBCC, SHORT):
3235 know (issword (disp));
3238 case TAB (BCC68000, SHORT):
3239 case TAB (ABRANCH, SHORT):
3240 know (issword (disp));
3241 fragP->fr_opcode[1] = 0x00;
3244 case TAB (ABRANCH, LONG):
3245 if (cpu_of_arch (current_architecture) < m68020)
3247 if (fragP->fr_opcode[0] == 0x61)
3250 fragP->fr_opcode[0] = 0x4E;
3251 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3252 subseg_change (text_section, 0); /* @@ */
3266 else if (fragP->fr_opcode[0] == 0x60)
3268 fragP->fr_opcode[0] = 0x4E;
3269 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3270 subseg_change (text_section, 0); /* @@ */
3271 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3272 fragP->fr_offset, 0, NO_RELOC);
3278 as_bad ("Long branch offset not supported.");
3283 fragP->fr_opcode[1] = (char) 0xff;
3287 case TAB (BCC68000, LONG):
3288 /* only Bcc 68000 instructions can come here */
3289 /* change bcc into b!cc/jmp absl long */
3290 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3291 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3293 /* JF: these used to be fr_opcode[2,3], but they may be in a
3294 different frag, in which case refering to them is a no-no.
3295 Only fr_opcode[0,1] are guaranteed to work. */
3296 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3297 *buffer_address++ = (char) 0xf9;
3298 fragP->fr_fix += 2; /* account for jmp instruction */
3299 subseg_change (text_section, 0);
3300 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3301 fragP->fr_offset, 0, NO_RELOC);
3305 case TAB (DBCC, LONG):
3306 /* only DBcc 68000 instructions can come here */
3307 /* change dbcc into dbcc/jmp absl long */
3308 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3309 *buffer_address++ = 0x00; /* branch offset = 4 */
3310 *buffer_address++ = 0x04;
3311 *buffer_address++ = 0x60; /* put in bra pc+6 */
3312 *buffer_address++ = 0x06;
3313 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3314 *buffer_address++ = (char) 0xf9;
3316 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3317 subseg_change (text_section, 0);
3318 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3319 fragP->fr_offset, 0, NO_RELOC);
3323 case TAB (FBRANCH, SHORT):
3324 know ((fragP->fr_opcode[1] & 0x40) == 0);
3327 case TAB (FBRANCH, LONG):
3328 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3331 case TAB (PCREL, SHORT):
3334 case TAB (PCREL, LONG):
3335 /* The thing to do here is force it to ABSOLUTE LONG, since
3336 PCREL is really trying to shorten an ABSOLUTE address anyway */
3337 /* JF FOO This code has not been tested */
3338 subseg_change (text_section, 0);
3339 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3341 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3342 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3343 (unsigned) fragP->fr_opcode[0],
3344 (unsigned long) fragP->fr_address);
3345 fragP->fr_opcode[1] &= ~0x3F;
3346 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3350 case TAB (PCLEA, SHORT):
3351 subseg_change (text_section, 0);
3352 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3353 fragP->fr_offset, 1, NO_RELOC);
3354 fragP->fr_opcode[1] &= ~0x3F;
3355 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3358 case TAB (PCLEA, LONG):
3359 subseg_change (text_section, 0);
3360 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3361 fragP->fr_offset, 1, NO_RELOC);
3362 fixP->fx_pcrel_adjust = 2;
3363 /* Already set to mode 7.3; this indicates: PC indirect with
3364 suppressed index, 32-bit displacement. */
3365 *buffer_address++ = 0x01;
3366 *buffer_address++ = 0x70;
3371 case TAB (PCINDEX, BYTE):
3373 if (!issbyte (disp))
3375 as_bad ("displacement doesn't fit in one byte");
3378 assert (fragP->fr_fix >= 2);
3379 buffer_address[-2] &= ~1;
3380 buffer_address[-1] = disp;
3383 case TAB (PCINDEX, SHORT):
3384 subseg_change (text_section, 0);
3386 assert (issword (disp));
3387 assert (fragP->fr_fix >= 2);
3388 buffer_address[-2] |= 0x1;
3389 buffer_address[-1] = 0x20;
3390 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3391 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3393 fixP->fx_pcrel_adjust = 2;
3396 case TAB (PCINDEX, LONG):
3397 subseg_change (text_section, 0);
3399 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3400 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3402 fixP->fx_pcrel_adjust = 2;
3403 assert (fragP->fr_fix >= 2);
3404 buffer_address[-2] |= 0x1;
3405 buffer_address[-1] = 0x30;
3412 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3413 fragP->fr_fix += ext;
3417 #ifndef BFD_ASSEMBLER
3420 md_convert_frag (headers, sec, fragP)
3421 object_headers *headers;
3425 md_convert_frag_1 (fragP);
3431 md_convert_frag (abfd, sec, fragP)
3436 md_convert_frag_1 (fragP);
3440 /* Force truly undefined symbols to their maximum size, and generally set up
3441 the frag list to be relaxed
3444 md_estimate_size_before_relax (fragP, segment)
3445 register fragS *fragP;
3449 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3451 old_fix = fragP->fr_fix;
3453 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3454 switch (fragP->fr_subtype)
3457 case TAB (ABRANCH, SZ_UNDEF):
3459 if ((fragP->fr_symbol != NULL) /* Not absolute */
3460 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3462 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3465 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3467 /* On 68000, or for absolute value, switch to abs long */
3468 /* FIXME, we should check abs val, pick short or long */
3469 if (fragP->fr_opcode[0] == 0x61)
3471 fragP->fr_opcode[0] = 0x4E;
3472 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3473 subseg_change (text_section, 0);
3474 fix_new (fragP, fragP->fr_fix, 4,
3475 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3479 else if (fragP->fr_opcode[0] == 0x60)
3481 fragP->fr_opcode[0] = 0x4E;
3482 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3483 subseg_change (text_section, 0);
3484 fix_new (fragP, fragP->fr_fix, 4,
3485 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3491 as_warn ("Long branch offset to extern symbol not supported.");
3495 { /* Symbol is still undefined. Make it simple */
3496 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3497 fragP->fr_offset, 1, NO_RELOC);
3499 fragP->fr_opcode[1] = (char) 0xff;
3505 } /* case TAB(ABRANCH,SZ_UNDEF) */
3507 case TAB (FBRANCH, SZ_UNDEF):
3509 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3511 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3516 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3517 fragP->fr_offset, 1, NO_RELOC);
3519 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3523 } /* TAB(FBRANCH,SZ_UNDEF) */
3525 case TAB (PCREL, SZ_UNDEF):
3527 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3529 || cpu_of_arch (current_architecture) < m68020)
3531 fragP->fr_subtype = TAB (PCREL, SHORT);
3536 fragP->fr_subtype = TAB (PCREL, LONG);
3540 } /* TAB(PCREL,SZ_UNDEF) */
3542 case TAB (BCC68000, SZ_UNDEF):
3544 if ((fragP->fr_symbol != NULL)
3545 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3547 fragP->fr_subtype = TAB (BCC68000, BYTE);
3550 /* only Bcc 68000 instructions can come here */
3551 /* change bcc into b!cc/jmp absl long */
3552 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3553 if (flag_short_refs)
3555 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3556 /* JF: these were fr_opcode[2,3] */
3557 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3558 buffer_address[1] = (char) 0xf8;
3559 fragP->fr_fix += 2; /* account for jmp instruction */
3560 subseg_change (text_section, 0);
3561 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3562 fragP->fr_offset, 0, NO_RELOC);
3567 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3568 /* JF: these were fr_opcode[2,3] */
3569 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3570 buffer_address[1] = (char) 0xf9;
3571 fragP->fr_fix += 2; /* account for jmp instruction */
3572 subseg_change (text_section, 0);
3573 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3574 fragP->fr_offset, 0, NO_RELOC);
3579 } /* case TAB(BCC68000,SZ_UNDEF) */
3581 case TAB (DBCC, SZ_UNDEF):
3583 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3585 fragP->fr_subtype = TAB (DBCC, SHORT);
3589 /* only DBcc 68000 instructions can come here */
3590 /* change dbcc into dbcc/jmp absl long */
3591 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3592 buffer_address[0] = 0x00; /* branch offset = 4 */
3593 buffer_address[1] = 0x04;
3594 buffer_address[2] = 0x60; /* put in bra pc + ... */
3596 if (flag_short_refs)
3598 /* JF: these were fr_opcode[5-7] */
3599 buffer_address[3] = 0x04; /* plus 4 */
3600 buffer_address[4] = 0x4e; /* Put in Jump Word */
3601 buffer_address[5] = (char) 0xf8;
3602 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3603 subseg_change (text_section, 0);
3604 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3605 fragP->fr_offset, 0, NO_RELOC);
3610 /* JF: these were fr_opcode[5-7] */
3611 buffer_address[3] = 0x06; /* Plus 6 */
3612 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3613 buffer_address[5] = (char) 0xf9;
3614 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3615 subseg_change (text_section, 0);
3616 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3617 fragP->fr_offset, 0, NO_RELOC);
3623 } /* case TAB(DBCC,SZ_UNDEF) */
3625 case TAB (PCLEA, SZ_UNDEF):
3627 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3629 || cpu_of_arch (current_architecture) < m68020)
3631 fragP->fr_subtype = TAB (PCLEA, SHORT);
3636 fragP->fr_subtype = TAB (PCLEA, LONG);
3640 } /* TAB(PCLEA,SZ_UNDEF) */
3642 case TAB (PCINDEX, SZ_UNDEF):
3643 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3644 || cpu_of_arch (current_architecture) < m68020)
3646 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3650 fragP->fr_subtype = TAB (PCINDEX, LONG);
3659 /* now that SZ_UNDEF are taken care of, check others */
3660 switch (fragP->fr_subtype)
3662 case TAB (BCC68000, BYTE):
3663 case TAB (ABRANCH, BYTE):
3664 /* We can't do a short jump to the next instruction,
3665 so we force word mode. */
3666 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3667 fragP->fr_symbol->sy_frag == fragP->fr_next)
3669 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3676 return fragP->fr_var + fragP->fr_fix - old_fix;
3679 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3680 /* the bit-field entries in the relocation_info struct plays hell
3681 with the byte-order problems of cross-assembly. So as a hack,
3682 I added this mach. dependent ri twiddler. Ugly, but it gets
3684 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3685 are symbolnum, most sig. byte first. Last byte is broken up with
3686 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3687 nibble as nuthin. (on Sun 3 at least) */
3688 /* Translate the internal relocation information into target-specific
3692 md_ri_to_chars (the_bytes, ri)
3694 struct reloc_info_generic *ri;
3697 md_number_to_chars (the_bytes, ri->r_address, 4);
3698 /* now the fun stuff */
3699 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3700 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3701 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3702 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3703 ((ri->r_extern << 4) & 0x10));
3706 #endif /* comment */
3708 #ifndef BFD_ASSEMBLER
3710 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3713 relax_addressT segment_address_in_file;
3716 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3717 * Out: GNU LD relocation length code: 0, 1, or 2.
3720 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3723 know (fixP->fx_addsy != NULL);
3725 md_number_to_chars (where,
3726 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3729 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3730 ? S_GET_TYPE (fixP->fx_addsy)
3731 : fixP->fx_addsy->sy_number);
3733 where[4] = (r_symbolnum >> 16) & 0x0ff;
3734 where[5] = (r_symbolnum >> 8) & 0x0ff;
3735 where[6] = r_symbolnum & 0x0ff;
3736 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3737 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
3741 #endif /* OBJ_AOUT or OBJ_BOUT */
3743 #ifndef WORKING_DOT_WORD
3744 CONST int md_short_jump_size = 4;
3745 CONST int md_long_jump_size = 6;
3748 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3750 addressT from_addr, to_addr;
3756 offset = to_addr - (from_addr + 2);
3758 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3759 md_number_to_chars (ptr + 2, (valueT) offset, 2);
3763 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3765 addressT from_addr, to_addr;
3771 if (cpu_of_arch (current_architecture) < m68020)
3773 offset = to_addr - S_GET_VALUE (to_symbol);
3774 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
3775 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3776 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
3781 offset = to_addr - (from_addr + 2);
3782 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
3783 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3789 /* Different values of OK tell what its OK to return. Things that
3790 aren't OK are an error (what a shock, no?)
3793 10: Absolute 1:8 only
3794 20: Absolute 0:7 only
3795 30: absolute 0:15 only
3796 40: Absolute 0:31 only
3797 50: absolute 0:127 only
3798 55: absolute -64:63 only
3799 60: absolute -128:127 only
3800 70: absolute 0:4095 only
3807 struct m68k_exp *exp;
3810 if (exp->exp.X_op == O_absent)
3812 /* Do the same thing the VAX asm does */
3813 op (exp) = O_constant;
3819 as_warn ("expression out of range: defaulting to 1");
3823 else if (exp->exp.X_op == O_constant)
3828 if (offs (exp) < 1 || offs (exp) > 8)
3830 as_warn ("expression out of range: defaulting to 1");
3835 if (offs (exp) < 0 || offs (exp) > 7)
3839 if (offs (exp) < 0 || offs (exp) > 15)
3843 if (offs (exp) < 0 || offs (exp) > 32)
3847 if (offs (exp) < 0 || offs (exp) > 127)
3851 if (offs (exp) < -64 || offs (exp) > 63)
3855 if (offs (exp) < -128 || offs (exp) > 127)
3859 if (offs (exp) < 0 || offs (exp) > 4095)
3862 as_warn ("expression out of range: defaulting to 0");
3870 else if (exp->exp.X_op == O_big)
3872 if (offs (exp) <= 0 /* flonum */
3873 && (ok == 80 /* no bignums */
3874 || (ok > 10 /* small-int ranges including 0 ok */
3875 /* If we have a flonum zero, a zero integer should
3876 do as well (e.g., in moveq). */
3877 && generic_floating_point_number.exponent == 0
3878 && generic_floating_point_number.low[0] == 0)))
3880 /* HACK! Turn it into a long */
3881 LITTLENUM_TYPE words[6];
3883 gen_to_words (words, 2, 8L); /* These numbers are magic! */
3884 op (exp) = O_constant;
3887 offs (exp) = words[1] | (words[0] << 16);
3891 op (exp) = O_constant;
3894 offs (exp) = (ok == 10) ? 1 : 0;
3895 as_warn ("Can't deal with expression; defaulting to %ld",
3901 if (ok >= 10 && ok <= 70)
3903 op (exp) = O_constant;
3906 offs (exp) = (ok == 10) ? 1 : 0;
3907 as_warn ("Can't deal with expression; defaulting to %ld",
3912 if (exp->size != SIZE_UNSPEC)
3920 if (!isbyte (offs (exp)))
3921 as_warn ("expression doesn't fit in BYTE");
3924 if (!isword (offs (exp)))
3925 as_warn ("expression doesn't fit in WORD");
3933 /* These are the back-ends for the various machine dependent pseudo-ops. */
3934 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
3940 subseg_set (data_section, 1);
3941 demand_empty_rest_of_line ();
3948 subseg_set (data_section, 2);
3949 demand_empty_rest_of_line ();
3956 /* We don't support putting frags in the BSS segment, we fake it
3957 by marking in_bss, then looking at s_skip for clues. */
3959 subseg_set (bss_section, 0);
3960 demand_empty_rest_of_line ();
3968 register long temp_fill;
3970 temp = 1; /* JF should be 2? */
3971 temp_fill = get_absolute_expression ();
3972 if (!need_pass_2) /* Never make frag if expect extra pass. */
3973 frag_align (temp, (int) temp_fill);
3974 demand_empty_rest_of_line ();
3981 demand_empty_rest_of_line ();
3984 /* Pseudo-ops handled for MRI compatibility. */
3986 /* Handle an MRI style chip specification. */
3995 s = input_line_pointer;
3996 c = get_symbol_end ();
3997 for (i = 0; i < n_archs; i++)
3998 if (strcasecmp (s, archs[i].name) == 0)
4002 as_bad ("%s: unrecognized processor name", s);
4003 *input_line_pointer = c;
4004 ignore_rest_of_line ();
4007 *input_line_pointer = c;
4009 if (*input_line_pointer == '/')
4010 current_architecture = 0;
4012 current_architecture &= m68881 | m68851;
4013 current_architecture |= archs[i].arch;
4015 while (*input_line_pointer == '/')
4017 ++input_line_pointer;
4018 s = input_line_pointer;
4019 c = get_symbol_end ();
4020 if (strcmp (s, "68881") == 0)
4021 current_architecture |= m68881;
4022 else if (strcmp (s, "68851") == 0)
4023 current_architecture |= m68851;
4024 *input_line_pointer = c;
4028 /* The MRI CHIP pseudo-op. */
4035 demand_empty_rest_of_line ();
4040 * Invocation line includes a switch not recognized by the base assembler.
4041 * See if it's a processor-specific option. These are:
4043 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4044 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4045 * Select the architecture. Instructions or features not
4046 * supported by the selected architecture cause fatal
4047 * errors. More than one may be specified. The default is
4048 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4049 * for -m68000, and -m68882 is a synonym for -m68881.
4050 * -[A]m[c]no-68851, -[A]m[c]no-68881
4051 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4052 * so don't use or document it, but that's the way the parsing
4055 * -pic Indicates PIC.
4056 * -k Indicates PIC. (Sun 3 only.)
4061 CONST char *md_shortopts = "lSA:m:kQ:V";
4063 CONST char *md_shortopts = "lSA:m:k";
4066 struct option md_longopts[] = {
4067 #define OPTION_PIC (OPTION_MD_BASE)
4068 {"pic", no_argument, NULL, OPTION_PIC},
4069 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
4070 {"register-prefix-optional", no_argument, NULL,
4071 OPTION_REGISTER_PREFIX_OPTIONAL},
4072 {NULL, no_argument, NULL, 0}
4074 size_t md_longopts_size = sizeof(md_longopts);
4077 md_parse_option (c, arg)
4083 case 'l': /* -l means keep external to 2 bit offset
4084 rather than 16 bit one */
4085 flag_short_refs = 1;
4088 case 'S': /* -S means that jbsr's always turn into
4090 flag_long_jumps = 1;
4096 /* intentional fall-through */
4099 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
4103 const char *oarg = arg;
4109 if (arg[0] == 'c' && arg[1] == '6')
4112 for (i = 0; i < n_archs; i++)
4113 if (!strcmp (arg, archs[i].name))
4118 as_bad ("unrecognized option `%s'", oarg);
4121 arch = archs[i].arch;
4124 else if (arch == m68851)
4133 if (arg[0] == 'c' && arg[1] == '6')
4136 for (i = 0; i < n_archs; i++)
4137 if (!strcmp (arg, archs[i].name))
4139 unsigned long arch = archs[i].arch;
4140 if (cpu_of_arch (arch))
4141 /* It's a cpu spec. */
4143 current_architecture &= ~m68000up;
4144 current_architecture |= arch;
4146 else if (arch == m68881)
4148 current_architecture |= m68881;
4151 else if (arch == m68851)
4153 current_architecture |= m68851;
4163 as_bad ("unrecognized architecture specification `%s'", arg);
4172 break; /* -pic, Position Independent Code */
4174 case OPTION_REGISTER_PREFIX_OPTIONAL:
4175 flag_reg_prefix_optional = 1;
4190 md_show_usage (stream)
4195 -l use 1 word for refs to undefined symbols [default 2]\n\
4196 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
4197 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
4199 specify variant of 680X0 architecture [default 68020]\n\
4200 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
4201 target has/lacks floating-point coprocessor\n\
4202 [default yes for 68020, 68030, and cpu32]\n\
4203 -m68851 | -mno-68851\n\
4204 target has/lacks memory-management unit coprocessor\n\
4205 [default yes for 68020 and up]\n\
4206 -pic, -k generate position independent code\n\
4207 -S turn jbsr into jsr\n\
4208 --register-prefix-optional\n\
4209 recognize register names without prefix character\n");
4214 /* TEST2: Test md_assemble() */
4215 /* Warning, this routine probably doesn't work anymore */
4219 struct m68k_it the_ins;
4227 if (!gets (buf) || !*buf)
4229 if (buf[0] == '|' || buf[1] == '.')
4231 for (cp = buf; *cp; cp++)
4236 memset (&the_ins, '\0', sizeof (the_ins));
4237 m68k_ip (&the_ins, buf);
4240 printf ("Error %s in %s\n", the_ins.error, buf);
4244 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
4245 for (n = 0; n < the_ins.numo; n++)
4246 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
4248 print_the_insn (&the_ins.opcode[0], stdout);
4249 (void) putchar ('\n');
4251 for (n = 0; n < strlen (the_ins.args) / 2; n++)
4253 if (the_ins.operands[n].error)
4255 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
4258 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
4259 if (the_ins.operands[n].b_const)
4260 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
4261 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
4262 if (the_ins.operands[n].b_iadd)
4263 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
4264 (void) putchar ('\n');
4276 while (*str && *str != ' ')
4278 if (str[-1] == ':' || str[1] == '=')
4285 /* Possible states for relaxation:
4287 0 0 branch offset byte (bra, etc)
4291 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4295 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4302 /* We have no need to default values of symbols. */
4306 md_undefined_symbol (name)
4312 /* Round up a section size to the appropriate boundary. */
4314 md_section_align (segment, size)
4318 return size; /* Byte alignment is fine */
4321 /* Exactly what point is a PC-relative offset relative TO?
4322 On the 68k, it is relative to the address of the first extension
4323 word. The difference between the addresses of the offset and the
4324 first extension word is stored in fx_pcrel_adjust. */
4326 md_pcrel_from (fixP)
4329 return (fixP->fx_where + fixP->fx_frag->fr_address - fixP->fx_pcrel_adjust);
4332 #ifndef BFD_ASSEMBLER
4335 tc_coff_symbol_emit_hook (ignore)
4341 tc_coff_sizemachdep (frag)
4344 switch (frag->fr_subtype & 0x3)
4359 /* end of tc-m68k.c */