1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "safe-ctype.h"
26 #include "opcode/m68hc11.h"
27 #include "dwarf2dbg.h"
28 #include "elf/m68hc11.h"
30 const char comment_chars[] = ";!";
31 const char line_comment_chars[] = "#*";
32 const char line_separator_chars[] = "";
34 const char EXP_CHARS[] = "eE";
35 const char FLT_CHARS[] = "dD";
37 #define STATE_CONDITIONAL_BRANCH (1)
38 #define STATE_PC_RELATIVE (2)
39 #define STATE_INDEXED_OFFSET (3)
40 #define STATE_XBCC_BRANCH (4)
41 #define STATE_CONDITIONAL_BRANCH_6812 (5)
43 #define STATE_BYTE (0)
44 #define STATE_BITS5 (0)
45 #define STATE_WORD (1)
46 #define STATE_BITS9 (1)
47 #define STATE_LONG (2)
48 #define STATE_BITS16 (2)
49 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
51 /* This macro has no side-effects. */
52 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
53 #define RELAX_STATE(s) ((s) >> 2)
54 #define RELAX_LENGTH(s) ((s) & 3)
56 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
58 /* This table describes how you change sizes for the various types of variable
59 size expressions. This version only supports two kinds. */
62 How far Forward this mode will reach.
63 How far Backward this mode will reach.
64 How many bytes this mode will add to the size of the frag.
65 Which mode to go to if the offset won't fit in this one. */
67 relax_typeS md_relax_table[] = {
68 {1, 1, 0, 0}, /* First entries aren't used. */
69 {1, 1, 0, 0}, /* For no good reason except. */
70 {1, 1, 0, 0}, /* that the VAX doesn't either. */
74 These insns are translated into b!cc +3 jmp L. */
75 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD)},
80 /* Relax for bsr <L> and bra <L>.
81 These insns are translated into jsr and jmp. */
82 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD)},
87 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
88 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9)},
89 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16)},
93 /* Relax for dbeq/ibeq/tbeq r,<L>:
94 These insns are translated into db!cc +3 jmp L. */
95 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD)},
100 /* Relax for bcc <L> on 68HC12.
101 These insns are translated into lbcc <L>. */
102 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD)},
109 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
110 typedef enum register_id {
122 typedef struct operand {
129 struct m68hc11_opcode_def {
135 struct m68hc11_opcode *opcode;
138 static struct m68hc11_opcode_def *m68hc11_opcode_defs = 0;
139 static int m68hc11_nb_opcode_defs = 0;
141 typedef struct alias {
146 static alias alias_opcodes[] = {
153 /* Local functions. */
154 static register_id reg_name_search PARAMS ((char *));
155 static register_id register_name PARAMS ((void));
156 static int cmp_opcode PARAMS ((struct m68hc11_opcode *,
157 struct m68hc11_opcode *));
158 static char *print_opcode_format PARAMS ((struct m68hc11_opcode *, int));
159 static char *skip_whites PARAMS ((char *));
160 static int check_range PARAMS ((long, int));
161 static void print_opcode_list PARAMS ((void));
162 static void get_default_target PARAMS ((void));
163 static void print_insn_format PARAMS ((char *));
164 static int get_operand PARAMS ((operand *, int, long));
165 static void fixup8 PARAMS ((expressionS *, int, int));
166 static void fixup16 PARAMS ((expressionS *, int, int));
167 static void fixup24 PARAMS ((expressionS *, int, int));
168 static unsigned char convert_branch PARAMS ((unsigned char));
169 static char *m68hc11_new_insn PARAMS ((int));
170 static void build_dbranch_insn PARAMS ((struct m68hc11_opcode *,
171 operand *, int, int));
172 static int build_indexed_byte PARAMS ((operand *, int, int));
173 static int build_reg_mode PARAMS ((operand *, int));
175 static struct m68hc11_opcode *find
176 PARAMS ((struct m68hc11_opcode_def *, operand *, int));
177 static struct m68hc11_opcode *find_opcode
178 PARAMS ((struct m68hc11_opcode_def *, operand *, int *));
179 static void build_jump_insn
180 PARAMS ((struct m68hc11_opcode *, operand *, int, int));
181 static void build_insn
182 PARAMS ((struct m68hc11_opcode *, operand *, int));
183 static int relaxable_symbol PARAMS ((symbolS *));
185 /* Controls whether relative branches can be turned into long branches.
186 When the relative offset is too large, the insn are changed:
194 Setting the flag forbidds this. */
195 static short flag_fixed_branchs = 0;
197 /* Force to use long jumps (absolute) instead of relative branches. */
198 static short flag_force_long_jumps = 0;
200 /* Change the direct addressing mode into an absolute addressing mode
201 when the insn does not support direct addressing.
202 For example, "clr *ZD0" is normally not possible and is changed
204 static short flag_strict_direct_addressing = 1;
206 /* When an opcode has invalid operand, print out the syntax of the opcode
208 static short flag_print_insn_syntax = 0;
210 /* Dumps the list of instructions with syntax and then exit:
211 1 -> Only dumps the list (sorted by name)
212 2 -> Generate an example (or test) that can be compiled. */
213 static short flag_print_opcodes = 0;
215 /* Opcode hash table. */
216 static struct hash_control *m68hc11_hash;
218 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
219 by 'get_default_target' by looking at default BFD vector. This is overriden
220 with the -m<cpu> option. */
221 static int current_architecture = 0;
223 /* Default cpu determined by 'get_default_target'. */
224 static const char *default_cpu;
226 /* Number of opcodes in the sorted table (filtered by current cpu). */
227 static int num_opcodes;
229 /* The opcodes sorted by name and filtered by current cpu. */
230 static struct m68hc11_opcode *m68hc11_sorted_opcodes;
232 /* These are the machine dependent pseudo-ops. These are included so
233 the assembler can work on the output from the SUN C compiler, which
236 /* This table describes all the machine specific pseudo-ops the assembler
237 has to support. The fields are:
238 pseudo-op name without dot
239 function to call to execute this pseudo-op
240 Integer arg to pass to the function. */
241 const pseudo_typeS md_pseudo_table[] = {
242 /* The following pseudo-ops are supported for MRI compatibility. */
245 {"fcc", stringer, 1},
248 /* Dwarf2 support for Gcc. */
249 {"file", dwarf2_directive_file, 0},
250 {"loc", dwarf2_directive_loc, 0},
253 {"xrefb", s_ignore, 0}, /* Same as xref */
258 /* Options and initialization. */
260 const char *md_shortopts = "Sm:";
262 struct option md_longopts[] = {
263 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
264 {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH},
266 #define OPTION_SHORT_BRANCHS (OPTION_MD_BASE + 1)
267 {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHS},
269 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
270 {"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE},
272 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
273 {"print-insn-syntax", no_argument, NULL, OPTION_PRINT_INSN_SYNTAX},
275 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
276 {"print-opcodes", no_argument, NULL, OPTION_PRINT_OPCODES},
278 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
279 {"generate-example", no_argument, NULL, OPTION_GENERATE_EXAMPLE},
281 {NULL, no_argument, NULL, 0}
283 size_t md_longopts_size = sizeof (md_longopts);
285 /* Get the target cpu for the assembler. This is based on the configure
286 options and on the -m68hc11/-m68hc12 option. If no option is specified,
287 we must get the default. */
289 m68hc11_arch_format ()
291 get_default_target ();
292 if (current_architecture & cpu6811)
293 return "elf32-m68hc11";
295 return "elf32-m68hc12";
298 enum bfd_architecture
301 get_default_target ();
302 if (current_architecture & cpu6811)
303 return bfd_arch_m68hc11;
305 return bfd_arch_m68hc12;
314 /* Listing header selected according to cpu. */
316 m68hc11_listing_header ()
318 if (current_architecture & cpu6811)
319 return "M68HC11 GAS ";
321 return "M68HC12 GAS ";
325 md_show_usage (stream)
328 get_default_target ();
329 fprintf (stream, _("\
330 Motorola 68HC11/68HC12 options:\n\
331 -m68hc11 | -m68hc12 specify the processor [default %s]\n\
332 --force-long-branchs always turn relative branchs into absolute ones\n\
333 -S,--short-branchs do not turn relative branchs into absolute ones\n\
334 when the offset is out of range\n\
335 --strict-direct-mode do not turn the direct mode into extended mode\n\
336 when the instruction does not support direct mode\n\
337 --print-insn-syntax print the syntax of instruction in case of error\n\
338 --print-opcodes print the list of instructions with syntax\n\
339 --generate-example generate an example of each instruction\n\
340 (used for testing)\n"), default_cpu);
344 /* Try to identify the default target based on the BFD library. */
346 get_default_target ()
348 const bfd_target *target;
351 if (current_architecture != 0)
354 default_cpu = "unknown";
355 target = bfd_find_target (0, &abfd);
356 if (target && target->name)
358 if (strcmp (target->name, "elf32-m68hc12") == 0)
360 current_architecture = cpu6812;
361 default_cpu = "m68hc12";
363 else if (strcmp (target->name, "elf32-m68hc11") == 0)
365 current_architecture = cpu6811;
366 default_cpu = "m68hc11";
370 as_bad (_("Default target `%s' is not supported."), target->name);
376 m68hc11_print_statistics (file)
380 struct m68hc11_opcode_def *opc;
382 hash_print_statistics (file, "opcode table", m68hc11_hash);
384 opc = m68hc11_opcode_defs;
385 if (opc == 0 || m68hc11_nb_opcode_defs == 0)
388 /* Dump the opcode statistics table. */
389 fprintf (file, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
390 for (i = 0; i < m68hc11_nb_opcode_defs; i++, opc++)
392 fprintf (file, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
395 opc->min_operands, opc->max_operands, opc->format, opc->used);
400 md_parse_option (c, arg)
404 get_default_target ();
407 /* -S means keep external to 2 bit offset rather than 16 bit one. */
408 case OPTION_SHORT_BRANCHS:
410 flag_fixed_branchs = 1;
413 case OPTION_FORCE_LONG_BRANCH:
414 flag_force_long_jumps = 1;
417 case OPTION_PRINT_INSN_SYNTAX:
418 flag_print_insn_syntax = 1;
421 case OPTION_PRINT_OPCODES:
422 flag_print_opcodes = 1;
425 case OPTION_STRICT_DIRECT_MODE:
426 flag_strict_direct_addressing = 0;
429 case OPTION_GENERATE_EXAMPLE:
430 flag_print_opcodes = 2;
434 if (strcasecmp (arg, "68hc11") == 0)
435 current_architecture = cpu6811;
436 else if (strcasecmp (arg, "68hc12") == 0)
437 current_architecture = cpu6812;
439 as_bad (_("Option `%s' is not recognized."), arg);
450 md_undefined_symbol (name)
451 char *name ATTRIBUTE_UNUSED;
456 /* Equal to MAX_PRECISION in atof-ieee.c. */
457 #define MAX_LITTLENUMS 6
459 /* Turn a string in input_line_pointer into a floating point constant
460 of type TYPE, and store the appropriate bytes in *LITP. The number
461 of LITTLENUMS emitted is stored in *SIZEP. An error message is
462 returned, or NULL on OK. */
464 md_atof (type, litP, sizeP)
470 LITTLENUM_TYPE words[MAX_LITTLENUMS];
471 LITTLENUM_TYPE *wordP;
502 return _("Bad call to MD_ATOF()");
504 t = atof_ieee (input_line_pointer, type, words);
506 input_line_pointer = t;
508 *sizeP = prec * sizeof (LITTLENUM_TYPE);
509 for (wordP = words; prec--;)
511 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
512 litP += sizeof (LITTLENUM_TYPE);
518 md_section_align (seg, addr)
522 int align = bfd_get_section_alignment (stdoutput, seg);
523 return ((addr + (1 << align) - 1) & (-1 << align));
527 cmp_opcode (op1, op2)
528 struct m68hc11_opcode *op1;
529 struct m68hc11_opcode *op2;
531 return strcmp (op1->name, op2->name);
534 #define IS_CALL_SYMBOL(MODE) \
535 (((MODE) & (M6812_OP_PAGE|M6811_OP_IND16)) \
536 == ((M6812_OP_PAGE|M6811_OP_IND16)))
538 /* Initialize the assembler. Create the opcode hash table
539 (sorted on the names) with the M6811 opcode table
540 (from opcode library). */
544 char *prev_name = "";
545 struct m68hc11_opcode *opcodes;
546 struct m68hc11_opcode_def *opc = 0;
549 get_default_target ();
551 m68hc11_hash = hash_new ();
553 /* Get a writable copy of the opcode table and sort it on the names. */
554 opcodes = (struct m68hc11_opcode *) xmalloc (m68hc11_num_opcodes *
557 m68hc11_sorted_opcodes = opcodes;
559 for (i = 0; i < m68hc11_num_opcodes; i++)
561 if (m68hc11_opcodes[i].arch & current_architecture)
563 opcodes[num_opcodes] = m68hc11_opcodes[i];
564 if (opcodes[num_opcodes].name[0] == 'b'
565 && opcodes[num_opcodes].format & M6811_OP_JUMP_REL
566 && !(opcodes[num_opcodes].format & M6811_OP_BITMASK))
569 opcodes[num_opcodes] = m68hc11_opcodes[i];
572 for (j = 0; alias_opcodes[j].name != 0; j++)
573 if (strcmp (m68hc11_opcodes[i].name, alias_opcodes[j].name) == 0)
575 opcodes[num_opcodes] = m68hc11_opcodes[i];
576 opcodes[num_opcodes].name = alias_opcodes[j].alias;
582 qsort (opcodes, num_opcodes, sizeof (struct m68hc11_opcode), cmp_opcode);
584 opc = (struct m68hc11_opcode_def *)
585 xmalloc (num_opcodes * sizeof (struct m68hc11_opcode_def));
586 m68hc11_opcode_defs = opc--;
588 /* Insert unique names into hash table. The M6811 instruction set
589 has several identical opcode names that have different opcodes based
590 on the operands. This hash table then provides a quick index to
591 the first opcode with a particular name in the opcode table. */
592 for (i = 0; i < num_opcodes; i++, opcodes++)
596 if (strcmp (prev_name, opcodes->name))
598 prev_name = (char *) opcodes->name;
602 opc->min_operands = 100;
603 opc->max_operands = 0;
605 opc->opcode = opcodes;
607 hash_insert (m68hc11_hash, opcodes->name, (char *) opc);
610 opc->format |= opcodes->format;
612 /* See how many operands this opcode needs. */
614 if (opcodes->format & M6811_OP_MASK)
616 if (opcodes->format & M6811_OP_BITMASK)
618 if (opcodes->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
620 if (opcodes->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
622 /* Special case for call instruction. */
623 if ((opcodes->format & M6812_OP_PAGE)
624 && !(opcodes->format & M6811_OP_IND16))
627 if (expect < opc->min_operands)
628 opc->min_operands = expect;
629 if (IS_CALL_SYMBOL (opcodes->format))
631 if (expect > opc->max_operands)
632 opc->max_operands = expect;
635 m68hc11_nb_opcode_defs = opc - m68hc11_opcode_defs;
637 if (flag_print_opcodes)
639 print_opcode_list ();
645 m68hc11_init_after_args ()
651 /* Return a string that represents the operand format for the instruction.
652 When example is true, this generates an example of operand. This is used
653 to give an example and also to generate a test. */
655 print_opcode_format (opcode, example)
656 struct m68hc11_opcode *opcode;
659 static char buf[128];
660 int format = opcode->format;
665 if (format & M6811_OP_IMM8)
668 sprintf (p, "#%d", rand () & 0x0FF);
670 strcpy (p, _("#<imm8>"));
674 if (format & M6811_OP_IMM16)
677 sprintf (p, "#%d", rand () & 0x0FFFF);
679 strcpy (p, _("#<imm16>"));
683 if (format & M6811_OP_IX)
686 sprintf (p, "%d,X", rand () & 0x0FF);
688 strcpy (p, _("<imm8>,X"));
692 if (format & M6811_OP_IY)
695 sprintf (p, "%d,X", rand () & 0x0FF);
697 strcpy (p, _("<imm8>,X"));
701 if (format & M6812_OP_IDX)
704 sprintf (p, "%d,X", rand () & 0x0FF);
710 if (format & M6812_OP_PAGE)
713 sprintf (p, ", %d", rand () & 0x0FF);
715 strcpy (p, ", <page>");
719 if (format & M6811_OP_DIRECT)
722 sprintf (p, "*Z%d", rand () & 0x0FF);
724 strcpy (p, _("*<abs8>"));
728 if (format & M6811_OP_BITMASK)
734 sprintf (p, "#$%02x", rand () & 0x0FF);
736 strcpy (p, _("#<mask>"));
739 if (format & M6811_OP_JUMP_REL)
743 if (format & M6811_OP_IND16)
746 sprintf (p, _("symbol%d"), rand () & 0x0FF);
748 strcpy (p, _("<abs>"));
753 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
757 if (format & M6811_OP_BITMASK)
759 sprintf (p, ".+%d", rand () & 0x7F);
763 sprintf (p, "L%d", rand () & 0x0FF);
767 strcpy (p, _("<label>"));
773 /* Prints the list of instructions with the possible operands. */
778 char *prev_name = "";
779 struct m68hc11_opcode *opcodes;
780 int example = flag_print_opcodes == 2;
783 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
786 opcodes = m68hc11_sorted_opcodes;
788 /* Walk the list sorted on names (by md_begin). We only report
789 one instruction per line, and we collect the different operand
791 for (i = 0; i < num_opcodes; i++, opcodes++)
793 char *fmt = print_opcode_format (opcodes, example);
797 printf ("L%d:\t", i);
798 printf ("%s %s\n", opcodes->name, fmt);
802 if (strcmp (prev_name, opcodes->name))
807 printf ("%-5.5s ", opcodes->name);
808 prev_name = (char *) opcodes->name;
811 printf (" [%s]", fmt);
817 /* Print the instruction format. This operation is called when some
818 instruction is not correct. Instruction format is printed as an
821 print_insn_format (name)
824 struct m68hc11_opcode_def *opc;
825 struct m68hc11_opcode *opcode;
828 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name);
831 as_bad (_("Instruction `%s' is not recognized."), name);
834 opcode = opc->opcode;
836 as_bad (_("Instruction formats for `%s':"), name);
841 fmt = print_opcode_format (opcode, 0);
842 sprintf (buf, "\t%-5.5s %s", opcode->name, fmt);
847 while (strcmp (opcode->name, name) == 0);
850 /* Analysis of 68HC11 and 68HC12 operands. */
852 /* reg_name_search() finds the register number given its name.
853 Returns the register number or REG_NONE on failure. */
855 reg_name_search (name)
858 if (strcasecmp (name, "x") == 0 || strcasecmp (name, "ix") == 0)
860 if (strcasecmp (name, "y") == 0 || strcasecmp (name, "iy") == 0)
862 if (strcasecmp (name, "a") == 0)
864 if (strcasecmp (name, "b") == 0)
866 if (strcasecmp (name, "d") == 0)
868 if (strcasecmp (name, "sp") == 0)
870 if (strcasecmp (name, "pc") == 0)
872 if (strcasecmp (name, "ccr") == 0)
882 while (*p == ' ' || *p == '\t')
888 /* Check the string at input_line_pointer
889 to see if it is a valid register name. */
893 register_id reg_number;
894 char c, *p = input_line_pointer;
896 if (!is_name_beginner (*p++))
899 while (is_part_of_name (*p++))
906 /* Look to see if it's in the register table. */
907 reg_number = reg_name_search (input_line_pointer);
908 if (reg_number != REG_NONE)
913 input_line_pointer = p;
922 /* Parse a string of operands and return an array of expressions.
924 Operand mode[0] mode[1] exp[0] exp[1]
925 #n M6811_OP_IMM16 - O_*
926 *<exp> M6811_OP_DIRECT - O_*
927 .{+-}<exp> M6811_OP_JUMP_REL - O_*
928 <exp> M6811_OP_IND16 - O_*
929 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
930 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
931 n,+r M6812_PRE_INC " "
932 n,r- M6812_POST_DEC " "
933 n,r+ M6812_POST_INC " "
934 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
935 [D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register
936 [n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */
938 get_operand (oper, which, opmode)
943 char *p = input_line_pointer;
947 oper->exp.X_op = O_absent;
948 oper->reg1 = REG_NONE;
949 oper->reg2 = REG_NONE;
950 mode = M6811_OP_NONE;
954 if (*p == 0 || *p == '\n' || *p == '\r')
956 input_line_pointer = p;
960 if (*p == '*' && (opmode & (M6811_OP_DIRECT | M6811_OP_IND16)))
962 mode = M6811_OP_DIRECT;
967 if (!(opmode & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK)))
969 as_bad (_("Immediate operand is not allowed for operand %d."),
974 mode = M6811_OP_IMM16;
976 if (strncmp (p, "%hi", 3) == 0)
979 mode |= M6811_OP_HIGH_ADDR;
981 else if (strncmp (p, "%lo", 3) == 0)
984 mode |= M6811_OP_LOW_ADDR;
987 else if (*p == '.' && (p[1] == '+' || p[1] == '-'))
990 mode = M6811_OP_JUMP_REL;
994 if (current_architecture & cpu6811)
995 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
998 mode = M6812_OP_D_IDX;
1001 else if (*p == ',') /* Special handling of ,x and ,y. */
1004 input_line_pointer = p;
1006 reg = register_name ();
1007 if (reg != REG_NONE)
1010 oper->exp.X_op = O_constant;
1011 oper->exp.X_add_number = 0;
1012 oper->mode = M6812_OP_IDX;
1015 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
1018 input_line_pointer = p;
1020 if (mode == M6811_OP_NONE || mode == M6812_OP_D_IDX)
1021 reg = register_name ();
1025 if (reg != REG_NONE)
1027 p = skip_whites (input_line_pointer);
1028 if (*p == ']' && mode == M6812_OP_D_IDX)
1031 (_("Missing second register or offset for indexed-indirect mode."));
1036 oper->mode = mode | M6812_OP_REG;
1039 if (mode == M6812_OP_D_IDX)
1041 as_bad (_("Missing second register for indexed-indirect mode."));
1048 input_line_pointer = p;
1049 reg = register_name ();
1050 if (reg != REG_NONE)
1052 p = skip_whites (input_line_pointer);
1053 if (mode == M6812_OP_D_IDX)
1057 as_bad (_("Missing `]' to close indexed-indirect mode."));
1061 oper->mode = M6812_OP_D_IDX;
1063 input_line_pointer = p;
1071 /* In MRI mode, isolate the operand because we can't distinguish
1072 operands from comments. */
1077 p = skip_whites (p);
1078 while (*p && *p != ' ' && *p != '\t')
1087 /* Parse as an expression. */
1088 expression (&oper->exp);
1097 expression (&oper->exp);
1100 if (oper->exp.X_op == O_illegal)
1102 as_bad (_("Illegal operand."));
1105 else if (oper->exp.X_op == O_absent)
1107 as_bad (_("Missing operand."));
1111 p = input_line_pointer;
1113 if (mode == M6811_OP_NONE || mode == M6811_OP_DIRECT
1114 || mode == M6812_OP_D_IDX)
1116 p = skip_whites (input_line_pointer);
1120 int possible_mode = M6811_OP_NONE;
1121 char *old_input_line;
1126 /* 68HC12 pre increment or decrement. */
1127 if (mode == M6811_OP_NONE)
1131 possible_mode = M6812_PRE_DEC;
1136 possible_mode = M6812_PRE_INC;
1139 p = skip_whites (p);
1141 input_line_pointer = p;
1142 reg = register_name ();
1144 /* Backtrack if we have a valid constant expression and
1145 it does not correspond to the offset of the 68HC12 indexed
1146 addressing mode (as in N,x). */
1147 if (reg == REG_NONE && mode == M6811_OP_NONE
1148 && possible_mode != M6811_OP_NONE)
1150 oper->mode = M6811_OP_IND16 | M6811_OP_JUMP_REL;
1151 input_line_pointer = skip_whites (old_input_line);
1155 if (possible_mode != M6811_OP_NONE)
1156 mode = possible_mode;
1158 if ((current_architecture & cpu6811)
1159 && possible_mode != M6811_OP_NONE)
1160 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1162 if (which == 0 && opmode & M6812_OP_IDX_P2
1163 && reg != REG_X && reg != REG_Y
1164 && reg != REG_PC && reg != REG_SP)
1167 input_line_pointer = p;
1170 if (reg == REG_NONE && mode != M6811_OP_DIRECT
1171 && !(mode == M6811_OP_NONE && opmode & M6811_OP_IND16))
1173 as_bad (_("Wrong register in register indirect mode."));
1176 if (mode == M6812_OP_D_IDX)
1178 p = skip_whites (input_line_pointer);
1181 as_bad (_("Missing `]' to close register indirect operand."));
1184 input_line_pointer = p;
1186 oper->mode = M6812_OP_D_IDX_2;
1189 if (reg != REG_NONE)
1192 if (mode == M6811_OP_NONE)
1194 p = input_line_pointer;
1197 mode = M6812_POST_DEC;
1199 if (current_architecture & cpu6811)
1201 (_("Post-decrement mode is not valid for 68HC11."));
1205 mode = M6812_POST_INC;
1207 if (current_architecture & cpu6811)
1209 (_("Post-increment mode is not valid for 68HC11."));
1212 mode = M6812_OP_IDX;
1214 input_line_pointer = p;
1217 mode |= M6812_OP_IDX;
1222 input_line_pointer = old_input_line;
1225 if (mode == M6812_OP_D_IDX_2)
1227 as_bad (_("Invalid indexed indirect mode."));
1232 /* If the mode is not known until now, this is either a label
1233 or an indirect address. */
1234 if (mode == M6811_OP_NONE)
1235 mode = M6811_OP_IND16 | M6811_OP_JUMP_REL;
1237 p = input_line_pointer;
1238 while (*p == ' ' || *p == '\t')
1240 input_line_pointer = p;
1246 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1247 | M6812_POST_INC | M6812_POST_DEC)
1249 /* Checks that the number 'num' fits for a given mode. */
1251 check_range (num, mode)
1255 /* Auto increment and decrement are ok for [-8..8] without 0. */
1256 if (mode & M6812_AUTO_INC_DEC)
1257 return (num != 0 && num <= 8 && num >= -8);
1259 /* The 68HC12 supports 5, 9 and 16-bit offsets. */
1260 if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX))
1261 mode = M6811_OP_IND16;
1263 if (mode & M6812_OP_JUMP_REL16)
1264 mode = M6811_OP_IND16;
1266 mode &= ~M6811_OP_BRANCH;
1271 case M6811_OP_DIRECT:
1272 return (num >= 0 && num <= 255) ? 1 : 0;
1274 case M6811_OP_BITMASK:
1277 return (((num & 0xFFFFFF00) == 0) || ((num & 0xFFFFFF00) == 0xFFFFFF00))
1280 case M6811_OP_JUMP_REL:
1281 return (num >= -128 && num <= 127) ? 1 : 0;
1283 case M6811_OP_IND16:
1284 case M6811_OP_IND16 | M6812_OP_PAGE:
1285 case M6811_OP_IMM16:
1286 return (((num & 0xFFFF0000) == 0) || ((num & 0xFFFF0000) == 0xFFFF0000))
1289 case M6812_OP_IBCC_MARKER:
1290 case M6812_OP_TBCC_MARKER:
1291 case M6812_OP_DBCC_MARKER:
1292 return (num >= -256 && num <= 255) ? 1 : 0;
1294 case M6812_OP_TRAP_ID:
1295 return ((num >= 0x30 && num <= 0x39)
1296 || (num >= 0x40 && num <= 0x0ff)) ? 1 : 0;
1303 /* Gas fixup generation. */
1305 /* Put a 1 byte expression described by 'oper'. If this expression contains
1306 unresolved symbols, generate an 8-bit fixup. */
1308 fixup8 (oper, mode, opmode)
1317 if (oper->X_op == O_constant)
1319 if (mode & M6812_OP_TRAP_ID
1320 && !check_range (oper->X_add_number, M6812_OP_TRAP_ID))
1322 static char trap_id_warn_once = 0;
1324 as_bad (_("Trap id `%ld' is out of range."), oper->X_add_number);
1325 if (trap_id_warn_once == 0)
1327 trap_id_warn_once = 1;
1328 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1332 if (!(mode & M6812_OP_TRAP_ID)
1333 && !check_range (oper->X_add_number, mode))
1335 as_bad (_("Operand out of 8-bit range: `%ld'."), oper->X_add_number);
1337 number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1);
1339 else if (oper->X_op != O_register)
1341 if (mode & M6812_OP_TRAP_ID)
1342 as_bad (_("The trap id must be a constant."));
1344 if (mode == M6811_OP_JUMP_REL)
1348 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
1349 oper, true, BFD_RELOC_8_PCREL);
1350 fixp->fx_pcrel_adjust = 1;
1354 /* Now create an 8-bit fixup. If there was some %hi or %lo
1355 modifier, generate the reloc accordingly. */
1356 fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
1358 ((opmode & M6811_OP_HIGH_ADDR)
1359 ? BFD_RELOC_M68HC11_HI8
1360 : ((opmode & M6811_OP_LOW_ADDR)
1361 ? BFD_RELOC_M68HC11_LO8
1362 : ((mode & M6812_OP_PAGE)
1363 ? BFD_RELOC_M68HC11_PAGE : BFD_RELOC_8))));
1365 number_to_chars_bigendian (f, 0, 1);
1369 as_fatal (_("Operand `%x' not recognized in fixup8."), oper->X_op);
1373 /* Put a 2 byte expression described by 'oper'. If this expression contains
1374 unresolved symbols, generate a 16-bit fixup. */
1376 fixup16 (oper, mode, opmode)
1379 int opmode ATTRIBUTE_UNUSED;
1385 if (oper->X_op == O_constant)
1387 if (!check_range (oper->X_add_number, mode))
1389 as_bad (_("Operand out of 16-bit range: `%ld'."),
1390 oper->X_add_number);
1392 number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFF, 2);
1394 else if (oper->X_op != O_register)
1398 /* Now create a 16-bit fixup. */
1399 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1401 (mode & M6812_OP_JUMP_REL16 ? true : false),
1402 (mode & M6812_OP_JUMP_REL16
1403 ? BFD_RELOC_16_PCREL
1404 : (mode & M6812_OP_PAGE)
1405 ? BFD_RELOC_M68HC11_LO16 : BFD_RELOC_16));
1406 number_to_chars_bigendian (f, 0, 2);
1407 if (mode & M6812_OP_JUMP_REL16)
1408 fixp->fx_pcrel_adjust = 2;
1412 as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op);
1416 /* Put a 3 byte expression described by 'oper'. If this expression contains
1417 unresolved symbols, generate a 24-bit fixup. */
1419 fixup24 (oper, mode, opmode)
1422 int opmode ATTRIBUTE_UNUSED;
1428 if (oper->X_op == O_constant)
1430 if (!check_range (oper->X_add_number, mode))
1432 as_bad (_("Operand out of 16-bit range: `%ld'."),
1433 oper->X_add_number);
1435 number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFFFF, 3);
1437 else if (oper->X_op != O_register)
1441 /* Now create a 24-bit fixup. */
1442 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1443 oper, false, BFD_RELOC_M68HC11_24);
1444 number_to_chars_bigendian (f, 0, 3);
1448 as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op);
1452 /* 68HC11 and 68HC12 code generation. */
1454 /* Translate the short branch/bsr instruction into a long branch. */
1455 static unsigned char
1456 convert_branch (code)
1459 if (IS_OPCODE (code, M6812_BSR))
1461 else if (IS_OPCODE (code, M6811_BSR))
1463 else if (IS_OPCODE (code, M6811_BRA))
1464 return (current_architecture & cpu6812) ? M6812_JMP : M6811_JMP;
1466 as_fatal (_("Unexpected branch conversion with `%x'"), code);
1468 /* Keep gcc happy. */
1472 /* Start a new insn that contains at least 'size' bytes. Record the
1473 line information of that insn in the dwarf2 debug sections. */
1475 m68hc11_new_insn (size)
1480 f = frag_more (size);
1482 dwarf2_emit_insn (size);
1487 /* Builds a jump instruction (bra, bcc, bsr). */
1489 build_jump_insn (opcode, operands, nb_operands, jmp_mode)
1490 struct m68hc11_opcode *opcode;
1499 /* The relative branch convertion is not supported for
1501 assert ((opcode->format & M6811_OP_BITMASK) == 0);
1502 assert (nb_operands == 1);
1503 assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE);
1505 code = opcode->opcode;
1507 n = operands[0].exp.X_add_number;
1509 /* Turn into a long branch:
1510 - when force long branch option (and not for jbcc pseudos),
1511 - when jbcc and the constant is out of -128..127 range,
1512 - when branch optimization is allowed and branch out of range. */
1513 if ((jmp_mode == 0 && flag_force_long_jumps)
1514 || (operands[0].exp.X_op == O_constant
1515 && (!check_range (n, opcode->format) &&
1516 (jmp_mode == 1 || flag_fixed_branchs == 0))))
1518 if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
1520 code = convert_branch (code);
1522 f = m68hc11_new_insn (1);
1523 number_to_chars_bigendian (f, code, 1);
1525 else if (current_architecture & cpu6812)
1527 /* 68HC12: translate the bcc into a lbcc. */
1528 f = m68hc11_new_insn (2);
1529 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1530 number_to_chars_bigendian (f + 1, code, 1);
1531 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16,
1532 M6812_OP_JUMP_REL16);
1537 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1538 f = m68hc11_new_insn (3);
1540 number_to_chars_bigendian (f, code, 1);
1541 number_to_chars_bigendian (f + 1, 3, 1);
1542 number_to_chars_bigendian (f + 2, M6811_JMP, 1);
1544 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16);
1548 /* Branch with a constant that must fit in 8-bits. */
1549 if (operands[0].exp.X_op == O_constant)
1551 if (!check_range (n, opcode->format))
1553 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1556 else if (opcode->format & M6812_OP_JUMP_REL16)
1558 f = m68hc11_new_insn (4);
1559 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1560 number_to_chars_bigendian (f + 1, code, 1);
1561 number_to_chars_bigendian (f + 2, n & 0x0ffff, 2);
1565 f = m68hc11_new_insn (2);
1566 number_to_chars_bigendian (f, code, 1);
1567 number_to_chars_bigendian (f + 1, n & 0x0FF, 1);
1570 else if (opcode->format & M6812_OP_JUMP_REL16)
1572 f = m68hc11_new_insn (2);
1573 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1574 number_to_chars_bigendian (f + 1, code, 1);
1575 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16, M6812_OP_JUMP_REL16);
1581 /* Branch offset must fit in 8-bits, don't do some relax. */
1582 if (jmp_mode == 0 && flag_fixed_branchs)
1584 opcode = m68hc11_new_insn (1);
1585 number_to_chars_bigendian (opcode, code, 1);
1586 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL);
1589 /* bra/bsr made be changed into jmp/jsr. */
1590 else if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
1592 /* Allocate worst case storage. */
1593 opcode = m68hc11_new_insn (3);
1594 number_to_chars_bigendian (opcode, code, 1);
1595 number_to_chars_bigendian (opcode + 1, 0, 1);
1596 frag_variant (rs_machine_dependent, 1, 1,
1597 ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF),
1598 operands[0].exp.X_add_symbol, (offsetT) n,
1601 else if (current_architecture & cpu6812)
1603 opcode = m68hc11_new_insn (2);
1604 number_to_chars_bigendian (opcode, code, 1);
1605 number_to_chars_bigendian (opcode + 1, 0, 1);
1606 frag_var (rs_machine_dependent, 2, 2,
1607 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_UNDF),
1608 operands[0].exp.X_add_symbol, (offsetT) n, opcode);
1612 opcode = m68hc11_new_insn (2);
1613 number_to_chars_bigendian (opcode, code, 1);
1614 number_to_chars_bigendian (opcode + 1, 0, 1);
1615 frag_var (rs_machine_dependent, 3, 3,
1616 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF),
1617 operands[0].exp.X_add_symbol, (offsetT) n, opcode);
1622 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1624 build_dbranch_insn (opcode, operands, nb_operands, jmp_mode)
1625 struct m68hc11_opcode *opcode;
1634 /* The relative branch convertion is not supported for
1636 assert ((opcode->format & M6811_OP_BITMASK) == 0);
1637 assert (nb_operands == 2);
1638 assert (operands[0].reg1 != REG_NONE);
1640 code = opcode->opcode & 0x0FF;
1642 f = m68hc11_new_insn (1);
1643 number_to_chars_bigendian (f, code, 1);
1645 n = operands[1].exp.X_add_number;
1646 code = operands[0].reg1;
1648 if (operands[0].reg1 == REG_NONE || operands[0].reg1 == REG_CCR
1649 || operands[0].reg1 == REG_PC)
1650 as_bad (_("Invalid register for dbcc/tbcc instruction."));
1652 if (opcode->format & M6812_OP_IBCC_MARKER)
1654 else if (opcode->format & M6812_OP_TBCC_MARKER)
1657 if (!(opcode->format & M6812_OP_EQ_MARKER))
1660 /* Turn into a long branch:
1661 - when force long branch option (and not for jbcc pseudos),
1662 - when jdbcc and the constant is out of -256..255 range,
1663 - when branch optimization is allowed and branch out of range. */
1664 if ((jmp_mode == 0 && flag_force_long_jumps)
1665 || (operands[1].exp.X_op == O_constant
1666 && (!check_range (n, M6812_OP_IBCC_MARKER) &&
1667 (jmp_mode == 1 || flag_fixed_branchs == 0))))
1671 number_to_chars_bigendian (f, code, 1);
1672 number_to_chars_bigendian (f + 1, M6812_JMP, 1);
1673 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16);
1677 /* Branch with a constant that must fit in 9-bits. */
1678 if (operands[1].exp.X_op == O_constant)
1680 if (!check_range (n, M6812_OP_IBCC_MARKER))
1682 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1691 number_to_chars_bigendian (f, code, 1);
1692 number_to_chars_bigendian (f + 1, n & 0x0FF, 1);
1697 /* Branch offset must fit in 8-bits, don't do some relax. */
1698 if (jmp_mode == 0 && flag_fixed_branchs)
1700 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL);
1706 number_to_chars_bigendian (f, code, 1);
1707 number_to_chars_bigendian (f + 1, 0, 1);
1708 frag_var (rs_machine_dependent, 3, 3,
1709 ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_UNDF),
1710 operands[1].exp.X_add_symbol, (offsetT) n, f);
1715 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
1717 /* Assemble the post index byte for 68HC12 extended addressing modes. */
1719 build_indexed_byte (op, format, move_insn)
1721 int format ATTRIBUTE_UNUSED;
1724 unsigned char byte = 0;
1729 val = op->exp.X_add_number;
1731 if (mode & M6812_AUTO_INC_DEC)
1734 if (mode & (M6812_POST_INC | M6812_POST_DEC))
1737 if (op->exp.X_op == O_constant)
1739 if (!check_range (val, mode))
1741 as_bad (_("Increment/decrement value is out of range: `%ld'."),
1744 if (mode & (M6812_POST_INC | M6812_PRE_INC))
1745 byte |= (val - 1) & 0x07;
1747 byte |= (8 - ((val) & 7)) | 0x8;
1752 as_fatal (_("Expecting a register."));
1767 as_bad (_("Invalid register for post/pre increment."));
1772 number_to_chars_bigendian (f, byte, 1);
1776 if (mode & (M6812_OP_IDX | M6812_OP_D_IDX_2))
1797 as_bad (_("Invalid register."));
1800 if (op->exp.X_op == O_constant)
1802 if (!check_range (val, M6812_OP_IDX))
1804 as_bad (_("Offset out of 16-bit range: %ld."), val);
1807 if (move_insn && !(val >= -16 && val <= 15))
1809 as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
1814 if (val >= -16 && val <= 15 && !(mode & M6812_OP_D_IDX_2))
1819 number_to_chars_bigendian (f, byte, 1);
1822 else if (val >= -256 && val <= 255 && !(mode & M6812_OP_D_IDX_2))
1829 number_to_chars_bigendian (f, byte, 1);
1830 number_to_chars_bigendian (f + 1, val & 0x0FF, 1);
1836 if (mode & M6812_OP_D_IDX_2)
1842 number_to_chars_bigendian (f, byte, 1);
1843 number_to_chars_bigendian (f + 1, val & 0x0FFFF, 2);
1847 if (mode & M6812_OP_D_IDX_2)
1849 byte = (byte << 3) | 0xe3;
1851 number_to_chars_bigendian (f, byte, 1);
1853 fixup16 (&op->exp, 0, 0);
1855 else if (op->reg1 != REG_PC)
1857 byte = (byte << 3) | 0xe2;
1859 number_to_chars_bigendian (f, byte, 1);
1862 fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1863 &op->exp, false, BFD_RELOC_16);
1864 number_to_chars_bigendian (f, 0, 2);
1869 number_to_chars_bigendian (f, byte, 1);
1870 frag_var (rs_machine_dependent, 2, 2,
1871 ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF),
1872 op->exp.X_add_symbol,
1873 op->exp.X_add_number, f);
1878 if (mode & (M6812_OP_REG | M6812_OP_D_IDX))
1880 if (mode & M6812_OP_D_IDX)
1882 if (op->reg1 != REG_D)
1883 as_bad (_("Expecting register D for indexed indirect mode."));
1885 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
1902 as_bad (_("Invalid accumulator register."));
1927 as_bad (_("Invalid indexed register."));
1931 number_to_chars_bigendian (f, byte, 1);
1935 as_fatal (_("Addressing mode not implemented yet."));
1939 /* Assemble the 68HC12 register mode byte. */
1941 build_reg_mode (op, format)
1948 if (format & M6812_OP_SEX_MARKER
1949 && op->reg1 != REG_A && op->reg1 != REG_B && op->reg1 != REG_CCR)
1950 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
1951 else if (op->reg1 == REG_NONE || op->reg1 == REG_PC)
1952 as_bad (_("Invalid source register."));
1954 if (format & M6812_OP_SEX_MARKER
1955 && op->reg2 != REG_D
1956 && op->reg2 != REG_X && op->reg2 != REG_Y && op->reg2 != REG_SP)
1957 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
1958 else if (op->reg2 == REG_NONE || op->reg2 == REG_PC)
1959 as_bad (_("Invalid destination register."));
1961 byte = (op->reg1 << 4) | (op->reg2);
1962 if (format & M6812_OP_EXG_MARKER)
1966 number_to_chars_bigendian (f, byte, 1);
1970 /* build_insn takes a pointer to the opcode entry in the opcode table,
1971 the array of operand expressions and builds the correspding instruction.
1972 This operation only deals with non relative jumps insn (need special
1975 build_insn (opcode, operands, nb_operands)
1976 struct m68hc11_opcode *opcode;
1978 int nb_operands ATTRIBUTE_UNUSED;
1985 /* Put the page code instruction if there is one. */
1986 format = opcode->format;
1987 if (format & OP_EXTENDED)
1991 f = m68hc11_new_insn (2);
1992 if (format & M6811_OP_PAGE2)
1993 page_code = M6811_OPCODE_PAGE2;
1994 else if (format & M6811_OP_PAGE3)
1995 page_code = M6811_OPCODE_PAGE3;
1997 page_code = M6811_OPCODE_PAGE4;
1999 number_to_chars_bigendian (f, page_code, 1);
2003 f = m68hc11_new_insn (1);
2005 number_to_chars_bigendian (f, opcode->opcode, 1);
2009 /* The 68HC12 movb and movw instructions are special. We have to handle
2010 them in a special way. */
2011 if (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
2014 if (format & M6812_OP_IDX)
2016 build_indexed_byte (&operands[0], format, 1);
2018 format &= ~M6812_OP_IDX;
2020 if (format & M6812_OP_IDX_P2)
2022 build_indexed_byte (&operands[1], format, 1);
2024 format &= ~M6812_OP_IDX_P2;
2028 if (format & (M6811_OP_DIRECT | M6811_OP_IMM8))
2030 fixup8 (&operands[i].exp,
2031 format & (M6811_OP_DIRECT | M6811_OP_IMM8 | M6812_OP_TRAP_ID),
2035 else if (IS_CALL_SYMBOL (format) && nb_operands == 1)
2037 format &= ~M6812_OP_PAGE;
2038 fixup24 (&operands[i].exp, format & M6811_OP_IND16,
2042 else if (format & (M6811_OP_IMM16 | M6811_OP_IND16))
2044 fixup16 (&operands[i].exp,
2045 format & (M6811_OP_IMM16 | M6811_OP_IND16 | M6812_OP_PAGE),
2049 else if (format & (M6811_OP_IX | M6811_OP_IY))
2051 if ((format & M6811_OP_IX) && (operands[0].reg1 != REG_X))
2052 as_bad (_("Invalid indexed register, expecting register X."));
2053 if ((format & M6811_OP_IY) && (operands[0].reg1 != REG_Y))
2054 as_bad (_("Invalid indexed register, expecting register Y."));
2056 fixup8 (&operands[0].exp, M6811_OP_IX, operands[0].mode);
2060 (M6812_OP_IDX | M6812_OP_IDX_2 | M6812_OP_IDX_1
2061 | M6812_OP_D_IDX | M6812_OP_D_IDX_2))
2063 build_indexed_byte (&operands[i], format, move_insn);
2066 else if (format & M6812_OP_REG && current_architecture & cpu6812)
2068 build_reg_mode (&operands[i], format);
2071 if (format & M6811_OP_BITMASK)
2073 fixup8 (&operands[i].exp, M6811_OP_BITMASK, operands[i].mode);
2076 if (format & M6811_OP_JUMP_REL)
2078 fixup8 (&operands[i].exp, M6811_OP_JUMP_REL, operands[i].mode);
2080 else if (format & M6812_OP_IND16_P2)
2082 fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode);
2084 if (format & M6812_OP_PAGE)
2086 fixup8 (&operands[i].exp, M6812_OP_PAGE, operands[i].mode);
2090 /* Opcode identification and operand analysis. */
2092 /* find() gets a pointer to an entry in the opcode table. It must look at all
2093 opcodes with the same name and use the operands to choose the correct
2094 opcode. Returns the opcode pointer if there was a match and 0 if none. */
2095 static struct m68hc11_opcode *
2096 find (opc, operands, nb_operands)
2097 struct m68hc11_opcode_def *opc;
2102 struct m68hc11_opcode *opcode;
2103 struct m68hc11_opcode *op_indirect;
2106 opcode = opc->opcode;
2108 /* Now search the opcode table table for one with operands
2109 that matches what we've got. We're only done if the operands matched so
2110 far AND there are no more to check. */
2111 for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++)
2113 int poss_indirect = 0;
2114 long format = opcode->format;
2118 if (opcode->format & M6811_OP_MASK)
2120 if (opcode->format & M6811_OP_BITMASK)
2122 if (opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2124 if (opcode->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
2126 if ((opcode->format & M6812_OP_PAGE)
2127 && (!IS_CALL_SYMBOL (opcode->format) || nb_operands == 2))
2130 for (i = 0; expect == nb_operands && i < nb_operands; i++)
2132 int mode = operands[i].mode;
2134 if (mode & M6811_OP_IMM16)
2137 (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK))
2141 if (mode == M6811_OP_DIRECT)
2143 if (format & M6811_OP_DIRECT)
2146 /* If the operand is a page 0 operand, remember a
2147 possible <abs-16> addressing mode. We mark
2148 this and continue to check other operands. */
2149 if (format & M6811_OP_IND16
2150 && flag_strict_direct_addressing && op_indirect == 0)
2157 if (mode & M6811_OP_IND16)
2159 if (i == 0 && (format & M6811_OP_IND16) != 0)
2161 if (i != 0 && (format & M6812_OP_PAGE) != 0)
2163 if (i != 0 && (format & M6812_OP_IND16_P2) != 0)
2165 if (i == 0 && (format & M6811_OP_BITMASK))
2168 if (mode & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2170 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2173 if (mode & M6812_OP_REG)
2176 && (format & M6812_OP_REG)
2177 && (operands[i].reg2 == REG_NONE))
2180 && (format & M6812_OP_REG)
2181 && (format & M6812_OP_REG_2)
2182 && (operands[i].reg2 != REG_NONE))
2185 && (format & M6812_OP_IDX)
2186 && (operands[i].reg2 != REG_NONE))
2189 && (format & M6812_OP_IDX)
2190 && (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)))
2193 && (format & M6812_OP_IDX_P2))
2197 if (mode & M6812_OP_IDX)
2199 if (format & M6811_OP_IX && operands[i].reg1 == REG_X)
2201 if (format & M6811_OP_IY && operands[i].reg1 == REG_Y)
2204 && format & (M6812_OP_IDX | M6812_OP_IDX_1 | M6812_OP_IDX_2)
2205 && (operands[i].reg1 == REG_X
2206 || operands[i].reg1 == REG_Y
2207 || operands[i].reg1 == REG_SP
2208 || operands[i].reg1 == REG_PC))
2210 if (i == 1 && format & M6812_OP_IDX_P2)
2213 if (mode & format & (M6812_OP_D_IDX | M6812_OP_D_IDX_2))
2218 if (mode & M6812_AUTO_INC_DEC)
2221 && format & (M6812_OP_IDX | M6812_OP_IDX_1 |
2224 if (i == 1 && format & M6812_OP_IDX_P2)
2229 match = i == nb_operands;
2231 /* Operands are ok but an operand uses page 0 addressing mode
2232 while the insn supports abs-16 mode. Keep a reference to this
2233 insns in case there is no insn supporting page 0 addressing. */
2234 if (match && poss_indirect)
2236 op_indirect = opcode;
2243 /* Page 0 addressing is used but not supported by any insn.
2244 If absolute addresses are supported, we use that insn. */
2245 if (match == 0 && op_indirect)
2247 opcode = op_indirect;
2259 /* Find the real opcode and its associated operands. We use a progressive
2260 approach here. On entry, 'opc' points to the first opcode in the
2261 table that matches the opcode name in the source line. We try to
2262 isolate an operand, find a possible match in the opcode table.
2263 We isolate another operand if no match were found. The table 'operands'
2264 is filled while operands are recognized.
2266 Returns the opcode pointer that matches the opcode name in the
2267 source line and the associated operands. */
2268 static struct m68hc11_opcode *
2269 find_opcode (opc, operands, nb_operands)
2270 struct m68hc11_opcode_def *opc;
2274 struct m68hc11_opcode *opcode;
2277 if (opc->max_operands == 0)
2283 for (i = 0; i < opc->max_operands;)
2287 result = get_operand (&operands[i], i, opc->format);
2291 /* Special case where the bitmask of the bclr/brclr
2292 instructions is not introduced by #.
2293 Example: bclr 3,x $80. */
2294 if (i == 1 && (opc->format & M6811_OP_BITMASK)
2295 && (operands[i].mode & M6811_OP_IND16))
2297 operands[i].mode = M6811_OP_IMM16;
2302 if (i >= opc->min_operands)
2304 opcode = find (opc, operands, i);
2305 if (opcode && !(opcode->format & M6812_OP_PAGE))
2308 if (opcode && *input_line_pointer != ',')
2312 if (*input_line_pointer == ',')
2313 input_line_pointer++;
2319 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2320 | M6812_OP_DBCC_MARKER \
2321 | M6812_OP_IBCC_MARKER)
2323 /* Gas line assembler entry point. */
2325 /* This is the main entry point for the machine-dependent assembler. str
2326 points to a machine-dependent instruction. This function is supposed to
2327 emit the frags/bytes it assembles to. */
2332 struct m68hc11_opcode_def *opc;
2333 struct m68hc11_opcode *opcode;
2335 unsigned char *op_start, *save;
2336 unsigned char *op_end;
2339 operand operands[M6811_MAX_OPERANDS];
2341 int branch_optimize = 0;
2344 /* Drop leading whitespace. */
2348 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2349 lower case (the opcode table only has lower case op-codes). */
2350 for (op_start = op_end = (unsigned char *) (str);
2351 *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' ';
2354 name[nlen] = TOLOWER (op_start[nlen]);
2361 as_bad (_("No instruction or missing opcode."));
2365 /* Find the opcode definition given its name. */
2366 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name);
2368 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
2369 pseudo insns for relative branch. For these branchs, we always
2370 optimize them (turned into absolute branchs) even if --short-branchs
2372 if (opc == NULL && name[0] == 'j' && name[1] == 'b')
2374 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, &name[1]);
2376 && (!(opc->format & M6811_OP_JUMP_REL)
2377 || (opc->format & M6811_OP_BITMASK)))
2380 branch_optimize = 1;
2383 /* The following test should probably be removed. This is not conform
2384 to Motorola assembler specs. */
2385 if (opc == NULL && flag_mri)
2387 if (*op_end == ' ' || *op_end == '\t')
2389 while (*op_end == ' ' || *op_end == '\t')
2394 (is_end_of_line[op_end[1]]
2395 || op_end[1] == ' ' || op_end[1] == '\t'
2396 || !ISALNUM (op_end[1])))
2397 && (*op_end == 'a' || *op_end == 'b'
2398 || *op_end == 'A' || *op_end == 'B'
2399 || *op_end == 'd' || *op_end == 'D'
2400 || *op_end == 'x' || *op_end == 'X'
2401 || *op_end == 'y' || *op_end == 'Y'))
2403 name[nlen++] = TOLOWER (*op_end++);
2405 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash,
2411 /* Identify a possible instruction alias. There are some on the
2412 68HC12 to emulate a few 68HC11 instructions. */
2413 if (opc == NULL && (current_architecture & cpu6812))
2417 for (i = 0; i < m68hc12_num_alias; i++)
2418 if (strcmp (m68hc12_alias[i].name, name) == 0)
2424 if (opc == NULL && alias_id < 0)
2426 as_bad (_("Opcode `%s' is not recognized."), name);
2429 save = input_line_pointer;
2430 input_line_pointer = op_end;
2435 opcode = find_opcode (opc, operands, &nb_operands);
2440 if ((opcode || alias_id >= 0) && !flag_mri)
2442 char *p = input_line_pointer;
2444 while (*p == ' ' || *p == '\t' || *p == '\n' || *p == '\r')
2447 if (*p != '\n' && *p)
2448 as_bad (_("Garbage at end of instruction: `%s'."), p);
2451 input_line_pointer = save;
2455 char *f = m68hc11_new_insn (m68hc12_alias[alias_id].size);
2457 number_to_chars_bigendian (f, m68hc12_alias[alias_id].code1, 1);
2458 if (m68hc12_alias[alias_id].size > 1)
2459 number_to_chars_bigendian (f + 1, m68hc12_alias[alias_id].code2, 1);
2464 /* Opcode is known but does not have valid operands. Print out the
2465 syntax for this opcode. */
2468 if (flag_print_insn_syntax)
2469 print_insn_format (name);
2471 as_bad (_("Invalid operand for `%s'"), name);
2475 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
2476 relative and must be in the range -256..255 (9-bits). */
2477 if ((opcode->format & M6812_XBCC_MARKER)
2478 && (opcode->format & M6811_OP_JUMP_REL))
2479 build_dbranch_insn (opcode, operands, nb_operands, branch_optimize);
2481 /* Relative jumps instructions are taken care of separately. We have to make
2482 sure that the relative branch is within the range -128..127. If it's out
2483 of range, the instructions are changed into absolute instructions.
2484 This is not supported for the brset and brclr instructions. */
2485 else if ((opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2486 && !(opcode->format & M6811_OP_BITMASK))
2487 build_jump_insn (opcode, operands, nb_operands, branch_optimize);
2489 build_insn (opcode, operands, nb_operands);
2492 /* Relocation, relaxation and frag conversions. */
2494 md_pcrel_from_section (fixp, sec)
2499 if (fixp->fx_addsy != (symbolS *) NULL
2500 && (!S_IS_DEFINED (fixp->fx_addsy)
2501 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
2504 adjust = fixp->fx_pcrel_adjust;
2505 return fixp->fx_frag->fr_address + fixp->fx_where + adjust;
2508 /* If while processing a fixup, a reloc really needs to be created
2509 then it is done here. */
2511 tc_gen_reloc (section, fixp)
2517 reloc = (arelent *) xmalloc (sizeof (arelent));
2518 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2519 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
2520 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2521 if (fixp->fx_r_type == 0)
2522 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
2524 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
2525 if (reloc->howto == (reloc_howto_type *) NULL)
2527 as_bad_where (fixp->fx_file, fixp->fx_line,
2528 _("Relocation %d is not supported by object file format."),
2529 (int) fixp->fx_r_type);
2533 if (!fixp->fx_pcrel)
2534 reloc->addend = fixp->fx_addnumber;
2536 reloc->addend = (section->vma
2537 + (fixp->fx_pcrel_adjust == 64
2538 ? -1 : fixp->fx_pcrel_adjust)
2539 + fixp->fx_addnumber
2540 + md_pcrel_from_section (fixp, section));
2545 md_convert_frag (abfd, sec, fragP)
2546 bfd *abfd ATTRIBUTE_UNUSED;
2547 asection *sec ATTRIBUTE_UNUSED;
2553 char *buffer_address = fragP->fr_literal;
2555 /* Address in object code of the displacement. */
2556 register int object_address = fragP->fr_fix + fragP->fr_address;
2558 buffer_address += fragP->fr_fix;
2560 /* The displacement of the address, from current location. */
2561 value = S_GET_VALUE (fragP->fr_symbol);
2562 disp = (value + fragP->fr_offset) - object_address;
2564 switch (fragP->fr_subtype)
2566 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE):
2567 fragP->fr_opcode[1] = disp;
2570 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD):
2571 /* This relax is only for bsr and bra. */
2572 assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
2573 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
2574 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
2576 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]);
2578 fix_new (fragP, fragP->fr_fix - 1, 2,
2579 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2583 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE):
2584 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_BYTE):
2585 fragP->fr_opcode[1] = disp;
2588 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD):
2589 /* Invert branch. */
2590 fragP->fr_opcode[0] ^= 1;
2591 fragP->fr_opcode[1] = 3; /* Branch offset. */
2592 buffer_address[0] = M6811_JMP;
2593 fix_new (fragP, fragP->fr_fix + 1, 2,
2594 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2598 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD):
2599 /* Translate branch into a long branch. */
2600 fragP->fr_opcode[1] = fragP->fr_opcode[0];
2601 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2;
2603 fixp = fix_new (fragP, fragP->fr_fix, 2,
2604 fragP->fr_symbol, fragP->fr_offset, 1,
2605 BFD_RELOC_16_PCREL);
2606 fixp->fx_pcrel_adjust = 2;
2610 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5):
2611 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 6;
2612 if ((fragP->fr_opcode[0] & 0x0ff) == 0x0c0)
2613 fragP->fr_opcode[0] |= disp & 0x1f;
2615 fragP->fr_opcode[0] |= value & 0x1f;
2618 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9):
2619 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3);
2620 fragP->fr_opcode[0] |= 0xE0;
2621 fix_new (fragP, fragP->fr_fix, 1,
2622 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_8);
2626 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16):
2627 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3);
2628 fragP->fr_opcode[0] |= 0xe2;
2629 if ((fragP->fr_opcode[0] & 0x0ff) == 0x0fa)
2631 fixp = fix_new (fragP, fragP->fr_fix, 2,
2632 fragP->fr_symbol, fragP->fr_offset,
2633 1, BFD_RELOC_16_PCREL);
2634 fixp->fx_pcrel_adjust = 2;
2638 fix_new (fragP, fragP->fr_fix, 2,
2639 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2644 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE):
2646 fragP->fr_opcode[0] |= 0x10;
2648 fragP->fr_opcode[1] = disp & 0x0FF;
2651 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD):
2652 /* Invert branch. */
2653 fragP->fr_opcode[0] ^= 0x20;
2654 fragP->fr_opcode[1] = 3; /* Branch offset. */
2655 buffer_address[0] = M6812_JMP;
2656 fix_new (fragP, fragP->fr_fix + 1, 2,
2657 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2666 /* On an ELF system, we can't relax a weak symbol. The weak symbol
2667 can be overridden at final link time by a non weak symbol. We can
2668 relax externally visible symbol because there is no shared library
2669 and such symbol can't be overridden (unless they are weak). */
2671 relaxable_symbol (symbol)
2674 return ! S_IS_WEAK (symbol);
2677 /* Force truly undefined symbols to their maximum size, and generally set up
2678 the frag list to be relaxed. */
2680 md_estimate_size_before_relax (fragP, segment)
2684 if (RELAX_LENGTH (fragP->fr_subtype) == STATE_UNDF)
2686 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
2687 || !relaxable_symbol (fragP->fr_symbol))
2689 /* Non-relaxable cases. */
2691 char *buffer_address;
2693 old_fr_fix = fragP->fr_fix;
2694 buffer_address = fragP->fr_fix + fragP->fr_literal;
2696 switch (RELAX_STATE (fragP->fr_subtype))
2698 case STATE_PC_RELATIVE:
2700 /* This relax is only for bsr and bra. */
2701 assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
2702 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
2703 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
2705 if (flag_fixed_branchs)
2706 as_bad_where (fragP->fr_file, fragP->fr_line,
2707 _("bra or bsr with undefined symbol."));
2709 /* The symbol is undefined or in a separate section.
2710 Turn bra into a jmp and bsr into a jsr. The insn
2711 becomes 3 bytes long (instead of 2). A fixup is
2712 necessary for the unresolved symbol address. */
2713 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]);
2715 fix_new (fragP, fragP->fr_fix - 1, 2, fragP->fr_symbol,
2716 fragP->fr_offset, 0, BFD_RELOC_16);
2720 case STATE_CONDITIONAL_BRANCH:
2721 assert (current_architecture & cpu6811);
2723 fragP->fr_opcode[0] ^= 1; /* Reverse sense of branch. */
2724 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */
2726 /* Don't use fr_opcode[2] because this may be
2727 in a different frag. */
2728 buffer_address[0] = M6811_JMP;
2731 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2732 fragP->fr_offset, 0, BFD_RELOC_16);
2736 case STATE_INDEXED_OFFSET:
2737 assert (current_architecture & cpu6812);
2739 /* Switch the indexed operation to 16-bit mode. */
2740 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 3;
2741 fragP->fr_opcode[0] |= 0xe2;
2743 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2744 fragP->fr_offset, 0, BFD_RELOC_16);
2748 case STATE_XBCC_BRANCH:
2749 assert (current_architecture & cpu6812);
2751 fragP->fr_opcode[0] ^= 0x20; /* Reverse sense of branch. */
2752 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */
2754 /* Don't use fr_opcode[2] because this may be
2755 in a different frag. */
2756 buffer_address[0] = M6812_JMP;
2759 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2760 fragP->fr_offset, 0, BFD_RELOC_16);
2764 case STATE_CONDITIONAL_BRANCH_6812:
2765 assert (current_architecture & cpu6812);
2767 /* Translate into a lbcc branch. */
2768 fragP->fr_opcode[1] = fragP->fr_opcode[0];
2769 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2;
2771 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2772 fragP->fr_offset, 0, BFD_RELOC_16_PCREL);
2777 as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype);
2781 /* Return the growth in the fixed part of the frag. */
2782 return fragP->fr_fix - old_fr_fix;
2785 /* Relaxable cases. */
2786 switch (RELAX_STATE (fragP->fr_subtype))
2788 case STATE_PC_RELATIVE:
2789 /* This relax is only for bsr and bra. */
2790 assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
2791 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
2792 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
2794 fragP->fr_subtype = ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE);
2797 case STATE_CONDITIONAL_BRANCH:
2798 assert (current_architecture & cpu6811);
2800 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH,
2804 case STATE_INDEXED_OFFSET:
2805 assert (current_architecture & cpu6812);
2807 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET,
2811 case STATE_XBCC_BRANCH:
2812 assert (current_architecture & cpu6812);
2814 fragP->fr_subtype = ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE);
2817 case STATE_CONDITIONAL_BRANCH_6812:
2818 assert (current_architecture & cpu6812);
2820 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812,
2826 if (fragP->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
2827 as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype);
2829 /* Return the size of the variable part of the frag. */
2830 return md_relax_table[fragP->fr_subtype].rlx_length;
2834 md_apply_fix3 (fixP, valP, seg)
2837 segT seg ATTRIBUTE_UNUSED;
2840 long value = * valP;
2843 if (fixP->fx_addsy == (symbolS *) NULL)
2846 else if (fixP->fx_pcrel)
2851 value = fixP->fx_offset;
2853 if (fixP->fx_subsy != (symbolS *) NULL)
2855 if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)
2856 value -= S_GET_VALUE (fixP->fx_subsy);
2858 /* We don't actually support subtracting a symbol. */
2859 as_bad_where (fixP->fx_file, fixP->fx_line,
2860 _("Expression too complex."));
2864 op_type = fixP->fx_r_type;
2866 /* Patch the instruction with the resolved operand. Elf relocation
2867 info will also be generated to take care of linker/loader fixups.
2868 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
2869 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
2870 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
2871 because it's either resolved or turned out into non-relative insns (see
2872 relax table, bcc, bra, bsr transformations)
2874 The BFD_RELOC_32 is necessary for the support of --gstabs. */
2875 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2877 switch (fixP->fx_r_type)
2880 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
2884 case BFD_RELOC_M68HC11_24:
2885 bfd_putb16 ((bfd_vma) (value & 0x0ffff), (unsigned char *) where);
2886 ((bfd_byte*) where)[2] = ((value >> 16) & 0x0ff);
2890 case BFD_RELOC_16_PCREL:
2891 case BFD_RELOC_M68HC11_LO16:
2892 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
2893 if (value < -65537 || value > 65535)
2894 as_bad_where (fixP->fx_file, fixP->fx_line,
2895 _("Value out of 16-bit range."));
2898 case BFD_RELOC_M68HC11_HI8:
2902 case BFD_RELOC_M68HC11_LO8:
2904 case BFD_RELOC_M68HC11_PAGE:
2906 bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
2908 ((bfd_byte *) where)[0] = (bfd_byte) value;
2911 case BFD_RELOC_8_PCREL:
2913 bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
2915 ((bfd_byte *) where)[0] = (bfd_byte) value;
2917 if (value < -128 || value > 127)
2918 as_bad_where (fixP->fx_file, fixP->fx_line,
2919 _("Value %ld too large for 8-bit PC-relative branch."),
2923 case BFD_RELOC_M68HC11_3B:
2924 if (value <= 0 || value > 8)
2925 as_bad_where (fixP->fx_file, fixP->fx_line,
2926 _("Auto increment/decrement offset '%ld' is out of range."),
2933 where[0] = where[0] | (value & 0x07);
2937 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
2938 fixP->fx_line, fixP->fx_r_type);