1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "safe-ctype.h"
26 #include "opcode/m68hc11.h"
27 #include "dwarf2dbg.h"
28 #include "elf/m68hc11.h"
30 const char comment_chars[] = ";!";
31 const char line_comment_chars[] = "#*";
32 const char line_separator_chars[] = "";
34 const char EXP_CHARS[] = "eE";
35 const char FLT_CHARS[] = "dD";
37 #define STATE_CONDITIONAL_BRANCH (1)
38 #define STATE_PC_RELATIVE (2)
39 #define STATE_INDEXED_OFFSET (3)
40 #define STATE_XBCC_BRANCH (4)
41 #define STATE_CONDITIONAL_BRANCH_6812 (5)
43 #define STATE_BYTE (0)
44 #define STATE_BITS5 (0)
45 #define STATE_WORD (1)
46 #define STATE_BITS9 (1)
47 #define STATE_LONG (2)
48 #define STATE_BITS16 (2)
49 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
51 /* This macro has no side-effects. */
52 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
53 #define RELAX_STATE(s) ((s) >> 2)
54 #define RELAX_LENGTH(s) ((s) & 3)
56 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
58 /* This table describes how you change sizes for the various types of variable
59 size expressions. This version only supports two kinds. */
62 How far Forward this mode will reach.
63 How far Backward this mode will reach.
64 How many bytes this mode will add to the size of the frag.
65 Which mode to go to if the offset won't fit in this one. */
67 relax_typeS md_relax_table[] = {
68 {1, 1, 0, 0}, /* First entries aren't used. */
69 {1, 1, 0, 0}, /* For no good reason except. */
70 {1, 1, 0, 0}, /* that the VAX doesn't either. */
74 These insns are translated into b!cc +3 jmp L. */
75 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD)},
80 /* Relax for bsr <L> and bra <L>.
81 These insns are translated into jsr and jmp. */
82 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD)},
87 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
88 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9)},
89 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16)},
93 /* Relax for dbeq/ibeq/tbeq r,<L>:
94 These insns are translated into db!cc +3 jmp L. */
95 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD)},
100 /* Relax for bcc <L> on 68HC12.
101 These insns are translated into lbcc <L>. */
102 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD)},
109 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
110 typedef enum register_id {
122 typedef struct operand {
129 struct m68hc11_opcode_def {
135 struct m68hc11_opcode *opcode;
138 static struct m68hc11_opcode_def *m68hc11_opcode_defs = 0;
139 static int m68hc11_nb_opcode_defs = 0;
141 typedef struct alias {
146 static alias alias_opcodes[] = {
153 /* Local functions. */
154 static register_id reg_name_search PARAMS ((char *));
155 static register_id register_name PARAMS ((void));
156 static int cmp_opcode PARAMS ((struct m68hc11_opcode *,
157 struct m68hc11_opcode *));
158 static char *print_opcode_format PARAMS ((struct m68hc11_opcode *, int));
159 static char *skip_whites PARAMS ((char *));
160 static int check_range PARAMS ((long, int));
161 static void print_opcode_list PARAMS ((void));
162 static void get_default_target PARAMS ((void));
163 static void print_insn_format PARAMS ((char *));
164 static int get_operand PARAMS ((operand *, int, long));
165 static void fixup8 PARAMS ((expressionS *, int, int));
166 static void fixup16 PARAMS ((expressionS *, int, int));
167 static void fixup24 PARAMS ((expressionS *, int, int));
168 static unsigned char convert_branch PARAMS ((unsigned char));
169 static char *m68hc11_new_insn PARAMS ((int));
170 static void build_dbranch_insn PARAMS ((struct m68hc11_opcode *,
171 operand *, int, int));
172 static int build_indexed_byte PARAMS ((operand *, int, int));
173 static int build_reg_mode PARAMS ((operand *, int));
175 static struct m68hc11_opcode *find
176 PARAMS ((struct m68hc11_opcode_def *, operand *, int));
177 static struct m68hc11_opcode *find_opcode
178 PARAMS ((struct m68hc11_opcode_def *, operand *, int *));
179 static void build_jump_insn
180 PARAMS ((struct m68hc11_opcode *, operand *, int, int));
181 static void build_insn
182 PARAMS ((struct m68hc11_opcode *, operand *, int));
183 static int relaxable_symbol PARAMS ((symbolS *));
185 /* Pseudo op to indicate a relax group. */
186 static void s_m68hc11_relax PARAMS((int));
188 /* Pseudo op to control the ELF flags. */
189 static void s_m68hc11_mode PARAMS ((int));
191 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
192 are using 'rtc' for returning. It is necessary to use 'call'
193 to invoke them. This is also used by the debugger to correctly
194 find the stack frame. */
195 static void s_m68hc11_mark_symbol PARAMS ((int));
197 /* Controls whether relative branches can be turned into long branches.
198 When the relative offset is too large, the insn are changed:
206 Setting the flag forbidds this. */
207 static short flag_fixed_branchs = 0;
209 /* Force to use long jumps (absolute) instead of relative branches. */
210 static short flag_force_long_jumps = 0;
212 /* Change the direct addressing mode into an absolute addressing mode
213 when the insn does not support direct addressing.
214 For example, "clr *ZD0" is normally not possible and is changed
216 static short flag_strict_direct_addressing = 1;
218 /* When an opcode has invalid operand, print out the syntax of the opcode
220 static short flag_print_insn_syntax = 0;
222 /* Dumps the list of instructions with syntax and then exit:
223 1 -> Only dumps the list (sorted by name)
224 2 -> Generate an example (or test) that can be compiled. */
225 static short flag_print_opcodes = 0;
227 /* Opcode hash table. */
228 static struct hash_control *m68hc11_hash;
230 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
231 by 'get_default_target' by looking at default BFD vector. This is overriden
232 with the -m<cpu> option. */
233 static int current_architecture = 0;
235 /* Default cpu determined by 'get_default_target'. */
236 static const char *default_cpu;
238 /* Number of opcodes in the sorted table (filtered by current cpu). */
239 static int num_opcodes;
241 /* The opcodes sorted by name and filtered by current cpu. */
242 static struct m68hc11_opcode *m68hc11_sorted_opcodes;
244 /* ELF flags to set in the output file header. */
245 static int elf_flags = E_M68HC11_F64;
247 /* These are the machine dependent pseudo-ops. These are included so
248 the assembler can work on the output from the SUN C compiler, which
251 /* This table describes all the machine specific pseudo-ops the assembler
252 has to support. The fields are:
253 pseudo-op name without dot
254 function to call to execute this pseudo-op
255 Integer arg to pass to the function. */
256 const pseudo_typeS md_pseudo_table[] = {
257 /* The following pseudo-ops are supported for MRI compatibility. */
260 {"fcc", stringer, 1},
263 /* Dwarf2 support for Gcc. */
264 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
265 {"loc", dwarf2_directive_loc, 0},
268 {"xrefb", s_ignore, 0}, /* Same as xref */
270 /* Gcc driven relaxation. */
271 {"relax", s_m68hc11_relax, 0},
273 /* .mode instruction (ala SH). */
274 {"mode", s_m68hc11_mode, 0},
276 /* .far instruction. */
277 {"far", s_m68hc11_mark_symbol, STO_M68HC12_FAR},
279 /* .interrupt instruction. */
280 {"interrupt", s_m68hc11_mark_symbol, STO_M68HC12_INTERRUPT},
285 /* Options and initialization. */
287 const char *md_shortopts = "Sm:";
289 struct option md_longopts[] = {
290 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
291 {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH},
293 #define OPTION_SHORT_BRANCHS (OPTION_MD_BASE + 1)
294 {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHS},
296 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
297 {"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE},
299 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
300 {"print-insn-syntax", no_argument, NULL, OPTION_PRINT_INSN_SYNTAX},
302 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
303 {"print-opcodes", no_argument, NULL, OPTION_PRINT_OPCODES},
305 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
306 {"generate-example", no_argument, NULL, OPTION_GENERATE_EXAMPLE},
308 #define OPTION_MSHORT (OPTION_MD_BASE + 6)
309 {"mshort", no_argument, NULL, OPTION_MSHORT},
311 #define OPTION_MLONG (OPTION_MD_BASE + 7)
312 {"mlong", no_argument, NULL, OPTION_MLONG},
314 #define OPTION_MSHORT_DOUBLE (OPTION_MD_BASE + 8)
315 {"mshort-double", no_argument, NULL, OPTION_MSHORT_DOUBLE},
317 #define OPTION_MLONG_DOUBLE (OPTION_MD_BASE + 9)
318 {"mlong-double", no_argument, NULL, OPTION_MLONG_DOUBLE},
320 {NULL, no_argument, NULL, 0}
322 size_t md_longopts_size = sizeof (md_longopts);
324 /* Get the target cpu for the assembler. This is based on the configure
325 options and on the -m68hc11/-m68hc12 option. If no option is specified,
326 we must get the default. */
328 m68hc11_arch_format ()
330 get_default_target ();
331 if (current_architecture & cpu6811)
332 return "elf32-m68hc11";
334 return "elf32-m68hc12";
337 enum bfd_architecture
340 get_default_target ();
341 if (current_architecture & cpu6811)
342 return bfd_arch_m68hc11;
344 return bfd_arch_m68hc12;
353 /* Listing header selected according to cpu. */
355 m68hc11_listing_header ()
357 if (current_architecture & cpu6811)
358 return "M68HC11 GAS ";
360 return "M68HC12 GAS ";
364 md_show_usage (stream)
367 get_default_target ();
368 fprintf (stream, _("\
369 Motorola 68HC11/68HC12 options:\n\
370 -m68hc11 | -m68hc12 specify the processor [default %s]\n\
371 -mshort use 16-bit int ABI (default)\n\
372 -mlong use 32-bit int ABI\n\
373 -mshort-double use 32-bit double ABI\n\
374 -mlong-double use 64-bit double ABI (default)\n\
375 --force-long-branchs always turn relative branchs into absolute ones\n\
376 -S,--short-branchs do not turn relative branchs into absolute ones\n\
377 when the offset is out of range\n\
378 --strict-direct-mode do not turn the direct mode into extended mode\n\
379 when the instruction does not support direct mode\n\
380 --print-insn-syntax print the syntax of instruction in case of error\n\
381 --print-opcodes print the list of instructions with syntax\n\
382 --generate-example generate an example of each instruction\n\
383 (used for testing)\n"), default_cpu);
387 /* Try to identify the default target based on the BFD library. */
389 get_default_target ()
391 const bfd_target *target;
394 if (current_architecture != 0)
397 default_cpu = "unknown";
398 target = bfd_find_target (0, &abfd);
399 if (target && target->name)
401 if (strcmp (target->name, "elf32-m68hc12") == 0)
403 current_architecture = cpu6812;
404 default_cpu = "m68hc12";
406 else if (strcmp (target->name, "elf32-m68hc11") == 0)
408 current_architecture = cpu6811;
409 default_cpu = "m68hc11";
413 as_bad (_("Default target `%s' is not supported."), target->name);
419 m68hc11_print_statistics (file)
423 struct m68hc11_opcode_def *opc;
425 hash_print_statistics (file, "opcode table", m68hc11_hash);
427 opc = m68hc11_opcode_defs;
428 if (opc == 0 || m68hc11_nb_opcode_defs == 0)
431 /* Dump the opcode statistics table. */
432 fprintf (file, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
433 for (i = 0; i < m68hc11_nb_opcode_defs; i++, opc++)
435 fprintf (file, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
438 opc->min_operands, opc->max_operands, opc->format, opc->used);
443 md_parse_option (c, arg)
447 get_default_target ();
450 /* -S means keep external to 2 bit offset rather than 16 bit one. */
451 case OPTION_SHORT_BRANCHS:
453 flag_fixed_branchs = 1;
456 case OPTION_FORCE_LONG_BRANCH:
457 flag_force_long_jumps = 1;
460 case OPTION_PRINT_INSN_SYNTAX:
461 flag_print_insn_syntax = 1;
464 case OPTION_PRINT_OPCODES:
465 flag_print_opcodes = 1;
468 case OPTION_STRICT_DIRECT_MODE:
469 flag_strict_direct_addressing = 0;
472 case OPTION_GENERATE_EXAMPLE:
473 flag_print_opcodes = 2;
477 elf_flags &= ~E_M68HC11_I32;
481 elf_flags |= E_M68HC11_I32;
484 case OPTION_MSHORT_DOUBLE:
485 elf_flags &= ~E_M68HC11_F64;
488 case OPTION_MLONG_DOUBLE:
489 elf_flags |= E_M68HC11_F64;
493 if (strcasecmp (arg, "68hc11") == 0)
494 current_architecture = cpu6811;
495 else if (strcasecmp (arg, "68hc12") == 0)
496 current_architecture = cpu6812;
498 as_bad (_("Option `%s' is not recognized."), arg);
509 md_undefined_symbol (name)
510 char *name ATTRIBUTE_UNUSED;
515 /* Equal to MAX_PRECISION in atof-ieee.c. */
516 #define MAX_LITTLENUMS 6
518 /* Turn a string in input_line_pointer into a floating point constant
519 of type TYPE, and store the appropriate bytes in *LITP. The number
520 of LITTLENUMS emitted is stored in *SIZEP. An error message is
521 returned, or NULL on OK. */
523 md_atof (type, litP, sizeP)
529 LITTLENUM_TYPE words[MAX_LITTLENUMS];
530 LITTLENUM_TYPE *wordP;
561 return _("Bad call to MD_ATOF()");
563 t = atof_ieee (input_line_pointer, type, words);
565 input_line_pointer = t;
567 *sizeP = prec * sizeof (LITTLENUM_TYPE);
568 for (wordP = words; prec--;)
570 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
571 litP += sizeof (LITTLENUM_TYPE);
577 md_section_align (seg, addr)
581 int align = bfd_get_section_alignment (stdoutput, seg);
582 return ((addr + (1 << align) - 1) & (-1 << align));
586 cmp_opcode (op1, op2)
587 struct m68hc11_opcode *op1;
588 struct m68hc11_opcode *op2;
590 return strcmp (op1->name, op2->name);
593 #define IS_CALL_SYMBOL(MODE) \
594 (((MODE) & (M6812_OP_PAGE|M6811_OP_IND16)) \
595 == ((M6812_OP_PAGE|M6811_OP_IND16)))
597 /* Initialize the assembler. Create the opcode hash table
598 (sorted on the names) with the M6811 opcode table
599 (from opcode library). */
603 char *prev_name = "";
604 struct m68hc11_opcode *opcodes;
605 struct m68hc11_opcode_def *opc = 0;
608 get_default_target ();
610 m68hc11_hash = hash_new ();
612 /* Get a writable copy of the opcode table and sort it on the names. */
613 opcodes = (struct m68hc11_opcode *) xmalloc (m68hc11_num_opcodes *
616 m68hc11_sorted_opcodes = opcodes;
618 for (i = 0; i < m68hc11_num_opcodes; i++)
620 if (m68hc11_opcodes[i].arch & current_architecture)
622 opcodes[num_opcodes] = m68hc11_opcodes[i];
623 if (opcodes[num_opcodes].name[0] == 'b'
624 && opcodes[num_opcodes].format & M6811_OP_JUMP_REL
625 && !(opcodes[num_opcodes].format & M6811_OP_BITMASK))
628 opcodes[num_opcodes] = m68hc11_opcodes[i];
631 for (j = 0; alias_opcodes[j].name != 0; j++)
632 if (strcmp (m68hc11_opcodes[i].name, alias_opcodes[j].name) == 0)
634 opcodes[num_opcodes] = m68hc11_opcodes[i];
635 opcodes[num_opcodes].name = alias_opcodes[j].alias;
641 qsort (opcodes, num_opcodes, sizeof (struct m68hc11_opcode), cmp_opcode);
643 opc = (struct m68hc11_opcode_def *)
644 xmalloc (num_opcodes * sizeof (struct m68hc11_opcode_def));
645 m68hc11_opcode_defs = opc--;
647 /* Insert unique names into hash table. The M6811 instruction set
648 has several identical opcode names that have different opcodes based
649 on the operands. This hash table then provides a quick index to
650 the first opcode with a particular name in the opcode table. */
651 for (i = 0; i < num_opcodes; i++, opcodes++)
655 if (strcmp (prev_name, opcodes->name))
657 prev_name = (char *) opcodes->name;
661 opc->min_operands = 100;
662 opc->max_operands = 0;
664 opc->opcode = opcodes;
666 hash_insert (m68hc11_hash, opcodes->name, (char *) opc);
669 opc->format |= opcodes->format;
671 /* See how many operands this opcode needs. */
673 if (opcodes->format & M6811_OP_MASK)
675 if (opcodes->format & M6811_OP_BITMASK)
677 if (opcodes->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
679 if (opcodes->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
681 /* Special case for call instruction. */
682 if ((opcodes->format & M6812_OP_PAGE)
683 && !(opcodes->format & M6811_OP_IND16))
686 if (expect < opc->min_operands)
687 opc->min_operands = expect;
688 if (IS_CALL_SYMBOL (opcodes->format))
690 if (expect > opc->max_operands)
691 opc->max_operands = expect;
694 m68hc11_nb_opcode_defs = opc - m68hc11_opcode_defs;
696 if (flag_print_opcodes)
698 print_opcode_list ();
704 m68hc11_init_after_args ()
710 /* Return a string that represents the operand format for the instruction.
711 When example is true, this generates an example of operand. This is used
712 to give an example and also to generate a test. */
714 print_opcode_format (opcode, example)
715 struct m68hc11_opcode *opcode;
718 static char buf[128];
719 int format = opcode->format;
724 if (format & M6811_OP_IMM8)
727 sprintf (p, "#%d", rand () & 0x0FF);
729 strcpy (p, _("#<imm8>"));
733 if (format & M6811_OP_IMM16)
736 sprintf (p, "#%d", rand () & 0x0FFFF);
738 strcpy (p, _("#<imm16>"));
742 if (format & M6811_OP_IX)
745 sprintf (p, "%d,X", rand () & 0x0FF);
747 strcpy (p, _("<imm8>,X"));
751 if (format & M6811_OP_IY)
754 sprintf (p, "%d,X", rand () & 0x0FF);
756 strcpy (p, _("<imm8>,X"));
760 if (format & M6812_OP_IDX)
763 sprintf (p, "%d,X", rand () & 0x0FF);
769 if (format & M6812_OP_PAGE)
772 sprintf (p, ", %d", rand () & 0x0FF);
774 strcpy (p, ", <page>");
778 if (format & M6811_OP_DIRECT)
781 sprintf (p, "*Z%d", rand () & 0x0FF);
783 strcpy (p, _("*<abs8>"));
787 if (format & M6811_OP_BITMASK)
793 sprintf (p, "#$%02x", rand () & 0x0FF);
795 strcpy (p, _("#<mask>"));
798 if (format & M6811_OP_JUMP_REL)
802 if (format & M6811_OP_IND16)
805 sprintf (p, _("symbol%d"), rand () & 0x0FF);
807 strcpy (p, _("<abs>"));
812 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
816 if (format & M6811_OP_BITMASK)
818 sprintf (p, ".+%d", rand () & 0x7F);
822 sprintf (p, "L%d", rand () & 0x0FF);
826 strcpy (p, _("<label>"));
832 /* Prints the list of instructions with the possible operands. */
837 char *prev_name = "";
838 struct m68hc11_opcode *opcodes;
839 int example = flag_print_opcodes == 2;
842 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
845 opcodes = m68hc11_sorted_opcodes;
847 /* Walk the list sorted on names (by md_begin). We only report
848 one instruction per line, and we collect the different operand
850 for (i = 0; i < num_opcodes; i++, opcodes++)
852 char *fmt = print_opcode_format (opcodes, example);
856 printf ("L%d:\t", i);
857 printf ("%s %s\n", opcodes->name, fmt);
861 if (strcmp (prev_name, opcodes->name))
866 printf ("%-5.5s ", opcodes->name);
867 prev_name = (char *) opcodes->name;
870 printf (" [%s]", fmt);
876 /* Print the instruction format. This operation is called when some
877 instruction is not correct. Instruction format is printed as an
880 print_insn_format (name)
883 struct m68hc11_opcode_def *opc;
884 struct m68hc11_opcode *opcode;
887 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name);
890 as_bad (_("Instruction `%s' is not recognized."), name);
893 opcode = opc->opcode;
895 as_bad (_("Instruction formats for `%s':"), name);
900 fmt = print_opcode_format (opcode, 0);
901 sprintf (buf, "\t%-5.5s %s", opcode->name, fmt);
906 while (strcmp (opcode->name, name) == 0);
909 /* Analysis of 68HC11 and 68HC12 operands. */
911 /* reg_name_search() finds the register number given its name.
912 Returns the register number or REG_NONE on failure. */
914 reg_name_search (name)
917 if (strcasecmp (name, "x") == 0 || strcasecmp (name, "ix") == 0)
919 if (strcasecmp (name, "y") == 0 || strcasecmp (name, "iy") == 0)
921 if (strcasecmp (name, "a") == 0)
923 if (strcasecmp (name, "b") == 0)
925 if (strcasecmp (name, "d") == 0)
927 if (strcasecmp (name, "sp") == 0)
929 if (strcasecmp (name, "pc") == 0)
931 if (strcasecmp (name, "ccr") == 0)
941 while (*p == ' ' || *p == '\t')
947 /* Check the string at input_line_pointer
948 to see if it is a valid register name. */
952 register_id reg_number;
953 char c, *p = input_line_pointer;
955 if (!is_name_beginner (*p++))
958 while (is_part_of_name (*p++))
965 /* Look to see if it's in the register table. */
966 reg_number = reg_name_search (input_line_pointer);
967 if (reg_number != REG_NONE)
972 input_line_pointer = p;
981 /* Parse a string of operands and return an array of expressions.
983 Operand mode[0] mode[1] exp[0] exp[1]
984 #n M6811_OP_IMM16 - O_*
985 *<exp> M6811_OP_DIRECT - O_*
986 .{+-}<exp> M6811_OP_JUMP_REL - O_*
987 <exp> M6811_OP_IND16 - O_*
988 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
989 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
990 n,+r M6812_PRE_INC " "
991 n,r- M6812_POST_DEC " "
992 n,r+ M6812_POST_INC " "
993 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
994 [D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register
995 [n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */
997 get_operand (oper, which, opmode)
1002 char *p = input_line_pointer;
1006 oper->exp.X_op = O_absent;
1007 oper->reg1 = REG_NONE;
1008 oper->reg2 = REG_NONE;
1009 mode = M6811_OP_NONE;
1011 p = skip_whites (p);
1013 if (*p == 0 || *p == '\n' || *p == '\r')
1015 input_line_pointer = p;
1019 if (*p == '*' && (opmode & (M6811_OP_DIRECT | M6811_OP_IND16)))
1021 mode = M6811_OP_DIRECT;
1026 if (!(opmode & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK)))
1028 as_bad (_("Immediate operand is not allowed for operand %d."),
1033 mode = M6811_OP_IMM16;
1035 if (strncmp (p, "%hi", 3) == 0)
1038 mode |= M6811_OP_HIGH_ADDR;
1040 else if (strncmp (p, "%lo", 3) == 0)
1043 mode |= M6811_OP_LOW_ADDR;
1046 else if (*p == '.' && (p[1] == '+' || p[1] == '-'))
1049 mode = M6811_OP_JUMP_REL;
1053 if (current_architecture & cpu6811)
1054 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
1057 mode = M6812_OP_D_IDX;
1058 p = skip_whites (p);
1060 else if (*p == ',') /* Special handling of ,x and ,y. */
1063 input_line_pointer = p;
1065 reg = register_name ();
1066 if (reg != REG_NONE)
1069 oper->exp.X_op = O_constant;
1070 oper->exp.X_add_number = 0;
1071 oper->mode = M6812_OP_IDX;
1074 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
1077 input_line_pointer = p;
1079 if (mode == M6811_OP_NONE || mode == M6812_OP_D_IDX)
1080 reg = register_name ();
1084 if (reg != REG_NONE)
1086 p = skip_whites (input_line_pointer);
1087 if (*p == ']' && mode == M6812_OP_D_IDX)
1090 (_("Missing second register or offset for indexed-indirect mode."));
1095 oper->mode = mode | M6812_OP_REG;
1098 if (mode == M6812_OP_D_IDX)
1100 as_bad (_("Missing second register for indexed-indirect mode."));
1107 input_line_pointer = p;
1108 reg = register_name ();
1109 if (reg != REG_NONE)
1111 p = skip_whites (input_line_pointer);
1112 if (mode == M6812_OP_D_IDX)
1116 as_bad (_("Missing `]' to close indexed-indirect mode."));
1120 oper->mode = M6812_OP_D_IDX;
1122 input_line_pointer = p;
1130 /* In MRI mode, isolate the operand because we can't distinguish
1131 operands from comments. */
1136 p = skip_whites (p);
1137 while (*p && *p != ' ' && *p != '\t')
1146 /* Parse as an expression. */
1147 expression (&oper->exp);
1156 expression (&oper->exp);
1159 if (oper->exp.X_op == O_illegal)
1161 as_bad (_("Illegal operand."));
1164 else if (oper->exp.X_op == O_absent)
1166 as_bad (_("Missing operand."));
1170 p = input_line_pointer;
1172 if (mode == M6811_OP_NONE || mode == M6811_OP_DIRECT
1173 || mode == M6812_OP_D_IDX)
1175 p = skip_whites (input_line_pointer);
1179 int possible_mode = M6811_OP_NONE;
1180 char *old_input_line;
1185 /* 68HC12 pre increment or decrement. */
1186 if (mode == M6811_OP_NONE)
1190 possible_mode = M6812_PRE_DEC;
1195 possible_mode = M6812_PRE_INC;
1198 p = skip_whites (p);
1200 input_line_pointer = p;
1201 reg = register_name ();
1203 /* Backtrack if we have a valid constant expression and
1204 it does not correspond to the offset of the 68HC12 indexed
1205 addressing mode (as in N,x). */
1206 if (reg == REG_NONE && mode == M6811_OP_NONE
1207 && possible_mode != M6811_OP_NONE)
1209 oper->mode = M6811_OP_IND16 | M6811_OP_JUMP_REL;
1210 input_line_pointer = skip_whites (old_input_line);
1214 if (possible_mode != M6811_OP_NONE)
1215 mode = possible_mode;
1217 if ((current_architecture & cpu6811)
1218 && possible_mode != M6811_OP_NONE)
1219 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1221 if (which == 0 && opmode & M6812_OP_IDX_P2
1222 && reg != REG_X && reg != REG_Y
1223 && reg != REG_PC && reg != REG_SP)
1226 input_line_pointer = p;
1229 if (reg == REG_NONE && mode != M6811_OP_DIRECT
1230 && !(mode == M6811_OP_NONE && opmode & M6811_OP_IND16))
1232 as_bad (_("Wrong register in register indirect mode."));
1235 if (mode == M6812_OP_D_IDX)
1237 p = skip_whites (input_line_pointer);
1240 as_bad (_("Missing `]' to close register indirect operand."));
1243 input_line_pointer = p;
1245 oper->mode = M6812_OP_D_IDX_2;
1248 if (reg != REG_NONE)
1251 if (mode == M6811_OP_NONE)
1253 p = input_line_pointer;
1256 mode = M6812_POST_DEC;
1258 if (current_architecture & cpu6811)
1260 (_("Post-decrement mode is not valid for 68HC11."));
1264 mode = M6812_POST_INC;
1266 if (current_architecture & cpu6811)
1268 (_("Post-increment mode is not valid for 68HC11."));
1271 mode = M6812_OP_IDX;
1273 input_line_pointer = p;
1276 mode |= M6812_OP_IDX;
1281 input_line_pointer = old_input_line;
1284 if (mode == M6812_OP_D_IDX_2)
1286 as_bad (_("Invalid indexed indirect mode."));
1291 /* If the mode is not known until now, this is either a label
1292 or an indirect address. */
1293 if (mode == M6811_OP_NONE)
1294 mode = M6811_OP_IND16 | M6811_OP_JUMP_REL;
1296 p = input_line_pointer;
1297 while (*p == ' ' || *p == '\t')
1299 input_line_pointer = p;
1305 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1306 | M6812_POST_INC | M6812_POST_DEC)
1308 /* Checks that the number 'num' fits for a given mode. */
1310 check_range (num, mode)
1314 /* Auto increment and decrement are ok for [-8..8] without 0. */
1315 if (mode & M6812_AUTO_INC_DEC)
1316 return (num != 0 && num <= 8 && num >= -8);
1318 /* The 68HC12 supports 5, 9 and 16-bit offsets. */
1319 if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX))
1320 mode = M6811_OP_IND16;
1322 if (mode & M6812_OP_JUMP_REL16)
1323 mode = M6811_OP_IND16;
1325 mode &= ~M6811_OP_BRANCH;
1330 case M6811_OP_DIRECT:
1331 return (num >= 0 && num <= 255) ? 1 : 0;
1333 case M6811_OP_BITMASK:
1336 return (((num & 0xFFFFFF00) == 0) || ((num & 0xFFFFFF00) == 0xFFFFFF00))
1339 case M6811_OP_JUMP_REL:
1340 return (num >= -128 && num <= 127) ? 1 : 0;
1342 case M6811_OP_IND16:
1343 case M6811_OP_IND16 | M6812_OP_PAGE:
1344 case M6811_OP_IMM16:
1345 return (((num & 0xFFFF0000) == 0) || ((num & 0xFFFF0000) == 0xFFFF0000))
1348 case M6812_OP_IBCC_MARKER:
1349 case M6812_OP_TBCC_MARKER:
1350 case M6812_OP_DBCC_MARKER:
1351 return (num >= -256 && num <= 255) ? 1 : 0;
1353 case M6812_OP_TRAP_ID:
1354 return ((num >= 0x30 && num <= 0x39)
1355 || (num >= 0x40 && num <= 0x0ff)) ? 1 : 0;
1362 /* Gas fixup generation. */
1364 /* Put a 1 byte expression described by 'oper'. If this expression contains
1365 unresolved symbols, generate an 8-bit fixup. */
1367 fixup8 (oper, mode, opmode)
1376 if (oper->X_op == O_constant)
1378 if (mode & M6812_OP_TRAP_ID
1379 && !check_range (oper->X_add_number, M6812_OP_TRAP_ID))
1381 static char trap_id_warn_once = 0;
1383 as_bad (_("Trap id `%ld' is out of range."), oper->X_add_number);
1384 if (trap_id_warn_once == 0)
1386 trap_id_warn_once = 1;
1387 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1391 if (!(mode & M6812_OP_TRAP_ID)
1392 && !check_range (oper->X_add_number, mode))
1394 as_bad (_("Operand out of 8-bit range: `%ld'."), oper->X_add_number);
1396 number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1);
1398 else if (oper->X_op != O_register)
1400 if (mode & M6812_OP_TRAP_ID)
1401 as_bad (_("The trap id must be a constant."));
1403 if (mode == M6811_OP_JUMP_REL)
1407 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
1408 oper, TRUE, BFD_RELOC_8_PCREL);
1409 fixp->fx_pcrel_adjust = 1;
1413 /* Now create an 8-bit fixup. If there was some %hi or %lo
1414 modifier, generate the reloc accordingly. */
1415 fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
1417 ((opmode & M6811_OP_HIGH_ADDR)
1418 ? BFD_RELOC_M68HC11_HI8
1419 : ((opmode & M6811_OP_LOW_ADDR)
1420 ? BFD_RELOC_M68HC11_LO8
1421 : ((mode & M6812_OP_PAGE)
1422 ? BFD_RELOC_M68HC11_PAGE : BFD_RELOC_8))));
1424 number_to_chars_bigendian (f, 0, 1);
1428 as_fatal (_("Operand `%x' not recognized in fixup8."), oper->X_op);
1432 /* Put a 2 byte expression described by 'oper'. If this expression contains
1433 unresolved symbols, generate a 16-bit fixup. */
1435 fixup16 (oper, mode, opmode)
1438 int opmode ATTRIBUTE_UNUSED;
1444 if (oper->X_op == O_constant)
1446 if (!check_range (oper->X_add_number, mode))
1448 as_bad (_("Operand out of 16-bit range: `%ld'."),
1449 oper->X_add_number);
1451 number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFF, 2);
1453 else if (oper->X_op != O_register)
1457 /* Now create a 16-bit fixup. */
1458 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1460 (mode & M6812_OP_JUMP_REL16 ? TRUE : FALSE),
1461 (mode & M6812_OP_JUMP_REL16
1462 ? BFD_RELOC_16_PCREL
1463 : (mode & M6812_OP_PAGE)
1464 ? BFD_RELOC_M68HC11_LO16 : BFD_RELOC_16));
1465 number_to_chars_bigendian (f, 0, 2);
1466 if (mode & M6812_OP_JUMP_REL16)
1467 fixp->fx_pcrel_adjust = 2;
1471 as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op);
1475 /* Put a 3 byte expression described by 'oper'. If this expression contains
1476 unresolved symbols, generate a 24-bit fixup. */
1478 fixup24 (oper, mode, opmode)
1481 int opmode ATTRIBUTE_UNUSED;
1487 if (oper->X_op == O_constant)
1489 if (!check_range (oper->X_add_number, mode))
1491 as_bad (_("Operand out of 16-bit range: `%ld'."),
1492 oper->X_add_number);
1494 number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFFFF, 3);
1496 else if (oper->X_op != O_register)
1500 /* Now create a 24-bit fixup. */
1501 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1502 oper, FALSE, BFD_RELOC_M68HC11_24);
1503 number_to_chars_bigendian (f, 0, 3);
1507 as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op);
1511 /* 68HC11 and 68HC12 code generation. */
1513 /* Translate the short branch/bsr instruction into a long branch. */
1514 static unsigned char
1515 convert_branch (code)
1518 if (IS_OPCODE (code, M6812_BSR))
1520 else if (IS_OPCODE (code, M6811_BSR))
1522 else if (IS_OPCODE (code, M6811_BRA))
1523 return (current_architecture & cpu6812) ? M6812_JMP : M6811_JMP;
1525 as_fatal (_("Unexpected branch conversion with `%x'"), code);
1527 /* Keep gcc happy. */
1531 /* Start a new insn that contains at least 'size' bytes. Record the
1532 line information of that insn in the dwarf2 debug sections. */
1534 m68hc11_new_insn (size)
1539 f = frag_more (size);
1541 dwarf2_emit_insn (size);
1546 /* Builds a jump instruction (bra, bcc, bsr). */
1548 build_jump_insn (opcode, operands, nb_operands, jmp_mode)
1549 struct m68hc11_opcode *opcode;
1560 /* The relative branch convertion is not supported for
1562 assert ((opcode->format & M6811_OP_BITMASK) == 0);
1563 assert (nb_operands == 1);
1564 assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE);
1566 code = opcode->opcode;
1568 n = operands[0].exp.X_add_number;
1570 /* Turn into a long branch:
1571 - when force long branch option (and not for jbcc pseudos),
1572 - when jbcc and the constant is out of -128..127 range,
1573 - when branch optimization is allowed and branch out of range. */
1574 if ((jmp_mode == 0 && flag_force_long_jumps)
1575 || (operands[0].exp.X_op == O_constant
1576 && (!check_range (n, opcode->format) &&
1577 (jmp_mode == 1 || flag_fixed_branchs == 0))))
1580 where = frag_now_fix ();
1582 fix_new (frag_now, frag_now_fix (), 1,
1583 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
1585 if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
1587 code = convert_branch (code);
1589 f = m68hc11_new_insn (1);
1590 number_to_chars_bigendian (f, code, 1);
1592 else if (current_architecture & cpu6812)
1594 /* 68HC12: translate the bcc into a lbcc. */
1595 f = m68hc11_new_insn (2);
1596 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1597 number_to_chars_bigendian (f + 1, code, 1);
1598 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16,
1599 M6812_OP_JUMP_REL16);
1604 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1605 f = m68hc11_new_insn (3);
1607 number_to_chars_bigendian (f, code, 1);
1608 number_to_chars_bigendian (f + 1, 3, 1);
1609 number_to_chars_bigendian (f + 2, M6811_JMP, 1);
1611 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16);
1615 /* Branch with a constant that must fit in 8-bits. */
1616 if (operands[0].exp.X_op == O_constant)
1618 if (!check_range (n, opcode->format))
1620 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1623 else if (opcode->format & M6812_OP_JUMP_REL16)
1625 f = m68hc11_new_insn (4);
1626 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1627 number_to_chars_bigendian (f + 1, code, 1);
1628 number_to_chars_bigendian (f + 2, n & 0x0ffff, 2);
1632 f = m68hc11_new_insn (2);
1633 number_to_chars_bigendian (f, code, 1);
1634 number_to_chars_bigendian (f + 1, n & 0x0FF, 1);
1637 else if (opcode->format & M6812_OP_JUMP_REL16)
1640 where = frag_now_fix ();
1642 fix_new (frag_now, frag_now_fix (), 1,
1643 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
1645 f = m68hc11_new_insn (2);
1646 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1647 number_to_chars_bigendian (f + 1, code, 1);
1648 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16, M6812_OP_JUMP_REL16);
1655 where = frag_now_fix ();
1657 fix_new (frag_now, frag_now_fix (), 1,
1658 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
1660 /* Branch offset must fit in 8-bits, don't do some relax. */
1661 if (jmp_mode == 0 && flag_fixed_branchs)
1663 opcode = m68hc11_new_insn (1);
1664 number_to_chars_bigendian (opcode, code, 1);
1665 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL);
1668 /* bra/bsr made be changed into jmp/jsr. */
1669 else if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
1671 /* Allocate worst case storage. */
1672 opcode = m68hc11_new_insn (3);
1673 number_to_chars_bigendian (opcode, code, 1);
1674 number_to_chars_bigendian (opcode + 1, 0, 1);
1675 frag_variant (rs_machine_dependent, 1, 1,
1676 ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF),
1677 operands[0].exp.X_add_symbol, (offsetT) n,
1680 else if (current_architecture & cpu6812)
1682 opcode = m68hc11_new_insn (2);
1683 number_to_chars_bigendian (opcode, code, 1);
1684 number_to_chars_bigendian (opcode + 1, 0, 1);
1685 frag_var (rs_machine_dependent, 2, 2,
1686 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_UNDF),
1687 operands[0].exp.X_add_symbol, (offsetT) n, opcode);
1691 opcode = m68hc11_new_insn (2);
1692 number_to_chars_bigendian (opcode, code, 1);
1693 number_to_chars_bigendian (opcode + 1, 0, 1);
1694 frag_var (rs_machine_dependent, 3, 3,
1695 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF),
1696 operands[0].exp.X_add_symbol, (offsetT) n, opcode);
1701 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1703 build_dbranch_insn (opcode, operands, nb_operands, jmp_mode)
1704 struct m68hc11_opcode *opcode;
1713 /* The relative branch convertion is not supported for
1715 assert ((opcode->format & M6811_OP_BITMASK) == 0);
1716 assert (nb_operands == 2);
1717 assert (operands[0].reg1 != REG_NONE);
1719 code = opcode->opcode & 0x0FF;
1721 f = m68hc11_new_insn (1);
1722 number_to_chars_bigendian (f, code, 1);
1724 n = operands[1].exp.X_add_number;
1725 code = operands[0].reg1;
1727 if (operands[0].reg1 == REG_NONE || operands[0].reg1 == REG_CCR
1728 || operands[0].reg1 == REG_PC)
1729 as_bad (_("Invalid register for dbcc/tbcc instruction."));
1731 if (opcode->format & M6812_OP_IBCC_MARKER)
1733 else if (opcode->format & M6812_OP_TBCC_MARKER)
1736 if (!(opcode->format & M6812_OP_EQ_MARKER))
1739 /* Turn into a long branch:
1740 - when force long branch option (and not for jbcc pseudos),
1741 - when jdbcc and the constant is out of -256..255 range,
1742 - when branch optimization is allowed and branch out of range. */
1743 if ((jmp_mode == 0 && flag_force_long_jumps)
1744 || (operands[1].exp.X_op == O_constant
1745 && (!check_range (n, M6812_OP_IBCC_MARKER) &&
1746 (jmp_mode == 1 || flag_fixed_branchs == 0))))
1750 number_to_chars_bigendian (f, code, 1);
1751 number_to_chars_bigendian (f + 1, M6812_JMP, 1);
1752 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16);
1756 /* Branch with a constant that must fit in 9-bits. */
1757 if (operands[1].exp.X_op == O_constant)
1759 if (!check_range (n, M6812_OP_IBCC_MARKER))
1761 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1770 number_to_chars_bigendian (f, code, 1);
1771 number_to_chars_bigendian (f + 1, n & 0x0FF, 1);
1776 /* Branch offset must fit in 8-bits, don't do some relax. */
1777 if (jmp_mode == 0 && flag_fixed_branchs)
1779 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL);
1785 number_to_chars_bigendian (f, code, 1);
1786 number_to_chars_bigendian (f + 1, 0, 1);
1787 frag_var (rs_machine_dependent, 3, 3,
1788 ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_UNDF),
1789 operands[1].exp.X_add_symbol, (offsetT) n, f);
1794 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
1796 /* Assemble the post index byte for 68HC12 extended addressing modes. */
1798 build_indexed_byte (op, format, move_insn)
1800 int format ATTRIBUTE_UNUSED;
1803 unsigned char byte = 0;
1808 val = op->exp.X_add_number;
1810 if (mode & M6812_AUTO_INC_DEC)
1813 if (mode & (M6812_POST_INC | M6812_POST_DEC))
1816 if (op->exp.X_op == O_constant)
1818 if (!check_range (val, mode))
1820 as_bad (_("Increment/decrement value is out of range: `%ld'."),
1823 if (mode & (M6812_POST_INC | M6812_PRE_INC))
1824 byte |= (val - 1) & 0x07;
1826 byte |= (8 - ((val) & 7)) | 0x8;
1831 as_fatal (_("Expecting a register."));
1846 as_bad (_("Invalid register for post/pre increment."));
1851 number_to_chars_bigendian (f, byte, 1);
1855 if (mode & (M6812_OP_IDX | M6812_OP_D_IDX_2))
1876 as_bad (_("Invalid register."));
1879 if (op->exp.X_op == O_constant)
1881 if (!check_range (val, M6812_OP_IDX))
1883 as_bad (_("Offset out of 16-bit range: %ld."), val);
1886 if (move_insn && !(val >= -16 && val <= 15))
1888 as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
1893 if (val >= -16 && val <= 15 && !(mode & M6812_OP_D_IDX_2))
1898 number_to_chars_bigendian (f, byte, 1);
1901 else if (val >= -256 && val <= 255 && !(mode & M6812_OP_D_IDX_2))
1908 number_to_chars_bigendian (f, byte, 1);
1909 number_to_chars_bigendian (f + 1, val & 0x0FF, 1);
1915 if (mode & M6812_OP_D_IDX_2)
1921 number_to_chars_bigendian (f, byte, 1);
1922 number_to_chars_bigendian (f + 1, val & 0x0FFFF, 2);
1926 if (mode & M6812_OP_D_IDX_2)
1928 byte = (byte << 3) | 0xe3;
1930 number_to_chars_bigendian (f, byte, 1);
1932 fixup16 (&op->exp, 0, 0);
1934 else if (op->reg1 != REG_PC)
1936 byte = (byte << 3) | 0xe2;
1938 number_to_chars_bigendian (f, byte, 1);
1941 fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1942 &op->exp, FALSE, BFD_RELOC_16);
1943 number_to_chars_bigendian (f, 0, 2);
1948 number_to_chars_bigendian (f, byte, 1);
1949 frag_var (rs_machine_dependent, 2, 2,
1950 ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF),
1951 op->exp.X_add_symbol,
1952 op->exp.X_add_number, f);
1957 if (mode & (M6812_OP_REG | M6812_OP_D_IDX))
1959 if (mode & M6812_OP_D_IDX)
1961 if (op->reg1 != REG_D)
1962 as_bad (_("Expecting register D for indexed indirect mode."));
1964 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
1981 as_bad (_("Invalid accumulator register."));
2006 as_bad (_("Invalid indexed register."));
2010 number_to_chars_bigendian (f, byte, 1);
2014 as_fatal (_("Addressing mode not implemented yet."));
2018 /* Assemble the 68HC12 register mode byte. */
2020 build_reg_mode (op, format)
2027 if (format & M6812_OP_SEX_MARKER
2028 && op->reg1 != REG_A && op->reg1 != REG_B && op->reg1 != REG_CCR)
2029 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
2030 else if (op->reg1 == REG_NONE || op->reg1 == REG_PC)
2031 as_bad (_("Invalid source register."));
2033 if (format & M6812_OP_SEX_MARKER
2034 && op->reg2 != REG_D
2035 && op->reg2 != REG_X && op->reg2 != REG_Y && op->reg2 != REG_SP)
2036 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
2037 else if (op->reg2 == REG_NONE || op->reg2 == REG_PC)
2038 as_bad (_("Invalid destination register."));
2040 byte = (op->reg1 << 4) | (op->reg2);
2041 if (format & M6812_OP_EXG_MARKER)
2045 number_to_chars_bigendian (f, byte, 1);
2049 /* build_insn takes a pointer to the opcode entry in the opcode table,
2050 the array of operand expressions and builds the correspding instruction.
2051 This operation only deals with non relative jumps insn (need special
2054 build_insn (opcode, operands, nb_operands)
2055 struct m68hc11_opcode *opcode;
2057 int nb_operands ATTRIBUTE_UNUSED;
2066 /* Put the page code instruction if there is one. */
2067 format = opcode->format;
2070 where = frag_now_fix ();
2072 if (format & M6811_OP_BRANCH)
2073 fix_new (frag, where, 1,
2074 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP);
2076 if (format & OP_EXTENDED)
2080 f = m68hc11_new_insn (2);
2081 if (format & M6811_OP_PAGE2)
2082 page_code = M6811_OPCODE_PAGE2;
2083 else if (format & M6811_OP_PAGE3)
2084 page_code = M6811_OPCODE_PAGE3;
2086 page_code = M6811_OPCODE_PAGE4;
2088 number_to_chars_bigendian (f, page_code, 1);
2092 f = m68hc11_new_insn (1);
2094 number_to_chars_bigendian (f, opcode->opcode, 1);
2098 /* The 68HC12 movb and movw instructions are special. We have to handle
2099 them in a special way. */
2100 if (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
2103 if (format & M6812_OP_IDX)
2105 build_indexed_byte (&operands[0], format, 1);
2107 format &= ~M6812_OP_IDX;
2109 if (format & M6812_OP_IDX_P2)
2111 build_indexed_byte (&operands[1], format, 1);
2113 format &= ~M6812_OP_IDX_P2;
2117 if (format & (M6811_OP_DIRECT | M6811_OP_IMM8))
2119 fixup8 (&operands[i].exp,
2120 format & (M6811_OP_DIRECT | M6811_OP_IMM8 | M6812_OP_TRAP_ID),
2124 else if (IS_CALL_SYMBOL (format) && nb_operands == 1)
2126 format &= ~M6812_OP_PAGE;
2127 fixup24 (&operands[i].exp, format & M6811_OP_IND16,
2131 else if (format & (M6811_OP_IMM16 | M6811_OP_IND16))
2133 fixup16 (&operands[i].exp,
2134 format & (M6811_OP_IMM16 | M6811_OP_IND16 | M6812_OP_PAGE),
2138 else if (format & (M6811_OP_IX | M6811_OP_IY))
2140 if ((format & M6811_OP_IX) && (operands[0].reg1 != REG_X))
2141 as_bad (_("Invalid indexed register, expecting register X."));
2142 if ((format & M6811_OP_IY) && (operands[0].reg1 != REG_Y))
2143 as_bad (_("Invalid indexed register, expecting register Y."));
2145 fixup8 (&operands[0].exp, M6811_OP_IX, operands[0].mode);
2149 (M6812_OP_IDX | M6812_OP_IDX_2 | M6812_OP_IDX_1
2150 | M6812_OP_D_IDX | M6812_OP_D_IDX_2))
2152 build_indexed_byte (&operands[i], format, move_insn);
2155 else if (format & M6812_OP_REG && current_architecture & cpu6812)
2157 build_reg_mode (&operands[i], format);
2160 if (format & M6811_OP_BITMASK)
2162 fixup8 (&operands[i].exp, M6811_OP_BITMASK, operands[i].mode);
2165 if (format & M6811_OP_JUMP_REL)
2167 fixup8 (&operands[i].exp, M6811_OP_JUMP_REL, operands[i].mode);
2169 else if (format & M6812_OP_IND16_P2)
2171 fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode);
2173 if (format & M6812_OP_PAGE)
2175 fixup8 (&operands[i].exp, M6812_OP_PAGE, operands[i].mode);
2179 /* Opcode identification and operand analysis. */
2181 /* find() gets a pointer to an entry in the opcode table. It must look at all
2182 opcodes with the same name and use the operands to choose the correct
2183 opcode. Returns the opcode pointer if there was a match and 0 if none. */
2184 static struct m68hc11_opcode *
2185 find (opc, operands, nb_operands)
2186 struct m68hc11_opcode_def *opc;
2191 struct m68hc11_opcode *opcode;
2192 struct m68hc11_opcode *op_indirect;
2195 opcode = opc->opcode;
2197 /* Now search the opcode table table for one with operands
2198 that matches what we've got. We're only done if the operands matched so
2199 far AND there are no more to check. */
2200 for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++)
2202 int poss_indirect = 0;
2203 long format = opcode->format;
2207 if (opcode->format & M6811_OP_MASK)
2209 if (opcode->format & M6811_OP_BITMASK)
2211 if (opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2213 if (opcode->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
2215 if ((opcode->format & M6812_OP_PAGE)
2216 && (!IS_CALL_SYMBOL (opcode->format) || nb_operands == 2))
2219 for (i = 0; expect == nb_operands && i < nb_operands; i++)
2221 int mode = operands[i].mode;
2223 if (mode & M6811_OP_IMM16)
2226 (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK))
2230 if (mode == M6811_OP_DIRECT)
2232 if (format & M6811_OP_DIRECT)
2235 /* If the operand is a page 0 operand, remember a
2236 possible <abs-16> addressing mode. We mark
2237 this and continue to check other operands. */
2238 if (format & M6811_OP_IND16
2239 && flag_strict_direct_addressing && op_indirect == 0)
2246 if (mode & M6811_OP_IND16)
2248 if (i == 0 && (format & M6811_OP_IND16) != 0)
2250 if (i != 0 && (format & M6812_OP_PAGE) != 0)
2252 if (i != 0 && (format & M6812_OP_IND16_P2) != 0)
2254 if (i == 0 && (format & M6811_OP_BITMASK))
2257 if (mode & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2259 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2262 if (mode & M6812_OP_REG)
2265 && (format & M6812_OP_REG)
2266 && (operands[i].reg2 == REG_NONE))
2269 && (format & M6812_OP_REG)
2270 && (format & M6812_OP_REG_2)
2271 && (operands[i].reg2 != REG_NONE))
2274 && (format & M6812_OP_IDX)
2275 && (operands[i].reg2 != REG_NONE))
2278 && (format & M6812_OP_IDX)
2279 && (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)))
2282 && (format & M6812_OP_IDX_P2))
2286 if (mode & M6812_OP_IDX)
2288 if (format & M6811_OP_IX && operands[i].reg1 == REG_X)
2290 if (format & M6811_OP_IY && operands[i].reg1 == REG_Y)
2293 && format & (M6812_OP_IDX | M6812_OP_IDX_1 | M6812_OP_IDX_2)
2294 && (operands[i].reg1 == REG_X
2295 || operands[i].reg1 == REG_Y
2296 || operands[i].reg1 == REG_SP
2297 || operands[i].reg1 == REG_PC))
2299 if (i == 1 && format & M6812_OP_IDX_P2)
2302 if (mode & format & (M6812_OP_D_IDX | M6812_OP_D_IDX_2))
2307 if (mode & M6812_AUTO_INC_DEC)
2310 && format & (M6812_OP_IDX | M6812_OP_IDX_1 |
2313 if (i == 1 && format & M6812_OP_IDX_P2)
2318 match = i == nb_operands;
2320 /* Operands are ok but an operand uses page 0 addressing mode
2321 while the insn supports abs-16 mode. Keep a reference to this
2322 insns in case there is no insn supporting page 0 addressing. */
2323 if (match && poss_indirect)
2325 op_indirect = opcode;
2332 /* Page 0 addressing is used but not supported by any insn.
2333 If absolute addresses are supported, we use that insn. */
2334 if (match == 0 && op_indirect)
2336 opcode = op_indirect;
2348 /* Find the real opcode and its associated operands. We use a progressive
2349 approach here. On entry, 'opc' points to the first opcode in the
2350 table that matches the opcode name in the source line. We try to
2351 isolate an operand, find a possible match in the opcode table.
2352 We isolate another operand if no match were found. The table 'operands'
2353 is filled while operands are recognized.
2355 Returns the opcode pointer that matches the opcode name in the
2356 source line and the associated operands. */
2357 static struct m68hc11_opcode *
2358 find_opcode (opc, operands, nb_operands)
2359 struct m68hc11_opcode_def *opc;
2363 struct m68hc11_opcode *opcode;
2366 if (opc->max_operands == 0)
2372 for (i = 0; i < opc->max_operands;)
2376 result = get_operand (&operands[i], i, opc->format);
2380 /* Special case where the bitmask of the bclr/brclr
2381 instructions is not introduced by #.
2382 Example: bclr 3,x $80. */
2383 if (i == 1 && (opc->format & M6811_OP_BITMASK)
2384 && (operands[i].mode & M6811_OP_IND16))
2386 operands[i].mode = M6811_OP_IMM16;
2391 if (i >= opc->min_operands)
2393 opcode = find (opc, operands, i);
2394 if (opcode && !(opcode->format & M6812_OP_PAGE))
2397 if (opcode && *input_line_pointer != ',')
2401 if (*input_line_pointer == ',')
2402 input_line_pointer++;
2408 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2409 | M6812_OP_DBCC_MARKER \
2410 | M6812_OP_IBCC_MARKER)
2412 /* Gas line assembler entry point. */
2414 /* This is the main entry point for the machine-dependent assembler. str
2415 points to a machine-dependent instruction. This function is supposed to
2416 emit the frags/bytes it assembles to. */
2421 struct m68hc11_opcode_def *opc;
2422 struct m68hc11_opcode *opcode;
2424 unsigned char *op_start, *save;
2425 unsigned char *op_end;
2428 operand operands[M6811_MAX_OPERANDS];
2430 int branch_optimize = 0;
2433 /* Drop leading whitespace. */
2437 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2438 lower case (the opcode table only has lower case op-codes). */
2439 for (op_start = op_end = (unsigned char *) (str);
2440 *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' ';
2443 name[nlen] = TOLOWER (op_start[nlen]);
2450 as_bad (_("No instruction or missing opcode."));
2454 /* Find the opcode definition given its name. */
2455 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name);
2457 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
2458 pseudo insns for relative branch. For these branchs, we always
2459 optimize them (turned into absolute branchs) even if --short-branchs
2461 if (opc == NULL && name[0] == 'j' && name[1] == 'b')
2463 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, &name[1]);
2465 && (!(opc->format & M6811_OP_JUMP_REL)
2466 || (opc->format & M6811_OP_BITMASK)))
2469 branch_optimize = 1;
2472 /* The following test should probably be removed. This is not conform
2473 to Motorola assembler specs. */
2474 if (opc == NULL && flag_mri)
2476 if (*op_end == ' ' || *op_end == '\t')
2478 while (*op_end == ' ' || *op_end == '\t')
2483 (is_end_of_line[op_end[1]]
2484 || op_end[1] == ' ' || op_end[1] == '\t'
2485 || !ISALNUM (op_end[1])))
2486 && (*op_end == 'a' || *op_end == 'b'
2487 || *op_end == 'A' || *op_end == 'B'
2488 || *op_end == 'd' || *op_end == 'D'
2489 || *op_end == 'x' || *op_end == 'X'
2490 || *op_end == 'y' || *op_end == 'Y'))
2492 name[nlen++] = TOLOWER (*op_end++);
2494 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash,
2500 /* Identify a possible instruction alias. There are some on the
2501 68HC12 to emulate a few 68HC11 instructions. */
2502 if (opc == NULL && (current_architecture & cpu6812))
2506 for (i = 0; i < m68hc12_num_alias; i++)
2507 if (strcmp (m68hc12_alias[i].name, name) == 0)
2513 if (opc == NULL && alias_id < 0)
2515 as_bad (_("Opcode `%s' is not recognized."), name);
2518 save = input_line_pointer;
2519 input_line_pointer = op_end;
2524 opcode = find_opcode (opc, operands, &nb_operands);
2529 if ((opcode || alias_id >= 0) && !flag_mri)
2531 char *p = input_line_pointer;
2533 while (*p == ' ' || *p == '\t' || *p == '\n' || *p == '\r')
2536 if (*p != '\n' && *p)
2537 as_bad (_("Garbage at end of instruction: `%s'."), p);
2540 input_line_pointer = save;
2544 char *f = m68hc11_new_insn (m68hc12_alias[alias_id].size);
2546 number_to_chars_bigendian (f, m68hc12_alias[alias_id].code1, 1);
2547 if (m68hc12_alias[alias_id].size > 1)
2548 number_to_chars_bigendian (f + 1, m68hc12_alias[alias_id].code2, 1);
2553 /* Opcode is known but does not have valid operands. Print out the
2554 syntax for this opcode. */
2557 if (flag_print_insn_syntax)
2558 print_insn_format (name);
2560 as_bad (_("Invalid operand for `%s'"), name);
2564 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
2565 relative and must be in the range -256..255 (9-bits). */
2566 if ((opcode->format & M6812_XBCC_MARKER)
2567 && (opcode->format & M6811_OP_JUMP_REL))
2568 build_dbranch_insn (opcode, operands, nb_operands, branch_optimize);
2570 /* Relative jumps instructions are taken care of separately. We have to make
2571 sure that the relative branch is within the range -128..127. If it's out
2572 of range, the instructions are changed into absolute instructions.
2573 This is not supported for the brset and brclr instructions. */
2574 else if ((opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2575 && !(opcode->format & M6811_OP_BITMASK))
2576 build_jump_insn (opcode, operands, nb_operands, branch_optimize);
2578 build_insn (opcode, operands, nb_operands);
2582 /* Pseudo op to control the ELF flags. */
2585 int x ATTRIBUTE_UNUSED;
2587 char *name = input_line_pointer, ch;
2589 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2590 input_line_pointer++;
2591 ch = *input_line_pointer;
2592 *input_line_pointer = '\0';
2594 if (strcmp (name, "mshort") == 0)
2596 elf_flags &= ~E_M68HC11_I32;
2598 else if (strcmp (name, "mlong") == 0)
2600 elf_flags |= E_M68HC11_I32;
2602 else if (strcmp (name, "mshort-double") == 0)
2604 elf_flags &= ~E_M68HC11_F64;
2606 else if (strcmp (name, "mlong-double") == 0)
2608 elf_flags |= E_M68HC11_F64;
2612 as_warn (_("Invalid mode: %s\n"), name);
2614 *input_line_pointer = ch;
2615 demand_empty_rest_of_line ();
2618 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
2619 are using 'rtc' for returning. It is necessary to use 'call'
2620 to invoke them. This is also used by the debugger to correctly
2621 find the stack frame. */
2623 s_m68hc11_mark_symbol (mark)
2630 elf_symbol_type *elfsym;
2634 name = input_line_pointer;
2635 c = get_symbol_end ();
2636 symbolP = symbol_find_or_make (name);
2637 *input_line_pointer = c;
2641 bfdsym = symbol_get_bfdsym (symbolP);
2642 elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym);
2646 /* Mark the symbol far (using rtc for function return). */
2647 elfsym->internal_elf_sym.st_other |= mark;
2651 input_line_pointer ++;
2655 if (*input_line_pointer == '\n')
2661 demand_empty_rest_of_line ();
2665 s_m68hc11_relax (ignore)
2666 int ignore ATTRIBUTE_UNUSED;
2672 if (ex.X_op != O_symbol || ex.X_add_number != 0)
2674 as_bad (_("bad .relax format"));
2675 ignore_rest_of_line ();
2679 fix_new_exp (frag_now, frag_now_fix (), 1, &ex, 1,
2680 BFD_RELOC_M68HC11_RL_GROUP);
2682 demand_empty_rest_of_line ();
2686 /* Relocation, relaxation and frag conversions. */
2688 /* PC-relative offsets are relative to the start of the
2689 next instruction. That is, the address of the offset, plus its
2690 size, since the offset is always the last part of the insn. */
2692 md_pcrel_from (fixP)
2695 if (fixP->fx_r_type == BFD_RELOC_M68HC11_RL_JUMP)
2698 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
2701 /* If while processing a fixup, a reloc really needs to be created
2702 then it is done here. */
2704 tc_gen_reloc (section, fixp)
2710 reloc = (arelent *) xmalloc (sizeof (arelent));
2711 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2712 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
2713 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2714 if (fixp->fx_r_type == 0)
2715 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
2717 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
2718 if (reloc->howto == (reloc_howto_type *) NULL)
2720 as_bad_where (fixp->fx_file, fixp->fx_line,
2721 _("Relocation %d is not supported by object file format."),
2722 (int) fixp->fx_r_type);
2726 /* Since we use Rel instead of Rela, encode the vtable entry to be
2727 used in the relocation's section offset. */
2728 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2729 reloc->address = fixp->fx_offset;
2736 md_convert_frag (abfd, sec, fragP)
2737 bfd *abfd ATTRIBUTE_UNUSED;
2738 asection *sec ATTRIBUTE_UNUSED;
2744 char *buffer_address = fragP->fr_literal;
2746 /* Address in object code of the displacement. */
2747 register int object_address = fragP->fr_fix + fragP->fr_address;
2749 buffer_address += fragP->fr_fix;
2751 /* The displacement of the address, from current location. */
2752 value = S_GET_VALUE (fragP->fr_symbol);
2753 disp = (value + fragP->fr_offset) - object_address;
2755 switch (fragP->fr_subtype)
2757 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE):
2758 fragP->fr_opcode[1] = disp;
2761 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD):
2762 /* This relax is only for bsr and bra. */
2763 assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
2764 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
2765 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
2767 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]);
2769 fix_new (fragP, fragP->fr_fix - 1, 2,
2770 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2774 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE):
2775 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_BYTE):
2776 fragP->fr_opcode[1] = disp;
2779 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD):
2780 /* Invert branch. */
2781 fragP->fr_opcode[0] ^= 1;
2782 fragP->fr_opcode[1] = 3; /* Branch offset. */
2783 buffer_address[0] = M6811_JMP;
2784 fix_new (fragP, fragP->fr_fix + 1, 2,
2785 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2789 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD):
2790 /* Translate branch into a long branch. */
2791 fragP->fr_opcode[1] = fragP->fr_opcode[0];
2792 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2;
2794 fixp = fix_new (fragP, fragP->fr_fix, 2,
2795 fragP->fr_symbol, fragP->fr_offset, 1,
2796 BFD_RELOC_16_PCREL);
2797 fixp->fx_pcrel_adjust = 2;
2801 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5):
2802 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 6;
2803 if ((fragP->fr_opcode[0] & 0x0ff) == 0x0c0)
2804 fragP->fr_opcode[0] |= disp & 0x1f;
2806 fragP->fr_opcode[0] |= value & 0x1f;
2809 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9):
2810 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3);
2811 fragP->fr_opcode[0] |= 0xE0;
2812 fix_new (fragP, fragP->fr_fix, 1,
2813 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_8);
2817 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16):
2818 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3);
2819 fragP->fr_opcode[0] |= 0xe2;
2820 if ((fragP->fr_opcode[0] & 0x0ff) == 0x0fa)
2822 fixp = fix_new (fragP, fragP->fr_fix, 2,
2823 fragP->fr_symbol, fragP->fr_offset,
2824 1, BFD_RELOC_16_PCREL);
2825 fixp->fx_pcrel_adjust = 2;
2829 fix_new (fragP, fragP->fr_fix, 2,
2830 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2835 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE):
2837 fragP->fr_opcode[0] |= 0x10;
2839 fragP->fr_opcode[1] = disp & 0x0FF;
2842 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD):
2843 /* Invert branch. */
2844 fragP->fr_opcode[0] ^= 0x20;
2845 fragP->fr_opcode[1] = 3; /* Branch offset. */
2846 buffer_address[0] = M6812_JMP;
2847 fix_new (fragP, fragP->fr_fix + 1, 2,
2848 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2857 /* On an ELF system, we can't relax a weak symbol. The weak symbol
2858 can be overridden at final link time by a non weak symbol. We can
2859 relax externally visible symbol because there is no shared library
2860 and such symbol can't be overridden (unless they are weak). */
2862 relaxable_symbol (symbol)
2865 return ! S_IS_WEAK (symbol);
2868 /* Force truly undefined symbols to their maximum size, and generally set up
2869 the frag list to be relaxed. */
2871 md_estimate_size_before_relax (fragP, segment)
2875 if (RELAX_LENGTH (fragP->fr_subtype) == STATE_UNDF)
2877 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
2878 || !relaxable_symbol (fragP->fr_symbol))
2880 /* Non-relaxable cases. */
2882 char *buffer_address;
2884 old_fr_fix = fragP->fr_fix;
2885 buffer_address = fragP->fr_fix + fragP->fr_literal;
2887 switch (RELAX_STATE (fragP->fr_subtype))
2889 case STATE_PC_RELATIVE:
2891 /* This relax is only for bsr and bra. */
2892 assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
2893 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
2894 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
2896 if (flag_fixed_branchs)
2897 as_bad_where (fragP->fr_file, fragP->fr_line,
2898 _("bra or bsr with undefined symbol."));
2900 /* The symbol is undefined or in a separate section.
2901 Turn bra into a jmp and bsr into a jsr. The insn
2902 becomes 3 bytes long (instead of 2). A fixup is
2903 necessary for the unresolved symbol address. */
2904 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]);
2906 fix_new (fragP, fragP->fr_fix - 1, 2, fragP->fr_symbol,
2907 fragP->fr_offset, 0, BFD_RELOC_16);
2911 case STATE_CONDITIONAL_BRANCH:
2912 assert (current_architecture & cpu6811);
2914 fragP->fr_opcode[0] ^= 1; /* Reverse sense of branch. */
2915 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */
2917 /* Don't use fr_opcode[2] because this may be
2918 in a different frag. */
2919 buffer_address[0] = M6811_JMP;
2922 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2923 fragP->fr_offset, 0, BFD_RELOC_16);
2927 case STATE_INDEXED_OFFSET:
2928 assert (current_architecture & cpu6812);
2930 /* Switch the indexed operation to 16-bit mode. */
2931 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 3;
2932 fragP->fr_opcode[0] |= 0xe2;
2934 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2935 fragP->fr_offset, 0, BFD_RELOC_16);
2939 case STATE_XBCC_BRANCH:
2940 assert (current_architecture & cpu6812);
2942 fragP->fr_opcode[0] ^= 0x20; /* Reverse sense of branch. */
2943 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */
2945 /* Don't use fr_opcode[2] because this may be
2946 in a different frag. */
2947 buffer_address[0] = M6812_JMP;
2950 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2951 fragP->fr_offset, 0, BFD_RELOC_16);
2955 case STATE_CONDITIONAL_BRANCH_6812:
2956 assert (current_architecture & cpu6812);
2958 /* Translate into a lbcc branch. */
2959 fragP->fr_opcode[1] = fragP->fr_opcode[0];
2960 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2;
2962 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2963 fragP->fr_offset, 1, BFD_RELOC_16_PCREL);
2968 as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype);
2972 /* Return the growth in the fixed part of the frag. */
2973 return fragP->fr_fix - old_fr_fix;
2976 /* Relaxable cases. */
2977 switch (RELAX_STATE (fragP->fr_subtype))
2979 case STATE_PC_RELATIVE:
2980 /* This relax is only for bsr and bra. */
2981 assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
2982 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
2983 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
2985 fragP->fr_subtype = ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE);
2988 case STATE_CONDITIONAL_BRANCH:
2989 assert (current_architecture & cpu6811);
2991 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH,
2995 case STATE_INDEXED_OFFSET:
2996 assert (current_architecture & cpu6812);
2998 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET,
3002 case STATE_XBCC_BRANCH:
3003 assert (current_architecture & cpu6812);
3005 fragP->fr_subtype = ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE);
3008 case STATE_CONDITIONAL_BRANCH_6812:
3009 assert (current_architecture & cpu6812);
3011 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812,
3017 if (fragP->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
3018 as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype);
3020 /* Return the size of the variable part of the frag. */
3021 return md_relax_table[fragP->fr_subtype].rlx_length;
3024 /* See whether we need to force a relocation into the output file. */
3026 tc_m68hc11_force_relocation (fixP)
3029 switch (fixP->fx_r_type)
3031 case BFD_RELOC_VTABLE_INHERIT:
3032 case BFD_RELOC_VTABLE_ENTRY:
3033 case BFD_RELOC_M68HC11_RL_GROUP:
3040 return S_FORCE_RELOC (fixP->fx_addsy);
3043 /* Here we decide which fixups can be adjusted to make them relative
3044 to the beginning of the section instead of the symbol. Basically
3045 we need to make sure that the linker relaxation is done
3046 correctly, so in some cases we force the original symbol to be
3049 tc_m68hc11_fix_adjustable (fixP)
3052 switch (fixP->fx_r_type)
3054 /* For the linker relaxation to work correctly, these relocs
3055 need to be on the symbol itself. */
3057 case BFD_RELOC_LO16:
3058 case BFD_RELOC_M68HC11_RL_JUMP:
3059 case BFD_RELOC_M68HC11_RL_GROUP:
3060 case BFD_RELOC_VTABLE_INHERIT:
3061 case BFD_RELOC_VTABLE_ENTRY:
3071 md_apply_fix3 (fixP, valP, seg)
3074 segT seg ATTRIBUTE_UNUSED;
3077 long value = * valP;
3080 if (fixP->fx_addsy == (symbolS *) NULL)
3083 /* We don't actually support subtracting a symbol. */
3084 if (fixP->fx_subsy != (symbolS *) NULL)
3085 as_bad_where (fixP->fx_file, fixP->fx_line, _("Expression too complex."));
3087 op_type = fixP->fx_r_type;
3089 /* Patch the instruction with the resolved operand. Elf relocation
3090 info will also be generated to take care of linker/loader fixups.
3091 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
3092 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
3093 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
3094 because it's either resolved or turned out into non-relative insns (see
3095 relax table, bcc, bra, bsr transformations)
3097 The BFD_RELOC_32 is necessary for the support of --gstabs. */
3098 where = fixP->fx_frag->fr_literal + fixP->fx_where;
3100 switch (fixP->fx_r_type)
3103 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
3107 case BFD_RELOC_M68HC11_24:
3108 bfd_putb16 ((bfd_vma) (value & 0x0ffff), (unsigned char *) where);
3109 ((bfd_byte*) where)[2] = ((value >> 16) & 0x0ff);
3113 case BFD_RELOC_16_PCREL:
3114 case BFD_RELOC_M68HC11_LO16:
3115 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
3116 if (value < -65537 || value > 65535)
3117 as_bad_where (fixP->fx_file, fixP->fx_line,
3118 _("Value out of 16-bit range."));
3121 case BFD_RELOC_M68HC11_HI8:
3125 case BFD_RELOC_M68HC11_LO8:
3127 case BFD_RELOC_M68HC11_PAGE:
3129 bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
3131 ((bfd_byte *) where)[0] = (bfd_byte) value;
3134 case BFD_RELOC_8_PCREL:
3136 bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
3138 ((bfd_byte *) where)[0] = (bfd_byte) value;
3140 if (value < -128 || value > 127)
3141 as_bad_where (fixP->fx_file, fixP->fx_line,
3142 _("Value %ld too large for 8-bit PC-relative branch."),
3146 case BFD_RELOC_M68HC11_3B:
3147 if (value <= 0 || value > 8)
3148 as_bad_where (fixP->fx_file, fixP->fx_line,
3149 _("Auto increment/decrement offset '%ld' is out of range."),
3156 where[0] = where[0] | (value & 0x07);
3159 case BFD_RELOC_M68HC11_RL_JUMP:
3160 case BFD_RELOC_M68HC11_RL_GROUP:
3161 case BFD_RELOC_VTABLE_INHERIT:
3162 case BFD_RELOC_VTABLE_ENTRY:
3167 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
3168 fixP->fx_line, fixP->fx_r_type);
3172 /* Set the ELF specific flags. */
3174 m68hc11_elf_final_processing ()
3176 elf_elfheader (stdoutput)->e_flags &= ~EF_M68HC11_ABI;
3177 elf_elfheader (stdoutput)->e_flags |= elf_flags;