1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright (C) 1999, 2000 Free Software Foundation.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/m68hc11.h"
27 #include "dwarf2dbg.h"
29 const char comment_chars[] = ";!";
30 const char line_comment_chars[] = "#*";
31 const char line_separator_chars[] = "";
33 const char EXP_CHARS[] = "eE";
34 const char FLT_CHARS[] = "dD";
36 #define STATE_CONDITIONAL_BRANCH (1)
37 #define STATE_PC_RELATIVE (2)
38 #define STATE_INDEXED_OFFSET (3)
39 #define STATE_XBCC_BRANCH (4)
40 #define STATE_CONDITIONAL_BRANCH_6812 (5)
42 #define STATE_BYTE (0)
43 #define STATE_BITS5 (0)
44 #define STATE_WORD (1)
45 #define STATE_BITS9 (1)
46 #define STATE_LONG (2)
47 #define STATE_BITS16 (2)
48 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
50 /* This macro has no side-effects. */
51 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
53 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
55 /* This table describes how you change sizes for the various types of variable
56 size expressions. This version only supports two kinds. */
59 How far Forward this mode will reach.
60 How far Backward this mode will reach.
61 How many bytes this mode will add to the size of the frag.
62 Which mode to go to if the offset won't fit in this one. */
64 relax_typeS md_relax_table[] =
66 {1, 1, 0, 0}, /* First entries aren't used. */
67 {1, 1, 0, 0}, /* For no good reason except. */
68 {1, 1, 0, 0}, /* that the VAX doesn't either. */
72 These insns are translated into b!cc +3 jmp L. */
73 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD)},
78 /* Relax for bsr <L> and bra <L>.
79 These insns are translated into jsr and jmp. */
80 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD)},
85 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
86 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9)},
87 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16)},
91 /* Relax for dbeq/ibeq/tbeq r,<L>:
92 These insns are translated into db!cc +3 jmp L. */
93 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD)},
98 /* Relax for bcc <L> on 68HC12.
99 These insns are translated into lbcc <L>. */
100 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD)},
107 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
108 typedef enum register_id
121 typedef struct operand
129 struct m68hc11_opcode_def
136 struct m68hc11_opcode *opcode;
139 static struct m68hc11_opcode_def *m68hc11_opcode_defs = 0;
140 static int m68hc11_nb_opcode_defs = 0;
149 static alias alias_opcodes[] =
157 /* Local functions. */
158 static register_id reg_name_search PARAMS ((char *));
159 static register_id register_name PARAMS ((void));
160 static int check_range PARAMS ((long, int));
161 static void print_opcode_list PARAMS ((void));
162 static void get_default_target PARAMS ((void));
163 static void print_insn_format PARAMS ((char *));
164 static int get_operand PARAMS ((operand *, int, long));
165 static void fixup8 PARAMS ((expressionS *, int, int));
166 static void fixup16 PARAMS ((expressionS *, int, int));
167 static struct m68hc11_opcode *find_opcode
168 PARAMS ((struct m68hc11_opcode_def *, operand *, int *));
169 static void build_jump_insn
170 PARAMS ((struct m68hc11_opcode *, operand *, int, int));
171 static void build_insn
172 PARAMS ((struct m68hc11_opcode *, operand *, int));
174 /* Controls whether relative branches can be turned into long branches.
175 When the relative offset is too large, the insn are changed:
183 Setting the flag forbidds this. */
184 static short flag_fixed_branchs = 0;
186 /* Force to use long jumps (absolute) instead of relative branches. */
187 static short flag_force_long_jumps = 0;
189 /* Change the direct addressing mode into an absolute addressing mode
190 when the insn does not support direct addressing.
191 For example, "clr *ZD0" is normally not possible and is changed
193 static short flag_strict_direct_addressing = 1;
195 /* When an opcode has invalid operand, print out the syntax of the opcode
197 static short flag_print_insn_syntax = 0;
199 /* Dumps the list of instructions with syntax and then exit:
200 1 -> Only dumps the list (sorted by name)
201 2 -> Generate an example (or test) that can be compiled. */
202 static short flag_print_opcodes = 0;
204 /* Opcode hash table. */
205 static struct hash_control *m68hc11_hash;
207 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
208 by 'get_default_target' by looking at default BFD vector. This is overriden
209 with the -m<cpu> option. */
210 static int current_architecture = 0;
212 /* Default cpu determined by 'get_default_target'. */
213 static const char *default_cpu;
215 /* Number of opcodes in the sorted table (filtered by current cpu). */
216 static int num_opcodes;
218 /* The opcodes sorted by name and filtered by current cpu. */
219 static struct m68hc11_opcode *m68hc11_sorted_opcodes;
221 /* These are the machine dependent pseudo-ops. These are included so
222 the assembler can work on the output from the SUN C compiler, which
225 /* This table describes all the machine specific pseudo-ops the assembler
226 has to support. The fields are:
227 pseudo-op name without dot
228 function to call to execute this pseudo-op
229 Integer arg to pass to the function. */
230 const pseudo_typeS md_pseudo_table[] =
232 /* The following pseudo-ops are supported for MRI compatibility. */
235 {"fcc", stringer, 1},
237 {"file", dwarf2_directive_file, 0},
238 {"loc", dwarf2_directive_loc, 0},
243 /* Options and initialization. */
245 CONST char *md_shortopts = "Sm:";
247 struct option md_longopts[] =
249 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
250 {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH},
252 #define OPTION_SHORT_BRANCHS (OPTION_MD_BASE + 1)
253 {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHS},
255 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
256 {"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE},
258 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
259 {"print-insn-syntax", no_argument, NULL, OPTION_PRINT_INSN_SYNTAX},
261 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
262 {"print-opcodes", no_argument, NULL, OPTION_PRINT_OPCODES},
264 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
265 {"generate-example", no_argument, NULL, OPTION_GENERATE_EXAMPLE},
267 {NULL, no_argument, NULL, 0}
269 size_t md_longopts_size = sizeof (md_longopts);
271 /* Get the target cpu for the assembler. This is based on the configure
272 options and on the -m68hc11/-m68hc12 option. If no option is specified,
273 we must get the default. */
275 m68hc11_arch_format ()
277 get_default_target ();
278 if (current_architecture & cpu6811)
279 return "elf32-m68hc11";
281 return "elf32-m68hc12";
284 enum bfd_architecture
287 get_default_target ();
288 if (current_architecture & cpu6811)
289 return bfd_arch_m68hc11;
291 return bfd_arch_m68hc12;
301 md_show_usage (stream)
304 get_default_target ();
305 fprintf (stream, _("\
306 Motorola 68HC11/68HC12 options:\n\
307 -m68hc11 | -m68hc12 specify the processor [default %s]\n\
308 --force-long-branchs always turn relative branchs into absolute ones\n\
309 -S,--short-branchs do not turn relative branchs into absolute ones\n\
310 when the offset is out of range\n\
311 --strict-direct-mode do not turn the direct mode into extended mode\n\
312 when the instruction does not support direct mode\n\
313 --print-insn-syntax print the syntax of instruction in case of error\n\
314 --print-opcodes print the list of instructions with syntax\n\
315 --generate-example generate an example of each instruction\n\
316 (used for testing)\n"), default_cpu);
320 /* Try to identify the default target based on the BFD library. */
322 get_default_target ()
324 const bfd_target *target;
327 if (current_architecture != 0)
330 default_cpu = "unknown";
331 target = bfd_find_target (0, &abfd);
332 if (target && target->name)
334 if (strcmp (target->name, "elf32-m68hc12") == 0)
336 current_architecture = cpu6812;
337 default_cpu = "m68hc12";
339 else if (strcmp (target->name, "elf32-m68hc11") == 0)
341 current_architecture = cpu6811;
342 default_cpu = "m68hc11";
346 as_bad (_("Default target `%s' is not supported."), target->name);
352 m68hc11_print_statistics (file)
356 struct m68hc11_opcode_def *opc;
358 hash_print_statistics (file, "opcode table", m68hc11_hash);
360 opc = m68hc11_opcode_defs;
361 if (opc == 0 || m68hc11_nb_opcode_defs == 0)
364 /* Dump the opcode statistics table. */
365 fprintf (file, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
366 for (i = 0; i < m68hc11_nb_opcode_defs; i++, opc++)
368 fprintf (file, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
371 opc->min_operands, opc->max_operands, opc->format, opc->used);
376 md_parse_option (c, arg)
380 get_default_target ();
383 /* -S means keep external to 2 bits offset rather than 16 bits one. */
384 case OPTION_SHORT_BRANCHS:
386 flag_fixed_branchs = 1;
389 case OPTION_FORCE_LONG_BRANCH:
390 flag_force_long_jumps = 1;
393 case OPTION_PRINT_INSN_SYNTAX:
394 flag_print_insn_syntax = 1;
397 case OPTION_PRINT_OPCODES:
398 flag_print_opcodes = 1;
401 case OPTION_STRICT_DIRECT_MODE:
402 flag_strict_direct_addressing = 0;
405 case OPTION_GENERATE_EXAMPLE:
406 flag_print_opcodes = 2;
410 if (strcasecmp (arg, "68hc11") == 0)
411 current_architecture = cpu6811;
412 else if (strcasecmp (arg, "68hc12") == 0)
413 current_architecture = cpu6812;
415 as_bad (_("Option `%s' is not recognized."), arg);
426 md_undefined_symbol (name)
427 char *name ATTRIBUTE_UNUSED;
432 /* Equal to MAX_PRECISION in atof-ieee.c. */
433 #define MAX_LITTLENUMS 6
435 /* Turn a string in input_line_pointer into a floating point constant
436 of type TYPE, and store the appropriate bytes in *LITP. The number
437 of LITTLENUMS emitted is stored in *SIZEP. An error message is
438 returned, or NULL on OK. */
440 md_atof (type, litP, sizeP)
446 LITTLENUM_TYPE words[MAX_LITTLENUMS];
447 LITTLENUM_TYPE *wordP;
478 return _("Bad call to MD_ATOF()");
480 t = atof_ieee (input_line_pointer, type, words);
482 input_line_pointer = t;
484 *sizeP = prec * sizeof (LITTLENUM_TYPE);
485 for (wordP = words; prec--;)
487 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
488 litP += sizeof (LITTLENUM_TYPE);
494 md_section_align (seg, addr)
498 int align = bfd_get_section_alignment (stdoutput, seg);
499 return ((addr + (1 << align) - 1) & (-1 << align));
503 cmp_opcode (op1, op2)
504 struct m68hc11_opcode *op1;
505 struct m68hc11_opcode *op2;
507 return strcmp (op1->name, op2->name);
510 /* Initialize the assembler. Create the opcode hash table
511 (sorted on the names) with the M6811 opcode table
512 (from opcode library). */
516 char *prev_name = "";
517 struct m68hc11_opcode *opcodes;
518 struct m68hc11_opcode_def *opc = 0;
521 get_default_target ();
523 m68hc11_hash = hash_new ();
525 /* Get a writable copy of the opcode table and sort it on the names. */
526 opcodes = (struct m68hc11_opcode *) xmalloc (m68hc11_num_opcodes *
529 m68hc11_sorted_opcodes = opcodes;
531 for (i = 0; i < m68hc11_num_opcodes; i++)
533 if (m68hc11_opcodes[i].arch & current_architecture)
535 opcodes[num_opcodes] = m68hc11_opcodes[i];
536 if (opcodes[num_opcodes].name[0] == 'b'
537 && opcodes[num_opcodes].format & M6811_OP_JUMP_REL
538 && !(opcodes[num_opcodes].format & M6811_OP_BITMASK))
541 opcodes[num_opcodes] = m68hc11_opcodes[i];
544 for (j = 0; alias_opcodes[j].name != 0; j++)
545 if (strcmp (m68hc11_opcodes[i].name, alias_opcodes[j].name) == 0)
547 opcodes[num_opcodes] = m68hc11_opcodes[i];
548 opcodes[num_opcodes].name = alias_opcodes[j].alias;
554 qsort (opcodes, num_opcodes, sizeof (struct m68hc11_opcode), cmp_opcode);
556 opc = (struct m68hc11_opcode_def *)
557 xmalloc (num_opcodes * sizeof (struct m68hc11_opcode_def));
558 m68hc11_opcode_defs = opc--;
560 /* Insert unique names into hash table. The M6811 instruction set
561 has several identical opcode names that have different opcodes based
562 on the operands. This hash table then provides a quick index to
563 the first opcode with a particular name in the opcode table. */
564 for (i = 0; i < num_opcodes; i++, opcodes++)
568 if (strcmp (prev_name, opcodes->name))
570 prev_name = (char *) opcodes->name;
574 opc->min_operands = 100;
575 opc->max_operands = 0;
577 opc->opcode = opcodes;
579 hash_insert (m68hc11_hash, opcodes->name, (char *) opc);
582 opc->format |= opcodes->format;
584 /* See how many operands this opcode needs. */
586 if (opcodes->format & M6811_OP_MASK)
588 if (opcodes->format & M6811_OP_BITMASK)
590 if (opcodes->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
592 if (opcodes->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
595 if (expect < opc->min_operands)
596 opc->min_operands = expect;
597 if (expect > opc->max_operands)
598 opc->max_operands = expect;
601 m68hc11_nb_opcode_defs = opc - m68hc11_opcode_defs;
603 if (flag_print_opcodes)
605 print_opcode_list ();
611 m68hc11_init_after_args ()
617 /* Return a string that represents the operand format for the instruction.
618 When example is true, this generates an example of operand. This is used
619 to give an example and also to generate a test. */
621 print_opcode_format (opcode, example)
622 struct m68hc11_opcode *opcode;
625 static char buf[128];
626 int format = opcode->format;
631 if (format & M6811_OP_IMM8)
634 sprintf (p, "#%d", rand () & 0x0FF);
636 strcpy (p, _("#<imm8>"));
640 if (format & M6811_OP_IMM16)
643 sprintf (p, "#%d", rand () & 0x0FFFF);
645 strcpy (p, _("#<imm16>"));
649 if (format & M6811_OP_IX)
652 sprintf (p, "%d,X", rand () & 0x0FF);
654 strcpy (p, _("<imm8>,X"));
658 if (format & M6811_OP_IY)
661 sprintf (p, "%d,X", rand () & 0x0FF);
663 strcpy (p, _("<imm8>,X"));
667 if (format & M6812_OP_IDX)
670 sprintf (p, "%d,X", rand () & 0x0FF);
676 if (format & M6811_OP_DIRECT)
679 sprintf (p, "*Z%d", rand () & 0x0FF);
681 strcpy (p, _("*<abs8>"));
685 if (format & M6811_OP_BITMASK)
691 sprintf (p, "#$%02x", rand () & 0x0FF);
693 strcpy (p, _("#<mask>"));
696 if (format & M6811_OP_JUMP_REL)
700 if (format & M6811_OP_IND16)
703 sprintf (p, _("symbol%d"), rand () & 0x0FF);
705 strcpy (p, _("<abs>"));
710 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
714 if (format & M6811_OP_BITMASK)
716 sprintf (p, ".+%d", rand () & 0x7F);
720 sprintf (p, "L%d", rand () & 0x0FF);
724 strcpy (p, _("<label>"));
730 /* Prints the list of instructions with the possible operands. */
735 char *prev_name = "";
736 struct m68hc11_opcode *opcodes;
737 int example = flag_print_opcodes == 2;
740 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
743 opcodes = m68hc11_sorted_opcodes;
745 /* Walk the list sorted on names (by md_begin). We only report
746 one instruction per line, and we collect the different operand
748 for (i = 0; i < num_opcodes; i++, opcodes++)
750 char *fmt = print_opcode_format (opcodes, example);
754 printf ("L%d:\t", i);
755 printf ("%s %s\n", opcodes->name, fmt);
759 if (strcmp (prev_name, opcodes->name))
764 printf ("%-5.5s ", opcodes->name);
765 prev_name = (char *) opcodes->name;
768 printf (" [%s]", fmt);
774 /* Print the instruction format. This operation is called when some
775 instruction is not correct. Instruction format is printed as an
778 print_insn_format (name)
781 struct m68hc11_opcode_def *opc;
782 struct m68hc11_opcode *opcode;
785 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name);
788 as_bad (_("Instruction `%s' is not recognized."), name);
791 opcode = opc->opcode;
793 as_bad (_("Instruction formats for `%s':"), name);
798 fmt = print_opcode_format (opcode, 0, 0);
799 sprintf (buf, "\t%-5.5s %s", opcode->name, fmt);
804 while (strcmp (opcode->name, name) == 0);
807 /* Analysis of 68HC11 and 68HC12 operands. */
809 /* reg_name_search() finds the register number given its name.
810 Returns the register number or REG_NONE on failure. */
812 reg_name_search (name)
815 if (strcasecmp (name, "x") == 0 || strcasecmp (name, "ix") == 0)
817 if (strcasecmp (name, "y") == 0 || strcasecmp (name, "iy") == 0)
819 if (strcasecmp (name, "a") == 0)
821 if (strcasecmp (name, "b") == 0)
823 if (strcasecmp (name, "d") == 0)
825 if (strcasecmp (name, "sp") == 0)
827 if (strcasecmp (name, "pc") == 0)
829 if (strcasecmp (name, "ccr") == 0)
839 while (*p == ' ' || *p == '\t')
845 /* Check the string at input_line_pointer
846 to see if it is a valid register name. */
850 register_id reg_number;
851 char c, *p = input_line_pointer;
853 if (!is_name_beginner (*p++))
856 while (is_part_of_name (*p++))
863 /* Look to see if it's in the register table. */
864 reg_number = reg_name_search (input_line_pointer);
865 if (reg_number != REG_NONE)
870 input_line_pointer = p;
879 /* Parse a string of operands and return an array of expressions.
881 Operand mode[0] mode[1] exp[0] exp[1]
882 #n M6811_OP_IMM16 - O_*
883 *<exp> M6811_OP_DIRECT - O_*
884 .{+-}<exp> M6811_OP_JUMP_REL - O_*
885 <exp> M6811_OP_IND16 - O_*
886 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
887 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
888 n,+r M6812_PRE_INC " "
889 n,r- M6812_POST_DEC " "
890 n,r+ M6812_POST_INC " "
891 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
892 [D,r] M6811_OP_IDX_2 M6812_OP_REG O_register O_register
893 [n,r] M6811_OP_IDX_1 M6812_OP_REG O_constant O_register */
895 get_operand (oper, which, opmode)
900 char *p = input_line_pointer;
904 oper->exp.X_op = O_absent;
905 oper->reg1 = REG_NONE;
906 oper->reg2 = REG_NONE;
907 mode = M6811_OP_NONE;
911 if (*p == 0 || *p == '\n' || *p == '\r')
913 input_line_pointer = p;
917 if (*p == '*' && (opmode & (M6811_OP_DIRECT | M6811_OP_IND16)))
919 mode = M6811_OP_DIRECT;
924 if (!(opmode & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK)))
926 as_bad (_("Immediate operand is not allowed for operand %d."),
931 mode = M6811_OP_IMM16;
933 if (strncmp (p, "%hi", 3) == 0)
936 mode |= M6811_OP_HIGH_ADDR;
938 else if (strncmp (p, "%lo", 3) == 0)
941 mode |= M6811_OP_LOW_ADDR;
944 else if (*p == '.' && (p[1] == '+' || p[1] == '-'))
947 mode = M6811_OP_JUMP_REL;
951 if (current_architecture & cpu6811)
952 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
955 mode = M6812_OP_IDX_2;
958 else if (*p == ',') /* Special handling of ,x and ,y. */
961 input_line_pointer = p;
963 reg = register_name ();
967 oper->exp.X_op = O_constant;
968 oper->exp.X_add_number = 0;
969 oper->mode = M6812_OP_IDX;
972 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
975 input_line_pointer = p;
977 if (mode == M6811_OP_NONE || mode == M6812_OP_IDX_2)
978 reg = register_name ();
984 p = skip_whites (input_line_pointer);
985 if (*p == ']' && mode == M6812_OP_IDX_2)
988 (_("Missing second register or offset for indexed-indirect mode."));
993 oper->mode = mode | M6812_OP_REG;
996 if (mode == M6812_OP_IDX_2)
998 as_bad (_("Missing second register for indexed-indirect mode."));
1005 input_line_pointer = p;
1006 reg = register_name ();
1007 if (reg != REG_NONE)
1009 p = skip_whites (input_line_pointer);
1010 if (mode == M6812_OP_IDX_2)
1014 as_bad (_("Missing `]' to close indexed-indirect mode."));
1019 input_line_pointer = p;
1027 /* In MRI mode, isolate the operand because we can't distinguish
1028 operands from comments. */
1033 p = skip_whites (p);
1034 while (*p && *p != ' ' && *p != '\t')
1043 /* Parse as an expression. */
1044 expression (&oper->exp);
1053 expression (&oper->exp);
1056 if (oper->exp.X_op == O_illegal)
1058 as_bad (_("Illegal operand."));
1061 else if (oper->exp.X_op == O_absent)
1063 as_bad (_("Missing operand."));
1067 p = input_line_pointer;
1069 if (mode == M6811_OP_NONE || mode == M6811_OP_DIRECT
1070 || mode == M6812_OP_IDX_2)
1072 p = skip_whites (input_line_pointer);
1078 /* 68HC12 pre increment or decrement. */
1079 if (mode == M6811_OP_NONE)
1083 mode = M6812_PRE_DEC;
1085 if (current_architecture & cpu6811)
1086 as_bad (_("Pre-decrement mode is not valid for 68HC11"));
1090 mode = M6812_PRE_INC;
1092 if (current_architecture & cpu6811)
1093 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1095 p = skip_whites (p);
1097 input_line_pointer = p;
1098 reg = register_name ();
1101 if (which == 0 && opmode & M6812_OP_IDX_P2
1102 && reg != REG_X && reg != REG_Y
1103 && reg != REG_PC && reg != REG_SP)
1106 input_line_pointer = p;
1109 if (reg == REG_NONE && mode != M6811_OP_DIRECT
1110 && !(mode == M6811_OP_NONE && opmode & M6811_OP_IND16))
1112 as_bad (_("Wrong register in register indirect mode."));
1115 if (mode == M6812_OP_IDX_2)
1117 p = skip_whites (input_line_pointer);
1120 as_bad (_("Missing `]' to close register indirect operand."));
1123 input_line_pointer = p;
1125 if (reg != REG_NONE)
1128 if (mode == M6811_OP_NONE)
1130 p = input_line_pointer;
1133 mode = M6812_POST_DEC;
1135 if (current_architecture & cpu6811)
1137 (_("Post-decrement mode is not valid for 68HC11."));
1141 mode = M6812_POST_INC;
1143 if (current_architecture & cpu6811)
1145 (_("Post-increment mode is not valid for 68HC11."));
1148 mode = M6812_OP_IDX;
1150 input_line_pointer = p;
1153 mode |= M6812_OP_IDX;
1160 if (mode == M6812_OP_D_IDX_2)
1162 as_bad (_("Invalid indexed indirect mode."));
1167 /* If the mode is not known until now, this is either a label
1168 or an indirect address. */
1169 if (mode == M6811_OP_NONE)
1170 mode = M6811_OP_IND16 | M6811_OP_JUMP_REL;
1172 p = input_line_pointer;
1173 while (*p == ' ' || *p == '\t')
1175 input_line_pointer = p;
1181 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1182 | M6812_POST_INC | M6812_POST_DEC)
1184 /* Checks that the number 'num' fits for a given mode. */
1186 check_range (num, mode)
1190 /* Auto increment and decrement are ok for [-8..8] without 0. */
1191 if (mode & M6812_AUTO_INC_DEC)
1192 return (num != 0 && num <= 8 && num >= -8);
1194 /* The 68HC12 supports 5, 9 and 16-bits offsets. */
1195 if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX))
1196 mode = M6811_OP_IND16;
1198 if (mode & M6812_OP_JUMP_REL16)
1199 mode = M6811_OP_IND16;
1205 case M6811_OP_DIRECT:
1206 return (num >= 0 && num <= 255) ? 1 : 0;
1208 case M6811_OP_BITMASK:
1210 return (((num & 0xFFFFFF00) == 0) || ((num & 0xFFFFFF00) == 0xFFFFFF00))
1213 case M6811_OP_JUMP_REL:
1214 return (num >= -128 && num <= 127) ? 1 : 0;
1216 case M6811_OP_IND16:
1217 case M6811_OP_IMM16:
1218 return (((num & 0xFFFF0000) == 0) || ((num & 0xFFFF0000) == 0xFFFF0000))
1221 case M6812_OP_IBCC_MARKER:
1222 case M6812_OP_TBCC_MARKER:
1223 case M6812_OP_DBCC_MARKER:
1224 return (num >= -256 && num <= 255) ? 1 : 0;
1226 case M6812_OP_TRAP_ID:
1227 return ((num >= 0x30 && num <= 0x39)
1228 || (num >= 0x40 && num <= 0x0ff)) ? 1 : 0;
1235 /* Gas fixup generation. */
1237 /* Put a 1 byte expression described by 'oper'. If this expression contains
1238 unresolved symbols, generate an 8-bit fixup. */
1240 fixup8 (oper, mode, opmode)
1249 if (oper->X_op == O_constant)
1251 if (mode & M6812_OP_TRAP_ID
1252 && !check_range (oper->X_add_number, M6812_OP_TRAP_ID))
1254 static char trap_id_warn_once = 0;
1256 as_bad (_("Trap id `%ld' is out of range."), oper->X_add_number);
1257 if (trap_id_warn_once == 0)
1259 trap_id_warn_once = 1;
1260 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1264 if (!(mode & M6812_OP_TRAP_ID)
1265 && !check_range (oper->X_add_number, mode))
1267 as_bad (_("Operand out of 8-bit range: `%ld'."), oper->X_add_number);
1269 number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1);
1271 else if (oper->X_op != O_register)
1273 if (mode & M6812_OP_TRAP_ID)
1274 as_bad (_("The trap id must be a constant."));
1276 if (mode == M6811_OP_JUMP_REL)
1280 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
1281 oper, true, BFD_RELOC_8_PCREL);
1282 fixp->fx_pcrel_adjust = 1;
1286 /* Now create an 8-bit fixup. If there was some %hi or %lo
1287 modifier, generate the reloc accordingly. */
1288 fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
1290 ((opmode & M6811_OP_HIGH_ADDR)
1291 ? BFD_RELOC_M68HC11_HI8
1292 : ((opmode & M6811_OP_LOW_ADDR)
1293 ? BFD_RELOC_M68HC11_LO8 : BFD_RELOC_8)));
1295 number_to_chars_bigendian (f, 0, 1);
1299 as_fatal (_("Operand `%x' not recognized in fixup8."), oper->X_op);
1303 /* Put a 2 bytes expression described by 'oper'. If this expression contains
1304 unresolved symbols, generate a 16-bit fixup. */
1306 fixup16 (oper, mode, opmode)
1309 int opmode ATTRIBUTE_UNUSED;
1315 if (oper->X_op == O_constant)
1317 if (!check_range (oper->X_add_number, mode))
1319 as_bad (_("Operand out of 16-bit range: `%ld'."),
1320 oper->X_add_number);
1322 number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFF, 2);
1324 else if (oper->X_op != O_register)
1328 /* Now create a 16-bit fixup. */
1329 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1331 (mode & M6812_OP_JUMP_REL16 ? true : false),
1332 (mode & M6812_OP_JUMP_REL16
1333 ? BFD_RELOC_16_PCREL : BFD_RELOC_16));
1334 number_to_chars_bigendian (f, 0, 2);
1335 if (mode & M6812_OP_JUMP_REL16)
1336 fixp->fx_pcrel_adjust = 2;
1340 as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op);
1344 /* 68HC11 and 68HC12 code generation. */
1346 /* Translate the short branch/bsr instruction into a long branch. */
1347 static unsigned char
1348 convert_branch (code)
1351 if (IS_OPCODE (code, M6812_BSR))
1353 else if (IS_OPCODE (code, M6811_BSR))
1355 else if (IS_OPCODE (code, M6811_BRA))
1356 return (current_architecture & cpu6812) ? M6812_JMP : M6811_JMP;
1358 as_fatal (_("Unexpected branch conversion with `%x'"), code);
1360 /* Keep gcc happy. */
1364 /* Start a new insn that contains at least 'size' bytes. Record the
1365 line information of that insn in the dwarf2 debug sections. */
1367 m68hc11_new_insn (size)
1372 f = frag_more (size);
1374 /* Emit line number information in dwarf2 debug sections. */
1375 if (debug_type == DEBUG_DWARF2)
1376 dwarf2_generate_asm_lineno (size);
1381 /* Builds a jump instruction (bra, bcc, bsr). */
1383 build_jump_insn (opcode, operands, nb_operands, jmp_mode)
1384 struct m68hc11_opcode *opcode;
1394 /* The relative branch convertion is not supported for
1396 assert ((opcode->format & M6811_OP_BITMASK) == 0);
1397 assert (nb_operands == 1);
1398 assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE);
1400 code = opcode->opcode;
1403 n = operands[0].exp.X_add_number;
1405 /* Turn into a long branch:
1406 - when force long branch option (and not for jbcc pseudos),
1407 - when jbcc and the constant is out of -128..127 range,
1408 - when branch optimization is allowed and branch out of range. */
1409 if ((jmp_mode == 0 && flag_force_long_jumps)
1410 || (operands[0].exp.X_op == O_constant
1411 && (!check_range (n, opcode->format) &&
1412 (jmp_mode == 1 || flag_fixed_branchs == 0))))
1414 if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
1416 code = convert_branch (code);
1418 f = m68hc11_new_insn (1);
1419 number_to_chars_bigendian (f, code, 1);
1421 else if (current_architecture & cpu6812)
1423 /* 68HC12: translate the bcc into a lbcc. */
1424 f = m68hc11_new_insn (2);
1425 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1426 number_to_chars_bigendian (f + 1, code, 1);
1427 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16,
1428 M6812_OP_JUMP_REL16);
1433 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1434 f = m68hc11_new_insn (3);
1436 number_to_chars_bigendian (f, code, 1);
1437 number_to_chars_bigendian (f + 1, 3, 1);
1438 number_to_chars_bigendian (f + 2, M6811_JMP, 1);
1440 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16);
1444 /* Branch with a constant that must fit in 8-bits. */
1445 if (operands[0].exp.X_op == O_constant)
1447 if (!check_range (n, opcode->format))
1449 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1452 else if (opcode->format & M6812_OP_JUMP_REL16)
1454 f = m68hc11_new_insn (4);
1455 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1456 number_to_chars_bigendian (f + 1, code, 1);
1457 number_to_chars_bigendian (f + 2, n & 0x0ffff, 2);
1461 f = m68hc11_new_insn (2);
1462 number_to_chars_bigendian (f, code, 1);
1463 number_to_chars_bigendian (f + 1, n & 0x0FF, 1);
1466 else if (opcode->format & M6812_OP_JUMP_REL16)
1468 f = m68hc11_new_insn (2);
1469 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1470 number_to_chars_bigendian (f + 1, code, 1);
1471 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16, M6812_OP_JUMP_REL16);
1477 /* Branch offset must fit in 8-bits, don't do some relax. */
1478 if (jmp_mode == 0 && flag_fixed_branchs)
1480 opcode = m68hc11_new_insn (1);
1481 number_to_chars_bigendian (opcode, code, 1);
1482 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL);
1485 /* bra/bsr made be changed into jmp/jsr. */
1486 else if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
1488 opcode = m68hc11_new_insn (2);
1489 number_to_chars_bigendian (opcode, code, 1);
1490 number_to_chars_bigendian (opcode + 1, 0, 1);
1491 frag_var (rs_machine_dependent, 2, 1,
1492 ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF),
1493 operands[0].exp.X_add_symbol, (offsetT) n, opcode);
1495 else if (current_architecture & cpu6812)
1497 opcode = m68hc11_new_insn (2);
1498 number_to_chars_bigendian (opcode, code, 1);
1499 number_to_chars_bigendian (opcode + 1, 0, 1);
1500 frag_var (rs_machine_dependent, 2, 2,
1501 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_UNDF),
1502 operands[0].exp.X_add_symbol, (offsetT) n, opcode);
1506 opcode = m68hc11_new_insn (2);
1507 number_to_chars_bigendian (opcode, code, 1);
1508 number_to_chars_bigendian (opcode + 1, 0, 1);
1509 frag_var (rs_machine_dependent, 3, 3,
1510 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF),
1511 operands[0].exp.X_add_symbol, (offsetT) n, opcode);
1516 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1518 build_dbranch_insn (opcode, operands, nb_operands, jmp_mode)
1519 struct m68hc11_opcode *opcode;
1529 /* The relative branch convertion is not supported for
1531 assert ((opcode->format & M6811_OP_BITMASK) == 0);
1532 assert (nb_operands == 2);
1533 assert (operands[0].reg1 != REG_NONE);
1535 code = opcode->opcode & 0x0FF;
1538 f = m68hc11_new_insn (1);
1539 number_to_chars_bigendian (f, code, 1);
1541 n = operands[1].exp.X_add_number;
1542 code = operands[0].reg1;
1544 if (operands[0].reg1 == REG_NONE || operands[0].reg1 == REG_CCR
1545 || operands[0].reg1 == REG_PC)
1546 as_bad (_("Invalid register for dbcc/tbcc instruction."));
1548 if (opcode->format & M6812_OP_IBCC_MARKER)
1550 else if (opcode->format & M6812_OP_TBCC_MARKER)
1553 if (!(opcode->format & M6812_OP_EQ_MARKER))
1556 /* Turn into a long branch:
1557 - when force long branch option (and not for jbcc pseudos),
1558 - when jdbcc and the constant is out of -256..255 range,
1559 - when branch optimization is allowed and branch out of range. */
1560 if ((jmp_mode == 0 && flag_force_long_jumps)
1561 || (operands[1].exp.X_op == O_constant
1562 && (!check_range (n, M6812_OP_IBCC_MARKER) &&
1563 (jmp_mode == 1 || flag_fixed_branchs == 0))))
1567 number_to_chars_bigendian (f, code, 1);
1568 number_to_chars_bigendian (f + 1, M6812_JMP, 1);
1569 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16);
1573 /* Branch with a constant that must fit in 9-bits. */
1574 if (operands[1].exp.X_op == O_constant)
1576 if (!check_range (n, M6812_OP_IBCC_MARKER))
1578 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1587 number_to_chars_bigendian (f, code, 1);
1588 number_to_chars_bigendian (f + 1, n & 0x0FF, 1);
1593 /* Branch offset must fit in 8-bits, don't do some relax. */
1594 if (jmp_mode == 0 && flag_fixed_branchs)
1596 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL);
1602 number_to_chars_bigendian (f, code, 1);
1603 number_to_chars_bigendian (f + 1, 0, 1);
1604 frag_var (rs_machine_dependent, 3, 3,
1605 ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_UNDF),
1606 operands[1].exp.X_add_symbol, (offsetT) n, f);
1611 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
1613 /* Assemble the post index byte for 68HC12 extended addressing modes. */
1615 build_indexed_byte (op, format, move_insn)
1617 int format ATTRIBUTE_UNUSED;
1620 unsigned char byte = 0;
1625 val = op->exp.X_add_number;
1627 if (mode & M6812_AUTO_INC_DEC)
1630 if (mode & (M6812_POST_INC | M6812_POST_DEC))
1633 if (op->exp.X_op == O_constant)
1635 if (!check_range (val, mode))
1637 as_bad (_("Increment/decrement value is out of range: `%ld'."),
1640 if (mode & (M6812_POST_INC | M6812_PRE_INC))
1641 byte |= (val - 1) & 0x07;
1643 byte |= (8 - ((val) & 7)) | 0x8;
1648 as_fatal (_("Expecting a register."));
1663 as_bad (_("Invalid register for post/pre increment."));
1668 number_to_chars_bigendian (f, byte, 1);
1672 if (mode & M6812_OP_IDX)
1693 as_bad (_("Invalid register."));
1696 if (op->exp.X_op == O_constant)
1698 if (!check_range (val, M6812_OP_IDX))
1700 as_bad (_("Offset out of 16-bit range: %ld."), val);
1703 if (move_insn && !(val >= -16 && val <= 15))
1705 as_bad (_("Offset out of 5-bit range for movw/movb insn."));
1709 if (val >= -16 && val <= 15 && !(mode & M6812_OP_IDX_2))
1714 number_to_chars_bigendian (f, byte, 1);
1717 else if (val >= -256 && val <= 255 && !(mode & M6812_OP_IDX_2))
1724 number_to_chars_bigendian (f, byte, 1);
1725 number_to_chars_bigendian (f + 1, val & 0x0FF, 1);
1731 if (mode & M6812_OP_IDX_2)
1737 number_to_chars_bigendian (f, byte, 1);
1738 number_to_chars_bigendian (f + 1, val & 0x0FFFF, 2);
1743 number_to_chars_bigendian (f, byte, 1);
1745 fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1746 &op->exp, false, BFD_RELOC_16);
1748 frag_var (rs_machine_dependent, 2, 2,
1749 ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF),
1750 op->exp.X_add_symbol, val, f);
1754 if (mode & M6812_OP_REG)
1756 if (mode & M6812_OP_IDX_2)
1758 if (op->reg1 != REG_D)
1759 as_bad (_("Expecting register D for indexed indirect mode."));
1761 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
1778 as_bad (_("Invalid accumulator register."));
1803 as_bad (_("Invalid indexed register."));
1807 number_to_chars_bigendian (f, byte, 1);
1811 as_fatal (_("Addressing mode not implemented yet."));
1815 /* Assemble the 68HC12 register mode byte. */
1817 build_reg_mode (op, format)
1824 if (format & M6812_OP_SEX_MARKER
1825 && op->reg1 != REG_A && op->reg1 != REG_B && op->reg1 != REG_CCR)
1826 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
1827 else if (op->reg1 == REG_NONE || op->reg1 == REG_PC)
1828 as_bad (_("Invalid source register."));
1830 if (format & M6812_OP_SEX_MARKER
1831 && op->reg2 != REG_D
1832 && op->reg2 != REG_X && op->reg2 != REG_Y && op->reg2 != REG_SP)
1833 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
1834 else if (op->reg2 == REG_NONE || op->reg2 == REG_PC)
1835 as_bad (_("Invalid destination register."));
1837 byte = (op->reg1 << 4) | (op->reg2);
1838 if (format & M6812_OP_EXG_MARKER)
1842 number_to_chars_bigendian (f, byte, 1);
1846 /* build_insn takes a pointer to the opcode entry in the opcode table,
1847 the array of operand expressions and builds the correspding instruction.
1848 This operation only deals with non relative jumps insn (need special
1851 build_insn (opcode, operands, nb_operands)
1852 struct m68hc11_opcode *opcode;
1854 int nb_operands ATTRIBUTE_UNUSED;
1862 /* Put the page code instruction if there is one. */
1863 format = opcode->format;
1864 if (format & OP_EXTENDED)
1868 f = m68hc11_new_insn (2);
1869 if (format & M6811_OP_PAGE2)
1870 page_code = M6811_OPCODE_PAGE2;
1871 else if (format & M6811_OP_PAGE3)
1872 page_code = M6811_OPCODE_PAGE3;
1874 page_code = M6811_OPCODE_PAGE4;
1876 number_to_chars_bigendian (f, page_code, 1);
1881 f = m68hc11_new_insn (1);
1883 number_to_chars_bigendian (f, opcode->opcode, 1);
1887 /* The 68HC12 movb and movw instructions are special. We have to handle
1888 them in a special way. */
1889 if (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
1892 if (format & M6812_OP_IDX)
1894 insn_size += build_indexed_byte (&operands[0], format, 1);
1896 format &= ~M6812_OP_IDX;
1898 if (format & M6812_OP_IDX_P2)
1900 insn_size += build_indexed_byte (&operands[1], format, 1);
1902 format &= ~M6812_OP_IDX_P2;
1906 if (format & (M6811_OP_DIRECT | M6811_OP_IMM8))
1909 fixup8 (&operands[i].exp,
1910 format & (M6811_OP_DIRECT | M6811_OP_IMM8 | M6812_OP_TRAP_ID),
1914 else if (format & (M6811_OP_IMM16 | M6811_OP_IND16))
1917 fixup16 (&operands[i].exp, format & (M6811_OP_IMM16 | M6811_OP_IND16),
1921 else if (format & (M6811_OP_IX | M6811_OP_IY))
1923 if ((format & M6811_OP_IX) && (operands[0].reg1 != REG_X))
1924 as_bad (_("Invalid indexed register, expecting register X."));
1925 if ((format & M6811_OP_IY) && (operands[0].reg1 != REG_Y))
1926 as_bad (_("Invalid indexed register, expecting register Y."));
1929 fixup8 (&operands[0].exp, M6811_OP_IX, operands[0].mode);
1933 (M6812_OP_IDX | M6812_OP_IDX_2 | M6812_OP_IDX_1 | M6812_OP_D_IDX))
1935 insn_size += build_indexed_byte (&operands[i], format, move_insn);
1938 else if (format & M6812_OP_REG && current_architecture & cpu6812)
1940 insn_size += build_reg_mode (&operands[i], format);
1943 if (format & M6811_OP_BITMASK)
1946 fixup8 (&operands[i].exp, M6811_OP_BITMASK, operands[i].mode);
1949 if (format & M6811_OP_JUMP_REL)
1952 fixup8 (&operands[i].exp, M6811_OP_JUMP_REL, operands[i].mode);
1955 else if (format & M6812_OP_IND16_P2)
1958 fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode);
1962 /* Opcode identification and operand analysis. */
1964 /* find() gets a pointer to an entry in the opcode table. It must look at all
1965 opcodes with the same name and use the operands to choose the correct
1966 opcode. Returns the opcode pointer if there was a match and 0 if none. */
1967 static struct m68hc11_opcode *
1968 find (opc, operands, nb_operands)
1969 struct m68hc11_opcode_def *opc;
1974 struct m68hc11_opcode *opcode;
1975 struct m68hc11_opcode *op_indirect;
1978 opcode = opc->opcode;
1980 /* Now search the opcode table table for one with operands
1981 that matches what we've got. We're only done if the operands matched so
1982 far AND there are no more to check. */
1983 for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++)
1985 int poss_indirect = 0;
1986 long format = opcode->format;
1990 if (opcode->format & M6811_OP_MASK)
1992 if (opcode->format & M6811_OP_BITMASK)
1994 if (opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
1996 if (opcode->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
1999 for (i = 0; expect == nb_operands && i < nb_operands; i++)
2001 int mode = operands[i].mode;
2003 if (mode & M6811_OP_IMM16)
2006 (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK))
2010 if (mode == M6811_OP_DIRECT)
2012 if (format & M6811_OP_DIRECT)
2015 /* If the operand is a page 0 operand, remember a
2016 possible <abs-16> addressing mode. We mark
2017 this and continue to check other operands. */
2018 if (format & M6811_OP_IND16
2019 && flag_strict_direct_addressing && op_indirect == 0)
2026 if (mode & M6811_OP_IND16)
2028 if (i == 0 && (format & M6811_OP_IND16) != 0)
2030 if (i != 0 && (format & M6812_OP_IND16_P2) != 0)
2032 if (i == 0 && (format & M6811_OP_BITMASK))
2035 if (mode & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2037 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2040 if (mode & M6812_OP_REG)
2043 && (format & M6812_OP_REG)
2044 && (operands[i].reg2 == REG_NONE))
2047 && (format & M6812_OP_REG)
2048 && (format & M6812_OP_REG_2)
2049 && (operands[i].reg2 != REG_NONE))
2052 && (format & M6812_OP_IDX)
2053 && (operands[i].reg2 != REG_NONE))
2056 && (format & M6812_OP_D_IDX))
2059 && (format & M6812_OP_IDX)
2060 && (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)))
2063 && (format & M6812_OP_IDX_P2))
2067 if (mode & M6812_OP_IDX)
2069 if (format & M6811_OP_IX && operands[i].reg1 == REG_X)
2071 if (format & M6811_OP_IY && operands[i].reg1 == REG_Y)
2074 && format & (M6812_OP_IDX | M6812_OP_IDX_1 | M6812_OP_IDX_2)
2075 && (operands[i].reg1 == REG_X
2076 || operands[i].reg1 == REG_Y
2077 || operands[i].reg1 == REG_SP
2078 || operands[i].reg1 == REG_PC))
2080 if (i == 1 && format & M6812_OP_IDX_P2)
2083 if (mode & M6812_AUTO_INC_DEC)
2086 && format & (M6812_OP_IDX | M6812_OP_IDX_1 |
2089 if (i == 1 && format & M6812_OP_IDX_P2)
2094 match = i == nb_operands;
2096 /* Operands are ok but an operand uses page 0 addressing mode
2097 while the insn supports abs-16 mode. Keep a reference to this
2098 insns in case there is no insn supporting page 0 addressing. */
2099 if (match && poss_indirect)
2101 op_indirect = opcode;
2108 /* Page 0 addressing is used but not supported by any insn.
2109 If absolute addresses are supported, we use that insn. */
2110 if (match == 0 && op_indirect)
2112 opcode = op_indirect;
2124 /* Find the real opcode and its associated operands. We use a progressive
2125 approach here. On entry, 'opc' points to the first opcode in the
2126 table that matches the opcode name in the source line. We try to
2127 isolate an operand, find a possible match in the opcode table.
2128 We isolate another operand if no match were found. The table 'operands'
2129 is filled while operands are recognized.
2131 Returns the opcode pointer that matches the opcode name in the
2132 source line and the associated operands. */
2133 static struct m68hc11_opcode *
2134 find_opcode (opc, operands, nb_operands)
2135 struct m68hc11_opcode_def *opc;
2139 struct m68hc11_opcode *opcode;
2142 if (opc->max_operands == 0)
2148 for (i = 0; i < opc->max_operands;)
2152 result = get_operand (&operands[i], i, opc->format);
2156 /* Special case where the bitmask of the bclr/brclr
2157 instructions is not introduced by #.
2158 Example: bclr 3,x $80. */
2159 if (i == 1 && (opc->format & M6811_OP_BITMASK)
2160 && (operands[i].mode & M6811_OP_IND16))
2162 operands[i].mode = M6811_OP_IMM16;
2167 if (i >= opc->min_operands)
2169 opcode = find (opc, operands, i);
2174 if (*input_line_pointer == ',')
2175 input_line_pointer++;
2181 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2182 | M6812_OP_DBCC_MARKER \
2183 | M6812_OP_IBCC_MARKER)
2185 /* Gas line assembler entry point. */
2187 /* This is the main entry point for the machine-dependent assembler. str
2188 points to a machine-dependent instruction. This function is supposed to
2189 emit the frags/bytes it assembles to. */
2194 struct m68hc11_opcode_def *opc;
2195 struct m68hc11_opcode *opcode;
2197 unsigned char *op_start, *save;
2198 unsigned char *op_end;
2201 operand operands[M6811_MAX_OPERANDS];
2203 int branch_optimize = 0;
2206 /* Drop leading whitespace. */
2210 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2211 lower case (the opcode table only has lower case op-codes). */
2212 for (op_start = op_end = (unsigned char *) (str);
2213 *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' ';
2216 name[nlen] = tolower (op_start[nlen]);
2223 as_bad (_("No instruction or missing opcode."));
2227 /* Find the opcode definition given its name. */
2228 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name);
2230 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
2231 pseudo insns for relative branch. For these branchs, we always
2232 optimize them (turned into absolute branchs) even if --short-branchs
2234 if (opc == NULL && name[0] == 'j' && name[1] == 'b')
2236 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, &name[1]);
2238 && (!(opc->format & M6811_OP_JUMP_REL)
2239 || (opc->format & M6811_OP_BITMASK)))
2242 branch_optimize = 1;
2245 /* The following test should probably be removed. This is not conform
2246 to Motorola assembler specs. */
2247 if (opc == NULL && flag_mri)
2249 if (*op_end == ' ' || *op_end == '\t')
2251 while (*op_end == ' ' || *op_end == '\t')
2256 (is_end_of_line[op_end[1]]
2257 || op_end[1] == ' ' || op_end[1] == '\t'
2258 || !isalnum (op_end[1])))
2259 && (*op_end == 'a' || *op_end == 'b'
2260 || *op_end == 'A' || *op_end == 'B'
2261 || *op_end == 'd' || *op_end == 'D'
2262 || *op_end == 'x' || *op_end == 'X'
2263 || *op_end == 'y' || *op_end == 'Y'))
2265 name[nlen++] = tolower (*op_end++);
2267 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash,
2273 /* Identify a possible instruction alias. There are some on the
2274 68HC12 to emulate a fiew 68HC11 instructions. */
2275 if (opc == NULL && (current_architecture & cpu6812))
2279 for (i = 0; i < m68hc12_num_alias; i++)
2280 if (strcmp (m68hc12_alias[i].name, name) == 0)
2286 if (opc == NULL && alias_id < 0)
2288 as_bad (_("Opcode `%s' is not recognized."), name);
2291 save = input_line_pointer;
2292 input_line_pointer = op_end;
2297 opcode = find_opcode (opc, operands, &nb_operands);
2302 if ((opcode || alias_id >= 0) && !flag_mri)
2304 char *p = input_line_pointer;
2306 while (*p == ' ' || *p == '\t' || *p == '\n' || *p == '\r')
2309 if (*p != '\n' && *p)
2310 as_bad (_("Garbage at end of instruction: `%s'."), p);
2313 input_line_pointer = save;
2317 char *f = m68hc11_new_insn (m68hc12_alias[alias_id].size);
2319 number_to_chars_bigendian (f, m68hc12_alias[alias_id].code1, 1);
2320 if (m68hc12_alias[alias_id].size > 1)
2321 number_to_chars_bigendian (f + 1, m68hc12_alias[alias_id].code2, 1);
2326 /* Opcode is known but does not have valid operands. Print out the
2327 syntax for this opcode. */
2330 if (flag_print_insn_syntax)
2331 print_insn_format (name);
2333 as_bad (_("Invalid operand for `%s'"), name);
2337 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
2338 relative and must be in the range -256..255 (9-bits). */
2339 if ((opcode->format & M6812_XBCC_MARKER)
2340 && (opcode->format & M6811_OP_JUMP_REL))
2341 build_dbranch_insn (opcode, operands, nb_operands);
2343 /* Relative jumps instructions are taken care of separately. We have to make
2344 sure that the relative branch is within the range -128..127. If it's out
2345 of range, the instructions are changed into absolute instructions.
2346 This is not supported for the brset and brclr instructions. */
2347 else if ((opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2348 && !(opcode->format & M6811_OP_BITMASK))
2349 build_jump_insn (opcode, operands, nb_operands, branch_optimize);
2351 build_insn (opcode, operands, nb_operands);
2354 /* Relocation, relaxation and frag conversions. */
2356 md_pcrel_from_section (fixp, sec)
2361 if (fixp->fx_addsy != (symbolS *) NULL
2362 && (!S_IS_DEFINED (fixp->fx_addsy)
2363 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
2366 adjust = fixp->fx_pcrel_adjust;
2367 return fixp->fx_frag->fr_address + fixp->fx_where + adjust;
2370 /* If while processing a fixup, a reloc really needs to be created
2371 then it is done here. */
2373 tc_gen_reloc (section, fixp)
2379 reloc = (arelent *) xmalloc (sizeof (arelent));
2380 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2381 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
2382 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2383 if (fixp->fx_r_type == 0)
2384 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
2386 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
2387 if (reloc->howto == (reloc_howto_type *) NULL)
2389 as_bad_where (fixp->fx_file, fixp->fx_line,
2390 _("Relocation %d is not supported by object file format."),
2391 (int) fixp->fx_r_type);
2395 if (!fixp->fx_pcrel)
2396 reloc->addend = fixp->fx_addnumber;
2398 reloc->addend = (section->vma
2399 + (fixp->fx_pcrel_adjust == 64
2400 ? -1 : fixp->fx_pcrel_adjust)
2401 + fixp->fx_addnumber
2402 + md_pcrel_from_section (fixp, section));
2407 md_convert_frag (abfd, sec, fragP)
2408 bfd *abfd ATTRIBUTE_UNUSED;
2409 asection *sec ATTRIBUTE_UNUSED;
2414 char *buffer_address = fragP->fr_literal;
2416 /* Address in object code of the displacement. */
2417 register int object_address = fragP->fr_fix + fragP->fr_address;
2419 buffer_address += fragP->fr_fix;
2421 /* The displacement of the address, from current location. */
2422 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
2423 disp = (disp + fragP->fr_offset) - object_address;
2424 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
2426 switch (fragP->fr_subtype)
2428 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE):
2429 fragP->fr_opcode[1] = disp;
2432 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD):
2433 /* This relax is only for bsr and bra. */
2434 assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
2435 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
2436 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
2438 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]);
2440 fix_new (fragP, fragP->fr_fix - 1, 2,
2441 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2445 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE):
2446 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_BYTE):
2447 fragP->fr_opcode[1] = disp;
2450 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD):
2451 /* Invert branch. */
2452 fragP->fr_opcode[0] ^= 1;
2453 fragP->fr_opcode[1] = 3; /* Branch offset. */
2454 buffer_address[0] = M6811_JMP;
2455 fix_new (fragP, fragP->fr_fix + 1, 2,
2456 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2460 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD):
2461 /* Translate branch into a long branch. */
2462 fragP->fr_opcode[1] = fragP->fr_opcode[0];
2463 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2;
2465 fixp = fix_new (fragP, fragP->fr_fix, 2,
2466 fragP->fr_symbol, fragP->fr_offset, 1,
2467 BFD_RELOC_16_PCREL);
2468 fixp->fx_pcrel_adjust = 2;
2472 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5):
2473 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 5;
2474 fragP->fr_opcode[0] |= disp & 0x1f;
2477 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9):
2478 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3);
2479 fragP->fr_opcode[0] |= 0xE0;
2480 fix_new (fragP, fragP->fr_fix + 1, 1,
2481 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_8);
2485 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16):
2486 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3);
2487 fragP->fr_opcode[0] |= 0xE2;
2488 fix_new (fragP, fragP->fr_fix, 2,
2489 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2493 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE):
2495 fragP->fr_opcode[0] |= 0x10;
2497 fragP->fr_opcode[1] = disp & 0x0FF;
2500 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD):
2501 /* Invert branch. */
2502 fragP->fr_opcode[0] ^= 0x20;
2503 fragP->fr_opcode[1] = 3; /* Branch offset. */
2504 buffer_address[0] = M6812_JMP;
2505 fix_new (fragP, fragP->fr_fix + 1, 2,
2506 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2515 /* Force truly undefined symbols to their maximum size, and generally set up
2516 the frag list to be relaxed. */
2518 md_estimate_size_before_relax (fragP, segment)
2523 char *buffer_address = fragP->fr_fix + fragP->fr_literal;
2525 old_fr_fix = fragP->fr_fix;
2527 switch (fragP->fr_subtype)
2529 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF):
2531 /* This relax is only for bsr and bra. */
2532 assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
2533 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
2534 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
2536 /* A relaxable case. */
2537 if (S_GET_SEGMENT (fragP->fr_symbol) == segment)
2539 fragP->fr_subtype = ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE);
2543 if (flag_fixed_branchs)
2544 as_bad_where (fragP->fr_file, fragP->fr_line,
2545 _("bra or bsr with undefined symbol."));
2547 /* The symbol is undefined or in a separate section. Turn bra into a
2548 jmp and bsr into a jsr. The insn becomes 3 bytes long (instead of
2549 2). A fixup is necessary for the unresolved symbol address. */
2551 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]);
2554 fix_new (fragP, old_fr_fix - 1, 2, fragP->fr_symbol,
2555 fragP->fr_offset, 0, BFD_RELOC_16);
2560 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF):
2561 assert (current_architecture & cpu6811);
2563 if (S_GET_SEGMENT (fragP->fr_symbol) == segment)
2565 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH,
2570 fragP->fr_opcode[0] ^= 1; /* Reverse sense of branch. */
2571 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */
2573 /* Don't use fr_opcode[2] because this may be
2574 in a different frag. */
2575 buffer_address[0] = M6811_JMP;
2578 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2579 fragP->fr_offset, 0, BFD_RELOC_16);
2585 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF):
2586 assert (current_architecture & cpu6812);
2588 if (S_GET_SEGMENT (fragP->fr_symbol) == segment)
2590 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET,
2595 /* Switch the indexed operation to 16-bit mode. */
2596 if ((fragP->fr_opcode[1] & 0x21) == 0x20)
2597 fragP->fr_opcode[1] = (fragP->fr_opcode[1] >> 3) | 0xc0 | 0x02;
2600 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2601 fragP->fr_offset, 0, BFD_RELOC_16);
2607 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_UNDF):
2608 assert (current_architecture & cpu6812);
2610 if (S_GET_SEGMENT (fragP->fr_symbol) == segment)
2612 fragP->fr_subtype = ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE);
2616 fragP->fr_opcode[0] ^= 0x20; /* Reverse sense of branch. */
2617 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */
2619 /* Don't use fr_opcode[2] because this may be
2620 in a different frag. */
2621 buffer_address[0] = M6812_JMP;
2624 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2625 fragP->fr_offset, 0, BFD_RELOC_16);
2631 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_UNDF):
2632 assert (current_architecture & cpu6812);
2634 if (S_GET_SEGMENT (fragP->fr_symbol) == segment)
2636 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812,
2641 /* Translate into a lbcc branch. */
2642 fragP->fr_opcode[1] = fragP->fr_opcode[0];
2643 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2;
2645 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2646 fragP->fr_offset, 0, BFD_RELOC_16_PCREL);
2653 as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype);
2656 return (fragP->fr_fix - old_fr_fix);
2660 md_apply_fix (fixp, valuep)
2668 if (fixp->fx_addsy == (symbolS *) NULL)
2673 else if (fixp->fx_pcrel)
2679 value = fixp->fx_offset;
2680 if (fixp->fx_subsy != (symbolS *) NULL)
2682 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
2684 value -= S_GET_VALUE (fixp->fx_subsy);
2688 /* We don't actually support subtracting a symbol. */
2689 as_bad_where (fixp->fx_file, fixp->fx_line,
2690 _("Expression too complex."));
2695 op_type = fixp->fx_r_type;
2697 /* Patch the instruction with the resolved operand. Elf relocation
2698 info will also be generated to take care of linker/loader fixups.
2699 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
2700 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
2701 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
2702 because it's either resolved or turned out into non-relative insns (see
2703 relax table, bcc, bra, bsr transformations)
2705 The BFD_RELOC_32 is necessary for the support of --gstabs. */
2706 where = fixp->fx_frag->fr_literal + fixp->fx_where;
2708 switch (fixp->fx_r_type)
2711 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
2715 case BFD_RELOC_16_PCREL:
2716 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
2717 if (value < -65537 || value > 65535)
2718 as_bad_where (fixp->fx_file, fixp->fx_line,
2719 _("Value out of 16-bit range."));
2722 case BFD_RELOC_M68HC11_HI8:
2726 case BFD_RELOC_M68HC11_LO8:
2729 bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
2731 ((bfd_byte *) where)[0] = (bfd_byte) value;
2734 case BFD_RELOC_8_PCREL:
2736 bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
2738 ((bfd_byte *) where)[0] = (bfd_byte) value;
2740 if (value < -128 || value > 127)
2741 as_bad_where (fixp->fx_file, fixp->fx_line,
2742 _("Value %ld too large for 8-bit PC-relative branch."),
2746 case BFD_RELOC_M68HC11_3B:
2747 if (value <= 0 || value > 8)
2748 as_bad_where (fixp->fx_file, fixp->fx_line,
2749 _("Auto increment/decrement offset '%ld' is out of range."),
2756 where[0] = where[0] | (value & 0x07);
2760 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
2761 fixp->fx_line, fixp->fx_r_type);
2774 m68hc11_end_of_source ()
2777 subsegT saved_subseg;
2780 long total_size = 0;
2782 if (debug_type != DEBUG_DWARF2)
2787 saved_seg = now_seg;
2788 saved_subseg = now_subseg;
2790 debug_info = subseg_new (".debug_info", 0);
2791 bfd_set_section_flags (stdoutput, debug_info, SEC_READONLY);
2792 subseg_set (debug_info, 0);
2796 # define STUFF(val,size) md_number_to_chars (p, val, size); p += size;
2797 STUFF (total_size, 4); /* Length of compilation unit. */
2798 STUFF (2, 2); /* Dwarf version */
2800 STUFF (2, 1); /* Pointer size */
2801 STUFF (1, 1); /* Compile unit */
2804 now_subseg = saved_subseg;
2805 now_seg = saved_seg;