1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
28 /* Structure to hold all of the different components describing an individual instruction. */
31 const CGEN_INSN * insn;
32 const CGEN_INSN * orig_insn;
35 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
37 char buffer [CGEN_MAX_INSN_SIZE];
41 int indices [MAX_OPERAND_INSTANCES];
45 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
46 boundary (i.e. was the first of two 16 bit insns). */
47 static m32r_insn prev_insn;
49 /* Non-zero if we've seen a relaxable insn since the last 32 bit
51 static int seen_relaxable_p = 0;
53 /* Non-zero if -relax specified, in which case sufficient relocs are output
54 for the linker to do relaxing.
55 We do simple forms of relaxing internally, but they are always done.
56 This flag does not apply to them. */
57 static int m32r_relax;
59 /* If non-NULL, pointer to cpu description file to read.
60 This allows runtime additions to the assembler. */
61 static char * m32r_cpu_desc;
63 /* start-sanitize-m32rx */
64 /* Non-zero if -m32rx has been specified, in which case support for the
65 extended M32RX instruction set should be enabled. */
66 static int enable_m32rx = 0;
68 /* Non-zero if the programmer should be warned when an explicit parallel
69 instruction might have constraint violations. */
70 static int warn_explicit_parallel_conflicts = 1;
71 /* end-sanitize-m32rx */
73 /* stuff for .scomm symbols. */
74 static segT sbss_section;
75 static asection scom_section;
76 static asymbol scom_symbol;
78 const char comment_chars[] = ";";
79 const char line_comment_chars[] = "#";
80 const char line_separator_chars[] = "";
81 const char EXP_CHARS[] = "eE";
82 const char FLT_CHARS[] = "dD";
84 /* Relocations against symbols are done in two
85 parts, with a HI relocation and a LO relocation. Each relocation
86 has only 16 bits of space to store an addend. This means that in
87 order for the linker to handle carries correctly, it must be able
88 to locate both the HI and the LO relocation. This means that the
89 relocations must appear in order in the relocation table.
91 In order to implement this, we keep track of each unmatched HI
92 relocation. We then sort them so that they immediately precede the
93 corresponding LO relocation. */
97 struct m32r_hi_fixup * next; /* Next HI fixup. */
98 fixS * fixp; /* This fixup. */
99 segT seg; /* The section this fixup is in. */
103 /* The list of unmatched HI relocs. */
105 static struct m32r_hi_fixup * m32r_hi_fixup_list;
108 /* start-sanitize-m32rx */
115 if (stdoutput != NULL)
116 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
117 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
119 /* end-sanitize-m32rx */
121 const char * md_shortopts = "";
123 struct option md_longopts[] =
125 /* start-sanitize-m32rx */
126 #define OPTION_M32RX (OPTION_MD_BASE)
127 {"m32rx", no_argument, NULL, OPTION_M32RX},
128 #define OPTION_WARN (OPTION_MD_BASE + 1)
129 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN},
130 {"Wp", no_argument, NULL, OPTION_WARN},
131 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
132 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
133 {"Wnp", no_argument, NULL, OPTION_NO_WARN},
134 /* end-sanitize-m32rx */
136 #if 0 /* not supported yet */
137 #define OPTION_RELAX (OPTION_MD_BASE + 3)
138 {"relax", no_argument, NULL, OPTION_RELAX},
139 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
140 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
143 {NULL, no_argument, NULL, 0}
145 size_t md_longopts_size = sizeof (md_longopts);
148 md_parse_option (c, arg)
154 /* start-sanitize-m32rx */
160 warn_explicit_parallel_conflicts = 1;
164 warn_explicit_parallel_conflicts = 0;
166 /* end-sanitize-m32rx */
168 #if 0 /* not supported yet */
172 case OPTION_CPU_DESC:
183 md_show_usage (stream)
186 fprintf (stream, "M32R/X options:\n");
187 /* start-sanitize-m32rx */
189 --m32rx support the extended m32rx instruction set\n");
192 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n");
194 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
196 --Wp Synonym for --warn-explicit-parallel-conflicts\n");
198 --Wnp Synonym for --no-warn-explicit-parallel-conflicts\n");
199 /* end-sanitize-m32rx */
203 --relax create linker relaxable code\n");
205 --cpu-desc provide runtime cpu description file\n");
209 static void fill_insn PARAMS ((int));
210 static void m32r_scomm PARAMS ((int));
212 /* Set by md_assemble for use by m32r_fill_insn. */
213 static subsegT prev_subseg;
214 static segT prev_seg;
216 /* The target specific pseudo-ops which we support. */
217 const pseudo_typeS md_pseudo_table[] =
220 { "fillinsn", fill_insn, 0 },
221 { "scomm", m32r_scomm, 0 },
222 /* start-sanitize-m32rx */
223 { "m32r", allow_m32rx, 0},
224 { "m32rx", allow_m32rx, 1},
225 /* end-sanitize-m32rx */
229 /* FIXME: Should be machine generated. */
230 #define NOP_INSN 0x7000
231 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
233 /* When we align the .text section, insert the correct NOP pattern.
234 N is the power of 2 alignment. LEN is the length of pattern FILL.
235 MAX is the maximum number of characters to skip when doing the alignment,
236 or 0 if there is no maximum. */
239 m32r_do_align (n, fill, len, max)
245 if ((fill == NULL || (* fill == 0 && len == 1))
246 && (now_seg->flags & SEC_CODE) != 0
247 /* Only do this special handling if aligning to at least a
250 /* Only do this special handling if we're allowed to emit at
252 && (max == 0 || max > 1))
254 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
257 /* First align to a 2 byte boundary, in case there is an odd .byte. */
258 /* FIXME: How much memory will cause gas to use when assembling a big
259 program? Perhaps we can avoid the frag_align call? */
260 frag_align (1, 0, 0);
262 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
264 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
265 /* If doing larger alignments use a repeating sequence of appropriate
269 static const unsigned char multi_nop_pattern[] =
270 { 0x70, 0x00, 0xf0, 0x00 };
271 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
281 assemble_nop (opcode)
284 char * f = frag_more (2);
285 md_number_to_chars (f, opcode, 2);
288 /* If the last instruction was the first of 2 16 bit insns,
289 output a nop to move the PC to a 32 bit boundary.
291 This is done via an alignment specification since branch relaxing
292 may make it unnecessary.
294 Internally, we need to output one of these each time a 32 bit insn is
295 seen after an insn that is relaxable. */
301 (void) m32r_do_align (2, NULL, 0, 0);
302 prev_insn.insn = NULL;
303 seen_relaxable_p = 0;
306 /* Cover function to fill_insn called after a label and at end of assembly.
308 The result is always 1: we're called in a conditional to see if the
309 current line is a label. */
312 m32r_fill_insn (done)
318 if (prev_seg != NULL)
323 subseg_set (prev_seg, prev_subseg);
327 subseg_set (seg, subseg);
340 /* Initialize the `cgen' interface. */
342 /* This is a callback from cgen to gas to parse operands. */
343 cgen_parse_operand_fn = cgen_parse_operand;
345 /* Set the machine number and endian. */
346 CGEN_SYM (init_asm) (0 /* mach number */,
348 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
350 #if 0 /* not supported yet */
351 /* If a runtime cpu description file was provided, parse it. */
352 if (m32r_cpu_desc != NULL)
356 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
358 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
362 /* Save the current subseg so we can restore it [it's the default one and
363 we don't want the initial section to be .sbss]. */
367 /* The sbss section is for local .scomm symbols. */
368 sbss_section = subseg_new (".sbss", 0);
370 /* This is copied from perform_an_assembly_pass. */
371 applicable = bfd_applicable_section_flags (stdoutput);
372 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
374 #if 0 /* What does this do? [see perform_an_assembly_pass] */
375 seg_info (bss_section)->bss = 1;
378 subseg_set (seg, subseg);
380 /* We must construct a fake section similar to bfd_com_section
381 but with the name .scommon. */
382 scom_section = bfd_com_section;
383 scom_section.name = ".scommon";
384 scom_section.output_section = & scom_section;
385 scom_section.symbol = & scom_symbol;
386 scom_section.symbol_ptr_ptr = & scom_section.symbol;
387 scom_symbol = * bfd_com_section.symbol;
388 scom_symbol.name = ".scommon";
389 scom_symbol.section = & scom_section;
391 /* start-sanitize-m32rx */
392 allow_m32rx (enable_m32rx);
393 /* end-sanitize-m32rx */
396 /* start-sanitize-m32rx */
398 #define OPERAND_IS_COND_BIT(operand, indices, index) \
399 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
400 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
401 && (indices [index] == 0 || indices [index] == 1)))
403 /* Returns true if an output of instruction 'a' is referenced by an operand
404 of instruction 'b'. If 'check_outputs' is true then b's outputs are
405 checked, otherwise its inputs are examined. */
407 first_writes_to_seconds_operands (a, b, check_outputs)
410 const int check_outputs;
412 const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn);
413 const CGEN_OPERAND_INSTANCE * b_ops = CGEN_INSN_OPERANDS (b->insn);
416 /* If at least one of the instructions takes no operands, then there is
417 nothing to check. There really are instructions without operands,
419 if (a_operands == NULL || b_ops == NULL)
422 /* Scan the operand list of 'a' looking for an output operand. */
424 CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
425 a_index ++, a_operands ++)
427 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT)
430 const CGEN_OPERAND_INSTANCE * b_operands = b_ops;
433 The Condition bit 'C' is a shadow of the CBR register (control
434 register 1) and also a shadow of bit 31 of the program status
435 word (control register 0). For now this is handled here, rather
438 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
440 /* Scan operand list of 'b' looking for another reference to the
441 condition bit, which goes in the right direction. */
443 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
444 b_index ++, b_operands ++)
446 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
447 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
448 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
454 /* Scan operand list of 'b' looking for an operand that references
455 the same hardware element, and which goes in the right direction. */
457 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
458 b_index ++, b_operands ++)
460 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
461 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
462 && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands))
463 && (a->indices [a_index] == b->indices [b_index]))
473 /* Returns true if the insn can (potentially) alter the program counter. */
478 #if 0 /* Once PC operands are working.... */
479 const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn);
481 if (a_operands == NULL)
484 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END)
486 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL
487 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
493 if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
494 || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
500 /* Returns NULL if the two 16 bit insns can be executed in parallel,
501 otherwise it returns a pointer to an error message explaining why not. */
503 can_make_parallel (a, b)
510 /* Make sure the instructions are the right length. */
511 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
512 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
515 if (first_writes_to_seconds_operands (a, b, true))
516 return "Instructions write to the same destination register.";
518 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
519 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
521 /* Make sure that the instructions use the correct execution pipelines. */
522 if ( a_pipe == PIPE_NONE
523 || b_pipe == PIPE_NONE)
524 return "Instructions do not use parallel execution pipelines.";
526 /* Leave this test for last, since it is the only test that can
527 go away if the instructions are swapped, and we want to make
528 sure that any other errors are detected before this happens. */
529 if ( a_pipe == PIPE_S
531 return "Instructions share the same execution pipeline";
538 make_parallel (buffer)
539 cgen_insn_t * buffer;
541 /* Force the top bit of the second insn to be set. */
545 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
547 value = bfd_getb16 ((bfd_byte *) buffer);
549 bfd_putb16 (value, (char *) buffer);
553 value = bfd_getl16 ((bfd_byte *) buffer);
555 bfd_putl16 (value, (char *) buffer);
560 make_parallel (buffer)
563 /* Force the top bit of the second insn to be set. */
565 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
571 assemble_parallel_insn (str, str2)
580 * str2 = 0; /* Seperate the two instructions. */
582 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
583 so that the parallel instruction will start on a 32 bit boundary. */
587 /* Parse the first instruction. */
588 if (! (first.insn = CGEN_SYM (assemble_insn)
589 (str, & first.fields, first.buffer, & errmsg)))
595 /* Check to see if this is an allowable parallel insn. */
596 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
598 as_bad ("instruction '%s' cannot be executed in parallel.", str);
603 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
605 as_bad ("instruction '%s' is for the M32RX only", str);
610 If the instruciton is relaxable, reparse it looking for a non-relaxable variant.
611 (We do not want to relax instructions inside a parallel construction, and if it
612 turns out that the branch is too far for the displacement field available to the
613 non-relaxed instruction, then this is the programmer's fault.
614 A better solution would be to pass attribute requirements to assemble_insn() so
615 that the relaxable variant would not be accepted as a valid parse of the instruction. */
617 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_RELAXABLE) != 0)
621 /* Oh dear - the insn is relaxable, so it might be replaced with a longer,
622 non-parallel version. Try appending ".s" to the instruction and reparsing it. */
624 p = strchr (str, ' ');
628 sprintf (buf, "%s.s %s", str, p + 1);
631 /* Reset fixup list to empty. */
634 first.insn = CGEN_SYM (assemble_insn) (buf, & first.fields, first.buffer, & errmsg);
636 if (first.insn == NULL)
640 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
641 str3 = str; /* Save the original string pointer. */
642 str = str2 + 2; /* Advanced past the parsed string. */
643 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
645 /* Preserve any fixups that have been generated and reset the list to empty. */
648 /* Get the indicies of the operands of the instruction. */
649 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
650 doesn't seem right. Perhaps allow passing fields like we do insn. */
651 /* FIXME: ALIAS insns do not have operands, so we use this function
652 to find the equivalent insn and overwrite the value stored in our
653 structure. We still need the original insn, however, since this
654 may have certain attributes that are not present in the unaliased
655 version (eg relaxability). When aliases behave differently this
656 may have to change. */
657 first.orig_insn = first.insn;
658 first.insn = m32r_cgen_get_insn_operands (first.insn, bfd_getb16 ((char *) first.buffer), 16,
660 if (first.insn == NULL)
661 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn");
663 /* Parse the second instruction. */
664 if (! (second.insn = CGEN_SYM (assemble_insn)
665 (str, & second.fields, second.buffer, & errmsg)))
673 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
675 as_bad ("instruction '%s' is for the M32RX only", str);
681 if ( strcmp (first.insn->name, "nop") != 0
682 && strcmp (second.insn->name, "nop") != 0)
684 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
689 /* See comment above. */
690 if (CGEN_INSN_ATTR (second.insn, CGEN_INSN_RELAXABLE) != 0)
694 /* Oh dear - the insn is relaxable, so it might be replaced with a longer,
695 non-parallel version. Try appending ".s" to the instruction and reparsing it. */
697 p = strchr (str, ' ');
701 sprintf (buf, "%s.s %s", str, p + 1);
704 /* Reset fixup list to empty, preserving saved fixups. */
705 cgen_restore_fixups();
708 second.insn = CGEN_SYM (assemble_insn) (buf, & second.fields, second.buffer, & errmsg);
710 if (second.insn == NULL)
714 /* Get the indicies of the operands of the instruction. */
715 second.orig_insn = second.insn;
716 second.insn = m32r_cgen_get_insn_operands (second.insn, bfd_getb16 ((char *) second.buffer), 16,
718 if (second.insn == NULL)
719 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn");
721 /* We assume that if the first instruction writes to a register that is
722 read by the second instruction it is because the programmer intended
723 this to happen, (after all they have explicitly requested that these
724 two instructions be executed in parallel). Although if the global
725 variable warn_explicit_parallel_conflicts is true then we do generate
726 a warning message. Similarly we assume that parallel branch and jump
727 instructions are deliberate and should not produce errors. */
729 if (warn_explicit_parallel_conflicts)
731 if (first_writes_to_seconds_operands (& first, & second, false))
732 as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2);
734 if (first_writes_to_seconds_operands (& second, & first, false))
735 as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2);
738 if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
740 /* Get the fixups for the first instruction. */
744 (void) cgen_asm_finish_insn (first.orig_insn, first.buffer,
745 CGEN_FIELDS_BITSIZE (& first.fields));
747 /* Force the top bit of the second insn to be set. */
748 make_parallel (second.buffer);
750 /* Get its fixups. */
751 cgen_restore_fixups ();
754 (void) cgen_asm_finish_insn (second.orig_insn, second.buffer,
755 CGEN_FIELDS_BITSIZE (& second.fields));
757 /* Try swapping the instructions to see if they work that way. */
758 else if (can_make_parallel (& second, & first) == NULL)
760 /* Write out the second instruction first. */
761 (void) cgen_asm_finish_insn (second.orig_insn, second.buffer,
762 CGEN_FIELDS_BITSIZE (& second.fields));
764 /* Force the top bit of the first instruction to be set. */
765 make_parallel (first.buffer);
767 /* Get the fixups for the first instruction. */
768 cgen_restore_fixups ();
770 /* Write out the first instruction. */
771 (void) cgen_asm_finish_insn (first.orig_insn, first.buffer,
772 CGEN_FIELDS_BITSIZE (& first.fields));
776 as_bad ("'%s': %s", str2, errmsg);
780 /* Set these so m32r_fill_insn can use them. */
782 prev_subseg = now_subseg;
787 /* end-sanitize-m32rx */
798 /* Initialize GAS's cgen interface for a new instruction. */
799 cgen_asm_init_parse ();
801 /* start-sanitize-m32rx */
802 /* Look for a parallel instruction seperator. */
803 if ((str2 = strstr (str, "||")) != NULL)
805 assemble_parallel_insn (str, str2);
808 /* end-sanitize-m32rx */
810 insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
817 /* start-sanitize-m32rx */
818 if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
820 as_bad ("instruction '%s' is for the M32RX only", str);
823 /* end-sanitize-m32rx */
825 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
827 /* 32 bit insns must live on 32 bit boundaries. */
828 if (prev_insn.insn || seen_relaxable_p)
830 /* ??? If calling fill_insn too many times turns us into a memory
831 pig, can we call assemble_nop instead of !seen_relaxable_p? */
835 (void) cgen_asm_finish_insn (insn.insn, insn.buffer,
836 CGEN_FIELDS_BITSIZE (& insn.fields));
840 /* start-sanitize-m32rx */
841 /* start-sanitize-phase2-m32rx */
843 /* end-sanitize-phase2-m32rx */
844 /* end-sanitize-m32rx */
846 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
849 /* Get the indices of the operands of the instruction. */
850 insn.insn = m32r_cgen_get_insn_operands (insn.insn,
851 bfd_getb16 ((char *) insn.buffer),
854 if (insn.insn == NULL)
855 as_fatal ("internal error: m32r_cgen_get_insn_operands failed");
857 /* Keep track of whether we've seen a pair of 16 bit insns.
858 prev_insn.insn is NULL when we're on a 32 bit boundary. */
861 /* start-sanitize-m32rx */
862 /* start-sanitize-phase2-m32rx */
863 /* Look to see if this instruction can be combined with the
864 previous instruction to make one, parallel, 32 bit instruction.
865 If the previous instruction (potentially) changed the flow of
866 program control, then it cannot be combined with the current
867 instruction. If the current instruction is relaxable, then it
868 might be replaced with a longer version, so we cannot combine it.
869 Also if the output of the previous instruction is used as an
870 input to the current instruction then it cannot be combined.
871 Otherwise call can_make_parallel() with both orderings of the
872 instructions to see if they can be combined. */
874 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) == 0
875 && ! writes_to_pc (& prev_insn)
876 && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
879 if (can_make_parallel (& prev_insn, & insn) == NULL)
880 make_parallel (insn.buffer);
881 else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
884 /* end-sanitize-phase2-m32rx */
885 /* end-sanitize-m32rx */
887 prev_insn.insn = NULL;
894 /* Record the frag that might be used by this insn. */
895 insn.frag = frag_now;
896 insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer,
897 CGEN_FIELDS_BITSIZE (& insn.fields));
899 /* start-sanitize-m32rx */
900 /* start-sanitize-phase2-m32rx */
905 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
907 /* Swap the two insns */
908 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
909 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
911 make_parallel (insn.addr);
913 /* Swap any relaxable frags recorded for the two insns. */
914 if (prev_insn.frag->fr_opcode == prev_insn.addr)
915 prev_insn.frag->fr_opcode = insn.addr;
916 else if (insn.frag->fr_opcode == insn.addr)
917 insn.frag->fr_opcode = prev_insn.addr;
919 /* end-sanitize-phase2-m32rx */
921 /* Record where this instruction was assembled. */
922 prev_insn.addr = insn.addr;
923 prev_insn.frag = insn.frag;
924 /* end-sanitize-m32rx */
926 /* If the insn needs the following one to be on a 32 bit boundary
927 (e.g. subroutine calls), fill this insn's slot. */
928 if (prev_insn.insn != NULL
929 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0)
932 /* If this is a relaxable insn (can be replaced with a larger version)
933 mark the fact so that we can emit an alignment directive for a
934 following 32 bit insn if we see one. */
935 if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0)
936 seen_relaxable_p = 1;
939 /* Set these so m32r_fill_insn can use them. */
941 prev_subseg = now_subseg;
944 /* The syntax in the manual says constants begin with '#'.
945 We just ignore it. */
948 md_operand (expressionP)
949 expressionS * expressionP;
951 if (* input_line_pointer == '#')
953 input_line_pointer ++;
954 expression (expressionP);
959 md_section_align (segment, size)
963 int align = bfd_get_section_alignment (stdoutput, segment);
964 return ((size + (1 << align) - 1) & (-1 << align));
968 md_undefined_symbol (name)
974 /* .scomm pseudo-op handler.
976 This is a new pseudo-op to handle putting objects in .scommon.
977 By doing this the linker won't need to do any work and more importantly
978 it removes the implicit -G arg necessary to correctly link the object file.
985 register char * name;
989 register symbolS * symbolP;
993 name = input_line_pointer;
994 c = get_symbol_end ();
996 /* just after name is now '\0' */
997 p = input_line_pointer;
1000 if (* input_line_pointer != ',')
1002 as_bad ("Expected comma after symbol-name: rest of line ignored.");
1003 ignore_rest_of_line ();
1007 input_line_pointer ++; /* skip ',' */
1008 if ((size = get_absolute_expression ()) < 0)
1010 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
1011 ignore_rest_of_line ();
1015 /* The third argument to .scomm is the alignment. */
1016 if (* input_line_pointer != ',')
1020 ++ input_line_pointer;
1021 align = get_absolute_expression ();
1024 as_warn ("ignoring bad alignment");
1028 /* Convert to a power of 2 alignment. */
1031 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
1035 as_bad ("Common alignment not a power of 2");
1036 ignore_rest_of_line ();
1044 symbolP = symbol_find_or_make (name);
1047 if (S_IS_DEFINED (symbolP))
1049 as_bad ("Ignoring attempt to re-define symbol `%s'.",
1050 S_GET_NAME (symbolP));
1051 ignore_rest_of_line ();
1055 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
1057 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
1058 S_GET_NAME (symbolP),
1059 (long) S_GET_VALUE (symbolP),
1062 ignore_rest_of_line ();
1068 segT old_sec = now_seg;
1069 int old_subsec = now_subseg;
1072 record_alignment (sbss_section, align2);
1073 subseg_set (sbss_section, 0);
1076 frag_align (align2, 0, 0);
1078 if (S_GET_SEGMENT (symbolP) == sbss_section)
1079 symbolP->sy_frag->fr_symbol = 0;
1081 symbolP->sy_frag = frag_now;
1083 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
1086 S_SET_SIZE (symbolP, size);
1087 S_SET_SEGMENT (symbolP, sbss_section);
1088 S_CLEAR_EXTERNAL (symbolP);
1089 subseg_set (old_sec, old_subsec);
1093 S_SET_VALUE (symbolP, (valueT) size);
1094 S_SET_ALIGN (symbolP, align2);
1095 S_SET_EXTERNAL (symbolP);
1096 S_SET_SEGMENT (symbolP, & scom_section);
1099 demand_empty_rest_of_line ();
1102 /* Interface to relax_segment. */
1104 /* FIXME: Build table by hand, get it working, then machine generate. */
1106 const relax_typeS md_relax_table[] =
1109 1) most positive reach of this state,
1110 2) most negative reach of this state,
1111 3) how many bytes this mode will add to the size of the current frag
1112 4) which index into the table to try if we can't fit into this one. */
1114 /* The first entry must be unused because an `rlx_more' value of zero ends
1118 /* The displacement used by GAS is from the end of the 2 byte insn,
1119 so we subtract 2 from the following. */
1120 /* 16 bit insn, 8 bit disp -> 10 bit range.
1121 This doesn't handle a branch in the right slot at the border:
1122 the "& -4" isn't taken into account. It's not important enough to
1123 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1125 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1126 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1127 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1128 /* Same thing, but with leading nop for alignment. */
1129 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1133 m32r_relax_frag (fragP, stretch)
1137 /* Address of branch insn. */
1138 long address = fragP->fr_address + fragP->fr_fix - 2;
1141 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1142 if (fragP->fr_subtype == 2)
1144 if ((address & 3) != 0)
1146 fragP->fr_subtype = 3;
1150 else if (fragP->fr_subtype == 3)
1152 if ((address & 3) == 0)
1154 fragP->fr_subtype = 2;
1160 growth = relax_frag (fragP, stretch);
1162 /* Long jump on odd halfword boundary? */
1163 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1165 fragP->fr_subtype = 3;
1173 /* Return an initial guess of the length by which a fragment must grow to
1174 hold a branch to reach its destination.
1175 Also updates fr_type/fr_subtype as necessary.
1177 Called just before doing relaxation.
1178 Any symbol that is now undefined will not become defined.
1179 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1180 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1181 Although it may not be explicit in the frag, pretend fr_var starts with a
1185 md_estimate_size_before_relax (fragP, segment)
1189 int old_fr_fix = fragP->fr_fix;
1190 char * opcode = fragP->fr_opcode;
1192 /* The only thing we have to handle here are symbols outside of the
1193 current segment. They may be undefined or in a different segment in
1194 which case linker scripts may place them anywhere.
1195 However, we can't finish the fragment here and emit the reloc as insn
1196 alignment requirements may move the insn about. */
1198 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1200 /* The symbol is undefined in this segment.
1201 Change the relaxation subtype to the max allowable and leave
1202 all further handling to md_convert_frag. */
1203 fragP->fr_subtype = 2;
1205 #if 0 /* Can't use this, but leave in for illustration. */
1206 /* Change 16 bit insn to 32 bit insn. */
1209 /* Increase known (fixed) size of fragment. */
1212 /* Create a relocation for it. */
1213 fix_new (fragP, old_fr_fix, 4,
1215 fragP->fr_offset, 1 /* pcrel */,
1216 /* FIXME: Can't use a real BFD reloc here.
1217 cgen_md_apply_fix3 can't handle it. */
1218 BFD_RELOC_M32R_26_PCREL);
1220 /* Mark this fragment as finished. */
1224 const CGEN_INSN * insn;
1227 /* Update the recorded insn.
1228 Fortunately we don't have to look very far.
1229 FIXME: Change this to record in the instruction the next higher
1230 relaxable insn to use. */
1231 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1233 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1234 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1236 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1242 fragP->fr_cgen.insn = insn;
1248 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1251 /* *fragP has been relaxed to its final size, and now needs to have
1252 the bytes inside it modified to conform to the new size.
1254 Called after relaxation is finished.
1255 fragP->fr_type == rs_machine_dependent.
1256 fragP->fr_subtype is the subtype of what the address relaxed to. */
1259 md_convert_frag (abfd, sec, fragP)
1265 char * displacement;
1271 opcode = fragP->fr_opcode;
1273 /* Address opcode resides at in file space. */
1274 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1276 switch (fragP->fr_subtype)
1280 displacement = & opcode[1];
1285 displacement = & opcode[1];
1288 opcode[2] = opcode[0] | 0x80;
1289 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1290 opcode_address += 2;
1292 displacement = & opcode[3];
1298 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1300 /* symbol must be resolved by linker */
1301 if (fragP->fr_offset & 3)
1302 as_warn ("Addend to unresolved symbol not on word boundary.");
1303 addend = fragP->fr_offset >> 2;
1307 /* Address we want to reach in file space. */
1308 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1309 target_address += fragP->fr_symbol->sy_frag->fr_address;
1310 addend = (target_address - (opcode_address & -4)) >> 2;
1313 /* Create a relocation for symbols that must be resolved by the linker.
1314 Otherwise output the completed insn. */
1316 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1318 assert (fragP->fr_subtype != 1);
1319 assert (fragP->fr_cgen.insn != 0);
1320 cgen_record_fixup (fragP,
1321 /* Offset of branch insn in frag. */
1322 fragP->fr_fix + extension - 4,
1323 fragP->fr_cgen.insn,
1325 /* FIXME: quick hack */
1327 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1329 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1331 fragP->fr_cgen.opinfo,
1332 fragP->fr_symbol, fragP->fr_offset);
1335 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1337 md_number_to_chars (displacement, (valueT) addend,
1338 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1340 fragP->fr_fix += extension;
1343 /* Functions concerning relocs. */
1345 /* The location from which a PC relative jump should be calculated,
1346 given a PC relative reloc. */
1349 md_pcrel_from_section (fixP, sec)
1353 if (fixP->fx_addsy != (symbolS *) NULL
1354 && (! S_IS_DEFINED (fixP->fx_addsy)
1355 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1357 /* The symbol is undefined (or is defined but not in this section).
1358 Let the linker figure it out. */
1362 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1365 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1366 Returns BFD_RELOC_NONE if no reloc type can be found.
1367 *FIXP may be modified if desired. */
1369 bfd_reloc_code_real_type
1370 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1371 const CGEN_INSN * insn;
1372 const CGEN_OPERAND * operand;
1375 switch (CGEN_OPERAND_TYPE (operand))
1377 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1378 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1379 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1380 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1381 case M32R_OPERAND_HI16 :
1382 case M32R_OPERAND_SLO16 :
1383 case M32R_OPERAND_ULO16 :
1384 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1385 if (fixP->tc_fix_data.opinfo != 0)
1386 return fixP->tc_fix_data.opinfo;
1389 return BFD_RELOC_NONE;
1392 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1395 m32r_record_hi16 (reloc_type, fixP, seg)
1400 struct m32r_hi_fixup * hi_fixup;
1402 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1403 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1405 hi_fixup = ((struct m32r_hi_fixup *)
1406 xmalloc (sizeof (struct m32r_hi_fixup)));
1407 hi_fixup->fixp = fixP;
1408 hi_fixup->seg = now_seg;
1409 hi_fixup->next = m32r_hi_fixup_list;
1411 m32r_hi_fixup_list = hi_fixup;
1414 /* Called while parsing an instruction to create a fixup.
1415 We need to check for HI16 relocs and queue them up for later sorting. */
1418 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1421 const CGEN_INSN * insn;
1423 const CGEN_OPERAND * operand;
1427 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1428 operand, opinfo, exp);
1430 switch (CGEN_OPERAND_TYPE (operand))
1432 case M32R_OPERAND_HI16 :
1433 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1434 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1435 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1436 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1443 /* Return BFD reloc type from opinfo field in a fixS.
1444 It's tricky using fx_r_type in m32r_frob_file because the values
1445 are BFD_RELOC_UNUSED + operand number. */
1446 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1448 /* Sort any unmatched HI16 relocs so that they immediately precede
1449 the corresponding LO16 reloc. This is called before md_apply_fix and
1455 struct m32r_hi_fixup * l;
1457 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1459 segment_info_type * seginfo;
1462 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1463 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1465 /* Check quickly whether the next fixup happens to be a matching low. */
1466 if (l->fixp->fx_next != NULL
1467 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1468 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1469 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1472 /* Look through the fixups for this segment for a matching `low'.
1473 When we find one, move the high/shigh just in front of it. We do
1474 this in two passes. In the first pass, we try to find a
1475 unique `low'. In the second pass, we permit multiple high's
1476 relocs for a single `low'. */
1477 seginfo = seg_info (l->seg);
1478 for (pass = 0; pass < 2; pass++)
1484 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1486 /* Check whether this is a `low' fixup which matches l->fixp. */
1487 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1488 && f->fx_addsy == l->fixp->fx_addsy
1489 && f->fx_offset == l->fixp->fx_offset
1492 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1493 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1494 || prev->fx_addsy != f->fx_addsy
1495 || prev->fx_offset != f->fx_offset))
1499 /* Move l->fixp before f. */
1500 for (pf = &seginfo->fix_root;
1502 pf = & (* pf)->fx_next)
1503 assert (* pf != NULL);
1505 * pf = l->fixp->fx_next;
1507 l->fixp->fx_next = f;
1509 seginfo->fix_root = l->fixp;
1511 prev->fx_next = l->fixp;
1523 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1524 "Unmatched high/shigh reloc");
1529 /* See whether we need to force a relocation into the output file.
1530 This is used to force out switch and PC relative relocations when
1534 m32r_force_relocation (fix)
1540 return (fix->fx_pcrel
1544 /* Write a value out to the object file, using the appropriate endianness. */
1547 md_number_to_chars (buf, val, n)
1552 if (target_big_endian)
1553 number_to_chars_bigendian (buf, val, n);
1555 number_to_chars_littleendian (buf, val, n);
1558 /* Turn a string in input_line_pointer into a floating point constant of type
1559 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1560 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1563 /* Equal to MAX_PRECISION in atof-ieee.c */
1564 #define MAX_LITTLENUMS 6
1567 md_atof (type, litP, sizeP)
1574 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1575 LITTLENUM_TYPE * wordP;
1577 char * atof_ieee ();
1595 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1599 return "Bad call to md_atof()";
1602 t = atof_ieee (input_line_pointer, type, words);
1604 input_line_pointer = t;
1605 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1607 if (target_big_endian)
1609 for (i = 0; i < prec; i++)
1611 md_number_to_chars (litP, (valueT) words[i],
1612 sizeof (LITTLENUM_TYPE));
1613 litP += sizeof (LITTLENUM_TYPE);
1618 for (i = prec - 1; i >= 0; i--)
1620 md_number_to_chars (litP, (valueT) words[i],
1621 sizeof (LITTLENUM_TYPE));
1622 litP += sizeof (LITTLENUM_TYPE);