1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 /* Linked list of symbols that are debugging symbols to be defined as the
30 beginning of the current instruction. */
31 typedef struct sym_link
33 struct sym_link *next;
37 static sym_linkS *debug_sym_link = (sym_linkS *)0;
39 /* Structure to hold all of the different components describing
40 an individual instruction. */
43 const CGEN_INSN * insn;
44 const CGEN_INSN * orig_insn;
47 CGEN_INSN_INT buffer [1];
48 #define INSN_VALUE(buf) (*(buf))
50 unsigned char buffer [CGEN_MAX_INSN_SIZE];
51 #define INSN_VALUE(buf) (buf)
56 fixS * fixups [GAS_CGEN_MAX_FIXUPS];
57 int indices [MAX_OPERAND_INSTANCES];
58 sym_linkS *debug_sym_link;
62 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
63 boundary (i.e. was the first of two 16 bit insns). */
64 static m32r_insn prev_insn;
66 /* Non-zero if we've seen a relaxable insn since the last 32 bit
68 static int seen_relaxable_p = 0;
70 /* Non-zero if -relax specified, in which case sufficient relocs are output
71 for the linker to do relaxing.
72 We do simple forms of relaxing internally, but they are always done.
73 This flag does not apply to them. */
74 static int m32r_relax;
76 #if 0 /* not supported yet */
77 /* If non-NULL, pointer to cpu description file to read.
78 This allows runtime additions to the assembler. */
79 static const char * m32r_cpu_desc;
82 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
83 Each high/shigh reloc must be paired with it's low cousin in order to
84 properly calculate the addend in a relocatable link (since there is a
85 potential carry from the low to the high/shigh).
86 This option is off by default though for user-written assembler code it
87 might make sense to make the default be on (i.e. have gcc pass a flag
88 to turn it off). This warning must not be on for GCC created code as
89 optimization may delete the low but not the high/shigh (at least we
90 shouldn't assume or require it to). */
91 static int warn_unmatched_high = 0;
93 /* start-sanitize-m32rx */
94 /* Non-zero if -m32rx has been specified, in which case support for the
95 extended M32RX instruction set should be enabled. */
96 static int enable_m32rx = 0;
98 /* Non-zero if -m32rx -hidden has been specified, in which case support for
99 the special M32RX instruction set should be enabled. */
100 static int enable_special = 0;
102 /* Non-zero if the programmer should be warned when an explicit parallel
103 instruction might have constraint violations. */
104 static int warn_explicit_parallel_conflicts = 1;
106 /* Non-zero if insns can be made parallel. */
108 /* end-sanitize-m32rx */
110 /* stuff for .scomm symbols. */
111 static segT sbss_section;
112 static asection scom_section;
113 static asymbol scom_symbol;
115 const char comment_chars[] = ";";
116 const char line_comment_chars[] = "#";
117 const char line_separator_chars[] = "";
118 const char EXP_CHARS[] = "eE";
119 const char FLT_CHARS[] = "dD";
121 /* Relocations against symbols are done in two
122 parts, with a HI relocation and a LO relocation. Each relocation
123 has only 16 bits of space to store an addend. This means that in
124 order for the linker to handle carries correctly, it must be able
125 to locate both the HI and the LO relocation. This means that the
126 relocations must appear in order in the relocation table.
128 In order to implement this, we keep track of each unmatched HI
129 relocation. We then sort them so that they immediately precede the
130 corresponding LO relocation. */
134 struct m32r_hi_fixup * next; /* Next HI fixup. */
135 fixS * fixp; /* This fixup. */
136 segT seg; /* The section this fixup is in. */
140 /* The list of unmatched HI relocs. */
142 static struct m32r_hi_fixup * m32r_hi_fixup_list;
145 /* start-sanitize-m32rx */
152 if (stdoutput != NULL)
153 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
154 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
156 /* end-sanitize-m32rx */
158 #define M32R_SHORTOPTS ""
159 /* start-sanitize-m32rx */
160 #undef M32R_SHORTOPTS
161 #define M32R_SHORTOPTS "O"
162 /* end-sanitize-m32rx */
163 const char * md_shortopts = M32R_SHORTOPTS;
165 struct option md_longopts[] =
167 /* start-sanitize-m32rx */
168 #define OPTION_M32RX (OPTION_MD_BASE)
169 {"m32rx", no_argument, NULL, OPTION_M32RX},
170 #define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
171 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
172 {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
173 #define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2)
174 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
175 {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
176 #define OPTION_SPECIAL (OPTION_MD_BASE + 3)
177 {"hidden", no_argument, NULL, OPTION_SPECIAL},
178 /* end-sanitize-m32rx */
180 /* Sigh. I guess all warnings must now have both variants. */
181 #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
182 {"warn-unmatched-high", OPTION_WARN_UNMATCHED},
183 {"Wuh", OPTION_WARN_UNMATCHED},
184 #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
185 {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED},
186 {"Wnuh", OPTION_WARN_UNMATCHED},
188 #if 0 /* not supported yet */
189 #define OPTION_RELAX (OPTION_MD_BASE + 6)
190 {"relax", no_argument, NULL, OPTION_RELAX},
191 #define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
192 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
195 {NULL, no_argument, NULL, 0}
197 size_t md_longopts_size = sizeof (md_longopts);
200 md_parse_option (c, arg)
206 /* start-sanitize-m32rx */
215 case OPTION_WARN_PARALLEL:
216 warn_explicit_parallel_conflicts = 1;
219 case OPTION_NO_WARN_PARALLEL:
220 warn_explicit_parallel_conflicts = 0;
228 extern char * myname;
230 /* Pretend that we do not recognise this option. */
231 fprintf (stderr, _("%s: unrecognised option: -hidden\n"), myname);
235 /* end-sanitize-m32rx */
237 case OPTION_WARN_UNMATCHED:
238 warn_unmatched_high = 1;
241 case OPTION_NO_WARN_UNMATCHED:
242 warn_unmatched_high = 0;
245 #if 0 /* not supported yet */
249 case OPTION_CPU_DESC:
261 md_show_usage (stream)
264 fprintf (stream, _(" M32R specific command line options:\n"));
266 /* start-sanitize-m32rx */
267 fprintf (stream, _("\
268 -m32rx support the extended m32rx instruction set\n"));
269 fprintf (stream, _("\
270 -O try to combine instructions in parallel\n"));
272 fprintf (stream, _("\
273 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
274 fprintf (stream, _("\
275 violate contraints\n"));
276 fprintf (stream, _("\
277 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
278 fprintf (stream, _("\
279 instructions violate contraints\n"));
280 fprintf (stream, _("\
281 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
282 fprintf (stream, _("\
283 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
284 /* end-sanitize-m32rx */
286 fprintf (stream, _("\
287 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
288 fprintf (stream, _("\
289 -no-warn-unmatched-high do not warn about missing low relocs\n"));
290 fprintf (stream, _("\
291 -Wuh synonym for -warn-unmatched-high\n"));
292 fprintf (stream, _("\
293 -Wnuh synonym for -no-warn-unmatched-high\n"));
296 fprintf (stream, _("\
297 -relax create linker relaxable code\n"));
298 fprintf (stream, _("\
299 -cpu-desc provide runtime cpu description file\n"));
303 static void fill_insn PARAMS ((int));
304 static void m32r_scomm PARAMS ((int));
305 static void debug_sym PARAMS ((int));
306 static void expand_debug_syms PARAMS ((sym_linkS *, int));
308 /* Set by md_assemble for use by m32r_fill_insn. */
309 static subsegT prev_subseg;
310 static segT prev_seg;
312 /* The target specific pseudo-ops which we support. */
313 const pseudo_typeS md_pseudo_table[] =
316 { "fillinsn", fill_insn, 0 },
317 { "scomm", m32r_scomm, 0 },
318 { "debugsym", debug_sym, 0 },
319 /* start-sanitize-m32rx */
320 /* Not documented as so far there is no need for them.... */
321 { "m32r", allow_m32rx, 0 },
322 { "m32rx", allow_m32rx, 1 },
323 /* end-sanitize-m32rx */
327 /* FIXME: Should be machine generated. */
328 #define NOP_INSN 0x7000
329 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
331 /* When we align the .text section, insert the correct NOP pattern.
332 N is the power of 2 alignment. LEN is the length of pattern FILL.
333 MAX is the maximum number of characters to skip when doing the alignment,
334 or 0 if there is no maximum. */
337 m32r_do_align (n, fill, len, max)
343 /* Only do this if the fill pattern wasn't specified. */
345 && (now_seg->flags & SEC_CODE) != 0
346 /* Only do this special handling if aligning to at least a
349 /* Only do this special handling if we're allowed to emit at
351 && (max == 0 || max > 1))
353 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
356 /* First align to a 2 byte boundary, in case there is an odd .byte. */
357 /* FIXME: How much memory will cause gas to use when assembling a big
358 program? Perhaps we can avoid the frag_align call? */
359 frag_align (1, 0, 0);
361 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
363 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
364 /* If doing larger alignments use a repeating sequence of appropriate
368 static const unsigned char multi_nop_pattern[] =
369 { 0x70, 0x00, 0xf0, 0x00 };
370 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
374 prev_insn.insn = NULL;
381 /* If the last instruction was the first of 2 16 bit insns,
382 output a nop to move the PC to a 32 bit boundary.
384 This is done via an alignment specification since branch relaxing
385 may make it unnecessary.
387 Internally, we need to output one of these each time a 32 bit insn is
388 seen after an insn that is relaxable. */
394 (void) m32r_do_align (2, NULL, 0, 0);
395 prev_insn.insn = NULL;
396 seen_relaxable_p = 0;
399 /* Record the symbol so that when we output the insn, we can create
400 a symbol that is at the start of the instruction. This is used
401 to emit the label for the start of a breakpoint without causing
402 the assembler to emit a NOP if the previous instruction was a
403 16 bit instruction. */
411 register char *end_name;
412 register symbolS *symbolP;
413 register sym_linkS *link;
415 name = input_line_pointer;
416 delim = get_symbol_end ();
417 end_name = input_line_pointer;
419 if ((symbolP = symbol_find (name)) == NULL
420 && (symbolP = md_undefined_symbol (name)) == NULL)
422 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
425 symbol_table_insert (symbolP);
426 if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section)
427 /* xgettext:c-format */
428 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
432 link = (sym_linkS *) xmalloc (sizeof (sym_linkS));
433 link->symbol = symbolP;
434 link->next = debug_sym_link;
435 debug_sym_link = link;
440 demand_empty_rest_of_line ();
443 /* Second pass to expanding the debug symbols, go through linked
444 list of symbols and reassign the address. */
447 expand_debug_syms (syms, align)
451 char *save_input_line = input_line_pointer;
452 sym_linkS *next_syms;
457 (void) m32r_do_align (align, NULL, 0, 0);
458 for (; syms != (sym_linkS *)0; syms = next_syms)
460 symbolS *symbolP = syms->symbol;
461 next_syms = syms->next;
462 input_line_pointer = ".\n";
463 pseudo_set (symbolP);
467 input_line_pointer = save_input_line;
470 /* Cover function to fill_insn called after a label and at end of assembly.
471 The result is always 1: we're called in a conditional to see if the
472 current line is a label. */
475 m32r_fill_insn (done)
478 if (prev_seg != NULL)
481 subsegT subseg = now_subseg;
483 subseg_set (prev_seg, prev_subseg);
487 subseg_set (seg, subseg);
490 if (done && debug_sym_link)
492 expand_debug_syms (debug_sym_link, 1);
493 debug_sym_link = (sym_linkS *)0;
506 /* Initialize the `cgen' interface. */
508 /* Set the machine number and endian. */
509 gas_cgen_opcode_desc = m32r_cgen_opcode_open (0 /* mach number */,
512 : CGEN_ENDIAN_LITTLE);
513 m32r_cgen_init_asm (gas_cgen_opcode_desc);
515 /* This is a callback from cgen to gas to parse operands. */
516 cgen_set_parse_operand_fn (gas_cgen_opcode_desc, gas_cgen_parse_operand);
518 #if 0 /* not supported yet */
519 /* If a runtime cpu description file was provided, parse it. */
520 if (m32r_cpu_desc != NULL)
524 errmsg = cgen_read_cpu_file (gas_cgen_opcode_desc, m32r_cpu_desc);
526 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
530 /* Save the current subseg so we can restore it [it's the default one and
531 we don't want the initial section to be .sbss]. */
535 /* The sbss section is for local .scomm symbols. */
536 sbss_section = subseg_new (".sbss", 0);
538 /* This is copied from perform_an_assembly_pass. */
539 applicable = bfd_applicable_section_flags (stdoutput);
540 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
542 #if 0 /* What does this do? [see perform_an_assembly_pass] */
543 seg_info (bss_section)->bss = 1;
546 subseg_set (seg, subseg);
548 /* We must construct a fake section similar to bfd_com_section
549 but with the name .scommon. */
550 scom_section = bfd_com_section;
551 scom_section.name = ".scommon";
552 scom_section.output_section = & scom_section;
553 scom_section.symbol = & scom_symbol;
554 scom_section.symbol_ptr_ptr = & scom_section.symbol;
555 scom_symbol = * bfd_com_section.symbol;
556 scom_symbol.name = ".scommon";
557 scom_symbol.section = & scom_section;
559 /* start-sanitize-m32rx */
560 allow_m32rx (enable_m32rx);
561 /* end-sanitize-m32rx */
564 /* start-sanitize-m32rx */
566 #define OPERAND_IS_COND_BIT(operand, indices, index) \
567 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
568 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_PSW) \
569 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
570 && (indices [index] == 0 || indices [index] == 1)))
572 /* Returns true if an output of instruction 'a' is referenced by an operand
573 of instruction 'b'. If 'check_outputs' is true then b's outputs are
574 checked, otherwise its inputs are examined. */
577 first_writes_to_seconds_operands (a, b, check_outputs)
580 const int check_outputs;
582 const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn);
583 const CGEN_OPERAND_INSTANCE * b_ops = CGEN_INSN_OPERANDS (b->insn);
586 /* If at least one of the instructions takes no operands, then there is
587 nothing to check. There really are instructions without operands,
589 if (a_operands == NULL || b_ops == NULL)
592 /* Scan the operand list of 'a' looking for an output operand. */
594 CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
595 a_index ++, a_operands ++)
597 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT)
600 const CGEN_OPERAND_INSTANCE * b_operands = b_ops;
603 The Condition bit 'C' is a shadow of the CBR register (control
604 register 1) and also a shadow of bit 31 of the program status
605 word (control register 0). For now this is handled here, rather
608 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
610 /* Scan operand list of 'b' looking for another reference to the
611 condition bit, which goes in the right direction. */
613 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
614 b_index ++, b_operands ++)
616 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
617 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
618 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
624 /* Scan operand list of 'b' looking for an operand that
625 references the same hardware element, and which goes in the
628 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
629 b_index ++, b_operands ++)
631 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
632 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
633 && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands))
634 && (a->indices [a_index] == b->indices [b_index]))
644 /* Returns true if the insn can (potentially) alter the program counter. */
650 #if 0 /* Once PC operands are working.... */
651 const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn);
653 if (a_operands == NULL)
656 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END)
658 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL
659 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
665 if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
666 || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
672 /* Returns NULL if the two 16 bit insns can be executed in parallel,
673 otherwise it returns a pointer to an error message explaining why not. */
676 can_make_parallel (a, b)
683 /* Make sure the instructions are the right length. */
684 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
685 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
688 if (first_writes_to_seconds_operands (a, b, true))
689 return _("Instructions write to the same destination register.");
691 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
692 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
694 /* Make sure that the instructions use the correct execution pipelines. */
695 if ( a_pipe == PIPE_NONE
696 || b_pipe == PIPE_NONE)
697 return _("Instructions do not use parallel execution pipelines.");
699 /* Leave this test for last, since it is the only test that can
700 go away if the instructions are swapped, and we want to make
701 sure that any other errors are detected before this happens. */
702 if ( a_pipe == PIPE_S
704 return _("Instructions share the same execution pipeline");
709 /* Force the top bit of the second 16-bit insn to be set. */
712 make_parallel (buffer)
713 CGEN_INSN_BYTES_PTR buffer;
718 buffer [CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
723 /* Same as make_parallel except buffer contains the bytes in target order. */
726 target_make_parallel (buffer)
729 buffer [CGEN_OPCODE_ENDIAN (gas_cgen_opcode_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
733 /* Assemble two instructions with an explicit parallel operation (||) or
734 sequential operation (->). */
737 assemble_two_insns (str, str2, parallel_p)
746 char save_str2 = *str2;
748 * str2 = 0; /* Seperate the two instructions. */
750 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
751 so that the parallel instruction will start on a 32 bit boundary.
752 This is also done for the serial case (foo -> bar), relaxing doesn't
753 affect insns written like this. */
757 first.debug_sym_link = debug_sym_link;
758 debug_sym_link = (sym_linkS *)0;
760 /* Parse the first instruction. */
761 if (! (first.insn = m32r_cgen_assemble_insn
762 (gas_cgen_opcode_desc, str, & first.fields, first.buffer, & errmsg)))
769 if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
771 /* xgettext:c-format */
772 as_bad (_("not a 16 bit instruction '%s'"), str);
775 else if (! enable_special
776 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_SPECIAL))
778 /* xgettext:c-format */
779 as_bad (_("unknown instruction '%s'"), str);
782 else if (! enable_m32rx
783 /* FIXME: Need standard macro to perform this test. */
784 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
786 /* xgettext:c-format */
787 as_bad (_("instruction '%s' is for the M32RX only"), str);
791 /* Check to see if this is an allowable parallel insn. */
792 if (parallel_p && CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
794 /* xgettext:c-format */
795 as_bad (_("instruction '%s' cannot be executed in parallel."), str);
799 *str2 = save_str2; /* Restore the original assembly text, just in case it is needed. */
800 str3 = str; /* Save the original string pointer. */
801 str = str2 + 2; /* Advanced past the parsed string. */
802 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
804 /* Convert the opcode to lower case. */
808 while (isspace (*s2 ++))
813 while (isalnum (*s2))
815 if (isupper ((unsigned char) *s2))
821 /* Preserve any fixups that have been generated and reset the list to empty. */
822 gas_cgen_save_fixups ();
824 /* Get the indices of the operands of the instruction. */
825 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
826 doesn't seem right. Perhaps allow passing fields like we do insn. */
827 /* FIXME: ALIAS insns do not have operands, so we use this function
828 to find the equivalent insn and overwrite the value stored in our
829 structure. We still need the original insn, however, since this
830 may have certain attributes that are not present in the unaliased
831 version (eg relaxability). When aliases behave differently this
832 may have to change. */
833 first.orig_insn = first.insn;
834 first.insn = m32r_cgen_lookup_get_insn_operands
835 (gas_cgen_opcode_desc, NULL, INSN_VALUE (first.buffer), 16,
838 if (first.insn == NULL)
839 as_fatal (_("internal error: lookup/get operands failed"));
841 second.debug_sym_link = NULL;
843 /* Parse the second instruction. */
844 if (! (second.insn = m32r_cgen_assemble_insn
845 (gas_cgen_opcode_desc, str, & second.fields, second.buffer, & errmsg)))
852 if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
854 /* xgettext:c-format */
855 as_bad (_("not a 16 bit instruction '%s'"), str);
858 else if (! enable_special
859 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_SPECIAL))
861 /* xgettext:c-format */
862 as_bad (_("unknown instruction '%s'"), str);
865 else if (! enable_m32rx
866 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
868 /* xgettext:c-format */
869 as_bad (_("instruction '%s' is for the M32RX only"), str);
873 /* Check to see if this is an allowable parallel insn. */
874 if (parallel_p && CGEN_INSN_ATTR (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
876 /* xgettext:c-format */
877 as_bad (_("instruction '%s' cannot be executed in parallel."), str);
881 if (parallel_p && ! enable_m32rx)
883 if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
884 && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
886 /* xgettext:c-format */
887 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
892 /* Get the indices of the operands of the instruction. */
893 second.orig_insn = second.insn;
894 second.insn = m32r_cgen_lookup_get_insn_operands
895 (gas_cgen_opcode_desc, NULL, INSN_VALUE (second.buffer), 16,
898 if (second.insn == NULL)
899 as_fatal (_("internal error: lookup/get operands failed"));
901 /* We assume that if the first instruction writes to a register that is
902 read by the second instruction it is because the programmer intended
903 this to happen, (after all they have explicitly requested that these
904 two instructions be executed in parallel). Although if the global
905 variable warn_explicit_parallel_conflicts is true then we do generate
906 a warning message. Similarly we assume that parallel branch and jump
907 instructions are deliberate and should not produce errors. */
909 if (parallel_p && warn_explicit_parallel_conflicts)
911 if (first_writes_to_seconds_operands (& first, & second, false))
912 /* xgettext:c-format */
913 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
915 if (first_writes_to_seconds_operands (& second, & first, false))
916 /* xgettext:c-format */
917 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
921 || (errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
923 /* Get the fixups for the first instruction. */
924 gas_cgen_swap_fixups ();
927 expand_debug_syms (first.debug_sym_link, 1);
928 gas_cgen_finish_insn (first.orig_insn, first.buffer,
929 CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
931 /* Force the top bit of the second insn to be set. */
933 make_parallel (second.buffer);
935 /* Get its fixups. */
936 gas_cgen_restore_fixups ();
939 expand_debug_syms (second.debug_sym_link, 1);
940 gas_cgen_finish_insn (second.orig_insn, second.buffer,
941 CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
943 /* Try swapping the instructions to see if they work that way. */
944 else if (can_make_parallel (& second, & first) == NULL)
946 /* Write out the second instruction first. */
947 expand_debug_syms (second.debug_sym_link, 1);
948 gas_cgen_finish_insn (second.orig_insn, second.buffer,
949 CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
951 /* Force the top bit of the first instruction to be set. */
952 make_parallel (first.buffer);
954 /* Get the fixups for the first instruction. */
955 gas_cgen_restore_fixups ();
957 /* Write out the first instruction. */
958 expand_debug_syms (first.debug_sym_link, 1);
959 gas_cgen_finish_insn (first.orig_insn, first.buffer,
960 CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
964 as_bad ("'%s': %s", str2, errmsg);
968 /* Set these so m32r_fill_insn can use them. */
970 prev_subseg = now_subseg;
973 /* end-sanitize-m32rx */
984 /* Initialize GAS's cgen interface for a new instruction. */
985 gas_cgen_init_parse ();
987 /* start-sanitize-m32rx */
988 /* Look for a parallel instruction seperator. */
989 if ((str2 = strstr (str, "||")) != NULL)
991 assemble_two_insns (str, str2, 1);
995 /* Also look for a sequential instruction seperator. */
996 if ((str2 = strstr (str, "->")) != NULL)
998 assemble_two_insns (str, str2, 0);
1001 /* end-sanitize-m32rx */
1003 insn.debug_sym_link = debug_sym_link;
1004 debug_sym_link = (sym_linkS *)0;
1006 insn.insn = m32r_cgen_assemble_insn
1007 (gas_cgen_opcode_desc, str, & insn.fields, insn.buffer, & errmsg);
1015 /* start-sanitize-m32rx */
1016 if (! enable_special
1017 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_SPECIAL))
1019 /* xgettext:c-format */
1020 as_bad (_("unknown instruction '%s'"), str);
1023 else if (! enable_m32rx
1024 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
1026 /* xgettext:c-format */
1027 as_bad (_("instruction '%s' is for the M32RX only"), str);
1030 /* end-sanitize-m32rx */
1032 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
1034 /* 32 bit insns must live on 32 bit boundaries. */
1035 if (prev_insn.insn || seen_relaxable_p)
1037 /* ??? If calling fill_insn too many times turns us into a memory
1038 pig, can we call a fn to assemble a nop instead of
1039 !seen_relaxable_p? */
1043 expand_debug_syms (insn.debug_sym_link, 2);
1045 /* Doesn't really matter what we pass for RELAX_P here. */
1046 gas_cgen_finish_insn (insn.insn, insn.buffer,
1047 CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
1051 int on_32bit_boundary_p;
1052 /* start-sanitize-m32rx */
1054 /* end-sanitize-m32rx */
1056 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
1059 insn.orig_insn = insn.insn;
1060 /* start-sanitize-m32rx */
1061 /* If the previous insn was relaxable, then it may be expanded
1062 to fill the current 16 bit slot. Emit a NOP here to occupy
1063 this slot, so that we can start at optimizing at a 32 bit
1065 if (prev_insn.insn && seen_relaxable_p && optimize)
1070 /* Get the indices of the operands of the instruction.
1071 FIXME: See assemble_parallel for notes on orig_insn. */
1072 insn.insn = m32r_cgen_lookup_get_insn_operands
1073 (gas_cgen_opcode_desc, NULL, INSN_VALUE (insn.buffer),
1076 if (insn.insn == NULL)
1077 as_fatal (_("internal error: lookup/get operands failed"));
1079 /* end-sanitize-m32rx */
1081 /* Compute whether we're on a 32 bit boundary or not.
1082 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1083 on_32bit_boundary_p = prev_insn.insn == NULL;
1085 /* start-sanitize-m32rx */
1086 /* Look to see if this instruction can be combined with the
1087 previous instruction to make one, parallel, 32 bit instruction.
1088 If the previous instruction (potentially) changed the flow of
1089 program control, then it cannot be combined with the current
1090 instruction. If the current instruction is relaxable, then it
1091 might be replaced with a longer version, so we cannot combine it.
1092 Also if the output of the previous instruction is used as an
1093 input to the current instruction then it cannot be combined.
1094 Otherwise call can_make_parallel() with both orderings of the
1095 instructions to see if they can be combined. */
1096 if ( ! on_32bit_boundary_p
1099 && CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
1100 && ! writes_to_pc (& prev_insn)
1101 && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
1104 if (can_make_parallel (& prev_insn, & insn) == NULL)
1105 make_parallel (insn.buffer);
1106 else if (can_make_parallel (& insn, & prev_insn) == NULL)
1109 /* end-sanitize-m32rx */
1111 expand_debug_syms (insn.debug_sym_link, 1);
1117 /* Ensure each pair of 16 bit insns is in the same frag. */
1120 gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
1121 CGEN_FIELDS_BITSIZE (& insn.fields),
1122 1 /*relax_p*/, &fi);
1123 insn.addr = fi.addr;
1124 insn.frag = fi.frag;
1125 insn.num_fixups = fi.num_fixups;
1126 for (i = 0; i < fi.num_fixups; ++i)
1127 insn.fixups[i] = fi.fixups[i];
1130 /* start-sanitize-m32rx */
1135 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1137 /* Swap the two insns */
1138 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
1139 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
1141 target_make_parallel (insn.addr);
1143 /* Swap any relaxable frags recorded for the two insns. */
1144 /* FIXME: Clarify. relaxation precludes parallel insns */
1145 if (prev_insn.frag->fr_opcode == prev_insn.addr)
1146 prev_insn.frag->fr_opcode = insn.addr;
1147 else if (insn.frag->fr_opcode == insn.addr)
1148 insn.frag->fr_opcode = prev_insn.addr;
1150 /* Update the addresses in any fixups.
1151 Note that we don't have to handle the case where each insn is in
1152 a different frag as we ensure they're in the same frag above. */
1153 for (i = 0; i < prev_insn.num_fixups; ++i)
1154 prev_insn.fixups[i]->fx_where += 2;
1155 for (i = 0; i < insn.num_fixups; ++i)
1156 insn.fixups[i]->fx_where -= 2;
1158 /* end-sanitize-m32rx */
1160 /* Keep track of whether we've seen a pair of 16 bit insns.
1161 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1162 if (on_32bit_boundary_p)
1165 prev_insn.insn = NULL;
1167 /* If the insn needs the following one to be on a 32 bit boundary
1168 (e.g. subroutine calls), fill this insn's slot. */
1169 if (on_32bit_boundary_p
1170 && CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
1173 /* If this is a relaxable insn (can be replaced with a larger version)
1174 mark the fact so that we can emit an alignment directive for a
1175 following 32 bit insn if we see one. */
1176 if (CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
1177 seen_relaxable_p = 1;
1180 /* Set these so m32r_fill_insn can use them. */
1182 prev_subseg = now_subseg;
1185 /* The syntax in the manual says constants begin with '#'.
1186 We just ignore it. */
1189 md_operand (expressionP)
1190 expressionS * expressionP;
1192 if (* input_line_pointer == '#')
1194 input_line_pointer ++;
1195 expression (expressionP);
1200 md_section_align (segment, size)
1204 int align = bfd_get_section_alignment (stdoutput, segment);
1205 return ((size + (1 << align) - 1) & (-1 << align));
1209 md_undefined_symbol (name)
1215 /* .scomm pseudo-op handler.
1217 This is a new pseudo-op to handle putting objects in .scommon.
1218 By doing this the linker won't need to do any work and more importantly
1219 it removes the implicit -G arg necessary to correctly link the object file.
1226 register char * name;
1230 register symbolS * symbolP;
1234 name = input_line_pointer;
1235 c = get_symbol_end ();
1237 /* just after name is now '\0' */
1238 p = input_line_pointer;
1241 if (* input_line_pointer != ',')
1243 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1244 ignore_rest_of_line ();
1248 input_line_pointer ++; /* skip ',' */
1249 if ((size = get_absolute_expression ()) < 0)
1251 /* xgettext:c-format */
1252 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
1253 ignore_rest_of_line ();
1257 /* The third argument to .scomm is the alignment. */
1258 if (* input_line_pointer != ',')
1262 ++ input_line_pointer;
1263 align = get_absolute_expression ();
1266 as_warn (_("ignoring bad alignment"));
1270 /* Convert to a power of 2 alignment. */
1273 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
1277 as_bad (_("Common alignment not a power of 2"));
1278 ignore_rest_of_line ();
1286 symbolP = symbol_find_or_make (name);
1289 if (S_IS_DEFINED (symbolP))
1291 /* xgettext:c-format */
1292 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1293 S_GET_NAME (symbolP));
1294 ignore_rest_of_line ();
1298 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
1300 /* xgettext:c-format */
1301 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1302 S_GET_NAME (symbolP),
1303 (long) S_GET_VALUE (symbolP),
1306 ignore_rest_of_line ();
1312 segT old_sec = now_seg;
1313 int old_subsec = now_subseg;
1316 record_alignment (sbss_section, align2);
1317 subseg_set (sbss_section, 0);
1320 frag_align (align2, 0, 0);
1322 if (S_GET_SEGMENT (symbolP) == sbss_section)
1323 symbolP->sy_frag->fr_symbol = 0;
1325 symbolP->sy_frag = frag_now;
1327 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
1330 S_SET_SIZE (symbolP, size);
1331 S_SET_SEGMENT (symbolP, sbss_section);
1332 S_CLEAR_EXTERNAL (symbolP);
1333 subseg_set (old_sec, old_subsec);
1337 S_SET_VALUE (symbolP, (valueT) size);
1338 S_SET_ALIGN (symbolP, align2);
1339 S_SET_EXTERNAL (symbolP);
1340 S_SET_SEGMENT (symbolP, & scom_section);
1343 demand_empty_rest_of_line ();
1346 /* Interface to relax_segment. */
1348 /* FIXME: Build table by hand, get it working, then machine generate. */
1350 const relax_typeS md_relax_table[] =
1353 1) most positive reach of this state,
1354 2) most negative reach of this state,
1355 3) how many bytes this mode will add to the size of the current frag
1356 4) which index into the table to try if we can't fit into this one. */
1358 /* The first entry must be unused because an `rlx_more' value of zero ends
1362 /* The displacement used by GAS is from the end of the 2 byte insn,
1363 so we subtract 2 from the following. */
1364 /* 16 bit insn, 8 bit disp -> 10 bit range.
1365 This doesn't handle a branch in the right slot at the border:
1366 the "& -4" isn't taken into account. It's not important enough to
1367 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1369 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1370 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1371 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1372 /* Same thing, but with leading nop for alignment. */
1373 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1377 m32r_relax_frag (fragP, stretch)
1381 /* Address of branch insn. */
1382 long address = fragP->fr_address + fragP->fr_fix - 2;
1385 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1386 if (fragP->fr_subtype == 2)
1388 if ((address & 3) != 0)
1390 fragP->fr_subtype = 3;
1394 else if (fragP->fr_subtype == 3)
1396 if ((address & 3) == 0)
1398 fragP->fr_subtype = 2;
1404 growth = relax_frag (fragP, stretch);
1406 /* Long jump on odd halfword boundary? */
1407 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1409 fragP->fr_subtype = 3;
1417 /* Return an initial guess of the length by which a fragment must grow to
1418 hold a branch to reach its destination.
1419 Also updates fr_type/fr_subtype as necessary.
1421 Called just before doing relaxation.
1422 Any symbol that is now undefined will not become defined.
1423 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1424 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1425 Although it may not be explicit in the frag, pretend fr_var starts with a
1429 md_estimate_size_before_relax (fragP, segment)
1433 int old_fr_fix = fragP->fr_fix;
1435 /* The only thing we have to handle here are symbols outside of the
1436 current segment. They may be undefined or in a different segment in
1437 which case linker scripts may place them anywhere.
1438 However, we can't finish the fragment here and emit the reloc as insn
1439 alignment requirements may move the insn about. */
1441 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1443 /* The symbol is undefined in this segment.
1444 Change the relaxation subtype to the max allowable and leave
1445 all further handling to md_convert_frag. */
1446 fragP->fr_subtype = 2;
1448 #if 0 /* Can't use this, but leave in for illustration. */
1449 /* Change 16 bit insn to 32 bit insn. */
1450 fragP->fr_opcode[0] |= 0x80;
1452 /* Increase known (fixed) size of fragment. */
1455 /* Create a relocation for it. */
1456 fix_new (fragP, old_fr_fix, 4,
1458 fragP->fr_offset, 1 /* pcrel */,
1459 /* FIXME: Can't use a real BFD reloc here.
1460 gas_cgen_md_apply_fix3 can't handle it. */
1461 BFD_RELOC_M32R_26_PCREL);
1463 /* Mark this fragment as finished. */
1467 const CGEN_INSN * insn;
1470 /* Update the recorded insn.
1471 Fortunately we don't have to look very far.
1472 FIXME: Change this to record in the instruction the next higher
1473 relaxable insn to use. */
1474 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1476 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1477 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1479 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1485 fragP->fr_cgen.insn = insn;
1491 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1494 /* *fragP has been relaxed to its final size, and now needs to have
1495 the bytes inside it modified to conform to the new size.
1497 Called after relaxation is finished.
1498 fragP->fr_type == rs_machine_dependent.
1499 fragP->fr_subtype is the subtype of what the address relaxed to. */
1502 md_convert_frag (abfd, sec, fragP)
1508 char * displacement;
1514 opcode = fragP->fr_opcode;
1516 /* Address opcode resides at in file space. */
1517 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1519 switch (fragP->fr_subtype)
1523 displacement = & opcode[1];
1528 displacement = & opcode[1];
1531 opcode[2] = opcode[0] | 0x80;
1532 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1533 opcode_address += 2;
1535 displacement = & opcode[3];
1541 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1543 /* symbol must be resolved by linker */
1544 if (fragP->fr_offset & 3)
1545 as_warn (_("Addend to unresolved symbol not on word boundary."));
1546 addend = fragP->fr_offset >> 2;
1550 /* Address we want to reach in file space. */
1551 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1552 target_address += fragP->fr_symbol->sy_frag->fr_address;
1553 addend = (target_address - (opcode_address & -4)) >> 2;
1556 /* Create a relocation for symbols that must be resolved by the linker.
1557 Otherwise output the completed insn. */
1559 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1561 assert (fragP->fr_subtype != 1);
1562 assert (fragP->fr_cgen.insn != 0);
1563 gas_cgen_record_fixup (fragP,
1564 /* Offset of branch insn in frag. */
1565 fragP->fr_fix + extension - 4,
1566 fragP->fr_cgen.insn,
1568 /* FIXME: quick hack */
1570 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1572 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1574 fragP->fr_cgen.opinfo,
1575 fragP->fr_symbol, fragP->fr_offset);
1578 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1580 md_number_to_chars (displacement, (valueT) addend,
1581 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1583 fragP->fr_fix += extension;
1586 /* Functions concerning relocs. */
1588 /* The location from which a PC relative jump should be calculated,
1589 given a PC relative reloc. */
1592 md_pcrel_from_section (fixP, sec)
1596 if (fixP->fx_addsy != (symbolS *) NULL
1597 && (! S_IS_DEFINED (fixP->fx_addsy)
1598 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1600 /* The symbol is undefined (or is defined but not in this section).
1601 Let the linker figure it out. */
1605 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1608 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1609 Returns BFD_RELOC_NONE if no reloc type can be found.
1610 *FIXP may be modified if desired. */
1612 bfd_reloc_code_real_type
1613 md_cgen_lookup_reloc (insn, operand, fixP)
1614 const CGEN_INSN * insn;
1615 const CGEN_OPERAND * operand;
1618 switch (CGEN_OPERAND_TYPE (operand))
1620 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1621 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1622 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1623 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1624 case M32R_OPERAND_HI16 :
1625 case M32R_OPERAND_SLO16 :
1626 case M32R_OPERAND_ULO16 :
1627 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1628 if (fixP->tc_fix_data.opinfo != 0)
1629 return fixP->tc_fix_data.opinfo;
1631 default : /* avoid -Wall warning */
1634 return BFD_RELOC_NONE;
1637 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1640 m32r_record_hi16 (reloc_type, fixP, seg)
1645 struct m32r_hi_fixup * hi_fixup;
1647 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1648 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1650 hi_fixup = ((struct m32r_hi_fixup *)
1651 xmalloc (sizeof (struct m32r_hi_fixup)));
1652 hi_fixup->fixp = fixP;
1653 hi_fixup->seg = now_seg;
1654 hi_fixup->next = m32r_hi_fixup_list;
1656 m32r_hi_fixup_list = hi_fixup;
1659 /* Called while parsing an instruction to create a fixup.
1660 We need to check for HI16 relocs and queue them up for later sorting. */
1663 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1666 const CGEN_INSN * insn;
1668 const CGEN_OPERAND * operand;
1672 fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
1673 operand, opinfo, exp);
1675 switch (CGEN_OPERAND_TYPE (operand))
1677 case M32R_OPERAND_HI16 :
1678 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1679 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1680 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1681 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1683 default : /* avoid -Wall warning */
1690 /* Return BFD reloc type from opinfo field in a fixS.
1691 It's tricky using fx_r_type in m32r_frob_file because the values
1692 are BFD_RELOC_UNUSED + operand number. */
1693 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1695 /* Sort any unmatched HI16 relocs so that they immediately precede
1696 the corresponding LO16 reloc. This is called before md_apply_fix and
1702 struct m32r_hi_fixup * l;
1704 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1706 segment_info_type * seginfo;
1709 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1710 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1712 /* Check quickly whether the next fixup happens to be a matching low. */
1713 if (l->fixp->fx_next != NULL
1714 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1715 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1716 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1719 /* Look through the fixups for this segment for a matching `low'.
1720 When we find one, move the high/shigh just in front of it. We do
1721 this in two passes. In the first pass, we try to find a
1722 unique `low'. In the second pass, we permit multiple high's
1723 relocs for a single `low'. */
1724 seginfo = seg_info (l->seg);
1725 for (pass = 0; pass < 2; pass++)
1731 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1733 /* Check whether this is a `low' fixup which matches l->fixp. */
1734 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1735 && f->fx_addsy == l->fixp->fx_addsy
1736 && f->fx_offset == l->fixp->fx_offset
1739 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1740 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1741 || prev->fx_addsy != f->fx_addsy
1742 || prev->fx_offset != f->fx_offset))
1746 /* Move l->fixp before f. */
1747 for (pf = &seginfo->fix_root;
1749 pf = & (* pf)->fx_next)
1750 assert (* pf != NULL);
1752 * pf = l->fixp->fx_next;
1754 l->fixp->fx_next = f;
1756 seginfo->fix_root = l->fixp;
1758 prev->fx_next = l->fixp;
1770 && warn_unmatched_high)
1771 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1772 _("Unmatched high/shigh reloc"));
1777 /* See whether we need to force a relocation into the output file.
1778 This is used to force out switch and PC relative relocations when
1782 m32r_force_relocation (fix)
1785 if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1786 || fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1792 return (fix->fx_pcrel
1796 /* Write a value out to the object file, using the appropriate endianness. */
1799 md_number_to_chars (buf, val, n)
1804 if (target_big_endian)
1805 number_to_chars_bigendian (buf, val, n);
1807 number_to_chars_littleendian (buf, val, n);
1810 /* Turn a string in input_line_pointer into a floating point constant of type
1811 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1812 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1815 /* Equal to MAX_PRECISION in atof-ieee.c */
1816 #define MAX_LITTLENUMS 6
1819 md_atof (type, litP, sizeP)
1826 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1828 char * atof_ieee ();
1846 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1850 return _("Bad call to md_atof()");
1853 t = atof_ieee (input_line_pointer, type, words);
1855 input_line_pointer = t;
1856 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1858 if (target_big_endian)
1860 for (i = 0; i < prec; i++)
1862 md_number_to_chars (litP, (valueT) words[i],
1863 sizeof (LITTLENUM_TYPE));
1864 litP += sizeof (LITTLENUM_TYPE);
1869 for (i = prec - 1; i >= 0; i--)
1871 md_number_to_chars (litP, (valueT) words[i],
1872 sizeof (LITTLENUM_TYPE));
1873 litP += sizeof (LITTLENUM_TYPE);
1881 m32r_elf_section_change_hook ()
1883 /* If we have reached the end of a section and we have just emitted a
1884 16 bit insn, then emit a nop to make sure that the section ends on
1885 a 32 bit boundary. */
1887 if (prev_insn.insn || seen_relaxable_p)
1888 (void) m32r_fill_insn (0);
1892 m32r_fix_adjustable (fixP)
1896 if (fixP->fx_addsy == NULL)
1899 /* Prevent all adjustments to global symbols. */
1900 if (S_IS_EXTERN (fixP->fx_addsy))
1902 if (S_IS_WEAK (fixP->fx_addsy))
1905 /* We need the symbol name for the VTABLE entries */
1906 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1907 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)