1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 const CGEN_INSN * insn;
32 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
34 char buffer [CGEN_MAX_INSN_SIZE];
41 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
42 boundary (i.e. was the first of two 16 bit insns). */
43 static m32r_insn prev_insn;
45 /* Non-zero if we've seen a relaxable insn since the last 32 bit
47 static int seen_relaxable_p = 0;
49 /* Non-zero if -relax specified, in which case sufficient relocs are output
50 for the linker to do relaxing.
51 We do simple forms of relaxing internally, but they are always done.
52 This flag does not apply to them. */
53 static int m32r_relax;
55 /* If non-NULL, pointer to cpu description file to read.
56 This allows runtime additions to the assembler. */
57 static char * m32r_cpu_desc;
59 /* start-sanitize-m32rx */
60 /* Non-zero if -m32rx has been specified, in which case support for the
61 extended M32RX instruction set should be enabled. */
62 static int enable_m32rx = 0;
64 /* Non-zero if the programmer should be warned when an explicit parallel
65 instruction might have constraint violations. */
66 static int warn_explicit_parallel_conflicts = 1;
67 /* end-sanitize-m32rx */
69 /* stuff for .scomm symbols. */
70 static segT sbss_section;
71 static asection scom_section;
72 static asymbol scom_symbol;
74 const char comment_chars[] = ";";
75 const char line_comment_chars[] = "#";
76 const char line_separator_chars[] = "";
77 const char EXP_CHARS[] = "eE";
78 const char FLT_CHARS[] = "dD";
80 /* Relocations against symbols are done in two
81 parts, with a HI relocation and a LO relocation. Each relocation
82 has only 16 bits of space to store an addend. This means that in
83 order for the linker to handle carries correctly, it must be able
84 to locate both the HI and the LO relocation. This means that the
85 relocations must appear in order in the relocation table.
87 In order to implement this, we keep track of each unmatched HI
88 relocation. We then sort them so that they immediately precede the
89 corresponding LO relocation. */
93 struct m32r_hi_fixup * next; /* Next HI fixup. */
94 fixS * fixp; /* This fixup. */
95 segT seg; /* The section this fixup is in. */
99 /* The list of unmatched HI relocs. */
101 static struct m32r_hi_fixup * m32r_hi_fixup_list;
104 /* start-sanitize-m32rx */
110 if (stdoutput != NULL)
111 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
112 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
114 /* end-sanitize-m32rx */
116 const char * md_shortopts = "";
118 struct option md_longopts[] =
120 /* start-sanitize-m32rx */
121 #define OPTION_M32RX (OPTION_MD_BASE)
122 {"m32rx", no_argument, NULL, OPTION_M32RX},
123 #define OPTION_WARN (OPTION_MD_BASE + 1)
124 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN},
125 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
126 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
127 /* end-sanitize-m32rx */
129 #if 0 /* not supported yet */
130 #define OPTION_RELAX (OPTION_MD_BASE + 3)
131 {"relax", no_argument, NULL, OPTION_RELAX},
132 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
133 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
136 {NULL, no_argument, NULL, 0}
138 size_t md_longopts_size = sizeof (md_longopts);
141 md_parse_option (c, arg)
147 /* start-sanitize-m32rx */
153 warn_explicit_parallel_conflicts = 1;
157 warn_explicit_parallel_conflicts = 0;
159 /* end-sanitize-m32rx */
161 #if 0 /* not supported yet */
165 case OPTION_CPU_DESC:
176 md_show_usage (stream)
179 fprintf (stream, "M32R/X options:\n");
180 /* start-sanitize-m32rx */
182 --m32rx support the extended m32rx instruction set\n");
185 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\
186 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
187 /* end-sanitize-m32rx */
191 --relax create linker relaxable code\n");
193 --cpu-desc provide runtime cpu description file\n");
197 static void fill_insn PARAMS ((int));
198 static void m32r_scomm PARAMS ((int));
200 /* Set by md_assemble for use by m32r_fill_insn. */
201 static subsegT prev_subseg;
202 static segT prev_seg;
204 /* The target specific pseudo-ops which we support. */
205 const pseudo_typeS md_pseudo_table[] =
208 { "fillinsn", fill_insn, 0 },
209 { "scomm", m32r_scomm, 0 },
210 /* start-sanitize-m32rx */
211 { "m32r", allow_m32rx, 0},
212 { "m32rx", allow_m32rx, 1},
213 /* end-sanitize-m32rx */
217 /* FIXME: Should be machine generated. */
218 #define NOP_INSN 0x7000
219 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
221 /* When we align the .text section, insert the correct NOP pattern.
222 N is the power of 2 alignment. LEN is the length of pattern FILL.
223 MAX is the maximum number of characters to skip when doing the alignment,
224 or 0 if there is no maximum. */
227 m32r_do_align (n, fill, len, max)
233 if ((fill == NULL || (* fill == 0 && len == 1))
234 && (now_seg->flags & SEC_CODE) != 0
235 /* Only do this special handling if aligning to at least a
238 /* Only do this special handling if we're allowed to emit at
240 && (max == 0 || max > 1))
242 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
245 /* First align to a 2 byte boundary, in case there is an odd .byte. */
246 /* FIXME: How much memory will cause gas to use when assembling a big
247 program? Perhaps we can avoid the frag_align call? */
248 frag_align (1, 0, 0);
250 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
252 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
253 /* If doing larger alignments use a repeating sequence of appropriate
257 static const unsigned char multi_nop_pattern[] =
258 { 0x70, 0x00, 0xf0, 0x00 };
259 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
269 assemble_nop (opcode)
272 char * f = frag_more (2);
273 md_number_to_chars (f, opcode, 2);
276 /* If the last instruction was the first of 2 16 bit insns,
277 output a nop to move the PC to a 32 bit boundary.
279 This is done via an alignment specification since branch relaxing
280 may make it unnecessary.
282 Internally, we need to output one of these each time a 32 bit insn is
283 seen after an insn that is relaxable. */
289 (void) m32r_do_align (2, NULL, 0, 0);
290 prev_insn.insn = NULL;
291 seen_relaxable_p = 0;
294 /* Cover function to fill_insn called after a label and at end of assembly.
296 The result is always 1: we're called in a conditional to see if the
297 current line is a label. */
300 m32r_fill_insn (done)
306 if (prev_seg != NULL)
311 subseg_set (prev_seg, prev_subseg);
315 subseg_set (seg, subseg);
328 /* Initialize the `cgen' interface. */
330 /* This is a callback from cgen to gas to parse operands. */
331 cgen_parse_operand_fn = cgen_parse_operand;
333 /* Set the machine number and endian. */
334 CGEN_SYM (init_asm) (0 /* mach number */,
336 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
338 #if 0 /* not supported yet */
339 /* If a runtime cpu description file was provided, parse it. */
340 if (m32r_cpu_desc != NULL)
344 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
346 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
350 /* Save the current subseg so we can restore it [it's the default one and
351 we don't want the initial section to be .sbss]. */
355 /* The sbss section is for local .scomm symbols. */
356 sbss_section = subseg_new (".sbss", 0);
358 /* This is copied from perform_an_assembly_pass. */
359 applicable = bfd_applicable_section_flags (stdoutput);
360 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
362 #if 0 /* What does this do? [see perform_an_assembly_pass] */
363 seg_info (bss_section)->bss = 1;
366 subseg_set (seg, subseg);
368 /* We must construct a fake section similar to bfd_com_section
369 but with the name .scommon. */
370 scom_section = bfd_com_section;
371 scom_section.name = ".scommon";
372 scom_section.output_section = & scom_section;
373 scom_section.symbol = & scom_symbol;
374 scom_section.symbol_ptr_ptr = & scom_section.symbol;
375 scom_symbol = * bfd_com_section.symbol;
376 scom_symbol.name = ".scommon";
377 scom_symbol.section = & scom_section;
379 /* start-sanitize-m32rx */
380 allow_m32rx (enable_m32rx);
381 /* end-sanitize-m32rx */
384 /* start-sanitize-m32rx */
385 /* Returns non zero if the given instruction writes to a destination register. */
387 writes_to_dest_reg (insn)
388 const CGEN_INSN * insn;
390 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
393 /* Scan the syntax string looking for a destination register. */
394 while ((c = (* syntax ++)) != 0)
395 if (c == 128 + M32R_OPERAND_DR)
401 /* Returns non zero if the given instruction reads from a source register.
402 Ignores the first 'num_ignore' macthes in the syntax string. */
404 reads_from_src_reg (insn, num_ignore)
405 const CGEN_INSN * insn;
408 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
411 /* Scan the syntax string looking for a source register. */
412 while ((c = (* syntax ++)) != 0)
414 if ( c == 128 + M32R_OPERAND_SR
415 || c == 128 + M32R_OPERAND_SRC1
416 || c == 128 + M32R_OPERAND_SRC2)
418 if (num_ignore -- > 0)
428 /* Returns the integer value of the destination register held in the fields. */
429 #define get_dest_reg(fields) (fields).f_r1
431 /* Returns an integer representing the source register of the given type. */
433 get_src_reg (syntax_field, fields)
434 unsigned char syntax_field;
435 CGEN_FIELDS * fields;
437 switch (syntax_field)
439 case 128 + M32R_OPERAND_SR: return fields->f_r2;
440 /* Relies upon the fact that no instruction with a $src1 operand
441 also has a $dr operand. */
442 case 128 + M32R_OPERAND_SRC1: return fields->f_r1;
443 case 128 + M32R_OPERAND_SRC2: return fields->f_r2;
444 default: abort(); return -1;
448 /* Returns zero iff the output register of instruction 'a'
449 is an input register to instruction 'b'. */
451 check_parallel_io_clash (a, b)
455 if (writes_to_dest_reg (a->insn))
457 unsigned char syntax_field;
460 while (syntax_field = reads_from_src_reg (b->insn, skip ++))
462 if (get_src_reg (syntax_field, & b->fields) == get_dest_reg (a->fields))
471 /* Returns NULL if the two 16 bit insns can be executed in parallel,
472 otherwise it returns a pointer to an error message explaining why not. */
474 can_make_parallel (a, b)
481 /* Make sure the instructions are the right length. */
482 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
483 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
486 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
487 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
489 /* Make sure that the instructions use the correct execution pipelines. */
490 if ( a_pipe == PIPE_NONE
491 || b_pipe == PIPE_NONE)
492 return "Instructions do not use parallel execution pipelines.";
494 if ( a_pipe == PIPE_S
496 return "Instructions share the same execution pipeline";
498 if ( writes_to_dest_reg (a->insn)
499 && writes_to_dest_reg (b->insn)
500 && (get_dest_reg (a->fields) == get_dest_reg (b->fields)))
501 return "Instructions write to the same destination register.";
508 make_parallel (buffer)
509 cgen_insn_t * buffer;
511 /* Force the top bit of the second insn to be set. */
515 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
517 value = bfd_getb16 ((bfd_byte *) buffer);
519 bfd_putb16 (value, (char *) buffer);
523 value = bfd_getl16 ((bfd_byte *) buffer);
525 bfd_putl16 (value, (char *) buffer);
530 make_parallel (buffer)
533 /* Force the top bit of the second insn to be set. */
535 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
541 assemble_parallel_insn (str, str2)
550 * str2 = 0; /* Seperate the two instructions. */
552 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
553 so that the parallel instruction will start on a 32 bit boundary. */
557 /* Parse the first instruction. */
558 if (! (first.insn = CGEN_SYM (assemble_insn)
559 (str, & first.fields, first.buffer, & errmsg)))
565 /* Check to see if this is an allowable parallel insn. */
566 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
568 as_bad ("instruction '%s' cannot be executed in parallel.", str);
573 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
575 as_bad ("instruction '%s' is for the M32RX only", str);
579 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
580 str3 = str; /* Save the original string pointer. */
581 str = str2 + 2; /* Advanced past the parsed string. */
582 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
584 /* Preserve any fixups that have been generated and reset the list to empty. */
587 /* Parse the second instruction. */
588 if (! (second.insn = CGEN_SYM (assemble_insn)
589 (str, & second.fields, second.buffer, & errmsg)))
597 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
599 as_bad ("instruction '%s' is for the M32RX only", str);
605 if ( strcmp (first.insn->name, "nop") != 0
606 && strcmp (second.insn->name, "nop") != 0)
608 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
613 /* We assume that if the first instruction writes to a register that is
614 read by the second instruction it is because the programmer intended
615 this to happen, (after all they have explicitly requested that these
616 two instructions be executed in parallel). Although if the global
617 variable warn_explicit_parallel_conflicts is true then we do generate
618 a warning message. Similarly we assume that parallel branch and jump
619 instructions are deliberate and should not produce errors. */
621 if (can_make_parallel (& first, & second) == NULL)
623 if (warn_explicit_parallel_conflicts
624 && (! check_parallel_io_clash (& first, & second)))
625 as_warn ("%s: output of first instruction fails to overwrite input of second instruction.", str2);
627 /* Get the fixups for the first instruction. */
631 (void) cgen_asm_finish_insn (first.insn, first.buffer,
632 CGEN_FIELDS_BITSIZE (& first.fields));
634 /* Force the top bit of the second insn to be set. */
635 make_parallel (second.buffer);
637 /* Get its fixups. */
638 cgen_restore_fixups ();
641 (void) cgen_asm_finish_insn (second.insn, second.buffer,
642 CGEN_FIELDS_BITSIZE (& second.fields));
644 else if ((errmsg = (char *) can_make_parallel (& second, & first,
645 false, false)) == NULL)
647 if (warn_explicit_parallel_conflicts
648 && (! check_parallel_io_clash (& second, & first)))
649 as_warn ("%s: output of second instruction fails to overwrite input of first instruction.", str2);
651 /* Write out the second instruction first. */
652 (void) cgen_asm_finish_insn (second.insn, second.buffer,
653 CGEN_FIELDS_BITSIZE (& second.fields));
655 /* Force the top bit of the first instruction to be set. */
656 make_parallel (first.buffer);
658 /* Get the fixups for the first instruction. */
659 cgen_restore_fixups ();
661 /* Write out the first instruction. */
662 (void) cgen_asm_finish_insn (first.insn, first.buffer,
663 CGEN_FIELDS_BITSIZE (& first.fields));
667 as_bad ("'%s': %s", str2, errmsg);
671 /* Set these so m32r_fill_insn can use them. */
673 prev_subseg = now_subseg;
677 /* end-sanitize-m32rx */
688 /* Initialize GAS's cgen interface for a new instruction. */
689 cgen_asm_init_parse ();
691 /* start-sanitize-m32rx */
692 /* Look for a parallel instruction seperator. */
693 if ((str2 = strstr (str, "||")) != NULL)
695 assemble_parallel_insn (str, str2);
698 /* end-sanitize-m32rx */
700 insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
707 /* start-sanitize-m32rx */
708 if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
710 as_bad ("instruction '%s' is for the M32RX only", str);
713 /* end-sanitize-m32rx */
715 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
717 /* 32 bit insns must live on 32 bit boundaries. */
718 if (prev_insn.insn || seen_relaxable_p)
720 /* FIXME: If calling fill_insn too many times turns us into a memory
721 pig, can we call assemble_nop instead of !seen_relaxable_p? */
725 (void) cgen_asm_finish_insn (insn.insn, insn.buffer,
726 CGEN_FIELDS_BITSIZE (& insn.fields));
730 /* start-sanitize-m32rx */
731 /* start-sanitize-phase2-m32rx */
733 /* end-sanitize-phase2-m32rx */
734 /* end-sanitize-m32rx */
736 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
739 /* Keep track of whether we've seen a pair of 16 bit insns.
740 prev_insn.insn is NULL when we're on a 32 bit boundary. */
743 /* start-sanitize-m32rx */
744 /* start-sanitize-phase2-m32rx */
745 /* Look to see if this instruction can be combined with the
746 previous instruction to make one, parallel, 32 bit instruction.
747 If the previous instruction (potentially) changed the flow of
748 program control, then it cannot be combined with the current
749 instruction. Also if the output of the previous instruction
750 is used as an input to the current instruction then it cannot
751 be combined. Otherwise call can_make_parallel() with both
752 orderings of the instructions to see if they can be combined. */
753 if ( ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_COND_CTI)
754 && ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_UNCOND_CTI)
755 && check_parallel_io_clash (& prev_insn, &insn)
758 if (can_make_parallel (& prev_insn, & insn) == NULL)
759 make_parallel (insn.buffer);
760 else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
763 /* end-sanitize-phase2-m32rx */
764 /* end-sanitize-m32rx */
766 prev_insn.insn = NULL;
773 /* Record the frag that might be used by this insn. */
774 insn.frag = frag_now;
775 insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer,
776 CGEN_FIELDS_BITSIZE (& insn.fields));
778 /* start-sanitize-m32rx */
779 /* start-sanitize-phase2-m32rx */
784 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
786 /* Swap the two insns */
787 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
788 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
790 make_parallel (insn.addr);
792 /* Swap any relaxable frags recorded for the two insns. */
793 if (prev_insn.frag->fr_opcode == prev_insn.addr)
795 prev_insn.frag->fr_opcode = insn.addr;
797 else if (insn.frag->fr_opcode == insn.addr)
799 insn.frag->fr_opcode = prev_insn.addr;
802 /* end-sanitize-phase2-m32rx */
804 /* Record where this instruction was assembled. */
805 prev_insn.addr = insn.addr;
806 prev_insn.frag = insn.frag;
807 /* end-sanitize-m32rx */
809 /* If the insn needs the following one to be on a 32 bit boundary
810 (e.g. subroutine calls), fill this insn's slot. */
812 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0)
815 /* If this is a relaxable insn (can be replaced with a larger version)
816 mark the fact so that we can emit an alignment directive for a
817 following 32 bit insn if we see one. */
818 if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0)
819 seen_relaxable_p = 1;
822 /* Set these so m32r_fill_insn can use them. */
824 prev_subseg = now_subseg;
827 /* The syntax in the manual says constants begin with '#'.
828 We just ignore it. */
831 md_operand (expressionP)
832 expressionS * expressionP;
834 if (* input_line_pointer == '#')
836 input_line_pointer ++;
837 expression (expressionP);
842 md_section_align (segment, size)
846 int align = bfd_get_section_alignment (stdoutput, segment);
847 return ((size + (1 << align) - 1) & (-1 << align));
851 md_undefined_symbol (name)
857 /* .scomm pseudo-op handler.
859 This is a new pseudo-op to handle putting objects in .scommon.
860 By doing this the linker won't need to do any work and more importantly
861 it removes the implicit -G arg necessary to correctly link the object file.
868 register char * name;
872 register symbolS * symbolP;
876 name = input_line_pointer;
877 c = get_symbol_end ();
879 /* just after name is now '\0' */
880 p = input_line_pointer;
883 if (* input_line_pointer != ',')
885 as_bad ("Expected comma after symbol-name: rest of line ignored.");
886 ignore_rest_of_line ();
890 input_line_pointer ++; /* skip ',' */
891 if ((size = get_absolute_expression ()) < 0)
893 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
894 ignore_rest_of_line ();
898 /* The third argument to .scomm is the alignment. */
899 if (* input_line_pointer != ',')
903 ++ input_line_pointer;
904 align = get_absolute_expression ();
907 as_warn ("ignoring bad alignment");
911 /* Convert to a power of 2 alignment. */
914 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
918 as_bad ("Common alignment not a power of 2");
919 ignore_rest_of_line ();
927 symbolP = symbol_find_or_make (name);
930 if (S_IS_DEFINED (symbolP))
932 as_bad ("Ignoring attempt to re-define symbol `%s'.",
933 S_GET_NAME (symbolP));
934 ignore_rest_of_line ();
938 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
940 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
941 S_GET_NAME (symbolP),
942 (long) S_GET_VALUE (symbolP),
945 ignore_rest_of_line ();
951 segT old_sec = now_seg;
952 int old_subsec = now_subseg;
955 record_alignment (sbss_section, align2);
956 subseg_set (sbss_section, 0);
959 frag_align (align2, 0, 0);
961 if (S_GET_SEGMENT (symbolP) == sbss_section)
962 symbolP->sy_frag->fr_symbol = 0;
964 symbolP->sy_frag = frag_now;
966 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
969 S_SET_SIZE (symbolP, size);
970 S_SET_SEGMENT (symbolP, sbss_section);
971 S_CLEAR_EXTERNAL (symbolP);
972 subseg_set (old_sec, old_subsec);
976 S_SET_VALUE (symbolP, (valueT) size);
977 S_SET_ALIGN (symbolP, align2);
978 S_SET_EXTERNAL (symbolP);
979 S_SET_SEGMENT (symbolP, & scom_section);
982 demand_empty_rest_of_line ();
985 /* Interface to relax_segment. */
987 /* FIXME: Build table by hand, get it working, then machine generate. */
989 const relax_typeS md_relax_table[] =
992 1) most positive reach of this state,
993 2) most negative reach of this state,
994 3) how many bytes this mode will add to the size of the current frag
995 4) which index into the table to try if we can't fit into this one. */
997 /* The first entry must be unused because an `rlx_more' value of zero ends
1001 /* The displacement used by GAS is from the end of the 2 byte insn,
1002 so we subtract 2 from the following. */
1003 /* 16 bit insn, 8 bit disp -> 10 bit range.
1004 This doesn't handle a branch in the right slot at the border:
1005 the "& -4" isn't taken into account. It's not important enough to
1006 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1008 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1009 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1010 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1011 /* Same thing, but with leading nop for alignment. */
1012 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1016 m32r_relax_frag (fragP, stretch)
1020 /* Address of branch insn. */
1021 long address = fragP->fr_address + fragP->fr_fix - 2;
1024 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1025 if (fragP->fr_subtype == 2)
1027 if ((address & 3) != 0)
1029 fragP->fr_subtype = 3;
1033 else if (fragP->fr_subtype == 3)
1035 if ((address & 3) == 0)
1037 fragP->fr_subtype = 2;
1043 growth = relax_frag (fragP, stretch);
1045 /* Long jump on odd halfword boundary? */
1046 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1048 fragP->fr_subtype = 3;
1056 /* Return an initial guess of the length by which a fragment must grow to
1057 hold a branch to reach its destination.
1058 Also updates fr_type/fr_subtype as necessary.
1060 Called just before doing relaxation.
1061 Any symbol that is now undefined will not become defined.
1062 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1063 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1064 Although it may not be explicit in the frag, pretend fr_var starts with a
1068 md_estimate_size_before_relax (fragP, segment)
1072 int old_fr_fix = fragP->fr_fix;
1073 char * opcode = fragP->fr_opcode;
1075 /* The only thing we have to handle here are symbols outside of the
1076 current segment. They may be undefined or in a different segment in
1077 which case linker scripts may place them anywhere.
1078 However, we can't finish the fragment here and emit the reloc as insn
1079 alignment requirements may move the insn about. */
1081 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1083 /* The symbol is undefined in this segment.
1084 Change the relaxation subtype to the max allowable and leave
1085 all further handling to md_convert_frag. */
1086 fragP->fr_subtype = 2;
1088 #if 0 /* Can't use this, but leave in for illustration. */
1089 /* Change 16 bit insn to 32 bit insn. */
1092 /* Increase known (fixed) size of fragment. */
1095 /* Create a relocation for it. */
1096 fix_new (fragP, old_fr_fix, 4,
1098 fragP->fr_offset, 1 /* pcrel */,
1099 /* FIXME: Can't use a real BFD reloc here.
1100 cgen_md_apply_fix3 can't handle it. */
1101 BFD_RELOC_M32R_26_PCREL);
1103 /* Mark this fragment as finished. */
1107 const CGEN_INSN * insn;
1110 /* Update the recorded insn.
1111 Fortunately we don't have to look very far.
1112 FIXME: Change this to record in the instruction the next higher
1113 relaxable insn to use. */
1114 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1116 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1117 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1119 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1125 fragP->fr_cgen.insn = insn;
1131 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1134 /* *fragP has been relaxed to its final size, and now needs to have
1135 the bytes inside it modified to conform to the new size.
1137 Called after relaxation is finished.
1138 fragP->fr_type == rs_machine_dependent.
1139 fragP->fr_subtype is the subtype of what the address relaxed to. */
1142 md_convert_frag (abfd, sec, fragP)
1148 char * displacement;
1154 opcode = fragP->fr_opcode;
1156 /* Address opcode resides at in file space. */
1157 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1159 switch (fragP->fr_subtype)
1163 displacement = & opcode[1];
1168 displacement = & opcode[1];
1171 opcode[2] = opcode[0] | 0x80;
1172 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1173 opcode_address += 2;
1175 displacement = & opcode[3];
1181 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1183 /* symbol must be resolved by linker */
1184 if (fragP->fr_offset & 3)
1185 as_warn ("Addend to unresolved symbol not on word boundary.");
1186 addend = fragP->fr_offset >> 2;
1190 /* Address we want to reach in file space. */
1191 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1192 target_address += fragP->fr_symbol->sy_frag->fr_address;
1193 addend = (target_address - (opcode_address & -4)) >> 2;
1196 /* Create a relocation for symbols that must be resolved by the linker.
1197 Otherwise output the completed insn. */
1199 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1201 assert (fragP->fr_subtype != 1);
1202 assert (fragP->fr_cgen.insn != 0);
1203 cgen_record_fixup (fragP,
1204 /* Offset of branch insn in frag. */
1205 fragP->fr_fix + extension - 4,
1206 fragP->fr_cgen.insn,
1208 /* FIXME: quick hack */
1210 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1212 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1214 fragP->fr_cgen.opinfo,
1215 fragP->fr_symbol, fragP->fr_offset);
1218 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1220 md_number_to_chars (displacement, (valueT) addend,
1221 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1223 fragP->fr_fix += extension;
1226 /* Functions concerning relocs. */
1228 /* The location from which a PC relative jump should be calculated,
1229 given a PC relative reloc. */
1232 md_pcrel_from_section (fixP, sec)
1236 if (fixP->fx_addsy != (symbolS *) NULL
1237 && (! S_IS_DEFINED (fixP->fx_addsy)
1238 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1240 /* The symbol is undefined (or is defined but not in this section).
1241 Let the linker figure it out. */
1245 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1248 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1249 Returns BFD_RELOC_NONE if no reloc type can be found.
1250 *FIXP may be modified if desired. */
1252 bfd_reloc_code_real_type
1253 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1254 const CGEN_INSN * insn;
1255 const CGEN_OPERAND * operand;
1258 switch (CGEN_OPERAND_TYPE (operand))
1260 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1261 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1262 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1263 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1264 case M32R_OPERAND_HI16 :
1265 case M32R_OPERAND_SLO16 :
1266 case M32R_OPERAND_ULO16 :
1267 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1268 if (fixP->tc_fix_data.opinfo != 0)
1269 return fixP->tc_fix_data.opinfo;
1272 return BFD_RELOC_NONE;
1275 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1278 m32r_record_hi16 (reloc_type, fixP, seg)
1283 struct m32r_hi_fixup * hi_fixup;
1285 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1286 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1288 hi_fixup = ((struct m32r_hi_fixup *)
1289 xmalloc (sizeof (struct m32r_hi_fixup)));
1290 hi_fixup->fixp = fixP;
1291 hi_fixup->seg = now_seg;
1292 hi_fixup->next = m32r_hi_fixup_list;
1294 m32r_hi_fixup_list = hi_fixup;
1297 /* Called while parsing an instruction to create a fixup.
1298 We need to check for HI16 relocs and queue them up for later sorting. */
1301 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1304 const CGEN_INSN * insn;
1306 const CGEN_OPERAND * operand;
1310 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1311 operand, opinfo, exp);
1313 switch (CGEN_OPERAND_TYPE (operand))
1315 case M32R_OPERAND_HI16 :
1316 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1317 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1318 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1319 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1326 /* Return BFD reloc type from opinfo field in a fixS.
1327 It's tricky using fx_r_type in m32r_frob_file because the values
1328 are BFD_RELOC_UNUSED + operand number. */
1329 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1331 /* Sort any unmatched HI16 relocs so that they immediately precede
1332 the corresponding LO16 reloc. This is called before md_apply_fix and
1338 struct m32r_hi_fixup * l;
1340 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1342 segment_info_type * seginfo;
1345 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1346 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1348 /* Check quickly whether the next fixup happens to be a matching low. */
1349 if (l->fixp->fx_next != NULL
1350 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1351 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1352 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1355 /* Look through the fixups for this segment for a matching `low'.
1356 When we find one, move the high/shigh just in front of it. We do
1357 this in two passes. In the first pass, we try to find a
1358 unique `low'. In the second pass, we permit multiple high's
1359 relocs for a single `low'. */
1360 seginfo = seg_info (l->seg);
1361 for (pass = 0; pass < 2; pass++)
1367 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1369 /* Check whether this is a `low' fixup which matches l->fixp. */
1370 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1371 && f->fx_addsy == l->fixp->fx_addsy
1372 && f->fx_offset == l->fixp->fx_offset
1375 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1376 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1377 || prev->fx_addsy != f->fx_addsy
1378 || prev->fx_offset != f->fx_offset))
1382 /* Move l->fixp before f. */
1383 for (pf = &seginfo->fix_root;
1385 pf = & (* pf)->fx_next)
1386 assert (* pf != NULL);
1388 * pf = l->fixp->fx_next;
1390 l->fixp->fx_next = f;
1392 seginfo->fix_root = l->fixp;
1394 prev->fx_next = l->fixp;
1406 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1407 "Unmatched high/shigh reloc");
1412 /* See whether we need to force a relocation into the output file.
1413 This is used to force out switch and PC relative relocations when
1417 m32r_force_relocation (fix)
1423 return (fix->fx_pcrel
1427 /* Write a value out to the object file, using the appropriate endianness. */
1430 md_number_to_chars (buf, val, n)
1435 if (target_big_endian)
1436 number_to_chars_bigendian (buf, val, n);
1438 number_to_chars_littleendian (buf, val, n);
1441 /* Turn a string in input_line_pointer into a floating point constant of type
1442 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1443 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1446 /* Equal to MAX_PRECISION in atof-ieee.c */
1447 #define MAX_LITTLENUMS 6
1450 md_atof (type, litP, sizeP)
1457 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1458 LITTLENUM_TYPE * wordP;
1460 char * atof_ieee ();
1478 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1482 return "Bad call to md_atof()";
1485 t = atof_ieee (input_line_pointer, type, words);
1487 input_line_pointer = t;
1488 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1490 if (target_big_endian)
1492 for (i = 0; i < prec; i++)
1494 md_number_to_chars (litP, (valueT) words[i],
1495 sizeof (LITTLENUM_TYPE));
1496 litP += sizeof (LITTLENUM_TYPE);
1501 for (i = prec - 1; i >= 0; i--)
1503 md_number_to_chars (litP, (valueT) words[i],
1504 sizeof (LITTLENUM_TYPE));
1505 litP += sizeof (LITTLENUM_TYPE);