1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
2 Copyright (C) 1996, 1997 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "../../opcodes/m32r-asm.c"
28 #include "../../opcodes/m32r-asm.in"
30 /* Non-null if last insn was a 16 bit insn on a 32 bit boundary
31 (i.e. was the first of two 16 bit insns). */
32 static const CGEN_INSN * prev_insn = NULL;
34 /* Non-zero if we've seen a relaxable insn since the last 32 bit
36 static int seen_relaxable_p = 0;
38 /* Non-zero if -relax specified, in which case sufficient relocs are output
39 for the linker to do relaxing.
40 We do simple forms of relaxing internally, but they are always done.
41 This flag does not apply to them. */
42 static int m32r_relax;
44 /* If non-NULL, pointer to cpu description file to read.
45 This allows runtime additions to the assembler. */
46 static char * m32r_cpu_desc;
48 /* start-sanitize-m32rx */
49 /* Non-zero if -m32rx has been specified, in which case support for the
50 extended M32RX instruction set should be enabled. */
51 static int enable_m32rx = 0;
52 /* end-sanitize-m32rx */
54 /* stuff for .scomm symbols. */
55 static segT sbss_section;
56 static asection scom_section;
57 static asymbol scom_symbol;
59 const char comment_chars[] = ";";
60 const char line_comment_chars[] = "#";
61 const char line_separator_chars[] = "";
62 const char EXP_CHARS[] = "eE";
63 const char FLT_CHARS[] = "dD";
65 /* Relocations against symbols are done in two
66 parts, with a HI relocation and a LO relocation. Each relocation
67 has only 16 bits of space to store an addend. This means that in
68 order for the linker to handle carries correctly, it must be able
69 to locate both the HI and the LO relocation. This means that the
70 relocations must appear in order in the relocation table.
72 In order to implement this, we keep track of each unmatched HI
73 relocation. We then sort them so that they immediately precede the
74 corresponding LO relocation. */
78 struct m32r_hi_fixup * next; /* Next HI fixup. */
79 fixS * fixp; /* This fixup. */
80 segT seg; /* The section this fixup is in. */
84 /* The list of unmatched HI relocs. */
86 static struct m32r_hi_fixup * m32r_hi_fixup_list;
88 static void m32r_record_hi16 PARAMS ((int, fixS *, segT seg));
91 /* start-sanitize-m32rx */
97 if (stdoutput != NULL)
98 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
99 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
101 /* end-sanitize-m32rx */
103 const char * md_shortopts = "";
105 struct option md_longopts[] =
107 /* start-sanitize-m32rx */
108 #define OPTION_M32RX (OPTION_MD_BASE)
109 {"m32rx", no_argument, NULL, OPTION_M32RX},
110 /* end-sanitize-m32rx */
112 #if 0 /* not supported yet */
113 #define OPTION_RELAX (OPTION_MD_BASE + 1)
114 {"relax", no_argument, NULL, OPTION_RELAX},
115 #define OPTION_CPU_DESC (OPTION_MD_BASE + 2)
116 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
119 {NULL, no_argument, NULL, 0}
121 size_t md_longopts_size = sizeof (md_longopts);
124 md_parse_option (c, arg)
130 /* start-sanitize-m32rx */
134 /* end-sanitize-m32rx */
136 #if 0 /* not supported yet */
140 case OPTION_CPU_DESC:
151 md_show_usage (stream)
154 fprintf (stream, "M32R/X options:\n");
155 /* start-sanitize-m32rx */
157 --m32rx support the extended m32rx instruction set\n");
158 /* end-sanitize-m32rx */
162 --relax create linker relaxable code\n");
164 --cpu-desc provide runtime cpu description file\n");
168 static void fill_insn PARAMS ((int));
169 static void m32r_scomm PARAMS ((int));
171 /* Set by md_assemble for use by m32r_fill_insn. */
172 static subsegT prev_subseg;
173 static segT prev_seg;
175 /* The target specific pseudo-ops which we support. */
176 const pseudo_typeS md_pseudo_table[] =
179 { "fillinsn", fill_insn, 0 },
180 { "scomm", m32r_scomm, 0 },
181 /* start-sanitize-m32rx */
182 { "m32r", allow_m32rx, 0},
183 { "m32rx", allow_m32rx, 1},
184 /* end-sanitize-m32rx */
188 /* FIXME: Should be machine generated. */
189 #define NOP_INSN 0x7000
190 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
192 /* When we align the .text section, insert the correct NOP pattern.
193 N is the power of 2 alignment. LEN is the length of pattern FILL.
194 MAX is the maximum number of characters to skip when doing the alignment,
195 or 0 if there is no maximum. */
198 m32r_do_align (n, fill, len, max)
204 if ((fill == NULL || (* fill == 0 && len == 1))
205 && (now_seg->flags & SEC_CODE) != 0
206 /* Only do this special handling if aligning to at least a
209 /* Only do this special handling if we're allowed to emit at
211 && (max == 0 || max > 1))
213 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
216 /* First align to a 2 byte boundary, in case there is an odd .byte. */
217 /* FIXME: How much memory will cause gas to use when assembling a big
218 program? Perhaps we can avoid the frag_align call? */
219 frag_align (1, 0, 0);
221 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
223 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
224 /* If doing larger alignments use a repeating sequence of appropriate
228 static const unsigned char multi_nop_pattern[] =
229 { 0x70, 0x00, 0xf0, 0x00 };
230 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
240 assemble_nop (opcode)
243 char * f = frag_more (2);
244 md_number_to_chars (f, opcode, 2);
247 /* If the last instruction was the first of 2 16 bit insns,
248 output a nop to move the PC to a 32 bit boundary.
250 This is done via an alignment specification since branch relaxing
251 may make it unnecessary.
253 Internally, we need to output one of these each time a 32 bit insn is
254 seen after an insn that is relaxable. */
260 (void) m32r_do_align (2, NULL, 0, 0);
262 seen_relaxable_p = 0;
265 /* Cover function to fill_insn called after a label and at end of assembly.
267 The result is always 1: we're called in a conditional to see if the
268 current line is a label. */
271 m32r_fill_insn (done)
277 if (prev_seg != NULL)
282 subseg_set (prev_seg, prev_subseg);
286 subseg_set (seg, subseg);
299 /* Initialize the `cgen' interface. */
301 /* This is a callback from cgen to gas to parse operands. */
302 cgen_parse_operand_fn = cgen_parse_operand;
304 /* Set the machine number and endian. */
305 CGEN_SYM (init_asm) (0 /* mach number */,
307 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
309 #if 0 /* not supported yet */
310 /* If a runtime cpu description file was provided, parse it. */
311 if (m32r_cpu_desc != NULL)
315 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
317 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
321 /* Save the current subseg so we can restore it [it's the default one and
322 we don't want the initial section to be .sbss]. */
326 /* The sbss section is for local .scomm symbols. */
327 sbss_section = subseg_new (".sbss", 0);
329 /* This is copied from perform_an_assembly_pass. */
330 applicable = bfd_applicable_section_flags (stdoutput);
331 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
333 #if 0 /* What does this do? [see perform_an_assembly_pass] */
334 seg_info (bss_section)->bss = 1;
337 subseg_set (seg, subseg);
339 /* We must construct a fake section similar to bfd_com_section
340 but with the name .scommon. */
341 scom_section = bfd_com_section;
342 scom_section.name = ".scommon";
343 scom_section.output_section = & scom_section;
344 scom_section.symbol = & scom_symbol;
345 scom_section.symbol_ptr_ptr = & scom_section.symbol;
346 scom_symbol = * bfd_com_section.symbol;
347 scom_symbol.name = ".scommon";
348 scom_symbol.section = & scom_section;
350 /* start-sanitize-m32rx */
351 allow_m32rx (enable_m32rx);
352 /* end-sanitize-m32rx */
355 /* Returns non zero if the given instruction writes to a destination register. */
357 writes_to_dest_reg (insn)
358 const CGEN_INSN * insn;
360 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
363 /* Scan the syntax string looking for a destination register. */
364 while ((c = (* syntax ++)) != 0)
365 if (c == 128 + M32R_OPERAND_DR)
371 /* Returns an integer representing the destination register of
372 the given insn, or -1 if the insn has no destination. */
375 const CGEN_INSN * insn;
377 /* XXX to be done. */
386 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
387 cgen_insn_t prev_buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
389 char buffer [CGEN_MAX_INSN_SIZE];
390 char prev_buffer [CGEN_MAX_INSN_SIZE];
393 CGEN_FIELDS prev_fields;
394 const CGEN_INSN * insn;
397 int is_parallel = false;
399 /* Initialize GAS's cgen interface for a new instruction. */
400 cgen_asm_init_parse ();
402 /* Look for a parallel instruction seperator. */
403 if ((str2 = strstr (str, "||")) != NULL)
407 * str2 = 0; /* Seperate the two instructions. */
409 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
410 so that the parallel instruction will start on a 32 bit boundary. */
414 /* Assemble the first instruction. */
415 prev_insn = CGEN_SYM (assemble_insn) (str, & prev_fields, prev_buffer, & errmsg);
422 /* Check to see if this is an allowable parallel insn. */
423 if (CGEN_INSN_ATTR (prev_insn, CGEN_INSN_PIPE) == PIPE_NONE)
425 as_bad ("instruction '%s' cannot be executed in parallel.", str);
429 /* start-sanitize-m32rx */
430 if (! enable_m32rx &&
431 CGEN_INSN_ATTR (prev_insn, CGEN_INSN_MACH) == MACH_M32RX)
433 as_bad ("instruction '%s' is for the M32RX only", str);
436 /* end-sanitize-m32rx */
438 /* fixups = fixups->next; */
440 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
441 str3 = str; /* Save the original string pointer. */
442 str = str2 + 2; /* Advanced past the parsed string. */
443 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
448 insn = CGEN_SYM (assemble_insn) (str, & fields, buffer, & errmsg);
455 /* start-sanitize-m32rx */
457 && CGEN_INSN_ATTR (insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
459 as_bad ("instruction '%s' is for the M32RX only", str);
462 /* end-sanitize-m32rx */
466 /* start-sanitize-m32rx */
469 if (strcmp (prev_insn->name, "nop") != 0
470 && strcmp (insn->name, "nop") != 0)
472 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
476 /* end-sanitize-m32rx */
478 /* Check to see if this is an allowable parallel insn. */
479 if (CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) == PIPE_NONE)
481 as_bad ("instruction '%s', cannot be executed in parallel.", str);
485 /* Check to see that the two instructions can be placed in parallel. */
486 if ((CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) == CGEN_INSN_ATTR (prev_insn, CGEN_INSN_PIPE))
487 && (CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) != PIPE_OS))
489 as_bad ("'%s': both instructions use the same execution pipeline", str2);
493 /* Check that the instructions do not write to the same destination register. */
494 if (writes_to_dest_reg (insn)
495 && writes_to_dest_reg (prev_insn) /* This test is actually redundant. */
496 && get_dest_reg (insn) == get_dest_reg (prev_insn))
498 as_bad ("'%s': both instructions write to the same destination register", str2);
503 /* Force the top bit of the second insn to be set. */
504 #if 0 /*def CGEN_INT_INSN*/
505 #define MAKE_PARALLEL(insn) ((insn) |= 0x8000)
506 switch (CGEN_FIELDS_BITSIZE (& fields))
511 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
513 value = bfd_getb16 ((bfd_vma) * buffer);
514 MAKE_PARALLEL (value);
515 bfd_putb16 (value, buffer);
519 value = bfd_getl16 ((bfd_vma) * buffer);
520 MAKE_PARALLEL (value);
521 bfd_putl16 (value, buffer);
528 #define MAKE_PARALLEL(insn) ((insn) |= 0x80)
529 MAKE_PARALLEL (buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1]);
532 /* Generate the parallel instructions */
533 cgen_asm_finish_insn (prev_insn, prev_buffer, CGEN_FIELDS_BITSIZE (& prev_fields));
534 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
536 /* If prev_ins is relaxable (and insn is not), then swap them, so that the test
537 after the end of this if-then-else section will work. */
538 if (CGEN_INSN_ATTR (prev_insn, CGEN_INSN_RELAXABLE))
541 /* Clear the prev_insn variable, since it only used if the insn was the first
542 16 bit insn in a 32 bit word. */
545 else if (CGEN_INSN_BITSIZE (insn) == 32)
547 /* 32 bit insns must live on 32 bit boundaries. */
548 if (prev_insn || seen_relaxable_p)
550 /* FIXME: If calling fill_insn too many times turns us into a memory
551 pig, can we call assemble_nop instead of !seen_relaxable_p? */
555 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
559 /* Keep track of whether we've seen a pair of 16 bit insns.
560 PREV_INSN is NULL when we're on a 32 bit boundary. */
566 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
568 /* If the insn needs the following one to be on a 32 bit boundary
569 (e.g. subroutine calls), fill this insn's slot. */
571 && CGEN_INSN_ATTR (insn, CGEN_INSN_FILL_SLOT) != 0)
575 /* If this is a relaxable insn (can be replaced with a larger version)
576 mark the fact so that we can emit an alignment directive for a following
577 32 bit insn if we see one. */
578 if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAXABLE) != 0)
579 seen_relaxable_p = 1;
581 /* Set these so m32r_fill_insn can use them. */
583 prev_subseg = now_subseg;
586 /* The syntax in the manual says constants begin with '#'.
587 We just ignore it. */
590 md_operand (expressionP)
591 expressionS * expressionP;
593 if (* input_line_pointer == '#')
595 input_line_pointer ++;
596 expression (expressionP);
601 md_section_align (segment, size)
605 int align = bfd_get_section_alignment (stdoutput, segment);
606 return ((size + (1 << align) - 1) & (-1 << align));
610 md_undefined_symbol (name)
616 /* .scomm pseudo-op handler.
618 This is a new pseudo-op to handle putting objects in .scommon.
619 By doing this the linker won't need to do any work and more importantly
620 it removes the implicit -G arg necessary to correctly link the object file.
627 register char * name;
631 register symbolS * symbolP;
635 name = input_line_pointer;
636 c = get_symbol_end ();
638 /* just after name is now '\0' */
639 p = input_line_pointer;
642 if (* input_line_pointer != ',')
644 as_bad ("Expected comma after symbol-name: rest of line ignored.");
645 ignore_rest_of_line ();
649 input_line_pointer++; /* skip ',' */
650 if ((size = get_absolute_expression ()) < 0)
652 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
653 ignore_rest_of_line ();
657 /* The third argument to .scomm is the alignment. */
658 if (* input_line_pointer != ',')
662 ++ input_line_pointer;
663 align = get_absolute_expression ();
666 as_warn ("ignoring bad alignment");
670 /* Convert to a power of 2 alignment. */
673 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
677 as_bad ("Common alignment not a power of 2");
678 ignore_rest_of_line ();
686 symbolP = symbol_find_or_make (name);
689 if (S_IS_DEFINED (symbolP))
691 as_bad ("Ignoring attempt to re-define symbol `%s'.",
692 S_GET_NAME (symbolP));
693 ignore_rest_of_line ();
697 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
699 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
700 S_GET_NAME (symbolP),
701 (long) S_GET_VALUE (symbolP),
704 ignore_rest_of_line ();
710 segT old_sec = now_seg;
711 int old_subsec = now_subseg;
714 record_alignment (sbss_section, align2);
715 subseg_set (sbss_section, 0);
717 frag_align (align2, 0, 0);
718 if (S_GET_SEGMENT (symbolP) == sbss_section)
719 symbolP->sy_frag->fr_symbol = 0;
720 symbolP->sy_frag = frag_now;
721 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
724 S_SET_SIZE (symbolP, size);
725 S_SET_SEGMENT (symbolP, sbss_section);
726 S_CLEAR_EXTERNAL (symbolP);
727 subseg_set (old_sec, old_subsec);
731 S_SET_VALUE (symbolP, (valueT) size);
732 S_SET_ALIGN (symbolP, align2);
733 S_SET_EXTERNAL (symbolP);
734 S_SET_SEGMENT (symbolP, &scom_section);
737 demand_empty_rest_of_line ();
740 /* Interface to relax_segment. */
742 /* FIXME: Build table by hand, get it working, then machine generate. */
744 const relax_typeS md_relax_table[] =
747 1) most positive reach of this state,
748 2) most negative reach of this state,
749 3) how many bytes this mode will add to the size of the current frag
750 4) which index into the table to try if we can't fit into this one. */
752 /* The first entry must be unused because an `rlx_more' value of zero ends
756 /* The displacement used by GAS is from the end of the 2 byte insn,
757 so we subtract 2 from the following. */
758 /* 16 bit insn, 8 bit disp -> 10 bit range.
759 This doesn't handle a branch in the right slot at the border:
760 the "& -4" isn't taken into account. It's not important enough to
761 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
763 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
764 /* 32 bit insn, 24 bit disp -> 26 bit range. */
765 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
766 /* Same thing, but with leading nop for alignment. */
767 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
771 m32r_relax_frag (fragP, stretch)
775 /* Address of branch insn. */
776 long address = fragP->fr_address + fragP->fr_fix - 2;
779 /* Keep 32 bit insns aligned on 32 bit boundaries. */
780 if (fragP->fr_subtype == 2)
782 if ((address & 3) != 0)
784 fragP->fr_subtype = 3;
788 else if (fragP->fr_subtype == 3)
790 if ((address & 3) == 0)
792 fragP->fr_subtype = 2;
798 growth = relax_frag (fragP, stretch);
800 /* Long jump on odd halfword boundary? */
801 if (fragP->fr_subtype == 2 && (address & 3) != 0)
803 fragP->fr_subtype = 3;
811 /* Return an initial guess of the length by which a fragment must grow to
812 hold a branch to reach its destination.
813 Also updates fr_type/fr_subtype as necessary.
815 Called just before doing relaxation.
816 Any symbol that is now undefined will not become defined.
817 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
818 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
819 Although it may not be explicit in the frag, pretend fr_var starts with a
823 md_estimate_size_before_relax (fragP, segment)
827 int old_fr_fix = fragP->fr_fix;
828 char * opcode = fragP->fr_opcode;
830 /* The only thing we have to handle here are symbols outside of the
831 current segment. They may be undefined or in a different segment in
832 which case linker scripts may place them anywhere.
833 However, we can't finish the fragment here and emit the reloc as insn
834 alignment requirements may move the insn about. */
836 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
838 /* The symbol is undefined in this segment.
839 Change the relaxation subtype to the max allowable and leave
840 all further handling to md_convert_frag. */
841 fragP->fr_subtype = 2;
843 #if 0 /* Can't use this, but leave in for illustration. */
844 /* Change 16 bit insn to 32 bit insn. */
847 /* Increase known (fixed) size of fragment. */
850 /* Create a relocation for it. */
851 fix_new (fragP, old_fr_fix, 4,
853 fragP->fr_offset, 1 /* pcrel */,
854 /* FIXME: Can't use a real BFD reloc here.
855 cgen_md_apply_fix3 can't handle it. */
856 BFD_RELOC_M32R_26_PCREL);
858 /* Mark this fragment as finished. */
862 const CGEN_INSN * insn;
865 /* Update the recorded insn.
866 Fortunately we don't have to look very far.
867 FIXME: Change this to record in the instruction the next higher
868 relaxable insn to use. */
869 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
871 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
872 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
874 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
879 fragP->fr_cgen.insn = insn;
885 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
888 /* *fragP has been relaxed to its final size, and now needs to have
889 the bytes inside it modified to conform to the new size.
891 Called after relaxation is finished.
892 fragP->fr_type == rs_machine_dependent.
893 fragP->fr_subtype is the subtype of what the address relaxed to. */
896 md_convert_frag (abfd, sec, fragP)
908 opcode = fragP->fr_opcode;
910 /* Address opcode resides at in file space. */
911 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
913 switch (fragP->fr_subtype)
917 displacement = & opcode[1];
922 displacement = & opcode[1];
925 opcode[2] = opcode[0] | 0x80;
926 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
929 displacement = & opcode[3];
935 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
937 /* symbol must be resolved by linker */
938 if (fragP->fr_offset & 3)
939 as_warn ("Addend to unresolved symbol not on word boundary.");
940 addend = fragP->fr_offset >> 2;
944 /* Address we want to reach in file space. */
945 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
946 target_address += fragP->fr_symbol->sy_frag->fr_address;
947 addend = (target_address - (opcode_address & -4)) >> 2;
950 /* Create a relocation for symbols that must be resolved by the linker.
951 Otherwise output the completed insn. */
953 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
955 assert (fragP->fr_subtype != 1);
956 assert (fragP->fr_cgen.insn != 0);
957 cgen_record_fixup (fragP,
958 /* Offset of branch insn in frag. */
959 fragP->fr_fix + extension - 4,
962 /* FIXME: quick hack */
964 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
966 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
968 fragP->fr_cgen.opinfo,
969 fragP->fr_symbol, fragP->fr_offset);
972 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
974 md_number_to_chars (displacement, (valueT) addend,
975 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
977 fragP->fr_fix += extension;
980 /* Functions concerning relocs. */
982 /* The location from which a PC relative jump should be calculated,
983 given a PC relative reloc. */
986 md_pcrel_from_section (fixP, sec)
990 if (fixP->fx_addsy != (symbolS *) NULL
991 && (! S_IS_DEFINED (fixP->fx_addsy)
992 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
994 /* The symbol is undefined (or is defined but not in this section).
995 Let the linker figure it out. */
999 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1002 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1003 Returns BFD_RELOC_NONE if no reloc type can be found.
1004 *FIXP may be modified if desired. */
1006 bfd_reloc_code_real_type
1007 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1008 const CGEN_INSN * insn;
1009 const CGEN_OPERAND * operand;
1012 switch (CGEN_OPERAND_TYPE (operand))
1014 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1015 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1016 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1017 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1018 case M32R_OPERAND_HI16 :
1019 case M32R_OPERAND_SLO16 :
1020 case M32R_OPERAND_ULO16 :
1021 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1022 if (fixP->tc_fix_data.opinfo != 0)
1023 return fixP->tc_fix_data.opinfo;
1026 return BFD_RELOC_NONE;
1029 /* Called while parsing an instruction to create a fixup.
1030 We need to check for HI16 relocs and queue them up for later sorting. */
1033 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1036 const CGEN_INSN * insn;
1038 const CGEN_OPERAND * operand;
1042 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1043 operand, opinfo, exp);
1045 switch (CGEN_OPERAND_TYPE (operand))
1047 case M32R_OPERAND_HI16 :
1048 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1049 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1050 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1051 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1058 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1061 m32r_record_hi16 (reloc_type, fixP, seg)
1066 struct m32r_hi_fixup * hi_fixup;
1068 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1069 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1071 hi_fixup = ((struct m32r_hi_fixup *)
1072 xmalloc (sizeof (struct m32r_hi_fixup)));
1073 hi_fixup->fixp = fixP;
1074 hi_fixup->seg = now_seg;
1075 hi_fixup->next = m32r_hi_fixup_list;
1077 m32r_hi_fixup_list = hi_fixup;
1080 /* Return BFD reloc type from opinfo field in a fixS.
1081 It's tricky using fx_r_type in m32r_frob_file because the values
1082 are BFD_RELOC_UNUSED + operand number. */
1083 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1085 /* Sort any unmatched HI16 relocs so that they immediately precede
1086 the corresponding LO16 reloc. This is called before md_apply_fix and
1092 struct m32r_hi_fixup * l;
1094 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1096 segment_info_type * seginfo;
1099 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1100 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1102 /* Check quickly whether the next fixup happens to be a matching low. */
1103 if (l->fixp->fx_next != NULL
1104 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1105 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1106 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1109 /* Look through the fixups for this segment for a matching `low'.
1110 When we find one, move the high/shigh just in front of it. We do
1111 this in two passes. In the first pass, we try to find a
1112 unique `low'. In the second pass, we permit multiple high's
1113 relocs for a single `low'. */
1114 seginfo = seg_info (l->seg);
1115 for (pass = 0; pass < 2; pass++)
1121 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1123 /* Check whether this is a `low' fixup which matches l->fixp. */
1124 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1125 && f->fx_addsy == l->fixp->fx_addsy
1126 && f->fx_offset == l->fixp->fx_offset
1129 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1130 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1131 || prev->fx_addsy != f->fx_addsy
1132 || prev->fx_offset != f->fx_offset))
1136 /* Move l->fixp before f. */
1137 for (pf = &seginfo->fix_root;
1139 pf = & (* pf)->fx_next)
1140 assert (* pf != NULL);
1142 * pf = l->fixp->fx_next;
1144 l->fixp->fx_next = f;
1146 seginfo->fix_root = l->fixp;
1148 prev->fx_next = l->fixp;
1160 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1161 "Unmatched high/shigh reloc");
1166 /* See whether we need to force a relocation into the output file.
1167 This is used to force out switch and PC relative relocations when
1171 m32r_force_relocation (fix)
1177 return (fix->fx_pcrel
1181 /* Write a value out to the object file, using the appropriate endianness. */
1184 md_number_to_chars (buf, val, n)
1189 if (target_big_endian)
1190 number_to_chars_bigendian (buf, val, n);
1192 number_to_chars_littleendian (buf, val, n);
1195 /* Turn a string in input_line_pointer into a floating point constant of type
1196 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1197 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1200 /* Equal to MAX_PRECISION in atof-ieee.c */
1201 #define MAX_LITTLENUMS 6
1204 md_atof (type, litP, sizeP)
1211 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1212 LITTLENUM_TYPE * wordP;
1214 char * atof_ieee ();
1232 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1236 return "Bad call to md_atof()";
1239 t = atof_ieee (input_line_pointer, type, words);
1241 input_line_pointer = t;
1242 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1244 if (target_big_endian)
1246 for (i = 0; i < prec; i++)
1248 md_number_to_chars (litP, (valueT) words[i],
1249 sizeof (LITTLENUM_TYPE));
1250 litP += sizeof (LITTLENUM_TYPE);
1255 for (i = prec - 1; i >= 0; i--)
1257 md_number_to_chars (litP, (valueT) words[i],
1258 sizeof (LITTLENUM_TYPE));
1259 litP += sizeof (LITTLENUM_TYPE);