1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 /* Linked list of symbols that are debugging symbols to be defined as the
30 beginning of the current instruction. */
31 typedef struct sym_link
33 struct sym_link *next;
37 static sym_linkS *debug_sym_link = (sym_linkS *)0;
39 /* Structure to hold all of the different components describing
40 an individual instruction. */
43 const CGEN_INSN * insn;
44 const CGEN_INSN * orig_insn;
47 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
49 char buffer [CGEN_MAX_INSN_SIZE];
54 fixS * fixups [CGEN_MAX_FIXUPS];
55 int indices [MAX_OPERAND_INSTANCES];
56 sym_linkS *debug_sym_link;
60 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
61 boundary (i.e. was the first of two 16 bit insns). */
62 static m32r_insn prev_insn;
64 /* Non-zero if we've seen a relaxable insn since the last 32 bit
66 static int seen_relaxable_p = 0;
68 /* Non-zero if -relax specified, in which case sufficient relocs are output
69 for the linker to do relaxing.
70 We do simple forms of relaxing internally, but they are always done.
71 This flag does not apply to them. */
72 static int m32r_relax;
74 /* If non-NULL, pointer to cpu description file to read.
75 This allows runtime additions to the assembler. */
76 static char * m32r_cpu_desc;
78 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
79 Each high/shigh reloc must be paired with it's low cousin in order to
80 properly calculate the addend in a relocatable link (since there is a
81 potential carry from the low to the high/shigh).
82 This option is off by default though for user-written assembler code it
83 might make sense to make the default be on (i.e. have gcc pass a flag
84 to turn it off). This warning must not be on for GCC created code as
85 optimization may delete the low but not the high/shigh (at least we
86 shouldn't assume or require it to). */
87 static int warn_unmatched_high = 0;
89 /* start-sanitize-m32rx */
90 /* Non-zero if --m32rx has been specified, in which case support for the
91 extended M32RX instruction set should be enabled. */
92 static int enable_m32rx = 0;
94 /* Non-zero if --m32rx-enable-special has been specified, in which case support for
95 the special M32RX instruction set should be enabled. */
96 static int enable_special = 0;
98 /* Non-zero if the programmer should be warned when an explicit parallel
99 instruction might have constraint violations. */
100 static int warn_explicit_parallel_conflicts = 1;
102 /* Non-zero if insns can be made parallel. */
104 /* end-sanitize-m32rx */
106 /* stuff for .scomm symbols. */
107 static segT sbss_section;
108 static asection scom_section;
109 static asymbol scom_symbol;
111 const char comment_chars[] = ";";
112 const char line_comment_chars[] = "#";
113 const char line_separator_chars[] = "";
114 const char EXP_CHARS[] = "eE";
115 const char FLT_CHARS[] = "dD";
117 /* Relocations against symbols are done in two
118 parts, with a HI relocation and a LO relocation. Each relocation
119 has only 16 bits of space to store an addend. This means that in
120 order for the linker to handle carries correctly, it must be able
121 to locate both the HI and the LO relocation. This means that the
122 relocations must appear in order in the relocation table.
124 In order to implement this, we keep track of each unmatched HI
125 relocation. We then sort them so that they immediately precede the
126 corresponding LO relocation. */
130 struct m32r_hi_fixup * next; /* Next HI fixup. */
131 fixS * fixp; /* This fixup. */
132 segT seg; /* The section this fixup is in. */
136 /* The list of unmatched HI relocs. */
138 static struct m32r_hi_fixup * m32r_hi_fixup_list;
141 /* start-sanitize-m32rx */
148 if (stdoutput != NULL)
149 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
150 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
152 /* end-sanitize-m32rx */
154 #define M32R_SHORTOPTS ""
155 /* start-sanitize-m32rx */
156 #undef M32R_SHORTOPTS
157 #define M32R_SHORTOPTS "O"
158 /* end-sanitize-m32rx */
159 const char * md_shortopts = M32R_SHORTOPTS;
161 struct option md_longopts[] =
163 /* start-sanitize-m32rx */
164 #define OPTION_M32RX (OPTION_MD_BASE)
165 {"m32rx", no_argument, NULL, OPTION_M32RX},
166 #define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
167 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
168 {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
169 #define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2)
170 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
171 {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
172 #define OPTION_SPECIAL (OPTION_MD_BASE + 3)
173 {"m32rx-enable-special", no_argument, NULL, OPTION_SPECIAL},
174 {"m32rx-es", no_argument, NULL, OPTION_SPECIAL},
175 /* end-sanitize-m32rx */
177 /* Sigh. I guess all warnings must now have both variants. */
178 #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
179 {"warn-unmatched-high", OPTION_WARN_UNMATCHED},
180 {"Wuh", OPTION_WARN_UNMATCHED},
181 #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
182 {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED},
183 {"Wnuh", OPTION_WARN_UNMATCHED},
185 #if 0 /* not supported yet */
186 #define OPTION_RELAX (OPTION_MD_BASE + 6)
187 {"relax", no_argument, NULL, OPTION_RELAX},
188 #define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
189 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
192 {NULL, no_argument, NULL, 0}
194 size_t md_longopts_size = sizeof (md_longopts);
197 md_parse_option (c, arg)
203 /* start-sanitize-m32rx */
212 case OPTION_WARN_PARALLEL:
213 warn_explicit_parallel_conflicts = 1;
216 case OPTION_NO_WARN_PARALLEL:
217 warn_explicit_parallel_conflicts = 0;
224 /* end-sanitize-m32rx */
226 case OPTION_WARN_UNMATCHED:
227 warn_unmatched_high = 1;
230 case OPTION_NO_WARN_UNMATCHED:
231 warn_unmatched_high = 0;
234 #if 0 /* not supported yet */
238 case OPTION_CPU_DESC:
250 md_show_usage (stream)
253 fprintf (stream, _("M32R specific command line options:\n"));
255 /* start-sanitize-m32rx */
256 fprintf (stream, _("\
257 --m32rx support the extended m32rx instruction set\n"));
258 fprintf (stream, _("\
259 --m32rx-enable-special support the special m32rx instructions\n"));
260 fprintf (stream, _("\
261 --m32rx-es synonym for --m32rx-enable-special\n"));
262 fprintf (stream, _("\
263 -O try to combine instructions in parallel\n"));
265 fprintf (stream, _("\
266 --warn-explicit-parallel-conflicts warn when parallel instrucitons violate contraints\n"));
267 fprintf (stream, _("\
268 --no-warn-explicit-parallel-conflicts do not warn when parallel instrucitons violate contraints\n"));
269 fprintf (stream, _("\
270 --Wp synonym for --warn-explicit-parallel-conflicts\n"));
271 fprintf (stream, _("\
272 --Wnp synonym for --no-warn-explicit-parallel-conflicts\n"));
273 /* end-sanitize-m32rx */
275 fprintf (stream, _("\
276 --warn-unmatched-high warn when a high or shigh reloc has no matching low reloc\n"));
277 fprintf (stream, _("\
278 --no-warn-unmatched-high do not warn when a high or shigh reloc has no matching low reloc\n"));
279 fprintf (stream, _("\
280 --Wuh synonym for --warn-unmatched-high\n"));
281 fprintf (stream, _("\
282 --Wnuh synonym for --no-warn-unmatched-high\n"));
285 fprintf (stream, _("\
286 --relax create linker relaxable code\n"));
287 fprintf (stream, _("\
288 --cpu-desc provide runtime cpu description file\n"));
292 static void fill_insn PARAMS ((int));
293 static void m32r_scomm PARAMS ((int));
294 static void debug_sym PARAMS ((int));
295 static void expand_debug_syms PARAMS ((sym_linkS *, int));
297 /* Set by md_assemble for use by m32r_fill_insn. */
298 static subsegT prev_subseg;
299 static segT prev_seg;
301 /* The target specific pseudo-ops which we support. */
302 const pseudo_typeS md_pseudo_table[] =
305 { "fillinsn", fill_insn, 0 },
306 { "scomm", m32r_scomm, 0 },
307 { "debugsym", debug_sym, 0 },
308 /* start-sanitize-m32rx */
309 { "m32r", allow_m32rx, 0 },
310 { "m32rx", allow_m32rx, 1 },
311 /* end-sanitize-m32rx */
315 /* FIXME: Should be machine generated. */
316 #define NOP_INSN 0x7000
317 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
319 /* When we align the .text section, insert the correct NOP pattern.
320 N is the power of 2 alignment. LEN is the length of pattern FILL.
321 MAX is the maximum number of characters to skip when doing the alignment,
322 or 0 if there is no maximum. */
325 m32r_do_align (n, fill, len, max)
331 if ((fill == NULL || (* fill == 0 && len == 1))
332 && (now_seg->flags & SEC_CODE) != 0
333 /* Only do this special handling if aligning to at least a
336 /* Only do this special handling if we're allowed to emit at
338 && (max == 0 || max > 1))
340 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
343 /* First align to a 2 byte boundary, in case there is an odd .byte. */
344 /* FIXME: How much memory will cause gas to use when assembling a big
345 program? Perhaps we can avoid the frag_align call? */
346 frag_align (1, 0, 0);
348 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
350 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
351 /* If doing larger alignments use a repeating sequence of appropriate
355 static const unsigned char multi_nop_pattern[] =
356 { 0x70, 0x00, 0xf0, 0x00 };
357 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
367 assemble_nop (opcode)
370 char * f = frag_more (2);
371 md_number_to_chars (f, opcode, 2);
374 /* If the last instruction was the first of 2 16 bit insns,
375 output a nop to move the PC to a 32 bit boundary.
377 This is done via an alignment specification since branch relaxing
378 may make it unnecessary.
380 Internally, we need to output one of these each time a 32 bit insn is
381 seen after an insn that is relaxable. */
387 (void) m32r_do_align (2, NULL, 0, 0);
388 prev_insn.insn = NULL;
389 seen_relaxable_p = 0;
392 /* Record the symbol so that when we output the insn, we can create
393 a symbol that is at the start of the instruction. This is used
394 to emit the label for the start of a breakpoint without causing
395 the assembler to emit a NOP if the previous instruction was a
396 16 bit instruction. */
404 register char *end_name;
405 register symbolS *symbolP;
406 register sym_linkS *link;
408 name = input_line_pointer;
409 delim = get_symbol_end ();
410 end_name = input_line_pointer;
412 if ((symbolP = symbol_find (name)) == NULL
413 && (symbolP = md_undefined_symbol (name)) == NULL)
415 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
418 symbol_table_insert (symbolP);
419 if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section)
420 /* xgettext:c-format */
421 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
425 link = (sym_linkS *) xmalloc (sizeof (sym_linkS));
426 link->symbol = symbolP;
427 link->next = debug_sym_link;
428 debug_sym_link = link;
433 demand_empty_rest_of_line ();
436 /* Second pass to expanding the debug symbols, go through linked
437 list of symbols and reassign the address. */
440 expand_debug_syms (syms, align)
444 char *save_input_line = input_line_pointer;
445 sym_linkS *next_syms;
451 (void) m32r_do_align (align, NULL, 0, 0);
452 for (; syms != (sym_linkS *)0; syms = next_syms)
454 symbolS *symbolP = syms->symbol;
455 next_syms = syms->next;
456 input_line_pointer = ".\n";
457 pseudo_set (symbolP);
461 input_line_pointer = save_input_line;
464 /* Cover function to fill_insn called after a label and at end of assembly.
465 The result is always 1: we're called in a conditional to see if the
466 current line is a label. */
469 m32r_fill_insn (done)
472 if (prev_seg != NULL)
475 subsegT subseg = now_subseg;
477 subseg_set (prev_seg, prev_subseg);
481 subseg_set (seg, subseg);
494 /* Initialize the `cgen' interface. */
496 /* This is a callback from cgen to gas to parse operands. */
497 cgen_parse_operand_fn = cgen_parse_operand;
499 /* Set the machine number and endian. */
500 CGEN_SYM (init_asm) (0 /* mach number */,
502 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
504 #if 0 /* not supported yet */
505 /* If a runtime cpu description file was provided, parse it. */
506 if (m32r_cpu_desc != NULL)
510 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
512 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
516 /* Save the current subseg so we can restore it [it's the default one and
517 we don't want the initial section to be .sbss]. */
521 /* The sbss section is for local .scomm symbols. */
522 sbss_section = subseg_new (".sbss", 0);
524 /* This is copied from perform_an_assembly_pass. */
525 applicable = bfd_applicable_section_flags (stdoutput);
526 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
528 #if 0 /* What does this do? [see perform_an_assembly_pass] */
529 seg_info (bss_section)->bss = 1;
532 subseg_set (seg, subseg);
534 /* We must construct a fake section similar to bfd_com_section
535 but with the name .scommon. */
536 scom_section = bfd_com_section;
537 scom_section.name = ".scommon";
538 scom_section.output_section = & scom_section;
539 scom_section.symbol = & scom_symbol;
540 scom_section.symbol_ptr_ptr = & scom_section.symbol;
541 scom_symbol = * bfd_com_section.symbol;
542 scom_symbol.name = ".scommon";
543 scom_symbol.section = & scom_section;
545 /* start-sanitize-m32rx */
546 allow_m32rx (enable_m32rx);
547 /* end-sanitize-m32rx */
550 /* start-sanitize-m32rx */
552 #define OPERAND_IS_COND_BIT(operand, indices, index) \
553 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
554 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
555 && (indices [index] == 0 || indices [index] == 1)))
557 /* Returns true if an output of instruction 'a' is referenced by an operand
558 of instruction 'b'. If 'check_outputs' is true then b's outputs are
559 checked, otherwise its inputs are examined. */
562 first_writes_to_seconds_operands (a, b, check_outputs)
565 const int check_outputs;
567 const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn);
568 const CGEN_OPERAND_INSTANCE * b_ops = CGEN_INSN_OPERANDS (b->insn);
571 /* If at least one of the instructions takes no operands, then there is
572 nothing to check. There really are instructions without operands,
574 if (a_operands == NULL || b_ops == NULL)
577 /* Scan the operand list of 'a' looking for an output operand. */
579 CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
580 a_index ++, a_operands ++)
582 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT)
585 const CGEN_OPERAND_INSTANCE * b_operands = b_ops;
588 The Condition bit 'C' is a shadow of the CBR register (control
589 register 1) and also a shadow of bit 31 of the program status
590 word (control register 0). For now this is handled here, rather
593 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
595 /* Scan operand list of 'b' looking for another reference to the
596 condition bit, which goes in the right direction. */
598 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
599 b_index ++, b_operands ++)
601 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
602 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
603 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
609 /* Scan operand list of 'b' looking for an operand that
610 references the same hardware element, and which goes in the
613 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
614 b_index ++, b_operands ++)
616 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
617 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
618 && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands))
619 && (a->indices [a_index] == b->indices [b_index]))
629 /* Returns true if the insn can (potentially) alter the program counter. */
635 #if 0 /* Once PC operands are working.... */
636 const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn);
638 if (a_operands == NULL)
641 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END)
643 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL
644 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
650 if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
651 || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
657 /* Returns NULL if the two 16 bit insns can be executed in parallel,
658 otherwise it returns a pointer to an error message explaining why not. */
661 can_make_parallel (a, b)
668 /* Make sure the instructions are the right length. */
669 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
670 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
673 if (first_writes_to_seconds_operands (a, b, true))
674 return _("Instructions write to the same destination register.");
676 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
677 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
679 /* Make sure that the instructions use the correct execution pipelines. */
680 if ( a_pipe == PIPE_NONE
681 || b_pipe == PIPE_NONE)
682 return _("Instructions do not use parallel execution pipelines.");
684 /* Leave this test for last, since it is the only test that can
685 go away if the instructions are swapped, and we want to make
686 sure that any other errors are detected before this happens. */
687 if ( a_pipe == PIPE_S
689 return _("Instructions share the same execution pipeline");
697 make_parallel (buffer)
698 cgen_insn_t * buffer;
700 /* Force the top bit of the second insn to be set. */
704 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
706 value = bfd_getb16 ((bfd_byte *) buffer);
708 bfd_putb16 (value, (char *) buffer);
712 value = bfd_getl16 ((bfd_byte *) buffer);
714 bfd_putl16 (value, (char *) buffer);
721 make_parallel (buffer)
724 /* Force the top bit of the second insn to be set. */
726 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
729 #endif /* ! CGEN_INT_INSN */
732 assemble_parallel_insn (str, str2)
741 * str2 = 0; /* Seperate the two instructions. */
743 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
744 so that the parallel instruction will start on a 32 bit boundary. */
748 first.debug_sym_link = debug_sym_link;
749 debug_sym_link = (sym_linkS *)0;
751 /* Parse the first instruction. */
752 if (! (first.insn = CGEN_SYM (assemble_insn)
753 (str, & first.fields, first.buffer, & errmsg)))
760 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_SPECIAL))
762 /* xgettext:c-format */
763 as_bad (_("unknown instruction '%s'"), str);
766 else if (! enable_m32rx
767 /* FIXME: Need standard macro to perform this test. */
768 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
770 /* xgettext:c-format */
771 as_bad (_("instruction '%s' is for the M32RX only"), str);
775 /* Check to see if this is an allowable parallel insn. */
776 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
778 /* xgettext:c-format */
779 as_bad (_("instruction '%s' cannot be executed in parallel."), str);
783 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
784 str3 = str; /* Save the original string pointer. */
785 str = str2 + 2; /* Advanced past the parsed string. */
786 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
788 /* Preserve any fixups that have been generated and reset the list to empty. */
791 /* Get the indices of the operands of the instruction. */
792 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
793 doesn't seem right. Perhaps allow passing fields like we do insn. */
794 /* FIXME: ALIAS insns do not have operands, so we use this function
795 to find the equivalent insn and overwrite the value stored in our
796 structure. We still need the original insn, however, since this
797 may have certain attributes that are not present in the unaliased
798 version (eg relaxability). When aliases behave differently this
799 may have to change. */
800 first.orig_insn = first.insn;
801 first.insn = m32r_cgen_lookup_get_insn_operands
802 (NULL, bfd_getb16 ((char *) first.buffer), 16, first.indices);
804 if (first.insn == NULL)
805 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for first insn"));
807 second.debug_sym_link = NULL;
809 /* Parse the second instruction. */
810 if (! (second.insn = CGEN_SYM (assemble_insn)
811 (str, & second.fields, second.buffer, & errmsg)))
819 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_SPECIAL))
821 /* xgettext:c-format */
822 as_bad (_("unknown instruction '%s'"), str);
825 else if (! enable_m32rx
826 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
828 /* xgettext:c-format */
829 as_bad (_("instruction '%s' is for the M32RX only"), str);
833 /* Check to see if this is an allowable parallel insn. */
834 if (CGEN_INSN_ATTR (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
836 /* xgettext:c-format */
837 as_bad (_("instruction '%s' cannot be executed in parallel."), str);
843 if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
844 && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
846 /* xgettext:c-format */
847 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
852 /* Get the indices of the operands of the instruction. */
853 second.orig_insn = second.insn;
854 second.insn = m32r_cgen_lookup_get_insn_operands
855 (NULL, bfd_getb16 ((char *) second.buffer), 16, second.indices);
857 if (second.insn == NULL)
858 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for second insn"));
860 /* We assume that if the first instruction writes to a register that is
861 read by the second instruction it is because the programmer intended
862 this to happen, (after all they have explicitly requested that these
863 two instructions be executed in parallel). Although if the global
864 variable warn_explicit_parallel_conflicts is true then we do generate
865 a warning message. Similarly we assume that parallel branch and jump
866 instructions are deliberate and should not produce errors. */
868 if (warn_explicit_parallel_conflicts)
870 if (first_writes_to_seconds_operands (& first, & second, false))
871 /* xgettext:c-format */
872 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
874 if (first_writes_to_seconds_operands (& second, & first, false))
875 /* xgettext:c-format */
876 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
879 if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
881 /* Get the fixups for the first instruction. */
885 expand_debug_syms (first.debug_sym_link, 1);
886 cgen_asm_finish_insn (first.orig_insn, first.buffer,
887 CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
889 /* Force the top bit of the second insn to be set. */
890 make_parallel (second.buffer);
892 /* Get its fixups. */
893 cgen_restore_fixups ();
896 expand_debug_syms (second.debug_sym_link, 1);
897 cgen_asm_finish_insn (second.orig_insn, second.buffer,
898 CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
900 /* Try swapping the instructions to see if they work that way. */
901 else if (can_make_parallel (& second, & first) == NULL)
903 /* Write out the second instruction first. */
904 expand_debug_syms (second.debug_sym_link, 1);
905 cgen_asm_finish_insn (second.orig_insn, second.buffer,
906 CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
908 /* Force the top bit of the first instruction to be set. */
909 make_parallel (first.buffer);
911 /* Get the fixups for the first instruction. */
912 cgen_restore_fixups ();
914 /* Write out the first instruction. */
915 expand_debug_syms (first.debug_sym_link, 1);
916 cgen_asm_finish_insn (first.orig_insn, first.buffer,
917 CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
921 as_bad ("'%s': %s", str2, errmsg);
925 /* Set these so m32r_fill_insn can use them. */
927 prev_subseg = now_subseg;
930 /* end-sanitize-m32rx */
941 /* Initialize GAS's cgen interface for a new instruction. */
942 cgen_asm_init_parse ();
944 /* start-sanitize-m32rx */
945 /* Look for a parallel instruction seperator. */
946 if ((str2 = strstr (str, "||")) != NULL)
948 assemble_parallel_insn (str, str2);
951 /* end-sanitize-m32rx */
953 insn.debug_sym_link = debug_sym_link;
954 debug_sym_link = (sym_linkS *)0;
956 insn.insn = CGEN_SYM (assemble_insn)
957 (str, & insn.fields, insn.buffer, & errmsg);
965 /* start-sanitize-m32rx */
967 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_SPECIAL))
969 /* xgettext:c-format */
970 as_bad (_("unknown instruction '%s'"), str);
973 else if (! enable_m32rx
974 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
976 /* xgettext:c-format */
977 as_bad (_("instruction '%s' is for the M32RX only"), str);
980 /* end-sanitize-m32rx */
982 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
984 /* 32 bit insns must live on 32 bit boundaries. */
985 if (prev_insn.insn || seen_relaxable_p)
987 /* ??? If calling fill_insn too many times turns us into a memory
988 pig, can we call assemble_nop instead of !seen_relaxable_p? */
992 expand_debug_syms (insn.debug_sym_link, 2);
994 /* Doesn't really matter what we pass for RELAX_P here. */
995 cgen_asm_finish_insn (insn.insn, insn.buffer,
996 CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
1000 int on_32bit_boundary_p;
1001 /* start-sanitize-m32rx */
1003 /* end-sanitize-m32rx */
1005 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
1008 insn.orig_insn = insn.insn;
1009 /* start-sanitize-m32rx */
1012 /* Get the indices of the operands of the instruction.
1013 FIXME: See assemble_parallel for notes on orig_insn. */
1014 insn.insn = m32r_cgen_lookup_get_insn_operands
1015 (NULL, bfd_getb16 ((char *) insn.buffer), 16, insn.indices);
1017 if (insn.insn == NULL)
1018 as_fatal (_("internal error: m32r_cgen_get_insn_operands failed"));
1020 /* end-sanitize-m32rx */
1022 /* Compute whether we're on a 32 bit boundary or not.
1023 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1024 on_32bit_boundary_p = prev_insn.insn == NULL;
1026 /* start-sanitize-m32rx */
1027 /* Look to see if this instruction can be combined with the
1028 previous instruction to make one, parallel, 32 bit instruction.
1029 If the previous instruction (potentially) changed the flow of
1030 program control, then it cannot be combined with the current
1031 instruction. If the current instruction is relaxable, then it
1032 might be replaced with a longer version, so we cannot combine it.
1033 Also if the output of the previous instruction is used as an
1034 input to the current instruction then it cannot be combined.
1035 Otherwise call can_make_parallel() with both orderings of the
1036 instructions to see if they can be combined. */
1037 if ( ! on_32bit_boundary_p
1040 && CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
1041 && ! writes_to_pc (& prev_insn)
1042 && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
1045 if (can_make_parallel (& prev_insn, & insn) == NULL)
1046 make_parallel (insn.buffer);
1047 else if (can_make_parallel (& insn, & prev_insn) == NULL)
1050 /* end-sanitize-m32rx */
1052 expand_debug_syms (insn.debug_sym_link, 1);
1058 /* Ensure each pair of 16 bit insns is in the same frag. */
1061 cgen_asm_finish_insn (insn.orig_insn, insn.buffer,
1062 CGEN_FIELDS_BITSIZE (& insn.fields),
1063 1 /*relax_p*/, &fi);
1064 insn.addr = fi.addr;
1065 insn.frag = fi.frag;
1066 insn.num_fixups = fi.num_fixups;
1067 for (i = 0; i < fi.num_fixups; ++i)
1068 insn.fixups[i] = fi.fixups[i];
1071 /* start-sanitize-m32rx */
1076 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1078 /* Swap the two insns */
1079 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
1080 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
1082 make_parallel (insn.addr);
1084 /* Swap any relaxable frags recorded for the two insns. */
1085 /* FIXME: Clarify. relaxation precludes parallel insns */
1086 if (prev_insn.frag->fr_opcode == prev_insn.addr)
1087 prev_insn.frag->fr_opcode = insn.addr;
1088 else if (insn.frag->fr_opcode == insn.addr)
1089 insn.frag->fr_opcode = prev_insn.addr;
1091 /* Update the addresses in any fixups.
1092 Note that we don't have to handle the case where each insn is in
1093 a different frag as we ensure they're in the same frag above. */
1094 for (i = 0; i < prev_insn.num_fixups; ++i)
1095 prev_insn.fixups[i]->fx_where += 2;
1096 for (i = 0; i < insn.num_fixups; ++i)
1097 insn.fixups[i]->fx_where -= 2;
1099 /* end-sanitize-m32rx */
1101 /* Keep track of whether we've seen a pair of 16 bit insns.
1102 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1103 if (on_32bit_boundary_p)
1106 prev_insn.insn = NULL;
1108 /* If the insn needs the following one to be on a 32 bit boundary
1109 (e.g. subroutine calls), fill this insn's slot. */
1110 if (on_32bit_boundary_p
1111 && CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
1114 /* If this is a relaxable insn (can be replaced with a larger version)
1115 mark the fact so that we can emit an alignment directive for a
1116 following 32 bit insn if we see one. */
1117 if (CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
1118 seen_relaxable_p = 1;
1121 /* Set these so m32r_fill_insn can use them. */
1123 prev_subseg = now_subseg;
1126 /* The syntax in the manual says constants begin with '#'.
1127 We just ignore it. */
1130 md_operand (expressionP)
1131 expressionS * expressionP;
1133 if (* input_line_pointer == '#')
1135 input_line_pointer ++;
1136 expression (expressionP);
1141 md_section_align (segment, size)
1145 int align = bfd_get_section_alignment (stdoutput, segment);
1146 return ((size + (1 << align) - 1) & (-1 << align));
1150 md_undefined_symbol (name)
1156 /* .scomm pseudo-op handler.
1158 This is a new pseudo-op to handle putting objects in .scommon.
1159 By doing this the linker won't need to do any work and more importantly
1160 it removes the implicit -G arg necessary to correctly link the object file.
1167 register char * name;
1171 register symbolS * symbolP;
1175 name = input_line_pointer;
1176 c = get_symbol_end ();
1178 /* just after name is now '\0' */
1179 p = input_line_pointer;
1182 if (* input_line_pointer != ',')
1184 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1185 ignore_rest_of_line ();
1189 input_line_pointer ++; /* skip ',' */
1190 if ((size = get_absolute_expression ()) < 0)
1192 /* xgettext:c-format */
1193 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
1194 ignore_rest_of_line ();
1198 /* The third argument to .scomm is the alignment. */
1199 if (* input_line_pointer != ',')
1203 ++ input_line_pointer;
1204 align = get_absolute_expression ();
1207 as_warn (_("ignoring bad alignment"));
1211 /* Convert to a power of 2 alignment. */
1214 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
1218 as_bad (_("Common alignment not a power of 2"));
1219 ignore_rest_of_line ();
1227 symbolP = symbol_find_or_make (name);
1230 if (S_IS_DEFINED (symbolP))
1232 /* xgettext:c-format */
1233 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1234 S_GET_NAME (symbolP));
1235 ignore_rest_of_line ();
1239 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
1241 /* xgettext:c-format */
1242 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1243 S_GET_NAME (symbolP),
1244 (long) S_GET_VALUE (symbolP),
1247 ignore_rest_of_line ();
1253 segT old_sec = now_seg;
1254 int old_subsec = now_subseg;
1257 record_alignment (sbss_section, align2);
1258 subseg_set (sbss_section, 0);
1261 frag_align (align2, 0, 0);
1263 if (S_GET_SEGMENT (symbolP) == sbss_section)
1264 symbolP->sy_frag->fr_symbol = 0;
1266 symbolP->sy_frag = frag_now;
1268 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
1271 S_SET_SIZE (symbolP, size);
1272 S_SET_SEGMENT (symbolP, sbss_section);
1273 S_CLEAR_EXTERNAL (symbolP);
1274 subseg_set (old_sec, old_subsec);
1278 S_SET_VALUE (symbolP, (valueT) size);
1279 S_SET_ALIGN (symbolP, align2);
1280 S_SET_EXTERNAL (symbolP);
1281 S_SET_SEGMENT (symbolP, & scom_section);
1284 demand_empty_rest_of_line ();
1287 /* Interface to relax_segment. */
1289 /* FIXME: Build table by hand, get it working, then machine generate. */
1291 const relax_typeS md_relax_table[] =
1294 1) most positive reach of this state,
1295 2) most negative reach of this state,
1296 3) how many bytes this mode will add to the size of the current frag
1297 4) which index into the table to try if we can't fit into this one. */
1299 /* The first entry must be unused because an `rlx_more' value of zero ends
1303 /* The displacement used by GAS is from the end of the 2 byte insn,
1304 so we subtract 2 from the following. */
1305 /* 16 bit insn, 8 bit disp -> 10 bit range.
1306 This doesn't handle a branch in the right slot at the border:
1307 the "& -4" isn't taken into account. It's not important enough to
1308 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1310 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1311 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1312 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1313 /* Same thing, but with leading nop for alignment. */
1314 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1318 m32r_relax_frag (fragP, stretch)
1322 /* Address of branch insn. */
1323 long address = fragP->fr_address + fragP->fr_fix - 2;
1326 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1327 if (fragP->fr_subtype == 2)
1329 if ((address & 3) != 0)
1331 fragP->fr_subtype = 3;
1335 else if (fragP->fr_subtype == 3)
1337 if ((address & 3) == 0)
1339 fragP->fr_subtype = 2;
1345 growth = relax_frag (fragP, stretch);
1347 /* Long jump on odd halfword boundary? */
1348 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1350 fragP->fr_subtype = 3;
1358 /* Return an initial guess of the length by which a fragment must grow to
1359 hold a branch to reach its destination.
1360 Also updates fr_type/fr_subtype as necessary.
1362 Called just before doing relaxation.
1363 Any symbol that is now undefined will not become defined.
1364 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1365 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1366 Although it may not be explicit in the frag, pretend fr_var starts with a
1370 md_estimate_size_before_relax (fragP, segment)
1374 int old_fr_fix = fragP->fr_fix;
1375 char * opcode = fragP->fr_opcode;
1377 /* The only thing we have to handle here are symbols outside of the
1378 current segment. They may be undefined or in a different segment in
1379 which case linker scripts may place them anywhere.
1380 However, we can't finish the fragment here and emit the reloc as insn
1381 alignment requirements may move the insn about. */
1383 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1385 /* The symbol is undefined in this segment.
1386 Change the relaxation subtype to the max allowable and leave
1387 all further handling to md_convert_frag. */
1388 fragP->fr_subtype = 2;
1390 #if 0 /* Can't use this, but leave in for illustration. */
1391 /* Change 16 bit insn to 32 bit insn. */
1394 /* Increase known (fixed) size of fragment. */
1397 /* Create a relocation for it. */
1398 fix_new (fragP, old_fr_fix, 4,
1400 fragP->fr_offset, 1 /* pcrel */,
1401 /* FIXME: Can't use a real BFD reloc here.
1402 cgen_md_apply_fix3 can't handle it. */
1403 BFD_RELOC_M32R_26_PCREL);
1405 /* Mark this fragment as finished. */
1409 const CGEN_INSN * insn;
1412 /* Update the recorded insn.
1413 Fortunately we don't have to look very far.
1414 FIXME: Change this to record in the instruction the next higher
1415 relaxable insn to use. */
1416 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1418 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1419 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1421 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1427 fragP->fr_cgen.insn = insn;
1433 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1436 /* *fragP has been relaxed to its final size, and now needs to have
1437 the bytes inside it modified to conform to the new size.
1439 Called after relaxation is finished.
1440 fragP->fr_type == rs_machine_dependent.
1441 fragP->fr_subtype is the subtype of what the address relaxed to. */
1444 md_convert_frag (abfd, sec, fragP)
1450 char * displacement;
1456 opcode = fragP->fr_opcode;
1458 /* Address opcode resides at in file space. */
1459 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1461 switch (fragP->fr_subtype)
1465 displacement = & opcode[1];
1470 displacement = & opcode[1];
1473 opcode[2] = opcode[0] | 0x80;
1474 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1475 opcode_address += 2;
1477 displacement = & opcode[3];
1483 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1485 /* symbol must be resolved by linker */
1486 if (fragP->fr_offset & 3)
1487 as_warn (_("Addend to unresolved symbol not on word boundary."));
1488 addend = fragP->fr_offset >> 2;
1492 /* Address we want to reach in file space. */
1493 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1494 target_address += fragP->fr_symbol->sy_frag->fr_address;
1495 addend = (target_address - (opcode_address & -4)) >> 2;
1498 /* Create a relocation for symbols that must be resolved by the linker.
1499 Otherwise output the completed insn. */
1501 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1503 assert (fragP->fr_subtype != 1);
1504 assert (fragP->fr_cgen.insn != 0);
1505 cgen_record_fixup (fragP,
1506 /* Offset of branch insn in frag. */
1507 fragP->fr_fix + extension - 4,
1508 fragP->fr_cgen.insn,
1510 /* FIXME: quick hack */
1512 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1514 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1516 fragP->fr_cgen.opinfo,
1517 fragP->fr_symbol, fragP->fr_offset);
1520 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1522 md_number_to_chars (displacement, (valueT) addend,
1523 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1525 fragP->fr_fix += extension;
1528 /* Functions concerning relocs. */
1530 /* The location from which a PC relative jump should be calculated,
1531 given a PC relative reloc. */
1534 md_pcrel_from_section (fixP, sec)
1538 if (fixP->fx_addsy != (symbolS *) NULL
1539 && (! S_IS_DEFINED (fixP->fx_addsy)
1540 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1542 /* The symbol is undefined (or is defined but not in this section).
1543 Let the linker figure it out. */
1547 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1550 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1551 Returns BFD_RELOC_NONE if no reloc type can be found.
1552 *FIXP may be modified if desired. */
1554 bfd_reloc_code_real_type
1555 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1556 const CGEN_INSN * insn;
1557 const CGEN_OPERAND * operand;
1560 switch (CGEN_OPERAND_TYPE (operand))
1562 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1563 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1564 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1565 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1566 case M32R_OPERAND_HI16 :
1567 case M32R_OPERAND_SLO16 :
1568 case M32R_OPERAND_ULO16 :
1569 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1570 if (fixP->tc_fix_data.opinfo != 0)
1571 return fixP->tc_fix_data.opinfo;
1574 return BFD_RELOC_NONE;
1577 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1580 m32r_record_hi16 (reloc_type, fixP, seg)
1585 struct m32r_hi_fixup * hi_fixup;
1587 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1588 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1590 hi_fixup = ((struct m32r_hi_fixup *)
1591 xmalloc (sizeof (struct m32r_hi_fixup)));
1592 hi_fixup->fixp = fixP;
1593 hi_fixup->seg = now_seg;
1594 hi_fixup->next = m32r_hi_fixup_list;
1596 m32r_hi_fixup_list = hi_fixup;
1599 /* Called while parsing an instruction to create a fixup.
1600 We need to check for HI16 relocs and queue them up for later sorting. */
1603 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1606 const CGEN_INSN * insn;
1608 const CGEN_OPERAND * operand;
1612 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1613 operand, opinfo, exp);
1615 switch (CGEN_OPERAND_TYPE (operand))
1617 case M32R_OPERAND_HI16 :
1618 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1619 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1620 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1621 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1628 /* Return BFD reloc type from opinfo field in a fixS.
1629 It's tricky using fx_r_type in m32r_frob_file because the values
1630 are BFD_RELOC_UNUSED + operand number. */
1631 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1633 /* Sort any unmatched HI16 relocs so that they immediately precede
1634 the corresponding LO16 reloc. This is called before md_apply_fix and
1640 struct m32r_hi_fixup * l;
1642 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1644 segment_info_type * seginfo;
1647 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1648 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1650 /* Check quickly whether the next fixup happens to be a matching low. */
1651 if (l->fixp->fx_next != NULL
1652 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1653 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1654 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1657 /* Look through the fixups for this segment for a matching `low'.
1658 When we find one, move the high/shigh just in front of it. We do
1659 this in two passes. In the first pass, we try to find a
1660 unique `low'. In the second pass, we permit multiple high's
1661 relocs for a single `low'. */
1662 seginfo = seg_info (l->seg);
1663 for (pass = 0; pass < 2; pass++)
1669 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1671 /* Check whether this is a `low' fixup which matches l->fixp. */
1672 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1673 && f->fx_addsy == l->fixp->fx_addsy
1674 && f->fx_offset == l->fixp->fx_offset
1677 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1678 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1679 || prev->fx_addsy != f->fx_addsy
1680 || prev->fx_offset != f->fx_offset))
1684 /* Move l->fixp before f. */
1685 for (pf = &seginfo->fix_root;
1687 pf = & (* pf)->fx_next)
1688 assert (* pf != NULL);
1690 * pf = l->fixp->fx_next;
1692 l->fixp->fx_next = f;
1694 seginfo->fix_root = l->fixp;
1696 prev->fx_next = l->fixp;
1708 && warn_unmatched_high)
1709 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1710 _("Unmatched high/shigh reloc"));
1715 /* See whether we need to force a relocation into the output file.
1716 This is used to force out switch and PC relative relocations when
1720 m32r_force_relocation (fix)
1726 return (fix->fx_pcrel
1730 /* Write a value out to the object file, using the appropriate endianness. */
1733 md_number_to_chars (buf, val, n)
1738 if (target_big_endian)
1739 number_to_chars_bigendian (buf, val, n);
1741 number_to_chars_littleendian (buf, val, n);
1744 /* Turn a string in input_line_pointer into a floating point constant of type
1745 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1746 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1749 /* Equal to MAX_PRECISION in atof-ieee.c */
1750 #define MAX_LITTLENUMS 6
1753 md_atof (type, litP, sizeP)
1760 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1761 LITTLENUM_TYPE * wordP;
1763 char * atof_ieee ();
1781 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1785 return _("Bad call to md_atof()");
1788 t = atof_ieee (input_line_pointer, type, words);
1790 input_line_pointer = t;
1791 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1793 if (target_big_endian)
1795 for (i = 0; i < prec; i++)
1797 md_number_to_chars (litP, (valueT) words[i],
1798 sizeof (LITTLENUM_TYPE));
1799 litP += sizeof (LITTLENUM_TYPE);
1804 for (i = prec - 1; i >= 0; i--)
1806 md_number_to_chars (litP, (valueT) words[i],
1807 sizeof (LITTLENUM_TYPE));
1808 litP += sizeof (LITTLENUM_TYPE);
1816 m32r_elf_section_change_hook ()
1818 /* If we have reached the end of a section and we have just emitted a
1819 16 bit insn, then emit a nop to make sure that the section ends on
1820 a 32 bit boundary. */
1822 if (prev_insn.insn || seen_relaxable_p)
1823 (void) m32r_fill_insn (0);