1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 const CGEN_INSN * insn;
32 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
34 char buffer [CGEN_MAX_INSN_SIZE];
38 int indices [MAX_OPERAND_INSTANCES];
42 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
43 boundary (i.e. was the first of two 16 bit insns). */
44 static m32r_insn prev_insn;
46 /* Non-zero if we've seen a relaxable insn since the last 32 bit
48 static int seen_relaxable_p = 0;
50 /* Non-zero if -relax specified, in which case sufficient relocs are output
51 for the linker to do relaxing.
52 We do simple forms of relaxing internally, but they are always done.
53 This flag does not apply to them. */
54 static int m32r_relax;
56 /* If non-NULL, pointer to cpu description file to read.
57 This allows runtime additions to the assembler. */
58 static char * m32r_cpu_desc;
60 /* start-sanitize-m32rx */
61 /* Non-zero if -m32rx has been specified, in which case support for the
62 extended M32RX instruction set should be enabled. */
63 static int enable_m32rx = 0;
65 /* Non-zero if the programmer should be warned when an explicit parallel
66 instruction might have constraint violations. */
67 static int warn_explicit_parallel_conflicts = 1;
68 /* end-sanitize-m32rx */
70 /* stuff for .scomm symbols. */
71 static segT sbss_section;
72 static asection scom_section;
73 static asymbol scom_symbol;
75 const char comment_chars[] = ";";
76 const char line_comment_chars[] = "#";
77 const char line_separator_chars[] = "";
78 const char EXP_CHARS[] = "eE";
79 const char FLT_CHARS[] = "dD";
81 /* Relocations against symbols are done in two
82 parts, with a HI relocation and a LO relocation. Each relocation
83 has only 16 bits of space to store an addend. This means that in
84 order for the linker to handle carries correctly, it must be able
85 to locate both the HI and the LO relocation. This means that the
86 relocations must appear in order in the relocation table.
88 In order to implement this, we keep track of each unmatched HI
89 relocation. We then sort them so that they immediately precede the
90 corresponding LO relocation. */
94 struct m32r_hi_fixup * next; /* Next HI fixup. */
95 fixS * fixp; /* This fixup. */
96 segT seg; /* The section this fixup is in. */
100 /* The list of unmatched HI relocs. */
102 static struct m32r_hi_fixup * m32r_hi_fixup_list;
105 /* start-sanitize-m32rx */
112 if (stdoutput != NULL)
113 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
114 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
116 /* end-sanitize-m32rx */
118 const char * md_shortopts = "";
120 struct option md_longopts[] =
122 /* start-sanitize-m32rx */
123 #define OPTION_M32RX (OPTION_MD_BASE)
124 {"m32rx", no_argument, NULL, OPTION_M32RX},
125 #define OPTION_WARN (OPTION_MD_BASE + 1)
126 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN},
127 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
128 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
129 /* end-sanitize-m32rx */
131 #if 0 /* not supported yet */
132 #define OPTION_RELAX (OPTION_MD_BASE + 3)
133 {"relax", no_argument, NULL, OPTION_RELAX},
134 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
135 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
138 {NULL, no_argument, NULL, 0}
140 size_t md_longopts_size = sizeof (md_longopts);
143 md_parse_option (c, arg)
149 /* start-sanitize-m32rx */
155 warn_explicit_parallel_conflicts = 1;
159 warn_explicit_parallel_conflicts = 0;
161 /* end-sanitize-m32rx */
163 #if 0 /* not supported yet */
167 case OPTION_CPU_DESC:
178 md_show_usage (stream)
181 fprintf (stream, "M32R/X options:\n");
182 /* start-sanitize-m32rx */
184 --m32rx support the extended m32rx instruction set\n");
187 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n");
189 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
190 /* end-sanitize-m32rx */
194 --relax create linker relaxable code\n");
196 --cpu-desc provide runtime cpu description file\n");
200 static void fill_insn PARAMS ((int));
201 static void m32r_scomm PARAMS ((int));
203 /* Set by md_assemble for use by m32r_fill_insn. */
204 static subsegT prev_subseg;
205 static segT prev_seg;
207 /* The target specific pseudo-ops which we support. */
208 const pseudo_typeS md_pseudo_table[] =
211 { "fillinsn", fill_insn, 0 },
212 { "scomm", m32r_scomm, 0 },
213 /* start-sanitize-m32rx */
214 { "m32r", allow_m32rx, 0},
215 { "m32rx", allow_m32rx, 1},
216 /* end-sanitize-m32rx */
220 /* FIXME: Should be machine generated. */
221 #define NOP_INSN 0x7000
222 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
224 /* When we align the .text section, insert the correct NOP pattern.
225 N is the power of 2 alignment. LEN is the length of pattern FILL.
226 MAX is the maximum number of characters to skip when doing the alignment,
227 or 0 if there is no maximum. */
230 m32r_do_align (n, fill, len, max)
236 if ((fill == NULL || (* fill == 0 && len == 1))
237 && (now_seg->flags & SEC_CODE) != 0
238 /* Only do this special handling if aligning to at least a
241 /* Only do this special handling if we're allowed to emit at
243 && (max == 0 || max > 1))
245 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
248 /* First align to a 2 byte boundary, in case there is an odd .byte. */
249 /* FIXME: How much memory will cause gas to use when assembling a big
250 program? Perhaps we can avoid the frag_align call? */
251 frag_align (1, 0, 0);
253 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
255 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
256 /* If doing larger alignments use a repeating sequence of appropriate
260 static const unsigned char multi_nop_pattern[] =
261 { 0x70, 0x00, 0xf0, 0x00 };
262 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
272 assemble_nop (opcode)
275 char * f = frag_more (2);
276 md_number_to_chars (f, opcode, 2);
279 /* If the last instruction was the first of 2 16 bit insns,
280 output a nop to move the PC to a 32 bit boundary.
282 This is done via an alignment specification since branch relaxing
283 may make it unnecessary.
285 Internally, we need to output one of these each time a 32 bit insn is
286 seen after an insn that is relaxable. */
292 (void) m32r_do_align (2, NULL, 0, 0);
293 prev_insn.insn = NULL;
294 seen_relaxable_p = 0;
297 /* Cover function to fill_insn called after a label and at end of assembly.
299 The result is always 1: we're called in a conditional to see if the
300 current line is a label. */
303 m32r_fill_insn (done)
309 if (prev_seg != NULL)
314 subseg_set (prev_seg, prev_subseg);
318 subseg_set (seg, subseg);
331 /* Initialize the `cgen' interface. */
333 /* This is a callback from cgen to gas to parse operands. */
334 cgen_parse_operand_fn = cgen_parse_operand;
336 /* Set the machine number and endian. */
337 CGEN_SYM (init_asm) (0 /* mach number */,
339 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
341 #if 0 /* not supported yet */
342 /* If a runtime cpu description file was provided, parse it. */
343 if (m32r_cpu_desc != NULL)
347 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
349 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
353 /* Save the current subseg so we can restore it [it's the default one and
354 we don't want the initial section to be .sbss]. */
358 /* The sbss section is for local .scomm symbols. */
359 sbss_section = subseg_new (".sbss", 0);
361 /* This is copied from perform_an_assembly_pass. */
362 applicable = bfd_applicable_section_flags (stdoutput);
363 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
365 #if 0 /* What does this do? [see perform_an_assembly_pass] */
366 seg_info (bss_section)->bss = 1;
369 subseg_set (seg, subseg);
371 /* We must construct a fake section similar to bfd_com_section
372 but with the name .scommon. */
373 scom_section = bfd_com_section;
374 scom_section.name = ".scommon";
375 scom_section.output_section = & scom_section;
376 scom_section.symbol = & scom_symbol;
377 scom_section.symbol_ptr_ptr = & scom_section.symbol;
378 scom_symbol = * bfd_com_section.symbol;
379 scom_symbol.name = ".scommon";
380 scom_symbol.section = & scom_section;
382 /* start-sanitize-m32rx */
383 allow_m32rx (enable_m32rx);
384 /* end-sanitize-m32rx */
387 /* start-sanitize-m32rx */
388 #ifdef HAVE_CPU_M32RX
390 /* Returns true if an output of instruction 'a' is referenced by an operand
391 of instruction 'b'. If 'check_outputs' is true then b's outputs are
392 checked, otherwise its inputs are examined. */
394 first_writes_to_seconds_operands (a, b, check_outputs)
397 const int check_outputs;
399 const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn);
400 const CGEN_OPERAND_INSTANCE * b_operands = CGEN_INSN_OPERANDS (b->insn);
403 /* If at least one of the instructions take sno opeands, then there is
404 nothing to check. There really are instructions without operands,
406 if (a_operands == NULL || b_operands == NULL)
409 /* Scan the operand list of 'a' looking for an output operand. */
411 CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
412 a_index ++, a_operands ++)
414 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT)
418 /* Scan operand list of 'b' looking for an operand that references
419 the same hardware element, and which goes in the right direction. */
421 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
422 b_index ++, b_operands ++)
424 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
425 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
426 && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands))
427 && (a->indices [a_index] == b->indices [b_index]))
436 /* Returns true if the insn can (potentially) alter the program counter. */
442 const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn);
444 if (a_operands == NULL)
447 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END)
449 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL
450 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
456 if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
457 || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
463 /* Returns NULL if the two 16 bit insns can be executed in parallel,
464 otherwise it returns a pointer to an error message explaining why not. */
466 can_make_parallel (a, b)
473 /* Make sure the instructions are the right length. */
474 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
475 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
478 if (first_writes_to_seconds_operands (a, b, true))
479 return "Instructions write to the same destination register.";
481 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
482 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
484 /* Make sure that the instructions use the correct execution pipelines. */
485 if ( a_pipe == PIPE_NONE
486 || b_pipe == PIPE_NONE)
487 return "Instructions do not use parallel execution pipelines.";
489 /* Leave this test for last, since it is the only test that can
490 go away if the instructions are swapped, and we want to make
491 sure that any other errors are detected before this happens. */
492 if ( a_pipe == PIPE_S
494 return "Instructions share the same execution pipeline";
501 make_parallel (buffer)
502 cgen_insn_t * buffer;
504 /* Force the top bit of the second insn to be set. */
508 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
510 value = bfd_getb16 ((bfd_byte *) buffer);
512 bfd_putb16 (value, (char *) buffer);
516 value = bfd_getl16 ((bfd_byte *) buffer);
518 bfd_putl16 (value, (char *) buffer);
523 make_parallel (buffer)
526 /* Force the top bit of the second insn to be set. */
528 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
534 assemble_parallel_insn (str, str2)
543 * str2 = 0; /* Seperate the two instructions. */
545 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
546 so that the parallel instruction will start on a 32 bit boundary. */
550 /* Parse the first instruction. */
551 if (! (first.insn = CGEN_SYM (assemble_insn)
552 (str, & first.fields, first.buffer, & errmsg)))
558 /* Check to see if this is an allowable parallel insn. */
559 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
561 as_bad ("instruction '%s' cannot be executed in parallel.", str);
566 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
568 as_bad ("instruction '%s' is for the M32RX only", str);
572 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
573 str3 = str; /* Save the original string pointer. */
574 str = str2 + 2; /* Advanced past the parsed string. */
575 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
577 /* Preserve any fixups that have been generated and reset the list to empty. */
580 /* Get the indicies of the operands of the instruction. */
581 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
582 doesn't seem right. Perhaps allow passing fields like we do insn. */
583 /* FIXME: ALIAS insns do not have operands, so we use this function
584 to find the equivalent insn and overwrite the value stored in our
585 structure. When aliases behave differently this may have to change. */
586 first.insn = m32r_cgen_get_insn_operands (first.insn, bfd_getb16 ((char *) first.buffer), 16,
588 if (first.insn == NULL)
589 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn");
591 /* Parse the second instruction. */
592 if (! (second.insn = CGEN_SYM (assemble_insn)
593 (str, & second.fields, second.buffer, & errmsg)))
601 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
603 as_bad ("instruction '%s' is for the M32RX only", str);
609 if ( strcmp (first.insn->name, "nop") != 0
610 && strcmp (second.insn->name, "nop") != 0)
612 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
617 /* Get the indicies of the operands of the instruction. */
618 second.insn = m32r_cgen_get_insn_operands (second.insn, bfd_getb16 ((char *) second.buffer), 16,
620 if (second.insn == NULL)
621 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn");
623 /* We assume that if the first instruction writes to a register that is
624 read by the second instruction it is because the programmer intended
625 this to happen, (after all they have explicitly requested that these
626 two instructions be executed in parallel). Although if the global
627 variable warn_explicit_parallel_conflicts is true then we do generate
628 a warning message. Similarly we assume that parallel branch and jump
629 instructions are deliberate and should not produce errors. */
631 if (warn_explicit_parallel_conflicts)
633 if (first_writes_to_seconds_operands (& first, & second, false))
634 as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2);
636 if (first_writes_to_seconds_operands (& second, & first, false))
637 as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2);
640 if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
642 /* Get the fixups for the first instruction. */
646 (void) cgen_asm_finish_insn (first.insn, first.buffer,
647 CGEN_FIELDS_BITSIZE (& first.fields));
649 /* Force the top bit of the second insn to be set. */
650 make_parallel (second.buffer);
652 /* Get its fixups. */
653 cgen_restore_fixups ();
656 (void) cgen_asm_finish_insn (second.insn, second.buffer,
657 CGEN_FIELDS_BITSIZE (& second.fields));
659 /* Try swapping the instructions to see if they work that way. */
660 else if (can_make_parallel (& second, & first) == NULL)
662 /* Write out the second instruction first. */
663 (void) cgen_asm_finish_insn (second.insn, second.buffer,
664 CGEN_FIELDS_BITSIZE (& second.fields));
666 /* Force the top bit of the first instruction to be set. */
667 make_parallel (first.buffer);
669 /* Get the fixups for the first instruction. */
670 cgen_restore_fixups ();
672 /* Write out the first instruction. */
673 (void) cgen_asm_finish_insn (first.insn, first.buffer,
674 CGEN_FIELDS_BITSIZE (& first.fields));
678 as_bad ("'%s': %s", str2, errmsg);
682 /* Set these so m32r_fill_insn can use them. */
684 prev_subseg = now_subseg;
689 #endif /* HAVE_CPU_M32RX */
691 /* end-sanitize-m32rx */
702 /* Initialize GAS's cgen interface for a new instruction. */
703 cgen_asm_init_parse ();
705 /* start-sanitize-m32rx */
706 #ifdef HAVE_CPU_M32RX
707 /* Look for a parallel instruction seperator. */
708 if ((str2 = strstr (str, "||")) != NULL)
710 assemble_parallel_insn (str, str2);
714 /* end-sanitize-m32rx */
716 insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
723 /* start-sanitize-m32rx */
724 #ifdef HAVE_CPU_M32RX
725 if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
727 as_bad ("instruction '%s' is for the M32RX only", str);
731 /* end-sanitize-m32rx */
733 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
735 /* 32 bit insns must live on 32 bit boundaries. */
736 if (prev_insn.insn || seen_relaxable_p)
738 /* FIXME: If calling fill_insn too many times turns us into a memory
739 pig, can we call assemble_nop instead of !seen_relaxable_p? */
743 (void) cgen_asm_finish_insn (insn.insn, insn.buffer,
744 CGEN_FIELDS_BITSIZE (& insn.fields));
748 /* start-sanitize-m32rx */
749 /* start-sanitize-phase2-m32rx */
751 /* end-sanitize-phase2-m32rx */
752 /* end-sanitize-m32rx */
754 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
757 /* Get the indicies of the operands of the instruction. */
758 insn.insn = m32r_cgen_get_insn_operands (insn.insn,
759 bfd_getb16 ((char *) insn.buffer),
762 if (insn.insn == NULL)
763 as_fatal ("internal error: m32r_cgen_get_insn_operands failed");
765 /* Keep track of whether we've seen a pair of 16 bit insns.
766 prev_insn.insn is NULL when we're on a 32 bit boundary. */
769 /* start-sanitize-m32rx */
770 /* start-sanitize-phase2-m32rx */
771 #ifdef HAVE_CPU_M32RX
772 /* Look to see if this instruction can be combined with the
773 previous instruction to make one, parallel, 32 bit instruction.
774 If the previous instruction (potentially) changed the flow of
775 program control, then it cannot be combined with the current
776 instruction. Also if the output of the previous instruction
777 is used as an input to the current instruction then it cannot
778 be combined. Otherwise call can_make_parallel() with both
779 orderings of the instructions to see if they can be combined. */
780 if (! writes_to_pc (& prev_insn)
781 && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
784 if (can_make_parallel (& prev_insn, & insn) == NULL)
785 make_parallel (insn.buffer);
786 else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
790 /* end-sanitize-phase2-m32rx */
791 /* end-sanitize-m32rx */
793 prev_insn.insn = NULL;
800 /* Record the frag that might be used by this insn. */
801 insn.frag = frag_now;
802 insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer,
803 CGEN_FIELDS_BITSIZE (& insn.fields));
805 /* start-sanitize-m32rx */
806 /* start-sanitize-phase2-m32rx */
807 #ifdef HAVE_CPU_M32RX
812 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
814 /* Swap the two insns */
815 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
816 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
818 make_parallel (insn.addr);
820 /* Swap any relaxable frags recorded for the two insns. */
821 if (prev_insn.frag->fr_opcode == prev_insn.addr)
823 prev_insn.frag->fr_opcode = insn.addr;
825 else if (insn.frag->fr_opcode == insn.addr)
827 insn.frag->fr_opcode = prev_insn.addr;
830 /* end-sanitize-phase2-m32rx */
832 /* Record where this instruction was assembled. */
833 prev_insn.addr = insn.addr;
834 prev_insn.frag = insn.frag;
836 /* end-sanitize-m32rx */
838 /* If the insn needs the following one to be on a 32 bit boundary
839 (e.g. subroutine calls), fill this insn's slot. */
841 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0)
844 /* If this is a relaxable insn (can be replaced with a larger version)
845 mark the fact so that we can emit an alignment directive for a
846 following 32 bit insn if we see one. */
847 if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0)
848 seen_relaxable_p = 1;
851 /* Set these so m32r_fill_insn can use them. */
853 prev_subseg = now_subseg;
856 /* The syntax in the manual says constants begin with '#'.
857 We just ignore it. */
860 md_operand (expressionP)
861 expressionS * expressionP;
863 if (* input_line_pointer == '#')
865 input_line_pointer ++;
866 expression (expressionP);
871 md_section_align (segment, size)
875 int align = bfd_get_section_alignment (stdoutput, segment);
876 return ((size + (1 << align) - 1) & (-1 << align));
880 md_undefined_symbol (name)
886 /* .scomm pseudo-op handler.
888 This is a new pseudo-op to handle putting objects in .scommon.
889 By doing this the linker won't need to do any work and more importantly
890 it removes the implicit -G arg necessary to correctly link the object file.
897 register char * name;
901 register symbolS * symbolP;
905 name = input_line_pointer;
906 c = get_symbol_end ();
908 /* just after name is now '\0' */
909 p = input_line_pointer;
912 if (* input_line_pointer != ',')
914 as_bad ("Expected comma after symbol-name: rest of line ignored.");
915 ignore_rest_of_line ();
919 input_line_pointer ++; /* skip ',' */
920 if ((size = get_absolute_expression ()) < 0)
922 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
923 ignore_rest_of_line ();
927 /* The third argument to .scomm is the alignment. */
928 if (* input_line_pointer != ',')
932 ++ input_line_pointer;
933 align = get_absolute_expression ();
936 as_warn ("ignoring bad alignment");
940 /* Convert to a power of 2 alignment. */
943 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
947 as_bad ("Common alignment not a power of 2");
948 ignore_rest_of_line ();
956 symbolP = symbol_find_or_make (name);
959 if (S_IS_DEFINED (symbolP))
961 as_bad ("Ignoring attempt to re-define symbol `%s'.",
962 S_GET_NAME (symbolP));
963 ignore_rest_of_line ();
967 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
969 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
970 S_GET_NAME (symbolP),
971 (long) S_GET_VALUE (symbolP),
974 ignore_rest_of_line ();
980 segT old_sec = now_seg;
981 int old_subsec = now_subseg;
984 record_alignment (sbss_section, align2);
985 subseg_set (sbss_section, 0);
988 frag_align (align2, 0, 0);
990 if (S_GET_SEGMENT (symbolP) == sbss_section)
991 symbolP->sy_frag->fr_symbol = 0;
993 symbolP->sy_frag = frag_now;
995 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
998 S_SET_SIZE (symbolP, size);
999 S_SET_SEGMENT (symbolP, sbss_section);
1000 S_CLEAR_EXTERNAL (symbolP);
1001 subseg_set (old_sec, old_subsec);
1005 S_SET_VALUE (symbolP, (valueT) size);
1006 S_SET_ALIGN (symbolP, align2);
1007 S_SET_EXTERNAL (symbolP);
1008 S_SET_SEGMENT (symbolP, & scom_section);
1011 demand_empty_rest_of_line ();
1014 /* Interface to relax_segment. */
1016 /* FIXME: Build table by hand, get it working, then machine generate. */
1018 const relax_typeS md_relax_table[] =
1021 1) most positive reach of this state,
1022 2) most negative reach of this state,
1023 3) how many bytes this mode will add to the size of the current frag
1024 4) which index into the table to try if we can't fit into this one. */
1026 /* The first entry must be unused because an `rlx_more' value of zero ends
1030 /* The displacement used by GAS is from the end of the 2 byte insn,
1031 so we subtract 2 from the following. */
1032 /* 16 bit insn, 8 bit disp -> 10 bit range.
1033 This doesn't handle a branch in the right slot at the border:
1034 the "& -4" isn't taken into account. It's not important enough to
1035 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1037 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1038 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1039 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1040 /* Same thing, but with leading nop for alignment. */
1041 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1045 m32r_relax_frag (fragP, stretch)
1049 /* Address of branch insn. */
1050 long address = fragP->fr_address + fragP->fr_fix - 2;
1053 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1054 if (fragP->fr_subtype == 2)
1056 if ((address & 3) != 0)
1058 fragP->fr_subtype = 3;
1062 else if (fragP->fr_subtype == 3)
1064 if ((address & 3) == 0)
1066 fragP->fr_subtype = 2;
1072 growth = relax_frag (fragP, stretch);
1074 /* Long jump on odd halfword boundary? */
1075 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1077 fragP->fr_subtype = 3;
1085 /* Return an initial guess of the length by which a fragment must grow to
1086 hold a branch to reach its destination.
1087 Also updates fr_type/fr_subtype as necessary.
1089 Called just before doing relaxation.
1090 Any symbol that is now undefined will not become defined.
1091 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1092 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1093 Although it may not be explicit in the frag, pretend fr_var starts with a
1097 md_estimate_size_before_relax (fragP, segment)
1101 int old_fr_fix = fragP->fr_fix;
1102 char * opcode = fragP->fr_opcode;
1104 /* The only thing we have to handle here are symbols outside of the
1105 current segment. They may be undefined or in a different segment in
1106 which case linker scripts may place them anywhere.
1107 However, we can't finish the fragment here and emit the reloc as insn
1108 alignment requirements may move the insn about. */
1110 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1112 /* The symbol is undefined in this segment.
1113 Change the relaxation subtype to the max allowable and leave
1114 all further handling to md_convert_frag. */
1115 fragP->fr_subtype = 2;
1117 #if 0 /* Can't use this, but leave in for illustration. */
1118 /* Change 16 bit insn to 32 bit insn. */
1121 /* Increase known (fixed) size of fragment. */
1124 /* Create a relocation for it. */
1125 fix_new (fragP, old_fr_fix, 4,
1127 fragP->fr_offset, 1 /* pcrel */,
1128 /* FIXME: Can't use a real BFD reloc here.
1129 cgen_md_apply_fix3 can't handle it. */
1130 BFD_RELOC_M32R_26_PCREL);
1132 /* Mark this fragment as finished. */
1136 const CGEN_INSN * insn;
1139 /* Update the recorded insn.
1140 Fortunately we don't have to look very far.
1141 FIXME: Change this to record in the instruction the next higher
1142 relaxable insn to use. */
1143 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1145 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1146 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1148 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1154 fragP->fr_cgen.insn = insn;
1160 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1163 /* *fragP has been relaxed to its final size, and now needs to have
1164 the bytes inside it modified to conform to the new size.
1166 Called after relaxation is finished.
1167 fragP->fr_type == rs_machine_dependent.
1168 fragP->fr_subtype is the subtype of what the address relaxed to. */
1171 md_convert_frag (abfd, sec, fragP)
1177 char * displacement;
1183 opcode = fragP->fr_opcode;
1185 /* Address opcode resides at in file space. */
1186 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1188 switch (fragP->fr_subtype)
1192 displacement = & opcode[1];
1197 displacement = & opcode[1];
1200 opcode[2] = opcode[0] | 0x80;
1201 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1202 opcode_address += 2;
1204 displacement = & opcode[3];
1210 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1212 /* symbol must be resolved by linker */
1213 if (fragP->fr_offset & 3)
1214 as_warn ("Addend to unresolved symbol not on word boundary.");
1215 addend = fragP->fr_offset >> 2;
1219 /* Address we want to reach in file space. */
1220 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1221 target_address += fragP->fr_symbol->sy_frag->fr_address;
1222 addend = (target_address - (opcode_address & -4)) >> 2;
1225 /* Create a relocation for symbols that must be resolved by the linker.
1226 Otherwise output the completed insn. */
1228 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1230 assert (fragP->fr_subtype != 1);
1231 assert (fragP->fr_cgen.insn != 0);
1232 cgen_record_fixup (fragP,
1233 /* Offset of branch insn in frag. */
1234 fragP->fr_fix + extension - 4,
1235 fragP->fr_cgen.insn,
1237 /* FIXME: quick hack */
1239 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1241 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1243 fragP->fr_cgen.opinfo,
1244 fragP->fr_symbol, fragP->fr_offset);
1247 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1249 md_number_to_chars (displacement, (valueT) addend,
1250 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1252 fragP->fr_fix += extension;
1255 /* Functions concerning relocs. */
1257 /* The location from which a PC relative jump should be calculated,
1258 given a PC relative reloc. */
1261 md_pcrel_from_section (fixP, sec)
1265 if (fixP->fx_addsy != (symbolS *) NULL
1266 && (! S_IS_DEFINED (fixP->fx_addsy)
1267 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1269 /* The symbol is undefined (or is defined but not in this section).
1270 Let the linker figure it out. */
1274 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1277 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1278 Returns BFD_RELOC_NONE if no reloc type can be found.
1279 *FIXP may be modified if desired. */
1281 bfd_reloc_code_real_type
1282 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1283 const CGEN_INSN * insn;
1284 const CGEN_OPERAND * operand;
1287 switch (CGEN_OPERAND_TYPE (operand))
1289 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1290 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1291 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1292 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1293 case M32R_OPERAND_HI16 :
1294 case M32R_OPERAND_SLO16 :
1295 case M32R_OPERAND_ULO16 :
1296 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1297 if (fixP->tc_fix_data.opinfo != 0)
1298 return fixP->tc_fix_data.opinfo;
1301 return BFD_RELOC_NONE;
1304 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1307 m32r_record_hi16 (reloc_type, fixP, seg)
1312 struct m32r_hi_fixup * hi_fixup;
1314 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1315 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1317 hi_fixup = ((struct m32r_hi_fixup *)
1318 xmalloc (sizeof (struct m32r_hi_fixup)));
1319 hi_fixup->fixp = fixP;
1320 hi_fixup->seg = now_seg;
1321 hi_fixup->next = m32r_hi_fixup_list;
1323 m32r_hi_fixup_list = hi_fixup;
1326 /* Called while parsing an instruction to create a fixup.
1327 We need to check for HI16 relocs and queue them up for later sorting. */
1330 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1333 const CGEN_INSN * insn;
1335 const CGEN_OPERAND * operand;
1339 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1340 operand, opinfo, exp);
1342 switch (CGEN_OPERAND_TYPE (operand))
1344 case M32R_OPERAND_HI16 :
1345 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1346 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1347 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1348 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1355 /* Return BFD reloc type from opinfo field in a fixS.
1356 It's tricky using fx_r_type in m32r_frob_file because the values
1357 are BFD_RELOC_UNUSED + operand number. */
1358 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1360 /* Sort any unmatched HI16 relocs so that they immediately precede
1361 the corresponding LO16 reloc. This is called before md_apply_fix and
1367 struct m32r_hi_fixup * l;
1369 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1371 segment_info_type * seginfo;
1374 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1375 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1377 /* Check quickly whether the next fixup happens to be a matching low. */
1378 if (l->fixp->fx_next != NULL
1379 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1380 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1381 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1384 /* Look through the fixups for this segment for a matching `low'.
1385 When we find one, move the high/shigh just in front of it. We do
1386 this in two passes. In the first pass, we try to find a
1387 unique `low'. In the second pass, we permit multiple high's
1388 relocs for a single `low'. */
1389 seginfo = seg_info (l->seg);
1390 for (pass = 0; pass < 2; pass++)
1396 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1398 /* Check whether this is a `low' fixup which matches l->fixp. */
1399 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1400 && f->fx_addsy == l->fixp->fx_addsy
1401 && f->fx_offset == l->fixp->fx_offset
1404 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1405 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1406 || prev->fx_addsy != f->fx_addsy
1407 || prev->fx_offset != f->fx_offset))
1411 /* Move l->fixp before f. */
1412 for (pf = &seginfo->fix_root;
1414 pf = & (* pf)->fx_next)
1415 assert (* pf != NULL);
1417 * pf = l->fixp->fx_next;
1419 l->fixp->fx_next = f;
1421 seginfo->fix_root = l->fixp;
1423 prev->fx_next = l->fixp;
1435 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1436 "Unmatched high/shigh reloc");
1441 /* See whether we need to force a relocation into the output file.
1442 This is used to force out switch and PC relative relocations when
1446 m32r_force_relocation (fix)
1452 return (fix->fx_pcrel
1456 /* Write a value out to the object file, using the appropriate endianness. */
1459 md_number_to_chars (buf, val, n)
1464 if (target_big_endian)
1465 number_to_chars_bigendian (buf, val, n);
1467 number_to_chars_littleendian (buf, val, n);
1470 /* Turn a string in input_line_pointer into a floating point constant of type
1471 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1472 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1475 /* Equal to MAX_PRECISION in atof-ieee.c */
1476 #define MAX_LITTLENUMS 6
1479 md_atof (type, litP, sizeP)
1486 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1487 LITTLENUM_TYPE * wordP;
1489 char * atof_ieee ();
1507 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1511 return "Bad call to md_atof()";
1514 t = atof_ieee (input_line_pointer, type, words);
1516 input_line_pointer = t;
1517 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1519 if (target_big_endian)
1521 for (i = 0; i < prec; i++)
1523 md_number_to_chars (litP, (valueT) words[i],
1524 sizeof (LITTLENUM_TYPE));
1525 litP += sizeof (LITTLENUM_TYPE);
1530 for (i = prec - 1; i >= 0; i--)
1532 md_number_to_chars (litP, (valueT) words[i],
1533 sizeof (LITTLENUM_TYPE));
1534 litP += sizeof (LITTLENUM_TYPE);