1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 /* Structure to hold all of the different components describing an individual instruction. */
30 const CGEN_INSN * insn;
33 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
35 char buffer [CGEN_MAX_INSN_SIZE];
39 int indices [MAX_OPERAND_INSTANCES];
43 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
44 boundary (i.e. was the first of two 16 bit insns). */
45 static m32r_insn prev_insn;
47 /* Non-zero if we've seen a relaxable insn since the last 32 bit
49 static int seen_relaxable_p = 0;
51 /* Non-zero if -relax specified, in which case sufficient relocs are output
52 for the linker to do relaxing.
53 We do simple forms of relaxing internally, but they are always done.
54 This flag does not apply to them. */
55 static int m32r_relax;
57 /* If non-NULL, pointer to cpu description file to read.
58 This allows runtime additions to the assembler. */
59 static char * m32r_cpu_desc;
61 /* start-sanitize-m32rx */
62 /* Non-zero if -m32rx has been specified, in which case support for the
63 extended M32RX instruction set should be enabled. */
64 static int enable_m32rx = 0;
66 /* Non-zero if the programmer should be warned when an explicit parallel
67 instruction might have constraint violations. */
68 static int warn_explicit_parallel_conflicts = 1;
69 /* end-sanitize-m32rx */
71 /* stuff for .scomm symbols. */
72 static segT sbss_section;
73 static asection scom_section;
74 static asymbol scom_symbol;
76 const char comment_chars[] = ";";
77 const char line_comment_chars[] = "#";
78 const char line_separator_chars[] = "";
79 const char EXP_CHARS[] = "eE";
80 const char FLT_CHARS[] = "dD";
82 /* Relocations against symbols are done in two
83 parts, with a HI relocation and a LO relocation. Each relocation
84 has only 16 bits of space to store an addend. This means that in
85 order for the linker to handle carries correctly, it must be able
86 to locate both the HI and the LO relocation. This means that the
87 relocations must appear in order in the relocation table.
89 In order to implement this, we keep track of each unmatched HI
90 relocation. We then sort them so that they immediately precede the
91 corresponding LO relocation. */
95 struct m32r_hi_fixup * next; /* Next HI fixup. */
96 fixS * fixp; /* This fixup. */
97 segT seg; /* The section this fixup is in. */
101 /* The list of unmatched HI relocs. */
103 static struct m32r_hi_fixup * m32r_hi_fixup_list;
106 /* start-sanitize-m32rx */
113 if (stdoutput != NULL)
114 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
115 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
117 /* end-sanitize-m32rx */
119 const char * md_shortopts = "";
121 struct option md_longopts[] =
123 /* start-sanitize-m32rx */
124 #define OPTION_M32RX (OPTION_MD_BASE)
125 {"m32rx", no_argument, NULL, OPTION_M32RX},
126 #define OPTION_WARN (OPTION_MD_BASE + 1)
127 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN},
128 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
129 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
130 /* end-sanitize-m32rx */
132 #if 0 /* not supported yet */
133 #define OPTION_RELAX (OPTION_MD_BASE + 3)
134 {"relax", no_argument, NULL, OPTION_RELAX},
135 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
136 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
139 {NULL, no_argument, NULL, 0}
141 size_t md_longopts_size = sizeof (md_longopts);
144 md_parse_option (c, arg)
150 /* start-sanitize-m32rx */
156 warn_explicit_parallel_conflicts = 1;
160 warn_explicit_parallel_conflicts = 0;
162 /* end-sanitize-m32rx */
164 #if 0 /* not supported yet */
168 case OPTION_CPU_DESC:
179 md_show_usage (stream)
182 fprintf (stream, "M32R/X options:\n");
183 /* start-sanitize-m32rx */
185 --m32rx support the extended m32rx instruction set\n");
188 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n");
190 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
191 /* end-sanitize-m32rx */
195 --relax create linker relaxable code\n");
197 --cpu-desc provide runtime cpu description file\n");
201 static void fill_insn PARAMS ((int));
202 static void m32r_scomm PARAMS ((int));
204 /* Set by md_assemble for use by m32r_fill_insn. */
205 static subsegT prev_subseg;
206 static segT prev_seg;
208 /* The target specific pseudo-ops which we support. */
209 const pseudo_typeS md_pseudo_table[] =
212 { "fillinsn", fill_insn, 0 },
213 { "scomm", m32r_scomm, 0 },
214 /* start-sanitize-m32rx */
215 { "m32r", allow_m32rx, 0},
216 { "m32rx", allow_m32rx, 1},
217 /* end-sanitize-m32rx */
221 /* FIXME: Should be machine generated. */
222 #define NOP_INSN 0x7000
223 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
225 /* When we align the .text section, insert the correct NOP pattern.
226 N is the power of 2 alignment. LEN is the length of pattern FILL.
227 MAX is the maximum number of characters to skip when doing the alignment,
228 or 0 if there is no maximum. */
231 m32r_do_align (n, fill, len, max)
237 if ((fill == NULL || (* fill == 0 && len == 1))
238 && (now_seg->flags & SEC_CODE) != 0
239 /* Only do this special handling if aligning to at least a
242 /* Only do this special handling if we're allowed to emit at
244 && (max == 0 || max > 1))
246 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
249 /* First align to a 2 byte boundary, in case there is an odd .byte. */
250 /* FIXME: How much memory will cause gas to use when assembling a big
251 program? Perhaps we can avoid the frag_align call? */
252 frag_align (1, 0, 0);
254 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
256 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
257 /* If doing larger alignments use a repeating sequence of appropriate
261 static const unsigned char multi_nop_pattern[] =
262 { 0x70, 0x00, 0xf0, 0x00 };
263 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
273 assemble_nop (opcode)
276 char * f = frag_more (2);
277 md_number_to_chars (f, opcode, 2);
280 /* If the last instruction was the first of 2 16 bit insns,
281 output a nop to move the PC to a 32 bit boundary.
283 This is done via an alignment specification since branch relaxing
284 may make it unnecessary.
286 Internally, we need to output one of these each time a 32 bit insn is
287 seen after an insn that is relaxable. */
293 (void) m32r_do_align (2, NULL, 0, 0);
294 prev_insn.insn = NULL;
295 seen_relaxable_p = 0;
298 /* Cover function to fill_insn called after a label and at end of assembly.
300 The result is always 1: we're called in a conditional to see if the
301 current line is a label. */
304 m32r_fill_insn (done)
310 if (prev_seg != NULL)
315 subseg_set (prev_seg, prev_subseg);
319 subseg_set (seg, subseg);
332 /* Initialize the `cgen' interface. */
334 /* This is a callback from cgen to gas to parse operands. */
335 cgen_parse_operand_fn = cgen_parse_operand;
337 /* Set the machine number and endian. */
338 CGEN_SYM (init_asm) (0 /* mach number */,
340 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
342 #if 0 /* not supported yet */
343 /* If a runtime cpu description file was provided, parse it. */
344 if (m32r_cpu_desc != NULL)
348 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
350 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
354 /* Save the current subseg so we can restore it [it's the default one and
355 we don't want the initial section to be .sbss]. */
359 /* The sbss section is for local .scomm symbols. */
360 sbss_section = subseg_new (".sbss", 0);
362 /* This is copied from perform_an_assembly_pass. */
363 applicable = bfd_applicable_section_flags (stdoutput);
364 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
366 #if 0 /* What does this do? [see perform_an_assembly_pass] */
367 seg_info (bss_section)->bss = 1;
370 subseg_set (seg, subseg);
372 /* We must construct a fake section similar to bfd_com_section
373 but with the name .scommon. */
374 scom_section = bfd_com_section;
375 scom_section.name = ".scommon";
376 scom_section.output_section = & scom_section;
377 scom_section.symbol = & scom_symbol;
378 scom_section.symbol_ptr_ptr = & scom_section.symbol;
379 scom_symbol = * bfd_com_section.symbol;
380 scom_symbol.name = ".scommon";
381 scom_symbol.section = & scom_section;
383 /* start-sanitize-m32rx */
384 allow_m32rx (enable_m32rx);
385 /* end-sanitize-m32rx */
388 /* start-sanitize-m32rx */
389 #ifdef HAVE_CPU_M32RX
391 /* Returns true if an output of instruction 'a' is referenced by an operand
392 of instruction 'b'. If 'check_outputs' is true then b's outputs are
393 checked, otherwise its inputs are examined. */
395 first_writes_to_seconds_operands (a, b, check_outputs)
398 const int check_outputs;
400 const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn);
401 const CGEN_OPERAND_INSTANCE * b_operands = CGEN_INSN_OPERANDS (b->insn);
404 /* If at least one of the instructions take sno opeands, then there is
405 nothing to check. There really are instructions without operands,
407 if (a_operands == NULL || b_operands == NULL)
410 /* Scan the operand list of 'a' looking for an output operand. */
412 CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
413 a_index ++, a_operands ++)
415 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT)
419 /* Scan operand list of 'b' looking for an operand that references
420 the same hardware element, and which goes in the right direction. */
422 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
423 b_index ++, b_operands ++)
425 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
426 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
427 && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands))
428 && (a->indices [a_index] == b->indices [b_index]))
437 /* Returns true if the insn can (potentially) alter the program counter. */
443 const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn);
445 if (a_operands == NULL)
448 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END)
450 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL
451 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
457 if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
458 || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
464 /* Returns NULL if the two 16 bit insns can be executed in parallel,
465 otherwise it returns a pointer to an error message explaining why not. */
467 can_make_parallel (a, b)
474 /* Make sure the instructions are the right length. */
475 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
476 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
479 if (first_writes_to_seconds_operands (a, b, true))
480 return "Instructions write to the same destination register.";
482 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
483 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
485 /* Make sure that the instructions use the correct execution pipelines. */
486 if ( a_pipe == PIPE_NONE
487 || b_pipe == PIPE_NONE)
488 return "Instructions do not use parallel execution pipelines.";
490 /* Leave this test for last, since it is the only test that can
491 go away if the instructions are swapped, and we want to make
492 sure that any other errors are detected before this happens. */
493 if ( a_pipe == PIPE_S
495 return "Instructions share the same execution pipeline";
502 make_parallel (buffer)
503 cgen_insn_t * buffer;
505 /* Force the top bit of the second insn to be set. */
509 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
511 value = bfd_getb16 ((bfd_byte *) buffer);
513 bfd_putb16 (value, (char *) buffer);
517 value = bfd_getl16 ((bfd_byte *) buffer);
519 bfd_putl16 (value, (char *) buffer);
524 make_parallel (buffer)
527 /* Force the top bit of the second insn to be set. */
529 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
535 assemble_parallel_insn (str, str2)
544 * str2 = 0; /* Seperate the two instructions. */
546 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
547 so that the parallel instruction will start on a 32 bit boundary. */
551 /* Parse the first instruction. */
552 if (! (first.insn = CGEN_SYM (assemble_insn)
553 (str, & first.fields, first.buffer, & errmsg)))
559 /* Check to see if this is an allowable parallel insn. */
560 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
562 as_bad ("instruction '%s' cannot be executed in parallel.", str);
567 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
569 as_bad ("instruction '%s' is for the M32RX only", str);
573 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
574 str3 = str; /* Save the original string pointer. */
575 str = str2 + 2; /* Advanced past the parsed string. */
576 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
578 /* Preserve any fixups that have been generated and reset the list to empty. */
581 /* Get the indicies of the operands of the instruction. */
582 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
583 doesn't seem right. Perhaps allow passing fields like we do insn. */
584 /* FIXME: ALIAS insns do not have operands, so we use this function
585 to find the equivalent insn and overwrite the value stored in our
586 structure. When aliases behave differently this may have to change. */
587 first.insn = m32r_cgen_get_insn_operands (first.insn, bfd_getb16 ((char *) first.buffer), 16,
589 if (first.insn == NULL)
590 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn");
592 /* Parse the second instruction. */
593 if (! (second.insn = CGEN_SYM (assemble_insn)
594 (str, & second.fields, second.buffer, & errmsg)))
602 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
604 as_bad ("instruction '%s' is for the M32RX only", str);
610 if ( strcmp (first.insn->name, "nop") != 0
611 && strcmp (second.insn->name, "nop") != 0)
613 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
618 /* Get the indicies of the operands of the instruction. */
619 second.insn = m32r_cgen_get_insn_operands (second.insn, bfd_getb16 ((char *) second.buffer), 16,
621 if (second.insn == NULL)
622 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn");
624 /* We assume that if the first instruction writes to a register that is
625 read by the second instruction it is because the programmer intended
626 this to happen, (after all they have explicitly requested that these
627 two instructions be executed in parallel). Although if the global
628 variable warn_explicit_parallel_conflicts is true then we do generate
629 a warning message. Similarly we assume that parallel branch and jump
630 instructions are deliberate and should not produce errors. */
632 if (warn_explicit_parallel_conflicts)
634 if (first_writes_to_seconds_operands (& first, & second, false))
635 as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2);
637 if (first_writes_to_seconds_operands (& second, & first, false))
638 as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2);
641 if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
643 /* Get the fixups for the first instruction. */
647 (void) cgen_asm_finish_insn (first.insn, first.buffer,
648 CGEN_FIELDS_BITSIZE (& first.fields));
650 /* Force the top bit of the second insn to be set. */
651 make_parallel (second.buffer);
653 /* Get its fixups. */
654 cgen_restore_fixups ();
657 (void) cgen_asm_finish_insn (second.insn, second.buffer,
658 CGEN_FIELDS_BITSIZE (& second.fields));
660 /* Try swapping the instructions to see if they work that way. */
661 else if (can_make_parallel (& second, & first) == NULL)
663 /* Write out the second instruction first. */
664 (void) cgen_asm_finish_insn (second.insn, second.buffer,
665 CGEN_FIELDS_BITSIZE (& second.fields));
667 /* Force the top bit of the first instruction to be set. */
668 make_parallel (first.buffer);
670 /* Get the fixups for the first instruction. */
671 cgen_restore_fixups ();
673 /* Write out the first instruction. */
674 (void) cgen_asm_finish_insn (first.insn, first.buffer,
675 CGEN_FIELDS_BITSIZE (& first.fields));
679 as_bad ("'%s': %s", str2, errmsg);
683 /* Set these so m32r_fill_insn can use them. */
685 prev_subseg = now_subseg;
690 #endif /* HAVE_CPU_M32RX */
692 /* end-sanitize-m32rx */
703 /* Initialize GAS's cgen interface for a new instruction. */
704 cgen_asm_init_parse ();
706 /* start-sanitize-m32rx */
707 #ifdef HAVE_CPU_M32RX
708 /* Look for a parallel instruction seperator. */
709 if ((str2 = strstr (str, "||")) != NULL)
711 assemble_parallel_insn (str, str2);
715 /* end-sanitize-m32rx */
717 insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
724 /* start-sanitize-m32rx */
725 #ifdef HAVE_CPU_M32RX
726 if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
728 as_bad ("instruction '%s' is for the M32RX only", str);
732 /* end-sanitize-m32rx */
734 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
736 /* 32 bit insns must live on 32 bit boundaries. */
737 if (prev_insn.insn || seen_relaxable_p)
739 /* FIXME: If calling fill_insn too many times turns us into a memory
740 pig, can we call assemble_nop instead of !seen_relaxable_p? */
744 (void) cgen_asm_finish_insn (insn.insn, insn.buffer,
745 CGEN_FIELDS_BITSIZE (& insn.fields));
749 /* start-sanitize-m32rx */
750 /* start-sanitize-phase2-m32rx */
752 /* end-sanitize-phase2-m32rx */
753 /* end-sanitize-m32rx */
755 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
758 /* Get the indicies of the operands of the instruction. */
759 insn.insn = m32r_cgen_get_insn_operands (insn.insn,
760 bfd_getb16 ((char *) insn.buffer),
763 if (insn.insn == NULL)
764 as_fatal ("internal error: m32r_cgen_get_insn_operands failed");
766 /* Keep track of whether we've seen a pair of 16 bit insns.
767 prev_insn.insn is NULL when we're on a 32 bit boundary. */
770 /* start-sanitize-m32rx */
771 /* start-sanitize-phase2-m32rx */
772 #ifdef HAVE_CPU_M32RX
773 /* Look to see if this instruction can be combined with the
774 previous instruction to make one, parallel, 32 bit instruction.
775 If the previous instruction (potentially) changed the flow of
776 program control, then it cannot be combined with the current
777 instruction. If the current instruction is relaxable, then it
778 might be replaced with a longer version, so we cannot combine it.
779 Also if the output of the previous instruction is used as an
780 input to the current instruction then it cannot be combined.
781 Otherwise call can_make_parallel() with both orderings of the
782 instructions to see if they can be combined. */
784 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) == 0
785 && ! writes_to_pc (& prev_insn)
786 && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
789 if (can_make_parallel (& prev_insn, & insn) == NULL)
790 make_parallel (insn.buffer);
791 else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
795 /* end-sanitize-phase2-m32rx */
796 /* end-sanitize-m32rx */
798 prev_insn.insn = NULL;
805 /* Record the frag that might be used by this insn. */
806 insn.frag = frag_now;
807 insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer,
808 CGEN_FIELDS_BITSIZE (& insn.fields));
810 /* start-sanitize-m32rx */
811 /* start-sanitize-phase2-m32rx */
812 #ifdef HAVE_CPU_M32RX
817 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
819 /* Swap the two insns */
820 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
821 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
823 make_parallel (insn.addr);
825 /* Swap any relaxable frags recorded for the two insns. */
826 if (prev_insn.frag->fr_opcode == prev_insn.addr)
827 prev_insn.frag->fr_opcode = insn.addr;
828 else if (insn.frag->fr_opcode == insn.addr)
829 insn.frag->fr_opcode = prev_insn.addr;
831 /* end-sanitize-phase2-m32rx */
833 /* Record where this instruction was assembled. */
834 prev_insn.addr = insn.addr;
835 prev_insn.frag = insn.frag;
837 /* end-sanitize-m32rx */
839 /* If the insn needs the following one to be on a 32 bit boundary
840 (e.g. subroutine calls), fill this insn's slot. */
841 if (prev_insn.insn != NULL
842 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0)
845 /* If this is a relaxable insn (can be replaced with a larger version)
846 mark the fact so that we can emit an alignment directive for a
847 following 32 bit insn if we see one. */
848 if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0)
849 seen_relaxable_p = 1;
852 /* Set these so m32r_fill_insn can use them. */
854 prev_subseg = now_subseg;
857 /* The syntax in the manual says constants begin with '#'.
858 We just ignore it. */
861 md_operand (expressionP)
862 expressionS * expressionP;
864 if (* input_line_pointer == '#')
866 input_line_pointer ++;
867 expression (expressionP);
872 md_section_align (segment, size)
876 int align = bfd_get_section_alignment (stdoutput, segment);
877 return ((size + (1 << align) - 1) & (-1 << align));
881 md_undefined_symbol (name)
887 /* .scomm pseudo-op handler.
889 This is a new pseudo-op to handle putting objects in .scommon.
890 By doing this the linker won't need to do any work and more importantly
891 it removes the implicit -G arg necessary to correctly link the object file.
898 register char * name;
902 register symbolS * symbolP;
906 name = input_line_pointer;
907 c = get_symbol_end ();
909 /* just after name is now '\0' */
910 p = input_line_pointer;
913 if (* input_line_pointer != ',')
915 as_bad ("Expected comma after symbol-name: rest of line ignored.");
916 ignore_rest_of_line ();
920 input_line_pointer ++; /* skip ',' */
921 if ((size = get_absolute_expression ()) < 0)
923 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
924 ignore_rest_of_line ();
928 /* The third argument to .scomm is the alignment. */
929 if (* input_line_pointer != ',')
933 ++ input_line_pointer;
934 align = get_absolute_expression ();
937 as_warn ("ignoring bad alignment");
941 /* Convert to a power of 2 alignment. */
944 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
948 as_bad ("Common alignment not a power of 2");
949 ignore_rest_of_line ();
957 symbolP = symbol_find_or_make (name);
960 if (S_IS_DEFINED (symbolP))
962 as_bad ("Ignoring attempt to re-define symbol `%s'.",
963 S_GET_NAME (symbolP));
964 ignore_rest_of_line ();
968 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
970 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
971 S_GET_NAME (symbolP),
972 (long) S_GET_VALUE (symbolP),
975 ignore_rest_of_line ();
981 segT old_sec = now_seg;
982 int old_subsec = now_subseg;
985 record_alignment (sbss_section, align2);
986 subseg_set (sbss_section, 0);
989 frag_align (align2, 0, 0);
991 if (S_GET_SEGMENT (symbolP) == sbss_section)
992 symbolP->sy_frag->fr_symbol = 0;
994 symbolP->sy_frag = frag_now;
996 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
999 S_SET_SIZE (symbolP, size);
1000 S_SET_SEGMENT (symbolP, sbss_section);
1001 S_CLEAR_EXTERNAL (symbolP);
1002 subseg_set (old_sec, old_subsec);
1006 S_SET_VALUE (symbolP, (valueT) size);
1007 S_SET_ALIGN (symbolP, align2);
1008 S_SET_EXTERNAL (symbolP);
1009 S_SET_SEGMENT (symbolP, & scom_section);
1012 demand_empty_rest_of_line ();
1015 /* Interface to relax_segment. */
1017 /* FIXME: Build table by hand, get it working, then machine generate. */
1019 const relax_typeS md_relax_table[] =
1022 1) most positive reach of this state,
1023 2) most negative reach of this state,
1024 3) how many bytes this mode will add to the size of the current frag
1025 4) which index into the table to try if we can't fit into this one. */
1027 /* The first entry must be unused because an `rlx_more' value of zero ends
1031 /* The displacement used by GAS is from the end of the 2 byte insn,
1032 so we subtract 2 from the following. */
1033 /* 16 bit insn, 8 bit disp -> 10 bit range.
1034 This doesn't handle a branch in the right slot at the border:
1035 the "& -4" isn't taken into account. It's not important enough to
1036 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1038 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1039 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1040 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1041 /* Same thing, but with leading nop for alignment. */
1042 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1046 m32r_relax_frag (fragP, stretch)
1050 /* Address of branch insn. */
1051 long address = fragP->fr_address + fragP->fr_fix - 2;
1054 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1055 if (fragP->fr_subtype == 2)
1057 if ((address & 3) != 0)
1059 fragP->fr_subtype = 3;
1063 else if (fragP->fr_subtype == 3)
1065 if ((address & 3) == 0)
1067 fragP->fr_subtype = 2;
1073 growth = relax_frag (fragP, stretch);
1075 /* Long jump on odd halfword boundary? */
1076 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1078 fragP->fr_subtype = 3;
1086 /* Return an initial guess of the length by which a fragment must grow to
1087 hold a branch to reach its destination.
1088 Also updates fr_type/fr_subtype as necessary.
1090 Called just before doing relaxation.
1091 Any symbol that is now undefined will not become defined.
1092 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1093 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1094 Although it may not be explicit in the frag, pretend fr_var starts with a
1098 md_estimate_size_before_relax (fragP, segment)
1102 int old_fr_fix = fragP->fr_fix;
1103 char * opcode = fragP->fr_opcode;
1105 /* The only thing we have to handle here are symbols outside of the
1106 current segment. They may be undefined or in a different segment in
1107 which case linker scripts may place them anywhere.
1108 However, we can't finish the fragment here and emit the reloc as insn
1109 alignment requirements may move the insn about. */
1111 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1113 /* The symbol is undefined in this segment.
1114 Change the relaxation subtype to the max allowable and leave
1115 all further handling to md_convert_frag. */
1116 fragP->fr_subtype = 2;
1118 #if 0 /* Can't use this, but leave in for illustration. */
1119 /* Change 16 bit insn to 32 bit insn. */
1122 /* Increase known (fixed) size of fragment. */
1125 /* Create a relocation for it. */
1126 fix_new (fragP, old_fr_fix, 4,
1128 fragP->fr_offset, 1 /* pcrel */,
1129 /* FIXME: Can't use a real BFD reloc here.
1130 cgen_md_apply_fix3 can't handle it. */
1131 BFD_RELOC_M32R_26_PCREL);
1133 /* Mark this fragment as finished. */
1137 const CGEN_INSN * insn;
1140 /* Update the recorded insn.
1141 Fortunately we don't have to look very far.
1142 FIXME: Change this to record in the instruction the next higher
1143 relaxable insn to use. */
1144 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1146 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1147 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1149 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1155 fragP->fr_cgen.insn = insn;
1161 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1164 /* *fragP has been relaxed to its final size, and now needs to have
1165 the bytes inside it modified to conform to the new size.
1167 Called after relaxation is finished.
1168 fragP->fr_type == rs_machine_dependent.
1169 fragP->fr_subtype is the subtype of what the address relaxed to. */
1172 md_convert_frag (abfd, sec, fragP)
1178 char * displacement;
1184 opcode = fragP->fr_opcode;
1186 /* Address opcode resides at in file space. */
1187 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1189 switch (fragP->fr_subtype)
1193 displacement = & opcode[1];
1198 displacement = & opcode[1];
1201 opcode[2] = opcode[0] | 0x80;
1202 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1203 opcode_address += 2;
1205 displacement = & opcode[3];
1211 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1213 /* symbol must be resolved by linker */
1214 if (fragP->fr_offset & 3)
1215 as_warn ("Addend to unresolved symbol not on word boundary.");
1216 addend = fragP->fr_offset >> 2;
1220 /* Address we want to reach in file space. */
1221 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1222 target_address += fragP->fr_symbol->sy_frag->fr_address;
1223 addend = (target_address - (opcode_address & -4)) >> 2;
1226 /* Create a relocation for symbols that must be resolved by the linker.
1227 Otherwise output the completed insn. */
1229 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1231 assert (fragP->fr_subtype != 1);
1232 assert (fragP->fr_cgen.insn != 0);
1233 cgen_record_fixup (fragP,
1234 /* Offset of branch insn in frag. */
1235 fragP->fr_fix + extension - 4,
1236 fragP->fr_cgen.insn,
1238 /* FIXME: quick hack */
1240 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1242 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1244 fragP->fr_cgen.opinfo,
1245 fragP->fr_symbol, fragP->fr_offset);
1248 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1250 md_number_to_chars (displacement, (valueT) addend,
1251 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1253 fragP->fr_fix += extension;
1256 /* Functions concerning relocs. */
1258 /* The location from which a PC relative jump should be calculated,
1259 given a PC relative reloc. */
1262 md_pcrel_from_section (fixP, sec)
1266 if (fixP->fx_addsy != (symbolS *) NULL
1267 && (! S_IS_DEFINED (fixP->fx_addsy)
1268 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1270 /* The symbol is undefined (or is defined but not in this section).
1271 Let the linker figure it out. */
1275 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1278 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1279 Returns BFD_RELOC_NONE if no reloc type can be found.
1280 *FIXP may be modified if desired. */
1282 bfd_reloc_code_real_type
1283 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1284 const CGEN_INSN * insn;
1285 const CGEN_OPERAND * operand;
1288 switch (CGEN_OPERAND_TYPE (operand))
1290 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1291 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1292 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1293 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1294 case M32R_OPERAND_HI16 :
1295 case M32R_OPERAND_SLO16 :
1296 case M32R_OPERAND_ULO16 :
1297 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1298 if (fixP->tc_fix_data.opinfo != 0)
1299 return fixP->tc_fix_data.opinfo;
1302 return BFD_RELOC_NONE;
1305 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1308 m32r_record_hi16 (reloc_type, fixP, seg)
1313 struct m32r_hi_fixup * hi_fixup;
1315 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1316 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1318 hi_fixup = ((struct m32r_hi_fixup *)
1319 xmalloc (sizeof (struct m32r_hi_fixup)));
1320 hi_fixup->fixp = fixP;
1321 hi_fixup->seg = now_seg;
1322 hi_fixup->next = m32r_hi_fixup_list;
1324 m32r_hi_fixup_list = hi_fixup;
1327 /* Called while parsing an instruction to create a fixup.
1328 We need to check for HI16 relocs and queue them up for later sorting. */
1331 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1334 const CGEN_INSN * insn;
1336 const CGEN_OPERAND * operand;
1340 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1341 operand, opinfo, exp);
1343 switch (CGEN_OPERAND_TYPE (operand))
1345 case M32R_OPERAND_HI16 :
1346 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1347 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1348 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1349 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1356 /* Return BFD reloc type from opinfo field in a fixS.
1357 It's tricky using fx_r_type in m32r_frob_file because the values
1358 are BFD_RELOC_UNUSED + operand number. */
1359 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1361 /* Sort any unmatched HI16 relocs so that they immediately precede
1362 the corresponding LO16 reloc. This is called before md_apply_fix and
1368 struct m32r_hi_fixup * l;
1370 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1372 segment_info_type * seginfo;
1375 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1376 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1378 /* Check quickly whether the next fixup happens to be a matching low. */
1379 if (l->fixp->fx_next != NULL
1380 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1381 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1382 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1385 /* Look through the fixups for this segment for a matching `low'.
1386 When we find one, move the high/shigh just in front of it. We do
1387 this in two passes. In the first pass, we try to find a
1388 unique `low'. In the second pass, we permit multiple high's
1389 relocs for a single `low'. */
1390 seginfo = seg_info (l->seg);
1391 for (pass = 0; pass < 2; pass++)
1397 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1399 /* Check whether this is a `low' fixup which matches l->fixp. */
1400 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1401 && f->fx_addsy == l->fixp->fx_addsy
1402 && f->fx_offset == l->fixp->fx_offset
1405 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1406 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1407 || prev->fx_addsy != f->fx_addsy
1408 || prev->fx_offset != f->fx_offset))
1412 /* Move l->fixp before f. */
1413 for (pf = &seginfo->fix_root;
1415 pf = & (* pf)->fx_next)
1416 assert (* pf != NULL);
1418 * pf = l->fixp->fx_next;
1420 l->fixp->fx_next = f;
1422 seginfo->fix_root = l->fixp;
1424 prev->fx_next = l->fixp;
1436 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1437 "Unmatched high/shigh reloc");
1442 /* See whether we need to force a relocation into the output file.
1443 This is used to force out switch and PC relative relocations when
1447 m32r_force_relocation (fix)
1453 return (fix->fx_pcrel
1457 /* Write a value out to the object file, using the appropriate endianness. */
1460 md_number_to_chars (buf, val, n)
1465 if (target_big_endian)
1466 number_to_chars_bigendian (buf, val, n);
1468 number_to_chars_littleendian (buf, val, n);
1471 /* Turn a string in input_line_pointer into a floating point constant of type
1472 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1473 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1476 /* Equal to MAX_PRECISION in atof-ieee.c */
1477 #define MAX_LITTLENUMS 6
1480 md_atof (type, litP, sizeP)
1487 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1488 LITTLENUM_TYPE * wordP;
1490 char * atof_ieee ();
1508 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1512 return "Bad call to md_atof()";
1515 t = atof_ieee (input_line_pointer, type, words);
1517 input_line_pointer = t;
1518 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1520 if (target_big_endian)
1522 for (i = 0; i < prec; i++)
1524 md_number_to_chars (litP, (valueT) words[i],
1525 sizeof (LITTLENUM_TYPE));
1526 litP += sizeof (LITTLENUM_TYPE);
1531 for (i = prec - 1; i >= 0; i--)
1533 md_number_to_chars (litP, (valueT) words[i],
1534 sizeof (LITTLENUM_TYPE));
1535 litP += sizeof (LITTLENUM_TYPE);