1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 const CGEN_INSN * insn;
32 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
34 char buffer [CGEN_MAX_INSN_SIZE];
41 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
42 boundary (i.e. was the first of two 16 bit insns). */
43 static m32r_insn prev_insn;
45 /* Non-zero if we've seen a relaxable insn since the last 32 bit
47 static int seen_relaxable_p = 0;
49 /* Non-zero if -relax specified, in which case sufficient relocs are output
50 for the linker to do relaxing.
51 We do simple forms of relaxing internally, but they are always done.
52 This flag does not apply to them. */
53 static int m32r_relax;
55 /* If non-NULL, pointer to cpu description file to read.
56 This allows runtime additions to the assembler. */
57 static char * m32r_cpu_desc;
59 /* start-sanitize-m32rx */
60 /* Non-zero if -m32rx has been specified, in which case support for the
61 extended M32RX instruction set should be enabled. */
62 static int enable_m32rx = 0;
64 /* Non-zero if the programmer should be warned when an explicit parallel
65 instruction might have constraint violations. */
66 static int warn_explicit_parallel_conflicts = 1;
67 /* end-sanitize-m32rx */
69 /* stuff for .scomm symbols. */
70 static segT sbss_section;
71 static asection scom_section;
72 static asymbol scom_symbol;
74 const char comment_chars[] = ";";
75 const char line_comment_chars[] = "#";
76 const char line_separator_chars[] = "";
77 const char EXP_CHARS[] = "eE";
78 const char FLT_CHARS[] = "dD";
80 /* Relocations against symbols are done in two
81 parts, with a HI relocation and a LO relocation. Each relocation
82 has only 16 bits of space to store an addend. This means that in
83 order for the linker to handle carries correctly, it must be able
84 to locate both the HI and the LO relocation. This means that the
85 relocations must appear in order in the relocation table.
87 In order to implement this, we keep track of each unmatched HI
88 relocation. We then sort them so that they immediately precede the
89 corresponding LO relocation. */
93 struct m32r_hi_fixup * next; /* Next HI fixup. */
94 fixS * fixp; /* This fixup. */
95 segT seg; /* The section this fixup is in. */
99 /* The list of unmatched HI relocs. */
101 static struct m32r_hi_fixup * m32r_hi_fixup_list;
104 /* start-sanitize-m32rx */
110 if (stdoutput != NULL)
111 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
112 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
114 /* end-sanitize-m32rx */
116 const char * md_shortopts = "";
118 struct option md_longopts[] =
120 /* start-sanitize-m32rx */
121 #define OPTION_M32RX (OPTION_MD_BASE)
122 {"m32rx", no_argument, NULL, OPTION_M32RX},
123 #define OPTION_WARN (OPTION_MD_BASE + 1)
124 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN},
125 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
126 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
127 /* end-sanitize-m32rx */
129 #if 0 /* not supported yet */
130 #define OPTION_RELAX (OPTION_MD_BASE + 3)
131 {"relax", no_argument, NULL, OPTION_RELAX},
132 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
133 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
136 {NULL, no_argument, NULL, 0}
138 size_t md_longopts_size = sizeof (md_longopts);
141 md_parse_option (c, arg)
147 /* start-sanitize-m32rx */
153 warn_explicit_parallel_conflicts = 1;
157 warn_explicit_parallel_conflicts = 0;
159 /* end-sanitize-m32rx */
161 #if 0 /* not supported yet */
165 case OPTION_CPU_DESC:
176 md_show_usage (stream)
179 fprintf (stream, "M32R/X options:\n");
180 /* start-sanitize-m32rx */
182 --m32rx support the extended m32rx instruction set\n");
185 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\
186 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
187 /* end-sanitize-m32rx */
191 --relax create linker relaxable code\n");
193 --cpu-desc provide runtime cpu description file\n");
197 static void fill_insn PARAMS ((int));
198 static void m32r_scomm PARAMS ((int));
200 /* Set by md_assemble for use by m32r_fill_insn. */
201 static subsegT prev_subseg;
202 static segT prev_seg;
204 /* The target specific pseudo-ops which we support. */
205 const pseudo_typeS md_pseudo_table[] =
208 { "fillinsn", fill_insn, 0 },
209 { "scomm", m32r_scomm, 0 },
210 /* start-sanitize-m32rx */
211 { "m32r", allow_m32rx, 0},
212 { "m32rx", allow_m32rx, 1},
213 /* end-sanitize-m32rx */
217 /* FIXME: Should be machine generated. */
218 #define NOP_INSN 0x7000
219 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
221 /* When we align the .text section, insert the correct NOP pattern.
222 N is the power of 2 alignment. LEN is the length of pattern FILL.
223 MAX is the maximum number of characters to skip when doing the alignment,
224 or 0 if there is no maximum. */
227 m32r_do_align (n, fill, len, max)
233 if ((fill == NULL || (* fill == 0 && len == 1))
234 && (now_seg->flags & SEC_CODE) != 0
235 /* Only do this special handling if aligning to at least a
238 /* Only do this special handling if we're allowed to emit at
240 && (max == 0 || max > 1))
242 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
245 /* First align to a 2 byte boundary, in case there is an odd .byte. */
246 /* FIXME: How much memory will cause gas to use when assembling a big
247 program? Perhaps we can avoid the frag_align call? */
248 frag_align (1, 0, 0);
250 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
252 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
253 /* If doing larger alignments use a repeating sequence of appropriate
257 static const unsigned char multi_nop_pattern[] =
258 { 0x70, 0x00, 0xf0, 0x00 };
259 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
269 assemble_nop (opcode)
272 char * f = frag_more (2);
273 md_number_to_chars (f, opcode, 2);
276 /* If the last instruction was the first of 2 16 bit insns,
277 output a nop to move the PC to a 32 bit boundary.
279 This is done via an alignment specification since branch relaxing
280 may make it unnecessary.
282 Internally, we need to output one of these each time a 32 bit insn is
283 seen after an insn that is relaxable. */
289 (void) m32r_do_align (2, NULL, 0, 0);
290 prev_insn.insn = NULL;
291 seen_relaxable_p = 0;
294 /* Cover function to fill_insn called after a label and at end of assembly.
296 The result is always 1: we're called in a conditional to see if the
297 current line is a label. */
300 m32r_fill_insn (done)
306 if (prev_seg != NULL)
311 subseg_set (prev_seg, prev_subseg);
315 subseg_set (seg, subseg);
328 /* Initialize the `cgen' interface. */
330 /* This is a callback from cgen to gas to parse operands. */
331 cgen_parse_operand_fn = cgen_parse_operand;
333 /* Set the machine number and endian. */
334 CGEN_SYM (init_asm) (0 /* mach number */,
336 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
338 #if 0 /* not supported yet */
339 /* If a runtime cpu description file was provided, parse it. */
340 if (m32r_cpu_desc != NULL)
344 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
346 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
350 /* Save the current subseg so we can restore it [it's the default one and
351 we don't want the initial section to be .sbss]. */
355 /* The sbss section is for local .scomm symbols. */
356 sbss_section = subseg_new (".sbss", 0);
358 /* This is copied from perform_an_assembly_pass. */
359 applicable = bfd_applicable_section_flags (stdoutput);
360 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
362 #if 0 /* What does this do? [see perform_an_assembly_pass] */
363 seg_info (bss_section)->bss = 1;
366 subseg_set (seg, subseg);
368 /* We must construct a fake section similar to bfd_com_section
369 but with the name .scommon. */
370 scom_section = bfd_com_section;
371 scom_section.name = ".scommon";
372 scom_section.output_section = & scom_section;
373 scom_section.symbol = & scom_symbol;
374 scom_section.symbol_ptr_ptr = & scom_section.symbol;
375 scom_symbol = * bfd_com_section.symbol;
376 scom_symbol.name = ".scommon";
377 scom_symbol.section = & scom_section;
379 /* start-sanitize-m32rx */
380 allow_m32rx (enable_m32rx);
381 /* end-sanitize-m32rx */
384 /* start-sanitize-m32rx */
385 /* Returns non zero if the given instruction writes to a destination register. */
387 writes_to_dest_reg (insn)
388 const CGEN_INSN * insn;
390 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
393 /* Scan the syntax string looking for a destination register. */
394 while ((c = (* syntax ++)) != 0)
395 if (c == 128 + M32R_OPERAND_DR)
401 /* Returns non zero if the given instruction reads from a source register.
402 Ignores the first 'num_ignore' macthes in the syntax string. */
404 reads_from_src_reg (insn, num_ignore)
405 const CGEN_INSN * insn;
408 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
411 /* Scan the syntax string looking for a source register. */
412 while ((c = (* syntax ++)) != 0)
414 if ( c == 128 + M32R_OPERAND_SR
415 || c == 128 + M32R_OPERAND_SRC1
416 || c == 128 + M32R_OPERAND_SRC2)
418 if (num_ignore -- > 0)
428 /* Returns the integer value of the destination register held in the fields. */
429 #define get_dest_reg(fields) (fields).f_r1
431 /* Returns an integer representing the source register of the given type. */
433 get_src_reg (syntax_field, fields)
434 unsigned char syntax_field;
435 CGEN_FIELDS * fields;
437 switch (syntax_field)
439 case 128 + M32R_OPERAND_SR: return fields->f_r2;
440 /* Relies upon the fact that no instruction with a $src1 operand
441 also has a $dr operand. */
442 case 128 + M32R_OPERAND_SRC1: return fields->f_r1;
443 case 128 + M32R_OPERAND_SRC2: return fields->f_r2;
444 default: abort(); return -1;
448 /* Returns NULL if the two 16 bit insns can be executed in parallel,
449 otherwise it returns a pointer to an error message explaining why not. */
451 can_make_parallel (a, b, test_a_inputs, test_b_inputs)
460 /* Make sure the instructions are the right length. */
461 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
462 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
465 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
466 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
468 /* Make sure that the instructions use the correct execution pipelines. */
469 if ( a_pipe == PIPE_NONE
470 || b_pipe == PIPE_NONE)
471 return "Instructions do not use parallel execution pipelines.";
473 if ( a_pipe == PIPE_S
475 return "Instructions share the same execution pipeline";
477 if ( writes_to_dest_reg (a->insn)
478 && writes_to_dest_reg (b->insn)
479 && (get_dest_reg (a->fields) == get_dest_reg (b->fields)))
480 return "Instructions write to the same destination register.";
482 /* If requested, make sure that the first instruction does not
483 overwrite the inputs of the second instruction. */
484 if (test_b_inputs && writes_to_dest_reg (a->insn))
486 unsigned char syntax_field;
489 while (syntax_field = reads_from_src_reg (b->insn, skip ++))
491 if (get_src_reg (syntax_field, & b->fields) == get_dest_reg (a->fields))
492 return "First instruction writes to register read by the second instruction";
496 /* Similarly, if requested, make sure that the second instruction
497 does not overwrite the inputs of the first instruction. */
498 if (test_a_inputs && writes_to_dest_reg (b->insn))
500 unsigned char syntax_field;
503 while (syntax_field = reads_from_src_reg (a->insn, skip ++))
505 if (get_src_reg (syntax_field, & a->fields) == get_dest_reg (b->fields))
506 return "Second instruction writes to register read by the first instruction";
515 make_parallel (buffer)
516 cgen_insn_t * buffer;
518 /* Force the top bit of the second insn to be set. */
522 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
524 value = bfd_getb16 ((bfd_byte *) buffer);
526 bfd_putb16 (value, (char *) buffer);
530 value = bfd_getl16 ((bfd_byte *) buffer);
532 bfd_putl16 (value, (char *) buffer);
537 make_parallel (buffer)
540 /* Force the top bit of the second insn to be set. */
542 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
548 assemble_parallel_insn (str, str2)
557 * str2 = 0; /* Seperate the two instructions. */
559 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
560 so that the parallel instruction will start on a 32 bit boundary. */
564 /* Parse the first instruction. */
565 if (! (first.insn = CGEN_SYM (assemble_insn)
566 (str, & first.fields, first.buffer, & errmsg)))
572 /* Check to see if this is an allowable parallel insn. */
573 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
575 as_bad ("instruction '%s' cannot be executed in parallel.", str);
580 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
582 as_bad ("instruction '%s' is for the M32RX only", str);
586 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
587 str3 = str; /* Save the original string pointer. */
588 str = str2 + 2; /* Advanced past the parsed string. */
589 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
591 /* Preserve any fixups that have been generated and reset the list to empty. */
594 /* Parse the second instruction. */
595 if (! (second.insn = CGEN_SYM (assemble_insn)
596 (str, & second.fields, second.buffer, & errmsg)))
604 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
606 as_bad ("instruction '%s' is for the M32RX only", str);
612 if ( strcmp (first.insn->name, "nop") != 0
613 && strcmp (second.insn->name, "nop") != 0)
615 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
620 /* We assume that if the first instruction writes to a register that is
621 read by the second instruction it is because the programmer intended
622 this to happen, (after all they have explicitly requested that these
623 two instructions be executed in parallel). Similarly we assume that
624 parallel branch and jump instructions are deliberate and should not
625 produce errors. If warn_explicit_parallel is defined however, we do
626 generate warning messages. */
628 if (can_make_parallel (& first, & second, false, false) == NULL)
630 /* Get the fixups for the first instruction. */
634 (void) cgen_asm_finish_insn (first.insn, first.buffer,
635 CGEN_FIELDS_BITSIZE (& first.fields));
637 /* Force the top bit of the second insn to be set. */
638 make_parallel (second.buffer);
640 /* Get its fixups. */
641 cgen_restore_fixups ();
644 (void) cgen_asm_finish_insn (second.insn, second.buffer,
645 CGEN_FIELDS_BITSIZE (& second.fields));
647 else if ((errmsg = (char *) can_make_parallel (& second, & first,
648 false, false)) == NULL)
650 /* Write out the second instruction first. */
651 (void) cgen_asm_finish_insn (second.insn, second.buffer,
652 CGEN_FIELDS_BITSIZE (& second.fields));
654 /* Force the top bit of the first instruction to be set. */
655 make_parallel (first.buffer);
657 /* Get the fixups for the first instruction. */
658 cgen_restore_fixups ();
660 /* Write out the first instruction. */
661 (void) cgen_asm_finish_insn (first.insn, first.buffer,
662 CGEN_FIELDS_BITSIZE (& first.fields));
666 as_bad ("'%s': %s", str2, errmsg);
670 /* Set these so m32r_fill_insn can use them. */
672 prev_subseg = now_subseg;
676 /* end-sanitize-m32rx */
687 /* Initialize GAS's cgen interface for a new instruction. */
688 cgen_asm_init_parse ();
690 /* start-sanitize-m32rx */
691 /* Look for a parallel instruction seperator. */
692 if ((str2 = strstr (str, "||")) != NULL)
694 assemble_parallel_insn (str, str2);
697 /* end-sanitize-m32rx */
699 insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
706 /* start-sanitize-m32rx */
707 if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
709 as_bad ("instruction '%s' is for the M32RX only", str);
712 /* end-sanitize-m32rx */
714 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
716 /* 32 bit insns must live on 32 bit boundaries. */
717 if (prev_insn.insn || seen_relaxable_p)
719 /* FIXME: If calling fill_insn too many times turns us into a memory
720 pig, can we call assemble_nop instead of !seen_relaxable_p? */
724 (void) cgen_asm_finish_insn (insn.insn, insn.buffer,
725 CGEN_FIELDS_BITSIZE (& insn.fields));
729 /* start-sanitize-m32rx */
730 /* start-sanitize-phase2-m32rx */
732 /* end-sanitize-phase2-m32rx */
733 /* end-sanitize-m32rx */
735 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
738 /* Keep track of whether we've seen a pair of 16 bit insns.
739 prev_insn.insn is NULL when we're on a 32 bit boundary. */
742 /* start-sanitize-m32rx */
743 /* start-sanitize-phase2-m32rx */
744 /* Look to see if this instruction can be combined with the
745 previous instruction to make one, parallel, 32 bit instruction.
746 If the previous instruction (potentially) changed the flow of
747 program control, then it cannot be combined with the current
748 instruction, otherwise call can_make_parallel() with both
749 orderings of the instructions to see if they can be combined. */
750 if ( ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_COND_CTI)
751 && ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_UNCOND_CTI))
753 if (can_make_parallel (& prev_insn, & insn, false, true) == NULL)
755 make_parallel (insn.buffer);
757 else if (can_make_parallel (& insn, & prev_insn.insn, true, false) == NULL)
762 /* end-sanitize-phase2-m32rx */
763 /* end-sanitize-m32rx */
765 prev_insn.insn = NULL;
772 /* Record the frag that might be used by this insn. */
773 insn.frag = frag_now;
774 insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer,
775 CGEN_FIELDS_BITSIZE (& insn.fields));
777 /* start-sanitize-m32rx */
778 /* start-sanitize-phase2-m32rx */
783 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
785 /* Swap the two insns */
786 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
787 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
789 make_parallel (insn.addr);
791 /* Swap any relaxable frags recorded for the two insns. */
792 if (prev_insn.frag->fr_opcode == prev_insn.addr)
794 prev_insn.frag->fr_opcode = insn.addr;
796 else if (insn.frag->fr_opcode == insn.addr)
798 insn.frag->fr_opcode = prev_insn.addr;
801 /* end-sanitize-phase2-m32rx */
803 /* Record where this instruction was assembled. */
804 prev_insn.addr = insn.addr;
805 prev_insn.frag = insn.frag;
806 /* end-sanitize-m32rx */
808 /* If the insn needs the following one to be on a 32 bit boundary
809 (e.g. subroutine calls), fill this insn's slot. */
811 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0)
814 /* If this is a relaxable insn (can be replaced with a larger version)
815 mark the fact so that we can emit an alignment directive for a
816 following 32 bit insn if we see one. */
817 if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0)
818 seen_relaxable_p = 1;
821 /* Set these so m32r_fill_insn can use them. */
823 prev_subseg = now_subseg;
826 /* The syntax in the manual says constants begin with '#'.
827 We just ignore it. */
830 md_operand (expressionP)
831 expressionS * expressionP;
833 if (* input_line_pointer == '#')
835 input_line_pointer ++;
836 expression (expressionP);
841 md_section_align (segment, size)
845 int align = bfd_get_section_alignment (stdoutput, segment);
846 return ((size + (1 << align) - 1) & (-1 << align));
850 md_undefined_symbol (name)
856 /* .scomm pseudo-op handler.
858 This is a new pseudo-op to handle putting objects in .scommon.
859 By doing this the linker won't need to do any work and more importantly
860 it removes the implicit -G arg necessary to correctly link the object file.
867 register char * name;
871 register symbolS * symbolP;
875 name = input_line_pointer;
876 c = get_symbol_end ();
878 /* just after name is now '\0' */
879 p = input_line_pointer;
882 if (* input_line_pointer != ',')
884 as_bad ("Expected comma after symbol-name: rest of line ignored.");
885 ignore_rest_of_line ();
889 input_line_pointer ++; /* skip ',' */
890 if ((size = get_absolute_expression ()) < 0)
892 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
893 ignore_rest_of_line ();
897 /* The third argument to .scomm is the alignment. */
898 if (* input_line_pointer != ',')
902 ++ input_line_pointer;
903 align = get_absolute_expression ();
906 as_warn ("ignoring bad alignment");
910 /* Convert to a power of 2 alignment. */
913 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
917 as_bad ("Common alignment not a power of 2");
918 ignore_rest_of_line ();
926 symbolP = symbol_find_or_make (name);
929 if (S_IS_DEFINED (symbolP))
931 as_bad ("Ignoring attempt to re-define symbol `%s'.",
932 S_GET_NAME (symbolP));
933 ignore_rest_of_line ();
937 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
939 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
940 S_GET_NAME (symbolP),
941 (long) S_GET_VALUE (symbolP),
944 ignore_rest_of_line ();
950 segT old_sec = now_seg;
951 int old_subsec = now_subseg;
954 record_alignment (sbss_section, align2);
955 subseg_set (sbss_section, 0);
958 frag_align (align2, 0, 0);
960 if (S_GET_SEGMENT (symbolP) == sbss_section)
961 symbolP->sy_frag->fr_symbol = 0;
963 symbolP->sy_frag = frag_now;
965 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
968 S_SET_SIZE (symbolP, size);
969 S_SET_SEGMENT (symbolP, sbss_section);
970 S_CLEAR_EXTERNAL (symbolP);
971 subseg_set (old_sec, old_subsec);
975 S_SET_VALUE (symbolP, (valueT) size);
976 S_SET_ALIGN (symbolP, align2);
977 S_SET_EXTERNAL (symbolP);
978 S_SET_SEGMENT (symbolP, & scom_section);
981 demand_empty_rest_of_line ();
984 /* Interface to relax_segment. */
986 /* FIXME: Build table by hand, get it working, then machine generate. */
988 const relax_typeS md_relax_table[] =
991 1) most positive reach of this state,
992 2) most negative reach of this state,
993 3) how many bytes this mode will add to the size of the current frag
994 4) which index into the table to try if we can't fit into this one. */
996 /* The first entry must be unused because an `rlx_more' value of zero ends
1000 /* The displacement used by GAS is from the end of the 2 byte insn,
1001 so we subtract 2 from the following. */
1002 /* 16 bit insn, 8 bit disp -> 10 bit range.
1003 This doesn't handle a branch in the right slot at the border:
1004 the "& -4" isn't taken into account. It's not important enough to
1005 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1007 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1008 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1009 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1010 /* Same thing, but with leading nop for alignment. */
1011 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1015 m32r_relax_frag (fragP, stretch)
1019 /* Address of branch insn. */
1020 long address = fragP->fr_address + fragP->fr_fix - 2;
1023 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1024 if (fragP->fr_subtype == 2)
1026 if ((address & 3) != 0)
1028 fragP->fr_subtype = 3;
1032 else if (fragP->fr_subtype == 3)
1034 if ((address & 3) == 0)
1036 fragP->fr_subtype = 2;
1042 growth = relax_frag (fragP, stretch);
1044 /* Long jump on odd halfword boundary? */
1045 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1047 fragP->fr_subtype = 3;
1055 /* Return an initial guess of the length by which a fragment must grow to
1056 hold a branch to reach its destination.
1057 Also updates fr_type/fr_subtype as necessary.
1059 Called just before doing relaxation.
1060 Any symbol that is now undefined will not become defined.
1061 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1062 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1063 Although it may not be explicit in the frag, pretend fr_var starts with a
1067 md_estimate_size_before_relax (fragP, segment)
1071 int old_fr_fix = fragP->fr_fix;
1072 char * opcode = fragP->fr_opcode;
1074 /* The only thing we have to handle here are symbols outside of the
1075 current segment. They may be undefined or in a different segment in
1076 which case linker scripts may place them anywhere.
1077 However, we can't finish the fragment here and emit the reloc as insn
1078 alignment requirements may move the insn about. */
1080 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1082 /* The symbol is undefined in this segment.
1083 Change the relaxation subtype to the max allowable and leave
1084 all further handling to md_convert_frag. */
1085 fragP->fr_subtype = 2;
1087 #if 0 /* Can't use this, but leave in for illustration. */
1088 /* Change 16 bit insn to 32 bit insn. */
1091 /* Increase known (fixed) size of fragment. */
1094 /* Create a relocation for it. */
1095 fix_new (fragP, old_fr_fix, 4,
1097 fragP->fr_offset, 1 /* pcrel */,
1098 /* FIXME: Can't use a real BFD reloc here.
1099 cgen_md_apply_fix3 can't handle it. */
1100 BFD_RELOC_M32R_26_PCREL);
1102 /* Mark this fragment as finished. */
1106 const CGEN_INSN * insn;
1109 /* Update the recorded insn.
1110 Fortunately we don't have to look very far.
1111 FIXME: Change this to record in the instruction the next higher
1112 relaxable insn to use. */
1113 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1115 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1116 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1118 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1124 fragP->fr_cgen.insn = insn;
1130 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1133 /* *fragP has been relaxed to its final size, and now needs to have
1134 the bytes inside it modified to conform to the new size.
1136 Called after relaxation is finished.
1137 fragP->fr_type == rs_machine_dependent.
1138 fragP->fr_subtype is the subtype of what the address relaxed to. */
1141 md_convert_frag (abfd, sec, fragP)
1147 char * displacement;
1153 opcode = fragP->fr_opcode;
1155 /* Address opcode resides at in file space. */
1156 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1158 switch (fragP->fr_subtype)
1162 displacement = & opcode[1];
1167 displacement = & opcode[1];
1170 opcode[2] = opcode[0] | 0x80;
1171 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1172 opcode_address += 2;
1174 displacement = & opcode[3];
1180 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1182 /* symbol must be resolved by linker */
1183 if (fragP->fr_offset & 3)
1184 as_warn ("Addend to unresolved symbol not on word boundary.");
1185 addend = fragP->fr_offset >> 2;
1189 /* Address we want to reach in file space. */
1190 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1191 target_address += fragP->fr_symbol->sy_frag->fr_address;
1192 addend = (target_address - (opcode_address & -4)) >> 2;
1195 /* Create a relocation for symbols that must be resolved by the linker.
1196 Otherwise output the completed insn. */
1198 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1200 assert (fragP->fr_subtype != 1);
1201 assert (fragP->fr_cgen.insn != 0);
1202 cgen_record_fixup (fragP,
1203 /* Offset of branch insn in frag. */
1204 fragP->fr_fix + extension - 4,
1205 fragP->fr_cgen.insn,
1207 /* FIXME: quick hack */
1209 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1211 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1213 fragP->fr_cgen.opinfo,
1214 fragP->fr_symbol, fragP->fr_offset);
1217 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1219 md_number_to_chars (displacement, (valueT) addend,
1220 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1222 fragP->fr_fix += extension;
1225 /* Functions concerning relocs. */
1227 /* The location from which a PC relative jump should be calculated,
1228 given a PC relative reloc. */
1231 md_pcrel_from_section (fixP, sec)
1235 if (fixP->fx_addsy != (symbolS *) NULL
1236 && (! S_IS_DEFINED (fixP->fx_addsy)
1237 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1239 /* The symbol is undefined (or is defined but not in this section).
1240 Let the linker figure it out. */
1244 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1247 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1248 Returns BFD_RELOC_NONE if no reloc type can be found.
1249 *FIXP may be modified if desired. */
1251 bfd_reloc_code_real_type
1252 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1253 const CGEN_INSN * insn;
1254 const CGEN_OPERAND * operand;
1257 switch (CGEN_OPERAND_TYPE (operand))
1259 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1260 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1261 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1262 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1263 case M32R_OPERAND_HI16 :
1264 case M32R_OPERAND_SLO16 :
1265 case M32R_OPERAND_ULO16 :
1266 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1267 if (fixP->tc_fix_data.opinfo != 0)
1268 return fixP->tc_fix_data.opinfo;
1271 return BFD_RELOC_NONE;
1274 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1277 m32r_record_hi16 (reloc_type, fixP, seg)
1282 struct m32r_hi_fixup * hi_fixup;
1284 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1285 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1287 hi_fixup = ((struct m32r_hi_fixup *)
1288 xmalloc (sizeof (struct m32r_hi_fixup)));
1289 hi_fixup->fixp = fixP;
1290 hi_fixup->seg = now_seg;
1291 hi_fixup->next = m32r_hi_fixup_list;
1293 m32r_hi_fixup_list = hi_fixup;
1296 /* Called while parsing an instruction to create a fixup.
1297 We need to check for HI16 relocs and queue them up for later sorting. */
1300 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1303 const CGEN_INSN * insn;
1305 const CGEN_OPERAND * operand;
1309 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1310 operand, opinfo, exp);
1312 switch (CGEN_OPERAND_TYPE (operand))
1314 case M32R_OPERAND_HI16 :
1315 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1316 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1317 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1318 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1325 /* Return BFD reloc type from opinfo field in a fixS.
1326 It's tricky using fx_r_type in m32r_frob_file because the values
1327 are BFD_RELOC_UNUSED + operand number. */
1328 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1330 /* Sort any unmatched HI16 relocs so that they immediately precede
1331 the corresponding LO16 reloc. This is called before md_apply_fix and
1337 struct m32r_hi_fixup * l;
1339 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1341 segment_info_type * seginfo;
1344 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1345 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1347 /* Check quickly whether the next fixup happens to be a matching low. */
1348 if (l->fixp->fx_next != NULL
1349 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1350 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1351 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1354 /* Look through the fixups for this segment for a matching `low'.
1355 When we find one, move the high/shigh just in front of it. We do
1356 this in two passes. In the first pass, we try to find a
1357 unique `low'. In the second pass, we permit multiple high's
1358 relocs for a single `low'. */
1359 seginfo = seg_info (l->seg);
1360 for (pass = 0; pass < 2; pass++)
1366 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1368 /* Check whether this is a `low' fixup which matches l->fixp. */
1369 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1370 && f->fx_addsy == l->fixp->fx_addsy
1371 && f->fx_offset == l->fixp->fx_offset
1374 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1375 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1376 || prev->fx_addsy != f->fx_addsy
1377 || prev->fx_offset != f->fx_offset))
1381 /* Move l->fixp before f. */
1382 for (pf = &seginfo->fix_root;
1384 pf = & (* pf)->fx_next)
1385 assert (* pf != NULL);
1387 * pf = l->fixp->fx_next;
1389 l->fixp->fx_next = f;
1391 seginfo->fix_root = l->fixp;
1393 prev->fx_next = l->fixp;
1405 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1406 "Unmatched high/shigh reloc");
1411 /* See whether we need to force a relocation into the output file.
1412 This is used to force out switch and PC relative relocations when
1416 m32r_force_relocation (fix)
1422 return (fix->fx_pcrel
1426 /* Write a value out to the object file, using the appropriate endianness. */
1429 md_number_to_chars (buf, val, n)
1434 if (target_big_endian)
1435 number_to_chars_bigendian (buf, val, n);
1437 number_to_chars_littleendian (buf, val, n);
1440 /* Turn a string in input_line_pointer into a floating point constant of type
1441 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1442 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1445 /* Equal to MAX_PRECISION in atof-ieee.c */
1446 #define MAX_LITTLENUMS 6
1449 md_atof (type, litP, sizeP)
1456 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1457 LITTLENUM_TYPE * wordP;
1459 char * atof_ieee ();
1477 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1481 return "Bad call to md_atof()";
1484 t = atof_ieee (input_line_pointer, type, words);
1486 input_line_pointer = t;
1487 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1489 if (target_big_endian)
1491 for (i = 0; i < prec; i++)
1493 md_number_to_chars (litP, (valueT) words[i],
1494 sizeof (LITTLENUM_TYPE));
1495 litP += sizeof (LITTLENUM_TYPE);
1500 for (i = prec - 1; i >= 0; i--)
1502 md_number_to_chars (litP, (valueT) words[i],
1503 sizeof (LITTLENUM_TYPE));
1504 litP += sizeof (LITTLENUM_TYPE);