1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
2 Copyright (C) 1996, 1997 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 /* Non-null if last insn was a 16 bit insn on a 32 bit boundary
28 (i.e. was the first of two 16 bit insns). */
29 static const CGEN_INSN *prev_insn = NULL;
31 /* Non-zero if we've seen a relaxable insn since the last 32 bit
33 static int seen_relaxable_p = 0;
35 /* Non-zero if -relax specified, in which case sufficient relocs are output
36 for the linker to do relaxing.
37 We do simple forms of relaxing internally, but they are always done.
38 This flag does not apply to them. */
39 static int m32r_relax;
41 /* If non-NULL, pointer to cpu description file to read.
42 This allows runtime additions to the assembler. */
43 static char *m32r_cpu_desc;
45 /* start-sanitize-m32rx */
46 /* Non-zero if -m32rx has been specified, in which case support for the
47 extended M32RX instruction set should be enabled. */
48 /* Indicates the target BFD machine number. */
49 static int enable_m32rx = 0;
50 /* end-sanitize-m32rx */
52 /* stuff for .scomm symbols. */
53 static segT sbss_section;
54 static asection scom_section;
55 static asymbol scom_symbol;
57 const char comment_chars[] = ";";
58 const char line_comment_chars[] = "#";
59 const char line_separator_chars[] = "";
60 const char EXP_CHARS[] = "eE";
61 const char FLT_CHARS[] = "dD";
63 /* Relocations against symbols are done in two
64 parts, with a HI relocation and a LO relocation. Each relocation
65 has only 16 bits of space to store an addend. This means that in
66 order for the linker to handle carries correctly, it must be able
67 to locate both the HI and the LO relocation. This means that the
68 relocations must appear in order in the relocation table.
70 In order to implement this, we keep track of each unmatched HI
71 relocation. We then sort them so that they immediately precede the
72 corresponding LO relocation. */
77 struct m32r_hi_fixup *next;
80 /* The section this fixup is in. */
84 /* The list of unmatched HI relocs. */
86 static struct m32r_hi_fixup *m32r_hi_fixup_list;
88 static void m32r_record_hi16 PARAMS ((int, fixS *, segT seg));
91 /* start-sanitize-m32rx */
97 if (stdoutput != NULL)
98 bfd_set_arch_mach (stdoutput, TARGET_ARCH, enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
100 /* end-sanitize-m32rx */
102 const char *md_shortopts = "";
104 struct option md_longopts[] =
106 /* start-sanitize-m32rx */
107 #define OPTION_M32RX (OPTION_MD_BASE)
108 {"m32rx", no_argument, NULL, OPTION_M32RX},
109 /* end-sanitize-m32rx */
111 #if 0 /* not supported yet */
112 #define OPTION_RELAX (OPTION_MD_BASE + 1)
113 {"relax", no_argument, NULL, OPTION_RELAX},
114 #define OPTION_CPU_DESC (OPTION_MD_BASE + 2)
115 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
118 {NULL, no_argument, NULL, 0}
120 size_t md_longopts_size = sizeof(md_longopts);
123 md_parse_option (c, arg)
129 /* start-sanitize-m32rx */
133 /* end-sanitize-m32rx */
135 #if 0 /* not supported yet */
139 case OPTION_CPU_DESC:
150 md_show_usage (stream)
153 fprintf (stream, "M32R/X options:\n");
154 /* start-sanitize-m32rx */
156 --m32rx support the extended m32rx instruction set\n");
157 /* end-sanitize-m32rx */
161 --relax create linker relaxable code\n");
163 --cpu-desc provide runtime cpu description file\n");
167 static void fill_insn PARAMS ((int));
168 static void m32r_scomm PARAMS ((int));
170 /* Set by md_assemble for use by m32r_fill_insn. */
171 static subsegT prev_subseg;
172 static segT prev_seg;
174 /* The target specific pseudo-ops which we support. */
175 const pseudo_typeS md_pseudo_table[] =
178 { "fillinsn", fill_insn, 0 },
179 { "scomm", m32r_scomm, 0 },
180 /* start-sanitize-m32rx */
181 { "m32r", allow_m32rx, 0},
182 { "m32rx", allow_m32rx, 1},
183 /* end-sanitize-m32rx */
187 /* FIXME: Should be machine generated. */
188 #define NOP_INSN 0x7000
189 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
191 /* When we align the .text section, insert the correct NOP pattern.
192 N is the power of 2 alignment. LEN is the length of pattern FILL.
193 MAX is the maximum number of characters to skip when doing the alignment,
194 or 0 if there is no maximum. */
197 m32r_do_align (n, fill, len, max)
203 if ((fill == NULL || (*fill == 0 && len == 1))
204 && (now_seg->flags & SEC_CODE) != 0
205 /* Only do this special handling if aligning to at least a
208 /* Only do this special handling if we're allowed to emit at
210 && (max == 0 || max > 1))
212 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
215 /* First align to a 2 byte boundary, in case there is an odd .byte. */
216 /* FIXME: How much memory will cause gas to use when assembling a big
217 program? Perhaps we can avoid the frag_align call? */
218 frag_align (1, 0, 0);
220 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
222 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
223 /* If doing larger alignments use a repeating sequence of appropriate
227 static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
228 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
238 assemble_nop (opcode)
241 char *f = frag_more (2);
242 md_number_to_chars (f, opcode, 2);
245 /* If the last instruction was the first of 2 16 bit insns,
246 output a nop to move the PC to a 32 bit boundary.
248 This is done via an alignment specification since branch relaxing
249 may make it unnecessary.
251 Internally, we need to output one of these each time a 32 bit insn is
252 seen after an insn that is relaxable. */
258 (void) m32r_do_align (2, NULL, 0, 0);
260 seen_relaxable_p = 0;
263 /* Cover function to fill_insn called after a label and at end of assembly.
265 The result is always 1: we're called in a conditional to see if the
266 current line is a label. */
269 m32r_fill_insn (done)
275 if (prev_seg != NULL)
279 subseg_set (prev_seg, prev_subseg);
281 subseg_set (seg, subseg);
293 /* Initialize the `cgen' interface. */
295 /* This is a callback from cgen to gas to parse operands. */
296 cgen_parse_operand_fn = cgen_parse_operand;
297 /* Set the machine number and endian. */
298 CGEN_SYM (init_asm) (0 /* mach number */,
299 target_big_endian ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
301 #if 0 /* not supported yet */
302 /* If a runtime cpu description file was provided, parse it. */
303 if (m32r_cpu_desc != NULL)
307 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
309 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
313 /* Save the current subseg so we can restore it [it's the default one and
314 we don't want the initial section to be .sbss. */
318 /* The sbss section is for local .scomm symbols. */
319 sbss_section = subseg_new (".sbss", 0);
320 /* This is copied from perform_an_assembly_pass. */
321 applicable = bfd_applicable_section_flags (stdoutput);
322 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
323 #if 0 /* What does this do? [see perform_an_assembly_pass] */
324 seg_info (bss_section)->bss = 1;
327 subseg_set (seg, subseg);
329 /* We must construct a fake section similar to bfd_com_section
330 but with the name .scommon. */
331 scom_section = bfd_com_section;
332 scom_section.name = ".scommon";
333 scom_section.output_section = &scom_section;
334 scom_section.symbol = &scom_symbol;
335 scom_section.symbol_ptr_ptr = &scom_section.symbol;
336 scom_symbol = *bfd_com_section.symbol;
337 scom_symbol.name = ".scommon";
338 scom_symbol.section = &scom_section;
340 /* start-sanitize-m32rx */
341 allow_m32rx (enable_m32rx);
342 /* end-sanitize-m32rx */
350 cgen_insn_t buffer[CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
352 char buffer[CGEN_MAX_INSN_SIZE];
355 const CGEN_INSN *insn;
358 /* Initialize GAS's cgen interface for a new instruction. */
359 cgen_asm_init_parse ();
361 insn = CGEN_SYM (assemble_insn) (str, &fields, buffer, &errmsg);
368 if (CGEN_INSN_BITSIZE (insn) == 32)
370 /* 32 bit insns must live on 32 bit boundaries. */
371 /* FIXME: If calling fill_insn too many times turns us into a memory
372 pig, can we call assemble_nop instead of !seen_relaxable_p? */
373 if (prev_insn || seen_relaxable_p)
375 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields));
379 /* Keep track of whether we've seen a pair of 16 bit insns.
380 PREV_INSN is NULL when we're on a 32 bit boundary. */
385 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields));
387 /* If the insn needs the following one to be on a 32 bit boundary
388 (e.g. subroutine calls), fill this insn's slot. */
390 && CGEN_INSN_ATTR (insn, CGEN_INSN_FILL_SLOT) != 0)
394 /* If this is a relaxable insn (can be replaced with a larger version)
395 mark the fact so that we can emit an alignment directive for a following
396 32 bit insn if we see one. */
397 if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAXABLE) != 0)
398 seen_relaxable_p = 1;
400 /* Set these so m32r_fill_insn can use them. */
402 prev_subseg = now_subseg;
405 /* The syntax in the manual says constants begin with '#'.
406 We just ignore it. */
409 md_operand (expressionP)
410 expressionS *expressionP;
412 if (*input_line_pointer == '#')
414 input_line_pointer++;
415 expression (expressionP);
420 md_section_align (segment, size)
424 int align = bfd_get_section_alignment (stdoutput, segment);
425 return ((size + (1 << align) - 1) & (-1 << align));
429 md_undefined_symbol (name)
435 /* .scomm pseudo-op handler.
437 This is a new pseudo-op to handle putting objects in .scommon.
438 By doing this the linker won't need to do any work and more importantly
439 it removes the implicit -G arg necessary to correctly link the object file.
450 register symbolS *symbolP;
454 name = input_line_pointer;
455 c = get_symbol_end ();
457 /* just after name is now '\0' */
458 p = input_line_pointer;
461 if (*input_line_pointer != ',')
463 as_bad ("Expected comma after symbol-name: rest of line ignored.");
464 ignore_rest_of_line ();
468 input_line_pointer++; /* skip ',' */
469 if ((size = get_absolute_expression ()) < 0)
471 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
472 ignore_rest_of_line ();
476 /* The third argument to .scomm is the alignment. */
477 if (*input_line_pointer != ',')
481 ++input_line_pointer;
482 align = get_absolute_expression ();
485 as_warn ("ignoring bad alignment");
489 /* Convert to a power of 2 alignment. */
492 for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
496 as_bad ("Common alignment not a power of 2");
497 ignore_rest_of_line ();
505 symbolP = symbol_find_or_make (name);
508 if (S_IS_DEFINED (symbolP))
510 as_bad ("Ignoring attempt to re-define symbol `%s'.",
511 S_GET_NAME (symbolP));
512 ignore_rest_of_line ();
516 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
518 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
519 S_GET_NAME (symbolP),
520 (long) S_GET_VALUE (symbolP),
523 ignore_rest_of_line ();
529 segT old_sec = now_seg;
530 int old_subsec = now_subseg;
533 record_alignment (sbss_section, align2);
534 subseg_set (sbss_section, 0);
536 frag_align (align2, 0, 0);
537 if (S_GET_SEGMENT (symbolP) == sbss_section)
538 symbolP->sy_frag->fr_symbol = 0;
539 symbolP->sy_frag = frag_now;
540 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
543 S_SET_SIZE (symbolP, size);
544 S_SET_SEGMENT (symbolP, sbss_section);
545 S_CLEAR_EXTERNAL (symbolP);
546 subseg_set (old_sec, old_subsec);
550 S_SET_VALUE (symbolP, (valueT) size);
551 S_SET_ALIGN (symbolP, align2);
552 S_SET_EXTERNAL (symbolP);
553 S_SET_SEGMENT (symbolP, &scom_section);
556 demand_empty_rest_of_line ();
559 /* Interface to relax_segment. */
561 /* FIXME: Build table by hand, get it working, then machine generate. */
563 const relax_typeS md_relax_table[] =
566 1) most positive reach of this state,
567 2) most negative reach of this state,
568 3) how many bytes this mode will add to the size of the current frag
569 4) which index into the table to try if we can't fit into this one. */
571 /* The first entry must be unused because an `rlx_more' value of zero ends
575 /* The displacement used by GAS is from the end of the 2 byte insn,
576 so we subtract 2 from the following. */
577 /* 16 bit insn, 8 bit disp -> 10 bit range.
578 This doesn't handle a branch in the right slot at the border:
579 the "& -4" isn't taken into account. It's not important enough to
580 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
582 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
583 /* 32 bit insn, 24 bit disp -> 26 bit range. */
584 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
585 /* Same thing, but with leading nop for alignment. */
586 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
590 m32r_relax_frag (fragP, stretch)
594 /* Address of branch insn. */
595 long address = fragP->fr_address + fragP->fr_fix - 2;
598 /* Keep 32 bit insns aligned on 32 bit boundaries. */
599 if (fragP->fr_subtype == 2)
601 if ((address & 3) != 0)
603 fragP->fr_subtype = 3;
607 else if (fragP->fr_subtype == 3)
609 if ((address & 3) == 0)
611 fragP->fr_subtype = 2;
617 growth = relax_frag (fragP, stretch);
619 /* Long jump on odd halfword boundary? */
620 if (fragP->fr_subtype == 2 && (address & 3) != 0)
622 fragP->fr_subtype = 3;
630 /* Return an initial guess of the length by which a fragment must grow to
631 hold a branch to reach its destination.
632 Also updates fr_type/fr_subtype as necessary.
634 Called just before doing relaxation.
635 Any symbol that is now undefined will not become defined.
636 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
637 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
638 Although it may not be explicit in the frag, pretend fr_var starts with a
642 md_estimate_size_before_relax (fragP, segment)
646 int old_fr_fix = fragP->fr_fix;
647 char *opcode = fragP->fr_opcode;
649 /* The only thing we have to handle here are symbols outside of the
650 current segment. They may be undefined or in a different segment in
651 which case linker scripts may place them anywhere.
652 However, we can't finish the fragment here and emit the reloc as insn
653 alignment requirements may move the insn about. */
655 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
657 /* The symbol is undefined in this segment.
658 Change the relaxation subtype to the max allowable and leave
659 all further handling to md_convert_frag. */
660 fragP->fr_subtype = 2;
662 #if 0 /* Can't use this, but leave in for illustration. */
663 /* Change 16 bit insn to 32 bit insn. */
666 /* Increase known (fixed) size of fragment. */
669 /* Create a relocation for it. */
670 fix_new (fragP, old_fr_fix, 4,
672 fragP->fr_offset, 1 /* pcrel */,
673 /* FIXME: Can't use a real BFD reloc here.
674 cgen_md_apply_fix3 can't handle it. */
675 BFD_RELOC_M32R_26_PCREL);
677 /* Mark this fragment as finished. */
681 const CGEN_INSN *insn;
684 /* Update the recorded insn.
685 Fortunately we don't have to look very far.
686 FIXME: Change this to record in the instruction the next higher
687 relaxable insn to use. */
688 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
690 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
691 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
693 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
698 fragP->fr_cgen.insn = insn;
704 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
707 /* *fragP has been relaxed to its final size, and now needs to have
708 the bytes inside it modified to conform to the new size.
710 Called after relaxation is finished.
711 fragP->fr_type == rs_machine_dependent.
712 fragP->fr_subtype is the subtype of what the address relaxed to. */
715 md_convert_frag (abfd, sec, fragP)
720 char *opcode, *displacement;
721 int target_address, opcode_address, extension, addend;
723 opcode = fragP->fr_opcode;
725 /* Address opcode resides at in file space. */
726 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
728 switch (fragP->fr_subtype)
732 displacement = &opcode[1];
737 displacement = &opcode[1];
740 opcode[2] = opcode[0] | 0x80;
741 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
744 displacement = &opcode[3];
750 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
752 /* symbol must be resolved by linker */
753 if (fragP->fr_offset & 3)
754 as_warn ("Addend to unresolved symbol not on word boundary.");
755 addend = fragP->fr_offset >> 2;
759 /* Address we want to reach in file space. */
760 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
761 target_address += fragP->fr_symbol->sy_frag->fr_address;
762 addend = (target_address - (opcode_address & -4)) >> 2;
765 /* Create a relocation for symbols that must be resolved by the linker.
766 Otherwise output the completed insn. */
768 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
770 assert (fragP->fr_subtype != 1);
771 assert (fragP->fr_cgen.insn != 0);
772 cgen_record_fixup (fragP,
773 /* Offset of branch insn in frag. */
774 fragP->fr_fix + extension - 4,
777 /* FIXME: quick hack */
779 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
781 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
783 fragP->fr_cgen.opinfo,
784 fragP->fr_symbol, fragP->fr_offset);
787 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
789 md_number_to_chars (displacement, (valueT) addend,
790 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
792 fragP->fr_fix += extension;
795 /* Functions concerning relocs. */
797 /* The location from which a PC relative jump should be calculated,
798 given a PC relative reloc. */
801 md_pcrel_from_section (fixP, sec)
805 if (fixP->fx_addsy != (symbolS *) NULL
806 && (! S_IS_DEFINED (fixP->fx_addsy)
807 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
809 /* The symbol is undefined (or is defined but not in this section).
810 Let the linker figure it out. */
814 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
817 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
818 Returns BFD_RELOC_NONE if no reloc type can be found.
819 *FIXP may be modified if desired. */
821 bfd_reloc_code_real_type
822 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
823 const CGEN_INSN *insn;
824 const CGEN_OPERAND *operand;
827 switch (CGEN_OPERAND_TYPE (operand))
829 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
830 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
831 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
832 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
833 case M32R_OPERAND_HI16 :
834 case M32R_OPERAND_SLO16 :
835 case M32R_OPERAND_ULO16 :
836 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
837 if (fixP->tc_fix_data.opinfo != 0)
838 return fixP->tc_fix_data.opinfo;
841 return BFD_RELOC_NONE;
844 /* Called while parsing an instruction to create a fixup.
845 We need to check for HI16 relocs and queue them up for later sorting. */
848 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
851 const CGEN_INSN *insn;
853 const CGEN_OPERAND *operand;
857 fixS *fixP = cgen_record_fixup_exp (frag, where, insn, length,
858 operand, opinfo, exp);
860 switch (CGEN_OPERAND_TYPE (operand))
862 case M32R_OPERAND_HI16 :
863 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
864 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
865 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
866 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
873 /* Record a HI16 reloc for later matching with its LO16 cousin. */
876 m32r_record_hi16 (reloc_type, fixP, seg)
881 struct m32r_hi_fixup *hi_fixup;
883 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
884 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
886 hi_fixup = ((struct m32r_hi_fixup *)
887 xmalloc (sizeof (struct m32r_hi_fixup)));
888 hi_fixup->fixp = fixP;
889 hi_fixup->seg = now_seg;
890 hi_fixup->next = m32r_hi_fixup_list;
891 m32r_hi_fixup_list = hi_fixup;
894 /* Return BFD reloc type from opinfo field in a fixS.
895 It's tricky using fx_r_type in m32r_frob_file because the values
896 are BFD_RELOC_UNUSED + operand number. */
897 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
899 /* Sort any unmatched HI16 relocs so that they immediately precede
900 the corresponding LO16 reloc. This is called before md_apply_fix and
906 struct m32r_hi_fixup *l;
908 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
910 segment_info_type *seginfo;
913 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
914 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
916 /* Check quickly whether the next fixup happens to be a matching low. */
917 if (l->fixp->fx_next != NULL
918 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
919 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
920 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
923 /* Look through the fixups for this segment for a matching `low'.
924 When we find one, move the high/shigh just in front of it. We do
925 this in two passes. In the first pass, we try to find a
926 unique `low'. In the second pass, we permit multiple high's
927 relocs for a single `low'. */
928 seginfo = seg_info (l->seg);
929 for (pass = 0; pass < 2; pass++)
934 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
936 /* Check whether this is a `low' fixup which matches l->fixp. */
937 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
938 && f->fx_addsy == l->fixp->fx_addsy
939 && f->fx_offset == l->fixp->fx_offset
942 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
943 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
944 || prev->fx_addsy != f->fx_addsy
945 || prev->fx_offset != f->fx_offset))
949 /* Move l->fixp before f. */
950 for (pf = &seginfo->fix_root;
952 pf = &(*pf)->fx_next)
953 assert (*pf != NULL);
955 *pf = l->fixp->fx_next;
957 l->fixp->fx_next = f;
959 seginfo->fix_root = l->fixp;
961 prev->fx_next = l->fixp;
973 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
974 "Unmatched high/shigh reloc");
979 /* See whether we need to force a relocation into the output file.
980 This is used to force out switch and PC relative relocations when
984 m32r_force_relocation (fix)
990 return (fix->fx_pcrel
994 /* Write a value out to the object file, using the appropriate endianness. */
997 md_number_to_chars (buf, val, n)
1002 if (target_big_endian)
1003 number_to_chars_bigendian (buf, val, n);
1005 number_to_chars_littleendian (buf, val, n);
1008 /* Turn a string in input_line_pointer into a floating point constant of type
1009 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1010 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1013 /* Equal to MAX_PRECISION in atof-ieee.c */
1014 #define MAX_LITTLENUMS 6
1017 md_atof (type, litP, sizeP)
1023 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1024 LITTLENUM_TYPE *wordP;
1044 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1048 return "Bad call to md_atof()";
1051 t = atof_ieee (input_line_pointer, type, words);
1053 input_line_pointer = t;
1054 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1056 if (target_big_endian)
1058 for (i = 0; i < prec; i++)
1060 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1061 litP += sizeof (LITTLENUM_TYPE);
1066 for (i = prec - 1; i >= 0; i--)
1068 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1069 litP += sizeof (LITTLENUM_TYPE);