1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
2 Copyright (C) 1996, 1997 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 /* Non-null if last insn was a 16 bit insn on a 32 bit boundary
28 (i.e. was the first of two 16 bit insns). */
29 static const struct cgen_insn *prev_insn = NULL;
31 /* Non-zero if we've seen a relaxable insn since the last 32 bit
33 static int seen_relaxable_p = 0;
35 /* Non-zero if -relax specified, in which case sufficient relocs are output
36 for the linker to do relaxing.
37 We do simple forms of relaxing internally, but they are always done.
38 This flag does not apply to them. */
39 static int m32r_relax;
41 /* If non-NULL, pointer to cpu description file to read.
42 This allows runtime additions to the assembler. */
43 static char *m32r_cpu_desc;
45 /* Non-zero if -m32rx has been specified, in which case support for the
46 extended M32RX instruction set should be enabled. */
47 /* Indicates the target BFD machine number. */
48 static int enable_m32rx = 0;
50 /* stuff for .scomm symbols. */
51 static segT sbss_section;
52 static asection scom_section;
53 static asymbol scom_symbol;
55 const char comment_chars[] = ";";
56 const char line_comment_chars[] = "#";
57 const char line_separator_chars[] = "";
58 const char EXP_CHARS[] = "eE";
59 const char FLT_CHARS[] = "dD";
61 /* Relocations against symbols are done in two
62 parts, with a HI relocation and a LO relocation. Each relocation
63 has only 16 bits of space to store an addend. This means that in
64 order for the linker to handle carries correctly, it must be able
65 to locate both the HI and the LO relocation. This means that the
66 relocations must appear in order in the relocation table.
68 In order to implement this, we keep track of each unmatched HI
69 relocation. We then sort them so that they immediately precede the
70 corresponding LO relocation. */
75 struct m32r_hi_fixup *next;
78 /* The section this fixup is in. */
82 /* The list of unmatched HI relocs. */
84 static struct m32r_hi_fixup *m32r_hi_fixup_list;
86 static void m32r_record_hi16 PARAMS ((int, fixS *, segT seg));
94 if (stdoutput != NULL)
95 bfd_set_arch_mach (stdoutput, TARGET_ARCH, enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
98 const char *md_shortopts = "";
100 struct option md_longopts[] =
102 #define OPTION_M32RX (OPTION_MD_BASE)
103 {"m32rx", no_argument, NULL, OPTION_M32RX},
105 #if 0 /* not supported yet */
106 #define OPTION_RELAX (OPTION_MD_BASE + 1)
107 {"relax", no_argument, NULL, OPTION_RELAX},
108 #define OPTION_CPU_DESC (OPTION_MD_BASE + 2)
109 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
112 {NULL, no_argument, NULL, 0}
114 size_t md_longopts_size = sizeof(md_longopts);
117 md_parse_option (c, arg)
127 #if 0 /* not supported yet */
131 case OPTION_CPU_DESC:
142 md_show_usage (stream)
145 fprintf (stream, "M32R/X options:\n");
147 --m32rx support the extended m32rx instruction set\n");
151 --relax create linker relaxable code\n");
153 --cpu-desc provide runtime cpu description file\n");
157 static void fill_insn PARAMS ((int));
158 static void m32r_scomm PARAMS ((int));
160 /* Set by md_assemble for use by m32r_fill_insn. */
161 static subsegT prev_subseg;
162 static segT prev_seg;
164 /* The target specific pseudo-ops which we support. */
165 const pseudo_typeS md_pseudo_table[] =
168 { "fillinsn", fill_insn, 0 },
169 { "scomm", m32r_scomm, 0 },
170 { "m32r", allow_m32rx, 0},
171 { "m32rx", allow_m32rx, 1},
175 /* FIXME: Should be machine generated. */
176 #define NOP_INSN 0x7000
177 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
179 /* When we align the .text section, insert the correct NOP pattern.
180 N is the power of 2 alignment. LEN is the length of pattern FILL.
181 MAX is the maximum number of characters to skip when doing the alignment,
182 or 0 if there is no maximum. */
185 m32r_do_align (n, fill, len, max)
191 if ((fill == NULL || (*fill == 0 && len == 1))
192 && (now_seg->flags & SEC_CODE) != 0
193 /* Only do this special handling if aligning to at least a
196 /* Only do this special handling if we're allowed to emit at
198 && (max == 0 || max > 1))
200 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
203 /* First align to a 2 byte boundary, in case there is an odd .byte. */
204 /* FIXME: How much memory will cause gas to use when assembling a big
205 program? Perhaps we can avoid the frag_align call? */
206 frag_align (1, 0, 0);
208 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
210 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
211 /* If doing larger alignments use a repeating sequence of appropriate
215 static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
216 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
226 assemble_nop (opcode)
229 char *f = frag_more (2);
230 md_number_to_chars (f, opcode, 2);
233 /* If the last instruction was the first of 2 16 bit insns,
234 output a nop to move the PC to a 32 bit boundary.
236 This is done via an alignment specification since branch relaxing
237 may make it unnecessary.
239 Internally, we need to output one of these each time a 32 bit insn is
240 seen after an insn that is relaxable. */
246 (void) m32r_do_align (2, NULL, 0, 0);
248 seen_relaxable_p = 0;
251 /* Cover function to fill_insn called after a label and at end of assembly.
253 The result is always 1: we're called in a conditional to see if the
254 current line is a label. */
257 m32r_fill_insn (done)
263 if (prev_seg != NULL)
267 subseg_set (prev_seg, prev_subseg);
269 subseg_set (seg, subseg);
281 /* Initialize the `cgen' interface. */
283 /* This is a callback from cgen to gas to parse operands. */
284 cgen_parse_operand_fn = cgen_parse_operand;
285 /* Set the machine number and endian. */
286 CGEN_SYM (init_asm) (0 /* mach number */,
287 target_big_endian ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
289 #if 0 /* not supported yet */
290 /* If a runtime cpu description file was provided, parse it. */
291 if (m32r_cpu_desc != NULL)
295 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
297 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
301 /* Save the current subseg so we can restore it [it's the default one and
302 we don't want the initial section to be .sbss. */
306 /* The sbss section is for local .scomm symbols. */
307 sbss_section = subseg_new (".sbss", 0);
308 /* This is copied from perform_an_assembly_pass. */
309 applicable = bfd_applicable_section_flags (stdoutput);
310 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
311 #if 0 /* What does this do? [see perform_an_assembly_pass] */
312 seg_info (bss_section)->bss = 1;
315 subseg_set (seg, subseg);
317 /* We must construct a fake section similar to bfd_com_section
318 but with the name .scommon. */
319 scom_section = bfd_com_section;
320 scom_section.name = ".scommon";
321 scom_section.output_section = &scom_section;
322 scom_section.symbol = &scom_symbol;
323 scom_section.symbol_ptr_ptr = &scom_section.symbol;
324 scom_symbol = *bfd_com_section.symbol;
325 scom_symbol.name = ".scommon";
326 scom_symbol.section = &scom_section;
328 allow_m32rx (enable_m32rx);
336 cgen_insn_t buffer[CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
338 char buffer[CGEN_MAX_INSN_SIZE];
340 struct cgen_fields fields;
341 const struct cgen_insn *insn;
344 /* Initialize GAS's cgen interface for a new instruction. */
345 cgen_asm_init_parse ();
347 insn = CGEN_SYM (assemble_insn) (str, &fields, buffer, &errmsg);
354 if (CGEN_INSN_BITSIZE (insn) == 32)
356 /* 32 bit insns must live on 32 bit boundaries. */
357 /* FIXME: If calling fill_insn too many times turns us into a memory
358 pig, can we call assemble_nop instead of !seen_relaxable_p? */
359 if (prev_insn || seen_relaxable_p)
361 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields));
365 /* Keep track of whether we've seen a pair of 16 bit insns.
366 PREV_INSN is NULL when we're on a 32 bit boundary. */
371 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields));
373 /* If the insn needs the following one to be on a 32 bit boundary
374 (e.g. subroutine calls), fill this insn's slot. */
376 && CGEN_INSN_ATTR (insn, CGEN_INSN_FILL_SLOT) != 0)
380 /* If this is a relaxable insn (can be replaced with a larger version)
381 mark the fact so that we can emit an alignment directive for a following
382 32 bit insn if we see one. */
383 if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAXABLE) != 0)
384 seen_relaxable_p = 1;
386 /* Set these so m32r_fill_insn can use them. */
388 prev_subseg = now_subseg;
391 /* The syntax in the manual says constants begin with '#'.
392 We just ignore it. */
395 md_operand (expressionP)
396 expressionS *expressionP;
398 if (*input_line_pointer == '#')
400 input_line_pointer++;
401 expression (expressionP);
406 md_section_align (segment, size)
410 int align = bfd_get_section_alignment (stdoutput, segment);
411 return ((size + (1 << align) - 1) & (-1 << align));
415 md_undefined_symbol (name)
421 /* .scomm pseudo-op handler.
423 This is a new pseudo-op to handle putting objects in .scommon.
424 By doing this the linker won't need to do any work and more importantly
425 it removes the implicit -G arg necessary to correctly link the object file.
436 register symbolS *symbolP;
440 name = input_line_pointer;
441 c = get_symbol_end ();
443 /* just after name is now '\0' */
444 p = input_line_pointer;
447 if (*input_line_pointer != ',')
449 as_bad ("Expected comma after symbol-name: rest of line ignored.");
450 ignore_rest_of_line ();
454 input_line_pointer++; /* skip ',' */
455 if ((size = get_absolute_expression ()) < 0)
457 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
458 ignore_rest_of_line ();
462 /* The third argument to .scomm is the alignment. */
463 if (*input_line_pointer != ',')
467 ++input_line_pointer;
468 align = get_absolute_expression ();
471 as_warn ("ignoring bad alignment");
475 /* Convert to a power of 2 alignment. */
478 for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
482 as_bad ("Common alignment not a power of 2");
483 ignore_rest_of_line ();
491 symbolP = symbol_find_or_make (name);
494 if (S_IS_DEFINED (symbolP))
496 as_bad ("Ignoring attempt to re-define symbol `%s'.",
497 S_GET_NAME (symbolP));
498 ignore_rest_of_line ();
502 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
504 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
505 S_GET_NAME (symbolP),
506 (long) S_GET_VALUE (symbolP),
509 ignore_rest_of_line ();
515 segT old_sec = now_seg;
516 int old_subsec = now_subseg;
519 record_alignment (sbss_section, align2);
520 subseg_set (sbss_section, 0);
522 frag_align (align2, 0, 0);
523 if (S_GET_SEGMENT (symbolP) == sbss_section)
524 symbolP->sy_frag->fr_symbol = 0;
525 symbolP->sy_frag = frag_now;
526 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
529 S_SET_SIZE (symbolP, size);
530 S_SET_SEGMENT (symbolP, sbss_section);
531 S_CLEAR_EXTERNAL (symbolP);
532 subseg_set (old_sec, old_subsec);
536 S_SET_VALUE (symbolP, (valueT) size);
537 S_SET_ALIGN (symbolP, align2);
538 S_SET_EXTERNAL (symbolP);
539 S_SET_SEGMENT (symbolP, &scom_section);
542 demand_empty_rest_of_line ();
545 /* Interface to relax_segment. */
547 /* FIXME: Build table by hand, get it working, then machine generate. */
549 const relax_typeS md_relax_table[] =
552 1) most positive reach of this state,
553 2) most negative reach of this state,
554 3) how many bytes this mode will add to the size of the current frag
555 4) which index into the table to try if we can't fit into this one. */
557 /* The first entry must be unused because an `rlx_more' value of zero ends
561 /* The displacement used by GAS is from the end of the 2 byte insn,
562 so we subtract 2 from the following. */
563 /* 16 bit insn, 8 bit disp -> 10 bit range.
564 This doesn't handle a branch in the right slot at the border:
565 the "& -4" isn't taken into account. It's not important enough to
566 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
568 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
569 /* 32 bit insn, 24 bit disp -> 26 bit range. */
570 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
571 /* Same thing, but with leading nop for alignment. */
572 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
576 m32r_relax_frag (fragP, stretch)
580 /* Address of branch insn. */
581 long address = fragP->fr_address + fragP->fr_fix - 2;
584 /* Keep 32 bit insns aligned on 32 bit boundaries. */
585 if (fragP->fr_subtype == 2)
587 if ((address & 3) != 0)
589 fragP->fr_subtype = 3;
593 else if (fragP->fr_subtype == 3)
595 if ((address & 3) == 0)
597 fragP->fr_subtype = 2;
603 growth = relax_frag (fragP, stretch);
605 /* Long jump on odd halfword boundary? */
606 if (fragP->fr_subtype == 2 && (address & 3) != 0)
608 fragP->fr_subtype = 3;
616 /* Return an initial guess of the length by which a fragment must grow to
617 hold a branch to reach its destination.
618 Also updates fr_type/fr_subtype as necessary.
620 Called just before doing relaxation.
621 Any symbol that is now undefined will not become defined.
622 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
623 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
624 Although it may not be explicit in the frag, pretend fr_var starts with a
628 md_estimate_size_before_relax (fragP, segment)
632 int old_fr_fix = fragP->fr_fix;
633 char *opcode = fragP->fr_opcode;
635 /* The only thing we have to handle here are symbols outside of the
636 current segment. They may be undefined or in a different segment in
637 which case linker scripts may place them anywhere.
638 However, we can't finish the fragment here and emit the reloc as insn
639 alignment requirements may move the insn about. */
641 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
643 /* The symbol is undefined in this segment.
644 Change the relaxation subtype to the max allowable and leave
645 all further handling to md_convert_frag. */
646 fragP->fr_subtype = 2;
648 #if 0 /* Can't use this, but leave in for illustration. */
649 /* Change 16 bit insn to 32 bit insn. */
652 /* Increase known (fixed) size of fragment. */
655 /* Create a relocation for it. */
656 fix_new (fragP, old_fr_fix, 4,
658 fragP->fr_offset, 1 /* pcrel */,
659 /* FIXME: Can't use a real BFD reloc here.
660 cgen_md_apply_fix3 can't handle it. */
661 BFD_RELOC_M32R_26_PCREL);
663 /* Mark this fragment as finished. */
667 const struct cgen_insn *insn;
670 /* Update the recorded insn.
671 Fortunately we don't have to look very far.
672 FIXME: Change this to record in the instruction the next higher
673 relaxable insn to use. */
674 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
676 if ((strcmp (CGEN_INSN_SYNTAX (insn)->mnemonic,
677 CGEN_INSN_SYNTAX (fragP->fr_cgen.insn)->mnemonic)
679 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
684 fragP->fr_cgen.insn = insn;
690 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
693 /* *fragP has been relaxed to its final size, and now needs to have
694 the bytes inside it modified to conform to the new size.
696 Called after relaxation is finished.
697 fragP->fr_type == rs_machine_dependent.
698 fragP->fr_subtype is the subtype of what the address relaxed to. */
701 md_convert_frag (abfd, sec, fragP)
706 char *opcode, *displacement;
707 int target_address, opcode_address, extension, addend;
709 opcode = fragP->fr_opcode;
711 /* Address opcode resides at in file space. */
712 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
714 switch (fragP->fr_subtype)
718 displacement = &opcode[1];
723 displacement = &opcode[1];
726 opcode[2] = opcode[0] | 0x80;
727 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
730 displacement = &opcode[3];
736 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
738 /* symbol must be resolved by linker */
739 if (fragP->fr_offset & 3)
740 as_warn ("Addend to unresolved symbol not on word boundary.");
741 addend = fragP->fr_offset >> 2;
745 /* Address we want to reach in file space. */
746 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
747 target_address += fragP->fr_symbol->sy_frag->fr_address;
748 addend = (target_address - (opcode_address & -4)) >> 2;
751 /* Create a relocation for symbols that must be resolved by the linker.
752 Otherwise output the completed insn. */
754 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
756 assert (fragP->fr_subtype != 1);
757 assert (fragP->fr_cgen.insn != 0);
758 cgen_record_fixup (fragP,
759 /* Offset of branch insn in frag. */
760 fragP->fr_fix + extension - 4,
763 /* FIXME: quick hack */
765 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
767 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
769 fragP->fr_cgen.opinfo,
770 fragP->fr_symbol, fragP->fr_offset);
773 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
775 md_number_to_chars (displacement, (valueT) addend,
776 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
778 fragP->fr_fix += extension;
781 /* Functions concerning relocs. */
783 /* The location from which a PC relative jump should be calculated,
784 given a PC relative reloc. */
787 md_pcrel_from_section (fixP, sec)
791 if (fixP->fx_addsy != (symbolS *) NULL
792 && (! S_IS_DEFINED (fixP->fx_addsy)
793 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
795 /* The symbol is undefined (or is defined but not in this section).
796 Let the linker figure it out. */
800 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
803 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
804 Returns BFD_RELOC_NONE if no reloc type can be found.
805 *FIXP may be modified if desired. */
807 bfd_reloc_code_real_type
808 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
809 const struct cgen_insn *insn;
810 const struct cgen_operand *operand;
813 switch (CGEN_OPERAND_TYPE (operand))
815 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
816 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
817 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
818 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
819 case M32R_OPERAND_HI16 :
820 case M32R_OPERAND_SLO16 :
821 case M32R_OPERAND_ULO16 :
822 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
823 if (fixP->tc_fix_data.opinfo != 0)
824 return fixP->tc_fix_data.opinfo;
827 return BFD_RELOC_NONE;
830 /* Called while parsing an instruction to create a fixup.
831 We need to check for HI16 relocs and queue them up for later sorting. */
834 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
837 const struct cgen_insn *insn;
839 const struct cgen_operand *operand;
843 fixS *fixP = cgen_record_fixup_exp (frag, where, insn, length,
844 operand, opinfo, exp);
846 switch (CGEN_OPERAND_TYPE (operand))
848 case M32R_OPERAND_HI16 :
849 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
850 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
851 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
852 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
859 /* Record a HI16 reloc for later matching with its LO16 cousin. */
862 m32r_record_hi16 (reloc_type, fixP, seg)
867 struct m32r_hi_fixup *hi_fixup;
869 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
870 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
872 hi_fixup = ((struct m32r_hi_fixup *)
873 xmalloc (sizeof (struct m32r_hi_fixup)));
874 hi_fixup->fixp = fixP;
875 hi_fixup->seg = now_seg;
876 hi_fixup->next = m32r_hi_fixup_list;
877 m32r_hi_fixup_list = hi_fixup;
880 /* Return BFD reloc type from opinfo field in a fixS.
881 It's tricky using fx_r_type in m32r_frob_file because the values
882 are BFD_RELOC_UNUSED + operand number. */
883 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
885 /* Sort any unmatched HI16 relocs so that they immediately precede
886 the corresponding LO16 reloc. This is called before md_apply_fix and
892 struct m32r_hi_fixup *l;
894 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
896 segment_info_type *seginfo;
899 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
900 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
902 /* Check quickly whether the next fixup happens to be a matching low. */
903 if (l->fixp->fx_next != NULL
904 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
905 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
906 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
909 /* Look through the fixups for this segment for a matching `low'.
910 When we find one, move the high/shigh just in front of it. We do
911 this in two passes. In the first pass, we try to find a
912 unique `low'. In the second pass, we permit multiple high's
913 relocs for a single `low'. */
914 seginfo = seg_info (l->seg);
915 for (pass = 0; pass < 2; pass++)
920 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
922 /* Check whether this is a `low' fixup which matches l->fixp. */
923 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
924 && f->fx_addsy == l->fixp->fx_addsy
925 && f->fx_offset == l->fixp->fx_offset
928 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
929 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
930 || prev->fx_addsy != f->fx_addsy
931 || prev->fx_offset != f->fx_offset))
935 /* Move l->fixp before f. */
936 for (pf = &seginfo->fix_root;
938 pf = &(*pf)->fx_next)
939 assert (*pf != NULL);
941 *pf = l->fixp->fx_next;
943 l->fixp->fx_next = f;
945 seginfo->fix_root = l->fixp;
947 prev->fx_next = l->fixp;
959 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
960 "Unmatched high/shigh reloc");
965 /* See whether we need to force a relocation into the output file.
966 This is used to force out switch and PC relative relocations when
970 m32r_force_relocation (fix)
976 return (fix->fx_pcrel
980 /* Write a value out to the object file, using the appropriate endianness. */
983 md_number_to_chars (buf, val, n)
988 if (target_big_endian)
989 number_to_chars_bigendian (buf, val, n);
991 number_to_chars_littleendian (buf, val, n);
994 /* Turn a string in input_line_pointer into a floating point constant of type
995 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
996 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
999 /* Equal to MAX_PRECISION in atof-ieee.c */
1000 #define MAX_LITTLENUMS 6
1003 md_atof (type, litP, sizeP)
1009 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1010 LITTLENUM_TYPE *wordP;
1030 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1034 return "Bad call to md_atof()";
1037 t = atof_ieee (input_line_pointer, type, words);
1039 input_line_pointer = t;
1040 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1042 if (target_big_endian)
1044 for (i = 0; i < prec; i++)
1046 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1047 litP += sizeof (LITTLENUM_TYPE);
1052 for (i = prec - 1; i >= 0; i--)
1054 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1055 litP += sizeof (LITTLENUM_TYPE);