1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
28 /* Structure to hold all of the different components describing an individual instruction. */
31 const CGEN_INSN * insn;
32 const CGEN_INSN * orig_insn;
35 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
37 char buffer [CGEN_MAX_INSN_SIZE];
41 int indices [MAX_OPERAND_INSTANCES];
45 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
46 boundary (i.e. was the first of two 16 bit insns). */
47 static m32r_insn prev_insn;
49 /* Non-zero if we've seen a relaxable insn since the last 32 bit
51 static int seen_relaxable_p = 0;
53 /* Non-zero if -relax specified, in which case sufficient relocs are output
54 for the linker to do relaxing.
55 We do simple forms of relaxing internally, but they are always done.
56 This flag does not apply to them. */
57 static int m32r_relax;
59 /* If non-NULL, pointer to cpu description file to read.
60 This allows runtime additions to the assembler. */
61 static char * m32r_cpu_desc;
63 /* start-sanitize-m32rx */
64 /* Non-zero if -m32rx has been specified, in which case support for the
65 extended M32RX instruction set should be enabled. */
66 static int enable_m32rx = 0;
68 /* Non-zero if the programmer should be warned when an explicit parallel
69 instruction might have constraint violations. */
70 static int warn_explicit_parallel_conflicts = 1;
71 /* end-sanitize-m32rx */
73 /* stuff for .scomm symbols. */
74 static segT sbss_section;
75 static asection scom_section;
76 static asymbol scom_symbol;
78 const char comment_chars[] = ";";
79 const char line_comment_chars[] = "#";
80 const char line_separator_chars[] = "";
81 const char EXP_CHARS[] = "eE";
82 const char FLT_CHARS[] = "dD";
84 /* Relocations against symbols are done in two
85 parts, with a HI relocation and a LO relocation. Each relocation
86 has only 16 bits of space to store an addend. This means that in
87 order for the linker to handle carries correctly, it must be able
88 to locate both the HI and the LO relocation. This means that the
89 relocations must appear in order in the relocation table.
91 In order to implement this, we keep track of each unmatched HI
92 relocation. We then sort them so that they immediately precede the
93 corresponding LO relocation. */
97 struct m32r_hi_fixup * next; /* Next HI fixup. */
98 fixS * fixp; /* This fixup. */
99 segT seg; /* The section this fixup is in. */
103 /* The list of unmatched HI relocs. */
105 static struct m32r_hi_fixup * m32r_hi_fixup_list;
108 /* start-sanitize-m32rx */
115 if (stdoutput != NULL)
116 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
117 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
119 /* end-sanitize-m32rx */
121 const char * md_shortopts = "";
123 struct option md_longopts[] =
125 /* start-sanitize-m32rx */
126 #define OPTION_M32RX (OPTION_MD_BASE)
127 {"m32rx", no_argument, NULL, OPTION_M32RX},
128 #define OPTION_WARN (OPTION_MD_BASE + 1)
129 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN},
130 {"Wp", no_argument, NULL, OPTION_WARN},
131 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
132 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
133 {"Wnp", no_argument, NULL, OPTION_NO_WARN},
134 /* end-sanitize-m32rx */
136 #if 0 /* not supported yet */
137 #define OPTION_RELAX (OPTION_MD_BASE + 3)
138 {"relax", no_argument, NULL, OPTION_RELAX},
139 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
140 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
143 {NULL, no_argument, NULL, 0}
145 size_t md_longopts_size = sizeof (md_longopts);
148 md_parse_option (c, arg)
154 /* start-sanitize-m32rx */
160 warn_explicit_parallel_conflicts = 1;
164 warn_explicit_parallel_conflicts = 0;
166 /* end-sanitize-m32rx */
168 #if 0 /* not supported yet */
172 case OPTION_CPU_DESC:
183 md_show_usage (stream)
186 fprintf (stream, "M32R/X options:\n");
187 /* start-sanitize-m32rx */
189 --m32rx support the extended m32rx instruction set\n");
192 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n");
194 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
196 --Wp Synonym for --warn-explicit-parallel-conflicts\n");
198 --Wnp Synonym for --no-warn-explicit-parallel-conflicts\n");
199 /* end-sanitize-m32rx */
203 --relax create linker relaxable code\n");
205 --cpu-desc provide runtime cpu description file\n");
209 static void fill_insn PARAMS ((int));
210 static void m32r_scomm PARAMS ((int));
212 /* Set by md_assemble for use by m32r_fill_insn. */
213 static subsegT prev_subseg;
214 static segT prev_seg;
216 /* The target specific pseudo-ops which we support. */
217 const pseudo_typeS md_pseudo_table[] =
220 { "fillinsn", fill_insn, 0 },
221 { "scomm", m32r_scomm, 0 },
222 /* start-sanitize-m32rx */
223 { "m32r", allow_m32rx, 0},
224 { "m32rx", allow_m32rx, 1},
225 /* end-sanitize-m32rx */
229 /* FIXME: Should be machine generated. */
230 #define NOP_INSN 0x7000
231 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
233 /* When we align the .text section, insert the correct NOP pattern.
234 N is the power of 2 alignment. LEN is the length of pattern FILL.
235 MAX is the maximum number of characters to skip when doing the alignment,
236 or 0 if there is no maximum. */
239 m32r_do_align (n, fill, len, max)
245 if ((fill == NULL || (* fill == 0 && len == 1))
246 && (now_seg->flags & SEC_CODE) != 0
247 /* Only do this special handling if aligning to at least a
250 /* Only do this special handling if we're allowed to emit at
252 && (max == 0 || max > 1))
254 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
257 /* First align to a 2 byte boundary, in case there is an odd .byte. */
258 /* FIXME: How much memory will cause gas to use when assembling a big
259 program? Perhaps we can avoid the frag_align call? */
260 frag_align (1, 0, 0);
262 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
264 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
265 /* If doing larger alignments use a repeating sequence of appropriate
269 static const unsigned char multi_nop_pattern[] =
270 { 0x70, 0x00, 0xf0, 0x00 };
271 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
281 assemble_nop (opcode)
284 char * f = frag_more (2);
285 md_number_to_chars (f, opcode, 2);
288 /* If the last instruction was the first of 2 16 bit insns,
289 output a nop to move the PC to a 32 bit boundary.
291 This is done via an alignment specification since branch relaxing
292 may make it unnecessary.
294 Internally, we need to output one of these each time a 32 bit insn is
295 seen after an insn that is relaxable. */
301 (void) m32r_do_align (2, NULL, 0, 0);
302 prev_insn.insn = NULL;
303 seen_relaxable_p = 0;
306 /* Cover function to fill_insn called after a label and at end of assembly.
308 The result is always 1: we're called in a conditional to see if the
309 current line is a label. */
312 m32r_fill_insn (done)
318 if (prev_seg != NULL)
323 subseg_set (prev_seg, prev_subseg);
327 subseg_set (seg, subseg);
340 /* Initialize the `cgen' interface. */
342 /* This is a callback from cgen to gas to parse operands. */
343 cgen_parse_operand_fn = cgen_parse_operand;
345 /* Set the machine number and endian. */
346 CGEN_SYM (init_asm) (0 /* mach number */,
348 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
350 #if 0 /* not supported yet */
351 /* If a runtime cpu description file was provided, parse it. */
352 if (m32r_cpu_desc != NULL)
356 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
358 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
362 /* Save the current subseg so we can restore it [it's the default one and
363 we don't want the initial section to be .sbss]. */
367 /* The sbss section is for local .scomm symbols. */
368 sbss_section = subseg_new (".sbss", 0);
370 /* This is copied from perform_an_assembly_pass. */
371 applicable = bfd_applicable_section_flags (stdoutput);
372 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
374 #if 0 /* What does this do? [see perform_an_assembly_pass] */
375 seg_info (bss_section)->bss = 1;
378 subseg_set (seg, subseg);
380 /* We must construct a fake section similar to bfd_com_section
381 but with the name .scommon. */
382 scom_section = bfd_com_section;
383 scom_section.name = ".scommon";
384 scom_section.output_section = & scom_section;
385 scom_section.symbol = & scom_symbol;
386 scom_section.symbol_ptr_ptr = & scom_section.symbol;
387 scom_symbol = * bfd_com_section.symbol;
388 scom_symbol.name = ".scommon";
389 scom_symbol.section = & scom_section;
391 /* start-sanitize-m32rx */
392 allow_m32rx (enable_m32rx);
393 /* end-sanitize-m32rx */
396 /* start-sanitize-m32rx */
398 #define OPERAND_IS_COND_BIT(operand, indices, index) \
399 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
400 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
401 && (indices [index] == 0 || indices [index] == 1)))
403 /* Returns true if an output of instruction 'a' is referenced by an operand
404 of instruction 'b'. If 'check_outputs' is true then b's outputs are
405 checked, otherwise its inputs are examined. */
407 first_writes_to_seconds_operands (a, b, check_outputs)
410 const int check_outputs;
412 const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn);
413 const CGEN_OPERAND_INSTANCE * b_operands = CGEN_INSN_OPERANDS (b->insn);
416 /* If at least one of the instructions takes no operands, then there is
417 nothing to check. There really are instructions without operands,
419 if (a_operands == NULL || b_operands == NULL)
422 /* Scan the operand list of 'a' looking for an output operand. */
424 CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
425 a_index ++, a_operands ++)
427 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT)
432 The Condition bit 'C' is a shadow of the CBR register (control
433 register 1) and also a shadow of bit 31 of the program status
434 word (control register 0). For now this is handled here, rather
437 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
439 /* Scan operand list of 'b' looking for another reference to the
440 condition bit, which goes in the right direction. */
442 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
443 b_index ++, b_operands ++)
445 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
446 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
447 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
453 /* Scan operand list of 'b' looking for an operand that references
454 the same hardware element, and which goes in the right direction. */
456 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
457 b_index ++, b_operands ++)
459 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
460 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
461 && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands))
462 && (a->indices [a_index] == b->indices [b_index]))
472 /* Returns true if the insn can (potentially) alter the program counter. */
477 #if 0 /* Once PC operands are working.... */
478 const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn);
480 if (a_operands == NULL)
483 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END)
485 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL
486 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
492 if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
493 || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
499 /* Returns NULL if the two 16 bit insns can be executed in parallel,
500 otherwise it returns a pointer to an error message explaining why not. */
502 can_make_parallel (a, b)
509 /* Make sure the instructions are the right length. */
510 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
511 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
514 if (first_writes_to_seconds_operands (a, b, true))
515 return "Instructions write to the same destination register.";
517 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
518 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
520 /* Make sure that the instructions use the correct execution pipelines. */
521 if ( a_pipe == PIPE_NONE
522 || b_pipe == PIPE_NONE)
523 return "Instructions do not use parallel execution pipelines.";
525 /* Leave this test for last, since it is the only test that can
526 go away if the instructions are swapped, and we want to make
527 sure that any other errors are detected before this happens. */
528 if ( a_pipe == PIPE_S
530 return "Instructions share the same execution pipeline";
537 make_parallel (buffer)
538 cgen_insn_t * buffer;
540 /* Force the top bit of the second insn to be set. */
544 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
546 value = bfd_getb16 ((bfd_byte *) buffer);
548 bfd_putb16 (value, (char *) buffer);
552 value = bfd_getl16 ((bfd_byte *) buffer);
554 bfd_putl16 (value, (char *) buffer);
559 make_parallel (buffer)
562 /* Force the top bit of the second insn to be set. */
564 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
570 assemble_parallel_insn (str, str2)
579 * str2 = 0; /* Seperate the two instructions. */
581 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
582 so that the parallel instruction will start on a 32 bit boundary. */
586 /* Parse the first instruction. */
587 if (! (first.insn = CGEN_SYM (assemble_insn)
588 (str, & first.fields, first.buffer, & errmsg)))
594 /* Check to see if this is an allowable parallel insn. */
595 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
597 as_bad ("instruction '%s' cannot be executed in parallel.", str);
602 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
604 as_bad ("instruction '%s' is for the M32RX only", str);
609 If the instruciton is relaxable, reparse it looking for a non-relaxable variant.
610 (We do not want to relax instructions inside a parallel construction, and if it
611 turns out that the branch is too far for the displacement field available to the
612 non-relaxed instruction, then this is the programmer's fault.
613 A better solution would be to pass attribute requirements to assemble_insn() so
614 that the relaxable variant would not be accepted as a valid parse of the instruction. */
616 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_RELAXABLE) != 0)
620 /* Oh dear - the insn is relaxable, so it might be replaced with a longer,
621 non-parallel version. Try appending ".s" to the instruction and reparsing it. */
623 p = strchr (str, ' ');
627 sprintf (buf, "%s.s %s", str, p + 1);
630 /* Reset fixup list to empty. */
633 first.insn = CGEN_SYM (assemble_insn) (buf, & first.fields, first.buffer, & errmsg);
635 if (first.insn == NULL)
639 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
640 str3 = str; /* Save the original string pointer. */
641 str = str2 + 2; /* Advanced past the parsed string. */
642 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
644 /* Preserve any fixups that have been generated and reset the list to empty. */
647 /* Get the indicies of the operands of the instruction. */
648 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
649 doesn't seem right. Perhaps allow passing fields like we do insn. */
650 /* FIXME: ALIAS insns do not have operands, so we use this function
651 to find the equivalent insn and overwrite the value stored in our
652 structure. We still need the original insn, however, since this
653 may have certain attributes that are not present in the unaliased
654 version (eg relaxability). When aliases behave differently this
655 may have to change. */
656 first.orig_insn = first.insn;
657 first.insn = m32r_cgen_get_insn_operands (first.insn, bfd_getb16 ((char *) first.buffer), 16,
659 if (first.insn == NULL)
660 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn");
662 /* Parse the second instruction. */
663 if (! (second.insn = CGEN_SYM (assemble_insn)
664 (str, & second.fields, second.buffer, & errmsg)))
672 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
674 as_bad ("instruction '%s' is for the M32RX only", str);
680 if ( strcmp (first.insn->name, "nop") != 0
681 && strcmp (second.insn->name, "nop") != 0)
683 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
688 /* See comment above. */
689 if (CGEN_INSN_ATTR (second.insn, CGEN_INSN_RELAXABLE) != 0)
693 /* Oh dear - the insn is relaxable, so it might be replaced with a longer,
694 non-parallel version. Try appending ".s" to the instruction and reparsing it. */
696 p = strchr (str, ' ');
700 sprintf (buf, "%s.s %s", str, p + 1);
703 /* Reset fixup list to empty, preserving saved fixups. */
704 cgen_restore_fixups();
707 second.insn = CGEN_SYM (assemble_insn) (buf, & second.fields, second.buffer, & errmsg);
709 if (second.insn == NULL)
713 /* Get the indicies of the operands of the instruction. */
714 second.orig_insn = second.insn;
715 second.insn = m32r_cgen_get_insn_operands (second.insn, bfd_getb16 ((char *) second.buffer), 16,
717 if (second.insn == NULL)
718 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn");
720 /* We assume that if the first instruction writes to a register that is
721 read by the second instruction it is because the programmer intended
722 this to happen, (after all they have explicitly requested that these
723 two instructions be executed in parallel). Although if the global
724 variable warn_explicit_parallel_conflicts is true then we do generate
725 a warning message. Similarly we assume that parallel branch and jump
726 instructions are deliberate and should not produce errors. */
728 if (warn_explicit_parallel_conflicts)
730 if (first_writes_to_seconds_operands (& first, & second, false))
731 as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2);
733 if (first_writes_to_seconds_operands (& second, & first, false))
734 as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2);
737 if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
739 /* Get the fixups for the first instruction. */
743 (void) cgen_asm_finish_insn (first.orig_insn, first.buffer,
744 CGEN_FIELDS_BITSIZE (& first.fields));
746 /* Force the top bit of the second insn to be set. */
747 make_parallel (second.buffer);
749 /* Get its fixups. */
750 cgen_restore_fixups ();
753 (void) cgen_asm_finish_insn (second.orig_insn, second.buffer,
754 CGEN_FIELDS_BITSIZE (& second.fields));
756 /* Try swapping the instructions to see if they work that way. */
757 else if (can_make_parallel (& second, & first) == NULL)
759 /* Write out the second instruction first. */
760 (void) cgen_asm_finish_insn (second.orig_insn, second.buffer,
761 CGEN_FIELDS_BITSIZE (& second.fields));
763 /* Force the top bit of the first instruction to be set. */
764 make_parallel (first.buffer);
766 /* Get the fixups for the first instruction. */
767 cgen_restore_fixups ();
769 /* Write out the first instruction. */
770 (void) cgen_asm_finish_insn (first.orig_insn, first.buffer,
771 CGEN_FIELDS_BITSIZE (& first.fields));
775 as_bad ("'%s': %s", str2, errmsg);
779 /* Set these so m32r_fill_insn can use them. */
781 prev_subseg = now_subseg;
786 /* end-sanitize-m32rx */
797 /* Initialize GAS's cgen interface for a new instruction. */
798 cgen_asm_init_parse ();
800 /* start-sanitize-m32rx */
801 /* Look for a parallel instruction seperator. */
802 if ((str2 = strstr (str, "||")) != NULL)
804 assemble_parallel_insn (str, str2);
807 /* end-sanitize-m32rx */
809 insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
816 /* start-sanitize-m32rx */
817 if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
819 as_bad ("instruction '%s' is for the M32RX only", str);
822 /* end-sanitize-m32rx */
824 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
826 /* 32 bit insns must live on 32 bit boundaries. */
827 if (prev_insn.insn || seen_relaxable_p)
829 /* ??? If calling fill_insn too many times turns us into a memory
830 pig, can we call assemble_nop instead of !seen_relaxable_p? */
834 (void) cgen_asm_finish_insn (insn.insn, insn.buffer,
835 CGEN_FIELDS_BITSIZE (& insn.fields));
839 /* start-sanitize-m32rx */
840 /* start-sanitize-phase2-m32rx */
842 /* end-sanitize-phase2-m32rx */
843 /* end-sanitize-m32rx */
845 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
848 /* Get the indices of the operands of the instruction. */
849 insn.insn = m32r_cgen_get_insn_operands (insn.insn,
850 bfd_getb16 ((char *) insn.buffer),
853 if (insn.insn == NULL)
854 as_fatal ("internal error: m32r_cgen_get_insn_operands failed");
856 /* Keep track of whether we've seen a pair of 16 bit insns.
857 prev_insn.insn is NULL when we're on a 32 bit boundary. */
860 /* start-sanitize-m32rx */
861 /* start-sanitize-phase2-m32rx */
862 /* Look to see if this instruction can be combined with the
863 previous instruction to make one, parallel, 32 bit instruction.
864 If the previous instruction (potentially) changed the flow of
865 program control, then it cannot be combined with the current
866 instruction. If the current instruction is relaxable, then it
867 might be replaced with a longer version, so we cannot combine it.
868 Also if the output of the previous instruction is used as an
869 input to the current instruction then it cannot be combined.
870 Otherwise call can_make_parallel() with both orderings of the
871 instructions to see if they can be combined. */
873 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) == 0
874 && ! writes_to_pc (& prev_insn)
875 && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
878 if (can_make_parallel (& prev_insn, & insn) == NULL)
879 make_parallel (insn.buffer);
880 else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
883 /* end-sanitize-phase2-m32rx */
884 /* end-sanitize-m32rx */
886 prev_insn.insn = NULL;
893 /* Record the frag that might be used by this insn. */
894 insn.frag = frag_now;
895 insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer,
896 CGEN_FIELDS_BITSIZE (& insn.fields));
898 /* start-sanitize-m32rx */
899 /* start-sanitize-phase2-m32rx */
904 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
906 /* Swap the two insns */
907 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
908 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
910 make_parallel (insn.addr);
912 /* Swap any relaxable frags recorded for the two insns. */
913 if (prev_insn.frag->fr_opcode == prev_insn.addr)
914 prev_insn.frag->fr_opcode = insn.addr;
915 else if (insn.frag->fr_opcode == insn.addr)
916 insn.frag->fr_opcode = prev_insn.addr;
918 /* end-sanitize-phase2-m32rx */
920 /* Record where this instruction was assembled. */
921 prev_insn.addr = insn.addr;
922 prev_insn.frag = insn.frag;
923 /* end-sanitize-m32rx */
925 /* If the insn needs the following one to be on a 32 bit boundary
926 (e.g. subroutine calls), fill this insn's slot. */
927 if (prev_insn.insn != NULL
928 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0)
931 /* If this is a relaxable insn (can be replaced with a larger version)
932 mark the fact so that we can emit an alignment directive for a
933 following 32 bit insn if we see one. */
934 if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0)
935 seen_relaxable_p = 1;
938 /* Set these so m32r_fill_insn can use them. */
940 prev_subseg = now_subseg;
943 /* The syntax in the manual says constants begin with '#'.
944 We just ignore it. */
947 md_operand (expressionP)
948 expressionS * expressionP;
950 if (* input_line_pointer == '#')
952 input_line_pointer ++;
953 expression (expressionP);
958 md_section_align (segment, size)
962 int align = bfd_get_section_alignment (stdoutput, segment);
963 return ((size + (1 << align) - 1) & (-1 << align));
967 md_undefined_symbol (name)
973 /* .scomm pseudo-op handler.
975 This is a new pseudo-op to handle putting objects in .scommon.
976 By doing this the linker won't need to do any work and more importantly
977 it removes the implicit -G arg necessary to correctly link the object file.
984 register char * name;
988 register symbolS * symbolP;
992 name = input_line_pointer;
993 c = get_symbol_end ();
995 /* just after name is now '\0' */
996 p = input_line_pointer;
999 if (* input_line_pointer != ',')
1001 as_bad ("Expected comma after symbol-name: rest of line ignored.");
1002 ignore_rest_of_line ();
1006 input_line_pointer ++; /* skip ',' */
1007 if ((size = get_absolute_expression ()) < 0)
1009 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
1010 ignore_rest_of_line ();
1014 /* The third argument to .scomm is the alignment. */
1015 if (* input_line_pointer != ',')
1019 ++ input_line_pointer;
1020 align = get_absolute_expression ();
1023 as_warn ("ignoring bad alignment");
1027 /* Convert to a power of 2 alignment. */
1030 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
1034 as_bad ("Common alignment not a power of 2");
1035 ignore_rest_of_line ();
1043 symbolP = symbol_find_or_make (name);
1046 if (S_IS_DEFINED (symbolP))
1048 as_bad ("Ignoring attempt to re-define symbol `%s'.",
1049 S_GET_NAME (symbolP));
1050 ignore_rest_of_line ();
1054 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
1056 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
1057 S_GET_NAME (symbolP),
1058 (long) S_GET_VALUE (symbolP),
1061 ignore_rest_of_line ();
1067 segT old_sec = now_seg;
1068 int old_subsec = now_subseg;
1071 record_alignment (sbss_section, align2);
1072 subseg_set (sbss_section, 0);
1075 frag_align (align2, 0, 0);
1077 if (S_GET_SEGMENT (symbolP) == sbss_section)
1078 symbolP->sy_frag->fr_symbol = 0;
1080 symbolP->sy_frag = frag_now;
1082 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
1085 S_SET_SIZE (symbolP, size);
1086 S_SET_SEGMENT (symbolP, sbss_section);
1087 S_CLEAR_EXTERNAL (symbolP);
1088 subseg_set (old_sec, old_subsec);
1092 S_SET_VALUE (symbolP, (valueT) size);
1093 S_SET_ALIGN (symbolP, align2);
1094 S_SET_EXTERNAL (symbolP);
1095 S_SET_SEGMENT (symbolP, & scom_section);
1098 demand_empty_rest_of_line ();
1101 /* Interface to relax_segment. */
1103 /* FIXME: Build table by hand, get it working, then machine generate. */
1105 const relax_typeS md_relax_table[] =
1108 1) most positive reach of this state,
1109 2) most negative reach of this state,
1110 3) how many bytes this mode will add to the size of the current frag
1111 4) which index into the table to try if we can't fit into this one. */
1113 /* The first entry must be unused because an `rlx_more' value of zero ends
1117 /* The displacement used by GAS is from the end of the 2 byte insn,
1118 so we subtract 2 from the following. */
1119 /* 16 bit insn, 8 bit disp -> 10 bit range.
1120 This doesn't handle a branch in the right slot at the border:
1121 the "& -4" isn't taken into account. It's not important enough to
1122 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1124 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1125 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1126 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1127 /* Same thing, but with leading nop for alignment. */
1128 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1132 m32r_relax_frag (fragP, stretch)
1136 /* Address of branch insn. */
1137 long address = fragP->fr_address + fragP->fr_fix - 2;
1140 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1141 if (fragP->fr_subtype == 2)
1143 if ((address & 3) != 0)
1145 fragP->fr_subtype = 3;
1149 else if (fragP->fr_subtype == 3)
1151 if ((address & 3) == 0)
1153 fragP->fr_subtype = 2;
1159 growth = relax_frag (fragP, stretch);
1161 /* Long jump on odd halfword boundary? */
1162 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1164 fragP->fr_subtype = 3;
1172 /* Return an initial guess of the length by which a fragment must grow to
1173 hold a branch to reach its destination.
1174 Also updates fr_type/fr_subtype as necessary.
1176 Called just before doing relaxation.
1177 Any symbol that is now undefined will not become defined.
1178 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1179 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1180 Although it may not be explicit in the frag, pretend fr_var starts with a
1184 md_estimate_size_before_relax (fragP, segment)
1188 int old_fr_fix = fragP->fr_fix;
1189 char * opcode = fragP->fr_opcode;
1191 /* The only thing we have to handle here are symbols outside of the
1192 current segment. They may be undefined or in a different segment in
1193 which case linker scripts may place them anywhere.
1194 However, we can't finish the fragment here and emit the reloc as insn
1195 alignment requirements may move the insn about. */
1197 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1199 /* The symbol is undefined in this segment.
1200 Change the relaxation subtype to the max allowable and leave
1201 all further handling to md_convert_frag. */
1202 fragP->fr_subtype = 2;
1204 #if 0 /* Can't use this, but leave in for illustration. */
1205 /* Change 16 bit insn to 32 bit insn. */
1208 /* Increase known (fixed) size of fragment. */
1211 /* Create a relocation for it. */
1212 fix_new (fragP, old_fr_fix, 4,
1214 fragP->fr_offset, 1 /* pcrel */,
1215 /* FIXME: Can't use a real BFD reloc here.
1216 cgen_md_apply_fix3 can't handle it. */
1217 BFD_RELOC_M32R_26_PCREL);
1219 /* Mark this fragment as finished. */
1223 const CGEN_INSN * insn;
1226 /* Update the recorded insn.
1227 Fortunately we don't have to look very far.
1228 FIXME: Change this to record in the instruction the next higher
1229 relaxable insn to use. */
1230 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1232 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1233 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1235 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1241 fragP->fr_cgen.insn = insn;
1247 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1250 /* *fragP has been relaxed to its final size, and now needs to have
1251 the bytes inside it modified to conform to the new size.
1253 Called after relaxation is finished.
1254 fragP->fr_type == rs_machine_dependent.
1255 fragP->fr_subtype is the subtype of what the address relaxed to. */
1258 md_convert_frag (abfd, sec, fragP)
1264 char * displacement;
1270 opcode = fragP->fr_opcode;
1272 /* Address opcode resides at in file space. */
1273 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1275 switch (fragP->fr_subtype)
1279 displacement = & opcode[1];
1284 displacement = & opcode[1];
1287 opcode[2] = opcode[0] | 0x80;
1288 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1289 opcode_address += 2;
1291 displacement = & opcode[3];
1297 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1299 /* symbol must be resolved by linker */
1300 if (fragP->fr_offset & 3)
1301 as_warn ("Addend to unresolved symbol not on word boundary.");
1302 addend = fragP->fr_offset >> 2;
1306 /* Address we want to reach in file space. */
1307 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1308 target_address += fragP->fr_symbol->sy_frag->fr_address;
1309 addend = (target_address - (opcode_address & -4)) >> 2;
1312 /* Create a relocation for symbols that must be resolved by the linker.
1313 Otherwise output the completed insn. */
1315 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1317 assert (fragP->fr_subtype != 1);
1318 assert (fragP->fr_cgen.insn != 0);
1319 cgen_record_fixup (fragP,
1320 /* Offset of branch insn in frag. */
1321 fragP->fr_fix + extension - 4,
1322 fragP->fr_cgen.insn,
1324 /* FIXME: quick hack */
1326 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1328 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1330 fragP->fr_cgen.opinfo,
1331 fragP->fr_symbol, fragP->fr_offset);
1334 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1336 md_number_to_chars (displacement, (valueT) addend,
1337 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1339 fragP->fr_fix += extension;
1342 /* Functions concerning relocs. */
1344 /* The location from which a PC relative jump should be calculated,
1345 given a PC relative reloc. */
1348 md_pcrel_from_section (fixP, sec)
1352 if (fixP->fx_addsy != (symbolS *) NULL
1353 && (! S_IS_DEFINED (fixP->fx_addsy)
1354 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1356 /* The symbol is undefined (or is defined but not in this section).
1357 Let the linker figure it out. */
1361 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1364 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1365 Returns BFD_RELOC_NONE if no reloc type can be found.
1366 *FIXP may be modified if desired. */
1368 bfd_reloc_code_real_type
1369 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1370 const CGEN_INSN * insn;
1371 const CGEN_OPERAND * operand;
1374 switch (CGEN_OPERAND_TYPE (operand))
1376 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1377 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1378 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1379 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1380 case M32R_OPERAND_HI16 :
1381 case M32R_OPERAND_SLO16 :
1382 case M32R_OPERAND_ULO16 :
1383 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1384 if (fixP->tc_fix_data.opinfo != 0)
1385 return fixP->tc_fix_data.opinfo;
1388 return BFD_RELOC_NONE;
1391 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1394 m32r_record_hi16 (reloc_type, fixP, seg)
1399 struct m32r_hi_fixup * hi_fixup;
1401 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1402 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1404 hi_fixup = ((struct m32r_hi_fixup *)
1405 xmalloc (sizeof (struct m32r_hi_fixup)));
1406 hi_fixup->fixp = fixP;
1407 hi_fixup->seg = now_seg;
1408 hi_fixup->next = m32r_hi_fixup_list;
1410 m32r_hi_fixup_list = hi_fixup;
1413 /* Called while parsing an instruction to create a fixup.
1414 We need to check for HI16 relocs and queue them up for later sorting. */
1417 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1420 const CGEN_INSN * insn;
1422 const CGEN_OPERAND * operand;
1426 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1427 operand, opinfo, exp);
1429 switch (CGEN_OPERAND_TYPE (operand))
1431 case M32R_OPERAND_HI16 :
1432 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1433 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1434 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1435 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1442 /* Return BFD reloc type from opinfo field in a fixS.
1443 It's tricky using fx_r_type in m32r_frob_file because the values
1444 are BFD_RELOC_UNUSED + operand number. */
1445 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1447 /* Sort any unmatched HI16 relocs so that they immediately precede
1448 the corresponding LO16 reloc. This is called before md_apply_fix and
1454 struct m32r_hi_fixup * l;
1456 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1458 segment_info_type * seginfo;
1461 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1462 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1464 /* Check quickly whether the next fixup happens to be a matching low. */
1465 if (l->fixp->fx_next != NULL
1466 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1467 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1468 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1471 /* Look through the fixups for this segment for a matching `low'.
1472 When we find one, move the high/shigh just in front of it. We do
1473 this in two passes. In the first pass, we try to find a
1474 unique `low'. In the second pass, we permit multiple high's
1475 relocs for a single `low'. */
1476 seginfo = seg_info (l->seg);
1477 for (pass = 0; pass < 2; pass++)
1483 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1485 /* Check whether this is a `low' fixup which matches l->fixp. */
1486 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1487 && f->fx_addsy == l->fixp->fx_addsy
1488 && f->fx_offset == l->fixp->fx_offset
1491 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1492 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1493 || prev->fx_addsy != f->fx_addsy
1494 || prev->fx_offset != f->fx_offset))
1498 /* Move l->fixp before f. */
1499 for (pf = &seginfo->fix_root;
1501 pf = & (* pf)->fx_next)
1502 assert (* pf != NULL);
1504 * pf = l->fixp->fx_next;
1506 l->fixp->fx_next = f;
1508 seginfo->fix_root = l->fixp;
1510 prev->fx_next = l->fixp;
1522 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1523 "Unmatched high/shigh reloc");
1528 /* See whether we need to force a relocation into the output file.
1529 This is used to force out switch and PC relative relocations when
1533 m32r_force_relocation (fix)
1539 return (fix->fx_pcrel
1543 /* Write a value out to the object file, using the appropriate endianness. */
1546 md_number_to_chars (buf, val, n)
1551 if (target_big_endian)
1552 number_to_chars_bigendian (buf, val, n);
1554 number_to_chars_littleendian (buf, val, n);
1557 /* Turn a string in input_line_pointer into a floating point constant of type
1558 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1559 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1562 /* Equal to MAX_PRECISION in atof-ieee.c */
1563 #define MAX_LITTLENUMS 6
1566 md_atof (type, litP, sizeP)
1573 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1574 LITTLENUM_TYPE * wordP;
1576 char * atof_ieee ();
1594 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1598 return "Bad call to md_atof()";
1601 t = atof_ieee (input_line_pointer, type, words);
1603 input_line_pointer = t;
1604 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1606 if (target_big_endian)
1608 for (i = 0; i < prec; i++)
1610 md_number_to_chars (litP, (valueT) words[i],
1611 sizeof (LITTLENUM_TYPE));
1612 litP += sizeof (LITTLENUM_TYPE);
1617 for (i = prec - 1; i >= 0; i--)
1619 md_number_to_chars (litP, (valueT) words[i],
1620 sizeof (LITTLENUM_TYPE));
1621 litP += sizeof (LITTLENUM_TYPE);