1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 /* Non-null if last insn was a 16 bit insn on a 32 bit boundary
28 (i.e. was the first of two 16 bit insns). */
29 static const CGEN_INSN * prev_insn = NULL;
31 /* Non-zero if we've seen a relaxable insn since the last 32 bit
33 static int seen_relaxable_p = 0;
35 /* Non-zero if -relax specified, in which case sufficient relocs are output
36 for the linker to do relaxing.
37 We do simple forms of relaxing internally, but they are always done.
38 This flag does not apply to them. */
39 static int m32r_relax;
41 /* If non-NULL, pointer to cpu description file to read.
42 This allows runtime additions to the assembler. */
43 static char * m32r_cpu_desc;
45 /* start-sanitize-m32rx */
46 /* Non-zero if -m32rx has been specified, in which case support for the
47 extended M32RX instruction set should be enabled. */
48 static int enable_m32rx = 0;
49 /* end-sanitize-m32rx */
51 /* stuff for .scomm symbols. */
52 static segT sbss_section;
53 static asection scom_section;
54 static asymbol scom_symbol;
56 const char comment_chars[] = ";";
57 const char line_comment_chars[] = "#";
58 const char line_separator_chars[] = "";
59 const char EXP_CHARS[] = "eE";
60 const char FLT_CHARS[] = "dD";
62 /* Relocations against symbols are done in two
63 parts, with a HI relocation and a LO relocation. Each relocation
64 has only 16 bits of space to store an addend. This means that in
65 order for the linker to handle carries correctly, it must be able
66 to locate both the HI and the LO relocation. This means that the
67 relocations must appear in order in the relocation table.
69 In order to implement this, we keep track of each unmatched HI
70 relocation. We then sort them so that they immediately precede the
71 corresponding LO relocation. */
75 struct m32r_hi_fixup * next; /* Next HI fixup. */
76 fixS * fixp; /* This fixup. */
77 segT seg; /* The section this fixup is in. */
81 /* The list of unmatched HI relocs. */
83 static struct m32r_hi_fixup * m32r_hi_fixup_list;
85 static void m32r_record_hi16 PARAMS ((int, fixS *, segT seg));
88 /* start-sanitize-m32rx */
94 if (stdoutput != NULL)
95 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
96 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
98 /* end-sanitize-m32rx */
100 const char * md_shortopts = "";
102 struct option md_longopts[] =
104 /* start-sanitize-m32rx */
105 #define OPTION_M32RX (OPTION_MD_BASE)
106 {"m32rx", no_argument, NULL, OPTION_M32RX},
107 /* end-sanitize-m32rx */
109 #if 0 /* not supported yet */
110 #define OPTION_RELAX (OPTION_MD_BASE + 1)
111 {"relax", no_argument, NULL, OPTION_RELAX},
112 #define OPTION_CPU_DESC (OPTION_MD_BASE + 2)
113 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
116 {NULL, no_argument, NULL, 0}
118 size_t md_longopts_size = sizeof (md_longopts);
121 md_parse_option (c, arg)
127 /* start-sanitize-m32rx */
131 /* end-sanitize-m32rx */
133 #if 0 /* not supported yet */
137 case OPTION_CPU_DESC:
148 md_show_usage (stream)
151 fprintf (stream, "M32R/X options:\n");
152 /* start-sanitize-m32rx */
154 --m32rx support the extended m32rx instruction set\n");
155 /* end-sanitize-m32rx */
159 --relax create linker relaxable code\n");
161 --cpu-desc provide runtime cpu description file\n");
165 static void fill_insn PARAMS ((int));
166 static void m32r_scomm PARAMS ((int));
168 /* Set by md_assemble for use by m32r_fill_insn. */
169 static subsegT prev_subseg;
170 static segT prev_seg;
172 /* The target specific pseudo-ops which we support. */
173 const pseudo_typeS md_pseudo_table[] =
176 { "fillinsn", fill_insn, 0 },
177 { "scomm", m32r_scomm, 0 },
178 /* start-sanitize-m32rx */
179 { "m32r", allow_m32rx, 0},
180 { "m32rx", allow_m32rx, 1},
181 /* end-sanitize-m32rx */
185 /* FIXME: Should be machine generated. */
186 #define NOP_INSN 0x7000
187 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
189 /* When we align the .text section, insert the correct NOP pattern.
190 N is the power of 2 alignment. LEN is the length of pattern FILL.
191 MAX is the maximum number of characters to skip when doing the alignment,
192 or 0 if there is no maximum. */
195 m32r_do_align (n, fill, len, max)
201 if ((fill == NULL || (* fill == 0 && len == 1))
202 && (now_seg->flags & SEC_CODE) != 0
203 /* Only do this special handling if aligning to at least a
206 /* Only do this special handling if we're allowed to emit at
208 && (max == 0 || max > 1))
210 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
213 /* First align to a 2 byte boundary, in case there is an odd .byte. */
214 /* FIXME: How much memory will cause gas to use when assembling a big
215 program? Perhaps we can avoid the frag_align call? */
216 frag_align (1, 0, 0);
218 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
220 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
221 /* If doing larger alignments use a repeating sequence of appropriate
225 static const unsigned char multi_nop_pattern[] =
226 { 0x70, 0x00, 0xf0, 0x00 };
227 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
237 assemble_nop (opcode)
240 char * f = frag_more (2);
241 md_number_to_chars (f, opcode, 2);
244 /* If the last instruction was the first of 2 16 bit insns,
245 output a nop to move the PC to a 32 bit boundary.
247 This is done via an alignment specification since branch relaxing
248 may make it unnecessary.
250 Internally, we need to output one of these each time a 32 bit insn is
251 seen after an insn that is relaxable. */
257 (void) m32r_do_align (2, NULL, 0, 0);
259 seen_relaxable_p = 0;
262 /* Cover function to fill_insn called after a label and at end of assembly.
264 The result is always 1: we're called in a conditional to see if the
265 current line is a label. */
268 m32r_fill_insn (done)
274 if (prev_seg != NULL)
279 subseg_set (prev_seg, prev_subseg);
283 subseg_set (seg, subseg);
296 /* Initialize the `cgen' interface. */
298 /* This is a callback from cgen to gas to parse operands. */
299 cgen_parse_operand_fn = cgen_parse_operand;
301 /* Set the machine number and endian. */
302 CGEN_SYM (init_asm) (0 /* mach number */,
304 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
306 #if 0 /* not supported yet */
307 /* If a runtime cpu description file was provided, parse it. */
308 if (m32r_cpu_desc != NULL)
312 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
314 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
318 /* Save the current subseg so we can restore it [it's the default one and
319 we don't want the initial section to be .sbss]. */
323 /* The sbss section is for local .scomm symbols. */
324 sbss_section = subseg_new (".sbss", 0);
326 /* This is copied from perform_an_assembly_pass. */
327 applicable = bfd_applicable_section_flags (stdoutput);
328 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
330 #if 0 /* What does this do? [see perform_an_assembly_pass] */
331 seg_info (bss_section)->bss = 1;
334 subseg_set (seg, subseg);
336 /* We must construct a fake section similar to bfd_com_section
337 but with the name .scommon. */
338 scom_section = bfd_com_section;
339 scom_section.name = ".scommon";
340 scom_section.output_section = & scom_section;
341 scom_section.symbol = & scom_symbol;
342 scom_section.symbol_ptr_ptr = & scom_section.symbol;
343 scom_symbol = * bfd_com_section.symbol;
344 scom_symbol.name = ".scommon";
345 scom_symbol.section = & scom_section;
347 /* start-sanitize-m32rx */
348 allow_m32rx (enable_m32rx);
349 /* end-sanitize-m32rx */
352 /* Returns non zero if the given instruction writes to a destination register. */
354 writes_to_dest_reg (insn)
355 const CGEN_INSN * insn;
357 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
360 /* Scan the syntax string looking for a destination register. */
361 while ((c = (* syntax ++)) != 0)
362 if (c == 128 + M32R_OPERAND_DR)
368 /* Returns an integer representing the destination register of
369 the given insn, or -1 if the insn has no destination. */
372 const CGEN_INSN * insn;
374 /* XXX to be done. */
383 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
384 cgen_insn_t prev_buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
386 char buffer [CGEN_MAX_INSN_SIZE];
387 char prev_buffer [CGEN_MAX_INSN_SIZE];
390 CGEN_FIELDS prev_fields;
391 const CGEN_INSN * insn;
394 int is_parallel = false;
396 /* Initialize GAS's cgen interface for a new instruction. */
397 cgen_asm_init_parse ();
399 /* Look for a parallel instruction seperator. */
400 if ((str2 = strstr (str, "||")) != NULL)
404 * str2 = 0; /* Seperate the two instructions. */
406 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
407 so that the parallel instruction will start on a 32 bit boundary. */
411 /* Assemble the first instruction. */
412 prev_insn = CGEN_SYM (assemble_insn) (str, & prev_fields, prev_buffer, & errmsg);
419 /* start-sanitize-m32rx */
420 /* Check to see if this is an allowable parallel insn. */
421 if (CGEN_INSN_ATTR (prev_insn, CGEN_INSN_PIPE) == PIPE_NONE)
423 as_bad ("instruction '%s' cannot be executed in parallel.", str);
427 if (! enable_m32rx &&
428 CGEN_INSN_ATTR (prev_insn, CGEN_INSN_MACH) == MACH_M32RX)
430 as_bad ("instruction '%s' is for the M32RX only", str);
433 /* end-sanitize-m32rx */
435 /* fixups = fixups->next; */
437 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
438 str3 = str; /* Save the original string pointer. */
439 str = str2 + 2; /* Advanced past the parsed string. */
440 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
445 insn = CGEN_SYM (assemble_insn) (str, & fields, buffer, & errmsg);
452 /* start-sanitize-m32rx */
454 && CGEN_INSN_ATTR (insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
456 as_bad ("instruction '%s' is for the M32RX only", str);
459 /* end-sanitize-m32rx */
463 /* start-sanitize-m32rx */
466 if (strcmp (prev_insn->name, "nop") != 0
467 && strcmp (insn->name, "nop") != 0)
469 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
473 /* Check to see if this is an allowable parallel insn. */
474 if (CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) == PIPE_NONE)
476 as_bad ("instruction '%s', cannot be executed in parallel.", str);
480 /* Check to see that the two instructions can be placed in parallel. */
481 if ((CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) == CGEN_INSN_ATTR (prev_insn, CGEN_INSN_PIPE))
482 && (CGEN_INSN_ATTR (insn, CGEN_INSN_PIPE) != PIPE_OS))
484 as_bad ("'%s': both instructions use the same execution pipeline", str2);
487 /* end-sanitize-m32rx */
490 /* Check that the instructions do not write to the same destination register. */
491 if (writes_to_dest_reg (insn)
492 && writes_to_dest_reg (prev_insn) /* This test is actually redundant. */
493 && get_dest_reg (insn) == get_dest_reg (prev_insn))
495 as_bad ("'%s': both instructions write to the same destination register", str2);
500 /* Force the top bit of the second insn to be set. */
501 #if 0 /*def CGEN_INT_INSN*/
502 #define MAKE_PARALLEL(insn) ((insn) |= 0x8000)
503 switch (CGEN_FIELDS_BITSIZE (& fields))
508 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
510 value = bfd_getb16 ((bfd_vma) * buffer);
511 MAKE_PARALLEL (value);
512 bfd_putb16 (value, buffer);
516 value = bfd_getl16 ((bfd_vma) * buffer);
517 MAKE_PARALLEL (value);
518 bfd_putl16 (value, buffer);
525 #define MAKE_PARALLEL(insn) ((insn) |= 0x80)
526 MAKE_PARALLEL (buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1]);
529 /* Generate the parallel instructions */
530 cgen_asm_finish_insn (prev_insn, prev_buffer, CGEN_FIELDS_BITSIZE (& prev_fields));
531 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
533 /* If prev_ins is relaxable (and insn is not), then swap them, so that the test
534 after the end of this if-then-else section will work. */
535 if (CGEN_INSN_ATTR (prev_insn, CGEN_INSN_RELAXABLE))
538 /* Clear the prev_insn variable, since it only used if the insn was the first
539 16 bit insn in a 32 bit word. */
542 else if (CGEN_INSN_BITSIZE (insn) == 32)
544 /* 32 bit insns must live on 32 bit boundaries. */
545 if (prev_insn || seen_relaxable_p)
547 /* FIXME: If calling fill_insn too many times turns us into a memory
548 pig, can we call assemble_nop instead of !seen_relaxable_p? */
552 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
556 /* Keep track of whether we've seen a pair of 16 bit insns.
557 PREV_INSN is NULL when we're on a 32 bit boundary. */
563 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
565 /* If the insn needs the following one to be on a 32 bit boundary
566 (e.g. subroutine calls), fill this insn's slot. */
568 && CGEN_INSN_ATTR (insn, CGEN_INSN_FILL_SLOT) != 0)
572 /* If this is a relaxable insn (can be replaced with a larger version)
573 mark the fact so that we can emit an alignment directive for a following
574 32 bit insn if we see one. */
575 if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAXABLE) != 0)
576 seen_relaxable_p = 1;
578 /* Set these so m32r_fill_insn can use them. */
580 prev_subseg = now_subseg;
583 /* The syntax in the manual says constants begin with '#'.
584 We just ignore it. */
587 md_operand (expressionP)
588 expressionS * expressionP;
590 if (* input_line_pointer == '#')
592 input_line_pointer ++;
593 expression (expressionP);
598 md_section_align (segment, size)
602 int align = bfd_get_section_alignment (stdoutput, segment);
603 return ((size + (1 << align) - 1) & (-1 << align));
607 md_undefined_symbol (name)
613 /* .scomm pseudo-op handler.
615 This is a new pseudo-op to handle putting objects in .scommon.
616 By doing this the linker won't need to do any work and more importantly
617 it removes the implicit -G arg necessary to correctly link the object file.
624 register char * name;
628 register symbolS * symbolP;
632 name = input_line_pointer;
633 c = get_symbol_end ();
635 /* just after name is now '\0' */
636 p = input_line_pointer;
639 if (* input_line_pointer != ',')
641 as_bad ("Expected comma after symbol-name: rest of line ignored.");
642 ignore_rest_of_line ();
646 input_line_pointer++; /* skip ',' */
647 if ((size = get_absolute_expression ()) < 0)
649 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
650 ignore_rest_of_line ();
654 /* The third argument to .scomm is the alignment. */
655 if (* input_line_pointer != ',')
659 ++ input_line_pointer;
660 align = get_absolute_expression ();
663 as_warn ("ignoring bad alignment");
667 /* Convert to a power of 2 alignment. */
670 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
674 as_bad ("Common alignment not a power of 2");
675 ignore_rest_of_line ();
683 symbolP = symbol_find_or_make (name);
686 if (S_IS_DEFINED (symbolP))
688 as_bad ("Ignoring attempt to re-define symbol `%s'.",
689 S_GET_NAME (symbolP));
690 ignore_rest_of_line ();
694 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
696 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
697 S_GET_NAME (symbolP),
698 (long) S_GET_VALUE (symbolP),
701 ignore_rest_of_line ();
707 segT old_sec = now_seg;
708 int old_subsec = now_subseg;
711 record_alignment (sbss_section, align2);
712 subseg_set (sbss_section, 0);
714 frag_align (align2, 0, 0);
715 if (S_GET_SEGMENT (symbolP) == sbss_section)
716 symbolP->sy_frag->fr_symbol = 0;
717 symbolP->sy_frag = frag_now;
718 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
721 S_SET_SIZE (symbolP, size);
722 S_SET_SEGMENT (symbolP, sbss_section);
723 S_CLEAR_EXTERNAL (symbolP);
724 subseg_set (old_sec, old_subsec);
728 S_SET_VALUE (symbolP, (valueT) size);
729 S_SET_ALIGN (symbolP, align2);
730 S_SET_EXTERNAL (symbolP);
731 S_SET_SEGMENT (symbolP, &scom_section);
734 demand_empty_rest_of_line ();
737 /* Interface to relax_segment. */
739 /* FIXME: Build table by hand, get it working, then machine generate. */
741 const relax_typeS md_relax_table[] =
744 1) most positive reach of this state,
745 2) most negative reach of this state,
746 3) how many bytes this mode will add to the size of the current frag
747 4) which index into the table to try if we can't fit into this one. */
749 /* The first entry must be unused because an `rlx_more' value of zero ends
753 /* The displacement used by GAS is from the end of the 2 byte insn,
754 so we subtract 2 from the following. */
755 /* 16 bit insn, 8 bit disp -> 10 bit range.
756 This doesn't handle a branch in the right slot at the border:
757 the "& -4" isn't taken into account. It's not important enough to
758 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
760 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
761 /* 32 bit insn, 24 bit disp -> 26 bit range. */
762 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
763 /* Same thing, but with leading nop for alignment. */
764 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
768 m32r_relax_frag (fragP, stretch)
772 /* Address of branch insn. */
773 long address = fragP->fr_address + fragP->fr_fix - 2;
776 /* Keep 32 bit insns aligned on 32 bit boundaries. */
777 if (fragP->fr_subtype == 2)
779 if ((address & 3) != 0)
781 fragP->fr_subtype = 3;
785 else if (fragP->fr_subtype == 3)
787 if ((address & 3) == 0)
789 fragP->fr_subtype = 2;
795 growth = relax_frag (fragP, stretch);
797 /* Long jump on odd halfword boundary? */
798 if (fragP->fr_subtype == 2 && (address & 3) != 0)
800 fragP->fr_subtype = 3;
808 /* Return an initial guess of the length by which a fragment must grow to
809 hold a branch to reach its destination.
810 Also updates fr_type/fr_subtype as necessary.
812 Called just before doing relaxation.
813 Any symbol that is now undefined will not become defined.
814 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
815 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
816 Although it may not be explicit in the frag, pretend fr_var starts with a
820 md_estimate_size_before_relax (fragP, segment)
824 int old_fr_fix = fragP->fr_fix;
825 char * opcode = fragP->fr_opcode;
827 /* The only thing we have to handle here are symbols outside of the
828 current segment. They may be undefined or in a different segment in
829 which case linker scripts may place them anywhere.
830 However, we can't finish the fragment here and emit the reloc as insn
831 alignment requirements may move the insn about. */
833 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
835 /* The symbol is undefined in this segment.
836 Change the relaxation subtype to the max allowable and leave
837 all further handling to md_convert_frag. */
838 fragP->fr_subtype = 2;
840 #if 0 /* Can't use this, but leave in for illustration. */
841 /* Change 16 bit insn to 32 bit insn. */
844 /* Increase known (fixed) size of fragment. */
847 /* Create a relocation for it. */
848 fix_new (fragP, old_fr_fix, 4,
850 fragP->fr_offset, 1 /* pcrel */,
851 /* FIXME: Can't use a real BFD reloc here.
852 cgen_md_apply_fix3 can't handle it. */
853 BFD_RELOC_M32R_26_PCREL);
855 /* Mark this fragment as finished. */
859 const CGEN_INSN * insn;
862 /* Update the recorded insn.
863 Fortunately we don't have to look very far.
864 FIXME: Change this to record in the instruction the next higher
865 relaxable insn to use. */
866 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
868 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
869 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
871 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
876 fragP->fr_cgen.insn = insn;
882 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
885 /* *fragP has been relaxed to its final size, and now needs to have
886 the bytes inside it modified to conform to the new size.
888 Called after relaxation is finished.
889 fragP->fr_type == rs_machine_dependent.
890 fragP->fr_subtype is the subtype of what the address relaxed to. */
893 md_convert_frag (abfd, sec, fragP)
905 opcode = fragP->fr_opcode;
907 /* Address opcode resides at in file space. */
908 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
910 switch (fragP->fr_subtype)
914 displacement = & opcode[1];
919 displacement = & opcode[1];
922 opcode[2] = opcode[0] | 0x80;
923 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
926 displacement = & opcode[3];
932 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
934 /* symbol must be resolved by linker */
935 if (fragP->fr_offset & 3)
936 as_warn ("Addend to unresolved symbol not on word boundary.");
937 addend = fragP->fr_offset >> 2;
941 /* Address we want to reach in file space. */
942 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
943 target_address += fragP->fr_symbol->sy_frag->fr_address;
944 addend = (target_address - (opcode_address & -4)) >> 2;
947 /* Create a relocation for symbols that must be resolved by the linker.
948 Otherwise output the completed insn. */
950 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
952 assert (fragP->fr_subtype != 1);
953 assert (fragP->fr_cgen.insn != 0);
954 cgen_record_fixup (fragP,
955 /* Offset of branch insn in frag. */
956 fragP->fr_fix + extension - 4,
959 /* FIXME: quick hack */
961 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
963 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
965 fragP->fr_cgen.opinfo,
966 fragP->fr_symbol, fragP->fr_offset);
969 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
971 md_number_to_chars (displacement, (valueT) addend,
972 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
974 fragP->fr_fix += extension;
977 /* Functions concerning relocs. */
979 /* The location from which a PC relative jump should be calculated,
980 given a PC relative reloc. */
983 md_pcrel_from_section (fixP, sec)
987 if (fixP->fx_addsy != (symbolS *) NULL
988 && (! S_IS_DEFINED (fixP->fx_addsy)
989 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
991 /* The symbol is undefined (or is defined but not in this section).
992 Let the linker figure it out. */
996 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
999 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1000 Returns BFD_RELOC_NONE if no reloc type can be found.
1001 *FIXP may be modified if desired. */
1003 bfd_reloc_code_real_type
1004 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1005 const CGEN_INSN * insn;
1006 const CGEN_OPERAND * operand;
1009 switch (CGEN_OPERAND_TYPE (operand))
1011 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1012 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1013 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1014 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1015 case M32R_OPERAND_HI16 :
1016 case M32R_OPERAND_SLO16 :
1017 case M32R_OPERAND_ULO16 :
1018 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1019 if (fixP->tc_fix_data.opinfo != 0)
1020 return fixP->tc_fix_data.opinfo;
1023 return BFD_RELOC_NONE;
1026 /* Called while parsing an instruction to create a fixup.
1027 We need to check for HI16 relocs and queue them up for later sorting. */
1030 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1033 const CGEN_INSN * insn;
1035 const CGEN_OPERAND * operand;
1039 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1040 operand, opinfo, exp);
1042 switch (CGEN_OPERAND_TYPE (operand))
1044 case M32R_OPERAND_HI16 :
1045 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1046 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1047 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1048 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1055 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1058 m32r_record_hi16 (reloc_type, fixP, seg)
1063 struct m32r_hi_fixup * hi_fixup;
1065 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1066 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1068 hi_fixup = ((struct m32r_hi_fixup *)
1069 xmalloc (sizeof (struct m32r_hi_fixup)));
1070 hi_fixup->fixp = fixP;
1071 hi_fixup->seg = now_seg;
1072 hi_fixup->next = m32r_hi_fixup_list;
1074 m32r_hi_fixup_list = hi_fixup;
1077 /* Return BFD reloc type from opinfo field in a fixS.
1078 It's tricky using fx_r_type in m32r_frob_file because the values
1079 are BFD_RELOC_UNUSED + operand number. */
1080 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1082 /* Sort any unmatched HI16 relocs so that they immediately precede
1083 the corresponding LO16 reloc. This is called before md_apply_fix and
1089 struct m32r_hi_fixup * l;
1091 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1093 segment_info_type * seginfo;
1096 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1097 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1099 /* Check quickly whether the next fixup happens to be a matching low. */
1100 if (l->fixp->fx_next != NULL
1101 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1102 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1103 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1106 /* Look through the fixups for this segment for a matching `low'.
1107 When we find one, move the high/shigh just in front of it. We do
1108 this in two passes. In the first pass, we try to find a
1109 unique `low'. In the second pass, we permit multiple high's
1110 relocs for a single `low'. */
1111 seginfo = seg_info (l->seg);
1112 for (pass = 0; pass < 2; pass++)
1118 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1120 /* Check whether this is a `low' fixup which matches l->fixp. */
1121 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1122 && f->fx_addsy == l->fixp->fx_addsy
1123 && f->fx_offset == l->fixp->fx_offset
1126 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1127 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1128 || prev->fx_addsy != f->fx_addsy
1129 || prev->fx_offset != f->fx_offset))
1133 /* Move l->fixp before f. */
1134 for (pf = &seginfo->fix_root;
1136 pf = & (* pf)->fx_next)
1137 assert (* pf != NULL);
1139 * pf = l->fixp->fx_next;
1141 l->fixp->fx_next = f;
1143 seginfo->fix_root = l->fixp;
1145 prev->fx_next = l->fixp;
1157 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1158 "Unmatched high/shigh reloc");
1163 /* See whether we need to force a relocation into the output file.
1164 This is used to force out switch and PC relative relocations when
1168 m32r_force_relocation (fix)
1174 return (fix->fx_pcrel
1178 /* Write a value out to the object file, using the appropriate endianness. */
1181 md_number_to_chars (buf, val, n)
1186 if (target_big_endian)
1187 number_to_chars_bigendian (buf, val, n);
1189 number_to_chars_littleendian (buf, val, n);
1192 /* Turn a string in input_line_pointer into a floating point constant of type
1193 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1194 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1197 /* Equal to MAX_PRECISION in atof-ieee.c */
1198 #define MAX_LITTLENUMS 6
1201 md_atof (type, litP, sizeP)
1208 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1209 LITTLENUM_TYPE * wordP;
1211 char * atof_ieee ();
1229 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1233 return "Bad call to md_atof()";
1236 t = atof_ieee (input_line_pointer, type, words);
1238 input_line_pointer = t;
1239 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1241 if (target_big_endian)
1243 for (i = 0; i < prec; i++)
1245 md_number_to_chars (litP, (valueT) words[i],
1246 sizeof (LITTLENUM_TYPE));
1247 litP += sizeof (LITTLENUM_TYPE);
1252 for (i = prec - 1; i >= 0; i--)
1254 md_number_to_chars (litP, (valueT) words[i],
1255 sizeof (LITTLENUM_TYPE));
1256 litP += sizeof (LITTLENUM_TYPE);