1 /* tc-m32r.c -- Assembler for the Renesas M32R.
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "safe-ctype.h"
27 #include "opcodes/m32r-desc.h"
28 #include "opcodes/m32r-opc.h"
32 /* Linked list of symbols that are debugging symbols to be defined as the
33 beginning of the current instruction. */
34 typedef struct sym_link
36 struct sym_link *next;
40 static sym_linkS *debug_sym_link = (sym_linkS *) 0;
42 /* Structure to hold all of the different components describing
43 an individual instruction. */
46 const CGEN_INSN *insn;
47 const CGEN_INSN *orig_insn;
50 CGEN_INSN_INT buffer[1];
51 #define INSN_VALUE(buf) (*(buf))
53 unsigned char buffer[CGEN_MAX_INSN_SIZE];
54 #define INSN_VALUE(buf) (buf)
59 fixS *fixups[GAS_CGEN_MAX_FIXUPS];
60 int indices[MAX_OPERAND_INSTANCES];
61 sym_linkS *debug_sym_link;
65 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
66 boundary (i.e. was the first of two 16 bit insns). */
67 static m32r_insn prev_insn;
69 /* Non-zero if we've seen a relaxable insn since the last 32 bit
71 static int seen_relaxable_p = 0;
73 /* Non-zero if -relax specified, in which case sufficient relocs are output
74 for the linker to do relaxing.
75 We do simple forms of relaxing internally, but they are always done.
76 This flag does not apply to them. */
77 static int m32r_relax;
80 /* Not supported yet. */
81 /* If non-NULL, pointer to cpu description file to read.
82 This allows runtime additions to the assembler. */
83 static const char *m32r_cpu_desc;
86 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
87 Each high/shigh reloc must be paired with it's low cousin in order to
88 properly calculate the addend in a relocatable link (since there is a
89 potential carry from the low to the high/shigh).
90 This option is off by default though for user-written assembler code it
91 might make sense to make the default be on (i.e. have gcc pass a flag
92 to turn it off). This warning must not be on for GCC created code as
93 optimization may delete the low but not the high/shigh (at least we
94 shouldn't assume or require it to). */
95 static int warn_unmatched_high = 0;
97 /* 1 if -m32rx has been specified, in which case support for
98 the extended M32RX instruction set should be enabled.
99 2 if -m32r2 has been specified, in which case support for
100 the extended M32R2 instruction set should be enabled. */
101 static int enable_m32rx = 0; /* Default to M32R. */
103 /* Non-zero if -m32rx -hidden has been specified, in which case support for
104 the special M32RX instruction set should be enabled. */
105 static int enable_special = 0;
107 /* Non-zero if -bitinst has been specified, in which case support
108 for extended M32R bit-field instruction set should be enabled. */
109 static int enable_special_m32r = 0;
111 /* Non-zero if -float has been specified, in which case support for
112 extended M32R floating point instruction set should be enabled. */
113 static int enable_special_float = 0;
115 /* Non-zero if the programmer should be warned when an explicit parallel
116 instruction might have constraint violations. */
117 static int warn_explicit_parallel_conflicts = 1;
119 /* Non-zero if the programmer should receive an error message when an
120 explicit parallel instruction might have constraint violations. */
121 static int error_explicit_parallel_conflicts = 1;
123 /* Non-zero if insns can be made parallel. */
124 static int use_parallel = 1;
126 /* Non-zero if optimizations should be performed. */
130 static int m32r_flags = 0;
132 /* Stuff for .scomm symbols. */
133 static segT sbss_section;
134 static asection scom_section;
135 static asymbol scom_symbol;
137 const char comment_chars[] = ";";
138 const char line_comment_chars[] = "#";
139 const char line_separator_chars[] = "!";
140 const char EXP_CHARS[] = "eE";
141 const char FLT_CHARS[] = "dD";
143 /* Relocations against symbols are done in two
144 parts, with a HI relocation and a LO relocation. Each relocation
145 has only 16 bits of space to store an addend. This means that in
146 order for the linker to handle carries correctly, it must be able
147 to locate both the HI and the LO relocation. This means that the
148 relocations must appear in order in the relocation table.
150 In order to implement this, we keep track of each unmatched HI
151 relocation. We then sort them so that they immediately precede the
152 corresponding LO relocation. */
157 struct m32r_hi_fixup *next;
162 /* The section this fixup is in. */
166 /* The list of unmatched HI relocs. */
168 static struct m32r_hi_fixup *m32r_hi_fixup_list;
171 enum bfd_architecture bfd_mach;
175 { bfd_mach_m32r, (1<<MACH_M32R) },
176 { bfd_mach_m32rx, (1<<MACH_M32RX) },
177 { bfd_mach_m32r2, (1<<MACH_M32R2) }
180 static void allow_m32rx (int);
187 if (stdoutput != NULL)
188 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach);
190 if (gas_cgen_cpu_desc != NULL)
191 gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
194 #define M32R_SHORTOPTS "O"
196 const char *md_shortopts = M32R_SHORTOPTS;
198 struct option md_longopts[] =
200 #define OPTION_M32R (OPTION_MD_BASE)
201 #define OPTION_M32RX (OPTION_M32R + 1)
202 #define OPTION_M32R2 (OPTION_M32RX + 1)
203 #define OPTION_BIG (OPTION_M32R2 + 1)
204 #define OPTION_LITTLE (OPTION_BIG + 1)
205 #define OPTION_PARALLEL (OPTION_LITTLE + 1)
206 #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1)
207 #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1)
208 #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1)
209 #define OPTION_ERROR_PARALLEL (OPTION_NO_WARN_PARALLEL + 1)
210 #define OPTION_NO_ERROR_PARALLEL (OPTION_ERROR_PARALLEL + 1)
211 #define OPTION_SPECIAL (OPTION_NO_ERROR_PARALLEL + 1)
212 #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1)
213 #define OPTION_SPECIAL_FLOAT (OPTION_SPECIAL_M32R + 1)
214 #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1)
215 #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1)
216 {"m32r", no_argument, NULL, OPTION_M32R},
217 {"m32rx", no_argument, NULL, OPTION_M32RX},
218 {"m32r2", no_argument, NULL, OPTION_M32R2},
219 {"big", no_argument, NULL, OPTION_BIG},
220 {"little", no_argument, NULL, OPTION_LITTLE},
221 {"EB", no_argument, NULL, OPTION_BIG},
222 {"EL", no_argument, NULL, OPTION_LITTLE},
223 {"parallel", no_argument, NULL, OPTION_PARALLEL},
224 {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL},
225 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
226 {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
227 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
228 {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
229 {"error-explicit-parallel-conflicts", no_argument, NULL, OPTION_ERROR_PARALLEL},
230 {"Ep", no_argument, NULL, OPTION_ERROR_PARALLEL},
231 {"no-error-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_ERROR_PARALLEL},
232 {"Enp", no_argument, NULL, OPTION_NO_ERROR_PARALLEL},
233 {"hidden", no_argument, NULL, OPTION_SPECIAL},
234 {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
235 {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
236 /* Sigh. I guess all warnings must now have both variants. */
237 {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
238 {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
239 {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
240 {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
243 /* Not supported yet. */
244 #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1)
245 #define OPTION_CPU_DESC (OPTION_RELAX + 1)
246 {"relax", no_argument, NULL, OPTION_RELAX},
247 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
249 {NULL, no_argument, NULL, 0}
252 size_t md_longopts_size = sizeof (md_longopts);
254 static void little (int);
255 static int parallel (void);
260 target_big_endian = ! on;
263 /* Use parallel execution. */
271 if (use_parallel == 1)
278 md_parse_option (c, arg)
280 char *arg ATTRIBUTE_UNUSED;
300 enable_special_m32r = 1;
304 target_big_endian = 1;
308 target_big_endian = 0;
311 case OPTION_PARALLEL:
315 case OPTION_NO_PARALLEL:
319 case OPTION_WARN_PARALLEL:
320 warn_explicit_parallel_conflicts = 1;
321 error_explicit_parallel_conflicts = 0;
324 case OPTION_NO_WARN_PARALLEL:
325 warn_explicit_parallel_conflicts = 0;
326 error_explicit_parallel_conflicts = 0;
329 case OPTION_ERROR_PARALLEL:
330 warn_explicit_parallel_conflicts = 1;
331 error_explicit_parallel_conflicts = 1;
334 case OPTION_NO_ERROR_PARALLEL:
335 error_explicit_parallel_conflicts = 0;
336 warn_explicit_parallel_conflicts = 0;
344 /* Pretend that we do not recognise this option. */
345 as_bad (_("Unrecognised option: -hidden"));
350 case OPTION_SPECIAL_M32R:
351 enable_special_m32r = 1;
354 case OPTION_SPECIAL_FLOAT:
355 enable_special_float = 1;
358 case OPTION_WARN_UNMATCHED:
359 warn_unmatched_high = 1;
362 case OPTION_NO_WARN_UNMATCHED:
363 warn_unmatched_high = 0;
367 /* Not supported yet. */
371 case OPTION_CPU_DESC:
384 md_show_usage (stream)
387 fprintf (stream, _(" M32R specific command line options:\n"));
389 fprintf (stream, _("\
390 -m32r disable support for the m32rx instruction set\n"));
391 fprintf (stream, _("\
392 -m32rx support the extended m32rx instruction set\n"));
393 fprintf (stream, _("\
394 -m32r2 support the extended m32r2 instruction set\n"));
395 fprintf (stream, _("\
396 -EL,-little produce little endian code and data\n"));
397 fprintf (stream, _("\
398 -EB,-big produce big endian code and data\n"));
399 fprintf (stream, _("\
400 -parallel try to combine instructions in parallel\n"));
401 fprintf (stream, _("\
402 -no-parallel disable -parallel\n"));
403 fprintf (stream, _("\
404 -O try to optimize code. Implies -parallel\n"));
406 fprintf (stream, _("\
407 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
408 fprintf (stream, _("\
409 violate contraints\n"));
410 fprintf (stream, _("\
411 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
412 fprintf (stream, _("\
413 instructions violate contraints\n"));
414 fprintf (stream, _("\
415 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
416 fprintf (stream, _("\
417 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
418 fprintf (stream, _("\
419 -error-explicit-parallel-conflicts error when parallel instructions\n"));
420 fprintf (stream, _("\
421 violate contraints\n"));
422 fprintf (stream, _("\
423 -no-error-explicit-parallel-conflicts do not error when parallel\n"));
424 fprintf (stream, _("\
425 instructions violate contraints\n"));
426 fprintf (stream, _("\
427 -Ep synonym for -error-explicit-parallel-conflicts\n"));
428 fprintf (stream, _("\
429 -Enp synonym for -no-error-explicit-parallel-conflicts\n"));
431 fprintf (stream, _("\
432 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
433 fprintf (stream, _("\
434 -no-warn-unmatched-high do not warn about missing low relocs\n"));
435 fprintf (stream, _("\
436 -Wuh synonym for -warn-unmatched-high\n"));
437 fprintf (stream, _("\
438 -Wnuh synonym for -no-warn-unmatched-high\n"));
441 fprintf (stream, _("\
442 -relax create linker relaxable code\n"));
443 fprintf (stream, _("\
444 -cpu-desc provide runtime cpu description file\n"));
448 static void fill_insn PARAMS ((int));
449 static void m32r_scomm PARAMS ((int));
450 static void debug_sym PARAMS ((int));
451 static void expand_debug_syms PARAMS ((sym_linkS *, int));
453 /* Set by md_assemble for use by m32r_fill_insn. */
454 static subsegT prev_subseg;
455 static segT prev_seg;
457 /* The target specific pseudo-ops which we support. */
458 const pseudo_typeS md_pseudo_table[] =
461 { "fillinsn", fill_insn, 0 },
462 { "scomm", m32r_scomm, 0 },
463 { "debugsym", debug_sym, 0 },
464 { "m32r", allow_m32rx, 0 },
465 { "m32rx", allow_m32rx, 1 },
466 { "m32r2", allow_m32rx, 2 },
467 { "little", little, 1 },
468 { "big", little, 0 },
472 /* FIXME: Should be machine generated. */
473 #define NOP_INSN 0x7000
474 #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */
476 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
477 of an rs_align_code fragment. */
480 m32r_handle_align (fragp)
483 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
484 static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
489 if (fragp->fr_type != rs_align_code)
492 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
493 p = fragp->fr_literal + fragp->fr_fix;
505 memcpy (p, nop_pattern, 2);
511 memcpy (p, multi_nop_pattern, 4);
513 fragp->fr_fix += fix;
517 /* If the last instruction was the first of 2 16 bit insns,
518 output a nop to move the PC to a 32 bit boundary.
520 This is done via an alignment specification since branch relaxing
521 may make it unnecessary.
523 Internally, we need to output one of these each time a 32 bit insn is
524 seen after an insn that is relaxable. */
528 int ignore ATTRIBUTE_UNUSED;
530 frag_align_code (2, 0);
531 prev_insn.insn = NULL;
532 seen_relaxable_p = 0;
535 /* Record the symbol so that when we output the insn, we can create
536 a symbol that is at the start of the instruction. This is used
537 to emit the label for the start of a breakpoint without causing
538 the assembler to emit a NOP if the previous instruction was a
539 16 bit instruction. */
543 int ignore ATTRIBUTE_UNUSED;
547 register char *end_name;
548 register symbolS *symbolP;
549 register sym_linkS *link;
551 name = input_line_pointer;
552 delim = get_symbol_end ();
553 end_name = input_line_pointer;
555 if ((symbolP = symbol_find (name)) == NULL
556 && (symbolP = md_undefined_symbol (name)) == NULL)
558 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
561 symbol_table_insert (symbolP);
562 if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section)
563 /* xgettext:c-format */
564 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
568 link = (sym_linkS *) xmalloc (sizeof (sym_linkS));
569 link->symbol = symbolP;
570 link->next = debug_sym_link;
571 debug_sym_link = link;
572 symbol_get_obj (symbolP)->local = 1;
576 demand_empty_rest_of_line ();
579 /* Second pass to expanding the debug symbols, go through linked
580 list of symbols and reassign the address. */
583 expand_debug_syms (syms, align)
587 char *save_input_line = input_line_pointer;
588 sym_linkS *next_syms;
593 (void) frag_align_code (align, 0);
594 for (; syms != (sym_linkS *) 0; syms = next_syms)
596 symbolS *symbolP = syms->symbol;
597 next_syms = syms->next;
598 input_line_pointer = ".\n";
599 pseudo_set (symbolP);
600 free ((char *) syms);
603 input_line_pointer = save_input_line;
607 m32r_flush_pending_output()
611 expand_debug_syms (debug_sym_link, 1);
612 debug_sym_link = (sym_linkS *) 0;
616 /* Cover function to fill_insn called after a label and at end of assembly.
617 The result is always 1: we're called in a conditional to see if the
618 current line is a label. */
621 m32r_fill_insn (done)
624 if (prev_seg != NULL)
627 subsegT subseg = now_subseg;
629 subseg_set (prev_seg, prev_subseg);
633 subseg_set (seg, subseg);
636 if (done && debug_sym_link)
638 expand_debug_syms (debug_sym_link, 1);
639 debug_sym_link = (sym_linkS *) 0;
645 /* The default target format to use. */
648 m32r_target_format ()
651 if (target_big_endian)
652 return "elf32-m32r-linux";
654 return "elf32-m32rle-linux";
656 if (target_big_endian)
659 return "elf32-m32rle";
670 /* Initialize the `cgen' interface. */
672 /* Set the machine number and endian. */
673 gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
674 CGEN_CPU_OPEN_ENDIAN,
676 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE),
678 m32r_cgen_init_asm (gas_cgen_cpu_desc);
680 /* The operand instance table is used during optimization to determine
681 which insns can be executed in parallel. It is also used to give
682 warnings regarding operand interference in parallel insns. */
683 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc);
685 /* This is a callback from cgen to gas to parse operands. */
686 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
689 /* Not supported yet. */
690 /* If a runtime cpu description file was provided, parse it. */
691 if (m32r_cpu_desc != NULL)
695 errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc);
697 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
701 /* Save the current subseg so we can restore it [it's the default one and
702 we don't want the initial section to be .sbss]. */
706 /* The sbss section is for local .scomm symbols. */
707 sbss_section = subseg_new (".sbss", 0);
709 /* This is copied from perform_an_assembly_pass. */
710 applicable = bfd_applicable_section_flags (stdoutput);
711 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
714 /* What does this do? [see perform_an_assembly_pass] */
715 seg_info (bss_section)->bss = 1;
718 subseg_set (seg, subseg);
720 /* We must construct a fake section similar to bfd_com_section
721 but with the name .scommon. */
722 scom_section = bfd_com_section;
723 scom_section.name = ".scommon";
724 scom_section.output_section = &scom_section;
725 scom_section.symbol = &scom_symbol;
726 scom_section.symbol_ptr_ptr = &scom_section.symbol;
727 scom_symbol = *bfd_com_section.symbol;
728 scom_symbol.name = ".scommon";
729 scom_symbol.section = &scom_section;
731 allow_m32rx (enable_m32rx);
733 gas_cgen_initialize_saved_fixups_array ();
736 #define OPERAND_IS_COND_BIT(operand, indices, index) \
737 ((operand)->hw_type == HW_H_COND \
738 || ((operand)->hw_type == HW_H_PSW) \
739 || ((operand)->hw_type == HW_H_CR \
740 && (indices [index] == 0 || indices [index] == 1)))
742 /* Returns true if an output of instruction 'a' is referenced by an operand
743 of instruction 'b'. If 'check_outputs' is true then b's outputs are
744 checked, otherwise its inputs are examined. */
746 static int first_writes_to_seconds_operands
747 PARAMS ((m32r_insn *, m32r_insn *, const int));
750 first_writes_to_seconds_operands (a, b, check_outputs)
753 const int check_outputs;
755 const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn);
756 const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn);
759 /* If at least one of the instructions takes no operands, then there is
760 nothing to check. There really are instructions without operands,
762 if (a_operands == NULL || b_ops == NULL)
765 /* Scan the operand list of 'a' looking for an output operand. */
767 a_operands->type != CGEN_OPINST_END;
768 a_index ++, a_operands ++)
770 if (a_operands->type == CGEN_OPINST_OUTPUT)
773 const CGEN_OPINST *b_operands = b_ops;
776 The Condition bit 'C' is a shadow of the CBR register (control
777 register 1) and also a shadow of bit 31 of the program status
778 word (control register 0). For now this is handled here, rather
781 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
783 /* Scan operand list of 'b' looking for another reference to the
784 condition bit, which goes in the right direction. */
786 b_operands->type != CGEN_OPINST_END;
787 b_index++, b_operands++)
789 if ((b_operands->type
792 : CGEN_OPINST_INPUT))
793 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
799 /* Scan operand list of 'b' looking for an operand that
800 references the same hardware element, and which goes in the
803 b_operands->type != CGEN_OPINST_END;
804 b_index++, b_operands++)
806 if ((b_operands->type
809 : CGEN_OPINST_INPUT))
810 && (b_operands->hw_type == a_operands->hw_type)
811 && (a->indices[a_index] == b->indices[b_index]))
821 /* Returns true if the insn can (potentially) alter the program counter. */
823 static int writes_to_pc PARAMS ((m32r_insn *));
830 /* Once PC operands are working.... */
831 const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc,
834 if (a_operands == NULL)
837 while (a_operands->type != CGEN_OPINST_END)
839 if (a_operands->operand != NULL
840 && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc,
841 a_operands->operand) == M32R_OPERAND_PC)
847 if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
848 || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
854 /* Return NULL if the two 16 bit insns can be executed in parallel.
855 Otherwise return a pointer to an error message explaining why not. */
857 static const char *can_make_parallel PARAMS ((m32r_insn *, m32r_insn *));
860 can_make_parallel (a, b)
867 /* Make sure the instructions are the right length. */
868 if (CGEN_FIELDS_BITSIZE (&a->fields) != 16
869 || CGEN_FIELDS_BITSIZE (&b->fields) != 16)
872 if (first_writes_to_seconds_operands (a, b, TRUE))
873 return _("Instructions write to the same destination register.");
875 a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
876 b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
878 /* Make sure that the instructions use the correct execution pipelines. */
879 if (a_pipe == PIPE_NONE
880 || b_pipe == PIPE_NONE)
881 return _("Instructions do not use parallel execution pipelines.");
883 /* Leave this test for last, since it is the only test that can
884 go away if the instructions are swapped, and we want to make
885 sure that any other errors are detected before this happens. */
888 || (b_pipe == PIPE_O_OS && (enable_m32rx != 2)))
889 return _("Instructions share the same execution pipeline");
894 /* Force the top bit of the second 16-bit insn to be set. */
896 static void make_parallel PARAMS ((CGEN_INSN_BYTES_PTR));
899 make_parallel (buffer)
900 CGEN_INSN_BYTES_PTR buffer;
905 buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
910 /* Same as make_parallel except buffer contains the bytes in target order. */
912 static void target_make_parallel PARAMS ((char *));
915 target_make_parallel (buffer)
918 buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
922 /* Assemble two instructions with an explicit parallel operation (||) or
923 sequential operation (->). */
925 static void assemble_two_insns PARAMS ((char *, char *, int));
928 assemble_two_insns (str, str2, parallel_p)
937 char save_str2 = *str2;
939 /* Separate the two instructions. */
942 /* Make sure the two insns begin on a 32 bit boundary.
943 This is also done for the serial case (foo -> bar), relaxing doesn't
944 affect insns written like this.
945 Note that we must always do this as we can't assume anything about
946 whether we're currently on a 32 bit boundary or not. Relaxing may
950 first.debug_sym_link = debug_sym_link;
951 debug_sym_link = (sym_linkS *) 0;
953 /* Parse the first instruction. */
954 if (! (first.insn = m32r_cgen_assemble_insn
955 (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg)))
962 if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
964 /* xgettext:c-format */
965 as_bad (_("not a 16 bit instruction '%s'"), str);
969 else if ((enable_m32rx == 1)
970 /* FIXME: Need standard macro to perform this test. */
971 && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
973 && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
974 & (1 << MACH_M32RX)))))
976 /* xgettext:c-format */
977 as_bad (_("instruction '%s' is for the M32R2 only"), str);
980 else if ((! enable_special
981 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
982 || (! enable_special_m32r
983 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)))
985 else if (! enable_special
986 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
989 /* xgettext:c-format */
990 as_bad (_("unknown instruction '%s'"), str);
993 else if (! enable_m32rx
994 /* FIXME: Need standard macro to perform this test. */
995 && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
996 == (1 << MACH_M32RX)))
998 /* xgettext:c-format */
999 as_bad (_("instruction '%s' is for the M32RX only"), str);
1003 /* Check to see if this is an allowable parallel insn. */
1005 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
1007 /* xgettext:c-format */
1008 as_bad (_("instruction '%s' cannot be executed in parallel."), str);
1012 /* Restore the original assembly text, just in case it is needed. */
1015 /* Save the original string pointer. */
1018 /* Advanced past the parsed string. */
1021 /* Remember the entire string in case it is needed for error
1025 /* Convert the opcode to lower case. */
1029 while (ISSPACE (*s2++))
1034 while (ISALNUM (*s2))
1036 *s2 = TOLOWER (*s2);
1041 /* Preserve any fixups that have been generated and reset the list
1043 gas_cgen_save_fixups (0);
1045 /* Get the indices of the operands of the instruction. */
1046 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
1047 doesn't seem right. Perhaps allow passing fields like we do insn. */
1048 /* FIXME: ALIAS insns do not have operands, so we use this function
1049 to find the equivalent insn and overwrite the value stored in our
1050 structure. We still need the original insn, however, since this
1051 may have certain attributes that are not present in the unaliased
1052 version (eg relaxability). When aliases behave differently this
1053 may have to change. */
1054 first.orig_insn = first.insn;
1056 CGEN_FIELDS tmp_fields;
1057 first.insn = cgen_lookup_get_insn_operands
1058 (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
1059 first.indices, &tmp_fields);
1062 if (first.insn == NULL)
1063 as_fatal (_("internal error: lookup/get operands failed"));
1065 second.debug_sym_link = NULL;
1067 /* Parse the second instruction. */
1068 if (! (second.insn = m32r_cgen_assemble_insn
1069 (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg)))
1076 if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
1078 /* xgettext:c-format */
1079 as_bad (_("not a 16 bit instruction '%s'"), str);
1083 else if ((enable_m32rx == 1)
1084 /* FIXME: Need standard macro to perform this test. */
1085 && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
1086 & (1 << MACH_M32R2))
1087 && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
1088 & (1 << MACH_M32RX)))))
1090 /* xgettext:c-format */
1091 as_bad (_("instruction '%s' is for the M32R2 only"), str);
1094 else if ((! enable_special
1095 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
1096 || (! enable_special_m32r
1097 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)))
1099 else if (! enable_special
1100 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
1103 /* xgettext:c-format */
1104 as_bad (_("unknown instruction '%s'"), str);
1107 else if (! enable_m32rx
1108 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
1110 /* xgettext:c-format */
1111 as_bad (_("instruction '%s' is for the M32RX only"), str);
1115 /* Check to see if this is an allowable parallel insn. */
1117 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
1119 /* xgettext:c-format */
1120 as_bad (_("instruction '%s' cannot be executed in parallel."), str);
1124 if (parallel_p && ! enable_m32rx)
1126 if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
1127 && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
1129 /* xgettext:c-format */
1130 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
1135 /* Get the indices of the operands of the instruction. */
1136 second.orig_insn = second.insn;
1138 CGEN_FIELDS tmp_fields;
1139 second.insn = cgen_lookup_get_insn_operands
1140 (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
1141 second.indices, &tmp_fields);
1144 if (second.insn == NULL)
1145 as_fatal (_("internal error: lookup/get operands failed"));
1147 /* We assume that if the first instruction writes to a register that is
1148 read by the second instruction it is because the programmer intended
1149 this to happen, (after all they have explicitly requested that these
1150 two instructions be executed in parallel). Although if the global
1151 variable warn_explicit_parallel_conflicts is true then we do generate
1152 a warning message. Similarly we assume that parallel branch and jump
1153 instructions are deliberate and should not produce errors. */
1155 if (parallel_p && warn_explicit_parallel_conflicts)
1157 void (* func)(const char *, ...);
1159 func = error_explicit_parallel_conflicts ? as_bad : as_warn;
1161 if (first_writes_to_seconds_operands (&first, &second, FALSE))
1162 /* xgettext:c-format */
1163 func (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
1165 if (first_writes_to_seconds_operands (&second, &first, FALSE))
1166 /* xgettext:c-format */
1167 func (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
1171 || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL)
1173 /* Get the fixups for the first instruction. */
1174 gas_cgen_swap_fixups (0);
1177 expand_debug_syms (first.debug_sym_link, 1);
1178 gas_cgen_finish_insn (first.orig_insn, first.buffer,
1179 CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
1181 /* Force the top bit of the second insn to be set. */
1183 make_parallel (second.buffer);
1185 /* Get its fixups. */
1186 gas_cgen_restore_fixups (0);
1189 expand_debug_syms (second.debug_sym_link, 1);
1190 gas_cgen_finish_insn (second.orig_insn, second.buffer,
1191 CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
1193 /* Try swapping the instructions to see if they work that way. */
1194 else if (can_make_parallel (&second, &first) == NULL)
1196 /* Write out the second instruction first. */
1197 expand_debug_syms (second.debug_sym_link, 1);
1198 gas_cgen_finish_insn (second.orig_insn, second.buffer,
1199 CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
1201 /* Force the top bit of the first instruction to be set. */
1202 make_parallel (first.buffer);
1204 /* Get the fixups for the first instruction. */
1205 gas_cgen_restore_fixups (0);
1207 /* Write out the first instruction. */
1208 expand_debug_syms (first.debug_sym_link, 1);
1209 gas_cgen_finish_insn (first.orig_insn, first.buffer,
1210 CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
1214 as_bad ("'%s': %s", str2, errmsg);
1218 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)
1219 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
1220 m32r_flags |= E_M32R_HAS_HIDDEN_INST;
1221 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)
1222 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))
1223 m32r_flags |= E_M32R_HAS_BIT_INST;
1224 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT)
1225 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT))
1226 m32r_flags |= E_M32R_HAS_FLOAT_INST;
1228 /* Set these so m32r_fill_insn can use them. */
1230 prev_subseg = now_subseg;
1241 /* Initialize GAS's cgen interface for a new instruction. */
1242 gas_cgen_init_parse ();
1244 /* Look for a parallel instruction separator. */
1245 if ((str2 = strstr (str, "||")) != NULL)
1247 assemble_two_insns (str, str2, 1);
1248 m32r_flags |= E_M32R_HAS_PARALLEL;
1252 /* Also look for a sequential instruction separator. */
1253 if ((str2 = strstr (str, "->")) != NULL)
1255 assemble_two_insns (str, str2, 0);
1259 insn.debug_sym_link = debug_sym_link;
1260 debug_sym_link = (sym_linkS *) 0;
1262 insn.insn = m32r_cgen_assemble_insn
1263 (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg);
1272 if ((enable_m32rx == 1)
1273 /* FIXME: Need standard macro to perform this test. */
1274 && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
1275 & (1 << MACH_M32R2))
1276 && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
1277 & (1 << MACH_M32RX)))))
1279 /* xgettext:c-format */
1280 as_bad (_("instruction '%s' is for the M32R2 only"), str);
1283 else if ((! enable_special
1284 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
1285 || (! enable_special_m32r
1286 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)))
1288 if (! enable_special
1289 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
1292 /* xgettext:c-format */
1293 as_bad (_("unknown instruction '%s'"), str);
1296 else if (! enable_m32rx
1297 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
1299 /* xgettext:c-format */
1300 as_bad (_("instruction '%s' is for the M32RX only"), str);
1304 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
1305 m32r_flags |= E_M32R_HAS_HIDDEN_INST;
1306 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))
1307 m32r_flags |= E_M32R_HAS_BIT_INST;
1308 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT))
1309 m32r_flags |= E_M32R_HAS_FLOAT_INST;
1311 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
1313 /* 32 bit insns must live on 32 bit boundaries. */
1314 if (prev_insn.insn || seen_relaxable_p)
1316 /* ??? If calling fill_insn too many times turns us into a memory
1317 pig, can we call a fn to assemble a nop instead of
1318 !seen_relaxable_p? */
1322 expand_debug_syms (insn.debug_sym_link, 2);
1324 /* Doesn't really matter what we pass for RELAX_P here. */
1325 gas_cgen_finish_insn (insn.insn, insn.buffer,
1326 CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL);
1330 int on_32bit_boundary_p;
1333 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
1336 insn.orig_insn = insn.insn;
1338 /* If the previous insn was relaxable, then it may be expanded
1339 to fill the current 16 bit slot. Emit a NOP here to occupy
1340 this slot, so that we can start at optimizing at a 32 bit
1342 if (prev_insn.insn && seen_relaxable_p && optimize)
1347 /* Get the indices of the operands of the instruction.
1348 FIXME: See assemble_parallel for notes on orig_insn. */
1350 CGEN_FIELDS tmp_fields;
1351 insn.insn = cgen_lookup_get_insn_operands
1352 (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
1353 16, insn.indices, &tmp_fields);
1356 if (insn.insn == NULL)
1357 as_fatal (_("internal error: lookup/get operands failed"));
1360 /* Compute whether we're on a 32 bit boundary or not.
1361 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1362 on_32bit_boundary_p = prev_insn.insn == NULL;
1364 /* Look to see if this instruction can be combined with the
1365 previous instruction to make one, parallel, 32 bit instruction.
1366 If the previous instruction (potentially) changed the flow of
1367 program control, then it cannot be combined with the current
1368 instruction. If the current instruction is relaxable, then it
1369 might be replaced with a longer version, so we cannot combine it.
1370 Also if the output of the previous instruction is used as an
1371 input to the current instruction then it cannot be combined.
1372 Otherwise call can_make_parallel() with both orderings of the
1373 instructions to see if they can be combined. */
1374 if (! on_32bit_boundary_p
1376 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
1377 && ! writes_to_pc (&prev_insn)
1378 && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE))
1380 if (can_make_parallel (&prev_insn, &insn) == NULL)
1381 make_parallel (insn.buffer);
1382 else if (can_make_parallel (&insn, &prev_insn) == NULL)
1386 expand_debug_syms (insn.debug_sym_link, 1);
1392 /* Ensure each pair of 16 bit insns is in the same frag. */
1395 gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
1396 CGEN_FIELDS_BITSIZE (&insn.fields),
1397 1 /* relax_p */, &fi);
1398 insn.addr = fi.addr;
1399 insn.frag = fi.frag;
1400 insn.num_fixups = fi.num_fixups;
1401 for (i = 0; i < fi.num_fixups; ++i)
1402 insn.fixups[i] = fi.fixups[i];
1409 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1411 /* Swap the two insns */
1412 SWAP_BYTES (prev_insn.addr[0], insn.addr[0]);
1413 SWAP_BYTES (prev_insn.addr[1], insn.addr[1]);
1415 target_make_parallel (insn.addr);
1417 /* Swap any relaxable frags recorded for the two insns. */
1418 /* FIXME: Clarify. relaxation precludes parallel insns */
1419 if (prev_insn.frag->fr_opcode == prev_insn.addr)
1420 prev_insn.frag->fr_opcode = insn.addr;
1421 else if (insn.frag->fr_opcode == insn.addr)
1422 insn.frag->fr_opcode = prev_insn.addr;
1424 /* Update the addresses in any fixups.
1425 Note that we don't have to handle the case where each insn is in
1426 a different frag as we ensure they're in the same frag above. */
1427 for (i = 0; i < prev_insn.num_fixups; ++i)
1428 prev_insn.fixups[i]->fx_where += 2;
1429 for (i = 0; i < insn.num_fixups; ++i)
1430 insn.fixups[i]->fx_where -= 2;
1433 /* Keep track of whether we've seen a pair of 16 bit insns.
1434 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1435 if (on_32bit_boundary_p)
1438 prev_insn.insn = NULL;
1440 /* If the insn needs the following one to be on a 32 bit boundary
1441 (e.g. subroutine calls), fill this insn's slot. */
1442 if (on_32bit_boundary_p
1443 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
1446 /* If this is a relaxable insn (can be replaced with a larger version)
1447 mark the fact so that we can emit an alignment directive for a
1448 following 32 bit insn if we see one. */
1449 if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
1450 seen_relaxable_p = 1;
1453 /* Set these so m32r_fill_insn can use them. */
1455 prev_subseg = now_subseg;
1458 /* The syntax in the manual says constants begin with '#'.
1459 We just ignore it. */
1462 md_operand (expressionP)
1463 expressionS *expressionP;
1465 if (*input_line_pointer == '#')
1467 input_line_pointer++;
1468 expression (expressionP);
1473 md_section_align (segment, size)
1477 int align = bfd_get_section_alignment (stdoutput, segment);
1478 return ((size + (1 << align) - 1) & (-1 << align));
1482 md_undefined_symbol (name)
1483 char *name ATTRIBUTE_UNUSED;
1488 /* .scomm pseudo-op handler.
1490 This is a new pseudo-op to handle putting objects in .scommon.
1491 By doing this the linker won't need to do any work,
1492 and more importantly it removes the implicit -G arg necessary to
1493 correctly link the object file. */
1497 int ignore ATTRIBUTE_UNUSED;
1499 register char *name;
1503 register symbolS *symbolP;
1507 name = input_line_pointer;
1508 c = get_symbol_end ();
1510 /* Just after name is now '\0'. */
1511 p = input_line_pointer;
1514 if (*input_line_pointer != ',')
1516 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1517 ignore_rest_of_line ();
1522 input_line_pointer++;
1523 if ((size = get_absolute_expression ()) < 0)
1525 /* xgettext:c-format */
1526 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
1527 ignore_rest_of_line ();
1531 /* The third argument to .scomm is the alignment. */
1532 if (*input_line_pointer != ',')
1536 ++input_line_pointer;
1537 align = get_absolute_expression ();
1540 as_warn (_("ignoring bad alignment"));
1545 /* Convert to a power of 2 alignment. */
1548 for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
1552 as_bad (_("Common alignment not a power of 2"));
1553 ignore_rest_of_line ();
1561 symbolP = symbol_find_or_make (name);
1564 if (S_IS_DEFINED (symbolP))
1566 /* xgettext:c-format */
1567 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1568 S_GET_NAME (symbolP));
1569 ignore_rest_of_line ();
1573 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
1575 /* xgettext:c-format */
1576 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1577 S_GET_NAME (symbolP),
1578 (long) S_GET_VALUE (symbolP),
1581 ignore_rest_of_line ();
1585 if (symbol_get_obj (symbolP)->local)
1587 segT old_sec = now_seg;
1588 int old_subsec = now_subseg;
1591 record_alignment (sbss_section, align2);
1592 subseg_set (sbss_section, 0);
1595 frag_align (align2, 0, 0);
1597 if (S_GET_SEGMENT (symbolP) == sbss_section)
1598 symbol_get_frag (symbolP)->fr_symbol = 0;
1600 symbol_set_frag (symbolP, frag_now);
1602 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
1605 S_SET_SIZE (symbolP, size);
1606 S_SET_SEGMENT (symbolP, sbss_section);
1607 S_CLEAR_EXTERNAL (symbolP);
1608 subseg_set (old_sec, old_subsec);
1612 S_SET_VALUE (symbolP, (valueT) size);
1613 S_SET_ALIGN (symbolP, align2);
1614 S_SET_EXTERNAL (symbolP);
1615 S_SET_SEGMENT (symbolP, &scom_section);
1618 demand_empty_rest_of_line ();
1621 /* Interface to relax_segment. */
1623 /* FIXME: Build table by hand, get it working, then machine generate. */
1625 const relax_typeS md_relax_table[] =
1628 1) most positive reach of this state,
1629 2) most negative reach of this state,
1630 3) how many bytes this mode will add to the size of the current frag
1631 4) which index into the table to try if we can't fit into this one. */
1633 /* The first entry must be unused because an `rlx_more' value of zero ends
1637 /* The displacement used by GAS is from the end of the 2 byte insn,
1638 so we subtract 2 from the following. */
1639 /* 16 bit insn, 8 bit disp -> 10 bit range.
1640 This doesn't handle a branch in the right slot at the border:
1641 the "& -4" isn't taken into account. It's not important enough to
1642 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1644 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1645 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1646 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1647 /* Same thing, but with leading nop for alignment. */
1648 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1652 m32r_relax_frag (segment, fragP, stretch)
1657 /* Address of branch insn. */
1658 long address = fragP->fr_address + fragP->fr_fix - 2;
1661 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1662 if (fragP->fr_subtype == 2)
1664 if ((address & 3) != 0)
1666 fragP->fr_subtype = 3;
1670 else if (fragP->fr_subtype == 3)
1672 if ((address & 3) == 0)
1674 fragP->fr_subtype = 2;
1680 growth = relax_frag (segment, fragP, stretch);
1682 /* Long jump on odd halfword boundary? */
1683 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1685 fragP->fr_subtype = 3;
1693 /* Return an initial guess of the length by which a fragment must grow to
1694 hold a branch to reach its destination.
1695 Also updates fr_type/fr_subtype as necessary.
1697 Called just before doing relaxation.
1698 Any symbol that is now undefined will not become defined.
1699 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1700 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1701 Although it may not be explicit in the frag, pretend fr_var starts
1705 md_estimate_size_before_relax (fragP, segment)
1709 /* The only thing we have to handle here are symbols outside of the
1710 current segment. They may be undefined or in a different segment in
1711 which case linker scripts may place them anywhere.
1712 However, we can't finish the fragment here and emit the reloc as insn
1713 alignment requirements may move the insn about. */
1715 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1718 int old_fr_fix = fragP->fr_fix;
1721 /* The symbol is undefined in this segment.
1722 Change the relaxation subtype to the max allowable and leave
1723 all further handling to md_convert_frag. */
1724 fragP->fr_subtype = 2;
1727 /* Can't use this, but leave in for illustration. */
1728 /* Change 16 bit insn to 32 bit insn. */
1729 fragP->fr_opcode[0] |= 0x80;
1731 /* Increase known (fixed) size of fragment. */
1734 /* Create a relocation for it. */
1735 fix_new (fragP, old_fr_fix, 4,
1737 fragP->fr_offset, 1 /* pcrel */,
1738 /* FIXME: Can't use a real BFD reloc here.
1739 gas_cgen_md_apply_fix3 can't handle it. */
1740 BFD_RELOC_M32R_26_PCREL);
1742 /* Mark this fragment as finished. */
1744 return fragP->fr_fix - old_fr_fix;
1747 const CGEN_INSN *insn;
1750 /* Update the recorded insn.
1751 Fortunately we don't have to look very far.
1752 FIXME: Change this to record in the instruction the next higher
1753 relaxable insn to use. */
1754 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1756 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1757 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1759 && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED))
1765 fragP->fr_cgen.insn = insn;
1771 return md_relax_table[fragP->fr_subtype].rlx_length;
1774 /* *FRAGP has been relaxed to its final size, and now needs to have
1775 the bytes inside it modified to conform to the new size.
1777 Called after relaxation is finished.
1778 fragP->fr_type == rs_machine_dependent.
1779 fragP->fr_subtype is the subtype of what the address relaxed to. */
1782 md_convert_frag (abfd, sec, fragP)
1783 bfd *abfd ATTRIBUTE_UNUSED;
1794 opcode = fragP->fr_opcode;
1796 /* Address opcode resides at in file space. */
1797 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1799 switch (fragP->fr_subtype)
1803 displacement = &opcode[1];
1808 displacement = &opcode[1];
1811 opcode[2] = opcode[0] | 0x80;
1812 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1813 opcode_address += 2;
1815 displacement = &opcode[3];
1821 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1823 /* Symbol must be resolved by linker. */
1824 if (fragP->fr_offset & 3)
1825 as_warn (_("Addend to unresolved symbol not on word boundary."));
1826 addend = fragP->fr_offset >> 2;
1830 /* Address we want to reach in file space. */
1831 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1832 addend = (target_address - (opcode_address & -4)) >> 2;
1835 /* Create a relocation for symbols that must be resolved by the linker.
1836 Otherwise output the completed insn. */
1838 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1840 assert (fragP->fr_subtype != 1);
1841 assert (fragP->fr_cgen.insn != 0);
1842 gas_cgen_record_fixup (fragP,
1843 /* Offset of branch insn in frag. */
1844 fragP->fr_fix + extension - 4,
1845 fragP->fr_cgen.insn,
1847 /* FIXME: quick hack. */
1849 cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
1850 fragP->fr_cgen.opindex),
1852 cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
1853 M32R_OPERAND_DISP24),
1855 fragP->fr_cgen.opinfo,
1856 fragP->fr_symbol, fragP->fr_offset);
1859 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1861 md_number_to_chars (displacement, (valueT) addend,
1862 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1864 fragP->fr_fix += extension;
1867 /* Functions concerning relocs. */
1869 /* The location from which a PC relative jump should be calculated,
1870 given a PC relative reloc. */
1873 md_pcrel_from_section (fixP, sec)
1877 if (fixP->fx_addsy != (symbolS *) NULL
1878 && (! S_IS_DEFINED (fixP->fx_addsy)
1879 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1881 /* The symbol is undefined (or is defined but not in this section).
1882 Let the linker figure it out. */
1886 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1889 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1890 Returns BFD_RELOC_NONE if no reloc type can be found.
1891 *FIXP may be modified if desired. */
1893 bfd_reloc_code_real_type
1894 md_cgen_lookup_reloc (insn, operand, fixP)
1895 const CGEN_INSN *insn ATTRIBUTE_UNUSED;
1896 const CGEN_OPERAND *operand;
1899 switch (operand->type)
1901 case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL;
1902 case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL;
1903 case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL;
1904 case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24;
1905 case M32R_OPERAND_HI16:
1906 case M32R_OPERAND_SLO16:
1907 case M32R_OPERAND_ULO16:
1908 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1909 if (fixP->fx_cgen.opinfo != 0)
1910 return fixP->fx_cgen.opinfo;
1913 /* Avoid -Wall warning. */
1916 return BFD_RELOC_NONE;
1919 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1921 static void m32r_record_hi16 PARAMS ((int, fixS *, segT));
1924 m32r_record_hi16 (reloc_type, fixP, seg)
1927 segT seg ATTRIBUTE_UNUSED;
1929 struct m32r_hi_fixup *hi_fixup;
1931 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1932 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1934 hi_fixup = ((struct m32r_hi_fixup *)
1935 xmalloc (sizeof (struct m32r_hi_fixup)));
1936 hi_fixup->fixp = fixP;
1937 hi_fixup->seg = now_seg;
1938 hi_fixup->next = m32r_hi_fixup_list;
1940 m32r_hi_fixup_list = hi_fixup;
1943 /* Called while parsing an instruction to create a fixup.
1944 We need to check for HI16 relocs and queue them up for later sorting. */
1947 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1950 const CGEN_INSN *insn;
1952 const CGEN_OPERAND *operand;
1956 fixS *fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
1957 operand, opinfo, exp);
1959 switch (operand->type)
1961 case M32R_OPERAND_HI16:
1962 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1963 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO
1964 || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
1965 m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
1968 /* Avoid -Wall warning */
1975 /* Return BFD reloc type from opinfo field in a fixS.
1976 It's tricky using fx_r_type in m32r_frob_file because the values
1977 are BFD_RELOC_UNUSED + operand number. */
1978 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
1980 /* Sort any unmatched HI16 relocs so that they immediately precede
1981 the corresponding LO16 reloc. This is called before md_apply_fix3 and
1987 struct m32r_hi_fixup *l;
1989 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1991 segment_info_type *seginfo;
1994 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1995 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1997 /* Check quickly whether the next fixup happens to be a matching low. */
1998 if (l->fixp->fx_next != NULL
1999 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
2000 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
2001 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
2004 /* Look through the fixups for this segment for a matching `low'.
2005 When we find one, move the high/shigh just in front of it. We do
2006 this in two passes. In the first pass, we try to find a
2007 unique `low'. In the second pass, we permit multiple high's
2008 relocs for a single `low'. */
2009 seginfo = seg_info (l->seg);
2010 for (pass = 0; pass < 2; pass++)
2016 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
2018 /* Check whether this is a `low' fixup which matches l->fixp. */
2019 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
2020 && f->fx_addsy == l->fixp->fx_addsy
2021 && f->fx_offset == l->fixp->fx_offset
2024 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
2025 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
2026 || prev->fx_addsy != f->fx_addsy
2027 || prev->fx_offset != f->fx_offset))
2031 /* Move l->fixp before f. */
2032 for (pf = &seginfo->fix_root;
2034 pf = & (*pf)->fx_next)
2035 assert (*pf != NULL);
2037 *pf = l->fixp->fx_next;
2039 l->fixp->fx_next = f;
2041 seginfo->fix_root = l->fixp;
2043 prev->fx_next = l->fixp;
2055 && warn_unmatched_high)
2056 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
2057 _("Unmatched high/shigh reloc"));
2062 /* See whether we need to force a relocation into the output file.
2063 This is used to force out switch and PC relative relocations when
2067 m32r_force_relocation (fix)
2070 if (generic_force_reloc (fix))
2076 return fix->fx_pcrel;
2079 /* Write a value out to the object file, using the appropriate endianness. */
2082 md_number_to_chars (buf, val, n)
2087 if (target_big_endian)
2088 number_to_chars_bigendian (buf, val, n);
2090 number_to_chars_littleendian (buf, val, n);
2093 /* Turn a string in input_line_pointer into a floating point constant
2094 of type TYPE, and store the appropriate bytes in *LITP. The number
2095 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2096 returned, or NULL on OK. */
2098 /* Equal to MAX_PRECISION in atof-ieee.c. */
2099 #define MAX_LITTLENUMS 6
2102 md_atof (type, litP, sizeP)
2109 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2128 /* FIXME: Some targets allow other format chars for bigger sizes
2133 return _("Bad call to md_atof()");
2136 t = atof_ieee (input_line_pointer, type, words);
2138 input_line_pointer = t;
2139 *sizeP = prec * sizeof (LITTLENUM_TYPE);
2141 if (target_big_endian)
2143 for (i = 0; i < prec; i++)
2145 md_number_to_chars (litP, (valueT) words[i],
2146 sizeof (LITTLENUM_TYPE));
2147 litP += sizeof (LITTLENUM_TYPE);
2152 for (i = prec - 1; i >= 0; i--)
2154 md_number_to_chars (litP, (valueT) words[i],
2155 sizeof (LITTLENUM_TYPE));
2156 litP += sizeof (LITTLENUM_TYPE);
2164 m32r_elf_section_change_hook ()
2166 /* If we have reached the end of a section and we have just emitted a
2167 16 bit insn, then emit a nop to make sure that the section ends on
2168 a 32 bit boundary. */
2170 if (prev_insn.insn || seen_relaxable_p)
2171 (void) m32r_fill_insn (0);
2174 /* Return true if can adjust the reloc to be relative to its section
2175 (such as .data) instead of relative to some symbol. */
2178 m32r_fix_adjustable (fixP)
2181 bfd_reloc_code_real_type reloc_type;
2183 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
2185 const CGEN_INSN *insn = NULL;
2186 int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
2187 const CGEN_OPERAND *operand =
2188 cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
2189 reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
2192 reloc_type = fixP->fx_r_type;
2194 /* We need the symbol name for the VTABLE entries. */
2195 if (reloc_type == BFD_RELOC_VTABLE_INHERIT
2196 || reloc_type == BFD_RELOC_VTABLE_ENTRY)
2203 m32r_elf_final_processing ()
2206 m32r_flags |= E_M32R_HAS_PARALLEL;
2207 elf_elfheader (stdoutput)->e_flags |= m32r_flags;