1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 /* Linked list of symbols that are debugging symbols to be defined as the
30 beginning of the current instruction. */
31 typedef struct sym_link
33 struct sym_link *next;
37 static sym_linkS *debug_sym_link = (sym_linkS *)0;
39 /* Structure to hold all of the different components describing an individual instruction. */
42 const CGEN_INSN * insn;
43 const CGEN_INSN * orig_insn;
46 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
48 char buffer [CGEN_MAX_INSN_SIZE];
53 fixS * fixups [CGEN_MAX_FIXUPS];
54 int indices [MAX_OPERAND_INSTANCES];
55 sym_linkS *debug_sym_link;
59 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
60 boundary (i.e. was the first of two 16 bit insns). */
61 static m32r_insn prev_insn;
63 /* Non-zero if we've seen a relaxable insn since the last 32 bit
65 static int seen_relaxable_p = 0;
67 /* Non-zero if -relax specified, in which case sufficient relocs are output
68 for the linker to do relaxing.
69 We do simple forms of relaxing internally, but they are always done.
70 This flag does not apply to them. */
71 static int m32r_relax;
73 /* If non-NULL, pointer to cpu description file to read.
74 This allows runtime additions to the assembler. */
75 static char * m32r_cpu_desc;
77 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
78 Each high/shigh reloc must be paired with it's low cousin in order to
79 properly calculate the addend in a relocatable link (since there is a
80 potential carry from the low to the high/shigh).
81 This option is off by default though for user-written assembler code it
82 might make sense to make the default be on (i.e. have gcc pass a flag
83 to turn it off). This warning must not be on for GCC created code as
84 optimization may delete the low but not the high/shigh (at least we
85 shouldn't assume or require it to). */
86 static int warn_unmatched_high = 0;
88 /* start-sanitize-m32rx */
89 /* Non-zero if --m32rx has been specified, in which case support for the
90 extended M32RX instruction set should be enabled. */
91 static int enable_m32rx = 0;
93 /* Non-zero if --enable-special has been specified, in which case support for
94 the special M32RX instruction set should be enabled. */
95 static int enable_special = 0;
97 /* Non-zero if the programmer should be warned when an explicit parallel
98 instruction might have constraint violations. */
99 static int warn_explicit_parallel_conflicts = 1;
101 /* Non-zero if insns can be made parallel. */
103 /* end-sanitize-m32rx */
105 /* stuff for .scomm symbols. */
106 static segT sbss_section;
107 static asection scom_section;
108 static asymbol scom_symbol;
110 const char comment_chars[] = ";";
111 const char line_comment_chars[] = "#";
112 const char line_separator_chars[] = "";
113 const char EXP_CHARS[] = "eE";
114 const char FLT_CHARS[] = "dD";
116 /* Relocations against symbols are done in two
117 parts, with a HI relocation and a LO relocation. Each relocation
118 has only 16 bits of space to store an addend. This means that in
119 order for the linker to handle carries correctly, it must be able
120 to locate both the HI and the LO relocation. This means that the
121 relocations must appear in order in the relocation table.
123 In order to implement this, we keep track of each unmatched HI
124 relocation. We then sort them so that they immediately precede the
125 corresponding LO relocation. */
129 struct m32r_hi_fixup * next; /* Next HI fixup. */
130 fixS * fixp; /* This fixup. */
131 segT seg; /* The section this fixup is in. */
135 /* The list of unmatched HI relocs. */
137 static struct m32r_hi_fixup * m32r_hi_fixup_list;
140 /* start-sanitize-m32rx */
147 if (stdoutput != NULL)
148 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
149 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
151 /* end-sanitize-m32rx */
153 #define M32R_SHORTOPTS ""
154 /* start-sanitize-m32rx */
155 #undef M32R_SHORTOPTS
156 #define M32R_SHORTOPTS "O"
157 /* end-sanitize-m32rx */
158 const char * md_shortopts = M32R_SHORTOPTS;
160 struct option md_longopts[] =
162 /* start-sanitize-m32rx */
163 #define OPTION_M32RX (OPTION_MD_BASE)
164 {"m32rx", no_argument, NULL, OPTION_M32RX},
165 #define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
166 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
167 {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
168 #define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2)
169 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
170 {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
171 #define OPTION_SPECIAL (OPTION_MD_BASE + 3)
172 {"enable-special", no_argument, NULL, OPTION_SPECIAL},
173 /* end-sanitize-m32rx */
175 /* Sigh. I guess all warnings must now have both variants. */
176 #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
177 {"warn-unmatched-high", OPTION_WARN_UNMATCHED},
178 {"Wuh", OPTION_WARN_UNMATCHED},
179 #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
180 {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED},
181 {"Wnuh", OPTION_WARN_UNMATCHED},
183 #if 0 /* not supported yet */
184 #define OPTION_RELAX (OPTION_MD_BASE + 6)
185 {"relax", no_argument, NULL, OPTION_RELAX},
186 #define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
187 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
190 {NULL, no_argument, NULL, 0}
192 size_t md_longopts_size = sizeof (md_longopts);
195 md_parse_option (c, arg)
201 /* start-sanitize-m32rx */
210 case OPTION_WARN_PARALLEL:
211 warn_explicit_parallel_conflicts = 1;
214 case OPTION_NO_WARN_PARALLEL:
215 warn_explicit_parallel_conflicts = 0;
222 /* end-sanitize-m32rx */
224 case OPTION_WARN_UNMATCHED:
225 warn_unmatched_high = 1;
228 case OPTION_NO_WARN_UNMATCHED:
229 warn_unmatched_high = 0;
232 #if 0 /* not supported yet */
236 case OPTION_CPU_DESC:
248 md_show_usage (stream)
251 fprintf (stream, _("M32R specific command line options:\n"));
253 /* start-sanitize-m32rx */
254 fprintf (stream, _("\
255 --m32rx support the extended m32rx instruction set\n"));
256 fprintf (stream, _("\
257 --enable-special support the special m32rx instructions\n"));
259 fprintf (stream, _("\
260 -O try to combine instructions in parallel\n"));
262 fprintf (stream, _("\
263 --warn-explicit-parallel-conflicts warn when parallel instrucitons violate contraints\n"));
264 fprintf (stream, _("\
265 --no-warn-explicit-parallel-conflicts do not warn when parallel instrucitons violate contraints\n"));
266 fprintf (stream, _("\
267 --Wp synonym for --warn-explicit-parallel-conflicts\n"));
268 fprintf (stream, _("\
269 --Wnp synonym for --no-warn-explicit-parallel-conflicts\n"));
270 /* end-sanitize-m32rx */
272 fprintf (stream, _("\
273 --warn-unmatched-high warn when a high or shigh reloc has no matching low reloc\n"));
274 fprintf (stream, _("\
275 --no-warn-unmatched-high do not warn when a high or shigh reloc has no matching low reloc\n"));
276 fprintf (stream, _("\
277 --Wuh synonym for --warn-unmatched-high\n"));
278 fprintf (stream, _("\
279 --Wnuh synonym for --no-warn-unmatched-high\n"));
282 fprintf (stream, _("\
283 --relax create linker relaxable code\n"));
284 fprintf (stream, _("\
285 --cpu-desc provide runtime cpu description file\n"));
289 static void fill_insn PARAMS ((int));
290 static void m32r_scomm PARAMS ((int));
291 static void debug_sym PARAMS ((int));
292 static void expand_debug_syms PARAMS ((sym_linkS *, int));
294 /* Set by md_assemble for use by m32r_fill_insn. */
295 static subsegT prev_subseg;
296 static segT prev_seg;
298 /* The target specific pseudo-ops which we support. */
299 const pseudo_typeS md_pseudo_table[] =
302 { "fillinsn", fill_insn, 0 },
303 { "scomm", m32r_scomm, 0 },
304 { "debugsym", debug_sym, 0 },
305 /* start-sanitize-m32rx */
306 { "m32r", allow_m32rx, 0 },
307 { "m32rx", allow_m32rx, 1 },
308 /* end-sanitize-m32rx */
312 /* FIXME: Should be machine generated. */
313 #define NOP_INSN 0x7000
314 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
316 /* When we align the .text section, insert the correct NOP pattern.
317 N is the power of 2 alignment. LEN is the length of pattern FILL.
318 MAX is the maximum number of characters to skip when doing the alignment,
319 or 0 if there is no maximum. */
322 m32r_do_align (n, fill, len, max)
328 if ((fill == NULL || (* fill == 0 && len == 1))
329 && (now_seg->flags & SEC_CODE) != 0
330 /* Only do this special handling if aligning to at least a
333 /* Only do this special handling if we're allowed to emit at
335 && (max == 0 || max > 1))
337 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
340 /* First align to a 2 byte boundary, in case there is an odd .byte. */
341 /* FIXME: How much memory will cause gas to use when assembling a big
342 program? Perhaps we can avoid the frag_align call? */
343 frag_align (1, 0, 0);
345 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
347 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
348 /* If doing larger alignments use a repeating sequence of appropriate
352 static const unsigned char multi_nop_pattern[] =
353 { 0x70, 0x00, 0xf0, 0x00 };
354 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
364 assemble_nop (opcode)
367 char * f = frag_more (2);
368 md_number_to_chars (f, opcode, 2);
371 /* If the last instruction was the first of 2 16 bit insns,
372 output a nop to move the PC to a 32 bit boundary.
374 This is done via an alignment specification since branch relaxing
375 may make it unnecessary.
377 Internally, we need to output one of these each time a 32 bit insn is
378 seen after an insn that is relaxable. */
384 (void) m32r_do_align (2, NULL, 0, 0);
385 prev_insn.insn = NULL;
386 seen_relaxable_p = 0;
389 /* Record the symbol so that when we output the insn, we can create
390 a symbol that is at the start of the instruction. This is used
391 to emit the label for the start of a breakpoint without causing
392 the assembler to emit a NOP if the previous instruction was a
393 16 bit instruction. */
401 register char *end_name;
402 register symbolS *symbolP;
403 register sym_linkS *link;
405 name = input_line_pointer;
406 delim = get_symbol_end ();
407 end_name = input_line_pointer;
409 if ((symbolP = symbol_find (name)) == NULL
410 && (symbolP = md_undefined_symbol (name)) == NULL)
412 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
415 symbol_table_insert (symbolP);
416 if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section)
417 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
421 link = (sym_linkS *) xmalloc (sizeof (sym_linkS));
422 link->symbol = symbolP;
423 link->next = debug_sym_link;
424 debug_sym_link = link;
429 demand_empty_rest_of_line ();
432 /* Second pass to expanding the debug symbols, go through linked
433 list of symbols and reassign the address. */
436 expand_debug_syms (syms, align)
440 char *save_input_line = input_line_pointer;
441 sym_linkS *next_syms;
447 (void) m32r_do_align (align, NULL, 0, 0);
448 for (; syms != (sym_linkS *)0; syms = next_syms)
450 symbolS *symbolP = syms->symbol;
451 next_syms = syms->next;
452 input_line_pointer = ".\n";
453 pseudo_set (symbolP);
457 input_line_pointer = save_input_line;
460 /* Cover function to fill_insn called after a label and at end of assembly.
462 The result is always 1: we're called in a conditional to see if the
463 current line is a label. */
466 m32r_fill_insn (done)
469 if (prev_seg != NULL)
472 subsegT subseg = now_subseg;
474 subseg_set (prev_seg, prev_subseg);
478 subseg_set (seg, subseg);
491 /* Initialize the `cgen' interface. */
493 /* This is a callback from cgen to gas to parse operands. */
494 cgen_parse_operand_fn = cgen_parse_operand;
496 /* Set the machine number and endian. */
497 CGEN_SYM (init_asm) (0 /* mach number */,
499 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
501 #if 0 /* not supported yet */
502 /* If a runtime cpu description file was provided, parse it. */
503 if (m32r_cpu_desc != NULL)
507 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
509 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
513 /* Save the current subseg so we can restore it [it's the default one and
514 we don't want the initial section to be .sbss]. */
518 /* The sbss section is for local .scomm symbols. */
519 sbss_section = subseg_new (".sbss", 0);
521 /* This is copied from perform_an_assembly_pass. */
522 applicable = bfd_applicable_section_flags (stdoutput);
523 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
525 #if 0 /* What does this do? [see perform_an_assembly_pass] */
526 seg_info (bss_section)->bss = 1;
529 subseg_set (seg, subseg);
531 /* We must construct a fake section similar to bfd_com_section
532 but with the name .scommon. */
533 scom_section = bfd_com_section;
534 scom_section.name = ".scommon";
535 scom_section.output_section = & scom_section;
536 scom_section.symbol = & scom_symbol;
537 scom_section.symbol_ptr_ptr = & scom_section.symbol;
538 scom_symbol = * bfd_com_section.symbol;
539 scom_symbol.name = ".scommon";
540 scom_symbol.section = & scom_section;
542 /* start-sanitize-m32rx */
543 allow_m32rx (enable_m32rx);
544 /* end-sanitize-m32rx */
547 /* start-sanitize-m32rx */
549 #define OPERAND_IS_COND_BIT(operand, indices, index) \
550 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
551 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
552 && (indices [index] == 0 || indices [index] == 1)))
554 /* Returns true if an output of instruction 'a' is referenced by an operand
555 of instruction 'b'. If 'check_outputs' is true then b's outputs are
556 checked, otherwise its inputs are examined. */
559 first_writes_to_seconds_operands (a, b, check_outputs)
562 const int check_outputs;
564 const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn);
565 const CGEN_OPERAND_INSTANCE * b_ops = CGEN_INSN_OPERANDS (b->insn);
568 /* If at least one of the instructions takes no operands, then there is
569 nothing to check. There really are instructions without operands,
571 if (a_operands == NULL || b_ops == NULL)
574 /* Scan the operand list of 'a' looking for an output operand. */
576 CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
577 a_index ++, a_operands ++)
579 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT)
582 const CGEN_OPERAND_INSTANCE * b_operands = b_ops;
585 The Condition bit 'C' is a shadow of the CBR register (control
586 register 1) and also a shadow of bit 31 of the program status
587 word (control register 0). For now this is handled here, rather
590 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
592 /* Scan operand list of 'b' looking for another reference to the
593 condition bit, which goes in the right direction. */
595 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
596 b_index ++, b_operands ++)
598 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
599 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
600 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
606 /* Scan operand list of 'b' looking for an operand that references
607 the same hardware element, and which goes in the right direction. */
609 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
610 b_index ++, b_operands ++)
612 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
613 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
614 && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands))
615 && (a->indices [a_index] == b->indices [b_index]))
625 /* Returns true if the insn can (potentially) alter the program counter. */
631 #if 0 /* Once PC operands are working.... */
632 const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn);
634 if (a_operands == NULL)
637 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END)
639 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL
640 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
646 if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
647 || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
653 /* Returns NULL if the two 16 bit insns can be executed in parallel,
654 otherwise it returns a pointer to an error message explaining why not. */
657 can_make_parallel (a, b)
664 /* Make sure the instructions are the right length. */
665 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
666 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
669 if (first_writes_to_seconds_operands (a, b, true))
670 return _("Instructions write to the same destination register.");
672 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
673 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
675 /* Make sure that the instructions use the correct execution pipelines. */
676 if ( a_pipe == PIPE_NONE
677 || b_pipe == PIPE_NONE)
678 return _("Instructions do not use parallel execution pipelines.");
680 /* Leave this test for last, since it is the only test that can
681 go away if the instructions are swapped, and we want to make
682 sure that any other errors are detected before this happens. */
683 if ( a_pipe == PIPE_S
685 return _("Instructions share the same execution pipeline");
693 make_parallel (buffer)
694 cgen_insn_t * buffer;
696 /* Force the top bit of the second insn to be set. */
700 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
702 value = bfd_getb16 ((bfd_byte *) buffer);
704 bfd_putb16 (value, (char *) buffer);
708 value = bfd_getl16 ((bfd_byte *) buffer);
710 bfd_putl16 (value, (char *) buffer);
717 make_parallel (buffer)
720 /* Force the top bit of the second insn to be set. */
722 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
725 #endif /* ! CGEN_INT_INSN */
728 assemble_parallel_insn (str, str2)
737 * str2 = 0; /* Seperate the two instructions. */
739 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
740 so that the parallel instruction will start on a 32 bit boundary. */
744 first.debug_sym_link = debug_sym_link;
745 debug_sym_link = (sym_linkS *)0;
747 /* Parse the first instruction. */
748 if (! (first.insn = CGEN_SYM (assemble_insn)
749 (str, & first.fields, first.buffer, & errmsg)))
756 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_SPECIAL))
758 /* xgettext:c-format */
759 as_bad (_("unknown instruction '%s'"), str);
762 else if (! enable_m32rx
763 /* FIXME: Need standard macro to perform this test. */
764 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
766 /* xgettext:c-format */
767 as_bad (_("instruction '%s' is for the M32RX only"), str);
771 /* Check to see if this is an allowable parallel insn. */
772 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
774 as_bad (_("instruction '%s' cannot be executed in parallel."), str);
778 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
779 str3 = str; /* Save the original string pointer. */
780 str = str2 + 2; /* Advanced past the parsed string. */
781 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
783 /* Preserve any fixups that have been generated and reset the list to empty. */
786 /* Get the indices of the operands of the instruction. */
787 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
788 doesn't seem right. Perhaps allow passing fields like we do insn. */
789 /* FIXME: ALIAS insns do not have operands, so we use this function
790 to find the equivalent insn and overwrite the value stored in our
791 structure. We still need the original insn, however, since this
792 may have certain attributes that are not present in the unaliased
793 version (eg relaxability). When aliases behave differently this
794 may have to change. */
795 first.orig_insn = first.insn;
796 first.insn = m32r_cgen_lookup_get_insn_operands (NULL,
797 bfd_getb16 ((char *) first.buffer),
800 if (first.insn == NULL)
801 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for first insn"));
803 second.debug_sym_link = NULL;
805 /* Parse the second instruction. */
806 if (! (second.insn = CGEN_SYM (assemble_insn)
807 (str, & second.fields, second.buffer, & errmsg)))
815 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_SPECIAL))
817 /* xgettext:c-format */
818 as_bad (_("unknown instruction '%s'"), str);
821 else if (! enable_m32rx
822 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
824 /* xgettext:c-format */
825 as_bad (_("instruction '%s' is for the M32RX only"), str);
829 /* Check to see if this is an allowable parallel insn. */
830 if (CGEN_INSN_ATTR (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
832 as_bad (_("instruction '%s' cannot be executed in parallel."), str);
838 if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
839 && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
841 /* xgettext:c-format */
842 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
847 /* Get the indices of the operands of the instruction. */
848 second.orig_insn = second.insn;
849 second.insn = m32r_cgen_lookup_get_insn_operands (NULL,
850 bfd_getb16 ((char *) second.buffer),
853 if (second.insn == NULL)
854 as_fatal (_("internal error: m32r_cgen_lookup_get_insn_operands failed for second insn"));
856 /* We assume that if the first instruction writes to a register that is
857 read by the second instruction it is because the programmer intended
858 this to happen, (after all they have explicitly requested that these
859 two instructions be executed in parallel). Although if the global
860 variable warn_explicit_parallel_conflicts is true then we do generate
861 a warning message. Similarly we assume that parallel branch and jump
862 instructions are deliberate and should not produce errors. */
864 if (warn_explicit_parallel_conflicts)
866 if (first_writes_to_seconds_operands (& first, & second, false))
867 /* xgettext:c-format */
868 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
870 if (first_writes_to_seconds_operands (& second, & first, false))
871 /* xgettext:c-format */
872 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
875 if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
877 /* Get the fixups for the first instruction. */
881 expand_debug_syms (first.debug_sym_link, 1);
882 cgen_asm_finish_insn (first.orig_insn, first.buffer,
883 CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
885 /* Force the top bit of the second insn to be set. */
886 make_parallel (second.buffer);
888 /* Get its fixups. */
889 cgen_restore_fixups ();
892 expand_debug_syms (second.debug_sym_link, 1);
893 cgen_asm_finish_insn (second.orig_insn, second.buffer,
894 CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
896 /* Try swapping the instructions to see if they work that way. */
897 else if (can_make_parallel (& second, & first) == NULL)
899 /* Write out the second instruction first. */
900 expand_debug_syms (second.debug_sym_link, 1);
901 cgen_asm_finish_insn (second.orig_insn, second.buffer,
902 CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
904 /* Force the top bit of the first instruction to be set. */
905 make_parallel (first.buffer);
907 /* Get the fixups for the first instruction. */
908 cgen_restore_fixups ();
910 /* Write out the first instruction. */
911 expand_debug_syms (first.debug_sym_link, 1);
912 cgen_asm_finish_insn (first.orig_insn, first.buffer,
913 CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
917 as_bad ("'%s': %s", str2, errmsg);
921 /* Set these so m32r_fill_insn can use them. */
923 prev_subseg = now_subseg;
926 /* end-sanitize-m32rx */
937 /* Initialize GAS's cgen interface for a new instruction. */
938 cgen_asm_init_parse ();
940 /* start-sanitize-m32rx */
941 /* Look for a parallel instruction seperator. */
942 if ((str2 = strstr (str, "||")) != NULL)
944 assemble_parallel_insn (str, str2);
947 /* end-sanitize-m32rx */
949 insn.debug_sym_link = debug_sym_link;
950 debug_sym_link = (sym_linkS *)0;
952 insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
959 /* start-sanitize-m32rx */
961 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_SPECIAL))
963 /* xgettext:c-format */
964 as_bad (_("unknown instruction '%s'"), str);
967 else if (! enable_m32rx
968 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
970 /* xgettext:c-format */
971 as_bad (_("instruction '%s' is for the M32RX only"), str);
974 /* end-sanitize-m32rx */
976 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
978 /* 32 bit insns must live on 32 bit boundaries. */
979 if (prev_insn.insn || seen_relaxable_p)
981 /* ??? If calling fill_insn too many times turns us into a memory
982 pig, can we call assemble_nop instead of !seen_relaxable_p? */
986 expand_debug_syms (insn.debug_sym_link, 2);
988 /* Doesn't really matter what we pass for RELAX_P here. */
989 cgen_asm_finish_insn (insn.insn, insn.buffer,
990 CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
994 int on_32bit_boundary_p;
995 /* start-sanitize-m32rx */
997 /* end-sanitize-m32rx */
999 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
1002 insn.orig_insn = insn.insn;
1003 /* start-sanitize-m32rx */
1006 /* Get the indices of the operands of the instruction.
1007 FIXME: See assemble_parallel for notes on orig_insn. */
1008 insn.insn = m32r_cgen_lookup_get_insn_operands (NULL,
1009 bfd_getb16 ((char *) insn.buffer),
1012 if (insn.insn == NULL)
1013 as_fatal (_("internal error: m32r_cgen_get_insn_operands failed"));
1015 /* end-sanitize-m32rx */
1017 /* Compute whether we're on a 32 bit boundary or not.
1018 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1019 on_32bit_boundary_p = prev_insn.insn == NULL;
1021 /* start-sanitize-m32rx */
1022 /* Look to see if this instruction can be combined with the
1023 previous instruction to make one, parallel, 32 bit instruction.
1024 If the previous instruction (potentially) changed the flow of
1025 program control, then it cannot be combined with the current
1026 instruction. If the current instruction is relaxable, then it
1027 might be replaced with a longer version, so we cannot combine it.
1028 Also if the output of the previous instruction is used as an
1029 input to the current instruction then it cannot be combined.
1030 Otherwise call can_make_parallel() with both orderings of the
1031 instructions to see if they can be combined. */
1032 if ( ! on_32bit_boundary_p
1035 && CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
1036 && ! writes_to_pc (& prev_insn)
1037 && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
1040 if (can_make_parallel (& prev_insn, & insn) == NULL)
1041 make_parallel (insn.buffer);
1042 else if (can_make_parallel (& insn, & prev_insn) == NULL)
1045 /* end-sanitize-m32rx */
1047 expand_debug_syms (insn.debug_sym_link, 1);
1053 /* Ensure each pair of 16 bit insns is in the same frag. */
1056 cgen_asm_finish_insn (insn.orig_insn, insn.buffer,
1057 CGEN_FIELDS_BITSIZE (& insn.fields),
1058 1 /*relax_p*/, &fi);
1059 insn.addr = fi.addr;
1060 insn.frag = fi.frag;
1061 insn.num_fixups = fi.num_fixups;
1062 for (i = 0; i < fi.num_fixups; ++i)
1063 insn.fixups[i] = fi.fixups[i];
1066 /* start-sanitize-m32rx */
1071 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1073 /* Swap the two insns */
1074 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
1075 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
1077 make_parallel (insn.addr);
1079 /* Swap any relaxable frags recorded for the two insns. */
1080 /* FIXME: Clarify. relaxation precludes parallel insns */
1081 if (prev_insn.frag->fr_opcode == prev_insn.addr)
1082 prev_insn.frag->fr_opcode = insn.addr;
1083 else if (insn.frag->fr_opcode == insn.addr)
1084 insn.frag->fr_opcode = prev_insn.addr;
1086 /* Update the addresses in any fixups.
1087 Note that we don't have to handle the case where each insn is in
1088 a different frag as we ensure they're in the same frag above. */
1089 for (i = 0; i < prev_insn.num_fixups; ++i)
1090 prev_insn.fixups[i]->fx_where += 2;
1091 for (i = 0; i < insn.num_fixups; ++i)
1092 insn.fixups[i]->fx_where -= 2;
1094 /* end-sanitize-m32rx */
1096 /* Keep track of whether we've seen a pair of 16 bit insns.
1097 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1098 if (on_32bit_boundary_p)
1101 prev_insn.insn = NULL;
1103 /* If the insn needs the following one to be on a 32 bit boundary
1104 (e.g. subroutine calls), fill this insn's slot. */
1105 if (on_32bit_boundary_p
1106 && CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
1109 /* If this is a relaxable insn (can be replaced with a larger version)
1110 mark the fact so that we can emit an alignment directive for a
1111 following 32 bit insn if we see one. */
1112 if (CGEN_INSN_ATTR (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
1113 seen_relaxable_p = 1;
1116 /* Set these so m32r_fill_insn can use them. */
1118 prev_subseg = now_subseg;
1121 /* The syntax in the manual says constants begin with '#'.
1122 We just ignore it. */
1125 md_operand (expressionP)
1126 expressionS * expressionP;
1128 if (* input_line_pointer == '#')
1130 input_line_pointer ++;
1131 expression (expressionP);
1136 md_section_align (segment, size)
1140 int align = bfd_get_section_alignment (stdoutput, segment);
1141 return ((size + (1 << align) - 1) & (-1 << align));
1145 md_undefined_symbol (name)
1151 /* .scomm pseudo-op handler.
1153 This is a new pseudo-op to handle putting objects in .scommon.
1154 By doing this the linker won't need to do any work and more importantly
1155 it removes the implicit -G arg necessary to correctly link the object file.
1162 register char * name;
1166 register symbolS * symbolP;
1170 name = input_line_pointer;
1171 c = get_symbol_end ();
1173 /* just after name is now '\0' */
1174 p = input_line_pointer;
1177 if (* input_line_pointer != ',')
1179 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1180 ignore_rest_of_line ();
1184 input_line_pointer ++; /* skip ',' */
1185 if ((size = get_absolute_expression ()) < 0)
1187 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
1188 ignore_rest_of_line ();
1192 /* The third argument to .scomm is the alignment. */
1193 if (* input_line_pointer != ',')
1197 ++ input_line_pointer;
1198 align = get_absolute_expression ();
1201 as_warn (_("ignoring bad alignment"));
1205 /* Convert to a power of 2 alignment. */
1208 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
1212 as_bad (_("Common alignment not a power of 2"));
1213 ignore_rest_of_line ();
1221 symbolP = symbol_find_or_make (name);
1224 if (S_IS_DEFINED (symbolP))
1226 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1227 S_GET_NAME (symbolP));
1228 ignore_rest_of_line ();
1232 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
1234 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1235 S_GET_NAME (symbolP),
1236 (long) S_GET_VALUE (symbolP),
1239 ignore_rest_of_line ();
1245 segT old_sec = now_seg;
1246 int old_subsec = now_subseg;
1249 record_alignment (sbss_section, align2);
1250 subseg_set (sbss_section, 0);
1253 frag_align (align2, 0, 0);
1255 if (S_GET_SEGMENT (symbolP) == sbss_section)
1256 symbolP->sy_frag->fr_symbol = 0;
1258 symbolP->sy_frag = frag_now;
1260 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
1263 S_SET_SIZE (symbolP, size);
1264 S_SET_SEGMENT (symbolP, sbss_section);
1265 S_CLEAR_EXTERNAL (symbolP);
1266 subseg_set (old_sec, old_subsec);
1270 S_SET_VALUE (symbolP, (valueT) size);
1271 S_SET_ALIGN (symbolP, align2);
1272 S_SET_EXTERNAL (symbolP);
1273 S_SET_SEGMENT (symbolP, & scom_section);
1276 demand_empty_rest_of_line ();
1279 /* Interface to relax_segment. */
1281 /* FIXME: Build table by hand, get it working, then machine generate. */
1283 const relax_typeS md_relax_table[] =
1286 1) most positive reach of this state,
1287 2) most negative reach of this state,
1288 3) how many bytes this mode will add to the size of the current frag
1289 4) which index into the table to try if we can't fit into this one. */
1291 /* The first entry must be unused because an `rlx_more' value of zero ends
1295 /* The displacement used by GAS is from the end of the 2 byte insn,
1296 so we subtract 2 from the following. */
1297 /* 16 bit insn, 8 bit disp -> 10 bit range.
1298 This doesn't handle a branch in the right slot at the border:
1299 the "& -4" isn't taken into account. It's not important enough to
1300 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1302 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1303 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1304 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1305 /* Same thing, but with leading nop for alignment. */
1306 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1310 m32r_relax_frag (fragP, stretch)
1314 /* Address of branch insn. */
1315 long address = fragP->fr_address + fragP->fr_fix - 2;
1318 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1319 if (fragP->fr_subtype == 2)
1321 if ((address & 3) != 0)
1323 fragP->fr_subtype = 3;
1327 else if (fragP->fr_subtype == 3)
1329 if ((address & 3) == 0)
1331 fragP->fr_subtype = 2;
1337 growth = relax_frag (fragP, stretch);
1339 /* Long jump on odd halfword boundary? */
1340 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1342 fragP->fr_subtype = 3;
1350 /* Return an initial guess of the length by which a fragment must grow to
1351 hold a branch to reach its destination.
1352 Also updates fr_type/fr_subtype as necessary.
1354 Called just before doing relaxation.
1355 Any symbol that is now undefined will not become defined.
1356 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1357 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1358 Although it may not be explicit in the frag, pretend fr_var starts with a
1362 md_estimate_size_before_relax (fragP, segment)
1366 int old_fr_fix = fragP->fr_fix;
1367 char * opcode = fragP->fr_opcode;
1369 /* The only thing we have to handle here are symbols outside of the
1370 current segment. They may be undefined or in a different segment in
1371 which case linker scripts may place them anywhere.
1372 However, we can't finish the fragment here and emit the reloc as insn
1373 alignment requirements may move the insn about. */
1375 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1377 /* The symbol is undefined in this segment.
1378 Change the relaxation subtype to the max allowable and leave
1379 all further handling to md_convert_frag. */
1380 fragP->fr_subtype = 2;
1382 #if 0 /* Can't use this, but leave in for illustration. */
1383 /* Change 16 bit insn to 32 bit insn. */
1386 /* Increase known (fixed) size of fragment. */
1389 /* Create a relocation for it. */
1390 fix_new (fragP, old_fr_fix, 4,
1392 fragP->fr_offset, 1 /* pcrel */,
1393 /* FIXME: Can't use a real BFD reloc here.
1394 cgen_md_apply_fix3 can't handle it. */
1395 BFD_RELOC_M32R_26_PCREL);
1397 /* Mark this fragment as finished. */
1401 const CGEN_INSN * insn;
1404 /* Update the recorded insn.
1405 Fortunately we don't have to look very far.
1406 FIXME: Change this to record in the instruction the next higher
1407 relaxable insn to use. */
1408 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1410 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1411 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1413 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1419 fragP->fr_cgen.insn = insn;
1425 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1428 /* *fragP has been relaxed to its final size, and now needs to have
1429 the bytes inside it modified to conform to the new size.
1431 Called after relaxation is finished.
1432 fragP->fr_type == rs_machine_dependent.
1433 fragP->fr_subtype is the subtype of what the address relaxed to. */
1436 md_convert_frag (abfd, sec, fragP)
1442 char * displacement;
1448 opcode = fragP->fr_opcode;
1450 /* Address opcode resides at in file space. */
1451 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1453 switch (fragP->fr_subtype)
1457 displacement = & opcode[1];
1462 displacement = & opcode[1];
1465 opcode[2] = opcode[0] | 0x80;
1466 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1467 opcode_address += 2;
1469 displacement = & opcode[3];
1475 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1477 /* symbol must be resolved by linker */
1478 if (fragP->fr_offset & 3)
1479 as_warn (_("Addend to unresolved symbol not on word boundary."));
1480 addend = fragP->fr_offset >> 2;
1484 /* Address we want to reach in file space. */
1485 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1486 target_address += fragP->fr_symbol->sy_frag->fr_address;
1487 addend = (target_address - (opcode_address & -4)) >> 2;
1490 /* Create a relocation for symbols that must be resolved by the linker.
1491 Otherwise output the completed insn. */
1493 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1495 assert (fragP->fr_subtype != 1);
1496 assert (fragP->fr_cgen.insn != 0);
1497 cgen_record_fixup (fragP,
1498 /* Offset of branch insn in frag. */
1499 fragP->fr_fix + extension - 4,
1500 fragP->fr_cgen.insn,
1502 /* FIXME: quick hack */
1504 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1506 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1508 fragP->fr_cgen.opinfo,
1509 fragP->fr_symbol, fragP->fr_offset);
1512 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1514 md_number_to_chars (displacement, (valueT) addend,
1515 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1517 fragP->fr_fix += extension;
1520 /* Functions concerning relocs. */
1522 /* The location from which a PC relative jump should be calculated,
1523 given a PC relative reloc. */
1526 md_pcrel_from_section (fixP, sec)
1530 if (fixP->fx_addsy != (symbolS *) NULL
1531 && (! S_IS_DEFINED (fixP->fx_addsy)
1532 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1534 /* The symbol is undefined (or is defined but not in this section).
1535 Let the linker figure it out. */
1539 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1542 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1543 Returns BFD_RELOC_NONE if no reloc type can be found.
1544 *FIXP may be modified if desired. */
1546 bfd_reloc_code_real_type
1547 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1548 const CGEN_INSN * insn;
1549 const CGEN_OPERAND * operand;
1552 switch (CGEN_OPERAND_TYPE (operand))
1554 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1555 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1556 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1557 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1558 case M32R_OPERAND_HI16 :
1559 case M32R_OPERAND_SLO16 :
1560 case M32R_OPERAND_ULO16 :
1561 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1562 if (fixP->tc_fix_data.opinfo != 0)
1563 return fixP->tc_fix_data.opinfo;
1566 return BFD_RELOC_NONE;
1569 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1572 m32r_record_hi16 (reloc_type, fixP, seg)
1577 struct m32r_hi_fixup * hi_fixup;
1579 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1580 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1582 hi_fixup = ((struct m32r_hi_fixup *)
1583 xmalloc (sizeof (struct m32r_hi_fixup)));
1584 hi_fixup->fixp = fixP;
1585 hi_fixup->seg = now_seg;
1586 hi_fixup->next = m32r_hi_fixup_list;
1588 m32r_hi_fixup_list = hi_fixup;
1591 /* Called while parsing an instruction to create a fixup.
1592 We need to check for HI16 relocs and queue them up for later sorting. */
1595 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1598 const CGEN_INSN * insn;
1600 const CGEN_OPERAND * operand;
1604 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1605 operand, opinfo, exp);
1607 switch (CGEN_OPERAND_TYPE (operand))
1609 case M32R_OPERAND_HI16 :
1610 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1611 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1612 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1613 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1620 /* Return BFD reloc type from opinfo field in a fixS.
1621 It's tricky using fx_r_type in m32r_frob_file because the values
1622 are BFD_RELOC_UNUSED + operand number. */
1623 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1625 /* Sort any unmatched HI16 relocs so that they immediately precede
1626 the corresponding LO16 reloc. This is called before md_apply_fix and
1632 struct m32r_hi_fixup * l;
1634 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1636 segment_info_type * seginfo;
1639 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1640 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1642 /* Check quickly whether the next fixup happens to be a matching low. */
1643 if (l->fixp->fx_next != NULL
1644 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1645 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1646 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1649 /* Look through the fixups for this segment for a matching `low'.
1650 When we find one, move the high/shigh just in front of it. We do
1651 this in two passes. In the first pass, we try to find a
1652 unique `low'. In the second pass, we permit multiple high's
1653 relocs for a single `low'. */
1654 seginfo = seg_info (l->seg);
1655 for (pass = 0; pass < 2; pass++)
1661 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1663 /* Check whether this is a `low' fixup which matches l->fixp. */
1664 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1665 && f->fx_addsy == l->fixp->fx_addsy
1666 && f->fx_offset == l->fixp->fx_offset
1669 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1670 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1671 || prev->fx_addsy != f->fx_addsy
1672 || prev->fx_offset != f->fx_offset))
1676 /* Move l->fixp before f. */
1677 for (pf = &seginfo->fix_root;
1679 pf = & (* pf)->fx_next)
1680 assert (* pf != NULL);
1682 * pf = l->fixp->fx_next;
1684 l->fixp->fx_next = f;
1686 seginfo->fix_root = l->fixp;
1688 prev->fx_next = l->fixp;
1700 && warn_unmatched_high)
1701 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1702 _("Unmatched high/shigh reloc"));
1707 /* See whether we need to force a relocation into the output file.
1708 This is used to force out switch and PC relative relocations when
1712 m32r_force_relocation (fix)
1718 return (fix->fx_pcrel
1722 /* Write a value out to the object file, using the appropriate endianness. */
1725 md_number_to_chars (buf, val, n)
1730 if (target_big_endian)
1731 number_to_chars_bigendian (buf, val, n);
1733 number_to_chars_littleendian (buf, val, n);
1736 /* Turn a string in input_line_pointer into a floating point constant of type
1737 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1738 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1741 /* Equal to MAX_PRECISION in atof-ieee.c */
1742 #define MAX_LITTLENUMS 6
1745 md_atof (type, litP, sizeP)
1752 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1753 LITTLENUM_TYPE * wordP;
1755 char * atof_ieee ();
1773 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1777 return _("Bad call to md_atof()");
1780 t = atof_ieee (input_line_pointer, type, words);
1782 input_line_pointer = t;
1783 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1785 if (target_big_endian)
1787 for (i = 0; i < prec; i++)
1789 md_number_to_chars (litP, (valueT) words[i],
1790 sizeof (LITTLENUM_TYPE));
1791 litP += sizeof (LITTLENUM_TYPE);
1796 for (i = prec - 1; i >= 0; i--)
1798 md_number_to_chars (litP, (valueT) words[i],
1799 sizeof (LITTLENUM_TYPE));
1800 litP += sizeof (LITTLENUM_TYPE);
1808 m32r_elf_section_change_hook ()
1810 /* If we have reached the end of a section and we have just emitted a
1811 16 bit insn, then emit a nop to make sure that the section ends on
1812 a 32 bit boundary. */
1814 if (prev_insn.insn || seen_relaxable_p)
1815 (void) m32r_fill_insn (0);