1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 const CGEN_INSN * insn;
32 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
34 char buffer [CGEN_MAX_INSN_SIZE];
41 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
42 boundary (i.e. was the first of two 16 bit insns). */
43 static m32r_insn prev_insn;
45 /* Non-zero if we've seen a relaxable insn since the last 32 bit
47 static int seen_relaxable_p = 0;
49 /* Non-zero if -relax specified, in which case sufficient relocs are output
50 for the linker to do relaxing.
51 We do simple forms of relaxing internally, but they are always done.
52 This flag does not apply to them. */
53 static int m32r_relax;
55 /* If non-NULL, pointer to cpu description file to read.
56 This allows runtime additions to the assembler. */
57 static char * m32r_cpu_desc;
59 /* start-sanitize-m32rx */
60 /* Non-zero if -m32rx has been specified, in which case support for the
61 extended M32RX instruction set should be enabled. */
62 static int enable_m32rx = 0;
64 /* Non-zero if the programmer should be warned when an explicit parallel
65 instruction might have constraint violations. */
66 static int warn_explicit_parallel_conflicts = 1;
67 /* end-sanitize-m32rx */
69 /* stuff for .scomm symbols. */
70 static segT sbss_section;
71 static asection scom_section;
72 static asymbol scom_symbol;
74 const char comment_chars[] = ";";
75 const char line_comment_chars[] = "#";
76 const char line_separator_chars[] = "";
77 const char EXP_CHARS[] = "eE";
78 const char FLT_CHARS[] = "dD";
80 /* Relocations against symbols are done in two
81 parts, with a HI relocation and a LO relocation. Each relocation
82 has only 16 bits of space to store an addend. This means that in
83 order for the linker to handle carries correctly, it must be able
84 to locate both the HI and the LO relocation. This means that the
85 relocations must appear in order in the relocation table.
87 In order to implement this, we keep track of each unmatched HI
88 relocation. We then sort them so that they immediately precede the
89 corresponding LO relocation. */
93 struct m32r_hi_fixup * next; /* Next HI fixup. */
94 fixS * fixp; /* This fixup. */
95 segT seg; /* The section this fixup is in. */
99 /* The list of unmatched HI relocs. */
101 static struct m32r_hi_fixup * m32r_hi_fixup_list;
104 /* start-sanitize-m32rx */
110 if (stdoutput != NULL)
111 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
112 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
114 /* end-sanitize-m32rx */
116 const char * md_shortopts = "";
118 struct option md_longopts[] =
120 /* start-sanitize-m32rx */
121 #define OPTION_M32RX (OPTION_MD_BASE)
122 {"m32rx", no_argument, NULL, OPTION_M32RX},
123 #define OPTION_WARN (OPTION_MD_BASE + 1)
124 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN},
125 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
126 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
127 /* end-sanitize-m32rx */
129 #if 0 /* not supported yet */
130 #define OPTION_RELAX (OPTION_MD_BASE + 3)
131 {"relax", no_argument, NULL, OPTION_RELAX},
132 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
133 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
136 {NULL, no_argument, NULL, 0}
138 size_t md_longopts_size = sizeof (md_longopts);
141 md_parse_option (c, arg)
147 /* start-sanitize-m32rx */
153 warn_explicit_parallel_conflicts = 1;
157 warn_explicit_parallel_conflicts = 0;
159 /* end-sanitize-m32rx */
161 #if 0 /* not supported yet */
165 case OPTION_CPU_DESC:
176 md_show_usage (stream)
179 fprintf (stream, "M32R/X options:\n");
180 /* start-sanitize-m32rx */
182 --m32rx support the extended m32rx instruction set\n");
185 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\
186 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
187 /* end-sanitize-m32rx */
191 --relax create linker relaxable code\n");
193 --cpu-desc provide runtime cpu description file\n");
197 static void fill_insn PARAMS ((int));
198 static void m32r_scomm PARAMS ((int));
200 /* Set by md_assemble for use by m32r_fill_insn. */
201 static subsegT prev_subseg;
202 static segT prev_seg;
204 /* The target specific pseudo-ops which we support. */
205 const pseudo_typeS md_pseudo_table[] =
208 { "fillinsn", fill_insn, 0 },
209 { "scomm", m32r_scomm, 0 },
210 /* start-sanitize-m32rx */
211 { "m32r", allow_m32rx, 0},
212 { "m32rx", allow_m32rx, 1},
213 /* end-sanitize-m32rx */
217 /* FIXME: Should be machine generated. */
218 #define NOP_INSN 0x7000
219 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
221 /* When we align the .text section, insert the correct NOP pattern.
222 N is the power of 2 alignment. LEN is the length of pattern FILL.
223 MAX is the maximum number of characters to skip when doing the alignment,
224 or 0 if there is no maximum. */
227 m32r_do_align (n, fill, len, max)
233 if ((fill == NULL || (* fill == 0 && len == 1))
234 && (now_seg->flags & SEC_CODE) != 0
235 /* Only do this special handling if aligning to at least a
238 /* Only do this special handling if we're allowed to emit at
240 && (max == 0 || max > 1))
242 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
245 /* First align to a 2 byte boundary, in case there is an odd .byte. */
246 /* FIXME: How much memory will cause gas to use when assembling a big
247 program? Perhaps we can avoid the frag_align call? */
248 frag_align (1, 0, 0);
250 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
252 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
253 /* If doing larger alignments use a repeating sequence of appropriate
257 static const unsigned char multi_nop_pattern[] =
258 { 0x70, 0x00, 0xf0, 0x00 };
259 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
269 assemble_nop (opcode)
272 char * f = frag_more (2);
273 md_number_to_chars (f, opcode, 2);
276 /* If the last instruction was the first of 2 16 bit insns,
277 output a nop to move the PC to a 32 bit boundary.
279 This is done via an alignment specification since branch relaxing
280 may make it unnecessary.
282 Internally, we need to output one of these each time a 32 bit insn is
283 seen after an insn that is relaxable. */
289 (void) m32r_do_align (2, NULL, 0, 0);
290 prev_insn.insn = NULL;
291 seen_relaxable_p = 0;
294 /* Cover function to fill_insn called after a label and at end of assembly.
296 The result is always 1: we're called in a conditional to see if the
297 current line is a label. */
300 m32r_fill_insn (done)
306 if (prev_seg != NULL)
311 subseg_set (prev_seg, prev_subseg);
315 subseg_set (seg, subseg);
328 /* Initialize the `cgen' interface. */
330 /* This is a callback from cgen to gas to parse operands. */
331 cgen_parse_operand_fn = cgen_parse_operand;
333 /* Set the machine number and endian. */
334 CGEN_SYM (init_asm) (0 /* mach number */,
336 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
338 #if 0 /* not supported yet */
339 /* If a runtime cpu description file was provided, parse it. */
340 if (m32r_cpu_desc != NULL)
344 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
346 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
350 /* Save the current subseg so we can restore it [it's the default one and
351 we don't want the initial section to be .sbss]. */
355 /* The sbss section is for local .scomm symbols. */
356 sbss_section = subseg_new (".sbss", 0);
358 /* This is copied from perform_an_assembly_pass. */
359 applicable = bfd_applicable_section_flags (stdoutput);
360 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
362 #if 0 /* What does this do? [see perform_an_assembly_pass] */
363 seg_info (bss_section)->bss = 1;
366 subseg_set (seg, subseg);
368 /* We must construct a fake section similar to bfd_com_section
369 but with the name .scommon. */
370 scom_section = bfd_com_section;
371 scom_section.name = ".scommon";
372 scom_section.output_section = & scom_section;
373 scom_section.symbol = & scom_symbol;
374 scom_section.symbol_ptr_ptr = & scom_section.symbol;
375 scom_symbol = * bfd_com_section.symbol;
376 scom_symbol.name = ".scommon";
377 scom_symbol.section = & scom_section;
379 /* start-sanitize-m32rx */
380 allow_m32rx (enable_m32rx);
381 /* end-sanitize-m32rx */
384 /* start-sanitize-m32rx */
385 /* Returns non zero if the given instruction writes to a destination register. */
387 writes_to_dest_reg (insn)
388 const CGEN_INSN * insn;
390 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
393 /* Scan the syntax string looking for a destination register. */
394 while ((c = (* syntax ++)) != 0)
395 if (c == 128 + M32R_OPERAND_DR)
401 /* Returns non zero if the given instruction reads from a source register.
402 Ignores the first 'num_ignore' macthes in the syntax string. */
404 reads_from_src_reg (insn, num_ignore)
405 const CGEN_INSN * insn;
408 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
411 /* Scan the syntax string looking for a source register. */
412 while ((c = (* syntax ++)) != 0)
414 if ( c == 128 + M32R_OPERAND_SR
415 || c == 128 + M32R_OPERAND_SRC1
416 || c == 128 + M32R_OPERAND_SRC2)
418 if (num_ignore -- > 0)
428 /* Returns the integer value of the destination register held in the fields. */
429 #define get_dest_reg(fields) (fields).f_r1
431 /* Returns an integer representing the source register of the given type. */
433 get_src_reg (syntax_field, fields)
434 unsigned char syntax_field;
435 CGEN_FIELDS * fields;
437 switch (syntax_field)
439 case 128 + M32R_OPERAND_SR: return fields->f_r2;
440 /* Relies upon the fact that no instruction with a $src1 operand
441 also has a $dr operand. */
442 case 128 + M32R_OPERAND_SRC1: return fields->f_r1;
443 case 128 + M32R_OPERAND_SRC2: return fields->f_r2;
444 default: abort(); return -1;
448 /* Returns zero iff the output register of instruction 'a'
449 is an input register to instruction 'b'. */
451 check_parallel_io_clash (a, b)
455 if (writes_to_dest_reg (a->insn))
457 unsigned char syntax_field;
460 while (syntax_field = reads_from_src_reg (b->insn, skip ++))
462 if (get_src_reg (syntax_field, & b->fields) == get_dest_reg (a->fields))
471 /* Returns NULL if the two 16 bit insns can be executed in parallel,
472 otherwise it returns a pointer to an error message explaining why not. */
474 can_make_parallel (a, b)
478 /* start-sanitize-m32rx */
482 /* Make sure the instructions are the right length. */
483 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
484 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
487 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
488 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
490 /* Make sure that the instructions use the correct execution pipelines. */
491 if ( a_pipe == PIPE_NONE
492 || b_pipe == PIPE_NONE)
493 return "Instructions do not use parallel execution pipelines.";
495 if ( a_pipe == PIPE_S
497 return "Instructions share the same execution pipeline";
499 /* end-sanitize-m32rx */
500 if ( writes_to_dest_reg (a->insn)
501 && writes_to_dest_reg (b->insn)
502 && (get_dest_reg (a->fields) == get_dest_reg (b->fields)))
503 return "Instructions write to the same destination register.";
510 make_parallel (buffer)
511 cgen_insn_t * buffer;
513 /* Force the top bit of the second insn to be set. */
517 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
519 value = bfd_getb16 ((bfd_byte *) buffer);
521 bfd_putb16 (value, (char *) buffer);
525 value = bfd_getl16 ((bfd_byte *) buffer);
527 bfd_putl16 (value, (char *) buffer);
532 make_parallel (buffer)
535 /* Force the top bit of the second insn to be set. */
537 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
543 assemble_parallel_insn (str, str2)
552 * str2 = 0; /* Seperate the two instructions. */
554 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
555 so that the parallel instruction will start on a 32 bit boundary. */
559 /* Parse the first instruction. */
560 if (! (first.insn = CGEN_SYM (assemble_insn)
561 (str, & first.fields, first.buffer, & errmsg)))
567 /* start-sanitize-m32rx */
568 /* Check to see if this is an allowable parallel insn. */
569 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
571 as_bad ("instruction '%s' cannot be executed in parallel.", str);
576 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
578 as_bad ("instruction '%s' is for the M32RX only", str);
581 /* end-sanitize-m32rx */
583 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
584 str3 = str; /* Save the original string pointer. */
585 str = str2 + 2; /* Advanced past the parsed string. */
586 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
588 /* Preserve any fixups that have been generated and reset the list to empty. */
591 /* Parse the second instruction. */
592 if (! (second.insn = CGEN_SYM (assemble_insn)
593 (str, & second.fields, second.buffer, & errmsg)))
599 /* start-sanitize-m32rx */
602 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
604 as_bad ("instruction '%s' is for the M32RX only", str);
610 if ( strcmp (first.insn->name, "nop") != 0
611 && strcmp (second.insn->name, "nop") != 0)
613 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
617 /* end-sanitize-m32rx */
619 /* We assume that if the first instruction writes to a register that is
620 read by the second instruction it is because the programmer intended
621 this to happen, (after all they have explicitly requested that these
622 two instructions be executed in parallel). Although if the global
623 variable warn_explicit_parallel_conflicts is true then we do generate
624 a warning message. Similarly we assume that parallel branch and jump
625 instructions are deliberate and should not produce errors. */
627 if (can_make_parallel (& first, & second) == NULL)
629 if (warn_explicit_parallel_conflicts
630 && (! check_parallel_io_clash (& first, & second)))
631 as_warn ("%s: output of first instruction fails to overwrite input of second instruction.", str2);
633 /* Get the fixups for the first instruction. */
637 (void) cgen_asm_finish_insn (first.insn, first.buffer,
638 CGEN_FIELDS_BITSIZE (& first.fields));
640 /* Force the top bit of the second insn to be set. */
641 make_parallel (second.buffer);
643 /* Get its fixups. */
644 cgen_restore_fixups ();
647 (void) cgen_asm_finish_insn (second.insn, second.buffer,
648 CGEN_FIELDS_BITSIZE (& second.fields));
650 else if ((errmsg = (char *) can_make_parallel (& second, & first,
651 false, false)) == NULL)
653 if (warn_explicit_parallel_conflicts
654 && (! check_parallel_io_clash (& second, & first)))
655 as_warn ("%s: output of second instruction fails to overwrite input of first instruction.", str2);
657 /* Write out the second instruction first. */
658 (void) cgen_asm_finish_insn (second.insn, second.buffer,
659 CGEN_FIELDS_BITSIZE (& second.fields));
661 /* Force the top bit of the first instruction to be set. */
662 make_parallel (first.buffer);
664 /* Get the fixups for the first instruction. */
665 cgen_restore_fixups ();
667 /* Write out the first instruction. */
668 (void) cgen_asm_finish_insn (first.insn, first.buffer,
669 CGEN_FIELDS_BITSIZE (& first.fields));
673 as_bad ("'%s': %s", str2, errmsg);
677 /* Set these so m32r_fill_insn can use them. */
679 prev_subseg = now_subseg;
683 /* end-sanitize-m32rx */
694 /* Initialize GAS's cgen interface for a new instruction. */
695 cgen_asm_init_parse ();
697 /* start-sanitize-m32rx */
698 /* Look for a parallel instruction seperator. */
699 if ((str2 = strstr (str, "||")) != NULL)
701 assemble_parallel_insn (str, str2);
704 /* end-sanitize-m32rx */
706 insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
713 /* start-sanitize-m32rx */
714 if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
716 as_bad ("instruction '%s' is for the M32RX only", str);
719 /* end-sanitize-m32rx */
721 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
723 /* 32 bit insns must live on 32 bit boundaries. */
724 if (prev_insn.insn || seen_relaxable_p)
726 /* FIXME: If calling fill_insn too many times turns us into a memory
727 pig, can we call assemble_nop instead of !seen_relaxable_p? */
731 (void) cgen_asm_finish_insn (insn.insn, insn.buffer,
732 CGEN_FIELDS_BITSIZE (& insn.fields));
736 /* start-sanitize-m32rx */
737 /* start-sanitize-phase2-m32rx */
739 /* end-sanitize-phase2-m32rx */
740 /* end-sanitize-m32rx */
742 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
745 /* Keep track of whether we've seen a pair of 16 bit insns.
746 prev_insn.insn is NULL when we're on a 32 bit boundary. */
749 /* start-sanitize-m32rx */
750 /* start-sanitize-phase2-m32rx */
751 /* Look to see if this instruction can be combined with the
752 previous instruction to make one, parallel, 32 bit instruction.
753 If the previous instruction (potentially) changed the flow of
754 program control, then it cannot be combined with the current
755 instruction. Also if the output of the previous instruction
756 is used as an input to the current instruction then it cannot
757 be combined. Otherwise call can_make_parallel() with both
758 orderings of the instructions to see if they can be combined. */
759 if ( ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_COND_CTI)
760 && ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_UNCOND_CTI)
761 && check_parallel_io_clash (& prev_insn, &insn)
764 if (can_make_parallel (& prev_insn, & insn) == NULL)
765 make_parallel (insn.buffer);
766 else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
769 /* end-sanitize-phase2-m32rx */
770 /* end-sanitize-m32rx */
772 prev_insn.insn = NULL;
779 /* Record the frag that might be used by this insn. */
780 insn.frag = frag_now;
781 insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer,
782 CGEN_FIELDS_BITSIZE (& insn.fields));
784 /* start-sanitize-m32rx */
785 /* start-sanitize-phase2-m32rx */
790 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
792 /* Swap the two insns */
793 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
794 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
796 make_parallel (insn.addr);
798 /* Swap any relaxable frags recorded for the two insns. */
799 if (prev_insn.frag->fr_opcode == prev_insn.addr)
801 prev_insn.frag->fr_opcode = insn.addr;
803 else if (insn.frag->fr_opcode == insn.addr)
805 insn.frag->fr_opcode = prev_insn.addr;
808 /* end-sanitize-phase2-m32rx */
810 /* Record where this instruction was assembled. */
811 prev_insn.addr = insn.addr;
812 prev_insn.frag = insn.frag;
813 /* end-sanitize-m32rx */
815 /* If the insn needs the following one to be on a 32 bit boundary
816 (e.g. subroutine calls), fill this insn's slot. */
818 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0)
821 /* If this is a relaxable insn (can be replaced with a larger version)
822 mark the fact so that we can emit an alignment directive for a
823 following 32 bit insn if we see one. */
824 if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0)
825 seen_relaxable_p = 1;
828 /* Set these so m32r_fill_insn can use them. */
830 prev_subseg = now_subseg;
833 /* The syntax in the manual says constants begin with '#'.
834 We just ignore it. */
837 md_operand (expressionP)
838 expressionS * expressionP;
840 if (* input_line_pointer == '#')
842 input_line_pointer ++;
843 expression (expressionP);
848 md_section_align (segment, size)
852 int align = bfd_get_section_alignment (stdoutput, segment);
853 return ((size + (1 << align) - 1) & (-1 << align));
857 md_undefined_symbol (name)
863 /* .scomm pseudo-op handler.
865 This is a new pseudo-op to handle putting objects in .scommon.
866 By doing this the linker won't need to do any work and more importantly
867 it removes the implicit -G arg necessary to correctly link the object file.
874 register char * name;
878 register symbolS * symbolP;
882 name = input_line_pointer;
883 c = get_symbol_end ();
885 /* just after name is now '\0' */
886 p = input_line_pointer;
889 if (* input_line_pointer != ',')
891 as_bad ("Expected comma after symbol-name: rest of line ignored.");
892 ignore_rest_of_line ();
896 input_line_pointer ++; /* skip ',' */
897 if ((size = get_absolute_expression ()) < 0)
899 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
900 ignore_rest_of_line ();
904 /* The third argument to .scomm is the alignment. */
905 if (* input_line_pointer != ',')
909 ++ input_line_pointer;
910 align = get_absolute_expression ();
913 as_warn ("ignoring bad alignment");
917 /* Convert to a power of 2 alignment. */
920 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
924 as_bad ("Common alignment not a power of 2");
925 ignore_rest_of_line ();
933 symbolP = symbol_find_or_make (name);
936 if (S_IS_DEFINED (symbolP))
938 as_bad ("Ignoring attempt to re-define symbol `%s'.",
939 S_GET_NAME (symbolP));
940 ignore_rest_of_line ();
944 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
946 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
947 S_GET_NAME (symbolP),
948 (long) S_GET_VALUE (symbolP),
951 ignore_rest_of_line ();
957 segT old_sec = now_seg;
958 int old_subsec = now_subseg;
961 record_alignment (sbss_section, align2);
962 subseg_set (sbss_section, 0);
965 frag_align (align2, 0, 0);
967 if (S_GET_SEGMENT (symbolP) == sbss_section)
968 symbolP->sy_frag->fr_symbol = 0;
970 symbolP->sy_frag = frag_now;
972 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
975 S_SET_SIZE (symbolP, size);
976 S_SET_SEGMENT (symbolP, sbss_section);
977 S_CLEAR_EXTERNAL (symbolP);
978 subseg_set (old_sec, old_subsec);
982 S_SET_VALUE (symbolP, (valueT) size);
983 S_SET_ALIGN (symbolP, align2);
984 S_SET_EXTERNAL (symbolP);
985 S_SET_SEGMENT (symbolP, & scom_section);
988 demand_empty_rest_of_line ();
991 /* Interface to relax_segment. */
993 /* FIXME: Build table by hand, get it working, then machine generate. */
995 const relax_typeS md_relax_table[] =
998 1) most positive reach of this state,
999 2) most negative reach of this state,
1000 3) how many bytes this mode will add to the size of the current frag
1001 4) which index into the table to try if we can't fit into this one. */
1003 /* The first entry must be unused because an `rlx_more' value of zero ends
1007 /* The displacement used by GAS is from the end of the 2 byte insn,
1008 so we subtract 2 from the following. */
1009 /* 16 bit insn, 8 bit disp -> 10 bit range.
1010 This doesn't handle a branch in the right slot at the border:
1011 the "& -4" isn't taken into account. It's not important enough to
1012 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1014 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1015 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1016 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1017 /* Same thing, but with leading nop for alignment. */
1018 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1022 m32r_relax_frag (fragP, stretch)
1026 /* Address of branch insn. */
1027 long address = fragP->fr_address + fragP->fr_fix - 2;
1030 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1031 if (fragP->fr_subtype == 2)
1033 if ((address & 3) != 0)
1035 fragP->fr_subtype = 3;
1039 else if (fragP->fr_subtype == 3)
1041 if ((address & 3) == 0)
1043 fragP->fr_subtype = 2;
1049 growth = relax_frag (fragP, stretch);
1051 /* Long jump on odd halfword boundary? */
1052 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1054 fragP->fr_subtype = 3;
1062 /* Return an initial guess of the length by which a fragment must grow to
1063 hold a branch to reach its destination.
1064 Also updates fr_type/fr_subtype as necessary.
1066 Called just before doing relaxation.
1067 Any symbol that is now undefined will not become defined.
1068 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1069 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1070 Although it may not be explicit in the frag, pretend fr_var starts with a
1074 md_estimate_size_before_relax (fragP, segment)
1078 int old_fr_fix = fragP->fr_fix;
1079 char * opcode = fragP->fr_opcode;
1081 /* The only thing we have to handle here are symbols outside of the
1082 current segment. They may be undefined or in a different segment in
1083 which case linker scripts may place them anywhere.
1084 However, we can't finish the fragment here and emit the reloc as insn
1085 alignment requirements may move the insn about. */
1087 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1089 /* The symbol is undefined in this segment.
1090 Change the relaxation subtype to the max allowable and leave
1091 all further handling to md_convert_frag. */
1092 fragP->fr_subtype = 2;
1094 #if 0 /* Can't use this, but leave in for illustration. */
1095 /* Change 16 bit insn to 32 bit insn. */
1098 /* Increase known (fixed) size of fragment. */
1101 /* Create a relocation for it. */
1102 fix_new (fragP, old_fr_fix, 4,
1104 fragP->fr_offset, 1 /* pcrel */,
1105 /* FIXME: Can't use a real BFD reloc here.
1106 cgen_md_apply_fix3 can't handle it. */
1107 BFD_RELOC_M32R_26_PCREL);
1109 /* Mark this fragment as finished. */
1113 const CGEN_INSN * insn;
1116 /* Update the recorded insn.
1117 Fortunately we don't have to look very far.
1118 FIXME: Change this to record in the instruction the next higher
1119 relaxable insn to use. */
1120 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1122 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1123 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1125 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1131 fragP->fr_cgen.insn = insn;
1137 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1140 /* *fragP has been relaxed to its final size, and now needs to have
1141 the bytes inside it modified to conform to the new size.
1143 Called after relaxation is finished.
1144 fragP->fr_type == rs_machine_dependent.
1145 fragP->fr_subtype is the subtype of what the address relaxed to. */
1148 md_convert_frag (abfd, sec, fragP)
1154 char * displacement;
1160 opcode = fragP->fr_opcode;
1162 /* Address opcode resides at in file space. */
1163 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1165 switch (fragP->fr_subtype)
1169 displacement = & opcode[1];
1174 displacement = & opcode[1];
1177 opcode[2] = opcode[0] | 0x80;
1178 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1179 opcode_address += 2;
1181 displacement = & opcode[3];
1187 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1189 /* symbol must be resolved by linker */
1190 if (fragP->fr_offset & 3)
1191 as_warn ("Addend to unresolved symbol not on word boundary.");
1192 addend = fragP->fr_offset >> 2;
1196 /* Address we want to reach in file space. */
1197 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1198 target_address += fragP->fr_symbol->sy_frag->fr_address;
1199 addend = (target_address - (opcode_address & -4)) >> 2;
1202 /* Create a relocation for symbols that must be resolved by the linker.
1203 Otherwise output the completed insn. */
1205 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1207 assert (fragP->fr_subtype != 1);
1208 assert (fragP->fr_cgen.insn != 0);
1209 cgen_record_fixup (fragP,
1210 /* Offset of branch insn in frag. */
1211 fragP->fr_fix + extension - 4,
1212 fragP->fr_cgen.insn,
1214 /* FIXME: quick hack */
1216 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1218 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1220 fragP->fr_cgen.opinfo,
1221 fragP->fr_symbol, fragP->fr_offset);
1224 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1226 md_number_to_chars (displacement, (valueT) addend,
1227 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1229 fragP->fr_fix += extension;
1232 /* Functions concerning relocs. */
1234 /* The location from which a PC relative jump should be calculated,
1235 given a PC relative reloc. */
1238 md_pcrel_from_section (fixP, sec)
1242 if (fixP->fx_addsy != (symbolS *) NULL
1243 && (! S_IS_DEFINED (fixP->fx_addsy)
1244 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1246 /* The symbol is undefined (or is defined but not in this section).
1247 Let the linker figure it out. */
1251 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1254 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1255 Returns BFD_RELOC_NONE if no reloc type can be found.
1256 *FIXP may be modified if desired. */
1258 bfd_reloc_code_real_type
1259 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1260 const CGEN_INSN * insn;
1261 const CGEN_OPERAND * operand;
1264 switch (CGEN_OPERAND_TYPE (operand))
1266 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1267 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1268 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1269 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1270 case M32R_OPERAND_HI16 :
1271 case M32R_OPERAND_SLO16 :
1272 case M32R_OPERAND_ULO16 :
1273 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1274 if (fixP->tc_fix_data.opinfo != 0)
1275 return fixP->tc_fix_data.opinfo;
1278 return BFD_RELOC_NONE;
1281 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1284 m32r_record_hi16 (reloc_type, fixP, seg)
1289 struct m32r_hi_fixup * hi_fixup;
1291 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1292 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1294 hi_fixup = ((struct m32r_hi_fixup *)
1295 xmalloc (sizeof (struct m32r_hi_fixup)));
1296 hi_fixup->fixp = fixP;
1297 hi_fixup->seg = now_seg;
1298 hi_fixup->next = m32r_hi_fixup_list;
1300 m32r_hi_fixup_list = hi_fixup;
1303 /* Called while parsing an instruction to create a fixup.
1304 We need to check for HI16 relocs and queue them up for later sorting. */
1307 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1310 const CGEN_INSN * insn;
1312 const CGEN_OPERAND * operand;
1316 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1317 operand, opinfo, exp);
1319 switch (CGEN_OPERAND_TYPE (operand))
1321 case M32R_OPERAND_HI16 :
1322 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1323 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1324 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1325 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1332 /* Return BFD reloc type from opinfo field in a fixS.
1333 It's tricky using fx_r_type in m32r_frob_file because the values
1334 are BFD_RELOC_UNUSED + operand number. */
1335 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1337 /* Sort any unmatched HI16 relocs so that they immediately precede
1338 the corresponding LO16 reloc. This is called before md_apply_fix and
1344 struct m32r_hi_fixup * l;
1346 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1348 segment_info_type * seginfo;
1351 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1352 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1354 /* Check quickly whether the next fixup happens to be a matching low. */
1355 if (l->fixp->fx_next != NULL
1356 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1357 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1358 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1361 /* Look through the fixups for this segment for a matching `low'.
1362 When we find one, move the high/shigh just in front of it. We do
1363 this in two passes. In the first pass, we try to find a
1364 unique `low'. In the second pass, we permit multiple high's
1365 relocs for a single `low'. */
1366 seginfo = seg_info (l->seg);
1367 for (pass = 0; pass < 2; pass++)
1373 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1375 /* Check whether this is a `low' fixup which matches l->fixp. */
1376 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1377 && f->fx_addsy == l->fixp->fx_addsy
1378 && f->fx_offset == l->fixp->fx_offset
1381 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1382 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1383 || prev->fx_addsy != f->fx_addsy
1384 || prev->fx_offset != f->fx_offset))
1388 /* Move l->fixp before f. */
1389 for (pf = &seginfo->fix_root;
1391 pf = & (* pf)->fx_next)
1392 assert (* pf != NULL);
1394 * pf = l->fixp->fx_next;
1396 l->fixp->fx_next = f;
1398 seginfo->fix_root = l->fixp;
1400 prev->fx_next = l->fixp;
1412 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1413 "Unmatched high/shigh reloc");
1418 /* See whether we need to force a relocation into the output file.
1419 This is used to force out switch and PC relative relocations when
1423 m32r_force_relocation (fix)
1429 return (fix->fx_pcrel
1433 /* Write a value out to the object file, using the appropriate endianness. */
1436 md_number_to_chars (buf, val, n)
1441 if (target_big_endian)
1442 number_to_chars_bigendian (buf, val, n);
1444 number_to_chars_littleendian (buf, val, n);
1447 /* Turn a string in input_line_pointer into a floating point constant of type
1448 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1449 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1452 /* Equal to MAX_PRECISION in atof-ieee.c */
1453 #define MAX_LITTLENUMS 6
1456 md_atof (type, litP, sizeP)
1463 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1464 LITTLENUM_TYPE * wordP;
1466 char * atof_ieee ();
1484 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1488 return "Bad call to md_atof()";
1491 t = atof_ieee (input_line_pointer, type, words);
1493 input_line_pointer = t;
1494 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1496 if (target_big_endian)
1498 for (i = 0; i < prec; i++)
1500 md_number_to_chars (litP, (valueT) words[i],
1501 sizeof (LITTLENUM_TYPE));
1502 litP += sizeof (LITTLENUM_TYPE);
1507 for (i = prec - 1; i >= 0; i--)
1509 md_number_to_chars (litP, (valueT) words[i],
1510 sizeof (LITTLENUM_TYPE));
1511 litP += sizeof (LITTLENUM_TYPE);