1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 /* Non-null if last insn was a 16 bit insn on a 32 bit boundary
28 (i.e. was the first of two 16 bit insns). */
29 static const CGEN_INSN * prev_insn = NULL;
30 static CGEN_FIELDS prev_fields;
32 /* Non-zero if we've seen a relaxable insn since the last 32 bit
34 static int seen_relaxable_p = 0;
36 /* Non-zero if -relax specified, in which case sufficient relocs are output
37 for the linker to do relaxing.
38 We do simple forms of relaxing internally, but they are always done.
39 This flag does not apply to them. */
40 static int m32r_relax;
42 /* If non-NULL, pointer to cpu description file to read.
43 This allows runtime additions to the assembler. */
44 static char * m32r_cpu_desc;
46 /* start-sanitize-m32rx */
47 /* Non-zero if -m32rx has been specified, in which case support for the
48 extended M32RX instruction set should be enabled. */
49 static int enable_m32rx = 0;
50 /* end-sanitize-m32rx */
52 /* stuff for .scomm symbols. */
53 static segT sbss_section;
54 static asection scom_section;
55 static asymbol scom_symbol;
57 const char comment_chars[] = ";";
58 const char line_comment_chars[] = "#";
59 const char line_separator_chars[] = "";
60 const char EXP_CHARS[] = "eE";
61 const char FLT_CHARS[] = "dD";
63 /* Relocations against symbols are done in two
64 parts, with a HI relocation and a LO relocation. Each relocation
65 has only 16 bits of space to store an addend. This means that in
66 order for the linker to handle carries correctly, it must be able
67 to locate both the HI and the LO relocation. This means that the
68 relocations must appear in order in the relocation table.
70 In order to implement this, we keep track of each unmatched HI
71 relocation. We then sort them so that they immediately precede the
72 corresponding LO relocation. */
76 struct m32r_hi_fixup * next; /* Next HI fixup. */
77 fixS * fixp; /* This fixup. */
78 segT seg; /* The section this fixup is in. */
82 /* The list of unmatched HI relocs. */
84 static struct m32r_hi_fixup * m32r_hi_fixup_list;
86 static void m32r_record_hi16 PARAMS ((int, fixS *, segT seg));
89 /* start-sanitize-m32rx */
95 if (stdoutput != NULL)
96 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
97 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
99 /* end-sanitize-m32rx */
101 const char * md_shortopts = "";
103 struct option md_longopts[] =
105 /* start-sanitize-m32rx */
106 #define OPTION_M32RX (OPTION_MD_BASE)
107 {"m32rx", no_argument, NULL, OPTION_M32RX},
108 /* end-sanitize-m32rx */
110 #if 0 /* not supported yet */
111 #define OPTION_RELAX (OPTION_MD_BASE + 1)
112 {"relax", no_argument, NULL, OPTION_RELAX},
113 #define OPTION_CPU_DESC (OPTION_MD_BASE + 2)
114 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
117 {NULL, no_argument, NULL, 0}
119 size_t md_longopts_size = sizeof (md_longopts);
122 md_parse_option (c, arg)
128 /* start-sanitize-m32rx */
132 /* end-sanitize-m32rx */
134 #if 0 /* not supported yet */
138 case OPTION_CPU_DESC:
149 md_show_usage (stream)
152 fprintf (stream, "M32R/X options:\n");
153 /* start-sanitize-m32rx */
155 --m32rx support the extended m32rx instruction set\n");
156 /* end-sanitize-m32rx */
160 --relax create linker relaxable code\n");
162 --cpu-desc provide runtime cpu description file\n");
166 static void fill_insn PARAMS ((int));
167 static void m32r_scomm PARAMS ((int));
169 /* Set by md_assemble for use by m32r_fill_insn. */
170 static subsegT prev_subseg;
171 static segT prev_seg;
173 /* The target specific pseudo-ops which we support. */
174 const pseudo_typeS md_pseudo_table[] =
177 { "fillinsn", fill_insn, 0 },
178 { "scomm", m32r_scomm, 0 },
179 /* start-sanitize-m32rx */
180 { "m32r", allow_m32rx, 0},
181 { "m32rx", allow_m32rx, 1},
182 /* end-sanitize-m32rx */
186 /* FIXME: Should be machine generated. */
187 #define NOP_INSN 0x7000
188 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
190 /* When we align the .text section, insert the correct NOP pattern.
191 N is the power of 2 alignment. LEN is the length of pattern FILL.
192 MAX is the maximum number of characters to skip when doing the alignment,
193 or 0 if there is no maximum. */
196 m32r_do_align (n, fill, len, max)
202 if ((fill == NULL || (* fill == 0 && len == 1))
203 && (now_seg->flags & SEC_CODE) != 0
204 /* Only do this special handling if aligning to at least a
207 /* Only do this special handling if we're allowed to emit at
209 && (max == 0 || max > 1))
211 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
214 /* First align to a 2 byte boundary, in case there is an odd .byte. */
215 /* FIXME: How much memory will cause gas to use when assembling a big
216 program? Perhaps we can avoid the frag_align call? */
217 frag_align (1, 0, 0);
219 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
221 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
222 /* If doing larger alignments use a repeating sequence of appropriate
226 static const unsigned char multi_nop_pattern[] =
227 { 0x70, 0x00, 0xf0, 0x00 };
228 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
238 assemble_nop (opcode)
241 char * f = frag_more (2);
242 md_number_to_chars (f, opcode, 2);
245 /* If the last instruction was the first of 2 16 bit insns,
246 output a nop to move the PC to a 32 bit boundary.
248 This is done via an alignment specification since branch relaxing
249 may make it unnecessary.
251 Internally, we need to output one of these each time a 32 bit insn is
252 seen after an insn that is relaxable. */
258 (void) m32r_do_align (2, NULL, 0, 0);
260 seen_relaxable_p = 0;
263 /* Cover function to fill_insn called after a label and at end of assembly.
265 The result is always 1: we're called in a conditional to see if the
266 current line is a label. */
269 m32r_fill_insn (done)
275 if (prev_seg != NULL)
280 subseg_set (prev_seg, prev_subseg);
284 subseg_set (seg, subseg);
297 /* Initialize the `cgen' interface. */
299 /* This is a callback from cgen to gas to parse operands. */
300 cgen_parse_operand_fn = cgen_parse_operand;
302 /* Set the machine number and endian. */
303 CGEN_SYM (init_asm) (0 /* mach number */,
305 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
307 #if 0 /* not supported yet */
308 /* If a runtime cpu description file was provided, parse it. */
309 if (m32r_cpu_desc != NULL)
313 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
315 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
319 /* Save the current subseg so we can restore it [it's the default one and
320 we don't want the initial section to be .sbss]. */
324 /* The sbss section is for local .scomm symbols. */
325 sbss_section = subseg_new (".sbss", 0);
327 /* This is copied from perform_an_assembly_pass. */
328 applicable = bfd_applicable_section_flags (stdoutput);
329 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
331 #if 0 /* What does this do? [see perform_an_assembly_pass] */
332 seg_info (bss_section)->bss = 1;
335 subseg_set (seg, subseg);
337 /* We must construct a fake section similar to bfd_com_section
338 but with the name .scommon. */
339 scom_section = bfd_com_section;
340 scom_section.name = ".scommon";
341 scom_section.output_section = & scom_section;
342 scom_section.symbol = & scom_symbol;
343 scom_section.symbol_ptr_ptr = & scom_section.symbol;
344 scom_symbol = * bfd_com_section.symbol;
345 scom_symbol.name = ".scommon";
346 scom_symbol.section = & scom_section;
348 /* start-sanitize-m32rx */
349 allow_m32rx (enable_m32rx);
350 /* end-sanitize-m32rx */
353 /* Returns non zero if the given instruction writes to a destination register. */
355 writes_to_dest_reg (insn)
356 const CGEN_INSN * insn;
358 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
361 /* Scan the syntax string looking for a destination register. */
362 while ((c = (* syntax ++)) != 0)
363 if (c == 128 + M32R_OPERAND_DR)
369 /* Returns non zero if the given instruction reads from a source register.
370 Syntax characters equal to 'ignore' are skipped as they have already been
371 processed. (This works provided that no potential parallel instruction
372 can have more than 2 input registers). */
374 reads_from_src_reg (insn, ignore)
375 const CGEN_INSN * insn;
376 unsigned char ignore;
378 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
381 /* Scan the syntax string looking for a source register. */
382 while ((c = (* syntax ++)) != 0)
387 if ( c == 128 + M32R_OPERAND_SR
388 || c == 128 + M32R_OPERAND_SRC1
389 || c == 128 + M32R_OPERAND_SRC2)
396 /* Returns the integer value of the destination register held in the fields. */
397 #define get_dest_reg(fields) fields->f_r1
399 /* Returns an integer representing the source register of the given type. */
401 get_src_reg (syntax, fields)
402 unsigned char syntax;
403 CGEN_FIELDS * fields;
407 case 128 + M32R_OPERAND_SR: return fields->f_r2;
408 /* Relies upon the fact that no instruction with a $src1 operand
409 also has a $dr operand. */
410 case 128 + M32R_OPERAND_SRC1: return fields->f_r1;
411 case 128 + M32R_OPERAND_SRC2: return fields->f_r2;
412 default: abort(); return -1;
416 /* start-sanitize-m32rx */
417 /* Returns NULL if the two 16 bit insns can be executed in parallel,
418 otherwise it returns a pointer to an error message explaining why not. */
420 can_make_parallel (a, a_fields, b, b_fields, test_a_inputs, test_b_inputs)
422 CGEN_FIELDS * a_fields;
424 CGEN_FIELDS * b_fields;
431 /* Make sure the instructions are the right length. */
432 if ( CGEN_FIELDS_BITSIZE (a_fields) != 16
433 || CGEN_FIELDS_BITSIZE (b_fields) != 16)
436 a_pipe = CGEN_INSN_ATTR (a, CGEN_INSN_PIPE);
437 b_pipe = CGEN_INSN_ATTR (b, CGEN_INSN_PIPE);
439 if ( a_pipe == PIPE_NONE
440 || b_pipe == PIPE_NONE)
441 return "Instructions do not use parallel execution pipelines.";
443 if ( a_pipe == PIPE_S
445 return "Instructions share the same execution pipeline";
447 if ( writes_to_dest_reg (a)
448 && writes_to_dest_reg (b)
449 && (get_dest_reg (a_fields) == get_dest_reg (b_fields)))
450 return "Instructions write to the same destination register.";
452 /* If requested, make sure that the first instruction does not
453 overwrite the inputs of the second instruction. */
454 if (test_b_inputs && writes_to_dest_reg (a))
456 unsigned char skip = 1;
458 while (skip = reads_from_src_reg (b, skip))
460 if (get_src_reg (skip, b_fields) == get_dest_reg (a_fields))
461 return "First instruction writes to register read by the second instruction";
465 /* Similarly, if requested, make sure that the second instruction
466 does not overwrite the inputs of the first instruction. */
467 if (test_a_inputs && writes_to_dest_reg (b))
469 unsigned char skip = 1;
471 while (skip = reads_from_src_reg (a, skip))
473 if (get_src_reg (skip, a_fields) == get_dest_reg (b_fields))
474 return "Second instruction writes to register read by the first instruction";
480 /* end-sanitize-m32rx */
485 make_parallel (insn, buffer)
486 const CGEN_INSN * insn;
487 cgen_insn_t * buffer;
489 /* Force the top bit of the second insn to be set. */
493 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
495 value = bfd_getb16 ((bfd_byte *) buffer);
497 bfd_putb16 (value, (char *) buffer);
501 value = bfd_getl16 ((bfd_byte *) buffer);
503 bfd_putl16 (value, (char *) buffer);
508 make_parallel (insn, buffer)
509 const CGEN_INSN * insn;
512 /* Force the top bit of the second insn to be set. */
514 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
524 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
525 cgen_insn_t prev_buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
527 char buffer [CGEN_MAX_INSN_SIZE];
528 char prev_buffer [CGEN_MAX_INSN_SIZE];
531 const CGEN_INSN * insn;
534 int is_parallel = false;
536 /* Initialize GAS's cgen interface for a new instruction. */
537 cgen_asm_init_parse ();
539 /* Look for a parallel instruction seperator. */
540 if ((str2 = strstr (str, "||")) != NULL)
544 * str2 = 0; /* Seperate the two instructions. */
546 /* If there was a previous 16 bit insn, then fill the following 16 bit
547 slot, so that the parallel instruction will start on a 32 bit
552 /* Assemble the first instruction. */
553 prev_insn = CGEN_SYM (assemble_insn) (str, & prev_fields, prev_buffer,
561 /* start-sanitize-m32rx */
562 /* Check to see if this is an allowable parallel insn. */
563 if (CGEN_INSN_ATTR (prev_insn, CGEN_INSN_PIPE) == PIPE_NONE)
565 as_bad ("instruction '%s' cannot be executed in parallel.", str);
569 if (! enable_m32rx &&
570 CGEN_INSN_ATTR (prev_insn, CGEN_INSN_MACH) == MACH_M32RX)
572 as_bad ("instruction '%s' is for the M32RX only", str);
575 /* end-sanitize-m32rx */
577 /* fixups = fixups->next; */
579 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
580 str3 = str; /* Save the original string pointer. */
581 str = str2 + 2; /* Advanced past the parsed string. */
582 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
587 insn = CGEN_SYM (assemble_insn) (str, & fields, buffer, & errmsg);
594 /* start-sanitize-m32rx */
595 if (! enable_m32rx && CGEN_INSN_ATTR (insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
597 as_bad ("instruction '%s' is for the M32RX only", str);
600 /* end-sanitize-m32rx */
606 /* start-sanitize-m32rx */
609 if (strcmp (prev_insn->name, "nop") != 0
610 && strcmp (insn->name, "nop") != 0)
612 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
617 /* We assume that if the first instruction writes to a register that is
618 read by the second instruction it is because the programmer intended
619 this to happen, (after all they have explicitly requested that these
620 two instructions be executed in parallel). So we do not generate an
621 error if this happens. */
622 if (can_make_parallel (prev_insn, & prev_fields, insn,
623 & fields, false, false) != NULL)
625 if ((errmsg = (char *) can_make_parallel (insn, & fields, prev_insn,
626 & prev_fields, false, false)) == NULL)
628 /* swap the two insns. */
633 as_bad ("'%s': %s", str2, errmsg);
637 /* end-sanitize-m32rx */
639 /* Generate the parallel instructions */
642 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
644 /* Force the top bit of the second insn to be set. */
645 make_parallel (prev_insn, prev_buffer);
647 cgen_asm_finish_insn (prev_insn, prev_buffer,
648 CGEN_FIELDS_BITSIZE (& prev_fields));
652 cgen_asm_finish_insn (prev_insn, prev_buffer,
653 CGEN_FIELDS_BITSIZE (& prev_fields));
655 /* Force the top bit of the second insn to be set. */
656 make_parallel (insn, buffer);
658 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
661 /* Clear the prev_insn variable, since it only used if the insn was the first
662 16 bit insn in a 32 bit word. */
665 else if (CGEN_INSN_BITSIZE (insn) == 32)
667 /* 32 bit insns must live on 32 bit boundaries. */
668 if (prev_insn || seen_relaxable_p)
670 /* FIXME: If calling fill_insn too many times turns us into a memory
671 pig, can we call assemble_nop instead of !seen_relaxable_p? */
675 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
679 /* Keep track of whether we've seen a pair of 16 bit insns.
680 PREV_INSN is NULL when we're on a 32 bit boundary. */
683 /* start-sanitize-m32rx */
684 if (can_make_parallel (prev_insn, & prev_fields, insn, & fields, false, true) == NULL)
685 make_parallel (insn, buffer);
686 else if (can_make_parallel (insn, & fields, prev_insn, & prev_fields, true, false) == NULL)
688 /* Swap instructions and make parallel. */
691 /* end-sanitize-m32rx */
698 prev_fields = fields;
701 cgen_asm_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (& fields));
703 /* If the insn needs the following one to be on a 32 bit boundary
704 (e.g. subroutine calls), fill this insn's slot. */
706 && CGEN_INSN_ATTR (insn, CGEN_INSN_FILL_SLOT) != 0)
709 /* If this is a relaxable insn (can be replaced with a larger version)
710 mark the fact so that we can emit an alignment directive for a following
711 32 bit insn if we see one. */
712 if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAXABLE) != 0)
713 seen_relaxable_p = 1;
716 /* Set these so m32r_fill_insn can use them. */
718 prev_subseg = now_subseg;
721 /* The syntax in the manual says constants begin with '#'.
722 We just ignore it. */
725 md_operand (expressionP)
726 expressionS * expressionP;
728 if (* input_line_pointer == '#')
730 input_line_pointer ++;
731 expression (expressionP);
736 md_section_align (segment, size)
740 int align = bfd_get_section_alignment (stdoutput, segment);
741 return ((size + (1 << align) - 1) & (-1 << align));
745 md_undefined_symbol (name)
751 /* .scomm pseudo-op handler.
753 This is a new pseudo-op to handle putting objects in .scommon.
754 By doing this the linker won't need to do any work and more importantly
755 it removes the implicit -G arg necessary to correctly link the object file.
762 register char * name;
766 register symbolS * symbolP;
770 name = input_line_pointer;
771 c = get_symbol_end ();
773 /* just after name is now '\0' */
774 p = input_line_pointer;
777 if (* input_line_pointer != ',')
779 as_bad ("Expected comma after symbol-name: rest of line ignored.");
780 ignore_rest_of_line ();
784 input_line_pointer++; /* skip ',' */
785 if ((size = get_absolute_expression ()) < 0)
787 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
788 ignore_rest_of_line ();
792 /* The third argument to .scomm is the alignment. */
793 if (* input_line_pointer != ',')
797 ++ input_line_pointer;
798 align = get_absolute_expression ();
801 as_warn ("ignoring bad alignment");
805 /* Convert to a power of 2 alignment. */
808 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
812 as_bad ("Common alignment not a power of 2");
813 ignore_rest_of_line ();
821 symbolP = symbol_find_or_make (name);
824 if (S_IS_DEFINED (symbolP))
826 as_bad ("Ignoring attempt to re-define symbol `%s'.",
827 S_GET_NAME (symbolP));
828 ignore_rest_of_line ();
832 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
834 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
835 S_GET_NAME (symbolP),
836 (long) S_GET_VALUE (symbolP),
839 ignore_rest_of_line ();
845 segT old_sec = now_seg;
846 int old_subsec = now_subseg;
849 record_alignment (sbss_section, align2);
850 subseg_set (sbss_section, 0);
853 frag_align (align2, 0, 0);
855 if (S_GET_SEGMENT (symbolP) == sbss_section)
856 symbolP->sy_frag->fr_symbol = 0;
858 symbolP->sy_frag = frag_now;
859 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
862 S_SET_SIZE (symbolP, size);
863 S_SET_SEGMENT (symbolP, sbss_section);
864 S_CLEAR_EXTERNAL (symbolP);
865 subseg_set (old_sec, old_subsec);
869 S_SET_VALUE (symbolP, (valueT) size);
870 S_SET_ALIGN (symbolP, align2);
871 S_SET_EXTERNAL (symbolP);
872 S_SET_SEGMENT (symbolP, &scom_section);
875 demand_empty_rest_of_line ();
878 /* Interface to relax_segment. */
880 /* FIXME: Build table by hand, get it working, then machine generate. */
882 const relax_typeS md_relax_table[] =
885 1) most positive reach of this state,
886 2) most negative reach of this state,
887 3) how many bytes this mode will add to the size of the current frag
888 4) which index into the table to try if we can't fit into this one. */
890 /* The first entry must be unused because an `rlx_more' value of zero ends
894 /* The displacement used by GAS is from the end of the 2 byte insn,
895 so we subtract 2 from the following. */
896 /* 16 bit insn, 8 bit disp -> 10 bit range.
897 This doesn't handle a branch in the right slot at the border:
898 the "& -4" isn't taken into account. It's not important enough to
899 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
901 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
902 /* 32 bit insn, 24 bit disp -> 26 bit range. */
903 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
904 /* Same thing, but with leading nop for alignment. */
905 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
909 m32r_relax_frag (fragP, stretch)
913 /* Address of branch insn. */
914 long address = fragP->fr_address + fragP->fr_fix - 2;
917 /* Keep 32 bit insns aligned on 32 bit boundaries. */
918 if (fragP->fr_subtype == 2)
920 if ((address & 3) != 0)
922 fragP->fr_subtype = 3;
926 else if (fragP->fr_subtype == 3)
928 if ((address & 3) == 0)
930 fragP->fr_subtype = 2;
936 growth = relax_frag (fragP, stretch);
938 /* Long jump on odd halfword boundary? */
939 if (fragP->fr_subtype == 2 && (address & 3) != 0)
941 fragP->fr_subtype = 3;
949 /* Return an initial guess of the length by which a fragment must grow to
950 hold a branch to reach its destination.
951 Also updates fr_type/fr_subtype as necessary.
953 Called just before doing relaxation.
954 Any symbol that is now undefined will not become defined.
955 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
956 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
957 Although it may not be explicit in the frag, pretend fr_var starts with a
961 md_estimate_size_before_relax (fragP, segment)
965 int old_fr_fix = fragP->fr_fix;
966 char * opcode = fragP->fr_opcode;
968 /* The only thing we have to handle here are symbols outside of the
969 current segment. They may be undefined or in a different segment in
970 which case linker scripts may place them anywhere.
971 However, we can't finish the fragment here and emit the reloc as insn
972 alignment requirements may move the insn about. */
974 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
976 /* The symbol is undefined in this segment.
977 Change the relaxation subtype to the max allowable and leave
978 all further handling to md_convert_frag. */
979 fragP->fr_subtype = 2;
981 #if 0 /* Can't use this, but leave in for illustration. */
982 /* Change 16 bit insn to 32 bit insn. */
985 /* Increase known (fixed) size of fragment. */
988 /* Create a relocation for it. */
989 fix_new (fragP, old_fr_fix, 4,
991 fragP->fr_offset, 1 /* pcrel */,
992 /* FIXME: Can't use a real BFD reloc here.
993 cgen_md_apply_fix3 can't handle it. */
994 BFD_RELOC_M32R_26_PCREL);
996 /* Mark this fragment as finished. */
1000 const CGEN_INSN * insn;
1003 /* Update the recorded insn.
1004 Fortunately we don't have to look very far.
1005 FIXME: Change this to record in the instruction the next higher
1006 relaxable insn to use. */
1007 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1009 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1010 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1012 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1017 fragP->fr_cgen.insn = insn;
1023 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1026 /* *fragP has been relaxed to its final size, and now needs to have
1027 the bytes inside it modified to conform to the new size.
1029 Called after relaxation is finished.
1030 fragP->fr_type == rs_machine_dependent.
1031 fragP->fr_subtype is the subtype of what the address relaxed to. */
1034 md_convert_frag (abfd, sec, fragP)
1040 char * displacement;
1046 opcode = fragP->fr_opcode;
1048 /* Address opcode resides at in file space. */
1049 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1051 switch (fragP->fr_subtype)
1055 displacement = & opcode[1];
1060 displacement = & opcode[1];
1063 opcode[2] = opcode[0] | 0x80;
1064 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1065 opcode_address += 2;
1067 displacement = & opcode[3];
1073 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1075 /* symbol must be resolved by linker */
1076 if (fragP->fr_offset & 3)
1077 as_warn ("Addend to unresolved symbol not on word boundary.");
1078 addend = fragP->fr_offset >> 2;
1082 /* Address we want to reach in file space. */
1083 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1084 target_address += fragP->fr_symbol->sy_frag->fr_address;
1085 addend = (target_address - (opcode_address & -4)) >> 2;
1088 /* Create a relocation for symbols that must be resolved by the linker.
1089 Otherwise output the completed insn. */
1091 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1093 assert (fragP->fr_subtype != 1);
1094 assert (fragP->fr_cgen.insn != 0);
1095 cgen_record_fixup (fragP,
1096 /* Offset of branch insn in frag. */
1097 fragP->fr_fix + extension - 4,
1098 fragP->fr_cgen.insn,
1100 /* FIXME: quick hack */
1102 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1104 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1106 fragP->fr_cgen.opinfo,
1107 fragP->fr_symbol, fragP->fr_offset);
1110 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1112 md_number_to_chars (displacement, (valueT) addend,
1113 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1115 fragP->fr_fix += extension;
1118 /* Functions concerning relocs. */
1120 /* The location from which a PC relative jump should be calculated,
1121 given a PC relative reloc. */
1124 md_pcrel_from_section (fixP, sec)
1128 if (fixP->fx_addsy != (symbolS *) NULL
1129 && (! S_IS_DEFINED (fixP->fx_addsy)
1130 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1132 /* The symbol is undefined (or is defined but not in this section).
1133 Let the linker figure it out. */
1137 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1140 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1141 Returns BFD_RELOC_NONE if no reloc type can be found.
1142 *FIXP may be modified if desired. */
1144 bfd_reloc_code_real_type
1145 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1146 const CGEN_INSN * insn;
1147 const CGEN_OPERAND * operand;
1150 switch (CGEN_OPERAND_TYPE (operand))
1152 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1153 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1154 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1155 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1156 case M32R_OPERAND_HI16 :
1157 case M32R_OPERAND_SLO16 :
1158 case M32R_OPERAND_ULO16 :
1159 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1160 if (fixP->tc_fix_data.opinfo != 0)
1161 return fixP->tc_fix_data.opinfo;
1164 return BFD_RELOC_NONE;
1167 /* Called while parsing an instruction to create a fixup.
1168 We need to check for HI16 relocs and queue them up for later sorting. */
1171 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1174 const CGEN_INSN * insn;
1176 const CGEN_OPERAND * operand;
1180 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1181 operand, opinfo, exp);
1183 switch (CGEN_OPERAND_TYPE (operand))
1185 case M32R_OPERAND_HI16 :
1186 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1187 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1188 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1189 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1196 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1199 m32r_record_hi16 (reloc_type, fixP, seg)
1204 struct m32r_hi_fixup * hi_fixup;
1206 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1207 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1209 hi_fixup = ((struct m32r_hi_fixup *)
1210 xmalloc (sizeof (struct m32r_hi_fixup)));
1211 hi_fixup->fixp = fixP;
1212 hi_fixup->seg = now_seg;
1213 hi_fixup->next = m32r_hi_fixup_list;
1215 m32r_hi_fixup_list = hi_fixup;
1218 /* Return BFD reloc type from opinfo field in a fixS.
1219 It's tricky using fx_r_type in m32r_frob_file because the values
1220 are BFD_RELOC_UNUSED + operand number. */
1221 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1223 /* Sort any unmatched HI16 relocs so that they immediately precede
1224 the corresponding LO16 reloc. This is called before md_apply_fix and
1230 struct m32r_hi_fixup * l;
1232 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1234 segment_info_type * seginfo;
1237 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1238 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1240 /* Check quickly whether the next fixup happens to be a matching low. */
1241 if (l->fixp->fx_next != NULL
1242 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1243 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1244 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1247 /* Look through the fixups for this segment for a matching `low'.
1248 When we find one, move the high/shigh just in front of it. We do
1249 this in two passes. In the first pass, we try to find a
1250 unique `low'. In the second pass, we permit multiple high's
1251 relocs for a single `low'. */
1252 seginfo = seg_info (l->seg);
1253 for (pass = 0; pass < 2; pass++)
1259 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1261 /* Check whether this is a `low' fixup which matches l->fixp. */
1262 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1263 && f->fx_addsy == l->fixp->fx_addsy
1264 && f->fx_offset == l->fixp->fx_offset
1267 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1268 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1269 || prev->fx_addsy != f->fx_addsy
1270 || prev->fx_offset != f->fx_offset))
1274 /* Move l->fixp before f. */
1275 for (pf = &seginfo->fix_root;
1277 pf = & (* pf)->fx_next)
1278 assert (* pf != NULL);
1280 * pf = l->fixp->fx_next;
1282 l->fixp->fx_next = f;
1284 seginfo->fix_root = l->fixp;
1286 prev->fx_next = l->fixp;
1298 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1299 "Unmatched high/shigh reloc");
1304 /* See whether we need to force a relocation into the output file.
1305 This is used to force out switch and PC relative relocations when
1309 m32r_force_relocation (fix)
1315 return (fix->fx_pcrel
1319 /* Write a value out to the object file, using the appropriate endianness. */
1322 md_number_to_chars (buf, val, n)
1327 if (target_big_endian)
1328 number_to_chars_bigendian (buf, val, n);
1330 number_to_chars_littleendian (buf, val, n);
1333 /* Turn a string in input_line_pointer into a floating point constant of type
1334 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1335 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1338 /* Equal to MAX_PRECISION in atof-ieee.c */
1339 #define MAX_LITTLENUMS 6
1342 md_atof (type, litP, sizeP)
1349 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1350 LITTLENUM_TYPE * wordP;
1352 char * atof_ieee ();
1370 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1374 return "Bad call to md_atof()";
1377 t = atof_ieee (input_line_pointer, type, words);
1379 input_line_pointer = t;
1380 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1382 if (target_big_endian)
1384 for (i = 0; i < prec; i++)
1386 md_number_to_chars (litP, (valueT) words[i],
1387 sizeof (LITTLENUM_TYPE));
1388 litP += sizeof (LITTLENUM_TYPE);
1393 for (i = prec - 1; i >= 0; i--)
1395 md_number_to_chars (litP, (valueT) words[i],
1396 sizeof (LITTLENUM_TYPE));
1397 litP += sizeof (LITTLENUM_TYPE);