1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 const CGEN_INSN * insn;
32 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
34 char buffer [CGEN_MAX_INSN_SIZE];
41 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
42 boundary (i.e. was the first of two 16 bit insns). */
43 static m32r_insn prev_insn;
45 /* Non-zero if we've seen a relaxable insn since the last 32 bit
47 static int seen_relaxable_p = 0;
49 /* Non-zero if -relax specified, in which case sufficient relocs are output
50 for the linker to do relaxing.
51 We do simple forms of relaxing internally, but they are always done.
52 This flag does not apply to them. */
53 static int m32r_relax;
55 /* If non-NULL, pointer to cpu description file to read.
56 This allows runtime additions to the assembler. */
57 static char * m32r_cpu_desc;
59 /* start-sanitize-m32rx */
60 /* Non-zero if -m32rx has been specified, in which case support for the
61 extended M32RX instruction set should be enabled. */
62 static int enable_m32rx = 0;
64 /* Non-zero if the programmer should be warned when an explicit parallel
65 instruction might have constraint violations. */
66 static int warn_explicit_parallel_conflicts = 1;
67 /* end-sanitize-m32rx */
69 /* stuff for .scomm symbols. */
70 static segT sbss_section;
71 static asection scom_section;
72 static asymbol scom_symbol;
74 const char comment_chars[] = ";";
75 const char line_comment_chars[] = "#";
76 const char line_separator_chars[] = "";
77 const char EXP_CHARS[] = "eE";
78 const char FLT_CHARS[] = "dD";
80 /* Relocations against symbols are done in two
81 parts, with a HI relocation and a LO relocation. Each relocation
82 has only 16 bits of space to store an addend. This means that in
83 order for the linker to handle carries correctly, it must be able
84 to locate both the HI and the LO relocation. This means that the
85 relocations must appear in order in the relocation table.
87 In order to implement this, we keep track of each unmatched HI
88 relocation. We then sort them so that they immediately precede the
89 corresponding LO relocation. */
93 struct m32r_hi_fixup * next; /* Next HI fixup. */
94 fixS * fixp; /* This fixup. */
95 segT seg; /* The section this fixup is in. */
99 /* The list of unmatched HI relocs. */
101 static struct m32r_hi_fixup * m32r_hi_fixup_list;
104 /* start-sanitize-m32rx */
111 if (stdoutput != NULL)
112 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
113 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
115 /* end-sanitize-m32rx */
117 const char * md_shortopts = "";
119 struct option md_longopts[] =
121 /* start-sanitize-m32rx */
122 #define OPTION_M32RX (OPTION_MD_BASE)
123 {"m32rx", no_argument, NULL, OPTION_M32RX},
124 #define OPTION_WARN (OPTION_MD_BASE + 1)
125 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN},
126 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
127 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
128 /* end-sanitize-m32rx */
130 #if 0 /* not supported yet */
131 #define OPTION_RELAX (OPTION_MD_BASE + 3)
132 {"relax", no_argument, NULL, OPTION_RELAX},
133 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
134 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
137 {NULL, no_argument, NULL, 0}
139 size_t md_longopts_size = sizeof (md_longopts);
142 md_parse_option (c, arg)
148 /* start-sanitize-m32rx */
154 warn_explicit_parallel_conflicts = 1;
158 warn_explicit_parallel_conflicts = 0;
160 /* end-sanitize-m32rx */
162 #if 0 /* not supported yet */
166 case OPTION_CPU_DESC:
177 md_show_usage (stream)
180 fprintf (stream, "M32R/X options:\n");
181 /* start-sanitize-m32rx */
183 --m32rx support the extended m32rx instruction set\n");
186 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\
187 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
188 /* end-sanitize-m32rx */
192 --relax create linker relaxable code\n");
194 --cpu-desc provide runtime cpu description file\n");
198 static void fill_insn PARAMS ((int));
199 static void m32r_scomm PARAMS ((int));
201 /* Set by md_assemble for use by m32r_fill_insn. */
202 static subsegT prev_subseg;
203 static segT prev_seg;
205 /* The target specific pseudo-ops which we support. */
206 const pseudo_typeS md_pseudo_table[] =
209 { "fillinsn", fill_insn, 0 },
210 { "scomm", m32r_scomm, 0 },
211 /* start-sanitize-m32rx */
212 { "m32r", allow_m32rx, 0},
213 { "m32rx", allow_m32rx, 1},
214 /* end-sanitize-m32rx */
218 /* FIXME: Should be machine generated. */
219 #define NOP_INSN 0x7000
220 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
222 /* When we align the .text section, insert the correct NOP pattern.
223 N is the power of 2 alignment. LEN is the length of pattern FILL.
224 MAX is the maximum number of characters to skip when doing the alignment,
225 or 0 if there is no maximum. */
228 m32r_do_align (n, fill, len, max)
234 if ((fill == NULL || (* fill == 0 && len == 1))
235 && (now_seg->flags & SEC_CODE) != 0
236 /* Only do this special handling if aligning to at least a
239 /* Only do this special handling if we're allowed to emit at
241 && (max == 0 || max > 1))
243 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
246 /* First align to a 2 byte boundary, in case there is an odd .byte. */
247 /* FIXME: How much memory will cause gas to use when assembling a big
248 program? Perhaps we can avoid the frag_align call? */
249 frag_align (1, 0, 0);
251 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
253 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
254 /* If doing larger alignments use a repeating sequence of appropriate
258 static const unsigned char multi_nop_pattern[] =
259 { 0x70, 0x00, 0xf0, 0x00 };
260 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
270 assemble_nop (opcode)
273 char * f = frag_more (2);
274 md_number_to_chars (f, opcode, 2);
277 /* If the last instruction was the first of 2 16 bit insns,
278 output a nop to move the PC to a 32 bit boundary.
280 This is done via an alignment specification since branch relaxing
281 may make it unnecessary.
283 Internally, we need to output one of these each time a 32 bit insn is
284 seen after an insn that is relaxable. */
290 (void) m32r_do_align (2, NULL, 0, 0);
291 prev_insn.insn = NULL;
292 seen_relaxable_p = 0;
295 /* Cover function to fill_insn called after a label and at end of assembly.
297 The result is always 1: we're called in a conditional to see if the
298 current line is a label. */
301 m32r_fill_insn (done)
307 if (prev_seg != NULL)
312 subseg_set (prev_seg, prev_subseg);
316 subseg_set (seg, subseg);
329 /* Initialize the `cgen' interface. */
331 /* This is a callback from cgen to gas to parse operands. */
332 cgen_parse_operand_fn = cgen_parse_operand;
334 /* Set the machine number and endian. */
335 CGEN_SYM (init_asm) (0 /* mach number */,
337 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
339 #if 0 /* not supported yet */
340 /* If a runtime cpu description file was provided, parse it. */
341 if (m32r_cpu_desc != NULL)
345 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
347 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
351 /* Save the current subseg so we can restore it [it's the default one and
352 we don't want the initial section to be .sbss]. */
356 /* The sbss section is for local .scomm symbols. */
357 sbss_section = subseg_new (".sbss", 0);
359 /* This is copied from perform_an_assembly_pass. */
360 applicable = bfd_applicable_section_flags (stdoutput);
361 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
363 #if 0 /* What does this do? [see perform_an_assembly_pass] */
364 seg_info (bss_section)->bss = 1;
367 subseg_set (seg, subseg);
369 /* We must construct a fake section similar to bfd_com_section
370 but with the name .scommon. */
371 scom_section = bfd_com_section;
372 scom_section.name = ".scommon";
373 scom_section.output_section = & scom_section;
374 scom_section.symbol = & scom_symbol;
375 scom_section.symbol_ptr_ptr = & scom_section.symbol;
376 scom_symbol = * bfd_com_section.symbol;
377 scom_symbol.name = ".scommon";
378 scom_symbol.section = & scom_section;
380 /* start-sanitize-m32rx */
381 allow_m32rx (enable_m32rx);
382 /* end-sanitize-m32rx */
385 #ifdef HAVE_CPU_M32RX
387 /* Returns non zero if the given instruction writes to a destination register. */
389 writes_to_dest_reg (insn)
390 const CGEN_INSN * insn;
392 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
395 /* Scan the syntax string looking for a destination register. */
396 while ((c = (* syntax ++)) != 0)
397 if (c == 128 + M32R_OPERAND_DR)
403 /* Returns non zero if the given instruction reads from a source register.
404 Ignores the first 'num_ignore' macthes in the syntax string. */
406 reads_from_src_reg (insn, num_ignore)
407 const CGEN_INSN * insn;
410 unsigned char * syntax = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
413 /* Scan the syntax string looking for a source register. */
414 while ((c = (* syntax ++)) != 0)
416 if ( c == 128 + M32R_OPERAND_SR
417 || c == 128 + M32R_OPERAND_SRC1
418 || c == 128 + M32R_OPERAND_SRC2)
420 if (num_ignore -- > 0)
430 /* Returns the integer value of the destination register held in the fields. */
431 #define get_dest_reg(fields) (fields).f_r1
433 /* Returns an integer representing the source register of the given type. */
435 get_src_reg (syntax_field, fields)
436 unsigned char syntax_field;
437 CGEN_FIELDS * fields;
439 switch (syntax_field)
441 case 128 + M32R_OPERAND_SR: return fields->f_r2;
442 /* Relies upon the fact that no instruction with a $src1 operand
443 also has a $dr operand. */
444 case 128 + M32R_OPERAND_SRC1: return fields->f_r1;
445 case 128 + M32R_OPERAND_SRC2: return fields->f_r2;
446 default: abort(); return -1;
450 /* Returns zero iff the output register of instruction 'a'
451 is an input register to instruction 'b'. */
453 check_parallel_io_clash (a, b)
457 if (writes_to_dest_reg (a->insn))
459 unsigned char syntax_field;
462 while (syntax_field = reads_from_src_reg (b->insn, skip ++))
464 if (get_src_reg (syntax_field, & b->fields) == get_dest_reg (a->fields))
473 /* Returns NULL if the two 16 bit insns can be executed in parallel,
474 otherwise it returns a pointer to an error message explaining why not. */
476 can_make_parallel (a, b)
480 /* start-sanitize-m32rx */
484 /* Make sure the instructions are the right length. */
485 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
486 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
489 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
490 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
492 /* Make sure that the instructions use the correct execution pipelines. */
493 if ( a_pipe == PIPE_NONE
494 || b_pipe == PIPE_NONE)
495 return "Instructions do not use parallel execution pipelines.";
497 if ( a_pipe == PIPE_S
499 return "Instructions share the same execution pipeline";
501 /* end-sanitize-m32rx */
502 if ( writes_to_dest_reg (a->insn)
503 && writes_to_dest_reg (b->insn)
504 && (get_dest_reg (a->fields) == get_dest_reg (b->fields)))
505 return "Instructions write to the same destination register.";
512 make_parallel (buffer)
513 cgen_insn_t * buffer;
515 /* Force the top bit of the second insn to be set. */
519 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
521 value = bfd_getb16 ((bfd_byte *) buffer);
523 bfd_putb16 (value, (char *) buffer);
527 value = bfd_getl16 ((bfd_byte *) buffer);
529 bfd_putl16 (value, (char *) buffer);
534 make_parallel (buffer)
537 /* Force the top bit of the second insn to be set. */
539 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
544 /* start-sanitize-m32rx */
546 assemble_parallel_insn (str, str2)
555 * str2 = 0; /* Seperate the two instructions. */
557 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
558 so that the parallel instruction will start on a 32 bit boundary. */
562 /* Parse the first instruction. */
563 if (! (first.insn = CGEN_SYM (assemble_insn)
564 (str, & first.fields, first.buffer, & errmsg)))
570 /* Check to see if this is an allowable parallel insn. */
571 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
573 as_bad ("instruction '%s' cannot be executed in parallel.", str);
578 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
580 as_bad ("instruction '%s' is for the M32RX only", str);
584 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
585 str3 = str; /* Save the original string pointer. */
586 str = str2 + 2; /* Advanced past the parsed string. */
587 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
589 /* Preserve any fixups that have been generated and reset the list to empty. */
592 /* Parse the second instruction. */
593 if (! (second.insn = CGEN_SYM (assemble_insn)
594 (str, & second.fields, second.buffer, & errmsg)))
602 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
604 as_bad ("instruction '%s' is for the M32RX only", str);
610 if ( strcmp (first.insn->name, "nop") != 0
611 && strcmp (second.insn->name, "nop") != 0)
613 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
618 /* We assume that if the first instruction writes to a register that is
619 read by the second instruction it is because the programmer intended
620 this to happen, (after all they have explicitly requested that these
621 two instructions be executed in parallel). Although if the global
622 variable warn_explicit_parallel_conflicts is true then we do generate
623 a warning message. Similarly we assume that parallel branch and jump
624 instructions are deliberate and should not produce errors. */
626 if (can_make_parallel (& first, & second) == NULL)
628 if (warn_explicit_parallel_conflicts
629 && (! check_parallel_io_clash (& first, & second)))
630 as_warn ("%s: output of first instruction fails to overwrite input of second instruction.", str2);
632 /* Get the fixups for the first instruction. */
636 (void) cgen_asm_finish_insn (first.insn, first.buffer,
637 CGEN_FIELDS_BITSIZE (& first.fields));
639 /* Force the top bit of the second insn to be set. */
640 make_parallel (second.buffer);
642 /* Get its fixups. */
643 cgen_restore_fixups ();
646 (void) cgen_asm_finish_insn (second.insn, second.buffer,
647 CGEN_FIELDS_BITSIZE (& second.fields));
649 else if ((errmsg = (char *) can_make_parallel (& second, & first,
650 false, false)) == NULL)
652 if (warn_explicit_parallel_conflicts
653 && (! check_parallel_io_clash (& second, & first)))
654 as_warn ("%s: output of second instruction fails to overwrite input of first instruction.", str2);
656 /* Write out the second instruction first. */
657 (void) cgen_asm_finish_insn (second.insn, second.buffer,
658 CGEN_FIELDS_BITSIZE (& second.fields));
660 /* Force the top bit of the first instruction to be set. */
661 make_parallel (first.buffer);
663 /* Get the fixups for the first instruction. */
664 cgen_restore_fixups ();
666 /* Write out the first instruction. */
667 (void) cgen_asm_finish_insn (first.insn, first.buffer,
668 CGEN_FIELDS_BITSIZE (& first.fields));
672 as_bad ("'%s': %s", str2, errmsg);
676 /* Set these so m32r_fill_insn can use them. */
678 prev_subseg = now_subseg;
683 #endif /* HAVE_CPU_M32RX */
685 /* end-sanitize-m32rx */
696 /* Initialize GAS's cgen interface for a new instruction. */
697 cgen_asm_init_parse ();
699 /* start-sanitize-m32rx */
700 #ifdef HAVE_CPU_M32RX
701 /* Look for a parallel instruction seperator. */
702 if ((str2 = strstr (str, "||")) != NULL)
704 assemble_parallel_insn (str, str2);
708 /* end-sanitize-m32rx */
710 insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
717 /* start-sanitize-m32rx */
718 #ifdef HAVE_CPU_M32RX
719 if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
721 as_bad ("instruction '%s' is for the M32RX only", str);
725 /* end-sanitize-m32rx */
727 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
729 /* 32 bit insns must live on 32 bit boundaries. */
730 if (prev_insn.insn || seen_relaxable_p)
732 /* FIXME: If calling fill_insn too many times turns us into a memory
733 pig, can we call assemble_nop instead of !seen_relaxable_p? */
737 (void) cgen_asm_finish_insn (insn.insn, insn.buffer,
738 CGEN_FIELDS_BITSIZE (& insn.fields));
742 /* start-sanitize-m32rx */
743 /* start-sanitize-phase2-m32rx */
745 /* end-sanitize-phase2-m32rx */
746 /* end-sanitize-m32rx */
748 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
751 /* Keep track of whether we've seen a pair of 16 bit insns.
752 prev_insn.insn is NULL when we're on a 32 bit boundary. */
755 /* start-sanitize-m32rx */
756 /* start-sanitize-phase2-m32rx */
757 #ifdef HAVE_CPU_M32RX
758 /* Look to see if this instruction can be combined with the
759 previous instruction to make one, parallel, 32 bit instruction.
760 If the previous instruction (potentially) changed the flow of
761 program control, then it cannot be combined with the current
762 instruction. Also if the output of the previous instruction
763 is used as an input to the current instruction then it cannot
764 be combined. Otherwise call can_make_parallel() with both
765 orderings of the instructions to see if they can be combined. */
766 if ( ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_COND_CTI)
767 && ! CGEN_INSN_ATTR (prev_insn.insn, CGEN_INSN_UNCOND_CTI)
768 && check_parallel_io_clash (& prev_insn, &insn)
771 if (can_make_parallel (& prev_insn, & insn) == NULL)
772 make_parallel (insn.buffer);
773 else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
777 /* end-sanitize-phase2-m32rx */
778 /* end-sanitize-m32rx */
780 prev_insn.insn = NULL;
787 /* Record the frag that might be used by this insn. */
788 insn.frag = frag_now;
789 insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer,
790 CGEN_FIELDS_BITSIZE (& insn.fields));
792 /* start-sanitize-m32rx */
793 /* start-sanitize-phase2-m32rx */
794 #ifdef HAVE_CPU_M32RX
799 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
801 /* Swap the two insns */
802 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
803 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
805 make_parallel (insn.addr);
807 /* Swap any relaxable frags recorded for the two insns. */
808 if (prev_insn.frag->fr_opcode == prev_insn.addr)
810 prev_insn.frag->fr_opcode = insn.addr;
812 else if (insn.frag->fr_opcode == insn.addr)
814 insn.frag->fr_opcode = prev_insn.addr;
817 /* end-sanitize-phase2-m32rx */
819 /* Record where this instruction was assembled. */
820 prev_insn.addr = insn.addr;
821 prev_insn.frag = insn.frag;
823 /* end-sanitize-m32rx */
825 /* If the insn needs the following one to be on a 32 bit boundary
826 (e.g. subroutine calls), fill this insn's slot. */
828 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0)
831 /* If this is a relaxable insn (can be replaced with a larger version)
832 mark the fact so that we can emit an alignment directive for a
833 following 32 bit insn if we see one. */
834 if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0)
835 seen_relaxable_p = 1;
838 /* Set these so m32r_fill_insn can use them. */
840 prev_subseg = now_subseg;
843 /* The syntax in the manual says constants begin with '#'.
844 We just ignore it. */
847 md_operand (expressionP)
848 expressionS * expressionP;
850 if (* input_line_pointer == '#')
852 input_line_pointer ++;
853 expression (expressionP);
858 md_section_align (segment, size)
862 int align = bfd_get_section_alignment (stdoutput, segment);
863 return ((size + (1 << align) - 1) & (-1 << align));
867 md_undefined_symbol (name)
873 /* .scomm pseudo-op handler.
875 This is a new pseudo-op to handle putting objects in .scommon.
876 By doing this the linker won't need to do any work and more importantly
877 it removes the implicit -G arg necessary to correctly link the object file.
884 register char * name;
888 register symbolS * symbolP;
892 name = input_line_pointer;
893 c = get_symbol_end ();
895 /* just after name is now '\0' */
896 p = input_line_pointer;
899 if (* input_line_pointer != ',')
901 as_bad ("Expected comma after symbol-name: rest of line ignored.");
902 ignore_rest_of_line ();
906 input_line_pointer ++; /* skip ',' */
907 if ((size = get_absolute_expression ()) < 0)
909 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
910 ignore_rest_of_line ();
914 /* The third argument to .scomm is the alignment. */
915 if (* input_line_pointer != ',')
919 ++ input_line_pointer;
920 align = get_absolute_expression ();
923 as_warn ("ignoring bad alignment");
927 /* Convert to a power of 2 alignment. */
930 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
934 as_bad ("Common alignment not a power of 2");
935 ignore_rest_of_line ();
943 symbolP = symbol_find_or_make (name);
946 if (S_IS_DEFINED (symbolP))
948 as_bad ("Ignoring attempt to re-define symbol `%s'.",
949 S_GET_NAME (symbolP));
950 ignore_rest_of_line ();
954 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
956 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
957 S_GET_NAME (symbolP),
958 (long) S_GET_VALUE (symbolP),
961 ignore_rest_of_line ();
967 segT old_sec = now_seg;
968 int old_subsec = now_subseg;
971 record_alignment (sbss_section, align2);
972 subseg_set (sbss_section, 0);
975 frag_align (align2, 0, 0);
977 if (S_GET_SEGMENT (symbolP) == sbss_section)
978 symbolP->sy_frag->fr_symbol = 0;
980 symbolP->sy_frag = frag_now;
982 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
985 S_SET_SIZE (symbolP, size);
986 S_SET_SEGMENT (symbolP, sbss_section);
987 S_CLEAR_EXTERNAL (symbolP);
988 subseg_set (old_sec, old_subsec);
992 S_SET_VALUE (symbolP, (valueT) size);
993 S_SET_ALIGN (symbolP, align2);
994 S_SET_EXTERNAL (symbolP);
995 S_SET_SEGMENT (symbolP, & scom_section);
998 demand_empty_rest_of_line ();
1001 /* Interface to relax_segment. */
1003 /* FIXME: Build table by hand, get it working, then machine generate. */
1005 const relax_typeS md_relax_table[] =
1008 1) most positive reach of this state,
1009 2) most negative reach of this state,
1010 3) how many bytes this mode will add to the size of the current frag
1011 4) which index into the table to try if we can't fit into this one. */
1013 /* The first entry must be unused because an `rlx_more' value of zero ends
1017 /* The displacement used by GAS is from the end of the 2 byte insn,
1018 so we subtract 2 from the following. */
1019 /* 16 bit insn, 8 bit disp -> 10 bit range.
1020 This doesn't handle a branch in the right slot at the border:
1021 the "& -4" isn't taken into account. It's not important enough to
1022 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1024 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1025 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1026 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1027 /* Same thing, but with leading nop for alignment. */
1028 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1032 m32r_relax_frag (fragP, stretch)
1036 /* Address of branch insn. */
1037 long address = fragP->fr_address + fragP->fr_fix - 2;
1040 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1041 if (fragP->fr_subtype == 2)
1043 if ((address & 3) != 0)
1045 fragP->fr_subtype = 3;
1049 else if (fragP->fr_subtype == 3)
1051 if ((address & 3) == 0)
1053 fragP->fr_subtype = 2;
1059 growth = relax_frag (fragP, stretch);
1061 /* Long jump on odd halfword boundary? */
1062 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1064 fragP->fr_subtype = 3;
1072 /* Return an initial guess of the length by which a fragment must grow to
1073 hold a branch to reach its destination.
1074 Also updates fr_type/fr_subtype as necessary.
1076 Called just before doing relaxation.
1077 Any symbol that is now undefined will not become defined.
1078 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1079 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1080 Although it may not be explicit in the frag, pretend fr_var starts with a
1084 md_estimate_size_before_relax (fragP, segment)
1088 int old_fr_fix = fragP->fr_fix;
1089 char * opcode = fragP->fr_opcode;
1091 /* The only thing we have to handle here are symbols outside of the
1092 current segment. They may be undefined or in a different segment in
1093 which case linker scripts may place them anywhere.
1094 However, we can't finish the fragment here and emit the reloc as insn
1095 alignment requirements may move the insn about. */
1097 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1099 /* The symbol is undefined in this segment.
1100 Change the relaxation subtype to the max allowable and leave
1101 all further handling to md_convert_frag. */
1102 fragP->fr_subtype = 2;
1104 #if 0 /* Can't use this, but leave in for illustration. */
1105 /* Change 16 bit insn to 32 bit insn. */
1108 /* Increase known (fixed) size of fragment. */
1111 /* Create a relocation for it. */
1112 fix_new (fragP, old_fr_fix, 4,
1114 fragP->fr_offset, 1 /* pcrel */,
1115 /* FIXME: Can't use a real BFD reloc here.
1116 cgen_md_apply_fix3 can't handle it. */
1117 BFD_RELOC_M32R_26_PCREL);
1119 /* Mark this fragment as finished. */
1123 const CGEN_INSN * insn;
1126 /* Update the recorded insn.
1127 Fortunately we don't have to look very far.
1128 FIXME: Change this to record in the instruction the next higher
1129 relaxable insn to use. */
1130 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1132 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1133 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1135 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1141 fragP->fr_cgen.insn = insn;
1147 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1150 /* *fragP has been relaxed to its final size, and now needs to have
1151 the bytes inside it modified to conform to the new size.
1153 Called after relaxation is finished.
1154 fragP->fr_type == rs_machine_dependent.
1155 fragP->fr_subtype is the subtype of what the address relaxed to. */
1158 md_convert_frag (abfd, sec, fragP)
1164 char * displacement;
1170 opcode = fragP->fr_opcode;
1172 /* Address opcode resides at in file space. */
1173 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1175 switch (fragP->fr_subtype)
1179 displacement = & opcode[1];
1184 displacement = & opcode[1];
1187 opcode[2] = opcode[0] | 0x80;
1188 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1189 opcode_address += 2;
1191 displacement = & opcode[3];
1197 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1199 /* symbol must be resolved by linker */
1200 if (fragP->fr_offset & 3)
1201 as_warn ("Addend to unresolved symbol not on word boundary.");
1202 addend = fragP->fr_offset >> 2;
1206 /* Address we want to reach in file space. */
1207 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1208 target_address += fragP->fr_symbol->sy_frag->fr_address;
1209 addend = (target_address - (opcode_address & -4)) >> 2;
1212 /* Create a relocation for symbols that must be resolved by the linker.
1213 Otherwise output the completed insn. */
1215 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1217 assert (fragP->fr_subtype != 1);
1218 assert (fragP->fr_cgen.insn != 0);
1219 cgen_record_fixup (fragP,
1220 /* Offset of branch insn in frag. */
1221 fragP->fr_fix + extension - 4,
1222 fragP->fr_cgen.insn,
1224 /* FIXME: quick hack */
1226 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1228 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1230 fragP->fr_cgen.opinfo,
1231 fragP->fr_symbol, fragP->fr_offset);
1234 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1236 md_number_to_chars (displacement, (valueT) addend,
1237 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1239 fragP->fr_fix += extension;
1242 /* Functions concerning relocs. */
1244 /* The location from which a PC relative jump should be calculated,
1245 given a PC relative reloc. */
1248 md_pcrel_from_section (fixP, sec)
1252 if (fixP->fx_addsy != (symbolS *) NULL
1253 && (! S_IS_DEFINED (fixP->fx_addsy)
1254 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1256 /* The symbol is undefined (or is defined but not in this section).
1257 Let the linker figure it out. */
1261 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1264 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1265 Returns BFD_RELOC_NONE if no reloc type can be found.
1266 *FIXP may be modified if desired. */
1268 bfd_reloc_code_real_type
1269 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1270 const CGEN_INSN * insn;
1271 const CGEN_OPERAND * operand;
1274 switch (CGEN_OPERAND_TYPE (operand))
1276 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1277 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1278 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1279 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1280 case M32R_OPERAND_HI16 :
1281 case M32R_OPERAND_SLO16 :
1282 case M32R_OPERAND_ULO16 :
1283 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1284 if (fixP->tc_fix_data.opinfo != 0)
1285 return fixP->tc_fix_data.opinfo;
1288 return BFD_RELOC_NONE;
1291 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1294 m32r_record_hi16 (reloc_type, fixP, seg)
1299 struct m32r_hi_fixup * hi_fixup;
1301 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1302 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1304 hi_fixup = ((struct m32r_hi_fixup *)
1305 xmalloc (sizeof (struct m32r_hi_fixup)));
1306 hi_fixup->fixp = fixP;
1307 hi_fixup->seg = now_seg;
1308 hi_fixup->next = m32r_hi_fixup_list;
1310 m32r_hi_fixup_list = hi_fixup;
1313 /* Called while parsing an instruction to create a fixup.
1314 We need to check for HI16 relocs and queue them up for later sorting. */
1317 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1320 const CGEN_INSN * insn;
1322 const CGEN_OPERAND * operand;
1326 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1327 operand, opinfo, exp);
1329 switch (CGEN_OPERAND_TYPE (operand))
1331 case M32R_OPERAND_HI16 :
1332 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1333 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1334 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1335 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1342 /* Return BFD reloc type from opinfo field in a fixS.
1343 It's tricky using fx_r_type in m32r_frob_file because the values
1344 are BFD_RELOC_UNUSED + operand number. */
1345 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1347 /* Sort any unmatched HI16 relocs so that they immediately precede
1348 the corresponding LO16 reloc. This is called before md_apply_fix and
1354 struct m32r_hi_fixup * l;
1356 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1358 segment_info_type * seginfo;
1361 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1362 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1364 /* Check quickly whether the next fixup happens to be a matching low. */
1365 if (l->fixp->fx_next != NULL
1366 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1367 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1368 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1371 /* Look through the fixups for this segment for a matching `low'.
1372 When we find one, move the high/shigh just in front of it. We do
1373 this in two passes. In the first pass, we try to find a
1374 unique `low'. In the second pass, we permit multiple high's
1375 relocs for a single `low'. */
1376 seginfo = seg_info (l->seg);
1377 for (pass = 0; pass < 2; pass++)
1383 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1385 /* Check whether this is a `low' fixup which matches l->fixp. */
1386 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1387 && f->fx_addsy == l->fixp->fx_addsy
1388 && f->fx_offset == l->fixp->fx_offset
1391 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1392 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1393 || prev->fx_addsy != f->fx_addsy
1394 || prev->fx_offset != f->fx_offset))
1398 /* Move l->fixp before f. */
1399 for (pf = &seginfo->fix_root;
1401 pf = & (* pf)->fx_next)
1402 assert (* pf != NULL);
1404 * pf = l->fixp->fx_next;
1406 l->fixp->fx_next = f;
1408 seginfo->fix_root = l->fixp;
1410 prev->fx_next = l->fixp;
1422 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1423 "Unmatched high/shigh reloc");
1428 /* See whether we need to force a relocation into the output file.
1429 This is used to force out switch and PC relative relocations when
1433 m32r_force_relocation (fix)
1439 return (fix->fx_pcrel
1443 /* Write a value out to the object file, using the appropriate endianness. */
1446 md_number_to_chars (buf, val, n)
1451 if (target_big_endian)
1452 number_to_chars_bigendian (buf, val, n);
1454 number_to_chars_littleendian (buf, val, n);
1457 /* Turn a string in input_line_pointer into a floating point constant of type
1458 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1459 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1462 /* Equal to MAX_PRECISION in atof-ieee.c */
1463 #define MAX_LITTLENUMS 6
1466 md_atof (type, litP, sizeP)
1473 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1474 LITTLENUM_TYPE * wordP;
1476 char * atof_ieee ();
1494 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1498 return "Bad call to md_atof()";
1501 t = atof_ieee (input_line_pointer, type, words);
1503 input_line_pointer = t;
1504 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1506 if (target_big_endian)
1508 for (i = 0; i < prec; i++)
1510 md_number_to_chars (litP, (valueT) words[i],
1511 sizeof (LITTLENUM_TYPE));
1512 litP += sizeof (LITTLENUM_TYPE);
1517 for (i = prec - 1; i >= 0; i--)
1519 md_number_to_chars (litP, (valueT) words[i],
1520 sizeof (LITTLENUM_TYPE));
1521 litP += sizeof (LITTLENUM_TYPE);