1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "opcodes/m32r-desc.h"
27 #include "opcodes/m32r-opc.h"
30 /* Linked list of symbols that are debugging symbols to be defined as the
31 beginning of the current instruction. */
32 typedef struct sym_link
34 struct sym_link *next;
38 static sym_linkS *debug_sym_link = (sym_linkS *)0;
40 /* Structure to hold all of the different components describing
41 an individual instruction. */
44 const CGEN_INSN * insn;
45 const CGEN_INSN * orig_insn;
48 CGEN_INSN_INT buffer [1];
49 #define INSN_VALUE(buf) (*(buf))
51 unsigned char buffer [CGEN_MAX_INSN_SIZE];
52 #define INSN_VALUE(buf) (buf)
57 fixS * fixups [GAS_CGEN_MAX_FIXUPS];
58 int indices [MAX_OPERAND_INSTANCES];
59 sym_linkS *debug_sym_link;
63 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
64 boundary (i.e. was the first of two 16 bit insns). */
65 static m32r_insn prev_insn;
67 /* Non-zero if we've seen a relaxable insn since the last 32 bit
69 static int seen_relaxable_p = 0;
71 /* Non-zero if -relax specified, in which case sufficient relocs are output
72 for the linker to do relaxing.
73 We do simple forms of relaxing internally, but they are always done.
74 This flag does not apply to them. */
75 static int m32r_relax;
77 #if 0 /* not supported yet */
78 /* If non-NULL, pointer to cpu description file to read.
79 This allows runtime additions to the assembler. */
80 static const char * m32r_cpu_desc;
83 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
84 Each high/shigh reloc must be paired with it's low cousin in order to
85 properly calculate the addend in a relocatable link (since there is a
86 potential carry from the low to the high/shigh).
87 This option is off by default though for user-written assembler code it
88 might make sense to make the default be on (i.e. have gcc pass a flag
89 to turn it off). This warning must not be on for GCC created code as
90 optimization may delete the low but not the high/shigh (at least we
91 shouldn't assume or require it to). */
92 static int warn_unmatched_high = 0;
94 /* start-sanitize-cygnus */
95 /* Non-zero if -m32rx has been specified, in which case support for the
96 extended M32RX instruction set should be enabled. */
97 static int enable_m32rx = 0;
99 /* Non-zero if -m32rx -hidden has been specified, in which case support for
100 the special M32RX instruction set should be enabled. */
101 static int enable_special = 0;
103 /* Non-zero if the programmer should be warned when an explicit parallel
104 instruction might have constraint violations. */
105 static int warn_explicit_parallel_conflicts = 1;
107 /* Non-zero if insns can be made parallel. */
109 /* end-sanitize-cygnus */
111 /* stuff for .scomm symbols. */
112 static segT sbss_section;
113 static asection scom_section;
114 static asymbol scom_symbol;
116 const char comment_chars[] = ";";
117 const char line_comment_chars[] = "#";
118 const char line_separator_chars[] = "";
119 const char EXP_CHARS[] = "eE";
120 const char FLT_CHARS[] = "dD";
122 /* Relocations against symbols are done in two
123 parts, with a HI relocation and a LO relocation. Each relocation
124 has only 16 bits of space to store an addend. This means that in
125 order for the linker to handle carries correctly, it must be able
126 to locate both the HI and the LO relocation. This means that the
127 relocations must appear in order in the relocation table.
129 In order to implement this, we keep track of each unmatched HI
130 relocation. We then sort them so that they immediately precede the
131 corresponding LO relocation. */
135 struct m32r_hi_fixup * next; /* Next HI fixup. */
136 fixS * fixp; /* This fixup. */
137 segT seg; /* The section this fixup is in. */
141 /* The list of unmatched HI relocs. */
143 static struct m32r_hi_fixup * m32r_hi_fixup_list;
146 /* start-sanitize-cygnus */
153 if (stdoutput != NULL)
154 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
155 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
157 /* end-sanitize-cygnus */
159 #define M32R_SHORTOPTS ""
160 /* start-sanitize-cygnus */
161 #undef M32R_SHORTOPTS
162 #define M32R_SHORTOPTS "O"
163 /* end-sanitize-cygnus */
164 const char * md_shortopts = M32R_SHORTOPTS;
166 struct option md_longopts[] =
168 /* start-sanitize-cygnus */
169 #define OPTION_M32RX (OPTION_MD_BASE)
170 {"m32rx", no_argument, NULL, OPTION_M32RX},
171 #define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
172 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
173 {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
174 #define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2)
175 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
176 {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
177 #define OPTION_SPECIAL (OPTION_MD_BASE + 3)
178 {"hidden", no_argument, NULL, OPTION_SPECIAL},
179 /* end-sanitize-cygnus */
181 /* Sigh. I guess all warnings must now have both variants. */
182 #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
183 {"warn-unmatched-high", OPTION_WARN_UNMATCHED},
184 {"Wuh", OPTION_WARN_UNMATCHED},
185 #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
186 {"no-warn-unmatched-high", OPTION_WARN_UNMATCHED},
187 {"Wnuh", OPTION_WARN_UNMATCHED},
189 #if 0 /* not supported yet */
190 #define OPTION_RELAX (OPTION_MD_BASE + 6)
191 {"relax", no_argument, NULL, OPTION_RELAX},
192 #define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
193 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
196 {NULL, no_argument, NULL, 0}
198 size_t md_longopts_size = sizeof (md_longopts);
201 md_parse_option (c, arg)
207 /* start-sanitize-cygnus */
216 case OPTION_WARN_PARALLEL:
217 warn_explicit_parallel_conflicts = 1;
220 case OPTION_NO_WARN_PARALLEL:
221 warn_explicit_parallel_conflicts = 0;
229 extern char * myname;
231 /* Pretend that we do not recognise this option. */
232 fprintf (stderr, _("%s: unrecognised option: -hidden\n"), myname);
236 /* end-sanitize-cygnus */
238 case OPTION_WARN_UNMATCHED:
239 warn_unmatched_high = 1;
242 case OPTION_NO_WARN_UNMATCHED:
243 warn_unmatched_high = 0;
246 #if 0 /* not supported yet */
250 case OPTION_CPU_DESC:
262 md_show_usage (stream)
265 fprintf (stream, _(" M32R specific command line options:\n"));
267 /* start-sanitize-cygnus */
268 fprintf (stream, _("\
269 -m32rx support the extended m32rx instruction set\n"));
270 fprintf (stream, _("\
271 -O try to combine instructions in parallel\n"));
273 fprintf (stream, _("\
274 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
275 fprintf (stream, _("\
276 violate contraints\n"));
277 fprintf (stream, _("\
278 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
279 fprintf (stream, _("\
280 instructions violate contraints\n"));
281 fprintf (stream, _("\
282 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
283 fprintf (stream, _("\
284 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
285 /* end-sanitize-cygnus */
287 fprintf (stream, _("\
288 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
289 fprintf (stream, _("\
290 -no-warn-unmatched-high do not warn about missing low relocs\n"));
291 fprintf (stream, _("\
292 -Wuh synonym for -warn-unmatched-high\n"));
293 fprintf (stream, _("\
294 -Wnuh synonym for -no-warn-unmatched-high\n"));
297 fprintf (stream, _("\
298 -relax create linker relaxable code\n"));
299 fprintf (stream, _("\
300 -cpu-desc provide runtime cpu description file\n"));
304 static void fill_insn PARAMS ((int));
305 static void m32r_scomm PARAMS ((int));
306 static void debug_sym PARAMS ((int));
307 static void expand_debug_syms PARAMS ((sym_linkS *, int));
309 /* Set by md_assemble for use by m32r_fill_insn. */
310 static subsegT prev_subseg;
311 static segT prev_seg;
313 /* The target specific pseudo-ops which we support. */
314 const pseudo_typeS md_pseudo_table[] =
317 { "fillinsn", fill_insn, 0 },
318 { "scomm", m32r_scomm, 0 },
319 { "debugsym", debug_sym, 0 },
320 /* start-sanitize-cygnus */
321 /* Not documented as so far there is no need for them.... */
322 { "m32r", allow_m32rx, 0 },
323 { "m32rx", allow_m32rx, 1 },
324 /* end-sanitize-cygnus */
328 /* FIXME: Should be machine generated. */
329 #define NOP_INSN 0x7000
330 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
332 /* When we align the .text section, insert the correct NOP pattern.
333 N is the power of 2 alignment. LEN is the length of pattern FILL.
334 MAX is the maximum number of characters to skip when doing the alignment,
335 or 0 if there is no maximum. */
338 m32r_do_align (n, fill, len, max)
344 /* Only do this if the fill pattern wasn't specified. */
346 && (now_seg->flags & SEC_CODE) != 0
347 /* Only do this special handling if aligning to at least a
350 /* Only do this special handling if we're allowed to emit at
352 && (max == 0 || max > 1))
354 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
357 /* First align to a 2 byte boundary, in case there is an odd .byte. */
358 /* FIXME: How much memory will cause gas to use when assembling a big
359 program? Perhaps we can avoid the frag_align call? */
360 frag_align (1, 0, 0);
362 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
364 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
365 /* If doing larger alignments use a repeating sequence of appropriate
369 static const unsigned char multi_nop_pattern[] =
370 { 0x70, 0x00, 0xf0, 0x00 };
371 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
375 prev_insn.insn = NULL;
382 /* If the last instruction was the first of 2 16 bit insns,
383 output a nop to move the PC to a 32 bit boundary.
385 This is done via an alignment specification since branch relaxing
386 may make it unnecessary.
388 Internally, we need to output one of these each time a 32 bit insn is
389 seen after an insn that is relaxable. */
395 (void) m32r_do_align (2, NULL, 0, 0);
396 prev_insn.insn = NULL;
397 seen_relaxable_p = 0;
400 /* Record the symbol so that when we output the insn, we can create
401 a symbol that is at the start of the instruction. This is used
402 to emit the label for the start of a breakpoint without causing
403 the assembler to emit a NOP if the previous instruction was a
404 16 bit instruction. */
412 register char *end_name;
413 register symbolS *symbolP;
414 register sym_linkS *link;
416 name = input_line_pointer;
417 delim = get_symbol_end ();
418 end_name = input_line_pointer;
420 if ((symbolP = symbol_find (name)) == NULL
421 && (symbolP = md_undefined_symbol (name)) == NULL)
423 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
426 symbol_table_insert (symbolP);
427 if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section)
428 /* xgettext:c-format */
429 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
433 link = (sym_linkS *) xmalloc (sizeof (sym_linkS));
434 link->symbol = symbolP;
435 link->next = debug_sym_link;
436 debug_sym_link = link;
441 demand_empty_rest_of_line ();
444 /* Second pass to expanding the debug symbols, go through linked
445 list of symbols and reassign the address. */
448 expand_debug_syms (syms, align)
452 char *save_input_line = input_line_pointer;
453 sym_linkS *next_syms;
458 (void) m32r_do_align (align, NULL, 0, 0);
459 for (; syms != (sym_linkS *)0; syms = next_syms)
461 symbolS *symbolP = syms->symbol;
462 next_syms = syms->next;
463 input_line_pointer = ".\n";
464 pseudo_set (symbolP);
468 input_line_pointer = save_input_line;
471 /* Cover function to fill_insn called after a label and at end of assembly.
472 The result is always 1: we're called in a conditional to see if the
473 current line is a label. */
476 m32r_fill_insn (done)
479 if (prev_seg != NULL)
482 subsegT subseg = now_subseg;
484 subseg_set (prev_seg, prev_subseg);
488 subseg_set (seg, subseg);
491 if (done && debug_sym_link)
493 expand_debug_syms (debug_sym_link, 1);
494 debug_sym_link = (sym_linkS *)0;
507 /* Initialize the `cgen' interface. */
509 /* Set the machine number and endian. */
510 gas_cgen_cpu_desc = m32r_cgen_cpu_open (0 /* mach number */,
513 : CGEN_ENDIAN_LITTLE);
514 m32r_cgen_init_asm (gas_cgen_cpu_desc);
516 /* The operand instance table is used during optimization to determine
517 which insns can be executed in parallel. It is also used to give
518 warnings regarding operand interference in parallel insns. */
519 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc);
521 /* This is a callback from cgen to gas to parse operands. */
522 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
524 #if 0 /* not supported yet */
525 /* If a runtime cpu description file was provided, parse it. */
526 if (m32r_cpu_desc != NULL)
530 errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc);
532 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
536 /* Save the current subseg so we can restore it [it's the default one and
537 we don't want the initial section to be .sbss]. */
541 /* The sbss section is for local .scomm symbols. */
542 sbss_section = subseg_new (".sbss", 0);
544 /* This is copied from perform_an_assembly_pass. */
545 applicable = bfd_applicable_section_flags (stdoutput);
546 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
548 #if 0 /* What does this do? [see perform_an_assembly_pass] */
549 seg_info (bss_section)->bss = 1;
552 subseg_set (seg, subseg);
554 /* We must construct a fake section similar to bfd_com_section
555 but with the name .scommon. */
556 scom_section = bfd_com_section;
557 scom_section.name = ".scommon";
558 scom_section.output_section = & scom_section;
559 scom_section.symbol = & scom_symbol;
560 scom_section.symbol_ptr_ptr = & scom_section.symbol;
561 scom_symbol = * bfd_com_section.symbol;
562 scom_symbol.name = ".scommon";
563 scom_symbol.section = & scom_section;
565 /* start-sanitize-cygnus */
566 allow_m32rx (enable_m32rx);
567 /* end-sanitize-cygnus */
570 /* start-sanitize-cygnus */
572 #define OPERAND_IS_COND_BIT(operand, indices, index) \
573 ((operand)->hw->type == HW_H_COND \
574 || ((operand)->hw->type == HW_H_PSW) \
575 || ((operand)->hw->type == HW_H_CR \
576 && (indices [index] == 0 || indices [index] == 1)))
578 /* Returns true if an output of instruction 'a' is referenced by an operand
579 of instruction 'b'. If 'check_outputs' is true then b's outputs are
580 checked, otherwise its inputs are examined. */
583 first_writes_to_seconds_operands (a, b, check_outputs)
586 const int check_outputs;
588 const CGEN_OPINST * a_operands = CGEN_INSN_OPERANDS (a->insn);
589 const CGEN_OPINST * b_ops = CGEN_INSN_OPERANDS (b->insn);
592 /* If at least one of the instructions takes no operands, then there is
593 nothing to check. There really are instructions without operands,
595 if (a_operands == NULL || b_ops == NULL)
598 /* Scan the operand list of 'a' looking for an output operand. */
600 a_operands->type != CGEN_OPINST_END;
601 a_index ++, a_operands ++)
603 if (a_operands->type == CGEN_OPINST_OUTPUT)
606 const CGEN_OPINST * b_operands = b_ops;
609 The Condition bit 'C' is a shadow of the CBR register (control
610 register 1) and also a shadow of bit 31 of the program status
611 word (control register 0). For now this is handled here, rather
614 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
616 /* Scan operand list of 'b' looking for another reference to the
617 condition bit, which goes in the right direction. */
619 b_operands->type != CGEN_OPINST_END;
620 b_index ++, b_operands ++)
622 if ((b_operands->type
625 : CGEN_OPINST_INPUT))
626 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
632 /* Scan operand list of 'b' looking for an operand that
633 references the same hardware element, and which goes in the
636 b_operands->type != CGEN_OPINST_END;
637 b_index ++, b_operands ++)
639 if ((b_operands->type
642 : CGEN_OPINST_INPUT))
643 && (b_operands->hw == a_operands->hw)
644 && (a->indices [a_index] == b->indices [b_index]))
654 /* Returns true if the insn can (potentially) alter the program counter. */
660 #if 0 /* Once PC operands are working.... */
661 const CGEN_OPINST * a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc,
664 if (a_operands == NULL)
667 while (a_operands->type != CGEN_OPINST_END)
669 if (a_operands->operand != NULL
670 && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, a_operands->operand) == M32R_OPERAND_PC)
676 if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
677 || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
683 /* Returns NULL if the two 16 bit insns can be executed in parallel,
684 otherwise it returns a pointer to an error message explaining why not. */
687 can_make_parallel (a, b)
694 /* Make sure the instructions are the right length. */
695 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
696 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
699 if (first_writes_to_seconds_operands (a, b, true))
700 return _("Instructions write to the same destination register.");
702 a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
703 b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
705 /* Make sure that the instructions use the correct execution pipelines. */
706 if ( a_pipe == PIPE_NONE
707 || b_pipe == PIPE_NONE)
708 return _("Instructions do not use parallel execution pipelines.");
710 /* Leave this test for last, since it is the only test that can
711 go away if the instructions are swapped, and we want to make
712 sure that any other errors are detected before this happens. */
713 if ( a_pipe == PIPE_S
715 return _("Instructions share the same execution pipeline");
720 /* Force the top bit of the second 16-bit insn to be set. */
723 make_parallel (buffer)
724 CGEN_INSN_BYTES_PTR buffer;
729 buffer [CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
734 /* Same as make_parallel except buffer contains the bytes in target order. */
737 target_make_parallel (buffer)
740 buffer [CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
744 /* Assemble two instructions with an explicit parallel operation (||) or
745 sequential operation (->). */
748 assemble_two_insns (str, str2, parallel_p)
757 char save_str2 = *str2;
759 * str2 = 0; /* Seperate the two instructions. */
761 /* Make sure the two insns begin on a 32 bit boundary.
762 This is also done for the serial case (foo -> bar), relaxing doesn't
763 affect insns written like this.
764 Note that we must always do this as we can't assume anything about
765 whether we're currently on a 32 bit boundary or not. Relaxing may
769 first.debug_sym_link = debug_sym_link;
770 debug_sym_link = (sym_linkS *)0;
772 /* Parse the first instruction. */
773 if (! (first.insn = m32r_cgen_assemble_insn
774 (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg)))
781 if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
783 /* xgettext:c-format */
784 as_bad (_("not a 16 bit instruction '%s'"), str);
787 else if (! enable_special
788 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
790 /* xgettext:c-format */
791 as_bad (_("unknown instruction '%s'"), str);
794 else if (! enable_m32rx
795 /* FIXME: Need standard macro to perform this test. */
796 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
798 /* xgettext:c-format */
799 as_bad (_("instruction '%s' is for the M32RX only"), str);
803 /* Check to see if this is an allowable parallel insn. */
804 if (parallel_p && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
806 /* xgettext:c-format */
807 as_bad (_("instruction '%s' cannot be executed in parallel."), str);
811 *str2 = save_str2; /* Restore the original assembly text, just in case it is needed. */
812 str3 = str; /* Save the original string pointer. */
813 str = str2 + 2; /* Advanced past the parsed string. */
814 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
816 /* Convert the opcode to lower case. */
820 while (isspace (*s2 ++))
825 while (isalnum (*s2))
827 if (isupper ((unsigned char) *s2))
833 /* Preserve any fixups that have been generated and reset the list to empty. */
834 gas_cgen_save_fixups ();
836 /* Get the indices of the operands of the instruction. */
837 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
838 doesn't seem right. Perhaps allow passing fields like we do insn. */
839 /* FIXME: ALIAS insns do not have operands, so we use this function
840 to find the equivalent insn and overwrite the value stored in our
841 structure. We still need the original insn, however, since this
842 may have certain attributes that are not present in the unaliased
843 version (eg relaxability). When aliases behave differently this
844 may have to change. */
845 first.orig_insn = first.insn;
847 CGEN_FIELDS tmp_fields;
848 first.insn = cgen_lookup_get_insn_operands
849 (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
850 first.indices, &tmp_fields);
853 if (first.insn == NULL)
854 as_fatal (_("internal error: lookup/get operands failed"));
856 second.debug_sym_link = NULL;
858 /* Parse the second instruction. */
859 if (! (second.insn = m32r_cgen_assemble_insn
860 (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg)))
867 if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
869 /* xgettext:c-format */
870 as_bad (_("not a 16 bit instruction '%s'"), str);
873 else if (! enable_special
874 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
876 /* xgettext:c-format */
877 as_bad (_("unknown instruction '%s'"), str);
880 else if (! enable_m32rx
881 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
883 /* xgettext:c-format */
884 as_bad (_("instruction '%s' is for the M32RX only"), str);
888 /* Check to see if this is an allowable parallel insn. */
889 if (parallel_p && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
891 /* xgettext:c-format */
892 as_bad (_("instruction '%s' cannot be executed in parallel."), str);
896 if (parallel_p && ! enable_m32rx)
898 if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
899 && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
901 /* xgettext:c-format */
902 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
907 /* Get the indices of the operands of the instruction. */
908 second.orig_insn = second.insn;
910 CGEN_FIELDS tmp_fields;
911 second.insn = cgen_lookup_get_insn_operands
912 (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
913 second.indices, &tmp_fields);
916 if (second.insn == NULL)
917 as_fatal (_("internal error: lookup/get operands failed"));
919 /* We assume that if the first instruction writes to a register that is
920 read by the second instruction it is because the programmer intended
921 this to happen, (after all they have explicitly requested that these
922 two instructions be executed in parallel). Although if the global
923 variable warn_explicit_parallel_conflicts is true then we do generate
924 a warning message. Similarly we assume that parallel branch and jump
925 instructions are deliberate and should not produce errors. */
927 if (parallel_p && warn_explicit_parallel_conflicts)
929 if (first_writes_to_seconds_operands (& first, & second, false))
930 /* xgettext:c-format */
931 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
933 if (first_writes_to_seconds_operands (& second, & first, false))
934 /* xgettext:c-format */
935 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
939 || (errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
941 /* Get the fixups for the first instruction. */
942 gas_cgen_swap_fixups ();
945 expand_debug_syms (first.debug_sym_link, 1);
946 gas_cgen_finish_insn (first.orig_insn, first.buffer,
947 CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
949 /* Force the top bit of the second insn to be set. */
951 make_parallel (second.buffer);
953 /* Get its fixups. */
954 gas_cgen_restore_fixups ();
957 expand_debug_syms (second.debug_sym_link, 1);
958 gas_cgen_finish_insn (second.orig_insn, second.buffer,
959 CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
961 /* Try swapping the instructions to see if they work that way. */
962 else if (can_make_parallel (& second, & first) == NULL)
964 /* Write out the second instruction first. */
965 expand_debug_syms (second.debug_sym_link, 1);
966 gas_cgen_finish_insn (second.orig_insn, second.buffer,
967 CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
969 /* Force the top bit of the first instruction to be set. */
970 make_parallel (first.buffer);
972 /* Get the fixups for the first instruction. */
973 gas_cgen_restore_fixups ();
975 /* Write out the first instruction. */
976 expand_debug_syms (first.debug_sym_link, 1);
977 gas_cgen_finish_insn (first.orig_insn, first.buffer,
978 CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
982 as_bad ("'%s': %s", str2, errmsg);
986 /* Set these so m32r_fill_insn can use them. */
988 prev_subseg = now_subseg;
991 /* end-sanitize-cygnus */
1002 /* Initialize GAS's cgen interface for a new instruction. */
1003 gas_cgen_init_parse ();
1005 /* start-sanitize-cygnus */
1006 /* Look for a parallel instruction seperator. */
1007 if ((str2 = strstr (str, "||")) != NULL)
1009 assemble_two_insns (str, str2, 1);
1013 /* Also look for a sequential instruction seperator. */
1014 if ((str2 = strstr (str, "->")) != NULL)
1016 assemble_two_insns (str, str2, 0);
1019 /* end-sanitize-cygnus */
1021 insn.debug_sym_link = debug_sym_link;
1022 debug_sym_link = (sym_linkS *)0;
1024 insn.insn = m32r_cgen_assemble_insn
1025 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
1033 /* start-sanitize-cygnus */
1034 if (! enable_special
1035 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
1037 /* xgettext:c-format */
1038 as_bad (_("unknown instruction '%s'"), str);
1041 else if (! enable_m32rx
1042 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
1044 /* xgettext:c-format */
1045 as_bad (_("instruction '%s' is for the M32RX only"), str);
1048 /* end-sanitize-cygnus */
1050 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
1052 /* 32 bit insns must live on 32 bit boundaries. */
1053 if (prev_insn.insn || seen_relaxable_p)
1055 /* ??? If calling fill_insn too many times turns us into a memory
1056 pig, can we call a fn to assemble a nop instead of
1057 !seen_relaxable_p? */
1061 expand_debug_syms (insn.debug_sym_link, 2);
1063 /* Doesn't really matter what we pass for RELAX_P here. */
1064 gas_cgen_finish_insn (insn.insn, insn.buffer,
1065 CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
1069 int on_32bit_boundary_p;
1070 /* start-sanitize-cygnus */
1072 /* end-sanitize-cygnus */
1074 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
1077 insn.orig_insn = insn.insn;
1078 /* start-sanitize-cygnus */
1079 /* If the previous insn was relaxable, then it may be expanded
1080 to fill the current 16 bit slot. Emit a NOP here to occupy
1081 this slot, so that we can start at optimizing at a 32 bit
1083 if (prev_insn.insn && seen_relaxable_p && optimize)
1088 /* Get the indices of the operands of the instruction.
1089 FIXME: See assemble_parallel for notes on orig_insn. */
1091 CGEN_FIELDS tmp_fields;
1092 insn.insn = cgen_lookup_get_insn_operands
1093 (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
1094 16, insn.indices, &tmp_fields);
1097 if (insn.insn == NULL)
1098 as_fatal (_("internal error: lookup/get operands failed"));
1100 /* end-sanitize-cygnus */
1102 /* Compute whether we're on a 32 bit boundary or not.
1103 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1104 on_32bit_boundary_p = prev_insn.insn == NULL;
1106 /* start-sanitize-cygnus */
1107 /* Look to see if this instruction can be combined with the
1108 previous instruction to make one, parallel, 32 bit instruction.
1109 If the previous instruction (potentially) changed the flow of
1110 program control, then it cannot be combined with the current
1111 instruction. If the current instruction is relaxable, then it
1112 might be replaced with a longer version, so we cannot combine it.
1113 Also if the output of the previous instruction is used as an
1114 input to the current instruction then it cannot be combined.
1115 Otherwise call can_make_parallel() with both orderings of the
1116 instructions to see if they can be combined. */
1117 if ( ! on_32bit_boundary_p
1120 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
1121 && ! writes_to_pc (& prev_insn)
1122 && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
1125 if (can_make_parallel (& prev_insn, & insn) == NULL)
1126 make_parallel (insn.buffer);
1127 else if (can_make_parallel (& insn, & prev_insn) == NULL)
1130 /* end-sanitize-cygnus */
1132 expand_debug_syms (insn.debug_sym_link, 1);
1138 /* Ensure each pair of 16 bit insns is in the same frag. */
1141 gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
1142 CGEN_FIELDS_BITSIZE (& insn.fields),
1143 1 /*relax_p*/, &fi);
1144 insn.addr = fi.addr;
1145 insn.frag = fi.frag;
1146 insn.num_fixups = fi.num_fixups;
1147 for (i = 0; i < fi.num_fixups; ++i)
1148 insn.fixups[i] = fi.fixups[i];
1151 /* start-sanitize-cygnus */
1156 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1158 /* Swap the two insns */
1159 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
1160 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
1162 target_make_parallel (insn.addr);
1164 /* Swap any relaxable frags recorded for the two insns. */
1165 /* FIXME: Clarify. relaxation precludes parallel insns */
1166 if (prev_insn.frag->fr_opcode == prev_insn.addr)
1167 prev_insn.frag->fr_opcode = insn.addr;
1168 else if (insn.frag->fr_opcode == insn.addr)
1169 insn.frag->fr_opcode = prev_insn.addr;
1171 /* Update the addresses in any fixups.
1172 Note that we don't have to handle the case where each insn is in
1173 a different frag as we ensure they're in the same frag above. */
1174 for (i = 0; i < prev_insn.num_fixups; ++i)
1175 prev_insn.fixups[i]->fx_where += 2;
1176 for (i = 0; i < insn.num_fixups; ++i)
1177 insn.fixups[i]->fx_where -= 2;
1179 /* end-sanitize-cygnus */
1181 /* Keep track of whether we've seen a pair of 16 bit insns.
1182 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1183 if (on_32bit_boundary_p)
1186 prev_insn.insn = NULL;
1188 /* If the insn needs the following one to be on a 32 bit boundary
1189 (e.g. subroutine calls), fill this insn's slot. */
1190 if (on_32bit_boundary_p
1191 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
1194 /* If this is a relaxable insn (can be replaced with a larger version)
1195 mark the fact so that we can emit an alignment directive for a
1196 following 32 bit insn if we see one. */
1197 if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
1198 seen_relaxable_p = 1;
1201 /* Set these so m32r_fill_insn can use them. */
1203 prev_subseg = now_subseg;
1206 /* The syntax in the manual says constants begin with '#'.
1207 We just ignore it. */
1210 md_operand (expressionP)
1211 expressionS * expressionP;
1213 if (* input_line_pointer == '#')
1215 input_line_pointer ++;
1216 expression (expressionP);
1221 md_section_align (segment, size)
1225 int align = bfd_get_section_alignment (stdoutput, segment);
1226 return ((size + (1 << align) - 1) & (-1 << align));
1230 md_undefined_symbol (name)
1236 /* .scomm pseudo-op handler.
1238 This is a new pseudo-op to handle putting objects in .scommon.
1239 By doing this the linker won't need to do any work and more importantly
1240 it removes the implicit -G arg necessary to correctly link the object file.
1247 register char * name;
1251 register symbolS * symbolP;
1255 name = input_line_pointer;
1256 c = get_symbol_end ();
1258 /* just after name is now '\0' */
1259 p = input_line_pointer;
1262 if (* input_line_pointer != ',')
1264 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1265 ignore_rest_of_line ();
1269 input_line_pointer ++; /* skip ',' */
1270 if ((size = get_absolute_expression ()) < 0)
1272 /* xgettext:c-format */
1273 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
1274 ignore_rest_of_line ();
1278 /* The third argument to .scomm is the alignment. */
1279 if (* input_line_pointer != ',')
1283 ++ input_line_pointer;
1284 align = get_absolute_expression ();
1287 as_warn (_("ignoring bad alignment"));
1291 /* Convert to a power of 2 alignment. */
1294 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
1298 as_bad (_("Common alignment not a power of 2"));
1299 ignore_rest_of_line ();
1307 symbolP = symbol_find_or_make (name);
1310 if (S_IS_DEFINED (symbolP))
1312 /* xgettext:c-format */
1313 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1314 S_GET_NAME (symbolP));
1315 ignore_rest_of_line ();
1319 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
1321 /* xgettext:c-format */
1322 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1323 S_GET_NAME (symbolP),
1324 (long) S_GET_VALUE (symbolP),
1327 ignore_rest_of_line ();
1333 segT old_sec = now_seg;
1334 int old_subsec = now_subseg;
1337 record_alignment (sbss_section, align2);
1338 subseg_set (sbss_section, 0);
1341 frag_align (align2, 0, 0);
1343 if (S_GET_SEGMENT (symbolP) == sbss_section)
1344 symbolP->sy_frag->fr_symbol = 0;
1346 symbolP->sy_frag = frag_now;
1348 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
1351 S_SET_SIZE (symbolP, size);
1352 S_SET_SEGMENT (symbolP, sbss_section);
1353 S_CLEAR_EXTERNAL (symbolP);
1354 subseg_set (old_sec, old_subsec);
1358 S_SET_VALUE (symbolP, (valueT) size);
1359 S_SET_ALIGN (symbolP, align2);
1360 S_SET_EXTERNAL (symbolP);
1361 S_SET_SEGMENT (symbolP, & scom_section);
1364 demand_empty_rest_of_line ();
1367 /* Interface to relax_segment. */
1369 /* FIXME: Build table by hand, get it working, then machine generate. */
1371 const relax_typeS md_relax_table[] =
1374 1) most positive reach of this state,
1375 2) most negative reach of this state,
1376 3) how many bytes this mode will add to the size of the current frag
1377 4) which index into the table to try if we can't fit into this one. */
1379 /* The first entry must be unused because an `rlx_more' value of zero ends
1383 /* The displacement used by GAS is from the end of the 2 byte insn,
1384 so we subtract 2 from the following. */
1385 /* 16 bit insn, 8 bit disp -> 10 bit range.
1386 This doesn't handle a branch in the right slot at the border:
1387 the "& -4" isn't taken into account. It's not important enough to
1388 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1390 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1391 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1392 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1393 /* Same thing, but with leading nop for alignment. */
1394 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1398 m32r_relax_frag (fragP, stretch)
1402 /* Address of branch insn. */
1403 long address = fragP->fr_address + fragP->fr_fix - 2;
1406 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1407 if (fragP->fr_subtype == 2)
1409 if ((address & 3) != 0)
1411 fragP->fr_subtype = 3;
1415 else if (fragP->fr_subtype == 3)
1417 if ((address & 3) == 0)
1419 fragP->fr_subtype = 2;
1425 growth = relax_frag (fragP, stretch);
1427 /* Long jump on odd halfword boundary? */
1428 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1430 fragP->fr_subtype = 3;
1438 /* Return an initial guess of the length by which a fragment must grow to
1439 hold a branch to reach its destination.
1440 Also updates fr_type/fr_subtype as necessary.
1442 Called just before doing relaxation.
1443 Any symbol that is now undefined will not become defined.
1444 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1445 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1446 Although it may not be explicit in the frag, pretend fr_var starts with a
1450 md_estimate_size_before_relax (fragP, segment)
1454 int old_fr_fix = fragP->fr_fix;
1456 /* The only thing we have to handle here are symbols outside of the
1457 current segment. They may be undefined or in a different segment in
1458 which case linker scripts may place them anywhere.
1459 However, we can't finish the fragment here and emit the reloc as insn
1460 alignment requirements may move the insn about. */
1462 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1464 /* The symbol is undefined in this segment.
1465 Change the relaxation subtype to the max allowable and leave
1466 all further handling to md_convert_frag. */
1467 fragP->fr_subtype = 2;
1469 #if 0 /* Can't use this, but leave in for illustration. */
1470 /* Change 16 bit insn to 32 bit insn. */
1471 fragP->fr_opcode[0] |= 0x80;
1473 /* Increase known (fixed) size of fragment. */
1476 /* Create a relocation for it. */
1477 fix_new (fragP, old_fr_fix, 4,
1479 fragP->fr_offset, 1 /* pcrel */,
1480 /* FIXME: Can't use a real BFD reloc here.
1481 gas_cgen_md_apply_fix3 can't handle it. */
1482 BFD_RELOC_M32R_26_PCREL);
1484 /* Mark this fragment as finished. */
1488 const CGEN_INSN * insn;
1491 /* Update the recorded insn.
1492 Fortunately we don't have to look very far.
1493 FIXME: Change this to record in the instruction the next higher
1494 relaxable insn to use. */
1495 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1497 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1498 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1500 && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX))
1506 fragP->fr_cgen.insn = insn;
1512 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1515 /* *fragP has been relaxed to its final size, and now needs to have
1516 the bytes inside it modified to conform to the new size.
1518 Called after relaxation is finished.
1519 fragP->fr_type == rs_machine_dependent.
1520 fragP->fr_subtype is the subtype of what the address relaxed to. */
1523 md_convert_frag (abfd, sec, fragP)
1529 char * displacement;
1535 opcode = fragP->fr_opcode;
1537 /* Address opcode resides at in file space. */
1538 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1540 switch (fragP->fr_subtype)
1544 displacement = & opcode[1];
1549 displacement = & opcode[1];
1552 opcode[2] = opcode[0] | 0x80;
1553 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1554 opcode_address += 2;
1556 displacement = & opcode[3];
1562 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1564 /* symbol must be resolved by linker */
1565 if (fragP->fr_offset & 3)
1566 as_warn (_("Addend to unresolved symbol not on word boundary."));
1567 addend = fragP->fr_offset >> 2;
1571 /* Address we want to reach in file space. */
1572 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1573 target_address += fragP->fr_symbol->sy_frag->fr_address;
1574 addend = (target_address - (opcode_address & -4)) >> 2;
1577 /* Create a relocation for symbols that must be resolved by the linker.
1578 Otherwise output the completed insn. */
1580 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1582 assert (fragP->fr_subtype != 1);
1583 assert (fragP->fr_cgen.insn != 0);
1584 gas_cgen_record_fixup (fragP,
1585 /* Offset of branch insn in frag. */
1586 fragP->fr_fix + extension - 4,
1587 fragP->fr_cgen.insn,
1589 /* FIXME: quick hack */
1591 CGEN_OPERAND_ENTRY (gas_cgen_cpu_desc,
1592 fragP->fr_cgen.opindex),
1594 CGEN_OPERAND_ENTRY (gas_cgen_cpu_desc,
1595 M32R_OPERAND_DISP24),
1597 fragP->fr_cgen.opinfo,
1598 fragP->fr_symbol, fragP->fr_offset);
1601 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1603 md_number_to_chars (displacement, (valueT) addend,
1604 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1606 fragP->fr_fix += extension;
1609 /* Functions concerning relocs. */
1611 /* The location from which a PC relative jump should be calculated,
1612 given a PC relative reloc. */
1615 md_pcrel_from_section (fixP, sec)
1619 if (fixP->fx_addsy != (symbolS *) NULL
1620 && (! S_IS_DEFINED (fixP->fx_addsy)
1621 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1623 /* The symbol is undefined (or is defined but not in this section).
1624 Let the linker figure it out. */
1628 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1631 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1632 Returns BFD_RELOC_NONE if no reloc type can be found.
1633 *FIXP may be modified if desired. */
1635 bfd_reloc_code_real_type
1636 md_cgen_lookup_reloc (insn, operand, fixP)
1637 const CGEN_INSN * insn;
1638 const CGEN_OPERAND * operand;
1641 switch (CGEN_OPERAND_TYPE (gas_cgen_cpu_desc, operand))
1643 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1644 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1645 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1646 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1647 case M32R_OPERAND_HI16 :
1648 case M32R_OPERAND_SLO16 :
1649 case M32R_OPERAND_ULO16 :
1650 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1651 if (fixP->tc_fix_data.opinfo != 0)
1652 return fixP->tc_fix_data.opinfo;
1654 default : /* avoid -Wall warning */
1657 return BFD_RELOC_NONE;
1660 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1663 m32r_record_hi16 (reloc_type, fixP, seg)
1668 struct m32r_hi_fixup * hi_fixup;
1670 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1671 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1673 hi_fixup = ((struct m32r_hi_fixup *)
1674 xmalloc (sizeof (struct m32r_hi_fixup)));
1675 hi_fixup->fixp = fixP;
1676 hi_fixup->seg = now_seg;
1677 hi_fixup->next = m32r_hi_fixup_list;
1679 m32r_hi_fixup_list = hi_fixup;
1682 /* Called while parsing an instruction to create a fixup.
1683 We need to check for HI16 relocs and queue them up for later sorting. */
1686 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1689 const CGEN_INSN * insn;
1691 const CGEN_OPERAND * operand;
1695 fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
1696 operand, opinfo, exp);
1698 switch (CGEN_OPERAND_TYPE (gas_cgen_cpu_desc, operand))
1700 case M32R_OPERAND_HI16 :
1701 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1702 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1703 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1704 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1706 default : /* avoid -Wall warning */
1713 /* Return BFD reloc type from opinfo field in a fixS.
1714 It's tricky using fx_r_type in m32r_frob_file because the values
1715 are BFD_RELOC_UNUSED + operand number. */
1716 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1718 /* Sort any unmatched HI16 relocs so that they immediately precede
1719 the corresponding LO16 reloc. This is called before md_apply_fix and
1725 struct m32r_hi_fixup * l;
1727 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1729 segment_info_type * seginfo;
1732 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1733 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1735 /* Check quickly whether the next fixup happens to be a matching low. */
1736 if (l->fixp->fx_next != NULL
1737 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1738 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1739 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1742 /* Look through the fixups for this segment for a matching `low'.
1743 When we find one, move the high/shigh just in front of it. We do
1744 this in two passes. In the first pass, we try to find a
1745 unique `low'. In the second pass, we permit multiple high's
1746 relocs for a single `low'. */
1747 seginfo = seg_info (l->seg);
1748 for (pass = 0; pass < 2; pass++)
1754 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1756 /* Check whether this is a `low' fixup which matches l->fixp. */
1757 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1758 && f->fx_addsy == l->fixp->fx_addsy
1759 && f->fx_offset == l->fixp->fx_offset
1762 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1763 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1764 || prev->fx_addsy != f->fx_addsy
1765 || prev->fx_offset != f->fx_offset))
1769 /* Move l->fixp before f. */
1770 for (pf = &seginfo->fix_root;
1772 pf = & (* pf)->fx_next)
1773 assert (* pf != NULL);
1775 * pf = l->fixp->fx_next;
1777 l->fixp->fx_next = f;
1779 seginfo->fix_root = l->fixp;
1781 prev->fx_next = l->fixp;
1793 && warn_unmatched_high)
1794 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1795 _("Unmatched high/shigh reloc"));
1800 /* See whether we need to force a relocation into the output file.
1801 This is used to force out switch and PC relative relocations when
1805 m32r_force_relocation (fix)
1808 if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1809 || fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1815 return (fix->fx_pcrel
1819 /* Write a value out to the object file, using the appropriate endianness. */
1822 md_number_to_chars (buf, val, n)
1827 if (target_big_endian)
1828 number_to_chars_bigendian (buf, val, n);
1830 number_to_chars_littleendian (buf, val, n);
1833 /* Turn a string in input_line_pointer into a floating point constant of type
1834 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1835 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1838 /* Equal to MAX_PRECISION in atof-ieee.c */
1839 #define MAX_LITTLENUMS 6
1842 md_atof (type, litP, sizeP)
1849 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1851 char * atof_ieee ();
1869 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1873 return _("Bad call to md_atof()");
1876 t = atof_ieee (input_line_pointer, type, words);
1878 input_line_pointer = t;
1879 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1881 if (target_big_endian)
1883 for (i = 0; i < prec; i++)
1885 md_number_to_chars (litP, (valueT) words[i],
1886 sizeof (LITTLENUM_TYPE));
1887 litP += sizeof (LITTLENUM_TYPE);
1892 for (i = prec - 1; i >= 0; i--)
1894 md_number_to_chars (litP, (valueT) words[i],
1895 sizeof (LITTLENUM_TYPE));
1896 litP += sizeof (LITTLENUM_TYPE);
1904 m32r_elf_section_change_hook ()
1906 /* If we have reached the end of a section and we have just emitted a
1907 16 bit insn, then emit a nop to make sure that the section ends on
1908 a 32 bit boundary. */
1910 if (prev_insn.insn || seen_relaxable_p)
1911 (void) m32r_fill_insn (0);
1915 m32r_fix_adjustable (fixP)
1919 if (fixP->fx_addsy == NULL)
1922 /* Prevent all adjustments to global symbols. */
1923 if (S_IS_EXTERN (fixP->fx_addsy))
1925 if (S_IS_WEAK (fixP->fx_addsy))
1928 /* We need the symbol name for the VTABLE entries */
1929 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1930 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)