1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 /* Structure to hold all of the different components describing an individual instruction. */
30 const CGEN_INSN * insn;
33 cgen_insn_t buffer [CGEN_MAX_INSN_SIZE / sizeof (cgen_insn_t)];
35 char buffer [CGEN_MAX_INSN_SIZE];
39 int indices [MAX_OPERAND_INSTANCES];
43 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
44 boundary (i.e. was the first of two 16 bit insns). */
45 static m32r_insn prev_insn;
47 /* Non-zero if we've seen a relaxable insn since the last 32 bit
49 static int seen_relaxable_p = 0;
51 /* Non-zero if -relax specified, in which case sufficient relocs are output
52 for the linker to do relaxing.
53 We do simple forms of relaxing internally, but they are always done.
54 This flag does not apply to them. */
55 static int m32r_relax;
57 /* If non-NULL, pointer to cpu description file to read.
58 This allows runtime additions to the assembler. */
59 static char * m32r_cpu_desc;
61 /* start-sanitize-m32rx */
62 /* Non-zero if -m32rx has been specified, in which case support for the
63 extended M32RX instruction set should be enabled. */
64 static int enable_m32rx = 0;
66 /* Non-zero if the programmer should be warned when an explicit parallel
67 instruction might have constraint violations. */
68 static int warn_explicit_parallel_conflicts = 1;
69 /* end-sanitize-m32rx */
71 /* stuff for .scomm symbols. */
72 static segT sbss_section;
73 static asection scom_section;
74 static asymbol scom_symbol;
76 const char comment_chars[] = ";";
77 const char line_comment_chars[] = "#";
78 const char line_separator_chars[] = "";
79 const char EXP_CHARS[] = "eE";
80 const char FLT_CHARS[] = "dD";
82 /* Relocations against symbols are done in two
83 parts, with a HI relocation and a LO relocation. Each relocation
84 has only 16 bits of space to store an addend. This means that in
85 order for the linker to handle carries correctly, it must be able
86 to locate both the HI and the LO relocation. This means that the
87 relocations must appear in order in the relocation table.
89 In order to implement this, we keep track of each unmatched HI
90 relocation. We then sort them so that they immediately precede the
91 corresponding LO relocation. */
95 struct m32r_hi_fixup * next; /* Next HI fixup. */
96 fixS * fixp; /* This fixup. */
97 segT seg; /* The section this fixup is in. */
101 /* The list of unmatched HI relocs. */
103 static struct m32r_hi_fixup * m32r_hi_fixup_list;
106 /* start-sanitize-m32rx */
113 if (stdoutput != NULL)
114 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
115 enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
117 /* end-sanitize-m32rx */
119 const char * md_shortopts = "";
121 struct option md_longopts[] =
123 /* start-sanitize-m32rx */
124 #define OPTION_M32RX (OPTION_MD_BASE)
125 {"m32rx", no_argument, NULL, OPTION_M32RX},
126 #define OPTION_WARN (OPTION_MD_BASE + 1)
127 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN},
128 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
129 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
130 /* end-sanitize-m32rx */
132 #if 0 /* not supported yet */
133 #define OPTION_RELAX (OPTION_MD_BASE + 3)
134 {"relax", no_argument, NULL, OPTION_RELAX},
135 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
136 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
139 {NULL, no_argument, NULL, 0}
141 size_t md_longopts_size = sizeof (md_longopts);
144 md_parse_option (c, arg)
150 /* start-sanitize-m32rx */
156 warn_explicit_parallel_conflicts = 1;
160 warn_explicit_parallel_conflicts = 0;
162 /* end-sanitize-m32rx */
164 #if 0 /* not supported yet */
168 case OPTION_CPU_DESC:
179 md_show_usage (stream)
182 fprintf (stream, "M32R/X options:\n");
183 /* start-sanitize-m32rx */
185 --m32rx support the extended m32rx instruction set\n");
188 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\n");
190 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
191 /* end-sanitize-m32rx */
195 --relax create linker relaxable code\n");
197 --cpu-desc provide runtime cpu description file\n");
201 static void fill_insn PARAMS ((int));
202 static void m32r_scomm PARAMS ((int));
204 /* Set by md_assemble for use by m32r_fill_insn. */
205 static subsegT prev_subseg;
206 static segT prev_seg;
208 /* The target specific pseudo-ops which we support. */
209 const pseudo_typeS md_pseudo_table[] =
212 { "fillinsn", fill_insn, 0 },
213 { "scomm", m32r_scomm, 0 },
214 /* start-sanitize-m32rx */
215 { "m32r", allow_m32rx, 0},
216 { "m32rx", allow_m32rx, 1},
217 /* end-sanitize-m32rx */
221 /* FIXME: Should be machine generated. */
222 #define NOP_INSN 0x7000
223 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
225 /* When we align the .text section, insert the correct NOP pattern.
226 N is the power of 2 alignment. LEN is the length of pattern FILL.
227 MAX is the maximum number of characters to skip when doing the alignment,
228 or 0 if there is no maximum. */
231 m32r_do_align (n, fill, len, max)
237 if ((fill == NULL || (* fill == 0 && len == 1))
238 && (now_seg->flags & SEC_CODE) != 0
239 /* Only do this special handling if aligning to at least a
242 /* Only do this special handling if we're allowed to emit at
244 && (max == 0 || max > 1))
246 static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
249 /* First align to a 2 byte boundary, in case there is an odd .byte. */
250 /* FIXME: How much memory will cause gas to use when assembling a big
251 program? Perhaps we can avoid the frag_align call? */
252 frag_align (1, 0, 0);
254 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
256 frag_align_pattern (2, nop_pattern, sizeof nop_pattern, 0);
257 /* If doing larger alignments use a repeating sequence of appropriate
261 static const unsigned char multi_nop_pattern[] =
262 { 0x70, 0x00, 0xf0, 0x00 };
263 frag_align_pattern (n, multi_nop_pattern, sizeof multi_nop_pattern,
273 assemble_nop (opcode)
276 char * f = frag_more (2);
277 md_number_to_chars (f, opcode, 2);
280 /* If the last instruction was the first of 2 16 bit insns,
281 output a nop to move the PC to a 32 bit boundary.
283 This is done via an alignment specification since branch relaxing
284 may make it unnecessary.
286 Internally, we need to output one of these each time a 32 bit insn is
287 seen after an insn that is relaxable. */
293 (void) m32r_do_align (2, NULL, 0, 0);
294 prev_insn.insn = NULL;
295 seen_relaxable_p = 0;
298 /* Cover function to fill_insn called after a label and at end of assembly.
300 The result is always 1: we're called in a conditional to see if the
301 current line is a label. */
304 m32r_fill_insn (done)
310 if (prev_seg != NULL)
315 subseg_set (prev_seg, prev_subseg);
319 subseg_set (seg, subseg);
332 /* Initialize the `cgen' interface. */
334 /* This is a callback from cgen to gas to parse operands. */
335 cgen_parse_operand_fn = cgen_parse_operand;
337 /* Set the machine number and endian. */
338 CGEN_SYM (init_asm) (0 /* mach number */,
340 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
342 #if 0 /* not supported yet */
343 /* If a runtime cpu description file was provided, parse it. */
344 if (m32r_cpu_desc != NULL)
348 errmsg = cgen_read_cpu_file (m32r_cpu_desc);
350 as_bad ("%s: %s", m32r_cpu_desc, errmsg);
354 /* Save the current subseg so we can restore it [it's the default one and
355 we don't want the initial section to be .sbss]. */
359 /* The sbss section is for local .scomm symbols. */
360 sbss_section = subseg_new (".sbss", 0);
362 /* This is copied from perform_an_assembly_pass. */
363 applicable = bfd_applicable_section_flags (stdoutput);
364 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
366 #if 0 /* What does this do? [see perform_an_assembly_pass] */
367 seg_info (bss_section)->bss = 1;
370 subseg_set (seg, subseg);
372 /* We must construct a fake section similar to bfd_com_section
373 but with the name .scommon. */
374 scom_section = bfd_com_section;
375 scom_section.name = ".scommon";
376 scom_section.output_section = & scom_section;
377 scom_section.symbol = & scom_symbol;
378 scom_section.symbol_ptr_ptr = & scom_section.symbol;
379 scom_symbol = * bfd_com_section.symbol;
380 scom_symbol.name = ".scommon";
381 scom_symbol.section = & scom_section;
383 /* start-sanitize-m32rx */
384 allow_m32rx (enable_m32rx);
385 /* end-sanitize-m32rx */
388 /* start-sanitize-m32rx */
390 /* Returns true if an output of instruction 'a' is referenced by an operand
391 of instruction 'b'. If 'check_outputs' is true then b's outputs are
392 checked, otherwise its inputs are examined. */
394 first_writes_to_seconds_operands (a, b, check_outputs)
397 const int check_outputs;
399 const CGEN_OPERAND_INSTANCE * a_operands = CGEN_INSN_OPERANDS (a->insn);
400 const CGEN_OPERAND_INSTANCE * b_operands = CGEN_INSN_OPERANDS (b->insn);
403 /* If at least one of the instructions takes no operands, then there is
404 nothing to check. There really are instructions without operands,
406 if (a_operands == NULL || b_operands == NULL)
409 /* Scan the operand list of 'a' looking for an output operand. */
411 CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END;
412 a_index ++, a_operands ++)
414 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands) == CGEN_OPERAND_INSTANCE_OUTPUT)
418 /* Scan operand list of 'b' looking for an operand that references
419 the same hardware element, and which goes in the right direction. */
421 CGEN_OPERAND_INSTANCE_TYPE (b_operands) != CGEN_OPERAND_INSTANCE_END;
422 b_index ++, b_operands ++)
424 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands) ==
425 (check_outputs ? CGEN_OPERAND_INSTANCE_OUTPUT : CGEN_OPERAND_INSTANCE_INPUT))
426 && (CGEN_OPERAND_INSTANCE_HW (b_operands) == CGEN_OPERAND_INSTANCE_HW (a_operands))
427 && (a->indices [a_index] == b->indices [b_index]))
436 /* Returns true if the insn can (potentially) alter the program counter. */
442 const CGEN_OPERAND_INSTANCE * a_operands == CGEN_INSN_OPERANDS (a->insn);
444 if (a_operands == NULL)
447 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands) != CGEN_OPERAND_INSTANCE_END)
449 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands) != NULL
450 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands)) == M32R_OPERAND_PC)
456 if (CGEN_INSN_ATTR (a->insn, CGEN_INSN_UNCOND_CTI)
457 || CGEN_INSN_ATTR (a->insn, CGEN_INSN_COND_CTI))
463 /* Returns NULL if the two 16 bit insns can be executed in parallel,
464 otherwise it returns a pointer to an error message explaining why not. */
466 can_make_parallel (a, b)
473 /* Make sure the instructions are the right length. */
474 if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
475 || CGEN_FIELDS_BITSIZE (& b->fields) != 16)
478 if (first_writes_to_seconds_operands (a, b, true))
479 return "Instructions write to the same destination register.";
481 a_pipe = CGEN_INSN_ATTR (a->insn, CGEN_INSN_PIPE);
482 b_pipe = CGEN_INSN_ATTR (b->insn, CGEN_INSN_PIPE);
484 /* Make sure that the instructions use the correct execution pipelines. */
485 if ( a_pipe == PIPE_NONE
486 || b_pipe == PIPE_NONE)
487 return "Instructions do not use parallel execution pipelines.";
489 /* Leave this test for last, since it is the only test that can
490 go away if the instructions are swapped, and we want to make
491 sure that any other errors are detected before this happens. */
492 if ( a_pipe == PIPE_S
494 return "Instructions share the same execution pipeline";
501 make_parallel (buffer)
502 cgen_insn_t * buffer;
504 /* Force the top bit of the second insn to be set. */
508 if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
510 value = bfd_getb16 ((bfd_byte *) buffer);
512 bfd_putb16 (value, (char *) buffer);
516 value = bfd_getl16 ((bfd_byte *) buffer);
518 bfd_putl16 (value, (char *) buffer);
523 make_parallel (buffer)
526 /* Force the top bit of the second insn to be set. */
528 buffer [CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG ? 0 : 1] |= 0x80;
534 assemble_parallel_insn (str, str2)
543 * str2 = 0; /* Seperate the two instructions. */
545 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
546 so that the parallel instruction will start on a 32 bit boundary. */
550 /* Parse the first instruction. */
551 if (! (first.insn = CGEN_SYM (assemble_insn)
552 (str, & first.fields, first.buffer, & errmsg)))
558 /* Check to see if this is an allowable parallel insn. */
559 if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
561 as_bad ("instruction '%s' cannot be executed in parallel.", str);
566 && CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
568 as_bad ("instruction '%s' is for the M32RX only", str);
572 *str2 = '|'; /* Restore the original assembly text, just in case it is needed. */
573 str3 = str; /* Save the original string pointer. */
574 str = str2 + 2; /* Advanced past the parsed string. */
575 str2 = str3; /* Remember the entire string in case it is needed for error messages. */
577 /* Preserve any fixups that have been generated and reset the list to empty. */
580 /* Get the indicies of the operands of the instruction. */
581 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
582 doesn't seem right. Perhaps allow passing fields like we do insn. */
583 /* FIXME: ALIAS insns do not have operands, so we use this function
584 to find the equivalent insn and overwrite the value stored in our
585 structure. When aliases behave differently this may have to change. */
586 first.insn = m32r_cgen_get_insn_operands (first.insn, bfd_getb16 ((char *) first.buffer), 16,
588 if (first.insn == NULL)
589 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for first insn");
591 /* Parse the second instruction. */
592 if (! (second.insn = CGEN_SYM (assemble_insn)
593 (str, & second.fields, second.buffer, & errmsg)))
601 && CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
603 as_bad ("instruction '%s' is for the M32RX only", str);
609 if ( strcmp (first.insn->name, "nop") != 0
610 && strcmp (second.insn->name, "nop") != 0)
612 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2);
617 /* Get the indicies of the operands of the instruction. */
618 second.insn = m32r_cgen_get_insn_operands (second.insn, bfd_getb16 ((char *) second.buffer), 16,
620 if (second.insn == NULL)
621 as_fatal ("internal error: m32r_cgen_get_insn_operands failed for second insn");
623 /* We assume that if the first instruction writes to a register that is
624 read by the second instruction it is because the programmer intended
625 this to happen, (after all they have explicitly requested that these
626 two instructions be executed in parallel). Although if the global
627 variable warn_explicit_parallel_conflicts is true then we do generate
628 a warning message. Similarly we assume that parallel branch and jump
629 instructions are deliberate and should not produce errors. */
631 if (warn_explicit_parallel_conflicts)
633 if (first_writes_to_seconds_operands (& first, & second, false))
634 as_warn ("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?", str2);
636 if (first_writes_to_seconds_operands (& second, & first, false))
637 as_warn ("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?", str2);
640 if ((errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
642 /* Get the fixups for the first instruction. */
646 (void) cgen_asm_finish_insn (first.insn, first.buffer,
647 CGEN_FIELDS_BITSIZE (& first.fields));
649 /* Force the top bit of the second insn to be set. */
650 make_parallel (second.buffer);
652 /* Get its fixups. */
653 cgen_restore_fixups ();
656 (void) cgen_asm_finish_insn (second.insn, second.buffer,
657 CGEN_FIELDS_BITSIZE (& second.fields));
659 /* Try swapping the instructions to see if they work that way. */
660 else if (can_make_parallel (& second, & first) == NULL)
662 /* Write out the second instruction first. */
663 (void) cgen_asm_finish_insn (second.insn, second.buffer,
664 CGEN_FIELDS_BITSIZE (& second.fields));
666 /* Force the top bit of the first instruction to be set. */
667 make_parallel (first.buffer);
669 /* Get the fixups for the first instruction. */
670 cgen_restore_fixups ();
672 /* Write out the first instruction. */
673 (void) cgen_asm_finish_insn (first.insn, first.buffer,
674 CGEN_FIELDS_BITSIZE (& first.fields));
678 as_bad ("'%s': %s", str2, errmsg);
682 /* Set these so m32r_fill_insn can use them. */
684 prev_subseg = now_subseg;
689 /* end-sanitize-m32rx */
700 /* Initialize GAS's cgen interface for a new instruction. */
701 cgen_asm_init_parse ();
703 /* start-sanitize-m32rx */
704 /* Look for a parallel instruction seperator. */
705 if ((str2 = strstr (str, "||")) != NULL)
707 assemble_parallel_insn (str, str2);
710 /* end-sanitize-m32rx */
712 insn.insn = CGEN_SYM (assemble_insn) (str, & insn.fields, insn.buffer, & errmsg);
719 /* start-sanitize-m32rx */
720 if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
722 as_bad ("instruction '%s' is for the M32RX only", str);
725 /* end-sanitize-m32rx */
727 if (CGEN_INSN_BITSIZE (insn.insn) == 32)
729 /* 32 bit insns must live on 32 bit boundaries. */
730 if (prev_insn.insn || seen_relaxable_p)
732 /* ??? If calling fill_insn too many times turns us into a memory
733 pig, can we call assemble_nop instead of !seen_relaxable_p? */
737 (void) cgen_asm_finish_insn (insn.insn, insn.buffer,
738 CGEN_FIELDS_BITSIZE (& insn.fields));
742 /* start-sanitize-m32rx */
743 /* start-sanitize-phase2-m32rx */
745 /* end-sanitize-phase2-m32rx */
746 /* end-sanitize-m32rx */
748 if (CGEN_INSN_BITSIZE (insn.insn) != 16)
751 /* Get the indices of the operands of the instruction. */
752 insn.insn = m32r_cgen_get_insn_operands (insn.insn,
753 bfd_getb16 ((char *) insn.buffer),
756 if (insn.insn == NULL)
757 as_fatal ("internal error: m32r_cgen_get_insn_operands failed");
759 /* Keep track of whether we've seen a pair of 16 bit insns.
760 prev_insn.insn is NULL when we're on a 32 bit boundary. */
763 /* start-sanitize-m32rx */
764 /* start-sanitize-phase2-m32rx */
765 /* Look to see if this instruction can be combined with the
766 previous instruction to make one, parallel, 32 bit instruction.
767 If the previous instruction (potentially) changed the flow of
768 program control, then it cannot be combined with the current
769 instruction. If the current instruction is relaxable, then it
770 might be replaced with a longer version, so we cannot combine it.
771 Also if the output of the previous instruction is used as an
772 input to the current instruction then it cannot be combined.
773 Otherwise call can_make_parallel() with both orderings of the
774 instructions to see if they can be combined. */
776 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) == 0
777 && ! writes_to_pc (& prev_insn)
778 && ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
781 if (can_make_parallel (& prev_insn, & insn) == NULL)
782 make_parallel (insn.buffer);
783 else if (can_make_parallel (& insn, & prev_insn.insn) == NULL)
786 /* end-sanitize-phase2-m32rx */
787 /* end-sanitize-m32rx */
789 prev_insn.insn = NULL;
796 /* Record the frag that might be used by this insn. */
797 insn.frag = frag_now;
798 insn.addr = cgen_asm_finish_insn (insn.insn, insn.buffer,
799 CGEN_FIELDS_BITSIZE (& insn.fields));
801 /* start-sanitize-m32rx */
802 /* start-sanitize-phase2-m32rx */
807 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
809 /* Swap the two insns */
810 SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
811 SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
813 make_parallel (insn.addr);
815 /* Swap any relaxable frags recorded for the two insns. */
816 if (prev_insn.frag->fr_opcode == prev_insn.addr)
817 prev_insn.frag->fr_opcode = insn.addr;
818 else if (insn.frag->fr_opcode == insn.addr)
819 insn.frag->fr_opcode = prev_insn.addr;
821 /* end-sanitize-phase2-m32rx */
823 /* Record where this instruction was assembled. */
824 prev_insn.addr = insn.addr;
825 prev_insn.frag = insn.frag;
826 /* end-sanitize-m32rx */
828 /* If the insn needs the following one to be on a 32 bit boundary
829 (e.g. subroutine calls), fill this insn's slot. */
830 if (prev_insn.insn != NULL
831 && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_FILL_SLOT) != 0)
834 /* If this is a relaxable insn (can be replaced with a larger version)
835 mark the fact so that we can emit an alignment directive for a
836 following 32 bit insn if we see one. */
837 if (CGEN_INSN_ATTR (insn.insn, CGEN_INSN_RELAXABLE) != 0)
838 seen_relaxable_p = 1;
841 /* Set these so m32r_fill_insn can use them. */
843 prev_subseg = now_subseg;
846 /* The syntax in the manual says constants begin with '#'.
847 We just ignore it. */
850 md_operand (expressionP)
851 expressionS * expressionP;
853 if (* input_line_pointer == '#')
855 input_line_pointer ++;
856 expression (expressionP);
861 md_section_align (segment, size)
865 int align = bfd_get_section_alignment (stdoutput, segment);
866 return ((size + (1 << align) - 1) & (-1 << align));
870 md_undefined_symbol (name)
876 /* .scomm pseudo-op handler.
878 This is a new pseudo-op to handle putting objects in .scommon.
879 By doing this the linker won't need to do any work and more importantly
880 it removes the implicit -G arg necessary to correctly link the object file.
887 register char * name;
891 register symbolS * symbolP;
895 name = input_line_pointer;
896 c = get_symbol_end ();
898 /* just after name is now '\0' */
899 p = input_line_pointer;
902 if (* input_line_pointer != ',')
904 as_bad ("Expected comma after symbol-name: rest of line ignored.");
905 ignore_rest_of_line ();
909 input_line_pointer ++; /* skip ',' */
910 if ((size = get_absolute_expression ()) < 0)
912 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size);
913 ignore_rest_of_line ();
917 /* The third argument to .scomm is the alignment. */
918 if (* input_line_pointer != ',')
922 ++ input_line_pointer;
923 align = get_absolute_expression ();
926 as_warn ("ignoring bad alignment");
930 /* Convert to a power of 2 alignment. */
933 for (align2 = 0; (align & 1) == 0; align >>= 1, ++ align2)
937 as_bad ("Common alignment not a power of 2");
938 ignore_rest_of_line ();
946 symbolP = symbol_find_or_make (name);
949 if (S_IS_DEFINED (symbolP))
951 as_bad ("Ignoring attempt to re-define symbol `%s'.",
952 S_GET_NAME (symbolP));
953 ignore_rest_of_line ();
957 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
959 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
960 S_GET_NAME (symbolP),
961 (long) S_GET_VALUE (symbolP),
964 ignore_rest_of_line ();
970 segT old_sec = now_seg;
971 int old_subsec = now_subseg;
974 record_alignment (sbss_section, align2);
975 subseg_set (sbss_section, 0);
978 frag_align (align2, 0, 0);
980 if (S_GET_SEGMENT (symbolP) == sbss_section)
981 symbolP->sy_frag->fr_symbol = 0;
983 symbolP->sy_frag = frag_now;
985 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
988 S_SET_SIZE (symbolP, size);
989 S_SET_SEGMENT (symbolP, sbss_section);
990 S_CLEAR_EXTERNAL (symbolP);
991 subseg_set (old_sec, old_subsec);
995 S_SET_VALUE (symbolP, (valueT) size);
996 S_SET_ALIGN (symbolP, align2);
997 S_SET_EXTERNAL (symbolP);
998 S_SET_SEGMENT (symbolP, & scom_section);
1001 demand_empty_rest_of_line ();
1004 /* Interface to relax_segment. */
1006 /* FIXME: Build table by hand, get it working, then machine generate. */
1008 const relax_typeS md_relax_table[] =
1011 1) most positive reach of this state,
1012 2) most negative reach of this state,
1013 3) how many bytes this mode will add to the size of the current frag
1014 4) which index into the table to try if we can't fit into this one. */
1016 /* The first entry must be unused because an `rlx_more' value of zero ends
1020 /* The displacement used by GAS is from the end of the 2 byte insn,
1021 so we subtract 2 from the following. */
1022 /* 16 bit insn, 8 bit disp -> 10 bit range.
1023 This doesn't handle a branch in the right slot at the border:
1024 the "& -4" isn't taken into account. It's not important enough to
1025 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1027 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1028 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1029 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1030 /* Same thing, but with leading nop for alignment. */
1031 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1035 m32r_relax_frag (fragP, stretch)
1039 /* Address of branch insn. */
1040 long address = fragP->fr_address + fragP->fr_fix - 2;
1043 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1044 if (fragP->fr_subtype == 2)
1046 if ((address & 3) != 0)
1048 fragP->fr_subtype = 3;
1052 else if (fragP->fr_subtype == 3)
1054 if ((address & 3) == 0)
1056 fragP->fr_subtype = 2;
1062 growth = relax_frag (fragP, stretch);
1064 /* Long jump on odd halfword boundary? */
1065 if (fragP->fr_subtype == 2 && (address & 3) != 0)
1067 fragP->fr_subtype = 3;
1075 /* Return an initial guess of the length by which a fragment must grow to
1076 hold a branch to reach its destination.
1077 Also updates fr_type/fr_subtype as necessary.
1079 Called just before doing relaxation.
1080 Any symbol that is now undefined will not become defined.
1081 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1082 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1083 Although it may not be explicit in the frag, pretend fr_var starts with a
1087 md_estimate_size_before_relax (fragP, segment)
1091 int old_fr_fix = fragP->fr_fix;
1092 char * opcode = fragP->fr_opcode;
1094 /* The only thing we have to handle here are symbols outside of the
1095 current segment. They may be undefined or in a different segment in
1096 which case linker scripts may place them anywhere.
1097 However, we can't finish the fragment here and emit the reloc as insn
1098 alignment requirements may move the insn about. */
1100 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
1102 /* The symbol is undefined in this segment.
1103 Change the relaxation subtype to the max allowable and leave
1104 all further handling to md_convert_frag. */
1105 fragP->fr_subtype = 2;
1107 #if 0 /* Can't use this, but leave in for illustration. */
1108 /* Change 16 bit insn to 32 bit insn. */
1111 /* Increase known (fixed) size of fragment. */
1114 /* Create a relocation for it. */
1115 fix_new (fragP, old_fr_fix, 4,
1117 fragP->fr_offset, 1 /* pcrel */,
1118 /* FIXME: Can't use a real BFD reloc here.
1119 cgen_md_apply_fix3 can't handle it. */
1120 BFD_RELOC_M32R_26_PCREL);
1122 /* Mark this fragment as finished. */
1126 const CGEN_INSN * insn;
1129 /* Update the recorded insn.
1130 Fortunately we don't have to look very far.
1131 FIXME: Change this to record in the instruction the next higher
1132 relaxable insn to use. */
1133 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
1135 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
1136 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
1138 && CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX))
1144 fragP->fr_cgen.insn = insn;
1150 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
1153 /* *fragP has been relaxed to its final size, and now needs to have
1154 the bytes inside it modified to conform to the new size.
1156 Called after relaxation is finished.
1157 fragP->fr_type == rs_machine_dependent.
1158 fragP->fr_subtype is the subtype of what the address relaxed to. */
1161 md_convert_frag (abfd, sec, fragP)
1167 char * displacement;
1173 opcode = fragP->fr_opcode;
1175 /* Address opcode resides at in file space. */
1176 opcode_address = fragP->fr_address + fragP->fr_fix - 2;
1178 switch (fragP->fr_subtype)
1182 displacement = & opcode[1];
1187 displacement = & opcode[1];
1190 opcode[2] = opcode[0] | 0x80;
1191 md_number_to_chars (opcode, PAR_NOP_INSN, 2);
1192 opcode_address += 2;
1194 displacement = & opcode[3];
1200 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1202 /* symbol must be resolved by linker */
1203 if (fragP->fr_offset & 3)
1204 as_warn ("Addend to unresolved symbol not on word boundary.");
1205 addend = fragP->fr_offset >> 2;
1209 /* Address we want to reach in file space. */
1210 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
1211 target_address += fragP->fr_symbol->sy_frag->fr_address;
1212 addend = (target_address - (opcode_address & -4)) >> 2;
1215 /* Create a relocation for symbols that must be resolved by the linker.
1216 Otherwise output the completed insn. */
1218 if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
1220 assert (fragP->fr_subtype != 1);
1221 assert (fragP->fr_cgen.insn != 0);
1222 cgen_record_fixup (fragP,
1223 /* Offset of branch insn in frag. */
1224 fragP->fr_fix + extension - 4,
1225 fragP->fr_cgen.insn,
1227 /* FIXME: quick hack */
1229 CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
1231 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24),
1233 fragP->fr_cgen.opinfo,
1234 fragP->fr_symbol, fragP->fr_offset);
1237 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1239 md_number_to_chars (displacement, (valueT) addend,
1240 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
1242 fragP->fr_fix += extension;
1245 /* Functions concerning relocs. */
1247 /* The location from which a PC relative jump should be calculated,
1248 given a PC relative reloc. */
1251 md_pcrel_from_section (fixP, sec)
1255 if (fixP->fx_addsy != (symbolS *) NULL
1256 && (! S_IS_DEFINED (fixP->fx_addsy)
1257 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
1259 /* The symbol is undefined (or is defined but not in this section).
1260 Let the linker figure it out. */
1264 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
1267 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1268 Returns BFD_RELOC_NONE if no reloc type can be found.
1269 *FIXP may be modified if desired. */
1271 bfd_reloc_code_real_type
1272 CGEN_SYM (lookup_reloc) (insn, operand, fixP)
1273 const CGEN_INSN * insn;
1274 const CGEN_OPERAND * operand;
1277 switch (CGEN_OPERAND_TYPE (operand))
1279 case M32R_OPERAND_DISP8 : return BFD_RELOC_M32R_10_PCREL;
1280 case M32R_OPERAND_DISP16 : return BFD_RELOC_M32R_18_PCREL;
1281 case M32R_OPERAND_DISP24 : return BFD_RELOC_M32R_26_PCREL;
1282 case M32R_OPERAND_UIMM24 : return BFD_RELOC_M32R_24;
1283 case M32R_OPERAND_HI16 :
1284 case M32R_OPERAND_SLO16 :
1285 case M32R_OPERAND_ULO16 :
1286 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1287 if (fixP->tc_fix_data.opinfo != 0)
1288 return fixP->tc_fix_data.opinfo;
1291 return BFD_RELOC_NONE;
1294 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1297 m32r_record_hi16 (reloc_type, fixP, seg)
1302 struct m32r_hi_fixup * hi_fixup;
1304 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
1305 || reloc_type == BFD_RELOC_M32R_HI16_ULO);
1307 hi_fixup = ((struct m32r_hi_fixup *)
1308 xmalloc (sizeof (struct m32r_hi_fixup)));
1309 hi_fixup->fixp = fixP;
1310 hi_fixup->seg = now_seg;
1311 hi_fixup->next = m32r_hi_fixup_list;
1313 m32r_hi_fixup_list = hi_fixup;
1316 /* Called while parsing an instruction to create a fixup.
1317 We need to check for HI16 relocs and queue them up for later sorting. */
1320 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
1323 const CGEN_INSN * insn;
1325 const CGEN_OPERAND * operand;
1329 fixS * fixP = cgen_record_fixup_exp (frag, where, insn, length,
1330 operand, opinfo, exp);
1332 switch (CGEN_OPERAND_TYPE (operand))
1334 case M32R_OPERAND_HI16 :
1335 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1336 if (fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_SLO
1337 || fixP->tc_fix_data.opinfo == BFD_RELOC_M32R_HI16_ULO)
1338 m32r_record_hi16 (fixP->tc_fix_data.opinfo, fixP, now_seg);
1345 /* Return BFD reloc type from opinfo field in a fixS.
1346 It's tricky using fx_r_type in m32r_frob_file because the values
1347 are BFD_RELOC_UNUSED + operand number. */
1348 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1350 /* Sort any unmatched HI16 relocs so that they immediately precede
1351 the corresponding LO16 reloc. This is called before md_apply_fix and
1357 struct m32r_hi_fixup * l;
1359 for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
1361 segment_info_type * seginfo;
1364 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
1365 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
1367 /* Check quickly whether the next fixup happens to be a matching low. */
1368 if (l->fixp->fx_next != NULL
1369 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
1370 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
1371 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
1374 /* Look through the fixups for this segment for a matching `low'.
1375 When we find one, move the high/shigh just in front of it. We do
1376 this in two passes. In the first pass, we try to find a
1377 unique `low'. In the second pass, we permit multiple high's
1378 relocs for a single `low'. */
1379 seginfo = seg_info (l->seg);
1380 for (pass = 0; pass < 2; pass++)
1386 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
1388 /* Check whether this is a `low' fixup which matches l->fixp. */
1389 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
1390 && f->fx_addsy == l->fixp->fx_addsy
1391 && f->fx_offset == l->fixp->fx_offset
1394 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
1395 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
1396 || prev->fx_addsy != f->fx_addsy
1397 || prev->fx_offset != f->fx_offset))
1401 /* Move l->fixp before f. */
1402 for (pf = &seginfo->fix_root;
1404 pf = & (* pf)->fx_next)
1405 assert (* pf != NULL);
1407 * pf = l->fixp->fx_next;
1409 l->fixp->fx_next = f;
1411 seginfo->fix_root = l->fixp;
1413 prev->fx_next = l->fixp;
1425 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
1426 "Unmatched high/shigh reloc");
1431 /* See whether we need to force a relocation into the output file.
1432 This is used to force out switch and PC relative relocations when
1436 m32r_force_relocation (fix)
1442 return (fix->fx_pcrel
1446 /* Write a value out to the object file, using the appropriate endianness. */
1449 md_number_to_chars (buf, val, n)
1454 if (target_big_endian)
1455 number_to_chars_bigendian (buf, val, n);
1457 number_to_chars_littleendian (buf, val, n);
1460 /* Turn a string in input_line_pointer into a floating point constant of type
1461 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1462 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1465 /* Equal to MAX_PRECISION in atof-ieee.c */
1466 #define MAX_LITTLENUMS 6
1469 md_atof (type, litP, sizeP)
1476 LITTLENUM_TYPE words [MAX_LITTLENUMS];
1477 LITTLENUM_TYPE * wordP;
1479 char * atof_ieee ();
1497 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1501 return "Bad call to md_atof()";
1504 t = atof_ieee (input_line_pointer, type, words);
1506 input_line_pointer = t;
1507 * sizeP = prec * sizeof (LITTLENUM_TYPE);
1509 if (target_big_endian)
1511 for (i = 0; i < prec; i++)
1513 md_number_to_chars (litP, (valueT) words[i],
1514 sizeof (LITTLENUM_TYPE));
1515 litP += sizeof (LITTLENUM_TYPE);
1520 for (i = prec - 1; i >= 0; i--)
1522 md_number_to_chars (litP, (valueT) words[i],
1523 sizeof (LITTLENUM_TYPE));
1524 litP += sizeof (LITTLENUM_TYPE);