1 /* tc-m32c.c -- Assembler for the Renesas M32C.
2 Copyright (C) 2005 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcodes/m32c-desc.h"
27 #include "opcodes/m32c-opc.h"
29 #include "elf/common.h"
32 #include "libiberty.h"
33 #include "safe-ctype.h"
35 /* Structure to hold all of the different components
36 describing an individual instruction. */
39 const CGEN_INSN * insn;
40 const CGEN_INSN * orig_insn;
43 CGEN_INSN_INT buffer [1];
44 #define INSN_VALUE(buf) (*(buf))
46 unsigned char buffer [CGEN_MAX_INSN_SIZE];
47 #define INSN_VALUE(buf) (buf)
52 fixS * fixups [GAS_CGEN_MAX_FIXUPS];
53 int indices [MAX_OPERAND_INSTANCES];
57 const char comment_chars[] = ";";
58 const char line_comment_chars[] = "#";
59 const char line_separator_chars[] = "|";
60 const char EXP_CHARS[] = "eE";
61 const char FLT_CHARS[] = "dD";
63 #define M32C_SHORTOPTS ""
64 const char * md_shortopts = M32C_SHORTOPTS;
66 /* assembler options */
67 #define OPTION_CPU_M16C (OPTION_MD_BASE)
68 #define OPTION_CPU_M32C (OPTION_MD_BASE + 1)
70 struct option md_longopts[] =
72 { "m16c", no_argument, NULL, OPTION_CPU_M16C },
73 { "m32c", no_argument, NULL, OPTION_CPU_M32C },
74 {NULL, no_argument, NULL, 0}
76 size_t md_longopts_size = sizeof (md_longopts);
80 #define DEFAULT_MACHINE bfd_mach_m16c
81 #define DEFAULT_FLAGS EF_M32C_CPU_M16C
83 static unsigned long m32c_mach = bfd_mach_m16c;
84 static int cpu_mach = (1 << MACH_M16C);
87 /* Flags to set in the elf header */
88 static flagword m32c_flags = DEFAULT_FLAGS;
90 static unsigned int m32c_isa = (1 << ISA_M16C);
93 set_isa (enum isa_attr isa_num)
95 m32c_isa = (1 << isa_num);
98 static void s_bss (int);
101 md_parse_option (int c, char * arg ATTRIBUTE_UNUSED)
105 case OPTION_CPU_M16C:
106 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M16C;
107 m32c_mach = bfd_mach_m16c;
108 cpu_mach = (1 << MACH_M16C);
112 case OPTION_CPU_M32C:
113 m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M32C;
114 m32c_mach = bfd_mach_m32c;
115 cpu_mach = (1 << MACH_M32C);
126 md_show_usage (FILE * stream)
128 fprintf (stream, _(" M32C specific command line options:\n"));
132 s_bss (int ignore ATTRIBUTE_UNUSED)
136 temp = get_absolute_expression ();
137 subseg_set (bss_section, (subsegT) temp);
138 demand_empty_rest_of_line ();
141 /* The target specific pseudo-ops which we support. */
142 const pseudo_typeS md_pseudo_table[] =
153 /* Initialize the `cgen' interface. */
155 /* Set the machine number and endian. */
156 gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
157 CGEN_CPU_OPEN_ENDIAN,
159 CGEN_CPU_OPEN_ISAS, & m32c_isa,
162 m32c_cgen_init_asm (gas_cgen_cpu_desc);
164 /* This is a callback from cgen to gas to parse operands. */
165 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
167 /* Set the ELF flags if desired. */
169 bfd_set_private_flags (stdoutput, m32c_flags);
171 /* Set the machine type */
172 bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach);
182 /* Pad with nops for objdump. */
183 n_nops = (32 - ((insn_size) % 32)) / 8;
184 for (i = 1; i <= n_nops; i++)
189 m32c_start_line_hook (void)
191 #if 0 /* not necessary....handled in the .cpu file */
192 char *s = input_line_pointer;
195 for (s = input_line_pointer ; s && s[0] != '\n'; s++)
199 /* Remove :g suffix. Squeeze out blanks. */
202 for (sg = s - 1; sg && sg >= input_line_pointer; sg--)
208 input_line_pointer += 2;
215 /* Process [[indirect-operands]] in instruction str. */
218 m32c_indirect_operand (char *str)
225 enum indirect_type {none, relative, absolute} ;
226 enum indirect_type indirection [3] = { none, none, none };
227 int brace_n [3] = { 0, 0, 0 };
232 for (s = str; *s; s++)
236 /* [abs] where abs is not a0 or a1 */
237 if (s[1] == '[' && ! (s[2] == 'a' && (s[3] == '0' || s[3] == '1'))
238 && (ISBLANK (s[0]) || s[0] == ','))
239 indirection[operand] = absolute;
240 if (s[0] == ']' && s[1] == ']')
241 indirection[operand] = relative;
242 if (s[0] == '[' && s[1] == '[')
243 indirection[operand] = relative;
246 if (indirection[1] == none && indirection[2] == none)
250 ns_len = strlen (str);
251 new_str = (char*) xmalloc (ns_len);
253 ns_end = ns + ns_len;
255 for (s = str; *s; s++)
260 if (s[0] == '[' && ! brace_n[operand])
262 brace_n[operand] += 1;
263 /* Squeeze [[ to [ if this is an indirect operand. */
264 if (indirection[operand] != none)
268 else if (s[0] == '[' && brace_n[operand])
270 brace_n[operand] += 1;
272 else if (s[0] == ']' && s[1] == ']' && indirection[operand] == relative)
274 s += 1; /* skip one ]. */
275 brace_n[operand] -= 2; /* allow for 2 [. */
277 else if (s[0] == ']' && indirection[operand] == absolute)
279 brace_n[operand] -= 1;
280 continue; /* skip closing ]. */
282 else if (s[0] == ']')
284 brace_n[operand] -= 1;
294 for (operand = 1; operand <= 2; operand++)
295 if (brace_n[operand])
297 fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]);
300 if (indirection[1] != none && indirection[2] != none)
301 md_assemble ("src-dest-indirect");
302 else if (indirection[1] != none)
303 md_assemble ("src-indirect");
304 else if (indirection[2] != none)
305 md_assemble ("dest-indirect");
307 md_assemble (new_str);
313 md_assemble (char * str)
315 static int last_insn_had_delay_slot = 0;
319 if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str))
322 /* Initialize GAS's cgen interface for a new instruction. */
323 gas_cgen_init_parse ();
325 insn.insn = m32c_cgen_assemble_insn
326 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
334 /* Doesn't really matter what we pass for RELAX_P here. */
335 gas_cgen_finish_insn (insn.insn, insn.buffer,
336 CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
338 last_insn_had_delay_slot
339 = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
340 insn_size = CGEN_INSN_BITSIZE(insn.insn);
343 /* The syntax in the manual says constants begin with '#'.
344 We just ignore it. */
347 md_operand (expressionS * exp)
349 /* In case of a syntax error, escape back to try next syntax combo. */
350 if (exp->X_op == O_absent)
351 gas_cgen_md_operand (exp);
355 md_section_align (segT segment, valueT size)
357 int align = bfd_get_section_alignment (stdoutput, segment);
358 return ((size + (1 << align) - 1) & (-1 << align));
362 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
367 const relax_typeS md_relax_table[] =
370 1) most positive reach of this state,
371 2) most negative reach of this state,
372 3) how many bytes this mode will have in the variable part of the frag
373 4) which index into the table to try if we can't fit into this one. */
375 /* 0 */ { 0, 0, 0, 0 }, /* unused */
376 /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
378 /* 2 */ { 127, -128, 2, 3 }, /* jcnd16_5.b */
379 /* 3 */ { 32767, -32768, 5, 4 }, /* jcnd16_5.w */
380 /* 4 */ { 0, 0, 6, 0 }, /* jcnd16_5.a */
382 /* 5 */ { 127, -128, 2, 6 }, /* jcnd16.b */
383 /* 6 */ { 32767, -32768, 5, 7 }, /* jcnd16.w */
384 /* 7 */ { 0, 0, 6, 0 }, /* jcnd16.a */
386 /* 8 */ { 8, 1, 1, 9 }, /* jmp16.s */
387 /* 9 */ { 127, -128, 2, 10 }, /* jmp16.b */
388 /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */
389 /* 11 */ { 0, 0, 4, 0 }, /* jmp16.a */
391 /* 12 */ { 127, -128, 2, 13 }, /* jcnd32.b */
392 /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */
393 /* 14 */ { 0, 0, 6, 0 }, /* jcnd32.a */
395 /* 15 */ { 8, 1, 1, 16 }, /* jmp32.s */
396 /* 16 */ { 127, -128, 2, 17 }, /* jmp32.b */
397 /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */
398 /* 18 */ { 0, 0, 4, 0 } /* jmp32.a */
402 M32C_MACRO_JCND16_5_W,
403 M32C_MACRO_JCND16_5_A,
414 int pcrel_aim_offset;
415 } subtype_mappings[] = {
416 /* 0 */ { 0, 0, 0, 0 },
417 /* 1 */ { 0, 0, 0, 0 },
419 /* 2 */ { M32C_INSN_JCND16_5, 2, -M32C_MACRO_JCND16_5_A, 1 },
420 /* 3 */ { -M32C_MACRO_JCND16_5_W, 5, -M32C_MACRO_JCND16_5_A, 4 },
421 /* 4 */ { -M32C_MACRO_JCND16_5_A, 6, -M32C_MACRO_JCND16_5_A, 0 },
423 /* 5 */ { M32C_INSN_JCND16, 3, -M32C_MACRO_JCND16_A, 1 },
424 /* 6 */ { -M32C_MACRO_JCND16_W, 6, -M32C_MACRO_JCND16_A, 4 },
425 /* 7 */ { -M32C_MACRO_JCND16_A, 7, -M32C_MACRO_JCND16_A, 0 },
427 /* 8 */ { M32C_INSN_JMP16_S, 1, M32C_INSN_JMP16_A, 0 },
428 /* 9 */ { M32C_INSN_JMP16_B, 2, M32C_INSN_JMP16_A, 1 },
429 /* 10 */ { M32C_INSN_JMP16_W, 3, M32C_INSN_JMP16_A, 2 },
430 /* 11 */ { M32C_INSN_JMP16_A, 4, M32C_INSN_JMP16_A, 0 },
432 /* 12 */ { M32C_INSN_JCND32, 2, -M32C_MACRO_JCND32_A, 1 },
433 /* 13 */ { -M32C_MACRO_JCND32_W, 5, -M32C_MACRO_JCND32_A, 4 },
434 /* 14 */ { -M32C_MACRO_JCND32_A, 6, -M32C_MACRO_JCND32_A, 0 },
436 /* 15 */ { M32C_INSN_JMP32_S, 1, M32C_INSN_JMP32_A, 0 },
437 /* 16 */ { M32C_INSN_JMP32_B, 2, M32C_INSN_JMP32_A, 1 },
438 /* 17 */ { M32C_INSN_JMP32_W, 3, M32C_INSN_JMP32_A, 2 },
439 /* 18 */ { M32C_INSN_JMP32_A, 4, M32C_INSN_JMP32_A, 0 }
441 #define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
444 m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
446 symbolS *symbolP = fragP->fr_symbol;
447 if (symbolP && !S_IS_DEFINED (symbolP))
449 /* Adjust for m32c pcrel not being relative to the next opcode. */
450 *aim += subtype_mappings[this_state].pcrel_aim_offset;
454 insn_to_subtype (int insn)
457 for (i=0; i<NUM_MAPPINGS; i++)
458 if (insn == subtype_mappings[i].insn)
460 /*printf("mapping %d used\n", i);*/
466 /* Return an initial guess of the length by which a fragment must grow to
467 hold a branch to reach its destination.
468 Also updates fr_type/fr_subtype as necessary.
470 Called just before doing relaxation.
471 Any symbol that is now undefined will not become defined.
472 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
473 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
474 Although it may not be explicit in the frag, pretend fr_var starts with a
478 md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED)
480 int where = fragP->fr_opcode - fragP->fr_literal;
482 if (fragP->fr_subtype == 1)
483 fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);
485 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
489 new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
490 fragP->fr_subtype = insn_to_subtype (new_insn);
493 if (fragP->fr_cgen.insn->base
494 && fragP->fr_cgen.insn->base->num
495 != subtype_mappings[fragP->fr_subtype].insn
496 && subtype_mappings[fragP->fr_subtype].insn > 0)
498 int new_insn= subtype_mappings[fragP->fr_subtype].insn;
501 fragP->fr_cgen.insn = (fragP->fr_cgen.insn
502 - fragP->fr_cgen.insn->base->num
507 return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where);
510 /* *fragP has been relaxed to its final size, and now needs to have
511 the bytes inside it modified to conform to the new size.
513 Called after relaxation is finished.
514 fragP->fr_type == rs_machine_dependent.
515 fragP->fr_subtype is the subtype of what the address relaxed to. */
518 target_address_for (fragS *frag)
520 int rv = frag->fr_offset;
521 symbolS *sym = frag->fr_symbol;
524 rv += S_GET_VALUE (sym);
526 /*printf("target_address_for returns %d\n", rv);*/
531 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
532 segT sec ATTRIBUTE_UNUSED,
533 fragS * fragP ATTRIBUTE_UNUSED)
538 int where = fragP->fr_opcode - fragP->fr_literal;
539 unsigned char *op = (unsigned char *)fragP->fr_opcode;
541 addend = target_address_for (fragP) - (fragP->fr_address + where);
542 new_insn = subtype_mappings[fragP->fr_subtype].insn;
544 fragP->fr_fix = where + subtype_mappings[fragP->fr_subtype].bytes;
546 switch (subtype_mappings[fragP->fr_subtype].insn)
548 case M32C_INSN_JCND16_5:
550 operand = M32C_OPERAND_LAB_8_8;
553 case -M32C_MACRO_JCND16_5_W:
558 op[4] = (addend - 3) >> 8;
559 operand = M32C_OPERAND_LAB_8_16;
561 new_insn = M32C_INSN_JMP16_W;
564 case -M32C_MACRO_JCND16_5_A:
568 operand = M32C_OPERAND_LAB_8_24;
570 new_insn = M32C_INSN_JMP16_A;
574 case M32C_INSN_JCND16:
576 operand = M32C_OPERAND_LAB_16_8;
579 case -M32C_MACRO_JCND16_W:
584 op[5] = (addend - 4) >> 8;
585 operand = M32C_OPERAND_LAB_8_16;
587 new_insn = M32C_INSN_JMP16_W;
590 case -M32C_MACRO_JCND16_A:
594 operand = M32C_OPERAND_LAB_8_24;
596 new_insn = M32C_INSN_JMP16_A;
599 case M32C_INSN_JMP16_S:
600 op[0] = 0x60 | ((addend-2) & 0x07);
601 operand = M32C_OPERAND_LAB_5_3;
604 case M32C_INSN_JMP16_B:
607 operand = M32C_OPERAND_LAB_8_8;
610 case M32C_INSN_JMP16_W:
613 op[2] = (addend - 1) >> 8;
614 operand = M32C_OPERAND_LAB_8_16;
617 case M32C_INSN_JMP16_A:
622 operand = M32C_OPERAND_LAB_8_24;
625 case M32C_INSN_JCND32:
627 operand = M32C_OPERAND_LAB_8_8;
630 case -M32C_MACRO_JCND32_W:
635 op[4] = (addend - 3) >> 8;
636 operand = M32C_OPERAND_LAB_8_16;
638 new_insn = M32C_INSN_JMP32_W;
641 case -M32C_MACRO_JCND32_A:
645 operand = M32C_OPERAND_LAB_8_24;
647 new_insn = M32C_INSN_JMP32_A;
652 case M32C_INSN_JMP32_S:
653 addend = ((addend-2) & 0x07);
654 op[0] = 0x4a | (addend & 0x01) | ((addend << 3) & 0x30);
655 operand = M32C_OPERAND_LAB32_JMP_S;
658 case M32C_INSN_JMP32_B:
661 operand = M32C_OPERAND_LAB_8_8;
664 case M32C_INSN_JMP32_W:
667 op[2] = (addend - 1) >> 8;
668 operand = M32C_OPERAND_LAB_8_16;
671 case M32C_INSN_JMP32_A:
676 operand = M32C_OPERAND_LAB_8_24;
681 printf("\nHey! Need more opcode converters! missing: %d %s\n\n",
683 fragP->fr_cgen.insn->base->name);
687 if (S_GET_SEGMENT (fragP->fr_symbol) != sec
688 || operand == M32C_OPERAND_LAB_8_24)
690 assert (fragP->fr_cgen.insn != 0);
691 gas_cgen_record_fixup (fragP,
694 (fragP->fr_fix - where) * 8,
695 cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
697 fragP->fr_cgen.opinfo,
698 fragP->fr_symbol, fragP->fr_offset);
702 /* Functions concerning relocs. */
704 /* The location from which a PC relative jump should be calculated,
705 given a PC relative reloc. */
708 md_pcrel_from_section (fixS * fixP, segT sec)
710 if (fixP->fx_addsy != (symbolS *) NULL
711 && (! S_IS_DEFINED (fixP->fx_addsy)
712 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
713 /* The symbol is undefined (or is defined but not in this section).
714 Let the linker figure it out. */
717 return (fixP->fx_frag->fr_address + fixP->fx_where);
720 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
721 Returns BFD_RELOC_NONE if no reloc type can be found.
722 *FIXP may be modified if desired. */
724 bfd_reloc_code_real_type
725 md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED,
726 const CGEN_OPERAND * operand,
727 fixS * fixP ATTRIBUTE_UNUSED)
729 static const struct op_reloc {
730 /* A CGEN operand type that can be a relocatable expression. */
731 CGEN_OPERAND_TYPE operand;
733 /* The appropriate BFD reloc type to use for that. */
734 bfd_reloc_code_real_type reloc;
736 /* The offset from the start of the instruction to the field to be
737 relocated, in bytes. */
739 } op_reloc_table[] = {
741 /* Absolute relocs for 16-bit fields. */
742 { M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 },
743 { M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 },
744 { M32C_OPERAND_IMM_32_HI, BFD_RELOC_16, 4 },
745 { M32C_OPERAND_DSP_16_S16, BFD_RELOC_16, 2 },
746 { M32C_OPERAND_DSP_24_S16, BFD_RELOC_16, 3 },
747 { M32C_OPERAND_DSP_32_S16, BFD_RELOC_16, 4 },
748 { M32C_OPERAND_DSP_40_S16, BFD_RELOC_16, 5 },
749 { M32C_OPERAND_DSP_8_U16, BFD_RELOC_16, 1 },
750 { M32C_OPERAND_DSP_16_U16, BFD_RELOC_16, 2 },
751 { M32C_OPERAND_DSP_24_U16, BFD_RELOC_16, 3 },
752 { M32C_OPERAND_DSP_32_U16, BFD_RELOC_16, 4 },
754 /* Absolute relocs for 24-bit fields. */
755 { M32C_OPERAND_LAB_8_24, BFD_RELOC_24, 1 },
756 { M32C_OPERAND_DSP_16_U24, BFD_RELOC_24, 2 },
757 { M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 },
758 { M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 },
759 { M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 },
761 /* Absolute relocs for 32-bit fields. */
762 { M32C_OPERAND_IMM_16_SI, BFD_RELOC_32, 2 },
763 { M32C_OPERAND_IMM_24_SI, BFD_RELOC_32, 3 },
764 { M32C_OPERAND_IMM_32_SI, BFD_RELOC_32, 4 },
765 { M32C_OPERAND_IMM_40_SI, BFD_RELOC_32, 5 },
771 for (i = ARRAY_SIZE (op_reloc_table); --i >= 0; )
773 const struct op_reloc *or = &op_reloc_table[i];
775 if (or->operand == operand->type)
777 fixP->fx_where += or->offset;
778 fixP->fx_size -= or->offset;
785 "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation %d\n",
788 return BFD_RELOC_NONE;
791 /* See whether we need to force a relocation into the output file.
792 This is used to force out switch and PC relative relocations when
796 m32c_force_relocation (fixS * fixp)
798 int reloc = fixp->fx_r_type;
800 if (reloc > (int)BFD_RELOC_UNUSED)
802 reloc -= (int)BFD_RELOC_UNUSED;
805 case M32C_OPERAND_DSP_32_S16:
806 case M32C_OPERAND_DSP_32_U16:
807 case M32C_OPERAND_IMM_32_HI:
808 case M32C_OPERAND_DSP_16_S16:
809 case M32C_OPERAND_DSP_16_U16:
810 case M32C_OPERAND_IMM_16_HI:
811 case M32C_OPERAND_DSP_24_S16:
812 case M32C_OPERAND_DSP_24_U16:
813 case M32C_OPERAND_IMM_24_HI:
819 if (fixp->fx_r_type == BFD_RELOC_16)
823 return generic_force_reloc (fixp);
826 /* Write a value out to the object file, using the appropriate endianness. */
829 md_number_to_chars (char * buf, valueT val, int n)
831 number_to_chars_littleendian (buf, val, n);
834 /* Turn a string in input_line_pointer into a floating point constant of type
835 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
836 emitted is stored in *sizeP . An error message is returned, or NULL on OK. */
838 /* Equal to MAX_PRECISION in atof-ieee.c. */
839 #define MAX_LITTLENUMS 6
842 md_atof (int type, char * litP, int * sizeP)
846 LITTLENUM_TYPE words [MAX_LITTLENUMS];
865 /* FIXME: Some targets allow other format chars for bigger sizes here. */
869 return _("Bad call to md_atof()");
872 t = atof_ieee (input_line_pointer, type, words);
874 input_line_pointer = t;
875 * sizeP = prec * sizeof (LITTLENUM_TYPE);
877 for (i = 0; i < prec; i++)
879 md_number_to_chars (litP, (valueT) words[i],
880 sizeof (LITTLENUM_TYPE));
881 litP += sizeof (LITTLENUM_TYPE);
888 m32c_fix_adjustable (fixS * fixP)
891 if (fixP->fx_addsy == NULL)
894 /* We need the symbol name for the VTABLE entries. */
895 reloc = fixP->fx_r_type;
896 if (reloc > (int)BFD_RELOC_UNUSED)
898 reloc -= (int)BFD_RELOC_UNUSED;
901 case M32C_OPERAND_DSP_32_S16:
902 case M32C_OPERAND_DSP_32_U16:
903 case M32C_OPERAND_IMM_32_HI:
904 case M32C_OPERAND_DSP_16_S16:
905 case M32C_OPERAND_DSP_16_U16:
906 case M32C_OPERAND_IMM_16_HI:
907 case M32C_OPERAND_DSP_24_S16:
908 case M32C_OPERAND_DSP_24_U16:
909 case M32C_OPERAND_IMM_24_HI:
915 if (fixP->fx_r_type == BFD_RELOC_16)
919 /* Do not adjust relocations involving symbols in merged sections.
921 A reloc patching in the value of some symbol S plus some addend A
922 can be produced in different ways:
924 1) It might simply be a reference to the data at S + A. Clearly,
925 if linker merging shift that data around, the value patched in
926 by the reloc needs to be adjusted accordingly.
928 2) Or, it might be a reference to S, with A added in as a constant
929 bias. For example, given code like this:
935 it would be reasonable for the compiler to rearrange the array
936 reference to something like:
940 and emit assembly code that refers to S - (8 * sizeof (int)),
941 so the subtraction is done entirely at compile-time. In this
942 case, the reloc's addend A would be -(8 * sizeof (int)), and
943 shifting around code or data at S + A should not affect the
944 reloc: the reloc isn't referring to that code or data at all.
946 The linker has no way of knowing which case it has in hand. So,
947 to disambiguate, we have the linker always treat reloc addends as
948 in case 2): they're constants that should be simply added to the
949 symbol value, just like the reloc says. And we express case 1)
950 in different way: we have the compiler place a label at the real
951 target, and reference that label with an addend of zero. (The
952 compiler is unlikely to reference code using a label plus an
953 offset anyway, since it doesn't know the sizes of the
956 The simplification being done by gas/write.c:adjust_reloc_syms,
957 however, turns the explicit-label usage into the label-plus-
958 offset usage, re-introducing the ambiguity the compiler avoided.
959 So we need to disable that simplification for symbols referring
962 This only affects object size a little bit. */
963 if (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE)
969 /* Worker function for m32c_is_colon_insn(). */
970 static char restore_colon PARAMS ((int));
973 restore_colon (int advance_i_l_p_by)
977 /* Restore the colon, and advance input_line_pointer to
978 the end of the new symbol. */
979 * input_line_pointer = ':';
980 input_line_pointer += advance_i_l_p_by;
981 c = * input_line_pointer;
982 * input_line_pointer = 0;
987 /* Determines if the symbol starting at START and ending in
988 a colon that was at the location pointed to by INPUT_LINE_POINTER
989 (but which has now been replaced bu a NUL) is in fact an
990 :Z, :S, :Q, or :G suffix.
991 If it is, then it restores the colon, advances INPUT_LINE_POINTER
992 to the real end of the instruction/symbol, and returns the character
993 that really terminated the symbol. Otherwise it returns 0. */
995 m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED)
997 char * i_l_p = input_line_pointer;
999 /* Check to see if the text following the colon is 'G' */
1000 if (TOLOWER (i_l_p[1]) == 'g' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1001 return restore_colon (2);
1003 /* Check to see if the text following the colon is 'Q' */
1004 if (TOLOWER (i_l_p[1]) == 'q' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1005 return restore_colon (2);
1007 /* Check to see if the text following the colon is 'S' */
1008 if (TOLOWER (i_l_p[1]) == 's' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1009 return restore_colon (2);
1011 /* Check to see if the text following the colon is 'Z' */
1012 if (TOLOWER (i_l_p[1]) == 'z' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
1013 return restore_colon (2);