1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "safe-ctype.h"
47 #include "dwarf2dbg.h"
50 #include "opcode/ia64.h"
54 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
55 #define MIN(a,b) ((a) < (b) ? (a) : (b))
58 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
59 #define CURR_SLOT md.slot[md.curr_slot]
61 #define O_pseudo_fixup (O_max + 1)
65 /* IA-64 ABI section pseudo-ops. */
66 SPECIAL_SECTION_BSS = 0,
68 SPECIAL_SECTION_SDATA,
69 SPECIAL_SECTION_RODATA,
70 SPECIAL_SECTION_COMMENT,
71 SPECIAL_SECTION_UNWIND,
72 SPECIAL_SECTION_UNWIND_INFO,
73 /* HPUX specific section pseudo-ops. */
74 SPECIAL_SECTION_INIT_ARRAY,
75 SPECIAL_SECTION_FINI_ARRAY,
92 FUNC_LT_FPTR_RELATIVE,
102 REG_FR = (REG_GR + 128),
103 REG_AR = (REG_FR + 128),
104 REG_CR = (REG_AR + 128),
105 REG_P = (REG_CR + 128),
106 REG_BR = (REG_P + 64),
107 REG_IP = (REG_BR + 8),
114 /* The following are pseudo-registers for use by gas only. */
126 /* The following pseudo-registers are used for unwind directives only: */
134 DYNREG_GR = 0, /* dynamic general purpose register */
135 DYNREG_FR, /* dynamic floating point register */
136 DYNREG_PR, /* dynamic predicate register */
140 enum operand_match_result
143 OPERAND_OUT_OF_RANGE,
147 /* On the ia64, we can't know the address of a text label until the
148 instructions are packed into a bundle. To handle this, we keep
149 track of the list of labels that appear in front of each
153 struct label_fix *next;
157 extern int target_big_endian;
159 /* Characters which always start a comment. */
160 const char comment_chars[] = "";
162 /* Characters which start a comment at the beginning of a line. */
163 const char line_comment_chars[] = "#";
165 /* Characters which may be used to separate multiple commands on a
167 const char line_separator_chars[] = ";";
169 /* Characters which are used to indicate an exponent in a floating
171 const char EXP_CHARS[] = "eE";
173 /* Characters which mean that a number is a floating point constant,
175 const char FLT_CHARS[] = "rRsSfFdDxXpP";
177 /* ia64-specific option processing: */
179 const char *md_shortopts = "m:N:x::";
181 struct option md_longopts[] =
183 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
184 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
185 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
186 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
189 size_t md_longopts_size = sizeof (md_longopts);
193 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
194 struct hash_control *reg_hash; /* register name hash table */
195 struct hash_control *dynreg_hash; /* dynamic register hash table */
196 struct hash_control *const_hash; /* constant hash table */
197 struct hash_control *entry_hash; /* code entry hint hash table */
199 symbolS *regsym[REG_NUM];
201 /* If X_op is != O_absent, the registername for the instruction's
202 qualifying predicate. If NULL, p0 is assumed for instructions
203 that are predicatable. */
210 explicit_mode : 1, /* which mode we're in */
211 default_explicit_mode : 1, /* which mode is the default */
212 mode_explicitly_set : 1, /* was the current mode explicitly set? */
214 keep_pending_output : 1;
216 /* Each bundle consists of up to three instructions. We keep
217 track of four most recent instructions so we can correctly set
218 the end_of_insn_group for the last instruction in a bundle. */
220 int num_slots_in_use;
224 end_of_insn_group : 1,
225 manual_bundling_on : 1,
226 manual_bundling_off : 1;
227 signed char user_template; /* user-selected template, if any */
228 unsigned char qp_regno; /* qualifying predicate */
229 /* This duplicates a good fraction of "struct fix" but we
230 can't use a "struct fix" instead since we can't call
231 fix_new_exp() until we know the address of the instruction. */
235 bfd_reloc_code_real_type code;
236 enum ia64_opnd opnd; /* type of operand in need of fix */
237 unsigned int is_pcrel : 1; /* is operand pc-relative? */
238 expressionS expr; /* the value to be inserted */
240 fixup[2]; /* at most two fixups per insn */
241 struct ia64_opcode *idesc;
242 struct label_fix *label_fixups;
243 struct label_fix *tag_fixups;
244 struct unw_rec_list *unwind_record; /* Unwind directive. */
247 unsigned int src_line;
248 struct dwarf2_line_info debug_line;
256 struct dynreg *next; /* next dynamic register */
258 unsigned short base; /* the base register number */
259 unsigned short num_regs; /* # of registers in this set */
261 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
263 flagword flags; /* ELF-header flags */
266 unsigned hint:1; /* is this hint currently valid? */
267 bfd_vma offset; /* mem.offset offset */
268 bfd_vma base; /* mem.offset base */
271 int path; /* number of alt. entry points seen */
272 const char **entry_labels; /* labels of all alternate paths in
273 the current DV-checking block. */
274 int maxpaths; /* size currently allocated for
276 /* Support for hardware errata workarounds. */
278 /* Record data about the last three insn groups. */
281 /* B-step workaround.
282 For each predicate register, this is set if the corresponding insn
283 group conditionally sets this register with one of the affected
286 /* B-step workaround.
287 For each general register, this is set if the corresponding insn
288 a) is conditional one one of the predicate registers for which
289 P_REG_SET is 1 in the corresponding entry of the previous group,
290 b) sets this general register with one of the affected
292 int g_reg_set_conditionally[128];
296 int pointer_size; /* size in bytes of a pointer */
297 int pointer_size_shift; /* shift size of a pointer for alignment */
301 /* application registers: */
307 #define AR_BSPSTORE 18
322 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
323 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
324 {"ar.rsc", 16}, {"ar.bsp", 17},
325 {"ar.bspstore", 18}, {"ar.rnat", 19},
326 {"ar.fcr", 21}, {"ar.eflag", 24},
327 {"ar.csd", 25}, {"ar.ssd", 26},
328 {"ar.cflg", 27}, {"ar.fsr", 28},
329 {"ar.fir", 29}, {"ar.fdr", 30},
330 {"ar.ccv", 32}, {"ar.unat", 36},
331 {"ar.fpsr", 40}, {"ar.itc", 44},
332 {"ar.pfs", 64}, {"ar.lc", 65},
353 /* control registers: */
395 static const struct const_desc
402 /* PSR constant masks: */
405 {"psr.be", ((valueT) 1) << 1},
406 {"psr.up", ((valueT) 1) << 2},
407 {"psr.ac", ((valueT) 1) << 3},
408 {"psr.mfl", ((valueT) 1) << 4},
409 {"psr.mfh", ((valueT) 1) << 5},
411 {"psr.ic", ((valueT) 1) << 13},
412 {"psr.i", ((valueT) 1) << 14},
413 {"psr.pk", ((valueT) 1) << 15},
415 {"psr.dt", ((valueT) 1) << 17},
416 {"psr.dfl", ((valueT) 1) << 18},
417 {"psr.dfh", ((valueT) 1) << 19},
418 {"psr.sp", ((valueT) 1) << 20},
419 {"psr.pp", ((valueT) 1) << 21},
420 {"psr.di", ((valueT) 1) << 22},
421 {"psr.si", ((valueT) 1) << 23},
422 {"psr.db", ((valueT) 1) << 24},
423 {"psr.lp", ((valueT) 1) << 25},
424 {"psr.tb", ((valueT) 1) << 26},
425 {"psr.rt", ((valueT) 1) << 27},
426 /* 28-31: reserved */
427 /* 32-33: cpl (current privilege level) */
428 {"psr.is", ((valueT) 1) << 34},
429 {"psr.mc", ((valueT) 1) << 35},
430 {"psr.it", ((valueT) 1) << 36},
431 {"psr.id", ((valueT) 1) << 37},
432 {"psr.da", ((valueT) 1) << 38},
433 {"psr.dd", ((valueT) 1) << 39},
434 {"psr.ss", ((valueT) 1) << 40},
435 /* 41-42: ri (restart instruction) */
436 {"psr.ed", ((valueT) 1) << 43},
437 {"psr.bn", ((valueT) 1) << 44},
440 /* indirect register-sets/memory: */
449 { "CPUID", IND_CPUID },
450 { "cpuid", IND_CPUID },
462 /* Pseudo functions used to indicate relocation types (these functions
463 start with an at sign (@). */
485 /* reloc pseudo functions (these must come first!): */
486 { "dtpmod", PSEUDO_FUNC_RELOC, { 0 } },
487 { "dtprel", PSEUDO_FUNC_RELOC, { 0 } },
488 { "fptr", PSEUDO_FUNC_RELOC, { 0 } },
489 { "gprel", PSEUDO_FUNC_RELOC, { 0 } },
490 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } },
491 { "ltoffx", PSEUDO_FUNC_RELOC, { 0 } },
492 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } },
493 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } },
494 { "secrel", PSEUDO_FUNC_RELOC, { 0 } },
495 { "segrel", PSEUDO_FUNC_RELOC, { 0 } },
496 { "tprel", PSEUDO_FUNC_RELOC, { 0 } },
497 { "ltv", PSEUDO_FUNC_RELOC, { 0 } },
498 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
499 { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_MODULE */
500 { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_RELATIVE */
501 { "", 0, { 0 } }, /* placeholder for FUNC_LT_TP_RELATIVE */
502 { "iplt", PSEUDO_FUNC_RELOC, { 0 } },
504 /* mbtype4 constants: */
505 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
506 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
507 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
508 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
509 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
511 /* fclass constants: */
512 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
513 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
514 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
515 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
516 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
517 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
518 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
519 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
520 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
522 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
524 /* hint constants: */
525 { "pause", PSEUDO_FUNC_CONST, { 0x0 } },
527 /* unwind-related constants: */
528 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
529 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
530 { "nt", PSEUDO_FUNC_CONST, { 2 } },
532 /* unwind-related registers: */
533 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
536 /* 41-bit nop opcodes (one per unit): */
537 static const bfd_vma nop[IA64_NUM_UNITS] =
539 0x0000000000LL, /* NIL => break 0 */
540 0x0008000000LL, /* I-unit nop */
541 0x0008000000LL, /* M-unit nop */
542 0x4000000000LL, /* B-unit nop */
543 0x0008000000LL, /* F-unit nop */
544 0x0008000000LL, /* L-"unit" nop */
545 0x0008000000LL, /* X-unit nop */
548 /* Can't be `const' as it's passed to input routines (which have the
549 habit of setting temporary sentinels. */
550 static char special_section_name[][20] =
552 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
553 {".IA_64.unwind"}, {".IA_64.unwind_info"},
554 {".init_array"}, {".fini_array"}
557 static char *special_linkonce_name[] =
559 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
562 /* The best template for a particular sequence of up to three
564 #define N IA64_NUM_TYPES
565 static unsigned char best_template[N][N][N];
568 /* Resource dependencies currently in effect */
570 int depind; /* dependency index */
571 const struct ia64_dependency *dependency; /* actual dependency */
572 unsigned specific:1, /* is this a specific bit/regno? */
573 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
574 int index; /* specific regno/bit within dependency */
575 int note; /* optional qualifying note (0 if none) */
579 int insn_srlz; /* current insn serialization state */
580 int data_srlz; /* current data serialization state */
581 int qp_regno; /* qualifying predicate for this usage */
582 char *file; /* what file marked this dependency */
583 unsigned int line; /* what line marked this dependency */
584 struct mem_offset mem_offset; /* optional memory offset hint */
585 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
586 int path; /* corresponding code entry index */
588 static int regdepslen = 0;
589 static int regdepstotlen = 0;
590 static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
591 static const char *dv_sem[] = { "none", "implied", "impliedf",
592 "data", "instr", "specific", "stop", "other" };
593 static const char *dv_cmp_type[] = { "none", "OR", "AND" };
595 /* Current state of PR mutexation */
596 static struct qpmutex {
599 } *qp_mutexes = NULL; /* QP mutex bitmasks */
600 static int qp_mutexeslen = 0;
601 static int qp_mutexestotlen = 0;
602 static valueT qp_safe_across_calls = 0;
604 /* Current state of PR implications */
605 static struct qp_imply {
608 unsigned p2_branched:1;
610 } *qp_implies = NULL;
611 static int qp_implieslen = 0;
612 static int qp_impliestotlen = 0;
614 /* Keep track of static GR values so that indirect register usage can
615 sometimes be tracked. */
620 } gr_values[128] = {{ 1, 0, 0 }};
622 /* These are the routines required to output the various types of
625 /* A slot_number is a frag address plus the slot index (0-2). We use the
626 frag address here so that if there is a section switch in the middle of
627 a function, then instructions emitted to a different section are not
628 counted. Since there may be more than one frag for a function, this
629 means we also need to keep track of which frag this address belongs to
630 so we can compute inter-frag distances. This also nicely solves the
631 problem with nops emitted for align directives, which can't easily be
632 counted, but can easily be derived from frag sizes. */
634 typedef struct unw_rec_list {
636 unsigned long slot_number;
638 struct unw_rec_list *next;
641 #define SLOT_NUM_NOT_SET (unsigned)-1
643 /* Linked list of saved prologue counts. A very poor
644 implementation of a map from label numbers to prologue counts. */
645 typedef struct label_prologue_count
647 struct label_prologue_count *next;
648 unsigned long label_number;
649 unsigned int prologue_count;
650 } label_prologue_count;
654 unsigned long next_slot_number;
655 fragS *next_slot_frag;
657 /* Maintain a list of unwind entries for the current function. */
661 /* Any unwind entires that should be attached to the current slot
662 that an insn is being constructed for. */
663 unw_rec_list *current_entry;
665 /* These are used to create the unwind table entry for this function. */
668 symbolS *info; /* pointer to unwind info */
669 symbolS *personality_routine;
671 subsegT saved_text_subseg;
672 unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */
674 /* TRUE if processing unwind directives in a prologue region. */
677 unsigned int prologue_count; /* number of .prologues seen so far */
678 /* Prologue counts at previous .label_state directives. */
679 struct label_prologue_count * saved_prologue_counts;
682 typedef void (*vbyte_func) PARAMS ((int, char *, char *));
684 /* Forward delarations: */
685 static int ar_is_in_integer_unit PARAMS ((int regnum));
686 static void set_section PARAMS ((char *name));
687 static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
688 unsigned int, unsigned int));
689 static void dot_radix PARAMS ((int));
690 static void dot_special_section PARAMS ((int));
691 static void dot_proc PARAMS ((int));
692 static void dot_fframe PARAMS ((int));
693 static void dot_vframe PARAMS ((int));
694 static void dot_vframesp PARAMS ((int));
695 static void dot_vframepsp PARAMS ((int));
696 static void dot_save PARAMS ((int));
697 static void dot_restore PARAMS ((int));
698 static void dot_restorereg PARAMS ((int));
699 static void dot_restorereg_p PARAMS ((int));
700 static void dot_handlerdata PARAMS ((int));
701 static void dot_unwentry PARAMS ((int));
702 static void dot_altrp PARAMS ((int));
703 static void dot_savemem PARAMS ((int));
704 static void dot_saveg PARAMS ((int));
705 static void dot_savef PARAMS ((int));
706 static void dot_saveb PARAMS ((int));
707 static void dot_savegf PARAMS ((int));
708 static void dot_spill PARAMS ((int));
709 static void dot_spillreg PARAMS ((int));
710 static void dot_spillmem PARAMS ((int));
711 static void dot_spillreg_p PARAMS ((int));
712 static void dot_spillmem_p PARAMS ((int));
713 static void dot_label_state PARAMS ((int));
714 static void dot_copy_state PARAMS ((int));
715 static void dot_unwabi PARAMS ((int));
716 static void dot_personality PARAMS ((int));
717 static void dot_body PARAMS ((int));
718 static void dot_prologue PARAMS ((int));
719 static void dot_endp PARAMS ((int));
720 static void dot_template PARAMS ((int));
721 static void dot_regstk PARAMS ((int));
722 static void dot_rot PARAMS ((int));
723 static void dot_byteorder PARAMS ((int));
724 static void dot_psr PARAMS ((int));
725 static void dot_alias PARAMS ((int));
726 static void dot_ln PARAMS ((int));
727 static char *parse_section_name PARAMS ((void));
728 static void dot_xdata PARAMS ((int));
729 static void stmt_float_cons PARAMS ((int));
730 static void stmt_cons_ua PARAMS ((int));
731 static void dot_xfloat_cons PARAMS ((int));
732 static void dot_xstringer PARAMS ((int));
733 static void dot_xdata_ua PARAMS ((int));
734 static void dot_xfloat_cons_ua PARAMS ((int));
735 static void print_prmask PARAMS ((valueT mask));
736 static void dot_pred_rel PARAMS ((int));
737 static void dot_reg_val PARAMS ((int));
738 static void dot_dv_mode PARAMS ((int));
739 static void dot_entry PARAMS ((int));
740 static void dot_mem_offset PARAMS ((int));
741 static void add_unwind_entry PARAMS((unw_rec_list *ptr));
742 static symbolS *declare_register PARAMS ((const char *name, int regnum));
743 static void declare_register_set PARAMS ((const char *, int, int));
744 static unsigned int operand_width PARAMS ((enum ia64_opnd));
745 static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc,
748 static int parse_operand PARAMS ((expressionS *e));
749 static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
750 static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit));
751 static void build_insn PARAMS ((struct slot *, bfd_vma *));
752 static void emit_one_bundle PARAMS ((void));
753 static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
754 static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
755 bfd_reloc_code_real_type r_type));
756 static void insn_group_break PARAMS ((int, int, int));
757 static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
758 struct rsrc *, int depind, int path));
759 static void add_qp_mutex PARAMS((valueT mask));
760 static void add_qp_imply PARAMS((int p1, int p2));
761 static void clear_qp_branch_flag PARAMS((valueT mask));
762 static void clear_qp_mutex PARAMS((valueT mask));
763 static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
764 static int has_suffix_p PARAMS((const char *, const char *));
765 static void clear_register_values PARAMS ((void));
766 static void print_dependency PARAMS ((const char *action, int depind));
767 static void instruction_serialization PARAMS ((void));
768 static void data_serialization PARAMS ((void));
769 static void remove_marked_resource PARAMS ((struct rsrc *));
770 static int is_conditional_branch PARAMS ((struct ia64_opcode *));
771 static int is_taken_branch PARAMS ((struct ia64_opcode *));
772 static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
773 static int depends_on PARAMS ((int, struct ia64_opcode *));
774 static int specify_resource PARAMS ((const struct ia64_dependency *,
775 struct ia64_opcode *, int, struct rsrc [], int, int));
776 static int check_dv PARAMS((struct ia64_opcode *idesc));
777 static void check_dependencies PARAMS((struct ia64_opcode *));
778 static void mark_resources PARAMS((struct ia64_opcode *));
779 static void update_dependencies PARAMS((struct ia64_opcode *));
780 static void note_register_values PARAMS((struct ia64_opcode *));
781 static int qp_mutex PARAMS ((int, int, int));
782 static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
783 static void output_vbyte_mem PARAMS ((int, char *, char *));
784 static void count_output PARAMS ((int, char *, char *));
785 static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
786 static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
787 static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
788 static void output_P1_format PARAMS ((vbyte_func, int));
789 static void output_P2_format PARAMS ((vbyte_func, int, int));
790 static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
791 static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
792 static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
793 static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
794 static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
795 static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
796 static void output_P9_format PARAMS ((vbyte_func, int, int));
797 static void output_P10_format PARAMS ((vbyte_func, int, int));
798 static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
799 static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
800 static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
801 static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
802 static char format_ab_reg PARAMS ((int, int));
803 static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
805 static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
806 static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
808 static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
809 static void free_list_records PARAMS ((unw_rec_list *));
810 static unw_rec_list *output_prologue PARAMS ((void));
811 static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
812 static unw_rec_list *output_body PARAMS ((void));
813 static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
814 static unw_rec_list *output_mem_stack_v PARAMS ((void));
815 static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
816 static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
817 static unw_rec_list *output_rp_when PARAMS ((void));
818 static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
819 static unw_rec_list *output_rp_br PARAMS ((unsigned int));
820 static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
821 static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
822 static unw_rec_list *output_pfs_when PARAMS ((void));
823 static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
824 static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
825 static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
826 static unw_rec_list *output_preds_when PARAMS ((void));
827 static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
828 static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
829 static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
830 static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
831 static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
832 static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
833 static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
834 static unw_rec_list *output_br_mem PARAMS ((unsigned int));
835 static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
836 static unw_rec_list *output_spill_base PARAMS ((unsigned int));
837 static unw_rec_list *output_unat_when PARAMS ((void));
838 static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
839 static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
840 static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
841 static unw_rec_list *output_lc_when PARAMS ((void));
842 static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
843 static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
844 static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
845 static unw_rec_list *output_fpsr_when PARAMS ((void));
846 static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
847 static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
848 static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
849 static unw_rec_list *output_priunat_when_gr PARAMS ((void));
850 static unw_rec_list *output_priunat_when_mem PARAMS ((void));
851 static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
852 static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
853 static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
854 static unw_rec_list *output_bsp_when PARAMS ((void));
855 static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
856 static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
857 static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
858 static unw_rec_list *output_bspstore_when PARAMS ((void));
859 static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
860 static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
861 static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
862 static unw_rec_list *output_rnat_when PARAMS ((void));
863 static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
864 static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
865 static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
866 static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
867 static unw_rec_list *output_epilogue PARAMS ((unsigned long));
868 static unw_rec_list *output_label_state PARAMS ((unsigned long));
869 static unw_rec_list *output_copy_state PARAMS ((unsigned long));
870 static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
871 static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
872 static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
874 static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
876 static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
878 static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
879 unsigned int, unsigned int));
880 static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
881 static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
882 static int calc_record_size PARAMS ((unw_rec_list *));
883 static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
884 static int count_bits PARAMS ((unsigned long));
885 static unsigned long slot_index PARAMS ((unsigned long, fragS *,
886 unsigned long, fragS *));
887 static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *));
888 static void fixup_unw_records PARAMS ((unw_rec_list *));
889 static int output_unw_records PARAMS ((unw_rec_list *, void **));
890 static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
891 static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
892 static int generate_unwind_image PARAMS ((const char *));
893 static unsigned int get_saved_prologue_count PARAMS ((unsigned long));
894 static void save_prologue_count PARAMS ((unsigned long, unsigned int));
895 static void free_saved_prologue_counts PARAMS ((void));
897 /* Build the unwind section name by appending the (possibly stripped)
898 text section NAME to the unwind PREFIX. The resulting string
899 pointer is assigned to RESULT. The string is allocated on the
900 stack, so this must be a macro... */
901 #define make_unw_section_name(special, text_name, result) \
903 const char *_prefix = special_section_name[special]; \
904 const char *_suffix = text_name; \
905 size_t _prefix_len, _suffix_len; \
907 if (strncmp (text_name, ".gnu.linkonce.t.", \
908 sizeof (".gnu.linkonce.t.") - 1) == 0) \
910 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
911 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
913 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
914 _result = alloca (_prefix_len + _suffix_len + 1); \
915 memcpy (_result, _prefix, _prefix_len); \
916 memcpy (_result + _prefix_len, _suffix, _suffix_len); \
917 _result[_prefix_len + _suffix_len] = '\0'; \
922 /* Determine if application register REGNUM resides in the integer
923 unit (as opposed to the memory unit). */
925 ar_is_in_integer_unit (reg)
930 return (reg == 64 /* pfs */
931 || reg == 65 /* lc */
932 || reg == 66 /* ec */
933 /* ??? ias accepts and puts these in the integer unit. */
934 || (reg >= 112 && reg <= 127));
937 /* Switch to section NAME and create section if necessary. It's
938 rather ugly that we have to manipulate input_line_pointer but I
939 don't see any other way to accomplish the same thing without
940 changing obj-elf.c (which may be the Right Thing, in the end). */
945 char *saved_input_line_pointer;
947 saved_input_line_pointer = input_line_pointer;
948 input_line_pointer = name;
950 input_line_pointer = saved_input_line_pointer;
953 /* Map 's' to SHF_IA_64_SHORT. */
956 ia64_elf_section_letter (letter, ptr_msg)
961 return SHF_IA_64_SHORT;
963 *ptr_msg = _("Bad .section directive: want a,s,w,x,M,S,G,T in string");
967 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
970 ia64_elf_section_flags (flags, attr, type)
972 int attr, type ATTRIBUTE_UNUSED;
974 if (attr & SHF_IA_64_SHORT)
975 flags |= SEC_SMALL_DATA;
980 ia64_elf_section_type (str, len)
984 #define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0))
986 if (STREQ (ELF_STRING_ia64_unwind_info))
989 if (STREQ (ELF_STRING_ia64_unwind_info_once))
992 if (STREQ (ELF_STRING_ia64_unwind))
993 return SHT_IA_64_UNWIND;
995 if (STREQ (ELF_STRING_ia64_unwind_once))
996 return SHT_IA_64_UNWIND;
998 if (STREQ ("init_array"))
999 return SHT_INIT_ARRAY;
1001 if (STREQ ("fini_array"))
1002 return SHT_FINI_ARRAY;
1009 set_regstack (ins, locs, outs, rots)
1010 unsigned int ins, locs, outs, rots;
1012 /* Size of frame. */
1015 sof = ins + locs + outs;
1018 as_bad ("Size of frame exceeds maximum of 96 registers");
1023 as_warn ("Size of rotating registers exceeds frame size");
1026 md.in.base = REG_GR + 32;
1027 md.loc.base = md.in.base + ins;
1028 md.out.base = md.loc.base + locs;
1030 md.in.num_regs = ins;
1031 md.loc.num_regs = locs;
1032 md.out.num_regs = outs;
1033 md.rot.num_regs = rots;
1040 struct label_fix *lfix;
1042 subsegT saved_subseg;
1045 if (!md.last_text_seg)
1048 saved_seg = now_seg;
1049 saved_subseg = now_subseg;
1051 subseg_set (md.last_text_seg, 0);
1053 while (md.num_slots_in_use > 0)
1054 emit_one_bundle (); /* force out queued instructions */
1056 /* In case there are labels following the last instruction, resolve
1058 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
1060 S_SET_VALUE (lfix->sym, frag_now_fix ());
1061 symbol_set_frag (lfix->sym, frag_now);
1063 CURR_SLOT.label_fixups = 0;
1064 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
1066 S_SET_VALUE (lfix->sym, frag_now_fix ());
1067 symbol_set_frag (lfix->sym, frag_now);
1069 CURR_SLOT.tag_fixups = 0;
1071 /* In case there are unwind directives following the last instruction,
1072 resolve those now. We only handle body and prologue directives here.
1073 Give an error for others. */
1074 for (ptr = unwind.current_entry; ptr; ptr = ptr->next)
1076 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
1077 || ptr->r.type == body)
1079 ptr->slot_number = (unsigned long) frag_more (0);
1080 ptr->slot_frag = frag_now;
1083 as_bad (_("Unwind directive not followed by an instruction."));
1085 unwind.current_entry = NULL;
1087 subseg_set (saved_seg, saved_subseg);
1089 if (md.qp.X_op == O_register)
1090 as_bad ("qualifying predicate not followed by instruction");
1094 ia64_do_align (nbytes)
1097 char *saved_input_line_pointer = input_line_pointer;
1099 input_line_pointer = "";
1100 s_align_bytes (nbytes);
1101 input_line_pointer = saved_input_line_pointer;
1105 ia64_cons_align (nbytes)
1110 char *saved_input_line_pointer = input_line_pointer;
1111 input_line_pointer = "";
1112 s_align_bytes (nbytes);
1113 input_line_pointer = saved_input_line_pointer;
1117 /* Output COUNT bytes to a memory location. */
1118 static unsigned char *vbyte_mem_ptr = NULL;
1121 output_vbyte_mem (count, ptr, comment)
1124 char *comment ATTRIBUTE_UNUSED;
1127 if (vbyte_mem_ptr == NULL)
1132 for (x = 0; x < count; x++)
1133 *(vbyte_mem_ptr++) = ptr[x];
1136 /* Count the number of bytes required for records. */
1137 static int vbyte_count = 0;
1139 count_output (count, ptr, comment)
1141 char *ptr ATTRIBUTE_UNUSED;
1142 char *comment ATTRIBUTE_UNUSED;
1144 vbyte_count += count;
1148 output_R1_format (f, rtype, rlen)
1150 unw_record_type rtype;
1157 output_R3_format (f, rtype, rlen);
1163 else if (rtype != prologue)
1164 as_bad ("record type is not valid");
1166 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
1167 (*f) (1, &byte, NULL);
1171 output_R2_format (f, mask, grsave, rlen)
1178 mask = (mask & 0x0f);
1179 grsave = (grsave & 0x7f);
1181 bytes[0] = (UNW_R2 | (mask >> 1));
1182 bytes[1] = (((mask & 0x01) << 7) | grsave);
1183 count += output_leb128 (bytes + 2, rlen, 0);
1184 (*f) (count, bytes, NULL);
1188 output_R3_format (f, rtype, rlen)
1190 unw_record_type rtype;
1197 output_R1_format (f, rtype, rlen);
1203 else if (rtype != prologue)
1204 as_bad ("record type is not valid");
1205 bytes[0] = (UNW_R3 | r);
1206 count = output_leb128 (bytes + 1, rlen, 0);
1207 (*f) (count + 1, bytes, NULL);
1211 output_P1_format (f, brmask)
1216 byte = UNW_P1 | (brmask & 0x1f);
1217 (*f) (1, &byte, NULL);
1221 output_P2_format (f, brmask, gr)
1227 brmask = (brmask & 0x1f);
1228 bytes[0] = UNW_P2 | (brmask >> 1);
1229 bytes[1] = (((brmask & 1) << 7) | gr);
1230 (*f) (2, bytes, NULL);
1234 output_P3_format (f, rtype, reg)
1236 unw_record_type rtype;
1281 as_bad ("Invalid record type for P3 format.");
1283 bytes[0] = (UNW_P3 | (r >> 1));
1284 bytes[1] = (((r & 1) << 7) | reg);
1285 (*f) (2, bytes, NULL);
1289 output_P4_format (f, imask, imask_size)
1291 unsigned char *imask;
1292 unsigned long imask_size;
1295 (*f) (imask_size, imask, NULL);
1299 output_P5_format (f, grmask, frmask)
1302 unsigned long frmask;
1305 grmask = (grmask & 0x0f);
1308 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1309 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1310 bytes[3] = (frmask & 0x000000ff);
1311 (*f) (4, bytes, NULL);
1315 output_P6_format (f, rtype, rmask)
1317 unw_record_type rtype;
1323 if (rtype == gr_mem)
1325 else if (rtype != fr_mem)
1326 as_bad ("Invalid record type for format P6");
1327 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1328 (*f) (1, &byte, NULL);
1332 output_P7_format (f, rtype, w1, w2)
1334 unw_record_type rtype;
1341 count += output_leb128 (bytes + 1, w1, 0);
1346 count += output_leb128 (bytes + count, w2 >> 4, 0);
1396 bytes[0] = (UNW_P7 | r);
1397 (*f) (count, bytes, NULL);
1401 output_P8_format (f, rtype, t)
1403 unw_record_type rtype;
1442 case bspstore_psprel:
1445 case bspstore_sprel:
1457 case priunat_when_gr:
1460 case priunat_psprel:
1466 case priunat_when_mem:
1473 count += output_leb128 (bytes + 2, t, 0);
1474 (*f) (count, bytes, NULL);
1478 output_P9_format (f, grmask, gr)
1485 bytes[1] = (grmask & 0x0f);
1486 bytes[2] = (gr & 0x7f);
1487 (*f) (3, bytes, NULL);
1491 output_P10_format (f, abi, context)
1498 bytes[1] = (abi & 0xff);
1499 bytes[2] = (context & 0xff);
1500 (*f) (3, bytes, NULL);
1504 output_B1_format (f, rtype, label)
1506 unw_record_type rtype;
1507 unsigned long label;
1513 output_B4_format (f, rtype, label);
1516 if (rtype == copy_state)
1518 else if (rtype != label_state)
1519 as_bad ("Invalid record type for format B1");
1521 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1522 (*f) (1, &byte, NULL);
1526 output_B2_format (f, ecount, t)
1528 unsigned long ecount;
1535 output_B3_format (f, ecount, t);
1538 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1539 count += output_leb128 (bytes + 1, t, 0);
1540 (*f) (count, bytes, NULL);
1544 output_B3_format (f, ecount, t)
1546 unsigned long ecount;
1553 output_B2_format (f, ecount, t);
1557 count += output_leb128 (bytes + 1, t, 0);
1558 count += output_leb128 (bytes + count, ecount, 0);
1559 (*f) (count, bytes, NULL);
1563 output_B4_format (f, rtype, label)
1565 unw_record_type rtype;
1566 unsigned long label;
1573 output_B1_format (f, rtype, label);
1577 if (rtype == copy_state)
1579 else if (rtype != label_state)
1580 as_bad ("Invalid record type for format B1");
1582 bytes[0] = (UNW_B4 | (r << 3));
1583 count += output_leb128 (bytes + 1, label, 0);
1584 (*f) (count, bytes, NULL);
1588 format_ab_reg (ab, reg)
1595 ret = (ab << 5) | reg;
1600 output_X1_format (f, rtype, ab, reg, t, w1)
1602 unw_record_type rtype;
1612 if (rtype == spill_sprel)
1614 else if (rtype != spill_psprel)
1615 as_bad ("Invalid record type for format X1");
1616 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
1617 count += output_leb128 (bytes + 2, t, 0);
1618 count += output_leb128 (bytes + count, w1, 0);
1619 (*f) (count, bytes, NULL);
1623 output_X2_format (f, ab, reg, x, y, treg, t)
1632 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1633 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1634 count += output_leb128 (bytes + 3, t, 0);
1635 (*f) (count, bytes, NULL);
1639 output_X3_format (f, rtype, qp, ab, reg, t, w1)
1641 unw_record_type rtype;
1652 if (rtype == spill_sprel_p)
1654 else if (rtype != spill_psprel_p)
1655 as_bad ("Invalid record type for format X3");
1656 bytes[1] = ((r << 7) | (qp & 0x3f));
1657 bytes[2] = format_ab_reg (ab, reg);
1658 count += output_leb128 (bytes + 3, t, 0);
1659 count += output_leb128 (bytes + count, w1, 0);
1660 (*f) (count, bytes, NULL);
1664 output_X4_format (f, qp, ab, reg, x, y, treg, t)
1674 bytes[1] = (qp & 0x3f);
1675 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1676 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1677 count += output_leb128 (bytes + 4, t, 0);
1678 (*f) (count, bytes, NULL);
1681 /* This function allocates a record list structure, and initializes fields. */
1683 static unw_rec_list *
1684 alloc_record (unw_record_type t)
1687 ptr = xmalloc (sizeof (*ptr));
1689 ptr->slot_number = SLOT_NUM_NOT_SET;
1694 /* This function frees an entire list of record structures. */
1697 free_list_records (unw_rec_list *first)
1700 for (ptr = first; ptr != NULL;)
1702 unw_rec_list *tmp = ptr;
1704 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1705 && tmp->r.record.r.mask.i)
1706 free (tmp->r.record.r.mask.i);
1713 static unw_rec_list *
1716 unw_rec_list *ptr = alloc_record (prologue);
1717 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1721 static unw_rec_list *
1722 output_prologue_gr (saved_mask, reg)
1723 unsigned int saved_mask;
1726 unw_rec_list *ptr = alloc_record (prologue_gr);
1727 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1728 ptr->r.record.r.grmask = saved_mask;
1729 ptr->r.record.r.grsave = reg;
1733 static unw_rec_list *
1736 unw_rec_list *ptr = alloc_record (body);
1740 static unw_rec_list *
1741 output_mem_stack_f (size)
1744 unw_rec_list *ptr = alloc_record (mem_stack_f);
1745 ptr->r.record.p.size = size;
1749 static unw_rec_list *
1750 output_mem_stack_v ()
1752 unw_rec_list *ptr = alloc_record (mem_stack_v);
1756 static unw_rec_list *
1760 unw_rec_list *ptr = alloc_record (psp_gr);
1761 ptr->r.record.p.gr = gr;
1765 static unw_rec_list *
1766 output_psp_sprel (offset)
1767 unsigned int offset;
1769 unw_rec_list *ptr = alloc_record (psp_sprel);
1770 ptr->r.record.p.spoff = offset / 4;
1774 static unw_rec_list *
1777 unw_rec_list *ptr = alloc_record (rp_when);
1781 static unw_rec_list *
1785 unw_rec_list *ptr = alloc_record (rp_gr);
1786 ptr->r.record.p.gr = gr;
1790 static unw_rec_list *
1794 unw_rec_list *ptr = alloc_record (rp_br);
1795 ptr->r.record.p.br = br;
1799 static unw_rec_list *
1800 output_rp_psprel (offset)
1801 unsigned int offset;
1803 unw_rec_list *ptr = alloc_record (rp_psprel);
1804 ptr->r.record.p.pspoff = offset / 4;
1808 static unw_rec_list *
1809 output_rp_sprel (offset)
1810 unsigned int offset;
1812 unw_rec_list *ptr = alloc_record (rp_sprel);
1813 ptr->r.record.p.spoff = offset / 4;
1817 static unw_rec_list *
1820 unw_rec_list *ptr = alloc_record (pfs_when);
1824 static unw_rec_list *
1828 unw_rec_list *ptr = alloc_record (pfs_gr);
1829 ptr->r.record.p.gr = gr;
1833 static unw_rec_list *
1834 output_pfs_psprel (offset)
1835 unsigned int offset;
1837 unw_rec_list *ptr = alloc_record (pfs_psprel);
1838 ptr->r.record.p.pspoff = offset / 4;
1842 static unw_rec_list *
1843 output_pfs_sprel (offset)
1844 unsigned int offset;
1846 unw_rec_list *ptr = alloc_record (pfs_sprel);
1847 ptr->r.record.p.spoff = offset / 4;
1851 static unw_rec_list *
1852 output_preds_when ()
1854 unw_rec_list *ptr = alloc_record (preds_when);
1858 static unw_rec_list *
1859 output_preds_gr (gr)
1862 unw_rec_list *ptr = alloc_record (preds_gr);
1863 ptr->r.record.p.gr = gr;
1867 static unw_rec_list *
1868 output_preds_psprel (offset)
1869 unsigned int offset;
1871 unw_rec_list *ptr = alloc_record (preds_psprel);
1872 ptr->r.record.p.pspoff = offset / 4;
1876 static unw_rec_list *
1877 output_preds_sprel (offset)
1878 unsigned int offset;
1880 unw_rec_list *ptr = alloc_record (preds_sprel);
1881 ptr->r.record.p.spoff = offset / 4;
1885 static unw_rec_list *
1886 output_fr_mem (mask)
1889 unw_rec_list *ptr = alloc_record (fr_mem);
1890 ptr->r.record.p.rmask = mask;
1894 static unw_rec_list *
1895 output_frgr_mem (gr_mask, fr_mask)
1896 unsigned int gr_mask;
1897 unsigned int fr_mask;
1899 unw_rec_list *ptr = alloc_record (frgr_mem);
1900 ptr->r.record.p.grmask = gr_mask;
1901 ptr->r.record.p.frmask = fr_mask;
1905 static unw_rec_list *
1906 output_gr_gr (mask, reg)
1910 unw_rec_list *ptr = alloc_record (gr_gr);
1911 ptr->r.record.p.grmask = mask;
1912 ptr->r.record.p.gr = reg;
1916 static unw_rec_list *
1917 output_gr_mem (mask)
1920 unw_rec_list *ptr = alloc_record (gr_mem);
1921 ptr->r.record.p.rmask = mask;
1925 static unw_rec_list *
1926 output_br_mem (unsigned int mask)
1928 unw_rec_list *ptr = alloc_record (br_mem);
1929 ptr->r.record.p.brmask = mask;
1933 static unw_rec_list *
1934 output_br_gr (save_mask, reg)
1935 unsigned int save_mask;
1938 unw_rec_list *ptr = alloc_record (br_gr);
1939 ptr->r.record.p.brmask = save_mask;
1940 ptr->r.record.p.gr = reg;
1944 static unw_rec_list *
1945 output_spill_base (offset)
1946 unsigned int offset;
1948 unw_rec_list *ptr = alloc_record (spill_base);
1949 ptr->r.record.p.pspoff = offset / 4;
1953 static unw_rec_list *
1956 unw_rec_list *ptr = alloc_record (unat_when);
1960 static unw_rec_list *
1964 unw_rec_list *ptr = alloc_record (unat_gr);
1965 ptr->r.record.p.gr = gr;
1969 static unw_rec_list *
1970 output_unat_psprel (offset)
1971 unsigned int offset;
1973 unw_rec_list *ptr = alloc_record (unat_psprel);
1974 ptr->r.record.p.pspoff = offset / 4;
1978 static unw_rec_list *
1979 output_unat_sprel (offset)
1980 unsigned int offset;
1982 unw_rec_list *ptr = alloc_record (unat_sprel);
1983 ptr->r.record.p.spoff = offset / 4;
1987 static unw_rec_list *
1990 unw_rec_list *ptr = alloc_record (lc_when);
1994 static unw_rec_list *
1998 unw_rec_list *ptr = alloc_record (lc_gr);
1999 ptr->r.record.p.gr = gr;
2003 static unw_rec_list *
2004 output_lc_psprel (offset)
2005 unsigned int offset;
2007 unw_rec_list *ptr = alloc_record (lc_psprel);
2008 ptr->r.record.p.pspoff = offset / 4;
2012 static unw_rec_list *
2013 output_lc_sprel (offset)
2014 unsigned int offset;
2016 unw_rec_list *ptr = alloc_record (lc_sprel);
2017 ptr->r.record.p.spoff = offset / 4;
2021 static unw_rec_list *
2024 unw_rec_list *ptr = alloc_record (fpsr_when);
2028 static unw_rec_list *
2032 unw_rec_list *ptr = alloc_record (fpsr_gr);
2033 ptr->r.record.p.gr = gr;
2037 static unw_rec_list *
2038 output_fpsr_psprel (offset)
2039 unsigned int offset;
2041 unw_rec_list *ptr = alloc_record (fpsr_psprel);
2042 ptr->r.record.p.pspoff = offset / 4;
2046 static unw_rec_list *
2047 output_fpsr_sprel (offset)
2048 unsigned int offset;
2050 unw_rec_list *ptr = alloc_record (fpsr_sprel);
2051 ptr->r.record.p.spoff = offset / 4;
2055 static unw_rec_list *
2056 output_priunat_when_gr ()
2058 unw_rec_list *ptr = alloc_record (priunat_when_gr);
2062 static unw_rec_list *
2063 output_priunat_when_mem ()
2065 unw_rec_list *ptr = alloc_record (priunat_when_mem);
2069 static unw_rec_list *
2070 output_priunat_gr (gr)
2073 unw_rec_list *ptr = alloc_record (priunat_gr);
2074 ptr->r.record.p.gr = gr;
2078 static unw_rec_list *
2079 output_priunat_psprel (offset)
2080 unsigned int offset;
2082 unw_rec_list *ptr = alloc_record (priunat_psprel);
2083 ptr->r.record.p.pspoff = offset / 4;
2087 static unw_rec_list *
2088 output_priunat_sprel (offset)
2089 unsigned int offset;
2091 unw_rec_list *ptr = alloc_record (priunat_sprel);
2092 ptr->r.record.p.spoff = offset / 4;
2096 static unw_rec_list *
2099 unw_rec_list *ptr = alloc_record (bsp_when);
2103 static unw_rec_list *
2107 unw_rec_list *ptr = alloc_record (bsp_gr);
2108 ptr->r.record.p.gr = gr;
2112 static unw_rec_list *
2113 output_bsp_psprel (offset)
2114 unsigned int offset;
2116 unw_rec_list *ptr = alloc_record (bsp_psprel);
2117 ptr->r.record.p.pspoff = offset / 4;
2121 static unw_rec_list *
2122 output_bsp_sprel (offset)
2123 unsigned int offset;
2125 unw_rec_list *ptr = alloc_record (bsp_sprel);
2126 ptr->r.record.p.spoff = offset / 4;
2130 static unw_rec_list *
2131 output_bspstore_when ()
2133 unw_rec_list *ptr = alloc_record (bspstore_when);
2137 static unw_rec_list *
2138 output_bspstore_gr (gr)
2141 unw_rec_list *ptr = alloc_record (bspstore_gr);
2142 ptr->r.record.p.gr = gr;
2146 static unw_rec_list *
2147 output_bspstore_psprel (offset)
2148 unsigned int offset;
2150 unw_rec_list *ptr = alloc_record (bspstore_psprel);
2151 ptr->r.record.p.pspoff = offset / 4;
2155 static unw_rec_list *
2156 output_bspstore_sprel (offset)
2157 unsigned int offset;
2159 unw_rec_list *ptr = alloc_record (bspstore_sprel);
2160 ptr->r.record.p.spoff = offset / 4;
2164 static unw_rec_list *
2167 unw_rec_list *ptr = alloc_record (rnat_when);
2171 static unw_rec_list *
2175 unw_rec_list *ptr = alloc_record (rnat_gr);
2176 ptr->r.record.p.gr = gr;
2180 static unw_rec_list *
2181 output_rnat_psprel (offset)
2182 unsigned int offset;
2184 unw_rec_list *ptr = alloc_record (rnat_psprel);
2185 ptr->r.record.p.pspoff = offset / 4;
2189 static unw_rec_list *
2190 output_rnat_sprel (offset)
2191 unsigned int offset;
2193 unw_rec_list *ptr = alloc_record (rnat_sprel);
2194 ptr->r.record.p.spoff = offset / 4;
2198 static unw_rec_list *
2199 output_unwabi (abi, context)
2201 unsigned long context;
2203 unw_rec_list *ptr = alloc_record (unwabi);
2204 ptr->r.record.p.abi = abi;
2205 ptr->r.record.p.context = context;
2209 static unw_rec_list *
2210 output_epilogue (unsigned long ecount)
2212 unw_rec_list *ptr = alloc_record (epilogue);
2213 ptr->r.record.b.ecount = ecount;
2217 static unw_rec_list *
2218 output_label_state (unsigned long label)
2220 unw_rec_list *ptr = alloc_record (label_state);
2221 ptr->r.record.b.label = label;
2225 static unw_rec_list *
2226 output_copy_state (unsigned long label)
2228 unw_rec_list *ptr = alloc_record (copy_state);
2229 ptr->r.record.b.label = label;
2233 static unw_rec_list *
2234 output_spill_psprel (ab, reg, offset)
2237 unsigned int offset;
2239 unw_rec_list *ptr = alloc_record (spill_psprel);
2240 ptr->r.record.x.ab = ab;
2241 ptr->r.record.x.reg = reg;
2242 ptr->r.record.x.pspoff = offset / 4;
2246 static unw_rec_list *
2247 output_spill_sprel (ab, reg, offset)
2250 unsigned int offset;
2252 unw_rec_list *ptr = alloc_record (spill_sprel);
2253 ptr->r.record.x.ab = ab;
2254 ptr->r.record.x.reg = reg;
2255 ptr->r.record.x.spoff = offset / 4;
2259 static unw_rec_list *
2260 output_spill_psprel_p (ab, reg, offset, predicate)
2263 unsigned int offset;
2264 unsigned int predicate;
2266 unw_rec_list *ptr = alloc_record (spill_psprel_p);
2267 ptr->r.record.x.ab = ab;
2268 ptr->r.record.x.reg = reg;
2269 ptr->r.record.x.pspoff = offset / 4;
2270 ptr->r.record.x.qp = predicate;
2274 static unw_rec_list *
2275 output_spill_sprel_p (ab, reg, offset, predicate)
2278 unsigned int offset;
2279 unsigned int predicate;
2281 unw_rec_list *ptr = alloc_record (spill_sprel_p);
2282 ptr->r.record.x.ab = ab;
2283 ptr->r.record.x.reg = reg;
2284 ptr->r.record.x.spoff = offset / 4;
2285 ptr->r.record.x.qp = predicate;
2289 static unw_rec_list *
2290 output_spill_reg (ab, reg, targ_reg, xy)
2293 unsigned int targ_reg;
2296 unw_rec_list *ptr = alloc_record (spill_reg);
2297 ptr->r.record.x.ab = ab;
2298 ptr->r.record.x.reg = reg;
2299 ptr->r.record.x.treg = targ_reg;
2300 ptr->r.record.x.xy = xy;
2304 static unw_rec_list *
2305 output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2308 unsigned int targ_reg;
2310 unsigned int predicate;
2312 unw_rec_list *ptr = alloc_record (spill_reg_p);
2313 ptr->r.record.x.ab = ab;
2314 ptr->r.record.x.reg = reg;
2315 ptr->r.record.x.treg = targ_reg;
2316 ptr->r.record.x.xy = xy;
2317 ptr->r.record.x.qp = predicate;
2321 /* Given a unw_rec_list process the correct format with the
2322 specified function. */
2325 process_one_record (ptr, f)
2329 unsigned long fr_mask, gr_mask;
2331 switch (ptr->r.type)
2337 /* These are taken care of by prologue/prologue_gr. */
2342 if (ptr->r.type == prologue_gr)
2343 output_R2_format (f, ptr->r.record.r.grmask,
2344 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2346 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2348 /* Output descriptor(s) for union of register spills (if any). */
2349 gr_mask = ptr->r.record.r.mask.gr_mem;
2350 fr_mask = ptr->r.record.r.mask.fr_mem;
2353 if ((fr_mask & ~0xfUL) == 0)
2354 output_P6_format (f, fr_mem, fr_mask);
2357 output_P5_format (f, gr_mask, fr_mask);
2362 output_P6_format (f, gr_mem, gr_mask);
2363 if (ptr->r.record.r.mask.br_mem)
2364 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2366 /* output imask descriptor if necessary: */
2367 if (ptr->r.record.r.mask.i)
2368 output_P4_format (f, ptr->r.record.r.mask.i,
2369 ptr->r.record.r.imask_size);
2373 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2377 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2378 ptr->r.record.p.size);
2391 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2394 output_P3_format (f, rp_br, ptr->r.record.p.br);
2397 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2405 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2414 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2424 case bspstore_sprel:
2426 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2429 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2432 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2435 as_bad ("spill_mask record unimplemented.");
2437 case priunat_when_gr:
2438 case priunat_when_mem:
2442 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2444 case priunat_psprel:
2446 case bspstore_psprel:
2448 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2451 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2454 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2458 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2461 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2462 ptr->r.record.x.reg, ptr->r.record.x.t,
2463 ptr->r.record.x.pspoff);
2466 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2467 ptr->r.record.x.reg, ptr->r.record.x.t,
2468 ptr->r.record.x.spoff);
2471 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2472 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2473 ptr->r.record.x.treg, ptr->r.record.x.t);
2475 case spill_psprel_p:
2476 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2477 ptr->r.record.x.ab, ptr->r.record.x.reg,
2478 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2481 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2482 ptr->r.record.x.ab, ptr->r.record.x.reg,
2483 ptr->r.record.x.t, ptr->r.record.x.spoff);
2486 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2487 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2488 ptr->r.record.x.xy, ptr->r.record.x.treg,
2492 as_bad ("record_type_not_valid");
2497 /* Given a unw_rec_list list, process all the records with
2498 the specified function. */
2500 process_unw_records (list, f)
2505 for (ptr = list; ptr; ptr = ptr->next)
2506 process_one_record (ptr, f);
2509 /* Determine the size of a record list in bytes. */
2511 calc_record_size (list)
2515 process_unw_records (list, count_output);
2519 /* Update IMASK bitmask to reflect the fact that one or more registers
2520 of type TYPE are saved starting at instruction with index T. If N
2521 bits are set in REGMASK, it is assumed that instructions T through
2522 T+N-1 save these registers.
2526 1: instruction saves next fp reg
2527 2: instruction saves next general reg
2528 3: instruction saves next branch reg */
2530 set_imask (region, regmask, t, type)
2531 unw_rec_list *region;
2532 unsigned long regmask;
2536 unsigned char *imask;
2537 unsigned long imask_size;
2541 imask = region->r.record.r.mask.i;
2542 imask_size = region->r.record.r.imask_size;
2545 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
2546 imask = xmalloc (imask_size);
2547 memset (imask, 0, imask_size);
2549 region->r.record.r.imask_size = imask_size;
2550 region->r.record.r.mask.i = imask;
2554 pos = 2 * (3 - t % 4);
2557 if (i >= imask_size)
2559 as_bad ("Ignoring attempt to spill beyond end of region");
2563 imask[i] |= (type & 0x3) << pos;
2565 regmask &= (regmask - 1);
2576 count_bits (unsigned long mask)
2588 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2589 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2590 containing FIRST_ADDR. */
2593 slot_index (slot_addr, slot_frag, first_addr, first_frag)
2594 unsigned long slot_addr;
2596 unsigned long first_addr;
2599 unsigned long index = 0;
2601 /* First time we are called, the initial address and frag are invalid. */
2602 if (first_addr == 0)
2605 /* If the two addresses are in different frags, then we need to add in
2606 the remaining size of this frag, and then the entire size of intermediate
2608 while (slot_frag != first_frag)
2610 unsigned long start_addr = (unsigned long) &first_frag->fr_literal;
2612 /* Add in the full size of the frag converted to instruction slots. */
2613 index += 3 * (first_frag->fr_fix >> 4);
2614 /* Subtract away the initial part before first_addr. */
2615 index -= (3 * ((first_addr >> 4) - (start_addr >> 4))
2616 + ((first_addr & 0x3) - (start_addr & 0x3)));
2618 /* Move to the beginning of the next frag. */
2619 first_frag = first_frag->fr_next;
2620 first_addr = (unsigned long) &first_frag->fr_literal;
2623 /* Add in the used part of the last frag. */
2624 index += (3 * ((slot_addr >> 4) - (first_addr >> 4))
2625 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2629 /* Optimize unwind record directives. */
2631 static unw_rec_list *
2632 optimize_unw_records (list)
2638 /* If the only unwind record is ".prologue" or ".prologue" followed
2639 by ".body", then we can optimize the unwind directives away. */
2640 if (list->r.type == prologue
2641 && (list->next == NULL
2642 || (list->next->r.type == body && list->next->next == NULL)))
2648 /* Given a complete record list, process any records which have
2649 unresolved fields, (ie length counts for a prologue). After
2650 this has been run, all neccessary information should be available
2651 within each record to generate an image. */
2654 fixup_unw_records (list)
2657 unw_rec_list *ptr, *region = 0;
2658 unsigned long first_addr = 0, rlen = 0, t;
2659 fragS *first_frag = 0;
2661 for (ptr = list; ptr; ptr = ptr->next)
2663 if (ptr->slot_number == SLOT_NUM_NOT_SET)
2664 as_bad (" Insn slot not set in unwind record.");
2665 t = slot_index (ptr->slot_number, ptr->slot_frag,
2666 first_addr, first_frag);
2667 switch (ptr->r.type)
2674 int size, dir_len = 0;
2675 unsigned long last_addr;
2678 first_addr = ptr->slot_number;
2679 first_frag = ptr->slot_frag;
2680 ptr->slot_number = 0;
2681 /* Find either the next body/prologue start, or the end of
2682 the list, and determine the size of the region. */
2683 last_addr = unwind.next_slot_number;
2684 last_frag = unwind.next_slot_frag;
2685 for (last = ptr->next; last != NULL; last = last->next)
2686 if (last->r.type == prologue || last->r.type == prologue_gr
2687 || last->r.type == body)
2689 last_addr = last->slot_number;
2690 last_frag = last->slot_frag;
2693 else if (!last->next)
2695 /* In the absence of an explicit .body directive,
2696 the prologue ends after the last instruction
2697 covered by an unwind directive. */
2698 if (ptr->r.type != body)
2700 last_addr = last->slot_number;
2701 last_frag = last->slot_frag;
2702 switch (last->r.type)
2705 dir_len = (count_bits (last->r.record.p.frmask)
2706 + count_bits (last->r.record.p.grmask));
2710 dir_len += count_bits (last->r.record.p.rmask);
2714 dir_len += count_bits (last->r.record.p.brmask);
2717 dir_len += count_bits (last->r.record.p.grmask);
2726 size = (slot_index (last_addr, last_frag, first_addr, first_frag)
2728 rlen = ptr->r.record.r.rlen = size;
2729 if (ptr->r.type == body)
2730 /* End of region. */
2737 ptr->r.record.b.t = rlen - 1 - t;
2748 case priunat_when_gr:
2749 case priunat_when_mem:
2753 ptr->r.record.p.t = t;
2761 case spill_psprel_p:
2762 ptr->r.record.x.t = t;
2768 as_bad ("frgr_mem record before region record!\n");
2771 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2772 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2773 set_imask (region, ptr->r.record.p.frmask, t, 1);
2774 set_imask (region, ptr->r.record.p.grmask, t, 2);
2779 as_bad ("fr_mem record before region record!\n");
2782 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2783 set_imask (region, ptr->r.record.p.rmask, t, 1);
2788 as_bad ("gr_mem record before region record!\n");
2791 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2792 set_imask (region, ptr->r.record.p.rmask, t, 2);
2797 as_bad ("br_mem record before region record!\n");
2800 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2801 set_imask (region, ptr->r.record.p.brmask, t, 3);
2807 as_bad ("gr_gr record before region record!\n");
2810 set_imask (region, ptr->r.record.p.grmask, t, 2);
2815 as_bad ("br_gr record before region record!\n");
2818 set_imask (region, ptr->r.record.p.brmask, t, 3);
2827 /* Helper routine for output_unw_records. Emits the header for the unwind
2831 setup_unwind_header (int size, unsigned char **mem)
2836 /* pad to pointer-size boundry. */
2837 x = size % md.pointer_size;
2839 extra = md.pointer_size - x;
2841 /* Add 8 for the header + a pointer for the
2842 personality offset. */
2843 *mem = xmalloc (size + extra + 8 + md.pointer_size);
2845 /* Clear the padding area and personality. */
2846 memset (*mem + 8 + size, 0, extra + md.pointer_size);
2848 /* Initialize the header area. */
2849 if (unwind.personality_routine)
2851 if (md.flags & EF_IA_64_ABI64)
2852 flag_value = (bfd_vma) 3 << 32;
2854 /* 32-bit unwind info block. */
2855 flag_value = (bfd_vma) 0x1003 << 32;
2860 md_number_to_chars (*mem, (((bfd_vma) 1 << 48) /* Version. */
2861 | flag_value /* U & E handler flags. */
2862 | ((size + extra) / md.pointer_size)), /* Length. */
2868 /* Generate an unwind image from a record list. Returns the number of
2869 bytes in the resulting image. The memory image itselof is returned
2870 in the 'ptr' parameter. */
2872 output_unw_records (list, ptr)
2881 list = optimize_unw_records (list);
2882 fixup_unw_records (list);
2883 size = calc_record_size (list);
2885 if (size > 0 || unwind.force_unwind_entry)
2887 unwind.force_unwind_entry = 0;
2888 extra = setup_unwind_header (size, &mem);
2890 vbyte_mem_ptr = mem + 8;
2891 process_unw_records (list, output_vbyte_mem);
2895 size += extra + 8 + md.pointer_size;
2901 convert_expr_to_ab_reg (e, ab, regp)
2908 if (e->X_op != O_register)
2911 reg = e->X_add_number;
2912 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7))
2915 *regp = reg - REG_GR;
2917 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5))
2918 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31)))
2921 *regp = reg - REG_FR;
2923 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5))
2926 *regp = reg - REG_BR;
2933 case REG_PR: *regp = 0; break;
2934 case REG_PSP: *regp = 1; break;
2935 case REG_PRIUNAT: *regp = 2; break;
2936 case REG_BR + 0: *regp = 3; break;
2937 case REG_AR + AR_BSP: *regp = 4; break;
2938 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2939 case REG_AR + AR_RNAT: *regp = 6; break;
2940 case REG_AR + AR_UNAT: *regp = 7; break;
2941 case REG_AR + AR_FPSR: *regp = 8; break;
2942 case REG_AR + AR_PFS: *regp = 9; break;
2943 case REG_AR + AR_LC: *regp = 10; break;
2953 convert_expr_to_xy_reg (e, xy, regp)
2960 if (e->X_op != O_register)
2963 reg = e->X_add_number;
2965 if (/* reg >= REG_GR && */ reg <= (REG_GR + 127))
2968 *regp = reg - REG_GR;
2970 else if (reg >= REG_FR && reg <= (REG_FR + 127))
2973 *regp = reg - REG_FR;
2975 else if (reg >= REG_BR && reg <= (REG_BR + 7))
2978 *regp = reg - REG_BR;
2987 int dummy ATTRIBUTE_UNUSED;
2992 radix = *input_line_pointer++;
2994 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2996 as_bad ("Radix `%c' unsupported", *input_line_pointer);
2997 ignore_rest_of_line ();
3002 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
3004 dot_special_section (which)
3007 set_section ((char *) special_section_name[which]);
3011 add_unwind_entry (ptr)
3015 unwind.tail->next = ptr;
3020 /* The current entry can in fact be a chain of unwind entries. */
3021 if (unwind.current_entry == NULL)
3022 unwind.current_entry = ptr;
3027 int dummy ATTRIBUTE_UNUSED;
3033 if (e.X_op != O_constant)
3034 as_bad ("Operand to .fframe must be a constant");
3036 add_unwind_entry (output_mem_stack_f (e.X_add_number));
3041 int dummy ATTRIBUTE_UNUSED;
3047 reg = e.X_add_number - REG_GR;
3048 if (e.X_op == O_register && reg < 128)
3050 add_unwind_entry (output_mem_stack_v ());
3051 if (! (unwind.prologue_mask & 2))
3052 add_unwind_entry (output_psp_gr (reg));
3055 as_bad ("First operand to .vframe must be a general register");
3059 dot_vframesp (dummy)
3060 int dummy ATTRIBUTE_UNUSED;
3065 if (e.X_op == O_constant)
3067 add_unwind_entry (output_mem_stack_v ());
3068 add_unwind_entry (output_psp_sprel (e.X_add_number));
3071 as_bad ("Operand to .vframesp must be a constant (sp-relative offset)");
3075 dot_vframepsp (dummy)
3076 int dummy ATTRIBUTE_UNUSED;
3081 if (e.X_op == O_constant)
3083 add_unwind_entry (output_mem_stack_v ());
3084 add_unwind_entry (output_psp_sprel (e.X_add_number));
3087 as_bad ("Operand to .vframepsp must be a constant (psp-relative offset)");
3092 int dummy ATTRIBUTE_UNUSED;
3098 sep = parse_operand (&e1);
3100 as_bad ("No second operand to .save");
3101 sep = parse_operand (&e2);
3103 reg1 = e1.X_add_number;
3104 reg2 = e2.X_add_number - REG_GR;
3106 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3107 if (e1.X_op == O_register)
3109 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
3113 case REG_AR + AR_BSP:
3114 add_unwind_entry (output_bsp_when ());
3115 add_unwind_entry (output_bsp_gr (reg2));
3117 case REG_AR + AR_BSPSTORE:
3118 add_unwind_entry (output_bspstore_when ());
3119 add_unwind_entry (output_bspstore_gr (reg2));
3121 case REG_AR + AR_RNAT:
3122 add_unwind_entry (output_rnat_when ());
3123 add_unwind_entry (output_rnat_gr (reg2));
3125 case REG_AR + AR_UNAT:
3126 add_unwind_entry (output_unat_when ());
3127 add_unwind_entry (output_unat_gr (reg2));
3129 case REG_AR + AR_FPSR:
3130 add_unwind_entry (output_fpsr_when ());
3131 add_unwind_entry (output_fpsr_gr (reg2));
3133 case REG_AR + AR_PFS:
3134 add_unwind_entry (output_pfs_when ());
3135 if (! (unwind.prologue_mask & 4))
3136 add_unwind_entry (output_pfs_gr (reg2));
3138 case REG_AR + AR_LC:
3139 add_unwind_entry (output_lc_when ());
3140 add_unwind_entry (output_lc_gr (reg2));
3143 add_unwind_entry (output_rp_when ());
3144 if (! (unwind.prologue_mask & 8))
3145 add_unwind_entry (output_rp_gr (reg2));
3148 add_unwind_entry (output_preds_when ());
3149 if (! (unwind.prologue_mask & 1))
3150 add_unwind_entry (output_preds_gr (reg2));
3153 add_unwind_entry (output_priunat_when_gr ());
3154 add_unwind_entry (output_priunat_gr (reg2));
3157 as_bad ("First operand not a valid register");
3161 as_bad (" Second operand not a valid register");
3164 as_bad ("First operand not a register");
3169 int dummy ATTRIBUTE_UNUSED;
3172 unsigned long ecount; /* # of _additional_ regions to pop */
3175 sep = parse_operand (&e1);
3176 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
3178 as_bad ("First operand to .restore must be stack pointer (sp)");
3184 parse_operand (&e2);
3185 if (e2.X_op != O_constant || e2.X_add_number < 0)
3187 as_bad ("Second operand to .restore must be a constant >= 0");
3190 ecount = e2.X_add_number;
3193 ecount = unwind.prologue_count - 1;
3195 if (ecount >= unwind.prologue_count)
3197 as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)",
3198 ecount + 1, unwind.prologue_count);
3202 add_unwind_entry (output_epilogue (ecount));
3204 if (ecount < unwind.prologue_count)
3205 unwind.prologue_count -= ecount + 1;
3207 unwind.prologue_count = 0;
3211 dot_restorereg (dummy)
3212 int dummy ATTRIBUTE_UNUSED;
3214 unsigned int ab, reg;
3219 if (!convert_expr_to_ab_reg (&e, &ab, ®))
3221 as_bad ("First operand to .restorereg must be a preserved register");
3224 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
3228 dot_restorereg_p (dummy)
3229 int dummy ATTRIBUTE_UNUSED;
3231 unsigned int qp, ab, reg;
3235 sep = parse_operand (&e1);
3238 as_bad ("No second operand to .restorereg.p");
3242 parse_operand (&e2);
3244 qp = e1.X_add_number - REG_P;
3245 if (e1.X_op != O_register || qp > 63)
3247 as_bad ("First operand to .restorereg.p must be a predicate");
3251 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3253 as_bad ("Second operand to .restorereg.p must be a preserved register");
3256 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
3260 generate_unwind_image (text_name)
3261 const char *text_name;
3266 /* Force out pending instructions, to make sure all unwind records have
3267 a valid slot_number field. */
3268 ia64_flush_insns ();
3270 /* Generate the unwind record. */
3271 size = output_unw_records (unwind.list, &unw_rec);
3272 if (size % md.pointer_size != 0)
3273 as_bad ("Unwind record is not a multiple of %d bytes.", md.pointer_size);
3275 /* If there are unwind records, switch sections, and output the info. */
3278 unsigned char *where;
3281 bfd_reloc_code_real_type reloc;
3283 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name);
3284 set_section (sec_name);
3285 bfd_set_section_flags (stdoutput, now_seg,
3286 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
3288 /* Make sure the section has 4 byte alignment for ILP32 and
3289 8 byte alignment for LP64. */
3290 frag_align (md.pointer_size_shift, 0, 0);
3291 record_alignment (now_seg, md.pointer_size_shift);
3293 /* Set expression which points to start of unwind descriptor area. */
3294 unwind.info = expr_build_dot ();
3296 where = (unsigned char *) frag_more (size);
3298 /* Issue a label for this address, and keep track of it to put it
3299 in the unwind section. */
3301 /* Copy the information from the unwind record into this section. The
3302 data is already in the correct byte order. */
3303 memcpy (where, unw_rec, size);
3305 /* Add the personality address to the image. */
3306 if (unwind.personality_routine != 0)
3308 exp.X_op = O_symbol;
3309 exp.X_add_symbol = unwind.personality_routine;
3310 exp.X_add_number = 0;
3312 if (md.flags & EF_IA_64_BE)
3314 if (md.flags & EF_IA_64_ABI64)
3315 reloc = BFD_RELOC_IA64_LTOFF_FPTR64MSB;
3317 reloc = BFD_RELOC_IA64_LTOFF_FPTR32MSB;
3321 if (md.flags & EF_IA_64_ABI64)
3322 reloc = BFD_RELOC_IA64_LTOFF_FPTR64LSB;
3324 reloc = BFD_RELOC_IA64_LTOFF_FPTR32LSB;
3327 fix_new_exp (frag_now, frag_now_fix () - md.pointer_size,
3328 md.pointer_size, &exp, 0, reloc);
3329 unwind.personality_routine = 0;
3333 free_list_records (unwind.list);
3334 free_saved_prologue_counts ();
3335 unwind.list = unwind.tail = unwind.current_entry = NULL;
3341 dot_handlerdata (dummy)
3342 int dummy ATTRIBUTE_UNUSED;
3344 const char *text_name = segment_name (now_seg);
3346 /* If text section name starts with ".text" (which it should),
3347 strip this prefix off. */
3348 if (strcmp (text_name, ".text") == 0)
3351 unwind.force_unwind_entry = 1;
3353 /* Remember which segment we're in so we can switch back after .endp */
3354 unwind.saved_text_seg = now_seg;
3355 unwind.saved_text_subseg = now_subseg;
3357 /* Generate unwind info into unwind-info section and then leave that
3358 section as the currently active one so dataXX directives go into
3359 the language specific data area of the unwind info block. */
3360 generate_unwind_image (text_name);
3361 demand_empty_rest_of_line ();
3365 dot_unwentry (dummy)
3366 int dummy ATTRIBUTE_UNUSED;
3368 unwind.force_unwind_entry = 1;
3369 demand_empty_rest_of_line ();
3374 int dummy ATTRIBUTE_UNUSED;
3380 reg = e.X_add_number - REG_BR;
3381 if (e.X_op == O_register && reg < 8)
3382 add_unwind_entry (output_rp_br (reg));
3384 as_bad ("First operand not a valid branch register");
3388 dot_savemem (psprel)
3395 sep = parse_operand (&e1);
3397 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
3398 sep = parse_operand (&e2);
3400 reg1 = e1.X_add_number;
3401 val = e2.X_add_number;
3403 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3404 if (e1.X_op == O_register)
3406 if (e2.X_op == O_constant)
3410 case REG_AR + AR_BSP:
3411 add_unwind_entry (output_bsp_when ());
3412 add_unwind_entry ((psprel
3414 : output_bsp_sprel) (val));
3416 case REG_AR + AR_BSPSTORE:
3417 add_unwind_entry (output_bspstore_when ());
3418 add_unwind_entry ((psprel
3419 ? output_bspstore_psprel
3420 : output_bspstore_sprel) (val));
3422 case REG_AR + AR_RNAT:
3423 add_unwind_entry (output_rnat_when ());
3424 add_unwind_entry ((psprel
3425 ? output_rnat_psprel
3426 : output_rnat_sprel) (val));
3428 case REG_AR + AR_UNAT:
3429 add_unwind_entry (output_unat_when ());
3430 add_unwind_entry ((psprel
3431 ? output_unat_psprel
3432 : output_unat_sprel) (val));
3434 case REG_AR + AR_FPSR:
3435 add_unwind_entry (output_fpsr_when ());
3436 add_unwind_entry ((psprel
3437 ? output_fpsr_psprel
3438 : output_fpsr_sprel) (val));
3440 case REG_AR + AR_PFS:
3441 add_unwind_entry (output_pfs_when ());
3442 add_unwind_entry ((psprel
3444 : output_pfs_sprel) (val));
3446 case REG_AR + AR_LC:
3447 add_unwind_entry (output_lc_when ());
3448 add_unwind_entry ((psprel
3450 : output_lc_sprel) (val));
3453 add_unwind_entry (output_rp_when ());
3454 add_unwind_entry ((psprel
3456 : output_rp_sprel) (val));
3459 add_unwind_entry (output_preds_when ());
3460 add_unwind_entry ((psprel
3461 ? output_preds_psprel
3462 : output_preds_sprel) (val));
3465 add_unwind_entry (output_priunat_when_mem ());
3466 add_unwind_entry ((psprel
3467 ? output_priunat_psprel
3468 : output_priunat_sprel) (val));
3471 as_bad ("First operand not a valid register");
3475 as_bad (" Second operand not a valid constant");
3478 as_bad ("First operand not a register");
3483 int dummy ATTRIBUTE_UNUSED;
3487 sep = parse_operand (&e1);
3489 parse_operand (&e2);
3491 if (e1.X_op != O_constant)
3492 as_bad ("First operand to .save.g must be a constant.");
3495 int grmask = e1.X_add_number;
3497 add_unwind_entry (output_gr_mem (grmask));
3500 int reg = e2.X_add_number - REG_GR;
3501 if (e2.X_op == O_register && reg >= 0 && reg < 128)
3502 add_unwind_entry (output_gr_gr (grmask, reg));
3504 as_bad ("Second operand is an invalid register.");
3511 int dummy ATTRIBUTE_UNUSED;
3515 sep = parse_operand (&e1);
3517 if (e1.X_op != O_constant)
3518 as_bad ("Operand to .save.f must be a constant.");
3520 add_unwind_entry (output_fr_mem (e1.X_add_number));
3525 int dummy ATTRIBUTE_UNUSED;
3532 sep = parse_operand (&e1);
3533 if (e1.X_op != O_constant)
3535 as_bad ("First operand to .save.b must be a constant.");
3538 brmask = e1.X_add_number;
3542 sep = parse_operand (&e2);
3543 reg = e2.X_add_number - REG_GR;
3544 if (e2.X_op != O_register || reg > 127)
3546 as_bad ("Second operand to .save.b must be a general register.");
3549 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3552 add_unwind_entry (output_br_mem (brmask));
3554 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3555 ignore_rest_of_line ();
3560 int dummy ATTRIBUTE_UNUSED;
3564 sep = parse_operand (&e1);
3566 parse_operand (&e2);
3568 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3569 as_bad ("Both operands of .save.gf must be constants.");
3572 int grmask = e1.X_add_number;
3573 int frmask = e2.X_add_number;
3574 add_unwind_entry (output_frgr_mem (grmask, frmask));
3580 int dummy ATTRIBUTE_UNUSED;
3585 sep = parse_operand (&e);
3586 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3587 ignore_rest_of_line ();
3589 if (e.X_op != O_constant)
3590 as_bad ("Operand to .spill must be a constant");
3592 add_unwind_entry (output_spill_base (e.X_add_number));
3596 dot_spillreg (dummy)
3597 int dummy ATTRIBUTE_UNUSED;
3599 int sep, ab, xy, reg, treg;
3602 sep = parse_operand (&e1);
3605 as_bad ("No second operand to .spillreg");
3609 parse_operand (&e2);
3611 if (!convert_expr_to_ab_reg (&e1, &ab, ®))
3613 as_bad ("First operand to .spillreg must be a preserved register");
3617 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3619 as_bad ("Second operand to .spillreg must be a register");
3623 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3627 dot_spillmem (psprel)
3633 sep = parse_operand (&e1);
3636 as_bad ("Second operand missing");
3640 parse_operand (&e2);
3642 if (!convert_expr_to_ab_reg (&e1, &ab, ®))
3644 as_bad ("First operand to .spill%s must be a preserved register",
3645 psprel ? "psp" : "sp");
3649 if (e2.X_op != O_constant)
3651 as_bad ("Second operand to .spill%s must be a constant",
3652 psprel ? "psp" : "sp");
3657 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3659 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3663 dot_spillreg_p (dummy)
3664 int dummy ATTRIBUTE_UNUSED;
3666 int sep, ab, xy, reg, treg;
3667 expressionS e1, e2, e3;
3670 sep = parse_operand (&e1);
3673 as_bad ("No second and third operand to .spillreg.p");
3677 sep = parse_operand (&e2);
3680 as_bad ("No third operand to .spillreg.p");
3684 parse_operand (&e3);
3686 qp = e1.X_add_number - REG_P;
3688 if (e1.X_op != O_register || qp > 63)
3690 as_bad ("First operand to .spillreg.p must be a predicate");
3694 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3696 as_bad ("Second operand to .spillreg.p must be a preserved register");
3700 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3702 as_bad ("Third operand to .spillreg.p must be a register");
3706 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3710 dot_spillmem_p (psprel)
3713 expressionS e1, e2, e3;
3717 sep = parse_operand (&e1);
3720 as_bad ("Second operand missing");
3724 parse_operand (&e2);
3727 as_bad ("Second operand missing");
3731 parse_operand (&e3);
3733 qp = e1.X_add_number - REG_P;
3734 if (e1.X_op != O_register || qp > 63)
3736 as_bad ("First operand to .spill%s_p must be a predicate",
3737 psprel ? "psp" : "sp");
3741 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3743 as_bad ("Second operand to .spill%s_p must be a preserved register",
3744 psprel ? "psp" : "sp");
3748 if (e3.X_op != O_constant)
3750 as_bad ("Third operand to .spill%s_p must be a constant",
3751 psprel ? "psp" : "sp");
3756 add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp));
3758 add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp));
3762 get_saved_prologue_count (lbl)
3765 label_prologue_count *lpc = unwind.saved_prologue_counts;
3767 while (lpc != NULL && lpc->label_number != lbl)
3771 return lpc->prologue_count;
3773 as_bad ("Missing .label_state %ld", lbl);
3778 save_prologue_count (lbl, count)
3782 label_prologue_count *lpc = unwind.saved_prologue_counts;
3784 while (lpc != NULL && lpc->label_number != lbl)
3788 lpc->prologue_count = count;
3791 label_prologue_count *new_lpc = xmalloc (sizeof (* new_lpc));
3793 new_lpc->next = unwind.saved_prologue_counts;
3794 new_lpc->label_number = lbl;
3795 new_lpc->prologue_count = count;
3796 unwind.saved_prologue_counts = new_lpc;
3801 free_saved_prologue_counts ()
3803 label_prologue_count *lpc = unwind.saved_prologue_counts;
3804 label_prologue_count *next;
3813 unwind.saved_prologue_counts = NULL;
3817 dot_label_state (dummy)
3818 int dummy ATTRIBUTE_UNUSED;
3823 if (e.X_op != O_constant)
3825 as_bad ("Operand to .label_state must be a constant");
3828 add_unwind_entry (output_label_state (e.X_add_number));
3829 save_prologue_count (e.X_add_number, unwind.prologue_count);
3833 dot_copy_state (dummy)
3834 int dummy ATTRIBUTE_UNUSED;
3839 if (e.X_op != O_constant)
3841 as_bad ("Operand to .copy_state must be a constant");
3844 add_unwind_entry (output_copy_state (e.X_add_number));
3845 unwind.prologue_count = get_saved_prologue_count (e.X_add_number);
3850 int dummy ATTRIBUTE_UNUSED;
3855 sep = parse_operand (&e1);
3858 as_bad ("Second operand to .unwabi missing");
3861 sep = parse_operand (&e2);
3862 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3863 ignore_rest_of_line ();
3865 if (e1.X_op != O_constant)
3867 as_bad ("First operand to .unwabi must be a constant");
3871 if (e2.X_op != O_constant)
3873 as_bad ("Second operand to .unwabi must be a constant");
3877 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
3881 dot_personality (dummy)
3882 int dummy ATTRIBUTE_UNUSED;
3886 name = input_line_pointer;
3887 c = get_symbol_end ();
3888 p = input_line_pointer;
3889 unwind.personality_routine = symbol_find_or_make (name);
3890 unwind.force_unwind_entry = 1;
3893 demand_empty_rest_of_line ();
3898 int dummy ATTRIBUTE_UNUSED;
3903 unwind.proc_start = expr_build_dot ();
3904 /* Parse names of main and alternate entry points and mark them as
3905 function symbols: */
3909 name = input_line_pointer;
3910 c = get_symbol_end ();
3911 p = input_line_pointer;
3912 sym = symbol_find_or_make (name);
3913 if (unwind.proc_start == 0)
3915 unwind.proc_start = sym;
3917 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3920 if (*input_line_pointer != ',')
3922 ++input_line_pointer;
3924 demand_empty_rest_of_line ();
3927 unwind.prologue_count = 0;
3928 unwind.list = unwind.tail = unwind.current_entry = NULL;
3929 unwind.personality_routine = 0;
3934 int dummy ATTRIBUTE_UNUSED;
3936 unwind.prologue = 0;
3937 unwind.prologue_mask = 0;
3939 add_unwind_entry (output_body ());
3940 demand_empty_rest_of_line ();
3944 dot_prologue (dummy)
3945 int dummy ATTRIBUTE_UNUSED;
3948 int mask = 0, grsave = 0;
3950 if (!is_it_end_of_statement ())
3953 sep = parse_operand (&e1);
3955 as_bad ("No second operand to .prologue");
3956 sep = parse_operand (&e2);
3957 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3958 ignore_rest_of_line ();
3960 if (e1.X_op == O_constant)
3962 mask = e1.X_add_number;
3964 if (e2.X_op == O_constant)
3965 grsave = e2.X_add_number;
3966 else if (e2.X_op == O_register
3967 && (grsave = e2.X_add_number - REG_GR) < 128)
3970 as_bad ("Second operand not a constant or general register");
3972 add_unwind_entry (output_prologue_gr (mask, grsave));
3975 as_bad ("First operand not a constant");
3978 add_unwind_entry (output_prologue ());
3980 unwind.prologue = 1;
3981 unwind.prologue_mask = mask;
3982 ++unwind.prologue_count;
3987 int dummy ATTRIBUTE_UNUSED;
3991 int bytes_per_address;
3994 subsegT saved_subseg;
3995 const char *sec_name, *text_name;
3999 if (unwind.saved_text_seg)
4001 saved_seg = unwind.saved_text_seg;
4002 saved_subseg = unwind.saved_text_subseg;
4003 unwind.saved_text_seg = NULL;
4007 saved_seg = now_seg;
4008 saved_subseg = now_subseg;
4012 Use a slightly ugly scheme to derive the unwind section names from
4013 the text section name:
4015 text sect. unwind table sect.
4016 name: name: comments:
4017 ---------- ----------------- --------------------------------
4019 .text.foo .IA_64.unwind.text.foo
4020 .foo .IA_64.unwind.foo
4022 .gnu.linkonce.ia64unw.foo
4023 _info .IA_64.unwind_info gas issues error message (ditto)
4024 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
4026 This mapping is done so that:
4028 (a) An object file with unwind info only in .text will use
4029 unwind section names .IA_64.unwind and .IA_64.unwind_info.
4030 This follows the letter of the ABI and also ensures backwards
4031 compatibility with older toolchains.
4033 (b) An object file with unwind info in multiple text sections
4034 will use separate unwind sections for each text section.
4035 This allows us to properly set the "sh_info" and "sh_link"
4036 fields in SHT_IA_64_UNWIND as required by the ABI and also
4037 lets GNU ld support programs with multiple segments
4038 containing unwind info (as might be the case for certain
4039 embedded applications).
4041 (c) An error is issued if there would be a name clash.
4043 text_name = segment_name (saved_seg);
4044 if (strncmp (text_name, "_info", 5) == 0)
4046 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
4048 ignore_rest_of_line ();
4051 if (strcmp (text_name, ".text") == 0)
4054 insn_group_break (1, 0, 0);
4056 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
4058 generate_unwind_image (text_name);
4060 if (unwind.info || unwind.force_unwind_entry)
4062 subseg_set (md.last_text_seg, 0);
4063 unwind.proc_end = expr_build_dot ();
4065 make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name);
4066 set_section ((char *) sec_name);
4067 bfd_set_section_flags (stdoutput, now_seg,
4068 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
4070 /* Make sure that section has 4 byte alignment for ILP32 and
4071 8 byte alignment for LP64. */
4072 record_alignment (now_seg, md.pointer_size_shift);
4074 /* Need space for 3 pointers for procedure start, procedure end,
4076 ptr = frag_more (3 * md.pointer_size);
4077 where = frag_now_fix () - (3 * md.pointer_size);
4078 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
4080 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
4081 e.X_op = O_pseudo_fixup;
4082 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
4084 e.X_add_symbol = unwind.proc_start;
4085 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
4087 e.X_op = O_pseudo_fixup;
4088 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
4090 e.X_add_symbol = unwind.proc_end;
4091 ia64_cons_fix_new (frag_now, where + bytes_per_address,
4092 bytes_per_address, &e);
4096 e.X_op = O_pseudo_fixup;
4097 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
4099 e.X_add_symbol = unwind.info;
4100 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2),
4101 bytes_per_address, &e);
4104 md_number_to_chars (ptr + (bytes_per_address * 2), 0,
4108 subseg_set (saved_seg, saved_subseg);
4110 /* Parse names of main and alternate entry points and set symbol sizes. */
4114 name = input_line_pointer;
4115 c = get_symbol_end ();
4116 p = input_line_pointer;
4117 sym = symbol_find (name);
4118 if (sym && unwind.proc_start
4119 && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION)
4120 && S_GET_SIZE (sym) == 0 && symbol_get_obj (sym)->size == NULL)
4122 fragS *fr = symbol_get_frag (unwind.proc_start);
4123 fragS *frag = symbol_get_frag (sym);
4125 /* Check whether the function label is at or beyond last
4127 while (fr && fr != frag)
4131 if (frag == frag_now && SEG_NORMAL (now_seg))
4132 S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym));
4135 symbol_get_obj (sym)->size =
4136 (expressionS *) xmalloc (sizeof (expressionS));
4137 symbol_get_obj (sym)->size->X_op = O_subtract;
4138 symbol_get_obj (sym)->size->X_add_symbol
4139 = symbol_new (FAKE_LABEL_NAME, now_seg,
4140 frag_now_fix (), frag_now);
4141 symbol_get_obj (sym)->size->X_op_symbol = sym;
4142 symbol_get_obj (sym)->size->X_add_number = 0;
4148 if (*input_line_pointer != ',')
4150 ++input_line_pointer;
4152 demand_empty_rest_of_line ();
4153 unwind.proc_start = unwind.proc_end = unwind.info = 0;
4157 dot_template (template)
4160 CURR_SLOT.user_template = template;
4165 int dummy ATTRIBUTE_UNUSED;
4167 int ins, locs, outs, rots;
4169 if (is_it_end_of_statement ())
4170 ins = locs = outs = rots = 0;
4173 ins = get_absolute_expression ();
4174 if (*input_line_pointer++ != ',')
4176 locs = get_absolute_expression ();
4177 if (*input_line_pointer++ != ',')
4179 outs = get_absolute_expression ();
4180 if (*input_line_pointer++ != ',')
4182 rots = get_absolute_expression ();
4184 set_regstack (ins, locs, outs, rots);
4188 as_bad ("Comma expected");
4189 ignore_rest_of_line ();
4196 unsigned num_regs, num_alloced = 0;
4197 struct dynreg **drpp, *dr;
4198 int ch, base_reg = 0;
4204 case DYNREG_GR: base_reg = REG_GR + 32; break;
4205 case DYNREG_FR: base_reg = REG_FR + 32; break;
4206 case DYNREG_PR: base_reg = REG_P + 16; break;
4210 /* First, remove existing names from hash table. */
4211 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
4213 hash_delete (md.dynreg_hash, dr->name);
4217 drpp = &md.dynreg[type];
4220 start = input_line_pointer;
4221 ch = get_symbol_end ();
4222 *input_line_pointer = ch;
4223 len = (input_line_pointer - start);
4226 if (*input_line_pointer != '[')
4228 as_bad ("Expected '['");
4231 ++input_line_pointer; /* skip '[' */
4233 num_regs = get_absolute_expression ();
4235 if (*input_line_pointer++ != ']')
4237 as_bad ("Expected ']'");
4242 num_alloced += num_regs;
4246 if (num_alloced > md.rot.num_regs)
4248 as_bad ("Used more than the declared %d rotating registers",
4254 if (num_alloced > 96)
4256 as_bad ("Used more than the available 96 rotating registers");
4261 if (num_alloced > 48)
4263 as_bad ("Used more than the available 48 rotating registers");
4272 name = obstack_alloc (¬es, len + 1);
4273 memcpy (name, start, len);
4278 *drpp = obstack_alloc (¬es, sizeof (*dr));
4279 memset (*drpp, 0, sizeof (*dr));
4284 dr->num_regs = num_regs;
4285 dr->base = base_reg;
4287 base_reg += num_regs;
4289 if (hash_insert (md.dynreg_hash, name, dr))
4291 as_bad ("Attempt to redefine register set `%s'", name);
4295 if (*input_line_pointer != ',')
4297 ++input_line_pointer; /* skip comma */
4300 demand_empty_rest_of_line ();
4304 ignore_rest_of_line ();
4308 dot_byteorder (byteorder)
4311 target_big_endian = byteorder;
4316 int dummy ATTRIBUTE_UNUSED;
4323 option = input_line_pointer;
4324 ch = get_symbol_end ();
4325 if (strcmp (option, "lsb") == 0)
4326 md.flags &= ~EF_IA_64_BE;
4327 else if (strcmp (option, "msb") == 0)
4328 md.flags |= EF_IA_64_BE;
4329 else if (strcmp (option, "abi32") == 0)
4330 md.flags &= ~EF_IA_64_ABI64;
4331 else if (strcmp (option, "abi64") == 0)
4332 md.flags |= EF_IA_64_ABI64;
4334 as_bad ("Unknown psr option `%s'", option);
4335 *input_line_pointer = ch;
4338 if (*input_line_pointer != ',')
4341 ++input_line_pointer;
4344 demand_empty_rest_of_line ();
4349 int dummy ATTRIBUTE_UNUSED;
4351 as_bad (".alias not implemented yet");
4356 int dummy ATTRIBUTE_UNUSED;
4358 new_logical_line (0, get_absolute_expression ());
4359 demand_empty_rest_of_line ();
4363 parse_section_name ()
4369 if (*input_line_pointer != '"')
4371 as_bad ("Missing section name");
4372 ignore_rest_of_line ();
4375 name = demand_copy_C_string (&len);
4378 ignore_rest_of_line ();
4382 if (*input_line_pointer != ',')
4384 as_bad ("Comma expected after section name");
4385 ignore_rest_of_line ();
4388 ++input_line_pointer; /* skip comma */
4396 char *name = parse_section_name ();
4400 md.keep_pending_output = 1;
4403 obj_elf_previous (0);
4404 md.keep_pending_output = 0;
4407 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4410 stmt_float_cons (kind)
4431 ia64_do_align (alignment);
4439 int saved_auto_align = md.auto_align;
4443 md.auto_align = saved_auto_align;
4447 dot_xfloat_cons (kind)
4450 char *name = parse_section_name ();
4454 md.keep_pending_output = 1;
4456 stmt_float_cons (kind);
4457 obj_elf_previous (0);
4458 md.keep_pending_output = 0;
4462 dot_xstringer (zero)
4465 char *name = parse_section_name ();
4469 md.keep_pending_output = 1;
4472 obj_elf_previous (0);
4473 md.keep_pending_output = 0;
4480 int saved_auto_align = md.auto_align;
4481 char *name = parse_section_name ();
4485 md.keep_pending_output = 1;
4489 md.auto_align = saved_auto_align;
4490 obj_elf_previous (0);
4491 md.keep_pending_output = 0;
4495 dot_xfloat_cons_ua (kind)
4498 int saved_auto_align = md.auto_align;
4499 char *name = parse_section_name ();
4503 md.keep_pending_output = 1;
4506 stmt_float_cons (kind);
4507 md.auto_align = saved_auto_align;
4508 obj_elf_previous (0);
4509 md.keep_pending_output = 0;
4512 /* .reg.val <regname>,value */
4516 int dummy ATTRIBUTE_UNUSED;
4521 if (reg.X_op != O_register)
4523 as_bad (_("Register name expected"));
4524 ignore_rest_of_line ();
4526 else if (*input_line_pointer++ != ',')
4528 as_bad (_("Comma expected"));
4529 ignore_rest_of_line ();
4533 valueT value = get_absolute_expression ();
4534 int regno = reg.X_add_number;
4535 if (regno < REG_GR || regno > REG_GR + 128)
4536 as_warn (_("Register value annotation ignored"));
4539 gr_values[regno - REG_GR].known = 1;
4540 gr_values[regno - REG_GR].value = value;
4541 gr_values[regno - REG_GR].path = md.path;
4544 demand_empty_rest_of_line ();
4547 /* select dv checking mode
4552 A stop is inserted when changing modes
4559 if (md.manual_bundling)
4560 as_warn (_("Directive invalid within a bundle"));
4562 if (type == 'E' || type == 'A')
4563 md.mode_explicitly_set = 0;
4565 md.mode_explicitly_set = 1;
4572 if (md.explicit_mode)
4573 insn_group_break (1, 0, 0);
4574 md.explicit_mode = 0;
4578 if (!md.explicit_mode)
4579 insn_group_break (1, 0, 0);
4580 md.explicit_mode = 1;
4584 if (md.explicit_mode != md.default_explicit_mode)
4585 insn_group_break (1, 0, 0);
4586 md.explicit_mode = md.default_explicit_mode;
4587 md.mode_explicitly_set = 0;
4598 for (regno = 0; regno < 64; regno++)
4600 if (mask & ((valueT) 1 << regno))
4602 fprintf (stderr, "%s p%d", comma, regno);
4609 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4610 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4611 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4612 .pred.safe_across_calls p1 [, p2 [,...]]
4621 int p1 = -1, p2 = -1;
4625 if (*input_line_pointer != '"')
4627 as_bad (_("Missing predicate relation type"));
4628 ignore_rest_of_line ();
4634 char *form = demand_copy_C_string (&len);
4635 if (strcmp (form, "mutex") == 0)
4637 else if (strcmp (form, "clear") == 0)
4639 else if (strcmp (form, "imply") == 0)
4643 as_bad (_("Unrecognized predicate relation type"));
4644 ignore_rest_of_line ();
4648 if (*input_line_pointer == ',')
4649 ++input_line_pointer;
4659 if (TOUPPER (*input_line_pointer) != 'P'
4660 || (regno = atoi (++input_line_pointer)) < 0
4663 as_bad (_("Predicate register expected"));
4664 ignore_rest_of_line ();
4667 while (ISDIGIT (*input_line_pointer))
4668 ++input_line_pointer;
4675 as_warn (_("Duplicate predicate register ignored"));
4678 /* See if it's a range. */
4679 if (*input_line_pointer == '-')
4682 ++input_line_pointer;
4684 if (TOUPPER (*input_line_pointer) != 'P'
4685 || (regno = atoi (++input_line_pointer)) < 0
4688 as_bad (_("Predicate register expected"));
4689 ignore_rest_of_line ();
4692 while (ISDIGIT (*input_line_pointer))
4693 ++input_line_pointer;
4697 as_bad (_("Bad register range"));
4698 ignore_rest_of_line ();
4709 if (*input_line_pointer != ',')
4711 ++input_line_pointer;
4720 clear_qp_mutex (mask);
4721 clear_qp_implies (mask, (valueT) 0);
4724 if (count != 2 || p1 == -1 || p2 == -1)
4725 as_bad (_("Predicate source and target required"));
4726 else if (p1 == 0 || p2 == 0)
4727 as_bad (_("Use of p0 is not valid in this context"));
4729 add_qp_imply (p1, p2);
4734 as_bad (_("At least two PR arguments expected"));
4739 as_bad (_("Use of p0 is not valid in this context"));
4742 add_qp_mutex (mask);
4745 /* note that we don't override any existing relations */
4748 as_bad (_("At least one PR argument expected"));
4753 fprintf (stderr, "Safe across calls: ");
4754 print_prmask (mask);
4755 fprintf (stderr, "\n");
4757 qp_safe_across_calls = mask;
4760 demand_empty_rest_of_line ();
4763 /* .entry label [, label [, ...]]
4764 Hint to DV code that the given labels are to be considered entry points.
4765 Otherwise, only global labels are considered entry points. */
4769 int dummy ATTRIBUTE_UNUSED;
4778 name = input_line_pointer;
4779 c = get_symbol_end ();
4780 symbolP = symbol_find_or_make (name);
4782 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4784 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4787 *input_line_pointer = c;
4789 c = *input_line_pointer;
4792 input_line_pointer++;
4794 if (*input_line_pointer == '\n')
4800 demand_empty_rest_of_line ();
4803 /* .mem.offset offset, base
4804 "base" is used to distinguish between offsets from a different base. */
4807 dot_mem_offset (dummy)
4808 int dummy ATTRIBUTE_UNUSED;
4810 md.mem_offset.hint = 1;
4811 md.mem_offset.offset = get_absolute_expression ();
4812 if (*input_line_pointer != ',')
4814 as_bad (_("Comma expected"));
4815 ignore_rest_of_line ();
4818 ++input_line_pointer;
4819 md.mem_offset.base = get_absolute_expression ();
4820 demand_empty_rest_of_line ();
4823 /* ia64-specific pseudo-ops: */
4824 const pseudo_typeS md_pseudo_table[] =
4826 { "radix", dot_radix, 0 },
4827 { "lcomm", s_lcomm_bytes, 1 },
4828 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4829 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4830 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4831 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4832 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4833 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4834 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4835 { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY },
4836 { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY },
4837 { "proc", dot_proc, 0 },
4838 { "body", dot_body, 0 },
4839 { "prologue", dot_prologue, 0 },
4840 { "endp", dot_endp, 0 },
4841 { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 },
4842 { "loc", dwarf2_directive_loc, 0 },
4844 { "fframe", dot_fframe, 0 },
4845 { "vframe", dot_vframe, 0 },
4846 { "vframesp", dot_vframesp, 0 },
4847 { "vframepsp", dot_vframepsp, 0 },
4848 { "save", dot_save, 0 },
4849 { "restore", dot_restore, 0 },
4850 { "restorereg", dot_restorereg, 0 },
4851 { "restorereg.p", dot_restorereg_p, 0 },
4852 { "handlerdata", dot_handlerdata, 0 },
4853 { "unwentry", dot_unwentry, 0 },
4854 { "altrp", dot_altrp, 0 },
4855 { "savesp", dot_savemem, 0 },
4856 { "savepsp", dot_savemem, 1 },
4857 { "save.g", dot_saveg, 0 },
4858 { "save.f", dot_savef, 0 },
4859 { "save.b", dot_saveb, 0 },
4860 { "save.gf", dot_savegf, 0 },
4861 { "spill", dot_spill, 0 },
4862 { "spillreg", dot_spillreg, 0 },
4863 { "spillsp", dot_spillmem, 0 },
4864 { "spillpsp", dot_spillmem, 1 },
4865 { "spillreg.p", dot_spillreg_p, 0 },
4866 { "spillsp.p", dot_spillmem_p, 0 },
4867 { "spillpsp.p", dot_spillmem_p, 1 },
4868 { "label_state", dot_label_state, 0 },
4869 { "copy_state", dot_copy_state, 0 },
4870 { "unwabi", dot_unwabi, 0 },
4871 { "personality", dot_personality, 0 },
4873 { "estate", dot_estate, 0 },
4875 { "mii", dot_template, 0x0 },
4876 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4877 { "mlx", dot_template, 0x2 },
4878 { "mmi", dot_template, 0x4 },
4879 { "mfi", dot_template, 0x6 },
4880 { "mmf", dot_template, 0x7 },
4881 { "mib", dot_template, 0x8 },
4882 { "mbb", dot_template, 0x9 },
4883 { "bbb", dot_template, 0xb },
4884 { "mmb", dot_template, 0xc },
4885 { "mfb", dot_template, 0xe },
4887 { "lb", dot_scope, 0 },
4888 { "le", dot_scope, 1 },
4890 { "align", s_align_bytes, 0 },
4891 { "regstk", dot_regstk, 0 },
4892 { "rotr", dot_rot, DYNREG_GR },
4893 { "rotf", dot_rot, DYNREG_FR },
4894 { "rotp", dot_rot, DYNREG_PR },
4895 { "lsb", dot_byteorder, 0 },
4896 { "msb", dot_byteorder, 1 },
4897 { "psr", dot_psr, 0 },
4898 { "alias", dot_alias, 0 },
4899 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4901 { "xdata1", dot_xdata, 1 },
4902 { "xdata2", dot_xdata, 2 },
4903 { "xdata4", dot_xdata, 4 },
4904 { "xdata8", dot_xdata, 8 },
4905 { "xreal4", dot_xfloat_cons, 'f' },
4906 { "xreal8", dot_xfloat_cons, 'd' },
4907 { "xreal10", dot_xfloat_cons, 'x' },
4908 { "xreal16", dot_xfloat_cons, 'X' },
4909 { "xstring", dot_xstringer, 0 },
4910 { "xstringz", dot_xstringer, 1 },
4912 /* unaligned versions: */
4913 { "xdata2.ua", dot_xdata_ua, 2 },
4914 { "xdata4.ua", dot_xdata_ua, 4 },
4915 { "xdata8.ua", dot_xdata_ua, 8 },
4916 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4917 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4918 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4919 { "xreal16.ua", dot_xfloat_cons_ua, 'X' },
4921 /* annotations/DV checking support */
4922 { "entry", dot_entry, 0 },
4923 { "mem.offset", dot_mem_offset, 0 },
4924 { "pred.rel", dot_pred_rel, 0 },
4925 { "pred.rel.clear", dot_pred_rel, 'c' },
4926 { "pred.rel.imply", dot_pred_rel, 'i' },
4927 { "pred.rel.mutex", dot_pred_rel, 'm' },
4928 { "pred.safe_across_calls", dot_pred_rel, 's' },
4929 { "reg.val", dot_reg_val, 0 },
4930 { "auto", dot_dv_mode, 'a' },
4931 { "explicit", dot_dv_mode, 'e' },
4932 { "default", dot_dv_mode, 'd' },
4934 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4935 IA-64 aligns data allocation pseudo-ops by default, so we have to
4936 tell it that these ones are supposed to be unaligned. Long term,
4937 should rewrite so that only IA-64 specific data allocation pseudo-ops
4938 are aligned by default. */
4939 {"2byte", stmt_cons_ua, 2},
4940 {"4byte", stmt_cons_ua, 4},
4941 {"8byte", stmt_cons_ua, 8},
4946 static const struct pseudo_opcode
4949 void (*handler) (int);
4954 /* these are more like pseudo-ops, but don't start with a dot */
4955 { "data1", cons, 1 },
4956 { "data2", cons, 2 },
4957 { "data4", cons, 4 },
4958 { "data8", cons, 8 },
4959 { "data16", cons, 16 },
4960 { "real4", stmt_float_cons, 'f' },
4961 { "real8", stmt_float_cons, 'd' },
4962 { "real10", stmt_float_cons, 'x' },
4963 { "real16", stmt_float_cons, 'X' },
4964 { "string", stringer, 0 },
4965 { "stringz", stringer, 1 },
4967 /* unaligned versions: */
4968 { "data2.ua", stmt_cons_ua, 2 },
4969 { "data4.ua", stmt_cons_ua, 4 },
4970 { "data8.ua", stmt_cons_ua, 8 },
4971 { "data16.ua", stmt_cons_ua, 16 },
4972 { "real4.ua", float_cons, 'f' },
4973 { "real8.ua", float_cons, 'd' },
4974 { "real10.ua", float_cons, 'x' },
4975 { "real16.ua", float_cons, 'X' },
4978 /* Declare a register by creating a symbol for it and entering it in
4979 the symbol table. */
4982 declare_register (name, regnum)
4989 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4991 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4993 as_fatal ("Inserting \"%s\" into register table failed: %s",
5000 declare_register_set (prefix, num_regs, base_regnum)
5008 for (i = 0; i < num_regs; ++i)
5010 sprintf (name, "%s%u", prefix, i);
5011 declare_register (name, base_regnum + i);
5016 operand_width (opnd)
5017 enum ia64_opnd opnd;
5019 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
5020 unsigned int bits = 0;
5024 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
5025 bits += odesc->field[i].bits;
5030 static enum operand_match_result
5031 operand_match (idesc, index, e)
5032 const struct ia64_opcode *idesc;
5036 enum ia64_opnd opnd = idesc->operands[index];
5037 int bits, relocatable = 0;
5038 struct insn_fix *fix;
5045 case IA64_OPND_AR_CCV:
5046 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
5047 return OPERAND_MATCH;
5050 case IA64_OPND_AR_CSD:
5051 if (e->X_op == O_register && e->X_add_number == REG_AR + 25)
5052 return OPERAND_MATCH;
5055 case IA64_OPND_AR_PFS:
5056 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
5057 return OPERAND_MATCH;
5061 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
5062 return OPERAND_MATCH;
5066 if (e->X_op == O_register && e->X_add_number == REG_IP)
5067 return OPERAND_MATCH;
5071 if (e->X_op == O_register && e->X_add_number == REG_PR)
5072 return OPERAND_MATCH;
5075 case IA64_OPND_PR_ROT:
5076 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
5077 return OPERAND_MATCH;
5081 if (e->X_op == O_register && e->X_add_number == REG_PSR)
5082 return OPERAND_MATCH;
5085 case IA64_OPND_PSR_L:
5086 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
5087 return OPERAND_MATCH;
5090 case IA64_OPND_PSR_UM:
5091 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
5092 return OPERAND_MATCH;
5096 if (e->X_op == O_constant)
5098 if (e->X_add_number == 1)
5099 return OPERAND_MATCH;
5101 return OPERAND_OUT_OF_RANGE;
5106 if (e->X_op == O_constant)
5108 if (e->X_add_number == 8)
5109 return OPERAND_MATCH;
5111 return OPERAND_OUT_OF_RANGE;
5116 if (e->X_op == O_constant)
5118 if (e->X_add_number == 16)
5119 return OPERAND_MATCH;
5121 return OPERAND_OUT_OF_RANGE;
5125 /* register operands: */
5128 if (e->X_op == O_register && e->X_add_number >= REG_AR
5129 && e->X_add_number < REG_AR + 128)
5130 return OPERAND_MATCH;
5135 if (e->X_op == O_register && e->X_add_number >= REG_BR
5136 && e->X_add_number < REG_BR + 8)
5137 return OPERAND_MATCH;
5141 if (e->X_op == O_register && e->X_add_number >= REG_CR
5142 && e->X_add_number < REG_CR + 128)
5143 return OPERAND_MATCH;
5150 if (e->X_op == O_register && e->X_add_number >= REG_FR
5151 && e->X_add_number < REG_FR + 128)
5152 return OPERAND_MATCH;
5157 if (e->X_op == O_register && e->X_add_number >= REG_P
5158 && e->X_add_number < REG_P + 64)
5159 return OPERAND_MATCH;
5165 if (e->X_op == O_register && e->X_add_number >= REG_GR
5166 && e->X_add_number < REG_GR + 128)
5167 return OPERAND_MATCH;
5170 case IA64_OPND_R3_2:
5171 if (e->X_op == O_register && e->X_add_number >= REG_GR)
5173 if (e->X_add_number < REG_GR + 4)
5174 return OPERAND_MATCH;
5175 else if (e->X_add_number < REG_GR + 128)
5176 return OPERAND_OUT_OF_RANGE;
5180 /* indirect operands: */
5181 case IA64_OPND_CPUID_R3:
5182 case IA64_OPND_DBR_R3:
5183 case IA64_OPND_DTR_R3:
5184 case IA64_OPND_ITR_R3:
5185 case IA64_OPND_IBR_R3:
5186 case IA64_OPND_MSR_R3:
5187 case IA64_OPND_PKR_R3:
5188 case IA64_OPND_PMC_R3:
5189 case IA64_OPND_PMD_R3:
5190 case IA64_OPND_RR_R3:
5191 if (e->X_op == O_index && e->X_op_symbol
5192 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
5193 == opnd - IA64_OPND_CPUID_R3))
5194 return OPERAND_MATCH;
5198 if (e->X_op == O_index && !e->X_op_symbol)
5199 return OPERAND_MATCH;
5202 /* immediate operands: */
5203 case IA64_OPND_CNT2a:
5204 case IA64_OPND_LEN4:
5205 case IA64_OPND_LEN6:
5206 bits = operand_width (idesc->operands[index]);
5207 if (e->X_op == O_constant)
5209 if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
5210 return OPERAND_MATCH;
5212 return OPERAND_OUT_OF_RANGE;
5216 case IA64_OPND_CNT2b:
5217 if (e->X_op == O_constant)
5219 if ((bfd_vma) (e->X_add_number - 1) < 3)
5220 return OPERAND_MATCH;
5222 return OPERAND_OUT_OF_RANGE;
5226 case IA64_OPND_CNT2c:
5227 val = e->X_add_number;
5228 if (e->X_op == O_constant)
5230 if ((val == 0 || val == 7 || val == 15 || val == 16))
5231 return OPERAND_MATCH;
5233 return OPERAND_OUT_OF_RANGE;
5238 /* SOR must be an integer multiple of 8 */
5239 if (e->X_op == O_constant && e->X_add_number & 0x7)
5240 return OPERAND_OUT_OF_RANGE;
5243 if (e->X_op == O_constant)
5245 if ((bfd_vma) e->X_add_number <= 96)
5246 return OPERAND_MATCH;
5248 return OPERAND_OUT_OF_RANGE;
5252 case IA64_OPND_IMMU62:
5253 if (e->X_op == O_constant)
5255 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
5256 return OPERAND_MATCH;
5258 return OPERAND_OUT_OF_RANGE;
5262 /* FIXME -- need 62-bit relocation type */
5263 as_bad (_("62-bit relocation not yet implemented"));
5267 case IA64_OPND_IMMU64:
5268 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
5269 || e->X_op == O_subtract)
5271 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5272 fix->code = BFD_RELOC_IA64_IMM64;
5273 if (e->X_op != O_subtract)
5275 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5276 if (e->X_op == O_pseudo_fixup)
5280 fix->opnd = idesc->operands[index];
5283 ++CURR_SLOT.num_fixups;
5284 return OPERAND_MATCH;
5286 else if (e->X_op == O_constant)
5287 return OPERAND_MATCH;
5290 case IA64_OPND_CCNT5:
5291 case IA64_OPND_CNT5:
5292 case IA64_OPND_CNT6:
5293 case IA64_OPND_CPOS6a:
5294 case IA64_OPND_CPOS6b:
5295 case IA64_OPND_CPOS6c:
5296 case IA64_OPND_IMMU2:
5297 case IA64_OPND_IMMU7a:
5298 case IA64_OPND_IMMU7b:
5299 case IA64_OPND_IMMU21:
5300 case IA64_OPND_IMMU24:
5301 case IA64_OPND_MBTYPE4:
5302 case IA64_OPND_MHTYPE8:
5303 case IA64_OPND_POS6:
5304 bits = operand_width (idesc->operands[index]);
5305 if (e->X_op == O_constant)
5307 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5308 return OPERAND_MATCH;
5310 return OPERAND_OUT_OF_RANGE;
5314 case IA64_OPND_IMMU9:
5315 bits = operand_width (idesc->operands[index]);
5316 if (e->X_op == O_constant)
5318 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5320 int lobits = e->X_add_number & 0x3;
5321 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
5322 e->X_add_number |= (bfd_vma) 0x3;
5323 return OPERAND_MATCH;
5326 return OPERAND_OUT_OF_RANGE;
5330 case IA64_OPND_IMM44:
5331 /* least 16 bits must be zero */
5332 if ((e->X_add_number & 0xffff) != 0)
5333 /* XXX technically, this is wrong: we should not be issuing warning
5334 messages until we're sure this instruction pattern is going to
5336 as_warn (_("lower 16 bits of mask ignored"));
5338 if (e->X_op == O_constant)
5340 if (((e->X_add_number >= 0
5341 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44))
5342 || (e->X_add_number < 0
5343 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44))))
5346 if (e->X_add_number >= 0
5347 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
5349 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
5351 return OPERAND_MATCH;
5354 return OPERAND_OUT_OF_RANGE;
5358 case IA64_OPND_IMM17:
5359 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5360 if (e->X_op == O_constant)
5362 if (((e->X_add_number >= 0
5363 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17))
5364 || (e->X_add_number < 0
5365 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17))))
5368 if (e->X_add_number >= 0
5369 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
5371 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
5373 return OPERAND_MATCH;
5376 return OPERAND_OUT_OF_RANGE;
5380 case IA64_OPND_IMM14:
5381 case IA64_OPND_IMM22:
5383 case IA64_OPND_IMM1:
5384 case IA64_OPND_IMM8:
5385 case IA64_OPND_IMM8U4:
5386 case IA64_OPND_IMM8M1:
5387 case IA64_OPND_IMM8M1U4:
5388 case IA64_OPND_IMM8M1U8:
5389 case IA64_OPND_IMM9a:
5390 case IA64_OPND_IMM9b:
5391 bits = operand_width (idesc->operands[index]);
5392 if (relocatable && (e->X_op == O_symbol
5393 || e->X_op == O_subtract
5394 || e->X_op == O_pseudo_fixup))
5396 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5398 if (idesc->operands[index] == IA64_OPND_IMM14)
5399 fix->code = BFD_RELOC_IA64_IMM14;
5401 fix->code = BFD_RELOC_IA64_IMM22;
5403 if (e->X_op != O_subtract)
5405 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5406 if (e->X_op == O_pseudo_fixup)
5410 fix->opnd = idesc->operands[index];
5413 ++CURR_SLOT.num_fixups;
5414 return OPERAND_MATCH;
5416 else if (e->X_op != O_constant
5417 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
5418 return OPERAND_MISMATCH;
5420 if (opnd == IA64_OPND_IMM8M1U4)
5422 /* Zero is not valid for unsigned compares that take an adjusted
5423 constant immediate range. */
5424 if (e->X_add_number == 0)
5425 return OPERAND_OUT_OF_RANGE;
5427 /* Sign-extend 32-bit unsigned numbers, so that the following range
5428 checks will work. */
5429 val = e->X_add_number;
5430 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5431 && ((val & ((bfd_vma) 1 << 31)) != 0))
5432 val = ((val << 32) >> 32);
5434 /* Check for 0x100000000. This is valid because
5435 0x100000000-1 is the same as ((uint32_t) -1). */
5436 if (val == ((bfd_signed_vma) 1 << 32))
5437 return OPERAND_MATCH;
5441 else if (opnd == IA64_OPND_IMM8M1U8)
5443 /* Zero is not valid for unsigned compares that take an adjusted
5444 constant immediate range. */
5445 if (e->X_add_number == 0)
5446 return OPERAND_OUT_OF_RANGE;
5448 /* Check for 0x10000000000000000. */
5449 if (e->X_op == O_big)
5451 if (generic_bignum[0] == 0
5452 && generic_bignum[1] == 0
5453 && generic_bignum[2] == 0
5454 && generic_bignum[3] == 0
5455 && generic_bignum[4] == 1)
5456 return OPERAND_MATCH;
5458 return OPERAND_OUT_OF_RANGE;
5461 val = e->X_add_number - 1;
5463 else if (opnd == IA64_OPND_IMM8M1)
5464 val = e->X_add_number - 1;
5465 else if (opnd == IA64_OPND_IMM8U4)
5467 /* Sign-extend 32-bit unsigned numbers, so that the following range
5468 checks will work. */
5469 val = e->X_add_number;
5470 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5471 && ((val & ((bfd_vma) 1 << 31)) != 0))
5472 val = ((val << 32) >> 32);
5475 val = e->X_add_number;
5477 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1)))
5478 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1))))
5479 return OPERAND_MATCH;
5481 return OPERAND_OUT_OF_RANGE;
5483 case IA64_OPND_INC3:
5484 /* +/- 1, 4, 8, 16 */
5485 val = e->X_add_number;
5488 if (e->X_op == O_constant)
5490 if ((val == 1 || val == 4 || val == 8 || val == 16))
5491 return OPERAND_MATCH;
5493 return OPERAND_OUT_OF_RANGE;
5497 case IA64_OPND_TGT25:
5498 case IA64_OPND_TGT25b:
5499 case IA64_OPND_TGT25c:
5500 case IA64_OPND_TGT64:
5501 if (e->X_op == O_symbol)
5503 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5504 if (opnd == IA64_OPND_TGT25)
5505 fix->code = BFD_RELOC_IA64_PCREL21F;
5506 else if (opnd == IA64_OPND_TGT25b)
5507 fix->code = BFD_RELOC_IA64_PCREL21M;
5508 else if (opnd == IA64_OPND_TGT25c)
5509 fix->code = BFD_RELOC_IA64_PCREL21B;
5510 else if (opnd == IA64_OPND_TGT64)
5511 fix->code = BFD_RELOC_IA64_PCREL60B;
5515 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5516 fix->opnd = idesc->operands[index];
5519 ++CURR_SLOT.num_fixups;
5520 return OPERAND_MATCH;
5522 case IA64_OPND_TAG13:
5523 case IA64_OPND_TAG13b:
5527 return OPERAND_MATCH;
5530 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5531 /* There are no external relocs for TAG13/TAG13b fields, so we
5532 create a dummy reloc. This will not live past md_apply_fix3. */
5533 fix->code = BFD_RELOC_UNUSED;
5534 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5535 fix->opnd = idesc->operands[index];
5538 ++CURR_SLOT.num_fixups;
5539 return OPERAND_MATCH;
5546 case IA64_OPND_LDXMOV:
5547 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5548 fix->code = BFD_RELOC_IA64_LDXMOV;
5549 fix->opnd = idesc->operands[index];
5552 ++CURR_SLOT.num_fixups;
5553 return OPERAND_MATCH;
5558 return OPERAND_MISMATCH;
5567 memset (e, 0, sizeof (*e));
5570 if (*input_line_pointer != '}')
5572 sep = *input_line_pointer++;
5576 if (!md.manual_bundling)
5577 as_warn ("Found '}' when manual bundling is off");
5579 CURR_SLOT.manual_bundling_off = 1;
5580 md.manual_bundling = 0;
5586 /* Returns the next entry in the opcode table that matches the one in
5587 IDESC, and frees the entry in IDESC. If no matching entry is
5588 found, NULL is returned instead. */
5590 static struct ia64_opcode *
5591 get_next_opcode (struct ia64_opcode *idesc)
5593 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
5594 ia64_free_opcode (idesc);
5598 /* Parse the operands for the opcode and find the opcode variant that
5599 matches the specified operands, or NULL if no match is possible. */
5601 static struct ia64_opcode *
5602 parse_operands (idesc)
5603 struct ia64_opcode *idesc;
5605 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
5606 int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0;
5607 enum ia64_opnd expected_operand = IA64_OPND_NIL;
5608 enum operand_match_result result;
5610 char *first_arg = 0, *end, *saved_input_pointer;
5613 assert (strlen (idesc->name) <= 128);
5615 strcpy (mnemonic, idesc->name);
5616 if (idesc->operands[2] == IA64_OPND_SOF)
5618 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5619 can't parse the first operand until we have parsed the
5620 remaining operands of the "alloc" instruction. */
5622 first_arg = input_line_pointer;
5623 end = strchr (input_line_pointer, '=');
5626 as_bad ("Expected separator `='");
5629 input_line_pointer = end + 1;
5634 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
5636 sep = parse_operand (CURR_SLOT.opnd + i);
5637 if (CURR_SLOT.opnd[i].X_op == O_absent)
5642 if (sep != '=' && sep != ',')
5647 if (num_outputs > 0)
5648 as_bad ("Duplicate equal sign (=) in instruction");
5650 num_outputs = i + 1;
5655 as_bad ("Illegal operand separator `%c'", sep);
5659 if (idesc->operands[2] == IA64_OPND_SOF)
5661 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5662 know (strcmp (idesc->name, "alloc") == 0);
5663 if (num_operands == 5 /* first_arg not included in this count! */
5664 && CURR_SLOT.opnd[2].X_op == O_constant
5665 && CURR_SLOT.opnd[3].X_op == O_constant
5666 && CURR_SLOT.opnd[4].X_op == O_constant
5667 && CURR_SLOT.opnd[5].X_op == O_constant)
5669 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5670 CURR_SLOT.opnd[3].X_add_number,
5671 CURR_SLOT.opnd[4].X_add_number,
5672 CURR_SLOT.opnd[5].X_add_number);
5674 /* now we can parse the first arg: */
5675 saved_input_pointer = input_line_pointer;
5676 input_line_pointer = first_arg;
5677 sep = parse_operand (CURR_SLOT.opnd + 0);
5679 --num_outputs; /* force error */
5680 input_line_pointer = saved_input_pointer;
5682 CURR_SLOT.opnd[2].X_add_number = sof;
5683 CURR_SLOT.opnd[3].X_add_number
5684 = sof - CURR_SLOT.opnd[4].X_add_number;
5685 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5689 highest_unmatched_operand = 0;
5690 curr_out_of_range_pos = -1;
5692 expected_operand = idesc->operands[0];
5693 for (; idesc; idesc = get_next_opcode (idesc))
5695 if (num_outputs != idesc->num_outputs)
5696 continue; /* mismatch in # of outputs */
5698 CURR_SLOT.num_fixups = 0;
5700 /* Try to match all operands. If we see an out-of-range operand,
5701 then continue trying to match the rest of the operands, since if
5702 the rest match, then this idesc will give the best error message. */
5704 out_of_range_pos = -1;
5705 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5707 result = operand_match (idesc, i, CURR_SLOT.opnd + i);
5708 if (result != OPERAND_MATCH)
5710 if (result != OPERAND_OUT_OF_RANGE)
5712 if (out_of_range_pos < 0)
5713 /* remember position of the first out-of-range operand: */
5714 out_of_range_pos = i;
5718 /* If we did not match all operands, or if at least one operand was
5719 out-of-range, then this idesc does not match. Keep track of which
5720 idesc matched the most operands before failing. If we have two
5721 idescs that failed at the same position, and one had an out-of-range
5722 operand, then prefer the out-of-range operand. Thus if we have
5723 "add r0=0x1000000,r1" we get an error saying the constant is out
5724 of range instead of an error saying that the constant should have been
5727 if (i != num_operands || out_of_range_pos >= 0)
5729 if (i > highest_unmatched_operand
5730 || (i == highest_unmatched_operand
5731 && out_of_range_pos > curr_out_of_range_pos))
5733 highest_unmatched_operand = i;
5734 if (out_of_range_pos >= 0)
5736 expected_operand = idesc->operands[out_of_range_pos];
5737 error_pos = out_of_range_pos;
5741 expected_operand = idesc->operands[i];
5744 curr_out_of_range_pos = out_of_range_pos;
5749 if (num_operands < NELEMS (idesc->operands)
5750 && idesc->operands[num_operands])
5751 continue; /* mismatch in number of arguments */
5757 if (expected_operand)
5758 as_bad ("Operand %u of `%s' should be %s",
5759 error_pos + 1, mnemonic,
5760 elf64_ia64_operands[expected_operand].desc);
5762 as_bad ("Operand mismatch");
5768 /* Keep track of state necessary to determine whether a NOP is necessary
5769 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5770 detect a case where additional NOPs may be necessary. */
5772 errata_nop_necessary_p (slot, insn_unit)
5774 enum ia64_unit insn_unit;
5777 struct group *this_group = md.last_groups + md.group_idx;
5778 struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3;
5779 struct ia64_opcode *idesc = slot->idesc;
5781 /* Test whether this could be the first insn in a problematic sequence. */
5782 if (insn_unit == IA64_UNIT_F)
5784 for (i = 0; i < idesc->num_outputs; i++)
5785 if (idesc->operands[i] == IA64_OPND_P1
5786 || idesc->operands[i] == IA64_OPND_P2)
5788 int regno = slot->opnd[i].X_add_number - REG_P;
5789 /* Ignore invalid operands; they generate errors elsewhere. */
5792 this_group->p_reg_set[regno] = 1;
5796 /* Test whether this could be the second insn in a problematic sequence. */
5797 if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0
5798 && prev_group->p_reg_set[slot->qp_regno])
5800 for (i = 0; i < idesc->num_outputs; i++)
5801 if (idesc->operands[i] == IA64_OPND_R1
5802 || idesc->operands[i] == IA64_OPND_R2
5803 || idesc->operands[i] == IA64_OPND_R3)
5805 int regno = slot->opnd[i].X_add_number - REG_GR;
5806 /* Ignore invalid operands; they generate errors elsewhere. */
5809 if (strncmp (idesc->name, "add", 3) != 0
5810 && strncmp (idesc->name, "sub", 3) != 0
5811 && strncmp (idesc->name, "shladd", 6) != 0
5812 && (idesc->flags & IA64_OPCODE_POSTINC) == 0)
5813 this_group->g_reg_set_conditionally[regno] = 1;
5817 /* Test whether this could be the third insn in a problematic sequence. */
5818 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++)
5820 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5821 idesc->operands[i] == IA64_OPND_R3
5822 /* For mov indirect. */
5823 || idesc->operands[i] == IA64_OPND_RR_R3
5824 || idesc->operands[i] == IA64_OPND_DBR_R3
5825 || idesc->operands[i] == IA64_OPND_IBR_R3
5826 || idesc->operands[i] == IA64_OPND_PKR_R3
5827 || idesc->operands[i] == IA64_OPND_PMC_R3
5828 || idesc->operands[i] == IA64_OPND_PMD_R3
5829 || idesc->operands[i] == IA64_OPND_MSR_R3
5830 || idesc->operands[i] == IA64_OPND_CPUID_R3
5832 || idesc->operands[i] == IA64_OPND_ITR_R3
5833 || idesc->operands[i] == IA64_OPND_DTR_R3
5834 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5835 || idesc->operands[i] == IA64_OPND_MR3)
5837 int regno = slot->opnd[i].X_add_number - REG_GR;
5838 /* Ignore invalid operands; they generate errors elsewhere. */
5841 if (idesc->operands[i] == IA64_OPND_R3)
5843 if (strcmp (idesc->name, "fc") != 0
5844 && strcmp (idesc->name, "tak") != 0
5845 && strcmp (idesc->name, "thash") != 0
5846 && strcmp (idesc->name, "tpa") != 0
5847 && strcmp (idesc->name, "ttag") != 0
5848 && strncmp (idesc->name, "ptr", 3) != 0
5849 && strncmp (idesc->name, "ptc", 3) != 0
5850 && strncmp (idesc->name, "probe", 5) != 0)
5853 if (prev_group->g_reg_set_conditionally[regno])
5861 build_insn (slot, insnp)
5865 const struct ia64_operand *odesc, *o2desc;
5866 struct ia64_opcode *idesc = slot->idesc;
5867 bfd_signed_vma insn, val;
5871 insn = idesc->opcode | slot->qp_regno;
5873 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5875 if (slot->opnd[i].X_op == O_register
5876 || slot->opnd[i].X_op == O_constant
5877 || slot->opnd[i].X_op == O_index)
5878 val = slot->opnd[i].X_add_number;
5879 else if (slot->opnd[i].X_op == O_big)
5881 /* This must be the value 0x10000000000000000. */
5882 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5888 switch (idesc->operands[i])
5890 case IA64_OPND_IMMU64:
5891 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5892 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5893 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5894 | (((val >> 63) & 0x1) << 36));
5897 case IA64_OPND_IMMU62:
5898 val &= 0x3fffffffffffffffULL;
5899 if (val != slot->opnd[i].X_add_number)
5900 as_warn (_("Value truncated to 62 bits"));
5901 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5902 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
5905 case IA64_OPND_TGT64:
5907 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5908 insn |= ((((val >> 59) & 0x1) << 36)
5909 | (((val >> 0) & 0xfffff) << 13));
5940 case IA64_OPND_R3_2:
5941 case IA64_OPND_CPUID_R3:
5942 case IA64_OPND_DBR_R3:
5943 case IA64_OPND_DTR_R3:
5944 case IA64_OPND_ITR_R3:
5945 case IA64_OPND_IBR_R3:
5947 case IA64_OPND_MSR_R3:
5948 case IA64_OPND_PKR_R3:
5949 case IA64_OPND_PMC_R3:
5950 case IA64_OPND_PMD_R3:
5951 case IA64_OPND_RR_R3:
5959 odesc = elf64_ia64_operands + idesc->operands[i];
5960 err = (*odesc->insert) (odesc, val, &insn);
5962 as_bad_where (slot->src_file, slot->src_line,
5963 "Bad operand value: %s", err);
5964 if (idesc->flags & IA64_OPCODE_PSEUDO)
5966 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5967 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5969 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5970 (*o2desc->insert) (o2desc, val, &insn);
5972 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5973 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5974 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
5976 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5977 (*o2desc->insert) (o2desc, 64 - val, &insn);
5987 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5988 unsigned int manual_bundling = 0;
5989 enum ia64_unit required_unit, insn_unit = 0;
5990 enum ia64_insn_type type[3], insn_type;
5991 unsigned int template, orig_template;
5992 bfd_vma insn[3] = { -1, -1, -1 };
5993 struct ia64_opcode *idesc;
5994 int end_of_insn_group = 0, user_template = -1;
5995 int n, i, j, first, curr;
5997 bfd_vma t0 = 0, t1 = 0;
5998 struct label_fix *lfix;
5999 struct insn_fix *ifix;
6004 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
6005 know (first >= 0 & first < NUM_SLOTS);
6006 n = MIN (3, md.num_slots_in_use);
6008 /* Determine template: user user_template if specified, best match
6011 if (md.slot[first].user_template >= 0)
6012 user_template = template = md.slot[first].user_template;
6015 /* Auto select appropriate template. */
6016 memset (type, 0, sizeof (type));
6018 for (i = 0; i < n; ++i)
6020 if (md.slot[curr].label_fixups && i != 0)
6022 type[i] = md.slot[curr].idesc->type;
6023 curr = (curr + 1) % NUM_SLOTS;
6025 template = best_template[type[0]][type[1]][type[2]];
6028 /* initialize instructions with appropriate nops: */
6029 for (i = 0; i < 3; ++i)
6030 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
6034 /* now fill in slots with as many insns as possible: */
6036 idesc = md.slot[curr].idesc;
6037 end_of_insn_group = 0;
6038 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
6040 /* Set the slot number for prologue/body records now as those
6041 refer to the current point, not the point after the
6042 instruction has been issued: */
6043 /* Don't try to delete prologue/body records here, as that will cause
6044 them to also be deleted from the master list of unwind records. */
6045 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
6046 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
6047 || ptr->r.type == body)
6049 ptr->slot_number = (unsigned long) f + i;
6050 ptr->slot_frag = frag_now;
6053 if (idesc->flags & IA64_OPCODE_SLOT2)
6055 if (manual_bundling && i != 2)
6056 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6057 "`%s' must be last in bundle", idesc->name);
6061 if (idesc->flags & IA64_OPCODE_LAST)
6064 unsigned int required_template;
6066 /* If we need a stop bit after an M slot, our only choice is
6067 template 5 (M;;MI). If we need a stop bit after a B
6068 slot, our only choice is to place it at the end of the
6069 bundle, because the only available templates are MIB,
6070 MBB, BBB, MMB, and MFB. We don't handle anything other
6071 than M and B slots because these are the only kind of
6072 instructions that can have the IA64_OPCODE_LAST bit set. */
6073 required_template = template;
6074 switch (idesc->type)
6078 required_template = 5;
6086 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6087 "Internal error: don't know how to force %s to end"
6088 "of instruction group", idesc->name);
6092 if (manual_bundling && i != required_slot)
6093 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6094 "`%s' must be last in instruction group",
6096 if (required_slot < i)
6097 /* Can't fit this instruction. */
6101 if (required_template != template)
6103 /* If we switch the template, we need to reset the NOPs
6104 after slot i. The slot-types of the instructions ahead
6105 of i never change, so we don't need to worry about
6106 changing NOPs in front of this slot. */
6107 for (j = i; j < 3; ++j)
6108 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
6110 template = required_template;
6112 if (curr != first && md.slot[curr].label_fixups)
6114 if (manual_bundling_on)
6115 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6116 "Label must be first in a bundle");
6117 /* This insn must go into the first slot of a bundle. */
6121 manual_bundling_on = md.slot[curr].manual_bundling_on;
6122 manual_bundling_off = md.slot[curr].manual_bundling_off;
6124 if (manual_bundling_on)
6127 manual_bundling = 1;
6129 break; /* need to start a new bundle */
6132 if (end_of_insn_group && md.num_slots_in_use >= 1)
6134 /* We need an instruction group boundary in the middle of a
6135 bundle. See if we can switch to an other template with
6136 an appropriate boundary. */
6138 orig_template = template;
6139 if (i == 1 && (user_template == 4
6140 || (user_template < 0
6141 && (ia64_templ_desc[template].exec_unit[0]
6145 end_of_insn_group = 0;
6147 else if (i == 2 && (user_template == 0
6148 || (user_template < 0
6149 && (ia64_templ_desc[template].exec_unit[1]
6151 /* This test makes sure we don't switch the template if
6152 the next instruction is one that needs to be first in
6153 an instruction group. Since all those instructions are
6154 in the M group, there is no way such an instruction can
6155 fit in this bundle even if we switch the template. The
6156 reason we have to check for this is that otherwise we
6157 may end up generating "MI;;I M.." which has the deadly
6158 effect that the second M instruction is no longer the
6159 first in the bundle! --davidm 99/12/16 */
6160 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
6163 end_of_insn_group = 0;
6165 else if (curr != first)
6166 /* can't fit this insn */
6169 if (template != orig_template)
6170 /* if we switch the template, we need to reset the NOPs
6171 after slot i. The slot-types of the instructions ahead
6172 of i never change, so we don't need to worry about
6173 changing NOPs in front of this slot. */
6174 for (j = i; j < 3; ++j)
6175 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
6177 required_unit = ia64_templ_desc[template].exec_unit[i];
6179 /* resolve dynamic opcodes such as "break", "hint", and "nop": */
6180 if (idesc->type == IA64_TYPE_DYN)
6182 if ((strcmp (idesc->name, "nop") == 0)
6183 || (strcmp (idesc->name, "hint") == 0)
6184 || (strcmp (idesc->name, "break") == 0))
6185 insn_unit = required_unit;
6186 else if (strcmp (idesc->name, "chk.s") == 0)
6188 insn_unit = IA64_UNIT_M;
6189 if (required_unit == IA64_UNIT_I)
6190 insn_unit = IA64_UNIT_I;
6193 as_fatal ("emit_one_bundle: unexpected dynamic op");
6195 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
6196 ia64_free_opcode (idesc);
6197 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
6199 know (!idesc->next); /* no resolved dynamic ops have collisions */
6204 insn_type = idesc->type;
6205 insn_unit = IA64_UNIT_NIL;
6209 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
6210 insn_unit = required_unit;
6212 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
6213 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
6214 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
6215 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
6216 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
6221 if (insn_unit != required_unit)
6223 if (required_unit == IA64_UNIT_L
6224 && insn_unit == IA64_UNIT_I
6225 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
6227 /* we got ourselves an MLX template but the current
6228 instruction isn't an X-unit, or an I-unit instruction
6229 that can go into the X slot of an MLX template. Duh. */
6230 if (md.num_slots_in_use >= NUM_SLOTS)
6232 as_bad_where (md.slot[curr].src_file,
6233 md.slot[curr].src_line,
6234 "`%s' can't go in X slot of "
6235 "MLX template", idesc->name);
6236 /* drop this insn so we don't livelock: */
6237 --md.num_slots_in_use;
6241 continue; /* try next slot */
6247 addr = frag_now->fr_address + frag_now_fix () - 16 + i;
6248 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
6251 if (errata_nop_necessary_p (md.slot + curr, insn_unit))
6252 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6254 build_insn (md.slot + curr, insn + i);
6256 /* Set slot counts for non prologue/body unwind records. */
6257 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
6258 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
6259 && ptr->r.type != body)
6261 ptr->slot_number = (unsigned long) f + i;
6262 ptr->slot_frag = frag_now;
6264 md.slot[curr].unwind_record = NULL;
6266 if (required_unit == IA64_UNIT_L)
6269 /* skip one slot for long/X-unit instructions */
6272 --md.num_slots_in_use;
6274 /* now is a good time to fix up the labels for this insn: */
6275 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
6277 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
6278 symbol_set_frag (lfix->sym, frag_now);
6280 /* and fix up the tags also. */
6281 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
6283 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
6284 symbol_set_frag (lfix->sym, frag_now);
6287 for (j = 0; j < md.slot[curr].num_fixups; ++j)
6289 ifix = md.slot[curr].fixup + j;
6290 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8,
6291 &ifix->expr, ifix->is_pcrel, ifix->code);
6292 fix->tc_fix_data.opnd = ifix->opnd;
6293 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
6294 fix->fx_file = md.slot[curr].src_file;
6295 fix->fx_line = md.slot[curr].src_line;
6298 end_of_insn_group = md.slot[curr].end_of_insn_group;
6300 if (end_of_insn_group)
6302 md.group_idx = (md.group_idx + 1) % 3;
6303 memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]);
6307 ia64_free_opcode (md.slot[curr].idesc);
6308 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
6309 md.slot[curr].user_template = -1;
6311 if (manual_bundling_off)
6313 manual_bundling = 0;
6316 curr = (curr + 1) % NUM_SLOTS;
6317 idesc = md.slot[curr].idesc;
6319 if (manual_bundling)
6321 if (md.num_slots_in_use > 0)
6322 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6323 "`%s' does not fit into %s template",
6324 idesc->name, ia64_templ_desc[template].name);
6326 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6327 "Missing '}' at end of file");
6329 know (md.num_slots_in_use < NUM_SLOTS);
6331 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
6332 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
6334 number_to_chars_littleendian (f + 0, t0, 8);
6335 number_to_chars_littleendian (f + 8, t1, 8);
6337 unwind.next_slot_number = (unsigned long) f + 16;
6338 unwind.next_slot_frag = frag_now;
6342 md_parse_option (c, arg)
6349 /* Switches from the Intel assembler. */
6351 if (strcmp (arg, "ilp64") == 0
6352 || strcmp (arg, "lp64") == 0
6353 || strcmp (arg, "p64") == 0)
6355 md.flags |= EF_IA_64_ABI64;
6357 else if (strcmp (arg, "ilp32") == 0)
6359 md.flags &= ~EF_IA_64_ABI64;
6361 else if (strcmp (arg, "le") == 0)
6363 md.flags &= ~EF_IA_64_BE;
6365 else if (strcmp (arg, "be") == 0)
6367 md.flags |= EF_IA_64_BE;
6374 if (strcmp (arg, "so") == 0)
6376 /* Suppress signon message. */
6378 else if (strcmp (arg, "pi") == 0)
6380 /* Reject privileged instructions. FIXME */
6382 else if (strcmp (arg, "us") == 0)
6384 /* Allow union of signed and unsigned range. FIXME */
6386 else if (strcmp (arg, "close_fcalls") == 0)
6388 /* Do not resolve global function calls. */
6395 /* temp[="prefix"] Insert temporary labels into the object file
6396 symbol table prefixed by "prefix".
6397 Default prefix is ":temp:".
6402 /* indirect=<tgt> Assume unannotated indirect branches behavior
6403 according to <tgt> --
6404 exit: branch out from the current context (default)
6405 labels: all labels in context may be branch targets
6407 if (strncmp (arg, "indirect=", 9) != 0)
6412 /* -X conflicts with an ignored option, use -x instead */
6414 if (!arg || strcmp (arg, "explicit") == 0)
6416 /* set default mode to explicit */
6417 md.default_explicit_mode = 1;
6420 else if (strcmp (arg, "auto") == 0)
6422 md.default_explicit_mode = 0;
6424 else if (strcmp (arg, "debug") == 0)
6428 else if (strcmp (arg, "debugx") == 0)
6430 md.default_explicit_mode = 1;
6435 as_bad (_("Unrecognized option '-x%s'"), arg);
6440 /* nops Print nops statistics. */
6443 /* GNU specific switches for gcc. */
6444 case OPTION_MCONSTANT_GP:
6445 md.flags |= EF_IA_64_CONS_GP;
6448 case OPTION_MAUTO_PIC:
6449 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
6460 md_show_usage (stream)
6465 --mconstant-gp mark output file as using the constant-GP model\n\
6466 (sets ELF header flag EF_IA_64_CONS_GP)\n\
6467 --mauto-pic mark output file as using the constant-GP model\n\
6468 without function descriptors (sets ELF header flag\n\
6469 EF_IA_64_NOFUNCDESC_CONS_GP)\n\
6470 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6471 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6472 -x | -xexplicit turn on dependency violation checking (default)\n\
6473 -xauto automagically remove dependency violations\n\
6474 -xdebug debug dependency violation checker\n"),
6479 ia64_after_parse_args ()
6481 if (debug_type == DEBUG_STABS)
6482 as_fatal (_("--gstabs is not supported for ia64"));
6485 /* Return true if TYPE fits in TEMPL at SLOT. */
6488 match (int templ, int type, int slot)
6490 enum ia64_unit unit;
6493 unit = ia64_templ_desc[templ].exec_unit[slot];
6496 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
6498 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
6500 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
6501 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
6502 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
6503 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
6504 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
6505 default: result = 0; break;
6510 /* Add a bit of extra goodness if a nop of type F or B would fit
6511 in TEMPL at SLOT. */
6514 extra_goodness (int templ, int slot)
6516 if (slot == 1 && match (templ, IA64_TYPE_F, slot))
6518 if (slot == 2 && match (templ, IA64_TYPE_B, slot))
6523 /* This function is called once, at assembler startup time. It sets
6524 up all the tables, etc. that the MD part of the assembler will need
6525 that can be determined before arguments are parsed. */
6529 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
6534 md.explicit_mode = md.default_explicit_mode;
6536 bfd_set_section_alignment (stdoutput, text_section, 4);
6538 target_big_endian = TARGET_BYTES_BIG_ENDIAN;
6539 pseudo_func[FUNC_DTP_MODULE].u.sym =
6540 symbol_new (".<dtpmod>", undefined_section, FUNC_DTP_MODULE,
6541 &zero_address_frag);
6543 pseudo_func[FUNC_DTP_RELATIVE].u.sym =
6544 symbol_new (".<dtprel>", undefined_section, FUNC_DTP_RELATIVE,
6545 &zero_address_frag);
6547 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
6548 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
6549 &zero_address_frag);
6551 pseudo_func[FUNC_GP_RELATIVE].u.sym =
6552 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
6553 &zero_address_frag);
6555 pseudo_func[FUNC_LT_RELATIVE].u.sym =
6556 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
6557 &zero_address_frag);
6559 pseudo_func[FUNC_LT_RELATIVE_X].u.sym =
6560 symbol_new (".<ltoffx>", undefined_section, FUNC_LT_RELATIVE_X,
6561 &zero_address_frag);
6563 pseudo_func[FUNC_PC_RELATIVE].u.sym =
6564 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
6565 &zero_address_frag);
6567 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
6568 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
6569 &zero_address_frag);
6571 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
6572 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
6573 &zero_address_frag);
6575 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
6576 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
6577 &zero_address_frag);
6579 pseudo_func[FUNC_TP_RELATIVE].u.sym =
6580 symbol_new (".<tprel>", undefined_section, FUNC_TP_RELATIVE,
6581 &zero_address_frag);
6583 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
6584 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
6585 &zero_address_frag);
6587 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
6588 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
6589 &zero_address_frag);
6591 pseudo_func[FUNC_LT_DTP_MODULE].u.sym =
6592 symbol_new (".<ltoff.dtpmod>", undefined_section, FUNC_LT_DTP_MODULE,
6593 &zero_address_frag);
6595 pseudo_func[FUNC_LT_DTP_RELATIVE].u.sym =
6596 symbol_new (".<ltoff.dptrel>", undefined_section, FUNC_LT_DTP_RELATIVE,
6597 &zero_address_frag);
6599 pseudo_func[FUNC_LT_TP_RELATIVE].u.sym =
6600 symbol_new (".<ltoff.tprel>", undefined_section, FUNC_LT_TP_RELATIVE,
6601 &zero_address_frag);
6603 pseudo_func[FUNC_IPLT_RELOC].u.sym =
6604 symbol_new (".<iplt>", undefined_section, FUNC_IPLT_RELOC,
6605 &zero_address_frag);
6607 /* Compute the table of best templates. We compute goodness as a
6608 base 4 value, in which each match counts for 3, each F counts
6609 for 2, each B counts for 1. This should maximize the number of
6610 F and B nops in the chosen bundles, which is good because these
6611 pipelines are least likely to be overcommitted. */
6612 for (i = 0; i < IA64_NUM_TYPES; ++i)
6613 for (j = 0; j < IA64_NUM_TYPES; ++j)
6614 for (k = 0; k < IA64_NUM_TYPES; ++k)
6617 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
6620 if (match (t, i, 0))
6622 if (match (t, j, 1))
6624 if (match (t, k, 2))
6625 goodness = 3 + 3 + 3;
6627 goodness = 3 + 3 + extra_goodness (t, 2);
6629 else if (match (t, j, 2))
6630 goodness = 3 + 3 + extra_goodness (t, 1);
6634 goodness += extra_goodness (t, 1);
6635 goodness += extra_goodness (t, 2);
6638 else if (match (t, i, 1))
6640 if (match (t, j, 2))
6643 goodness = 3 + extra_goodness (t, 2);
6645 else if (match (t, i, 2))
6646 goodness = 3 + extra_goodness (t, 1);
6648 if (goodness > best)
6651 best_template[i][j][k] = t;
6656 for (i = 0; i < NUM_SLOTS; ++i)
6657 md.slot[i].user_template = -1;
6659 md.pseudo_hash = hash_new ();
6660 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
6662 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
6663 (void *) (pseudo_opcode + i));
6665 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6666 pseudo_opcode[i].name, err);
6669 md.reg_hash = hash_new ();
6670 md.dynreg_hash = hash_new ();
6671 md.const_hash = hash_new ();
6672 md.entry_hash = hash_new ();
6674 /* general registers: */
6677 for (i = 0; i < total; ++i)
6679 sprintf (name, "r%d", i - REG_GR);
6680 md.regsym[i] = declare_register (name, i);
6683 /* floating point registers: */
6685 for (; i < total; ++i)
6687 sprintf (name, "f%d", i - REG_FR);
6688 md.regsym[i] = declare_register (name, i);
6691 /* application registers: */
6694 for (; i < total; ++i)
6696 sprintf (name, "ar%d", i - REG_AR);
6697 md.regsym[i] = declare_register (name, i);
6700 /* control registers: */
6703 for (; i < total; ++i)
6705 sprintf (name, "cr%d", i - REG_CR);
6706 md.regsym[i] = declare_register (name, i);
6709 /* predicate registers: */
6711 for (; i < total; ++i)
6713 sprintf (name, "p%d", i - REG_P);
6714 md.regsym[i] = declare_register (name, i);
6717 /* branch registers: */
6719 for (; i < total; ++i)
6721 sprintf (name, "b%d", i - REG_BR);
6722 md.regsym[i] = declare_register (name, i);
6725 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
6726 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
6727 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
6728 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
6729 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
6730 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
6731 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
6733 for (i = 0; i < NELEMS (indirect_reg); ++i)
6735 regnum = indirect_reg[i].regnum;
6736 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
6739 /* define synonyms for application registers: */
6740 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
6741 md.regsym[i] = declare_register (ar[i - REG_AR].name,
6742 REG_AR + ar[i - REG_AR].regnum);
6744 /* define synonyms for control registers: */
6745 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
6746 md.regsym[i] = declare_register (cr[i - REG_CR].name,
6747 REG_CR + cr[i - REG_CR].regnum);
6749 declare_register ("gp", REG_GR + 1);
6750 declare_register ("sp", REG_GR + 12);
6751 declare_register ("rp", REG_BR + 0);
6753 /* pseudo-registers used to specify unwind info: */
6754 declare_register ("psp", REG_PSP);
6756 declare_register_set ("ret", 4, REG_GR + 8);
6757 declare_register_set ("farg", 8, REG_FR + 8);
6758 declare_register_set ("fret", 8, REG_FR + 8);
6760 for (i = 0; i < NELEMS (const_bits); ++i)
6762 err = hash_insert (md.const_hash, const_bits[i].name,
6763 (PTR) (const_bits + i));
6765 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6769 /* Set the architecture and machine depending on defaults and command line
6771 if (md.flags & EF_IA_64_ABI64)
6772 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64);
6774 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32);
6777 as_warn (_("Could not set architecture and machine"));
6779 /* Set the pointer size and pointer shift size depending on md.flags */
6781 if (md.flags & EF_IA_64_ABI64)
6783 md.pointer_size = 8; /* pointers are 8 bytes */
6784 md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */
6788 md.pointer_size = 4; /* pointers are 4 bytes */
6789 md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */
6792 md.mem_offset.hint = 0;
6795 md.entry_labels = NULL;
6798 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6799 because that is called after md_parse_option which is where we do the
6800 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6801 default endianness. */
6804 ia64_init (argc, argv)
6805 int argc ATTRIBUTE_UNUSED;
6806 char **argv ATTRIBUTE_UNUSED;
6808 md.flags = MD_FLAGS_DEFAULT;
6811 /* Return a string for the target object file format. */
6814 ia64_target_format ()
6816 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6818 if (md.flags & EF_IA_64_BE)
6820 if (md.flags & EF_IA_64_ABI64)
6821 #if defined(TE_AIX50)
6822 return "elf64-ia64-aix-big";
6823 #elif defined(TE_HPUX)
6824 return "elf64-ia64-hpux-big";
6826 return "elf64-ia64-big";
6829 #if defined(TE_AIX50)
6830 return "elf32-ia64-aix-big";
6831 #elif defined(TE_HPUX)
6832 return "elf32-ia64-hpux-big";
6834 return "elf32-ia64-big";
6839 if (md.flags & EF_IA_64_ABI64)
6841 return "elf64-ia64-aix-little";
6843 return "elf64-ia64-little";
6847 return "elf32-ia64-aix-little";
6849 return "elf32-ia64-little";
6854 return "unknown-format";
6858 ia64_end_of_source ()
6860 /* terminate insn group upon reaching end of file: */
6861 insn_group_break (1, 0, 0);
6863 /* emits slots we haven't written yet: */
6864 ia64_flush_insns ();
6866 bfd_set_private_flags (stdoutput, md.flags);
6868 md.mem_offset.hint = 0;
6874 if (md.qp.X_op == O_register)
6875 as_bad ("qualifying predicate not followed by instruction");
6876 md.qp.X_op = O_absent;
6878 if (ignore_input ())
6881 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
6883 if (md.detect_dv && !md.explicit_mode)
6884 as_warn (_("Explicit stops are ignored in auto mode"));
6886 insn_group_break (1, 0, 0);
6890 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6892 static int defining_tag = 0;
6895 ia64_unrecognized_line (ch)
6901 expression (&md.qp);
6902 if (*input_line_pointer++ != ')')
6904 as_bad ("Expected ')'");
6907 if (md.qp.X_op != O_register)
6909 as_bad ("Qualifying predicate expected");
6912 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
6914 as_bad ("Predicate register expected");
6920 if (md.manual_bundling)
6921 as_warn ("Found '{' when manual bundling is already turned on");
6923 CURR_SLOT.manual_bundling_on = 1;
6924 md.manual_bundling = 1;
6926 /* Bundling is only acceptable in explicit mode
6927 or when in default automatic mode. */
6928 if (md.detect_dv && !md.explicit_mode)
6930 if (!md.mode_explicitly_set
6931 && !md.default_explicit_mode)
6934 as_warn (_("Found '{' after explicit switch to automatic mode"));
6939 if (!md.manual_bundling)
6940 as_warn ("Found '}' when manual bundling is off");
6942 PREV_SLOT.manual_bundling_off = 1;
6943 md.manual_bundling = 0;
6945 /* switch back to automatic mode, if applicable */
6948 && !md.mode_explicitly_set
6949 && !md.default_explicit_mode)
6952 /* Allow '{' to follow on the same line. We also allow ";;", but that
6953 happens automatically because ';' is an end of line marker. */
6955 if (input_line_pointer[0] == '{')
6957 input_line_pointer++;
6958 return ia64_unrecognized_line ('{');
6961 demand_empty_rest_of_line ();
6971 if (md.qp.X_op == O_register)
6973 as_bad ("Tag must come before qualifying predicate.");
6977 /* This implements just enough of read_a_source_file in read.c to
6978 recognize labels. */
6979 if (is_name_beginner (*input_line_pointer))
6981 s = input_line_pointer;
6982 c = get_symbol_end ();
6984 else if (LOCAL_LABELS_FB
6985 && ISDIGIT (*input_line_pointer))
6988 while (ISDIGIT (*input_line_pointer))
6989 temp = (temp * 10) + *input_line_pointer++ - '0';
6990 fb_label_instance_inc (temp);
6991 s = fb_label_name (temp, 0);
6992 c = *input_line_pointer;
7001 /* Put ':' back for error messages' sake. */
7002 *input_line_pointer++ = ':';
7003 as_bad ("Expected ':'");
7010 /* Put ':' back for error messages' sake. */
7011 *input_line_pointer++ = ':';
7012 if (*input_line_pointer++ != ']')
7014 as_bad ("Expected ']'");
7019 as_bad ("Tag name expected");
7029 /* Not a valid line. */
7034 ia64_frob_label (sym)
7037 struct label_fix *fix;
7039 /* Tags need special handling since they are not bundle breaks like
7043 fix = obstack_alloc (¬es, sizeof (*fix));
7045 fix->next = CURR_SLOT.tag_fixups;
7046 CURR_SLOT.tag_fixups = fix;
7051 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
7053 md.last_text_seg = now_seg;
7054 fix = obstack_alloc (¬es, sizeof (*fix));
7056 fix->next = CURR_SLOT.label_fixups;
7057 CURR_SLOT.label_fixups = fix;
7059 /* Keep track of how many code entry points we've seen. */
7060 if (md.path == md.maxpaths)
7063 md.entry_labels = (const char **)
7064 xrealloc ((void *) md.entry_labels,
7065 md.maxpaths * sizeof (char *));
7067 md.entry_labels[md.path++] = S_GET_NAME (sym);
7072 ia64_flush_pending_output ()
7074 if (!md.keep_pending_output
7075 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
7077 /* ??? This causes many unnecessary stop bits to be emitted.
7078 Unfortunately, it isn't clear if it is safe to remove this. */
7079 insn_group_break (1, 0, 0);
7080 ia64_flush_insns ();
7084 /* Do ia64-specific expression optimization. All that's done here is
7085 to transform index expressions that are either due to the indexing
7086 of rotating registers or due to the indexing of indirect register
7089 ia64_optimize_expr (l, op, r)
7098 if (l->X_op == O_register && r->X_op == O_constant)
7100 num_regs = (l->X_add_number >> 16);
7101 if ((unsigned) r->X_add_number >= num_regs)
7104 as_bad ("No current frame");
7106 as_bad ("Index out of range 0..%u", num_regs - 1);
7107 r->X_add_number = 0;
7109 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
7112 else if (l->X_op == O_register && r->X_op == O_register)
7114 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
7115 || l->X_add_number == IND_MEM)
7117 as_bad ("Indirect register set name expected");
7118 l->X_add_number = IND_CPUID;
7121 l->X_op_symbol = md.regsym[l->X_add_number];
7122 l->X_add_number = r->X_add_number;
7130 ia64_parse_name (name, e)
7134 struct const_desc *cdesc;
7135 struct dynreg *dr = 0;
7136 unsigned int regnum;
7140 /* first see if NAME is a known register name: */
7141 sym = hash_find (md.reg_hash, name);
7144 e->X_op = O_register;
7145 e->X_add_number = S_GET_VALUE (sym);
7149 cdesc = hash_find (md.const_hash, name);
7152 e->X_op = O_constant;
7153 e->X_add_number = cdesc->value;
7157 /* check for inN, locN, or outN: */
7161 if (name[1] == 'n' && ISDIGIT (name[2]))
7169 if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3]))
7177 if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3]))
7190 /* The name is inN, locN, or outN; parse the register number. */
7191 regnum = strtoul (name, &end, 10);
7192 if (end > name && *end == '\0')
7194 if ((unsigned) regnum >= dr->num_regs)
7197 as_bad ("No current frame");
7199 as_bad ("Register number out of range 0..%u",
7203 e->X_op = O_register;
7204 e->X_add_number = dr->base + regnum;
7209 if ((dr = hash_find (md.dynreg_hash, name)))
7211 /* We've got ourselves the name of a rotating register set.
7212 Store the base register number in the low 16 bits of
7213 X_add_number and the size of the register set in the top 16
7215 e->X_op = O_register;
7216 e->X_add_number = dr->base | (dr->num_regs << 16);
7222 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
7225 ia64_canonicalize_symbol_name (name)
7228 size_t len = strlen (name);
7229 if (len > 1 && name[len - 1] == '#')
7230 name[len - 1] = '\0';
7234 /* Return true if idesc is a conditional branch instruction. This excludes
7235 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
7236 because they always read/write resources regardless of the value of the
7237 qualifying predicate. br.ia must always use p0, and hence is always
7238 taken. Thus this function returns true for branches which can fall
7239 through, and which use no resources if they do fall through. */
7242 is_conditional_branch (idesc)
7243 struct ia64_opcode *idesc;
7245 /* br is a conditional branch. Everything that starts with br. except
7246 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
7247 Everything that starts with brl is a conditional branch. */
7248 return (idesc->name[0] == 'b' && idesc->name[1] == 'r'
7249 && (idesc->name[2] == '\0'
7250 || (idesc->name[2] == '.' && idesc->name[3] != 'i'
7251 && idesc->name[3] != 'c' && idesc->name[3] != 'w')
7252 || idesc->name[2] == 'l'
7253 /* br.cond, br.call, br.clr */
7254 || (idesc->name[2] == '.' && idesc->name[3] == 'c'
7255 && (idesc->name[4] == 'a' || idesc->name[4] == 'o'
7256 || (idesc->name[4] == 'l' && idesc->name[5] == 'r')))));
7259 /* Return whether the given opcode is a taken branch. If there's any doubt,
7263 is_taken_branch (idesc)
7264 struct ia64_opcode *idesc;
7266 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
7267 || strncmp (idesc->name, "br.ia", 5) == 0);
7270 /* Return whether the given opcode is an interruption or rfi. If there's any
7271 doubt, returns zero. */
7274 is_interruption_or_rfi (idesc)
7275 struct ia64_opcode *idesc;
7277 if (strcmp (idesc->name, "rfi") == 0)
7282 /* Returns the index of the given dependency in the opcode's list of chks, or
7283 -1 if there is no dependency. */
7286 depends_on (depind, idesc)
7288 struct ia64_opcode *idesc;
7291 const struct ia64_opcode_dependency *dep = idesc->dependencies;
7292 for (i = 0; i < dep->nchks; i++)
7294 if (depind == DEP (dep->chks[i]))
7300 /* Determine a set of specific resources used for a particular resource
7301 class. Returns the number of specific resources identified For those
7302 cases which are not determinable statically, the resource returned is
7305 Meanings of value in 'NOTE':
7306 1) only read/write when the register number is explicitly encoded in the
7308 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
7309 accesses CFM when qualifying predicate is in the rotating region.
7310 3) general register value is used to specify an indirect register; not
7311 determinable statically.
7312 4) only read the given resource when bits 7:0 of the indirect index
7313 register value does not match the register number of the resource; not
7314 determinable statically.
7315 5) all rules are implementation specific.
7316 6) only when both the index specified by the reader and the index specified
7317 by the writer have the same value in bits 63:61; not determinable
7319 7) only access the specified resource when the corresponding mask bit is
7321 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7322 only read when these insns reference FR2-31
7323 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7324 written when these insns write FR32-127
7325 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7327 11) The target predicates are written independently of PR[qp], but source
7328 registers are only read if PR[qp] is true. Since the state of PR[qp]
7329 cannot statically be determined, all source registers are marked used.
7330 12) This insn only reads the specified predicate register when that
7331 register is the PR[qp].
7332 13) This reference to ld-c only applies to teh GR whose value is loaded
7333 with data returned from memory, not the post-incremented address register.
7334 14) The RSE resource includes the implementation-specific RSE internal
7335 state resources. At least one (and possibly more) of these resources are
7336 read by each instruction listed in IC:rse-readers. At least one (and
7337 possibly more) of these resources are written by each insn listed in
7339 15+16) Represents reserved instructions, which the assembler does not
7342 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7343 this code; there are no dependency violations based on memory access.
7346 #define MAX_SPECS 256
7351 specify_resource (dep, idesc, type, specs, note, path)
7352 const struct ia64_dependency *dep;
7353 struct ia64_opcode *idesc;
7354 int type; /* is this a DV chk or a DV reg? */
7355 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
7356 int note; /* resource note for this insn's usage */
7357 int path; /* which execution path to examine */
7364 if (dep->mode == IA64_DV_WAW
7365 || (dep->mode == IA64_DV_RAW && type == DV_REG)
7366 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
7369 /* template for any resources we identify */
7370 tmpl.dependency = dep;
7372 tmpl.insn_srlz = tmpl.data_srlz = 0;
7373 tmpl.qp_regno = CURR_SLOT.qp_regno;
7374 tmpl.link_to_qp_branch = 1;
7375 tmpl.mem_offset.hint = 0;
7378 tmpl.cmp_type = CMP_NONE;
7381 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7382 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7383 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7385 /* we don't need to track these */
7386 if (dep->semantics == IA64_DVS_NONE)
7389 switch (dep->specifier)
7394 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7396 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7397 if (regno >= 0 && regno <= 7)
7399 specs[count] = tmpl;
7400 specs[count++].index = regno;
7406 for (i = 0; i < 8; i++)
7408 specs[count] = tmpl;
7409 specs[count++].index = i;
7418 case IA64_RS_AR_UNAT:
7419 /* This is a mov =AR or mov AR= instruction. */
7420 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7422 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7423 if (regno == AR_UNAT)
7425 specs[count++] = tmpl;
7430 /* This is a spill/fill, or other instruction that modifies the
7433 /* Unless we can determine the specific bits used, mark the whole
7434 thing; bits 8:3 of the memory address indicate the bit used in
7435 UNAT. The .mem.offset hint may be used to eliminate a small
7436 subset of conflicts. */
7437 specs[count] = tmpl;
7438 if (md.mem_offset.hint)
7441 fprintf (stderr, " Using hint for spill/fill\n");
7442 /* The index isn't actually used, just set it to something
7443 approximating the bit index. */
7444 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
7445 specs[count].mem_offset.hint = 1;
7446 specs[count].mem_offset.offset = md.mem_offset.offset;
7447 specs[count++].mem_offset.base = md.mem_offset.base;
7451 specs[count++].specific = 0;
7459 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7461 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7462 if ((regno >= 8 && regno <= 15)
7463 || (regno >= 20 && regno <= 23)
7464 || (regno >= 31 && regno <= 39)
7465 || (regno >= 41 && regno <= 47)
7466 || (regno >= 67 && regno <= 111))
7468 specs[count] = tmpl;
7469 specs[count++].index = regno;
7482 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7484 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7485 if ((regno >= 48 && regno <= 63)
7486 || (regno >= 112 && regno <= 127))
7488 specs[count] = tmpl;
7489 specs[count++].index = regno;
7495 for (i = 48; i < 64; i++)
7497 specs[count] = tmpl;
7498 specs[count++].index = i;
7500 for (i = 112; i < 128; i++)
7502 specs[count] = tmpl;
7503 specs[count++].index = i;
7521 for (i = 0; i < idesc->num_outputs; i++)
7522 if (idesc->operands[i] == IA64_OPND_B1
7523 || idesc->operands[i] == IA64_OPND_B2)
7525 specs[count] = tmpl;
7526 specs[count++].index =
7527 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7532 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
7533 if (idesc->operands[i] == IA64_OPND_B1
7534 || idesc->operands[i] == IA64_OPND_B2)
7536 specs[count] = tmpl;
7537 specs[count++].index =
7538 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7544 case IA64_RS_CPUID: /* four or more registers */
7547 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
7549 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7550 if (regno >= 0 && regno < NELEMS (gr_values)
7553 specs[count] = tmpl;
7554 specs[count++].index = gr_values[regno].value & 0xFF;
7558 specs[count] = tmpl;
7559 specs[count++].specific = 0;
7569 case IA64_RS_DBR: /* four or more registers */
7572 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
7574 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7575 if (regno >= 0 && regno < NELEMS (gr_values)
7578 specs[count] = tmpl;
7579 specs[count++].index = gr_values[regno].value & 0xFF;
7583 specs[count] = tmpl;
7584 specs[count++].specific = 0;
7588 else if (note == 0 && !rsrc_write)
7590 specs[count] = tmpl;
7591 specs[count++].specific = 0;
7599 case IA64_RS_IBR: /* four or more registers */
7602 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
7604 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7605 if (regno >= 0 && regno < NELEMS (gr_values)
7608 specs[count] = tmpl;
7609 specs[count++].index = gr_values[regno].value & 0xFF;
7613 specs[count] = tmpl;
7614 specs[count++].specific = 0;
7627 /* These are implementation specific. Force all references to
7628 conflict with all other references. */
7629 specs[count] = tmpl;
7630 specs[count++].specific = 0;
7638 case IA64_RS_PKR: /* 16 or more registers */
7639 if (note == 3 || note == 4)
7641 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
7643 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7644 if (regno >= 0 && regno < NELEMS (gr_values)
7649 specs[count] = tmpl;
7650 specs[count++].index = gr_values[regno].value & 0xFF;
7653 for (i = 0; i < NELEMS (gr_values); i++)
7655 /* Uses all registers *except* the one in R3. */
7656 if ((unsigned)i != (gr_values[regno].value & 0xFF))
7658 specs[count] = tmpl;
7659 specs[count++].index = i;
7665 specs[count] = tmpl;
7666 specs[count++].specific = 0;
7673 specs[count] = tmpl;
7674 specs[count++].specific = 0;
7678 case IA64_RS_PMC: /* four or more registers */
7681 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
7682 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
7685 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
7687 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
7688 if (regno >= 0 && regno < NELEMS (gr_values)
7691 specs[count] = tmpl;
7692 specs[count++].index = gr_values[regno].value & 0xFF;
7696 specs[count] = tmpl;
7697 specs[count++].specific = 0;
7707 case IA64_RS_PMD: /* four or more registers */
7710 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
7712 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7713 if (regno >= 0 && regno < NELEMS (gr_values)
7716 specs[count] = tmpl;
7717 specs[count++].index = gr_values[regno].value & 0xFF;
7721 specs[count] = tmpl;
7722 specs[count++].specific = 0;
7732 case IA64_RS_RR: /* eight registers */
7735 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
7737 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7738 if (regno >= 0 && regno < NELEMS (gr_values)
7741 specs[count] = tmpl;
7742 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
7746 specs[count] = tmpl;
7747 specs[count++].specific = 0;
7751 else if (note == 0 && !rsrc_write)
7753 specs[count] = tmpl;
7754 specs[count++].specific = 0;
7762 case IA64_RS_CR_IRR:
7765 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7766 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
7768 && idesc->operands[1] == IA64_OPND_CR3
7771 for (i = 0; i < 4; i++)
7773 specs[count] = tmpl;
7774 specs[count++].index = CR_IRR0 + i;
7780 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7781 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7783 && regno <= CR_IRR3)
7785 specs[count] = tmpl;
7786 specs[count++].index = regno;
7795 case IA64_RS_CR_LRR:
7802 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7803 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7804 && (regno == CR_LRR0 || regno == CR_LRR1))
7806 specs[count] = tmpl;
7807 specs[count++].index = regno;
7815 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7817 specs[count] = tmpl;
7818 specs[count++].index =
7819 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7834 else if (rsrc_write)
7836 if (dep->specifier == IA64_RS_FRb
7837 && idesc->operands[0] == IA64_OPND_F1)
7839 specs[count] = tmpl;
7840 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
7845 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
7847 if (idesc->operands[i] == IA64_OPND_F2
7848 || idesc->operands[i] == IA64_OPND_F3
7849 || idesc->operands[i] == IA64_OPND_F4)
7851 specs[count] = tmpl;
7852 specs[count++].index =
7853 CURR_SLOT.opnd[i].X_add_number - REG_FR;
7862 /* This reference applies only to the GR whose value is loaded with
7863 data returned from memory. */
7864 specs[count] = tmpl;
7865 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7871 for (i = 0; i < idesc->num_outputs; i++)
7872 if (idesc->operands[i] == IA64_OPND_R1
7873 || idesc->operands[i] == IA64_OPND_R2
7874 || idesc->operands[i] == IA64_OPND_R3)
7876 specs[count] = tmpl;
7877 specs[count++].index =
7878 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7880 if (idesc->flags & IA64_OPCODE_POSTINC)
7881 for (i = 0; i < NELEMS (idesc->operands); i++)
7882 if (idesc->operands[i] == IA64_OPND_MR3)
7884 specs[count] = tmpl;
7885 specs[count++].index =
7886 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7891 /* Look for anything that reads a GR. */
7892 for (i = 0; i < NELEMS (idesc->operands); i++)
7894 if (idesc->operands[i] == IA64_OPND_MR3
7895 || idesc->operands[i] == IA64_OPND_CPUID_R3
7896 || idesc->operands[i] == IA64_OPND_DBR_R3
7897 || idesc->operands[i] == IA64_OPND_IBR_R3
7898 || idesc->operands[i] == IA64_OPND_MSR_R3
7899 || idesc->operands[i] == IA64_OPND_PKR_R3
7900 || idesc->operands[i] == IA64_OPND_PMC_R3
7901 || idesc->operands[i] == IA64_OPND_PMD_R3
7902 || idesc->operands[i] == IA64_OPND_RR_R3
7903 || ((i >= idesc->num_outputs)
7904 && (idesc->operands[i] == IA64_OPND_R1
7905 || idesc->operands[i] == IA64_OPND_R2
7906 || idesc->operands[i] == IA64_OPND_R3
7907 /* addl source register. */
7908 || idesc->operands[i] == IA64_OPND_R3_2)))
7910 specs[count] = tmpl;
7911 specs[count++].index =
7912 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7923 /* This is the same as IA64_RS_PRr, except that the register range is
7924 from 1 - 15, and there are no rotating register reads/writes here. */
7928 for (i = 1; i < 16; i++)
7930 specs[count] = tmpl;
7931 specs[count++].index = i;
7937 /* Mark only those registers indicated by the mask. */
7940 mask = CURR_SLOT.opnd[2].X_add_number;
7941 for (i = 1; i < 16; i++)
7942 if (mask & ((valueT) 1 << i))
7944 specs[count] = tmpl;
7945 specs[count++].index = i;
7953 else if (note == 11) /* note 11 implies note 1 as well */
7957 for (i = 0; i < idesc->num_outputs; i++)
7959 if (idesc->operands[i] == IA64_OPND_P1
7960 || idesc->operands[i] == IA64_OPND_P2)
7962 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7963 if (regno >= 1 && regno < 16)
7965 specs[count] = tmpl;
7966 specs[count++].index = regno;
7976 else if (note == 12)
7978 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7980 specs[count] = tmpl;
7981 specs[count++].index = CURR_SLOT.qp_regno;
7988 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7989 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7990 int or_andcm = strstr (idesc->name, "or.andcm") != NULL;
7991 int and_orcm = strstr (idesc->name, "and.orcm") != NULL;
7993 if ((idesc->operands[0] == IA64_OPND_P1
7994 || idesc->operands[0] == IA64_OPND_P2)
7995 && p1 >= 1 && p1 < 16)
7997 specs[count] = tmpl;
7998 specs[count].cmp_type =
7999 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
8000 specs[count++].index = p1;
8002 if ((idesc->operands[1] == IA64_OPND_P1
8003 || idesc->operands[1] == IA64_OPND_P2)
8004 && p2 >= 1 && p2 < 16)
8006 specs[count] = tmpl;
8007 specs[count].cmp_type =
8008 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
8009 specs[count++].index = p2;
8014 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
8016 specs[count] = tmpl;
8017 specs[count++].index = CURR_SLOT.qp_regno;
8019 if (idesc->operands[1] == IA64_OPND_PR)
8021 for (i = 1; i < 16; i++)
8023 specs[count] = tmpl;
8024 specs[count++].index = i;
8035 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
8036 simplified cases of this. */
8040 for (i = 16; i < 63; i++)
8042 specs[count] = tmpl;
8043 specs[count++].index = i;
8049 /* Mark only those registers indicated by the mask. */
8051 && idesc->operands[0] == IA64_OPND_PR)
8053 mask = CURR_SLOT.opnd[2].X_add_number;
8054 if (mask & ((valueT) 1 << 16))
8055 for (i = 16; i < 63; i++)
8057 specs[count] = tmpl;
8058 specs[count++].index = i;
8062 && idesc->operands[0] == IA64_OPND_PR_ROT)
8064 for (i = 16; i < 63; i++)
8066 specs[count] = tmpl;
8067 specs[count++].index = i;
8075 else if (note == 11) /* note 11 implies note 1 as well */
8079 for (i = 0; i < idesc->num_outputs; i++)
8081 if (idesc->operands[i] == IA64_OPND_P1
8082 || idesc->operands[i] == IA64_OPND_P2)
8084 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
8085 if (regno >= 16 && regno < 63)
8087 specs[count] = tmpl;
8088 specs[count++].index = regno;
8098 else if (note == 12)
8100 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
8102 specs[count] = tmpl;
8103 specs[count++].index = CURR_SLOT.qp_regno;
8110 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8111 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8112 int or_andcm = strstr (idesc->name, "or.andcm") != NULL;
8113 int and_orcm = strstr (idesc->name, "and.orcm") != NULL;
8115 if ((idesc->operands[0] == IA64_OPND_P1
8116 || idesc->operands[0] == IA64_OPND_P2)
8117 && p1 >= 16 && p1 < 63)
8119 specs[count] = tmpl;
8120 specs[count].cmp_type =
8121 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
8122 specs[count++].index = p1;
8124 if ((idesc->operands[1] == IA64_OPND_P1
8125 || idesc->operands[1] == IA64_OPND_P2)
8126 && p2 >= 16 && p2 < 63)
8128 specs[count] = tmpl;
8129 specs[count].cmp_type =
8130 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
8131 specs[count++].index = p2;
8136 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
8138 specs[count] = tmpl;
8139 specs[count++].index = CURR_SLOT.qp_regno;
8141 if (idesc->operands[1] == IA64_OPND_PR)
8143 for (i = 16; i < 63; i++)
8145 specs[count] = tmpl;
8146 specs[count++].index = i;
8158 /* Verify that the instruction is using the PSR bit indicated in
8162 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
8164 if (dep->regindex < 6)
8166 specs[count++] = tmpl;
8169 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
8171 if (dep->regindex < 32
8172 || dep->regindex == 35
8173 || dep->regindex == 36
8174 || (!rsrc_write && dep->regindex == PSR_CPL))
8176 specs[count++] = tmpl;
8179 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
8181 if (dep->regindex < 32
8182 || dep->regindex == 35
8183 || dep->regindex == 36
8184 || (rsrc_write && dep->regindex == PSR_CPL))
8186 specs[count++] = tmpl;
8191 /* Several PSR bits have very specific dependencies. */
8192 switch (dep->regindex)
8195 specs[count++] = tmpl;
8200 specs[count++] = tmpl;
8204 /* Only certain CR accesses use PSR.ic */
8205 if (idesc->operands[0] == IA64_OPND_CR3
8206 || idesc->operands[1] == IA64_OPND_CR3)
8209 ((idesc->operands[0] == IA64_OPND_CR3)
8212 CURR_SLOT.opnd[index].X_add_number - REG_CR;
8227 specs[count++] = tmpl;
8236 specs[count++] = tmpl;
8240 /* Only some AR accesses use cpl */
8241 if (idesc->operands[0] == IA64_OPND_AR3
8242 || idesc->operands[1] == IA64_OPND_AR3)
8245 ((idesc->operands[0] == IA64_OPND_AR3)
8248 CURR_SLOT.opnd[index].X_add_number - REG_AR;
8255 && regno <= AR_K7))))
8257 specs[count++] = tmpl;
8262 specs[count++] = tmpl;
8272 if (idesc->operands[0] == IA64_OPND_IMMU24)
8274 mask = CURR_SLOT.opnd[0].X_add_number;
8280 if (mask & ((valueT) 1 << dep->regindex))
8282 specs[count++] = tmpl;
8287 int min = dep->regindex == PSR_DFL ? 2 : 32;
8288 int max = dep->regindex == PSR_DFL ? 31 : 127;
8289 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8290 for (i = 0; i < NELEMS (idesc->operands); i++)
8292 if (idesc->operands[i] == IA64_OPND_F1
8293 || idesc->operands[i] == IA64_OPND_F2
8294 || idesc->operands[i] == IA64_OPND_F3
8295 || idesc->operands[i] == IA64_OPND_F4)
8297 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8298 if (reg >= min && reg <= max)
8300 specs[count++] = tmpl;
8307 int min = dep->regindex == PSR_MFL ? 2 : 32;
8308 int max = dep->regindex == PSR_MFL ? 31 : 127;
8309 /* mfh is read on writes to FR32-127; mfl is read on writes to
8311 for (i = 0; i < idesc->num_outputs; i++)
8313 if (idesc->operands[i] == IA64_OPND_F1)
8315 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8316 if (reg >= min && reg <= max)
8318 specs[count++] = tmpl;
8323 else if (note == 10)
8325 for (i = 0; i < NELEMS (idesc->operands); i++)
8327 if (idesc->operands[i] == IA64_OPND_R1
8328 || idesc->operands[i] == IA64_OPND_R2
8329 || idesc->operands[i] == IA64_OPND_R3)
8331 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8332 if (regno >= 16 && regno <= 31)
8334 specs[count++] = tmpl;
8345 case IA64_RS_AR_FPSR:
8346 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
8348 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8349 if (regno == AR_FPSR)
8351 specs[count++] = tmpl;
8356 specs[count++] = tmpl;
8361 /* Handle all AR[REG] resources */
8362 if (note == 0 || note == 1)
8364 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8365 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
8366 && regno == dep->regindex)
8368 specs[count++] = tmpl;
8370 /* other AR[REG] resources may be affected by AR accesses */
8371 else if (idesc->operands[0] == IA64_OPND_AR3)
8374 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
8375 switch (dep->regindex)
8381 if (regno == AR_BSPSTORE)
8383 specs[count++] = tmpl;
8387 (regno == AR_BSPSTORE
8388 || regno == AR_RNAT))
8390 specs[count++] = tmpl;
8395 else if (idesc->operands[1] == IA64_OPND_AR3)
8398 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
8399 switch (dep->regindex)
8404 if (regno == AR_BSPSTORE || regno == AR_RNAT)
8406 specs[count++] = tmpl;
8413 specs[count++] = tmpl;
8423 /* Handle all CR[REG] resources */
8424 if (note == 0 || note == 1)
8426 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
8428 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
8429 if (regno == dep->regindex)
8431 specs[count++] = tmpl;
8433 else if (!rsrc_write)
8435 /* Reads from CR[IVR] affect other resources. */
8436 if (regno == CR_IVR)
8438 if ((dep->regindex >= CR_IRR0
8439 && dep->regindex <= CR_IRR3)
8440 || dep->regindex == CR_TPR)
8442 specs[count++] = tmpl;
8449 specs[count++] = tmpl;
8458 case IA64_RS_INSERVICE:
8459 /* look for write of EOI (67) or read of IVR (65) */
8460 if ((idesc->operands[0] == IA64_OPND_CR3
8461 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
8462 || (idesc->operands[1] == IA64_OPND_CR3
8463 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
8465 specs[count++] = tmpl;
8472 specs[count++] = tmpl;
8483 specs[count++] = tmpl;
8487 /* Check if any of the registers accessed are in the rotating region.
8488 mov to/from pr accesses CFM only when qp_regno is in the rotating
8490 for (i = 0; i < NELEMS (idesc->operands); i++)
8492 if (idesc->operands[i] == IA64_OPND_R1
8493 || idesc->operands[i] == IA64_OPND_R2
8494 || idesc->operands[i] == IA64_OPND_R3)
8496 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8497 /* Assumes that md.rot.num_regs is always valid */
8498 if (md.rot.num_regs > 0
8500 && num < 31 + md.rot.num_regs)
8502 specs[count] = tmpl;
8503 specs[count++].specific = 0;
8506 else if (idesc->operands[i] == IA64_OPND_F1
8507 || idesc->operands[i] == IA64_OPND_F2
8508 || idesc->operands[i] == IA64_OPND_F3
8509 || idesc->operands[i] == IA64_OPND_F4)
8511 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8514 specs[count] = tmpl;
8515 specs[count++].specific = 0;
8518 else if (idesc->operands[i] == IA64_OPND_P1
8519 || idesc->operands[i] == IA64_OPND_P2)
8521 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
8524 specs[count] = tmpl;
8525 specs[count++].specific = 0;
8529 if (CURR_SLOT.qp_regno > 15)
8531 specs[count] = tmpl;
8532 specs[count++].specific = 0;
8537 /* This is the same as IA64_RS_PRr, except simplified to account for
8538 the fact that there is only one register. */
8542 specs[count++] = tmpl;
8547 if (idesc->operands[2] == IA64_OPND_IMM17)
8548 mask = CURR_SLOT.opnd[2].X_add_number;
8549 if (mask & ((valueT) 1 << 63))
8550 specs[count++] = tmpl;
8552 else if (note == 11)
8554 if ((idesc->operands[0] == IA64_OPND_P1
8555 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
8556 || (idesc->operands[1] == IA64_OPND_P2
8557 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
8559 specs[count++] = tmpl;
8562 else if (note == 12)
8564 if (CURR_SLOT.qp_regno == 63)
8566 specs[count++] = tmpl;
8573 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8574 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8575 int or_andcm = strstr (idesc->name, "or.andcm") != NULL;
8576 int and_orcm = strstr (idesc->name, "and.orcm") != NULL;
8579 && (idesc->operands[0] == IA64_OPND_P1
8580 || idesc->operands[0] == IA64_OPND_P2))
8582 specs[count] = tmpl;
8583 specs[count++].cmp_type =
8584 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
8587 && (idesc->operands[1] == IA64_OPND_P1
8588 || idesc->operands[1] == IA64_OPND_P2))
8590 specs[count] = tmpl;
8591 specs[count++].cmp_type =
8592 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
8597 if (CURR_SLOT.qp_regno == 63)
8599 specs[count++] = tmpl;
8610 /* FIXME we can identify some individual RSE written resources, but RSE
8611 read resources have not yet been completely identified, so for now
8612 treat RSE as a single resource */
8613 if (strncmp (idesc->name, "mov", 3) == 0)
8617 if (idesc->operands[0] == IA64_OPND_AR3
8618 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
8620 specs[count] = tmpl;
8621 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8626 if (idesc->operands[0] == IA64_OPND_AR3)
8628 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
8629 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
8631 specs[count++] = tmpl;
8634 else if (idesc->operands[1] == IA64_OPND_AR3)
8636 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
8637 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
8638 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
8640 specs[count++] = tmpl;
8647 specs[count++] = tmpl;
8652 /* FIXME -- do any of these need to be non-specific? */
8653 specs[count++] = tmpl;
8657 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
8664 /* Clear branch flags on marked resources. This breaks the link between the
8665 QP of the marking instruction and a subsequent branch on the same QP. */
8668 clear_qp_branch_flag (mask)
8672 for (i = 0; i < regdepslen; i++)
8674 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
8675 if ((bit & mask) != 0)
8677 regdeps[i].link_to_qp_branch = 0;
8682 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8684 Any changes to a PR clears the mutex relations which include that PR. */
8687 clear_qp_mutex (mask)
8693 while (i < qp_mutexeslen)
8695 if ((qp_mutexes[i].prmask & mask) != 0)
8699 fprintf (stderr, " Clearing mutex relation");
8700 print_prmask (qp_mutexes[i].prmask);
8701 fprintf (stderr, "\n");
8703 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
8710 /* Clear implies relations which contain PRs in the given masks.
8711 P1_MASK indicates the source of the implies relation, while P2_MASK
8712 indicates the implied PR. */
8715 clear_qp_implies (p1_mask, p2_mask)
8722 while (i < qp_implieslen)
8724 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
8725 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
8728 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
8729 qp_implies[i].p1, qp_implies[i].p2);
8730 qp_implies[i] = qp_implies[--qp_implieslen];
8737 /* Add the PRs specified to the list of implied relations. */
8740 add_qp_imply (p1, p2)
8747 /* p0 is not meaningful here. */
8748 if (p1 == 0 || p2 == 0)
8754 /* If it exists already, ignore it. */
8755 for (i = 0; i < qp_implieslen; i++)
8757 if (qp_implies[i].p1 == p1
8758 && qp_implies[i].p2 == p2
8759 && qp_implies[i].path == md.path
8760 && !qp_implies[i].p2_branched)
8764 if (qp_implieslen == qp_impliestotlen)
8766 qp_impliestotlen += 20;
8767 qp_implies = (struct qp_imply *)
8768 xrealloc ((void *) qp_implies,
8769 qp_impliestotlen * sizeof (struct qp_imply));
8772 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
8773 qp_implies[qp_implieslen].p1 = p1;
8774 qp_implies[qp_implieslen].p2 = p2;
8775 qp_implies[qp_implieslen].path = md.path;
8776 qp_implies[qp_implieslen++].p2_branched = 0;
8778 /* Add in the implied transitive relations; for everything that p2 implies,
8779 make p1 imply that, too; for everything that implies p1, make it imply p2
8781 for (i = 0; i < qp_implieslen; i++)
8783 if (qp_implies[i].p1 == p2)
8784 add_qp_imply (p1, qp_implies[i].p2);
8785 if (qp_implies[i].p2 == p1)
8786 add_qp_imply (qp_implies[i].p1, p2);
8788 /* Add in mutex relations implied by this implies relation; for each mutex
8789 relation containing p2, duplicate it and replace p2 with p1. */
8790 bit = (valueT) 1 << p1;
8791 mask = (valueT) 1 << p2;
8792 for (i = 0; i < qp_mutexeslen; i++)
8794 if (qp_mutexes[i].prmask & mask)
8795 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
8799 /* Add the PRs specified in the mask to the mutex list; this means that only
8800 one of the PRs can be true at any time. PR0 should never be included in
8810 if (qp_mutexeslen == qp_mutexestotlen)
8812 qp_mutexestotlen += 20;
8813 qp_mutexes = (struct qpmutex *)
8814 xrealloc ((void *) qp_mutexes,
8815 qp_mutexestotlen * sizeof (struct qpmutex));
8819 fprintf (stderr, " Registering mutex on");
8820 print_prmask (mask);
8821 fprintf (stderr, "\n");
8823 qp_mutexes[qp_mutexeslen].path = md.path;
8824 qp_mutexes[qp_mutexeslen++].prmask = mask;
8828 has_suffix_p (name, suffix)
8832 size_t namelen = strlen (name);
8833 size_t sufflen = strlen (suffix);
8835 if (namelen <= sufflen)
8837 return strcmp (name + namelen - sufflen, suffix) == 0;
8841 clear_register_values ()
8845 fprintf (stderr, " Clearing register values\n");
8846 for (i = 1; i < NELEMS (gr_values); i++)
8847 gr_values[i].known = 0;
8850 /* Keep track of register values/changes which affect DV tracking.
8852 optimization note: should add a flag to classes of insns where otherwise we
8853 have to examine a group of strings to identify them. */
8856 note_register_values (idesc)
8857 struct ia64_opcode *idesc;
8859 valueT qp_changemask = 0;
8862 /* Invalidate values for registers being written to. */
8863 for (i = 0; i < idesc->num_outputs; i++)
8865 if (idesc->operands[i] == IA64_OPND_R1
8866 || idesc->operands[i] == IA64_OPND_R2
8867 || idesc->operands[i] == IA64_OPND_R3)
8869 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8870 if (regno > 0 && regno < NELEMS (gr_values))
8871 gr_values[regno].known = 0;
8873 else if (idesc->operands[i] == IA64_OPND_R3_2)
8875 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8876 if (regno > 0 && regno < 4)
8877 gr_values[regno].known = 0;
8879 else if (idesc->operands[i] == IA64_OPND_P1
8880 || idesc->operands[i] == IA64_OPND_P2)
8882 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
8883 qp_changemask |= (valueT) 1 << regno;
8885 else if (idesc->operands[i] == IA64_OPND_PR)
8887 if (idesc->operands[2] & (valueT) 0x10000)
8888 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
8890 qp_changemask = idesc->operands[2];
8893 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
8895 if (idesc->operands[1] & ((valueT) 1 << 43))
8896 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
8898 qp_changemask = idesc->operands[1];
8899 qp_changemask &= ~(valueT) 0xFFFF;
8904 /* Always clear qp branch flags on any PR change. */
8905 /* FIXME there may be exceptions for certain compares. */
8906 clear_qp_branch_flag (qp_changemask);
8908 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8909 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
8911 qp_changemask |= ~(valueT) 0xFFFF;
8912 if (strcmp (idesc->name, "clrrrb.pr") != 0)
8914 for (i = 32; i < 32 + md.rot.num_regs; i++)
8915 gr_values[i].known = 0;
8917 clear_qp_mutex (qp_changemask);
8918 clear_qp_implies (qp_changemask, qp_changemask);
8920 /* After a call, all register values are undefined, except those marked
8922 else if (strncmp (idesc->name, "br.call", 6) == 0
8923 || strncmp (idesc->name, "brl.call", 7) == 0)
8925 /* FIXME keep GR values which are marked as "safe_across_calls" */
8926 clear_register_values ();
8927 clear_qp_mutex (~qp_safe_across_calls);
8928 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
8929 clear_qp_branch_flag (~qp_safe_across_calls);
8931 else if (is_interruption_or_rfi (idesc)
8932 || is_taken_branch (idesc))
8934 clear_register_values ();
8935 clear_qp_mutex (~(valueT) 0);
8936 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
8938 /* Look for mutex and implies relations. */
8939 else if ((idesc->operands[0] == IA64_OPND_P1
8940 || idesc->operands[0] == IA64_OPND_P2)
8941 && (idesc->operands[1] == IA64_OPND_P1
8942 || idesc->operands[1] == IA64_OPND_P2))
8944 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8945 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8946 valueT p1mask = (valueT) 1 << p1;
8947 valueT p2mask = (valueT) 1 << p2;
8949 /* If one of the PRs is PR0, we can't really do anything. */
8950 if (p1 == 0 || p2 == 0)
8953 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
8955 /* In general, clear mutexes and implies which include P1 or P2,
8956 with the following exceptions. */
8957 else if (has_suffix_p (idesc->name, ".or.andcm")
8958 || has_suffix_p (idesc->name, ".and.orcm"))
8960 add_qp_mutex (p1mask | p2mask);
8961 clear_qp_implies (p2mask, p1mask);
8963 else if (has_suffix_p (idesc->name, ".andcm")
8964 || has_suffix_p (idesc->name, ".and"))
8966 clear_qp_implies (0, p1mask | p2mask);
8968 else if (has_suffix_p (idesc->name, ".orcm")
8969 || has_suffix_p (idesc->name, ".or"))
8971 clear_qp_mutex (p1mask | p2mask);
8972 clear_qp_implies (p1mask | p2mask, 0);
8976 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
8977 if (has_suffix_p (idesc->name, ".unc"))
8979 add_qp_mutex (p1mask | p2mask);
8980 if (CURR_SLOT.qp_regno != 0)
8982 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
8983 CURR_SLOT.qp_regno);
8984 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
8985 CURR_SLOT.qp_regno);
8988 else if (CURR_SLOT.qp_regno == 0)
8990 add_qp_mutex (p1mask | p2mask);
8994 clear_qp_mutex (p1mask | p2mask);
8998 /* Look for mov imm insns into GRs. */
8999 else if (idesc->operands[0] == IA64_OPND_R1
9000 && (idesc->operands[1] == IA64_OPND_IMM22
9001 || idesc->operands[1] == IA64_OPND_IMMU64)
9002 && (strcmp (idesc->name, "mov") == 0
9003 || strcmp (idesc->name, "movl") == 0))
9005 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
9006 if (regno > 0 && regno < NELEMS (gr_values))
9008 gr_values[regno].known = 1;
9009 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
9010 gr_values[regno].path = md.path;
9013 fprintf (stderr, " Know gr%d = ", regno);
9014 fprintf_vma (stderr, gr_values[regno].value);
9015 fputs ("\n", stderr);
9021 clear_qp_mutex (qp_changemask);
9022 clear_qp_implies (qp_changemask, qp_changemask);
9026 /* Return whether the given predicate registers are currently mutex. */
9029 qp_mutex (p1, p2, path)
9039 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
9040 for (i = 0; i < qp_mutexeslen; i++)
9042 if (qp_mutexes[i].path >= path
9043 && (qp_mutexes[i].prmask & mask) == mask)
9050 /* Return whether the given resource is in the given insn's list of chks
9051 Return 1 if the conflict is absolutely determined, 2 if it's a potential
9055 resources_match (rs, idesc, note, qp_regno, path)
9057 struct ia64_opcode *idesc;
9062 struct rsrc specs[MAX_SPECS];
9065 /* If the marked resource's qp_regno and the given qp_regno are mutex,
9066 we don't need to check. One exception is note 11, which indicates that
9067 target predicates are written regardless of PR[qp]. */
9068 if (qp_mutex (rs->qp_regno, qp_regno, path)
9072 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
9075 /* UNAT checking is a bit more specific than other resources */
9076 if (rs->dependency->specifier == IA64_RS_AR_UNAT
9077 && specs[count].mem_offset.hint
9078 && rs->mem_offset.hint)
9080 if (rs->mem_offset.base == specs[count].mem_offset.base)
9082 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
9083 ((specs[count].mem_offset.offset >> 3) & 0x3F))
9090 /* Skip apparent PR write conflicts where both writes are an AND or both
9091 writes are an OR. */
9092 if (rs->dependency->specifier == IA64_RS_PR
9093 || rs->dependency->specifier == IA64_RS_PRr
9094 || rs->dependency->specifier == IA64_RS_PR63)
9096 if (specs[count].cmp_type != CMP_NONE
9097 && specs[count].cmp_type == rs->cmp_type)
9100 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
9101 dv_mode[rs->dependency->mode],
9102 rs->dependency->specifier != IA64_RS_PR63 ?
9103 specs[count].index : 63);
9108 " %s on parallel compare conflict %s vs %s on PR%d\n",
9109 dv_mode[rs->dependency->mode],
9110 dv_cmp_type[rs->cmp_type],
9111 dv_cmp_type[specs[count].cmp_type],
9112 rs->dependency->specifier != IA64_RS_PR63 ?
9113 specs[count].index : 63);
9117 /* If either resource is not specific, conservatively assume a conflict
9119 if (!specs[count].specific || !rs->specific)
9121 else if (specs[count].index == rs->index)
9126 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
9132 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
9133 insert a stop to create the break. Update all resource dependencies
9134 appropriately. If QP_REGNO is non-zero, only apply the break to resources
9135 which use the same QP_REGNO and have the link_to_qp_branch flag set.
9136 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
9140 insn_group_break (insert_stop, qp_regno, save_current)
9147 if (insert_stop && md.num_slots_in_use > 0)
9148 PREV_SLOT.end_of_insn_group = 1;
9152 fprintf (stderr, " Insn group break%s",
9153 (insert_stop ? " (w/stop)" : ""));
9155 fprintf (stderr, " effective for QP=%d", qp_regno);
9156 fprintf (stderr, "\n");
9160 while (i < regdepslen)
9162 const struct ia64_dependency *dep = regdeps[i].dependency;
9165 && regdeps[i].qp_regno != qp_regno)
9172 && CURR_SLOT.src_file == regdeps[i].file
9173 && CURR_SLOT.src_line == regdeps[i].line)
9179 /* clear dependencies which are automatically cleared by a stop, or
9180 those that have reached the appropriate state of insn serialization */
9181 if (dep->semantics == IA64_DVS_IMPLIED
9182 || dep->semantics == IA64_DVS_IMPLIEDF
9183 || regdeps[i].insn_srlz == STATE_SRLZ)
9185 print_dependency ("Removing", i);
9186 regdeps[i] = regdeps[--regdepslen];
9190 if (dep->semantics == IA64_DVS_DATA
9191 || dep->semantics == IA64_DVS_INSTR
9192 || dep->semantics == IA64_DVS_SPECIFIC)
9194 if (regdeps[i].insn_srlz == STATE_NONE)
9195 regdeps[i].insn_srlz = STATE_STOP;
9196 if (regdeps[i].data_srlz == STATE_NONE)
9197 regdeps[i].data_srlz = STATE_STOP;
9204 /* Add the given resource usage spec to the list of active dependencies. */
9207 mark_resource (idesc, dep, spec, depind, path)
9208 struct ia64_opcode *idesc ATTRIBUTE_UNUSED;
9209 const struct ia64_dependency *dep ATTRIBUTE_UNUSED;
9214 if (regdepslen == regdepstotlen)
9216 regdepstotlen += 20;
9217 regdeps = (struct rsrc *)
9218 xrealloc ((void *) regdeps,
9219 regdepstotlen * sizeof (struct rsrc));
9222 regdeps[regdepslen] = *spec;
9223 regdeps[regdepslen].depind = depind;
9224 regdeps[regdepslen].path = path;
9225 regdeps[regdepslen].file = CURR_SLOT.src_file;
9226 regdeps[regdepslen].line = CURR_SLOT.src_line;
9228 print_dependency ("Adding", regdepslen);
9234 print_dependency (action, depind)
9240 fprintf (stderr, " %s %s '%s'",
9241 action, dv_mode[(regdeps[depind].dependency)->mode],
9242 (regdeps[depind].dependency)->name);
9243 if (regdeps[depind].specific && regdeps[depind].index != 0)
9244 fprintf (stderr, " (%d)", regdeps[depind].index);
9245 if (regdeps[depind].mem_offset.hint)
9247 fputs (" ", stderr);
9248 fprintf_vma (stderr, regdeps[depind].mem_offset.base);
9249 fputs ("+", stderr);
9250 fprintf_vma (stderr, regdeps[depind].mem_offset.offset);
9252 fprintf (stderr, "\n");
9257 instruction_serialization ()
9261 fprintf (stderr, " Instruction serialization\n");
9262 for (i = 0; i < regdepslen; i++)
9263 if (regdeps[i].insn_srlz == STATE_STOP)
9264 regdeps[i].insn_srlz = STATE_SRLZ;
9268 data_serialization ()
9272 fprintf (stderr, " Data serialization\n");
9273 while (i < regdepslen)
9275 if (regdeps[i].data_srlz == STATE_STOP
9276 /* Note: as of 991210, all "other" dependencies are cleared by a
9277 data serialization. This might change with new tables */
9278 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
9280 print_dependency ("Removing", i);
9281 regdeps[i] = regdeps[--regdepslen];
9288 /* Insert stops and serializations as needed to avoid DVs. */
9291 remove_marked_resource (rs)
9294 switch (rs->dependency->semantics)
9296 case IA64_DVS_SPECIFIC:
9298 fprintf (stderr, "Implementation-specific, assume worst case...\n");
9299 /* ...fall through... */
9300 case IA64_DVS_INSTR:
9302 fprintf (stderr, "Inserting instr serialization\n");
9303 if (rs->insn_srlz < STATE_STOP)
9304 insn_group_break (1, 0, 0);
9305 if (rs->insn_srlz < STATE_SRLZ)
9307 int oldqp = CURR_SLOT.qp_regno;
9308 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
9309 /* Manually jam a srlz.i insn into the stream */
9310 CURR_SLOT.qp_regno = 0;
9311 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
9312 instruction_serialization ();
9313 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9314 if (++md.num_slots_in_use >= NUM_SLOTS)
9316 CURR_SLOT.qp_regno = oldqp;
9317 CURR_SLOT.idesc = oldidesc;
9319 insn_group_break (1, 0, 0);
9321 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
9322 "other" types of DV are eliminated
9323 by a data serialization */
9326 fprintf (stderr, "Inserting data serialization\n");
9327 if (rs->data_srlz < STATE_STOP)
9328 insn_group_break (1, 0, 0);
9330 int oldqp = CURR_SLOT.qp_regno;
9331 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
9332 /* Manually jam a srlz.d insn into the stream */
9333 CURR_SLOT.qp_regno = 0;
9334 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
9335 data_serialization ();
9336 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9337 if (++md.num_slots_in_use >= NUM_SLOTS)
9339 CURR_SLOT.qp_regno = oldqp;
9340 CURR_SLOT.idesc = oldidesc;
9343 case IA64_DVS_IMPLIED:
9344 case IA64_DVS_IMPLIEDF:
9346 fprintf (stderr, "Inserting stop\n");
9347 insn_group_break (1, 0, 0);
9354 /* Check the resources used by the given opcode against the current dependency
9357 The check is run once for each execution path encountered. In this case,
9358 a unique execution path is the sequence of instructions following a code
9359 entry point, e.g. the following has three execution paths, one starting
9360 at L0, one at L1, and one at L2.
9369 check_dependencies (idesc)
9370 struct ia64_opcode *idesc;
9372 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9376 /* Note that the number of marked resources may change within the
9377 loop if in auto mode. */
9379 while (i < regdepslen)
9381 struct rsrc *rs = ®deps[i];
9382 const struct ia64_dependency *dep = rs->dependency;
9387 if (dep->semantics == IA64_DVS_NONE
9388 || (chkind = depends_on (rs->depind, idesc)) == -1)
9394 note = NOTE (opdeps->chks[chkind]);
9396 /* Check this resource against each execution path seen thus far. */
9397 for (path = 0; path <= md.path; path++)
9401 /* If the dependency wasn't on the path being checked, ignore it. */
9402 if (rs->path < path)
9405 /* If the QP for this insn implies a QP which has branched, don't
9406 bother checking. Ed. NOTE: I don't think this check is terribly
9407 useful; what's the point of generating code which will only be
9408 reached if its QP is zero?
9409 This code was specifically inserted to handle the following code,
9410 based on notes from Intel's DV checking code, where p1 implies p2.
9416 if (CURR_SLOT.qp_regno != 0)
9420 for (implies = 0; implies < qp_implieslen; implies++)
9422 if (qp_implies[implies].path >= path
9423 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
9424 && qp_implies[implies].p2_branched)
9434 if ((matchtype = resources_match (rs, idesc, note,
9435 CURR_SLOT.qp_regno, path)) != 0)
9438 char pathmsg[256] = "";
9439 char indexmsg[256] = "";
9440 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
9443 sprintf (pathmsg, " when entry is at label '%s'",
9444 md.entry_labels[path - 1]);
9445 if (rs->specific && rs->index != 0)
9446 sprintf (indexmsg, ", specific resource number is %d",
9448 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9450 (certain ? "violates" : "may violate"),
9451 dv_mode[dep->mode], dep->name,
9452 dv_sem[dep->semantics],
9455 if (md.explicit_mode)
9457 as_warn ("%s", msg);
9459 as_warn (_("Only the first path encountering the conflict "
9461 as_warn_where (rs->file, rs->line,
9462 _("This is the location of the "
9463 "conflicting usage"));
9464 /* Don't bother checking other paths, to avoid duplicating
9471 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
9473 remove_marked_resource (rs);
9475 /* since the set of dependencies has changed, start over */
9476 /* FIXME -- since we're removing dvs as we go, we
9477 probably don't really need to start over... */
9490 /* Register new dependencies based on the given opcode. */
9493 mark_resources (idesc)
9494 struct ia64_opcode *idesc;
9497 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9498 int add_only_qp_reads = 0;
9500 /* A conditional branch only uses its resources if it is taken; if it is
9501 taken, we stop following that path. The other branch types effectively
9502 *always* write their resources. If it's not taken, register only QP
9504 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
9506 add_only_qp_reads = 1;
9510 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
9512 for (i = 0; i < opdeps->nregs; i++)
9514 const struct ia64_dependency *dep;
9515 struct rsrc specs[MAX_SPECS];
9520 dep = ia64_find_dependency (opdeps->regs[i]);
9521 note = NOTE (opdeps->regs[i]);
9523 if (add_only_qp_reads
9524 && !(dep->mode == IA64_DV_WAR
9525 && (dep->specifier == IA64_RS_PR
9526 || dep->specifier == IA64_RS_PRr
9527 || dep->specifier == IA64_RS_PR63)))
9530 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
9533 if (md.debug_dv && !count)
9534 fprintf (stderr, " No %s %s usage found (path %d)\n",
9535 dv_mode[dep->mode], dep->name, md.path);
9540 mark_resource (idesc, dep, &specs[count],
9541 DEP (opdeps->regs[i]), md.path);
9544 /* The execution path may affect register values, which may in turn
9545 affect which indirect-access resources are accessed. */
9546 switch (dep->specifier)
9558 for (path = 0; path < md.path; path++)
9560 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
9562 mark_resource (idesc, dep, &specs[count],
9563 DEP (opdeps->regs[i]), path);
9570 /* Remove dependencies when they no longer apply. */
9573 update_dependencies (idesc)
9574 struct ia64_opcode *idesc;
9578 if (strcmp (idesc->name, "srlz.i") == 0)
9580 instruction_serialization ();
9582 else if (strcmp (idesc->name, "srlz.d") == 0)
9584 data_serialization ();
9586 else if (is_interruption_or_rfi (idesc)
9587 || is_taken_branch (idesc))
9589 /* Although technically the taken branch doesn't clear dependencies
9590 which require a srlz.[id], we don't follow the branch; the next
9591 instruction is assumed to start with a clean slate. */
9595 else if (is_conditional_branch (idesc)
9596 && CURR_SLOT.qp_regno != 0)
9598 int is_call = strstr (idesc->name, ".call") != NULL;
9600 for (i = 0; i < qp_implieslen; i++)
9602 /* If the conditional branch's predicate is implied by the predicate
9603 in an existing dependency, remove that dependency. */
9604 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
9607 /* Note that this implied predicate takes a branch so that if
9608 a later insn generates a DV but its predicate implies this
9609 one, we can avoid the false DV warning. */
9610 qp_implies[i].p2_branched = 1;
9611 while (depind < regdepslen)
9613 if (regdeps[depind].qp_regno == qp_implies[i].p1)
9615 print_dependency ("Removing", depind);
9616 regdeps[depind] = regdeps[--regdepslen];
9623 /* Any marked resources which have this same predicate should be
9624 cleared, provided that the QP hasn't been modified between the
9625 marking instruction and the branch. */
9628 insn_group_break (0, CURR_SLOT.qp_regno, 1);
9633 while (i < regdepslen)
9635 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
9636 && regdeps[i].link_to_qp_branch
9637 && (regdeps[i].file != CURR_SLOT.src_file
9638 || regdeps[i].line != CURR_SLOT.src_line))
9640 /* Treat like a taken branch */
9641 print_dependency ("Removing", i);
9642 regdeps[i] = regdeps[--regdepslen];
9651 /* Examine the current instruction for dependency violations. */
9655 struct ia64_opcode *idesc;
9659 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
9660 idesc->name, CURR_SLOT.src_line,
9661 idesc->dependencies->nchks,
9662 idesc->dependencies->nregs);
9665 /* Look through the list of currently marked resources; if the current
9666 instruction has the dependency in its chks list which uses that resource,
9667 check against the specific resources used. */
9668 check_dependencies (idesc);
9670 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9671 then add them to the list of marked resources. */
9672 mark_resources (idesc);
9674 /* There are several types of dependency semantics, and each has its own
9675 requirements for being cleared
9677 Instruction serialization (insns separated by interruption, rfi, or
9678 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9680 Data serialization (instruction serialization, or writer + srlz.d +
9681 reader, where writer and srlz.d are in separate groups) clears
9682 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9683 always be the case).
9685 Instruction group break (groups separated by stop, taken branch,
9686 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9688 update_dependencies (idesc);
9690 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9691 warning. Keep track of as many as possible that are useful. */
9692 note_register_values (idesc);
9694 /* We don't need or want this anymore. */
9695 md.mem_offset.hint = 0;
9700 /* Translate one line of assembly. Pseudo ops and labels do not show
9706 char *saved_input_line_pointer, *mnemonic;
9707 const struct pseudo_opcode *pdesc;
9708 struct ia64_opcode *idesc;
9709 unsigned char qp_regno;
9713 saved_input_line_pointer = input_line_pointer;
9714 input_line_pointer = str;
9716 /* extract the opcode (mnemonic): */
9718 mnemonic = input_line_pointer;
9719 ch = get_symbol_end ();
9720 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
9723 *input_line_pointer = ch;
9724 (*pdesc->handler) (pdesc->arg);
9728 /* Find the instruction descriptor matching the arguments. */
9730 idesc = ia64_find_opcode (mnemonic);
9731 *input_line_pointer = ch;
9734 as_bad ("Unknown opcode `%s'", mnemonic);
9738 idesc = parse_operands (idesc);
9742 /* Handle the dynamic ops we can handle now: */
9743 if (idesc->type == IA64_TYPE_DYN)
9745 if (strcmp (idesc->name, "add") == 0)
9747 if (CURR_SLOT.opnd[2].X_op == O_register
9748 && CURR_SLOT.opnd[2].X_add_number < 4)
9752 ia64_free_opcode (idesc);
9753 idesc = ia64_find_opcode (mnemonic);
9755 know (!idesc->next);
9758 else if (strcmp (idesc->name, "mov") == 0)
9760 enum ia64_opnd opnd1, opnd2;
9763 opnd1 = idesc->operands[0];
9764 opnd2 = idesc->operands[1];
9765 if (opnd1 == IA64_OPND_AR3)
9767 else if (opnd2 == IA64_OPND_AR3)
9771 if (CURR_SLOT.opnd[rop].X_op == O_register
9772 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
9776 ia64_free_opcode (idesc);
9777 idesc = ia64_find_opcode (mnemonic);
9778 while (idesc != NULL
9779 && (idesc->operands[0] != opnd1
9780 || idesc->operands[1] != opnd2))
9781 idesc = get_next_opcode (idesc);
9786 if (md.qp.X_op == O_register)
9788 qp_regno = md.qp.X_add_number - REG_P;
9789 md.qp.X_op = O_absent;
9792 flags = idesc->flags;
9794 if ((flags & IA64_OPCODE_FIRST) != 0)
9795 insn_group_break (1, 0, 0);
9797 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
9799 as_bad ("`%s' cannot be predicated", idesc->name);
9803 /* Build the instruction. */
9804 CURR_SLOT.qp_regno = qp_regno;
9805 CURR_SLOT.idesc = idesc;
9806 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
9807 dwarf2_where (&CURR_SLOT.debug_line);
9809 /* Add unwind entry, if there is one. */
9810 if (unwind.current_entry)
9812 CURR_SLOT.unwind_record = unwind.current_entry;
9813 unwind.current_entry = NULL;
9816 /* Check for dependency violations. */
9820 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9821 if (++md.num_slots_in_use >= NUM_SLOTS)
9824 if ((flags & IA64_OPCODE_LAST) != 0)
9825 insn_group_break (1, 0, 0);
9827 md.last_text_seg = now_seg;
9830 input_line_pointer = saved_input_line_pointer;
9833 /* Called when symbol NAME cannot be found in the symbol table.
9834 Should be used for dynamic valued symbols only. */
9837 md_undefined_symbol (name)
9838 char *name ATTRIBUTE_UNUSED;
9843 /* Called for any expression that can not be recognized. When the
9844 function is called, `input_line_pointer' will point to the start of
9851 enum pseudo_type pseudo_type;
9856 switch (*input_line_pointer)
9859 /* Find what relocation pseudo-function we're dealing with. */
9861 ch = *++input_line_pointer;
9862 for (i = 0; i < NELEMS (pseudo_func); ++i)
9863 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
9865 len = strlen (pseudo_func[i].name);
9866 if (strncmp (pseudo_func[i].name + 1,
9867 input_line_pointer + 1, len - 1) == 0
9868 && !is_part_of_name (input_line_pointer[len]))
9870 input_line_pointer += len;
9871 pseudo_type = pseudo_func[i].type;
9875 switch (pseudo_type)
9877 case PSEUDO_FUNC_RELOC:
9879 if (*input_line_pointer != '(')
9881 as_bad ("Expected '('");
9885 ++input_line_pointer;
9887 if (*input_line_pointer++ != ')')
9889 as_bad ("Missing ')'");
9892 if (e->X_op != O_symbol)
9894 if (e->X_op != O_pseudo_fixup)
9896 as_bad ("Not a symbolic expression");
9899 if (i != FUNC_LT_RELATIVE)
9901 as_bad ("Illegal combination of relocation functions");
9904 switch (S_GET_VALUE (e->X_op_symbol))
9906 case FUNC_FPTR_RELATIVE:
9907 i = FUNC_LT_FPTR_RELATIVE; break;
9908 case FUNC_DTP_MODULE:
9909 i = FUNC_LT_DTP_MODULE; break;
9910 case FUNC_DTP_RELATIVE:
9911 i = FUNC_LT_DTP_RELATIVE; break;
9912 case FUNC_TP_RELATIVE:
9913 i = FUNC_LT_TP_RELATIVE; break;
9915 as_bad ("Illegal combination of relocation functions");
9919 /* Make sure gas doesn't get rid of local symbols that are used
9921 e->X_op = O_pseudo_fixup;
9922 e->X_op_symbol = pseudo_func[i].u.sym;
9925 case PSEUDO_FUNC_CONST:
9926 e->X_op = O_constant;
9927 e->X_add_number = pseudo_func[i].u.ival;
9930 case PSEUDO_FUNC_REG:
9931 e->X_op = O_register;
9932 e->X_add_number = pseudo_func[i].u.ival;
9936 name = input_line_pointer - 1;
9938 as_bad ("Unknown pseudo function `%s'", name);
9944 ++input_line_pointer;
9946 if (*input_line_pointer != ']')
9948 as_bad ("Closing bracket misssing");
9953 if (e->X_op != O_register)
9954 as_bad ("Register expected as index");
9956 ++input_line_pointer;
9967 ignore_rest_of_line ();
9970 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9971 a section symbol plus some offset. For relocs involving @fptr(),
9972 directives we don't want such adjustments since we need to have the
9973 original symbol's name in the reloc. */
9975 ia64_fix_adjustable (fix)
9978 /* Prevent all adjustments to global symbols */
9979 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
9982 switch (fix->fx_r_type)
9984 case BFD_RELOC_IA64_FPTR64I:
9985 case BFD_RELOC_IA64_FPTR32MSB:
9986 case BFD_RELOC_IA64_FPTR32LSB:
9987 case BFD_RELOC_IA64_FPTR64MSB:
9988 case BFD_RELOC_IA64_FPTR64LSB:
9989 case BFD_RELOC_IA64_LTOFF_FPTR22:
9990 case BFD_RELOC_IA64_LTOFF_FPTR64I:
10000 ia64_force_relocation (fix)
10003 switch (fix->fx_r_type)
10005 case BFD_RELOC_IA64_FPTR64I:
10006 case BFD_RELOC_IA64_FPTR32MSB:
10007 case BFD_RELOC_IA64_FPTR32LSB:
10008 case BFD_RELOC_IA64_FPTR64MSB:
10009 case BFD_RELOC_IA64_FPTR64LSB:
10011 case BFD_RELOC_IA64_LTOFF22:
10012 case BFD_RELOC_IA64_LTOFF64I:
10013 case BFD_RELOC_IA64_LTOFF_FPTR22:
10014 case BFD_RELOC_IA64_LTOFF_FPTR64I:
10015 case BFD_RELOC_IA64_PLTOFF22:
10016 case BFD_RELOC_IA64_PLTOFF64I:
10017 case BFD_RELOC_IA64_PLTOFF64MSB:
10018 case BFD_RELOC_IA64_PLTOFF64LSB:
10020 case BFD_RELOC_IA64_LTOFF22X:
10021 case BFD_RELOC_IA64_LDXMOV:
10028 return generic_force_reloc (fix);
10031 /* Decide from what point a pc-relative relocation is relative to,
10032 relative to the pc-relative fixup. Er, relatively speaking. */
10034 ia64_pcrel_from_section (fix, sec)
10038 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
10040 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
10047 /* Used to emit section-relative relocs for the dwarf2 debug data. */
10049 ia64_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10053 expr.X_op = O_pseudo_fixup;
10054 expr.X_op_symbol = pseudo_func[FUNC_SEC_RELATIVE].u.sym;
10055 expr.X_add_number = 0;
10056 expr.X_add_symbol = symbol;
10057 emit_expr (&expr, size);
10060 /* This is called whenever some data item (not an instruction) needs a
10061 fixup. We pick the right reloc code depending on the byteorder
10062 currently in effect. */
10064 ia64_cons_fix_new (f, where, nbytes, exp)
10070 bfd_reloc_code_real_type code;
10075 /* There are no reloc for 8 and 16 bit quantities, but we allow
10076 them here since they will work fine as long as the expression
10077 is fully defined at the end of the pass over the source file. */
10078 case 1: code = BFD_RELOC_8; break;
10079 case 2: code = BFD_RELOC_16; break;
10081 if (target_big_endian)
10082 code = BFD_RELOC_IA64_DIR32MSB;
10084 code = BFD_RELOC_IA64_DIR32LSB;
10088 /* In 32-bit mode, data8 could mean function descriptors too. */
10089 if (exp->X_op == O_pseudo_fixup
10090 && exp->X_op_symbol
10091 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC
10092 && !(md.flags & EF_IA_64_ABI64))
10094 if (target_big_endian)
10095 code = BFD_RELOC_IA64_IPLTMSB;
10097 code = BFD_RELOC_IA64_IPLTLSB;
10098 exp->X_op = O_symbol;
10103 if (target_big_endian)
10104 code = BFD_RELOC_IA64_DIR64MSB;
10106 code = BFD_RELOC_IA64_DIR64LSB;
10111 if (exp->X_op == O_pseudo_fixup
10112 && exp->X_op_symbol
10113 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC)
10115 if (target_big_endian)
10116 code = BFD_RELOC_IA64_IPLTMSB;
10118 code = BFD_RELOC_IA64_IPLTLSB;
10119 exp->X_op = O_symbol;
10125 as_bad ("Unsupported fixup size %d", nbytes);
10126 ignore_rest_of_line ();
10130 if (exp->X_op == O_pseudo_fixup)
10132 exp->X_op = O_symbol;
10133 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
10134 /* ??? If code unchanged, unsupported. */
10137 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
10138 /* We need to store the byte order in effect in case we're going
10139 to fix an 8 or 16 bit relocation (for which there no real
10140 relocs available). See md_apply_fix3(). */
10141 fix->tc_fix_data.bigendian = target_big_endian;
10144 /* Return the actual relocation we wish to associate with the pseudo
10145 reloc described by SYM and R_TYPE. SYM should be one of the
10146 symbols in the pseudo_func array, or NULL. */
10148 static bfd_reloc_code_real_type
10149 ia64_gen_real_reloc_type (sym, r_type)
10150 struct symbol *sym;
10151 bfd_reloc_code_real_type r_type;
10153 bfd_reloc_code_real_type new = 0;
10160 switch (S_GET_VALUE (sym))
10162 case FUNC_FPTR_RELATIVE:
10165 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
10166 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
10167 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
10168 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
10169 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
10174 case FUNC_GP_RELATIVE:
10177 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
10178 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
10179 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
10180 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
10181 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
10182 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
10187 case FUNC_LT_RELATIVE:
10190 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
10191 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
10196 case FUNC_LT_RELATIVE_X:
10199 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22X; break;
10204 case FUNC_PC_RELATIVE:
10207 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
10208 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
10209 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
10210 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
10211 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
10212 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
10217 case FUNC_PLT_RELATIVE:
10220 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
10221 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
10222 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
10223 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
10228 case FUNC_SEC_RELATIVE:
10231 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
10232 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
10233 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
10234 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
10239 case FUNC_SEG_RELATIVE:
10242 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
10243 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
10244 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
10245 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
10250 case FUNC_LTV_RELATIVE:
10253 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
10254 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
10255 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
10256 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
10261 case FUNC_LT_FPTR_RELATIVE:
10264 case BFD_RELOC_IA64_IMM22:
10265 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
10266 case BFD_RELOC_IA64_IMM64:
10267 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
10273 case FUNC_TP_RELATIVE:
10276 case BFD_RELOC_IA64_IMM14:
10277 new = BFD_RELOC_IA64_TPREL14; break;
10278 case BFD_RELOC_IA64_IMM22:
10279 new = BFD_RELOC_IA64_TPREL22; break;
10280 case BFD_RELOC_IA64_IMM64:
10281 new = BFD_RELOC_IA64_TPREL64I; break;
10287 case FUNC_LT_TP_RELATIVE:
10290 case BFD_RELOC_IA64_IMM22:
10291 new = BFD_RELOC_IA64_LTOFF_TPREL22; break;
10297 case FUNC_LT_DTP_MODULE:
10300 case BFD_RELOC_IA64_IMM22:
10301 new = BFD_RELOC_IA64_LTOFF_DTPMOD22; break;
10307 case FUNC_DTP_RELATIVE:
10310 case BFD_RELOC_IA64_DIR64MSB:
10311 new = BFD_RELOC_IA64_DTPREL64MSB; break;
10312 case BFD_RELOC_IA64_DIR64LSB:
10313 new = BFD_RELOC_IA64_DTPREL64LSB; break;
10314 case BFD_RELOC_IA64_IMM14:
10315 new = BFD_RELOC_IA64_DTPREL14; break;
10316 case BFD_RELOC_IA64_IMM22:
10317 new = BFD_RELOC_IA64_DTPREL22; break;
10318 case BFD_RELOC_IA64_IMM64:
10319 new = BFD_RELOC_IA64_DTPREL64I; break;
10325 case FUNC_LT_DTP_RELATIVE:
10328 case BFD_RELOC_IA64_IMM22:
10329 new = BFD_RELOC_IA64_LTOFF_DTPREL22; break;
10335 case FUNC_IPLT_RELOC:
10342 /* Hmmmm. Should this ever occur? */
10349 /* Here is where generate the appropriate reloc for pseudo relocation
10352 ia64_validate_fix (fix)
10355 switch (fix->fx_r_type)
10357 case BFD_RELOC_IA64_FPTR64I:
10358 case BFD_RELOC_IA64_FPTR32MSB:
10359 case BFD_RELOC_IA64_FPTR64LSB:
10360 case BFD_RELOC_IA64_LTOFF_FPTR22:
10361 case BFD_RELOC_IA64_LTOFF_FPTR64I:
10362 if (fix->fx_offset != 0)
10363 as_bad_where (fix->fx_file, fix->fx_line,
10364 "No addend allowed in @fptr() relocation");
10374 fix_insn (fix, odesc, value)
10376 const struct ia64_operand *odesc;
10379 bfd_vma insn[3], t0, t1, control_bits;
10384 slot = fix->fx_where & 0x3;
10385 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
10387 /* Bundles are always in little-endian byte order */
10388 t0 = bfd_getl64 (fixpos);
10389 t1 = bfd_getl64 (fixpos + 8);
10390 control_bits = t0 & 0x1f;
10391 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
10392 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
10393 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
10396 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
10398 insn[1] = (value >> 22) & 0x1ffffffffffLL;
10399 insn[2] |= (((value & 0x7f) << 13)
10400 | (((value >> 7) & 0x1ff) << 27)
10401 | (((value >> 16) & 0x1f) << 22)
10402 | (((value >> 21) & 0x1) << 21)
10403 | (((value >> 63) & 0x1) << 36));
10405 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
10407 if (value & ~0x3fffffffffffffffULL)
10408 err = "integer operand out of range";
10409 insn[1] = (value >> 21) & 0x1ffffffffffLL;
10410 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
10412 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
10415 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
10416 insn[2] |= ((((value >> 59) & 0x1) << 36)
10417 | (((value >> 0) & 0xfffff) << 13));
10420 err = (*odesc->insert) (odesc, value, insn + slot);
10423 as_bad_where (fix->fx_file, fix->fx_line, err);
10425 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
10426 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
10427 number_to_chars_littleendian (fixpos + 0, t0, 8);
10428 number_to_chars_littleendian (fixpos + 8, t1, 8);
10431 /* Attempt to simplify or even eliminate a fixup. The return value is
10432 ignored; perhaps it was once meaningful, but now it is historical.
10433 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10435 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
10439 md_apply_fix3 (fix, valP, seg)
10442 segT seg ATTRIBUTE_UNUSED;
10445 valueT value = *valP;
10447 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
10451 switch (fix->fx_r_type)
10453 case BFD_RELOC_IA64_DIR32MSB:
10454 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
10457 case BFD_RELOC_IA64_DIR32LSB:
10458 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
10461 case BFD_RELOC_IA64_DIR64MSB:
10462 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
10465 case BFD_RELOC_IA64_DIR64LSB:
10466 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
10475 switch (fix->fx_r_type)
10477 case BFD_RELOC_UNUSED:
10478 /* This must be a TAG13 or TAG13b operand. There are no external
10479 relocs defined for them, so we must give an error. */
10480 as_bad_where (fix->fx_file, fix->fx_line,
10481 "%s must have a constant value",
10482 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
10486 case BFD_RELOC_IA64_TPREL14:
10487 case BFD_RELOC_IA64_TPREL22:
10488 case BFD_RELOC_IA64_TPREL64I:
10489 case BFD_RELOC_IA64_LTOFF_TPREL22:
10490 case BFD_RELOC_IA64_LTOFF_DTPMOD22:
10491 case BFD_RELOC_IA64_DTPREL14:
10492 case BFD_RELOC_IA64_DTPREL22:
10493 case BFD_RELOC_IA64_DTPREL64I:
10494 case BFD_RELOC_IA64_LTOFF_DTPREL22:
10495 S_SET_THREAD_LOCAL (fix->fx_addsy);
10502 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
10504 if (fix->tc_fix_data.bigendian)
10505 number_to_chars_bigendian (fixpos, value, fix->fx_size);
10507 number_to_chars_littleendian (fixpos, value, fix->fx_size);
10512 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
10517 /* Generate the BFD reloc to be stuck in the object file from the
10518 fixup used internally in the assembler. */
10521 tc_gen_reloc (sec, fixp)
10522 asection *sec ATTRIBUTE_UNUSED;
10527 reloc = xmalloc (sizeof (*reloc));
10528 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10529 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10530 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
10531 reloc->addend = fixp->fx_offset;
10532 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
10536 as_bad_where (fixp->fx_file, fixp->fx_line,
10537 "Cannot represent %s relocation in object file",
10538 bfd_get_reloc_code_name (fixp->fx_r_type));
10543 /* Turn a string in input_line_pointer into a floating point constant
10544 of type TYPE, and store the appropriate bytes in *LIT. The number
10545 of LITTLENUMS emitted is stored in *SIZE. An error message is
10546 returned, or NULL on OK. */
10548 #define MAX_LITTLENUMS 5
10551 md_atof (type, lit, size)
10556 LITTLENUM_TYPE words[MAX_LITTLENUMS];
10557 LITTLENUM_TYPE *word;
10587 return "Bad call to MD_ATOF()";
10589 t = atof_ieee (input_line_pointer, type, words);
10591 input_line_pointer = t;
10592 *size = prec * sizeof (LITTLENUM_TYPE);
10594 for (word = words + prec - 1; prec--;)
10596 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
10597 lit += sizeof (LITTLENUM_TYPE);
10601 /* It is 10 byte floating point with 6 byte padding. */
10602 memset (lit, 0, 6);
10603 *size = 8 * sizeof (LITTLENUM_TYPE);
10608 /* Handle ia64 specific semantics of the align directive. */
10611 ia64_md_do_align (n, fill, len, max)
10612 int n ATTRIBUTE_UNUSED;
10613 const char *fill ATTRIBUTE_UNUSED;
10614 int len ATTRIBUTE_UNUSED;
10615 int max ATTRIBUTE_UNUSED;
10617 if (subseg_text_p (now_seg))
10618 ia64_flush_insns ();
10621 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10622 of an rs_align_code fragment. */
10625 ia64_handle_align (fragp)
10628 /* Use mfi bundle of nops with no stop bits. */
10629 static const unsigned char be_nop[]
10630 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10631 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10632 static const unsigned char le_nop[]
10633 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10634 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10639 if (fragp->fr_type != rs_align_code)
10642 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
10643 p = fragp->fr_literal + fragp->fr_fix;
10645 /* Make sure we are on a 16-byte boundary, in case someone has been
10646 putting data into a text section. */
10649 int fix = bytes & 15;
10650 memset (p, 0, fix);
10653 fragp->fr_fix += fix;
10656 memcpy (p, (target_big_endian ? be_nop : le_nop), 16);
10657 fragp->fr_var = 16;