1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS = 0,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
127 enum operand_match_result
130 OPERAND_OUT_OF_RANGE,
134 /* On the ia64, we can't know the address of a text label until the
135 instructions are packed into a bundle. To handle this, we keep
136 track of the list of labels that appear in front of each
140 struct label_fix *next;
144 extern int target_big_endian;
146 /* Characters which always start a comment. */
147 const char comment_chars[] = "";
149 /* Characters which start a comment at the beginning of a line. */
150 const char line_comment_chars[] = "#";
152 /* Characters which may be used to separate multiple commands on a
154 const char line_separator_chars[] = ";";
156 /* Characters which are used to indicate an exponent in a floating
158 const char EXP_CHARS[] = "eE";
160 /* Characters which mean that a number is a floating point constant,
162 const char FLT_CHARS[] = "rRsSfFdDxXpP";
164 /* ia64-specific option processing: */
166 const char *md_shortopts = "m:N:x::";
168 struct option md_longopts[] =
170 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
171 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
172 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
173 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
176 size_t md_longopts_size = sizeof (md_longopts);
180 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
181 struct hash_control *reg_hash; /* register name hash table */
182 struct hash_control *dynreg_hash; /* dynamic register hash table */
183 struct hash_control *const_hash; /* constant hash table */
184 struct hash_control *entry_hash; /* code entry hint hash table */
186 symbolS *regsym[REG_NUM];
188 /* If X_op is != O_absent, the registername for the instruction's
189 qualifying predicate. If NULL, p0 is assumed for instructions
190 that are predicatable. */
197 explicit_mode : 1, /* which mode we're in */
198 default_explicit_mode : 1, /* which mode is the default */
199 mode_explicitly_set : 1, /* was the current mode explicitly set? */
201 keep_pending_output : 1;
203 /* Each bundle consists of up to three instructions. We keep
204 track of four most recent instructions so we can correctly set
205 the end_of_insn_group for the last instruction in a bundle. */
207 int num_slots_in_use;
211 end_of_insn_group : 1,
212 manual_bundling_on : 1,
213 manual_bundling_off : 1;
214 signed char user_template; /* user-selected template, if any */
215 unsigned char qp_regno; /* qualifying predicate */
216 /* This duplicates a good fraction of "struct fix" but we
217 can't use a "struct fix" instead since we can't call
218 fix_new_exp() until we know the address of the instruction. */
222 bfd_reloc_code_real_type code;
223 enum ia64_opnd opnd; /* type of operand in need of fix */
224 unsigned int is_pcrel : 1; /* is operand pc-relative? */
225 expressionS expr; /* the value to be inserted */
227 fixup[2]; /* at most two fixups per insn */
228 struct ia64_opcode *idesc;
229 struct label_fix *label_fixups;
230 struct label_fix *tag_fixups;
231 struct unw_rec_list *unwind_record; /* Unwind directive. */
234 unsigned int src_line;
235 struct dwarf2_line_info debug_line;
243 struct dynreg *next; /* next dynamic register */
245 unsigned short base; /* the base register number */
246 unsigned short num_regs; /* # of registers in this set */
248 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
250 flagword flags; /* ELF-header flags */
253 unsigned hint:1; /* is this hint currently valid? */
254 bfd_vma offset; /* mem.offset offset */
255 bfd_vma base; /* mem.offset base */
258 int path; /* number of alt. entry points seen */
259 const char **entry_labels; /* labels of all alternate paths in
260 the current DV-checking block. */
261 int maxpaths; /* size currently allocated for
263 /* Support for hardware errata workarounds. */
265 /* Record data about the last three insn groups. */
268 /* B-step workaround.
269 For each predicate register, this is set if the corresponding insn
270 group conditionally sets this register with one of the affected
273 /* B-step workaround.
274 For each general register, this is set if the corresponding insn
275 a) is conditional one one of the predicate registers for which
276 P_REG_SET is 1 in the corresponding entry of the previous group,
277 b) sets this general register with one of the affected
279 int g_reg_set_conditionally[128];
285 /* application registers: */
291 #define AR_BSPSTORE 18
306 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
307 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
308 {"ar.rsc", 16}, {"ar.bsp", 17},
309 {"ar.bspstore", 18}, {"ar.rnat", 19},
310 {"ar.fcr", 21}, {"ar.eflag", 24},
311 {"ar.csd", 25}, {"ar.ssd", 26},
312 {"ar.cflg", 27}, {"ar.fsr", 28},
313 {"ar.fir", 29}, {"ar.fdr", 30},
314 {"ar.ccv", 32}, {"ar.unat", 36},
315 {"ar.fpsr", 40}, {"ar.itc", 44},
316 {"ar.pfs", 64}, {"ar.lc", 65},
337 /* control registers: */
379 static const struct const_desc
386 /* PSR constant masks: */
389 {"psr.be", ((valueT) 1) << 1},
390 {"psr.up", ((valueT) 1) << 2},
391 {"psr.ac", ((valueT) 1) << 3},
392 {"psr.mfl", ((valueT) 1) << 4},
393 {"psr.mfh", ((valueT) 1) << 5},
395 {"psr.ic", ((valueT) 1) << 13},
396 {"psr.i", ((valueT) 1) << 14},
397 {"psr.pk", ((valueT) 1) << 15},
399 {"psr.dt", ((valueT) 1) << 17},
400 {"psr.dfl", ((valueT) 1) << 18},
401 {"psr.dfh", ((valueT) 1) << 19},
402 {"psr.sp", ((valueT) 1) << 20},
403 {"psr.pp", ((valueT) 1) << 21},
404 {"psr.di", ((valueT) 1) << 22},
405 {"psr.si", ((valueT) 1) << 23},
406 {"psr.db", ((valueT) 1) << 24},
407 {"psr.lp", ((valueT) 1) << 25},
408 {"psr.tb", ((valueT) 1) << 26},
409 {"psr.rt", ((valueT) 1) << 27},
410 /* 28-31: reserved */
411 /* 32-33: cpl (current privilege level) */
412 {"psr.is", ((valueT) 1) << 34},
413 {"psr.mc", ((valueT) 1) << 35},
414 {"psr.it", ((valueT) 1) << 36},
415 {"psr.id", ((valueT) 1) << 37},
416 {"psr.da", ((valueT) 1) << 38},
417 {"psr.dd", ((valueT) 1) << 39},
418 {"psr.ss", ((valueT) 1) << 40},
419 /* 41-42: ri (restart instruction) */
420 {"psr.ed", ((valueT) 1) << 43},
421 {"psr.bn", ((valueT) 1) << 44},
424 /* indirect register-sets/memory: */
433 { "CPUID", IND_CPUID },
434 { "cpuid", IND_CPUID },
446 /* Pseudo functions used to indicate relocation types (these functions
447 start with an at sign (@). */
469 /* reloc pseudo functions (these must come first!): */
470 { "fptr", PSEUDO_FUNC_RELOC, { 0 } },
471 { "gprel", PSEUDO_FUNC_RELOC, { 0 } },
472 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } },
473 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } },
474 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } },
475 { "secrel", PSEUDO_FUNC_RELOC, { 0 } },
476 { "segrel", PSEUDO_FUNC_RELOC, { 0 } },
477 { "ltv", PSEUDO_FUNC_RELOC, { 0 } },
478 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
480 /* mbtype4 constants: */
481 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
482 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
483 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
484 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
485 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
487 /* fclass constants: */
488 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
489 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
490 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
491 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
492 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
493 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
494 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
495 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
496 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
498 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
500 /* unwind-related constants: */
501 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
502 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
503 { "nt", PSEUDO_FUNC_CONST, { 2 } },
505 /* unwind-related registers: */
506 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
509 /* 41-bit nop opcodes (one per unit): */
510 static const bfd_vma nop[IA64_NUM_UNITS] =
512 0x0000000000LL, /* NIL => break 0 */
513 0x0008000000LL, /* I-unit nop */
514 0x0008000000LL, /* M-unit nop */
515 0x4000000000LL, /* B-unit nop */
516 0x0008000000LL, /* F-unit nop */
517 0x0008000000LL, /* L-"unit" nop */
518 0x0008000000LL, /* X-unit nop */
521 /* Can't be `const' as it's passed to input routines (which have the
522 habit of setting temporary sentinels. */
523 static char special_section_name[][20] =
525 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
526 {".IA_64.unwind"}, {".IA_64.unwind_info"}
529 static char *special_linkonce_name[] =
531 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
534 /* The best template for a particular sequence of up to three
536 #define N IA64_NUM_TYPES
537 static unsigned char best_template[N][N][N];
540 /* Resource dependencies currently in effect */
542 int depind; /* dependency index */
543 const struct ia64_dependency *dependency; /* actual dependency */
544 unsigned specific:1, /* is this a specific bit/regno? */
545 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
546 int index; /* specific regno/bit within dependency */
547 int note; /* optional qualifying note (0 if none) */
551 int insn_srlz; /* current insn serialization state */
552 int data_srlz; /* current data serialization state */
553 int qp_regno; /* qualifying predicate for this usage */
554 char *file; /* what file marked this dependency */
555 unsigned int line; /* what line marked this dependency */
556 struct mem_offset mem_offset; /* optional memory offset hint */
557 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
558 int path; /* corresponding code entry index */
560 static int regdepslen = 0;
561 static int regdepstotlen = 0;
562 static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
563 static const char *dv_sem[] = { "none", "implied", "impliedf",
564 "data", "instr", "specific", "stop", "other" };
565 static const char *dv_cmp_type[] = { "none", "OR", "AND" };
567 /* Current state of PR mutexation */
568 static struct qpmutex {
571 } *qp_mutexes = NULL; /* QP mutex bitmasks */
572 static int qp_mutexeslen = 0;
573 static int qp_mutexestotlen = 0;
574 static valueT qp_safe_across_calls = 0;
576 /* Current state of PR implications */
577 static struct qp_imply {
580 unsigned p2_branched:1;
582 } *qp_implies = NULL;
583 static int qp_implieslen = 0;
584 static int qp_impliestotlen = 0;
586 /* Keep track of static GR values so that indirect register usage can
587 sometimes be tracked. */
592 } gr_values[128] = {{ 1, 0, 0 }};
594 /* These are the routines required to output the various types of
597 /* A slot_number is a frag address plus the slot index (0-2). We use the
598 frag address here so that if there is a section switch in the middle of
599 a function, then instructions emitted to a different section are not
600 counted. Since there may be more than one frag for a function, this
601 means we also need to keep track of which frag this address belongs to
602 so we can compute inter-frag distances. This also nicely solves the
603 problem with nops emitted for align directives, which can't easily be
604 counted, but can easily be derived from frag sizes. */
606 typedef struct unw_rec_list {
608 unsigned long slot_number;
610 struct unw_rec_list *next;
613 #define SLOT_NUM_NOT_SET (unsigned)-1
617 unsigned long next_slot_number;
618 fragS *next_slot_frag;
620 /* Maintain a list of unwind entries for the current function. */
624 /* Any unwind entires that should be attached to the current slot
625 that an insn is being constructed for. */
626 unw_rec_list *current_entry;
628 /* These are used to create the unwind table entry for this function. */
631 symbolS *info; /* pointer to unwind info */
632 symbolS *personality_routine;
634 subsegT saved_text_subseg;
635 unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */
637 /* TRUE if processing unwind directives in a prologue region. */
640 unsigned int prologue_count; /* number of .prologues seen so far */
643 typedef void (*vbyte_func) PARAMS ((int, char *, char *));
645 /* Forward delarations: */
646 static int ar_is_in_integer_unit PARAMS ((int regnum));
647 static void set_section PARAMS ((char *name));
648 static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
649 unsigned int, unsigned int));
650 static void dot_radix PARAMS ((int));
651 static void dot_special_section PARAMS ((int));
652 static void dot_proc PARAMS ((int));
653 static void dot_fframe PARAMS ((int));
654 static void dot_vframe PARAMS ((int));
655 static void dot_vframesp PARAMS ((int));
656 static void dot_vframepsp PARAMS ((int));
657 static void dot_save PARAMS ((int));
658 static void dot_restore PARAMS ((int));
659 static void dot_restorereg PARAMS ((int));
660 static void dot_restorereg_p PARAMS ((int));
661 static void dot_handlerdata PARAMS ((int));
662 static void dot_unwentry PARAMS ((int));
663 static void dot_altrp PARAMS ((int));
664 static void dot_savemem PARAMS ((int));
665 static void dot_saveg PARAMS ((int));
666 static void dot_savef PARAMS ((int));
667 static void dot_saveb PARAMS ((int));
668 static void dot_savegf PARAMS ((int));
669 static void dot_spill PARAMS ((int));
670 static void dot_spillreg PARAMS ((int));
671 static void dot_spillmem PARAMS ((int));
672 static void dot_spillreg_p PARAMS ((int));
673 static void dot_spillmem_p PARAMS ((int));
674 static void dot_label_state PARAMS ((int));
675 static void dot_copy_state PARAMS ((int));
676 static void dot_unwabi PARAMS ((int));
677 static void dot_personality PARAMS ((int));
678 static void dot_body PARAMS ((int));
679 static void dot_prologue PARAMS ((int));
680 static void dot_endp PARAMS ((int));
681 static void dot_template PARAMS ((int));
682 static void dot_regstk PARAMS ((int));
683 static void dot_rot PARAMS ((int));
684 static void dot_byteorder PARAMS ((int));
685 static void dot_psr PARAMS ((int));
686 static void dot_alias PARAMS ((int));
687 static void dot_ln PARAMS ((int));
688 static char *parse_section_name PARAMS ((void));
689 static void dot_xdata PARAMS ((int));
690 static void stmt_float_cons PARAMS ((int));
691 static void stmt_cons_ua PARAMS ((int));
692 static void dot_xfloat_cons PARAMS ((int));
693 static void dot_xstringer PARAMS ((int));
694 static void dot_xdata_ua PARAMS ((int));
695 static void dot_xfloat_cons_ua PARAMS ((int));
696 static void print_prmask PARAMS ((valueT mask));
697 static void dot_pred_rel PARAMS ((int));
698 static void dot_reg_val PARAMS ((int));
699 static void dot_dv_mode PARAMS ((int));
700 static void dot_entry PARAMS ((int));
701 static void dot_mem_offset PARAMS ((int));
702 static void add_unwind_entry PARAMS((unw_rec_list *ptr));
703 static symbolS *declare_register PARAMS ((const char *name, int regnum));
704 static void declare_register_set PARAMS ((const char *, int, int));
705 static unsigned int operand_width PARAMS ((enum ia64_opnd));
706 static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc,
709 static int parse_operand PARAMS ((expressionS *e));
710 static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
711 static void build_insn PARAMS ((struct slot *, bfd_vma *));
712 static void emit_one_bundle PARAMS ((void));
713 static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
714 static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
715 bfd_reloc_code_real_type r_type));
716 static void insn_group_break PARAMS ((int, int, int));
717 static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
718 struct rsrc *, int depind, int path));
719 static void add_qp_mutex PARAMS((valueT mask));
720 static void add_qp_imply PARAMS((int p1, int p2));
721 static void clear_qp_branch_flag PARAMS((valueT mask));
722 static void clear_qp_mutex PARAMS((valueT mask));
723 static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
724 static void clear_register_values PARAMS ((void));
725 static void print_dependency PARAMS ((const char *action, int depind));
726 static void instruction_serialization PARAMS ((void));
727 static void data_serialization PARAMS ((void));
728 static void remove_marked_resource PARAMS ((struct rsrc *));
729 static int is_conditional_branch PARAMS ((struct ia64_opcode *));
730 static int is_taken_branch PARAMS ((struct ia64_opcode *));
731 static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
732 static int depends_on PARAMS ((int, struct ia64_opcode *));
733 static int specify_resource PARAMS ((const struct ia64_dependency *,
734 struct ia64_opcode *, int, struct rsrc [], int, int));
735 static int check_dv PARAMS((struct ia64_opcode *idesc));
736 static void check_dependencies PARAMS((struct ia64_opcode *));
737 static void mark_resources PARAMS((struct ia64_opcode *));
738 static void update_dependencies PARAMS((struct ia64_opcode *));
739 static void note_register_values PARAMS((struct ia64_opcode *));
740 static int qp_mutex PARAMS ((int, int, int));
741 static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
742 static void output_vbyte_mem PARAMS ((int, char *, char *));
743 static void count_output PARAMS ((int, char *, char *));
744 static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
745 static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
746 static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
747 static void output_P1_format PARAMS ((vbyte_func, int));
748 static void output_P2_format PARAMS ((vbyte_func, int, int));
749 static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
750 static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
751 static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
752 static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
753 static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
754 static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
755 static void output_P9_format PARAMS ((vbyte_func, int, int));
756 static void output_P10_format PARAMS ((vbyte_func, int, int));
757 static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
758 static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
759 static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
760 static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
761 static char format_ab_reg PARAMS ((int, int));
762 static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
764 static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
765 static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
767 static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
768 static void free_list_records PARAMS ((unw_rec_list *));
769 static unw_rec_list *output_prologue PARAMS ((void));
770 static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
771 static unw_rec_list *output_body PARAMS ((void));
772 static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
773 static unw_rec_list *output_mem_stack_v PARAMS ((void));
774 static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
775 static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
776 static unw_rec_list *output_rp_when PARAMS ((void));
777 static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
778 static unw_rec_list *output_rp_br PARAMS ((unsigned int));
779 static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
780 static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
781 static unw_rec_list *output_pfs_when PARAMS ((void));
782 static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
783 static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
784 static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
785 static unw_rec_list *output_preds_when PARAMS ((void));
786 static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
787 static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
788 static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
789 static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
790 static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
791 static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
792 static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
793 static unw_rec_list *output_br_mem PARAMS ((unsigned int));
794 static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
795 static unw_rec_list *output_spill_base PARAMS ((unsigned int));
796 static unw_rec_list *output_unat_when PARAMS ((void));
797 static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
798 static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
799 static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
800 static unw_rec_list *output_lc_when PARAMS ((void));
801 static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
802 static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
803 static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
804 static unw_rec_list *output_fpsr_when PARAMS ((void));
805 static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
806 static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
807 static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
808 static unw_rec_list *output_priunat_when_gr PARAMS ((void));
809 static unw_rec_list *output_priunat_when_mem PARAMS ((void));
810 static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
811 static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
812 static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
813 static unw_rec_list *output_bsp_when PARAMS ((void));
814 static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
815 static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
816 static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
817 static unw_rec_list *output_bspstore_when PARAMS ((void));
818 static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
819 static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
820 static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
821 static unw_rec_list *output_rnat_when PARAMS ((void));
822 static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
823 static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
824 static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
825 static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
826 static unw_rec_list *output_epilogue PARAMS ((unsigned long));
827 static unw_rec_list *output_label_state PARAMS ((unsigned long));
828 static unw_rec_list *output_copy_state PARAMS ((unsigned long));
829 static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
830 static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
831 static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
833 static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
835 static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
837 static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
838 unsigned int, unsigned int));
839 static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
840 static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
841 static int calc_record_size PARAMS ((unw_rec_list *));
842 static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
843 static int count_bits PARAMS ((unsigned long));
844 static unsigned long slot_index PARAMS ((unsigned long, fragS *,
845 unsigned long, fragS *));
846 static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *));
847 static void fixup_unw_records PARAMS ((unw_rec_list *));
848 static int output_unw_records PARAMS ((unw_rec_list *, void **));
849 static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
850 static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
851 static int generate_unwind_image PARAMS ((const char *));
853 /* Build the unwind section name by appending the (possibly stripped)
854 text section NAME to the unwind PREFIX. The resulting string
855 pointer is assigned to RESULT. The string is allocated on the
856 stack, so this must be a macro... */
857 #define make_unw_section_name(special, text_name, result) \
859 char *_prefix = special_section_name[special]; \
860 char *_suffix = text_name; \
861 size_t _prefix_len, _suffix_len; \
863 if (strncmp (text_name, ".gnu.linkonce.t.", \
864 sizeof (".gnu.linkonce.t.") - 1) == 0) \
866 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
867 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
869 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
870 _result = alloca (_prefix_len + _suffix_len + 1); \
871 memcpy(_result, _prefix, _prefix_len); \
872 memcpy(_result + _prefix_len, _suffix, _suffix_len); \
873 _result[_prefix_len + _suffix_len] = '\0'; \
878 /* Determine if application register REGNUM resides in the integer
879 unit (as opposed to the memory unit). */
881 ar_is_in_integer_unit (reg)
886 return (reg == 64 /* pfs */
887 || reg == 65 /* lc */
888 || reg == 66 /* ec */
889 /* ??? ias accepts and puts these in the integer unit. */
890 || (reg >= 112 && reg <= 127));
893 /* Switch to section NAME and create section if necessary. It's
894 rather ugly that we have to manipulate input_line_pointer but I
895 don't see any other way to accomplish the same thing without
896 changing obj-elf.c (which may be the Right Thing, in the end). */
901 char *saved_input_line_pointer;
903 saved_input_line_pointer = input_line_pointer;
904 input_line_pointer = name;
906 input_line_pointer = saved_input_line_pointer;
909 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
912 ia64_elf_section_flags (flags, attr, type)
914 int attr, type ATTRIBUTE_UNUSED;
916 if (attr & SHF_IA_64_SHORT)
917 flags |= SEC_SMALL_DATA;
922 ia64_elf_section_type (str, len)
926 len = sizeof (ELF_STRING_ia64_unwind_info) - 1;
927 if (strncmp (str, ELF_STRING_ia64_unwind_info, len) == 0)
930 len = sizeof (ELF_STRING_ia64_unwind_info_once) - 1;
931 if (strncmp (str, ELF_STRING_ia64_unwind_info_once, len) == 0)
934 len = sizeof (ELF_STRING_ia64_unwind) - 1;
935 if (strncmp (str, ELF_STRING_ia64_unwind, len) == 0)
936 return SHT_IA_64_UNWIND;
938 len = sizeof (ELF_STRING_ia64_unwind_once) - 1;
939 if (strncmp (str, ELF_STRING_ia64_unwind_once, len) == 0)
940 return SHT_IA_64_UNWIND;
946 set_regstack (ins, locs, outs, rots)
947 unsigned int ins, locs, outs, rots;
952 sof = ins + locs + outs;
955 as_bad ("Size of frame exceeds maximum of 96 registers");
960 as_warn ("Size of rotating registers exceeds frame size");
963 md.in.base = REG_GR + 32;
964 md.loc.base = md.in.base + ins;
965 md.out.base = md.loc.base + locs;
967 md.in.num_regs = ins;
968 md.loc.num_regs = locs;
969 md.out.num_regs = outs;
970 md.rot.num_regs = rots;
977 struct label_fix *lfix;
979 subsegT saved_subseg;
982 if (!md.last_text_seg)
986 saved_subseg = now_subseg;
988 subseg_set (md.last_text_seg, 0);
990 while (md.num_slots_in_use > 0)
991 emit_one_bundle (); /* force out queued instructions */
993 /* In case there are labels following the last instruction, resolve
995 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
997 S_SET_VALUE (lfix->sym, frag_now_fix ());
998 symbol_set_frag (lfix->sym, frag_now);
1000 CURR_SLOT.label_fixups = 0;
1001 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
1003 S_SET_VALUE (lfix->sym, frag_now_fix ());
1004 symbol_set_frag (lfix->sym, frag_now);
1006 CURR_SLOT.tag_fixups = 0;
1008 /* In case there are unwind directives following the last instruction,
1009 resolve those now. We only handle body and prologue directives here.
1010 Give an error for others. */
1011 for (ptr = unwind.current_entry; ptr; ptr = ptr->next)
1013 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
1014 || ptr->r.type == body)
1016 ptr->slot_number = (unsigned long) frag_more (0);
1017 ptr->slot_frag = frag_now;
1020 as_bad (_("Unwind directive not followed by an instruction."));
1022 unwind.current_entry = NULL;
1024 subseg_set (saved_seg, saved_subseg);
1026 if (md.qp.X_op == O_register)
1027 as_bad ("qualifying predicate not followed by instruction");
1031 ia64_do_align (nbytes)
1034 char *saved_input_line_pointer = input_line_pointer;
1036 input_line_pointer = "";
1037 s_align_bytes (nbytes);
1038 input_line_pointer = saved_input_line_pointer;
1042 ia64_cons_align (nbytes)
1047 char *saved_input_line_pointer = input_line_pointer;
1048 input_line_pointer = "";
1049 s_align_bytes (nbytes);
1050 input_line_pointer = saved_input_line_pointer;
1054 /* Output COUNT bytes to a memory location. */
1055 static unsigned char *vbyte_mem_ptr = NULL;
1058 output_vbyte_mem (count, ptr, comment)
1061 char *comment ATTRIBUTE_UNUSED;
1064 if (vbyte_mem_ptr == NULL)
1069 for (x = 0; x < count; x++)
1070 *(vbyte_mem_ptr++) = ptr[x];
1073 /* Count the number of bytes required for records. */
1074 static int vbyte_count = 0;
1076 count_output (count, ptr, comment)
1078 char *ptr ATTRIBUTE_UNUSED;
1079 char *comment ATTRIBUTE_UNUSED;
1081 vbyte_count += count;
1085 output_R1_format (f, rtype, rlen)
1087 unw_record_type rtype;
1094 output_R3_format (f, rtype, rlen);
1100 else if (rtype != prologue)
1101 as_bad ("record type is not valid");
1103 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
1104 (*f) (1, &byte, NULL);
1108 output_R2_format (f, mask, grsave, rlen)
1115 mask = (mask & 0x0f);
1116 grsave = (grsave & 0x7f);
1118 bytes[0] = (UNW_R2 | (mask >> 1));
1119 bytes[1] = (((mask & 0x01) << 7) | grsave);
1120 count += output_leb128 (bytes + 2, rlen, 0);
1121 (*f) (count, bytes, NULL);
1125 output_R3_format (f, rtype, rlen)
1127 unw_record_type rtype;
1134 output_R1_format (f, rtype, rlen);
1140 else if (rtype != prologue)
1141 as_bad ("record type is not valid");
1142 bytes[0] = (UNW_R3 | r);
1143 count = output_leb128 (bytes + 1, rlen, 0);
1144 (*f) (count + 1, bytes, NULL);
1148 output_P1_format (f, brmask)
1153 byte = UNW_P1 | (brmask & 0x1f);
1154 (*f) (1, &byte, NULL);
1158 output_P2_format (f, brmask, gr)
1164 brmask = (brmask & 0x1f);
1165 bytes[0] = UNW_P2 | (brmask >> 1);
1166 bytes[1] = (((brmask & 1) << 7) | gr);
1167 (*f) (2, bytes, NULL);
1171 output_P3_format (f, rtype, reg)
1173 unw_record_type rtype;
1218 as_bad ("Invalid record type for P3 format.");
1220 bytes[0] = (UNW_P3 | (r >> 1));
1221 bytes[1] = (((r & 1) << 7) | reg);
1222 (*f) (2, bytes, NULL);
1226 output_P4_format (f, imask, imask_size)
1228 unsigned char *imask;
1229 unsigned long imask_size;
1232 (*f) (imask_size, imask, NULL);
1236 output_P5_format (f, grmask, frmask)
1239 unsigned long frmask;
1242 grmask = (grmask & 0x0f);
1245 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1246 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1247 bytes[3] = (frmask & 0x000000ff);
1248 (*f) (4, bytes, NULL);
1252 output_P6_format (f, rtype, rmask)
1254 unw_record_type rtype;
1260 if (rtype == gr_mem)
1262 else if (rtype != fr_mem)
1263 as_bad ("Invalid record type for format P6");
1264 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1265 (*f) (1, &byte, NULL);
1269 output_P7_format (f, rtype, w1, w2)
1271 unw_record_type rtype;
1278 count += output_leb128 (bytes + 1, w1, 0);
1283 count += output_leb128 (bytes + count, w2 >> 4, 0);
1333 bytes[0] = (UNW_P7 | r);
1334 (*f) (count, bytes, NULL);
1338 output_P8_format (f, rtype, t)
1340 unw_record_type rtype;
1379 case bspstore_psprel:
1382 case bspstore_sprel:
1394 case priunat_when_gr:
1397 case priunat_psprel:
1403 case priunat_when_mem:
1410 count += output_leb128 (bytes + 2, t, 0);
1411 (*f) (count, bytes, NULL);
1415 output_P9_format (f, grmask, gr)
1422 bytes[1] = (grmask & 0x0f);
1423 bytes[2] = (gr & 0x7f);
1424 (*f) (3, bytes, NULL);
1428 output_P10_format (f, abi, context)
1435 bytes[1] = (abi & 0xff);
1436 bytes[2] = (context & 0xff);
1437 (*f) (3, bytes, NULL);
1441 output_B1_format (f, rtype, label)
1443 unw_record_type rtype;
1444 unsigned long label;
1450 output_B4_format (f, rtype, label);
1453 if (rtype == copy_state)
1455 else if (rtype != label_state)
1456 as_bad ("Invalid record type for format B1");
1458 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1459 (*f) (1, &byte, NULL);
1463 output_B2_format (f, ecount, t)
1465 unsigned long ecount;
1472 output_B3_format (f, ecount, t);
1475 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1476 count += output_leb128 (bytes + 1, t, 0);
1477 (*f) (count, bytes, NULL);
1481 output_B3_format (f, ecount, t)
1483 unsigned long ecount;
1490 output_B2_format (f, ecount, t);
1494 count += output_leb128 (bytes + 1, t, 0);
1495 count += output_leb128 (bytes + count, ecount, 0);
1496 (*f) (count, bytes, NULL);
1500 output_B4_format (f, rtype, label)
1502 unw_record_type rtype;
1503 unsigned long label;
1510 output_B1_format (f, rtype, label);
1514 if (rtype == copy_state)
1516 else if (rtype != label_state)
1517 as_bad ("Invalid record type for format B1");
1519 bytes[0] = (UNW_B4 | (r << 3));
1520 count += output_leb128 (bytes + 1, label, 0);
1521 (*f) (count, bytes, NULL);
1525 format_ab_reg (ab, reg)
1532 ret = (ab << 5) | reg;
1537 output_X1_format (f, rtype, ab, reg, t, w1)
1539 unw_record_type rtype;
1549 if (rtype == spill_sprel)
1551 else if (rtype != spill_psprel)
1552 as_bad ("Invalid record type for format X1");
1553 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
1554 count += output_leb128 (bytes + 2, t, 0);
1555 count += output_leb128 (bytes + count, w1, 0);
1556 (*f) (count, bytes, NULL);
1560 output_X2_format (f, ab, reg, x, y, treg, t)
1569 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1570 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1571 count += output_leb128 (bytes + 3, t, 0);
1572 (*f) (count, bytes, NULL);
1576 output_X3_format (f, rtype, qp, ab, reg, t, w1)
1578 unw_record_type rtype;
1589 if (rtype == spill_sprel_p)
1591 else if (rtype != spill_psprel_p)
1592 as_bad ("Invalid record type for format X3");
1593 bytes[1] = ((r << 7) | (qp & 0x3f));
1594 bytes[2] = format_ab_reg (ab, reg);
1595 count += output_leb128 (bytes + 3, t, 0);
1596 count += output_leb128 (bytes + count, w1, 0);
1597 (*f) (count, bytes, NULL);
1601 output_X4_format (f, qp, ab, reg, x, y, treg, t)
1611 bytes[1] = (qp & 0x3f);
1612 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1613 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1614 count += output_leb128 (bytes + 4, t, 0);
1615 (*f) (count, bytes, NULL);
1618 /* This function allocates a record list structure, and initializes fields. */
1620 static unw_rec_list *
1621 alloc_record (unw_record_type t)
1624 ptr = xmalloc (sizeof (*ptr));
1626 ptr->slot_number = SLOT_NUM_NOT_SET;
1631 /* This function frees an entire list of record structures. */
1634 free_list_records (unw_rec_list *first)
1637 for (ptr = first; ptr != NULL;)
1639 unw_rec_list *tmp = ptr;
1641 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1642 && tmp->r.record.r.mask.i)
1643 free (tmp->r.record.r.mask.i);
1650 static unw_rec_list *
1653 unw_rec_list *ptr = alloc_record (prologue);
1654 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1658 static unw_rec_list *
1659 output_prologue_gr (saved_mask, reg)
1660 unsigned int saved_mask;
1663 unw_rec_list *ptr = alloc_record (prologue_gr);
1664 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1665 ptr->r.record.r.grmask = saved_mask;
1666 ptr->r.record.r.grsave = reg;
1670 static unw_rec_list *
1673 unw_rec_list *ptr = alloc_record (body);
1677 static unw_rec_list *
1678 output_mem_stack_f (size)
1681 unw_rec_list *ptr = alloc_record (mem_stack_f);
1682 ptr->r.record.p.size = size;
1686 static unw_rec_list *
1687 output_mem_stack_v ()
1689 unw_rec_list *ptr = alloc_record (mem_stack_v);
1693 static unw_rec_list *
1697 unw_rec_list *ptr = alloc_record (psp_gr);
1698 ptr->r.record.p.gr = gr;
1702 static unw_rec_list *
1703 output_psp_sprel (offset)
1704 unsigned int offset;
1706 unw_rec_list *ptr = alloc_record (psp_sprel);
1707 ptr->r.record.p.spoff = offset / 4;
1711 static unw_rec_list *
1714 unw_rec_list *ptr = alloc_record (rp_when);
1718 static unw_rec_list *
1722 unw_rec_list *ptr = alloc_record (rp_gr);
1723 ptr->r.record.p.gr = gr;
1727 static unw_rec_list *
1731 unw_rec_list *ptr = alloc_record (rp_br);
1732 ptr->r.record.p.br = br;
1736 static unw_rec_list *
1737 output_rp_psprel (offset)
1738 unsigned int offset;
1740 unw_rec_list *ptr = alloc_record (rp_psprel);
1741 ptr->r.record.p.pspoff = offset / 4;
1745 static unw_rec_list *
1746 output_rp_sprel (offset)
1747 unsigned int offset;
1749 unw_rec_list *ptr = alloc_record (rp_sprel);
1750 ptr->r.record.p.spoff = offset / 4;
1754 static unw_rec_list *
1757 unw_rec_list *ptr = alloc_record (pfs_when);
1761 static unw_rec_list *
1765 unw_rec_list *ptr = alloc_record (pfs_gr);
1766 ptr->r.record.p.gr = gr;
1770 static unw_rec_list *
1771 output_pfs_psprel (offset)
1772 unsigned int offset;
1774 unw_rec_list *ptr = alloc_record (pfs_psprel);
1775 ptr->r.record.p.pspoff = offset / 4;
1779 static unw_rec_list *
1780 output_pfs_sprel (offset)
1781 unsigned int offset;
1783 unw_rec_list *ptr = alloc_record (pfs_sprel);
1784 ptr->r.record.p.spoff = offset / 4;
1788 static unw_rec_list *
1789 output_preds_when ()
1791 unw_rec_list *ptr = alloc_record (preds_when);
1795 static unw_rec_list *
1796 output_preds_gr (gr)
1799 unw_rec_list *ptr = alloc_record (preds_gr);
1800 ptr->r.record.p.gr = gr;
1804 static unw_rec_list *
1805 output_preds_psprel (offset)
1806 unsigned int offset;
1808 unw_rec_list *ptr = alloc_record (preds_psprel);
1809 ptr->r.record.p.pspoff = offset / 4;
1813 static unw_rec_list *
1814 output_preds_sprel (offset)
1815 unsigned int offset;
1817 unw_rec_list *ptr = alloc_record (preds_sprel);
1818 ptr->r.record.p.spoff = offset / 4;
1822 static unw_rec_list *
1823 output_fr_mem (mask)
1826 unw_rec_list *ptr = alloc_record (fr_mem);
1827 ptr->r.record.p.rmask = mask;
1831 static unw_rec_list *
1832 output_frgr_mem (gr_mask, fr_mask)
1833 unsigned int gr_mask;
1834 unsigned int fr_mask;
1836 unw_rec_list *ptr = alloc_record (frgr_mem);
1837 ptr->r.record.p.grmask = gr_mask;
1838 ptr->r.record.p.frmask = fr_mask;
1842 static unw_rec_list *
1843 output_gr_gr (mask, reg)
1847 unw_rec_list *ptr = alloc_record (gr_gr);
1848 ptr->r.record.p.grmask = mask;
1849 ptr->r.record.p.gr = reg;
1853 static unw_rec_list *
1854 output_gr_mem (mask)
1857 unw_rec_list *ptr = alloc_record (gr_mem);
1858 ptr->r.record.p.rmask = mask;
1862 static unw_rec_list *
1863 output_br_mem (unsigned int mask)
1865 unw_rec_list *ptr = alloc_record (br_mem);
1866 ptr->r.record.p.brmask = mask;
1870 static unw_rec_list *
1871 output_br_gr (save_mask, reg)
1872 unsigned int save_mask;
1875 unw_rec_list *ptr = alloc_record (br_gr);
1876 ptr->r.record.p.brmask = save_mask;
1877 ptr->r.record.p.gr = reg;
1881 static unw_rec_list *
1882 output_spill_base (offset)
1883 unsigned int offset;
1885 unw_rec_list *ptr = alloc_record (spill_base);
1886 ptr->r.record.p.pspoff = offset / 4;
1890 static unw_rec_list *
1893 unw_rec_list *ptr = alloc_record (unat_when);
1897 static unw_rec_list *
1901 unw_rec_list *ptr = alloc_record (unat_gr);
1902 ptr->r.record.p.gr = gr;
1906 static unw_rec_list *
1907 output_unat_psprel (offset)
1908 unsigned int offset;
1910 unw_rec_list *ptr = alloc_record (unat_psprel);
1911 ptr->r.record.p.pspoff = offset / 4;
1915 static unw_rec_list *
1916 output_unat_sprel (offset)
1917 unsigned int offset;
1919 unw_rec_list *ptr = alloc_record (unat_sprel);
1920 ptr->r.record.p.spoff = offset / 4;
1924 static unw_rec_list *
1927 unw_rec_list *ptr = alloc_record (lc_when);
1931 static unw_rec_list *
1935 unw_rec_list *ptr = alloc_record (lc_gr);
1936 ptr->r.record.p.gr = gr;
1940 static unw_rec_list *
1941 output_lc_psprel (offset)
1942 unsigned int offset;
1944 unw_rec_list *ptr = alloc_record (lc_psprel);
1945 ptr->r.record.p.pspoff = offset / 4;
1949 static unw_rec_list *
1950 output_lc_sprel (offset)
1951 unsigned int offset;
1953 unw_rec_list *ptr = alloc_record (lc_sprel);
1954 ptr->r.record.p.spoff = offset / 4;
1958 static unw_rec_list *
1961 unw_rec_list *ptr = alloc_record (fpsr_when);
1965 static unw_rec_list *
1969 unw_rec_list *ptr = alloc_record (fpsr_gr);
1970 ptr->r.record.p.gr = gr;
1974 static unw_rec_list *
1975 output_fpsr_psprel (offset)
1976 unsigned int offset;
1978 unw_rec_list *ptr = alloc_record (fpsr_psprel);
1979 ptr->r.record.p.pspoff = offset / 4;
1983 static unw_rec_list *
1984 output_fpsr_sprel (offset)
1985 unsigned int offset;
1987 unw_rec_list *ptr = alloc_record (fpsr_sprel);
1988 ptr->r.record.p.spoff = offset / 4;
1992 static unw_rec_list *
1993 output_priunat_when_gr ()
1995 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1999 static unw_rec_list *
2000 output_priunat_when_mem ()
2002 unw_rec_list *ptr = alloc_record (priunat_when_mem);
2006 static unw_rec_list *
2007 output_priunat_gr (gr)
2010 unw_rec_list *ptr = alloc_record (priunat_gr);
2011 ptr->r.record.p.gr = gr;
2015 static unw_rec_list *
2016 output_priunat_psprel (offset)
2017 unsigned int offset;
2019 unw_rec_list *ptr = alloc_record (priunat_psprel);
2020 ptr->r.record.p.pspoff = offset / 4;
2024 static unw_rec_list *
2025 output_priunat_sprel (offset)
2026 unsigned int offset;
2028 unw_rec_list *ptr = alloc_record (priunat_sprel);
2029 ptr->r.record.p.spoff = offset / 4;
2033 static unw_rec_list *
2036 unw_rec_list *ptr = alloc_record (bsp_when);
2040 static unw_rec_list *
2044 unw_rec_list *ptr = alloc_record (bsp_gr);
2045 ptr->r.record.p.gr = gr;
2049 static unw_rec_list *
2050 output_bsp_psprel (offset)
2051 unsigned int offset;
2053 unw_rec_list *ptr = alloc_record (bsp_psprel);
2054 ptr->r.record.p.pspoff = offset / 4;
2058 static unw_rec_list *
2059 output_bsp_sprel (offset)
2060 unsigned int offset;
2062 unw_rec_list *ptr = alloc_record (bsp_sprel);
2063 ptr->r.record.p.spoff = offset / 4;
2067 static unw_rec_list *
2068 output_bspstore_when ()
2070 unw_rec_list *ptr = alloc_record (bspstore_when);
2074 static unw_rec_list *
2075 output_bspstore_gr (gr)
2078 unw_rec_list *ptr = alloc_record (bspstore_gr);
2079 ptr->r.record.p.gr = gr;
2083 static unw_rec_list *
2084 output_bspstore_psprel (offset)
2085 unsigned int offset;
2087 unw_rec_list *ptr = alloc_record (bspstore_psprel);
2088 ptr->r.record.p.pspoff = offset / 4;
2092 static unw_rec_list *
2093 output_bspstore_sprel (offset)
2094 unsigned int offset;
2096 unw_rec_list *ptr = alloc_record (bspstore_sprel);
2097 ptr->r.record.p.spoff = offset / 4;
2101 static unw_rec_list *
2104 unw_rec_list *ptr = alloc_record (rnat_when);
2108 static unw_rec_list *
2112 unw_rec_list *ptr = alloc_record (rnat_gr);
2113 ptr->r.record.p.gr = gr;
2117 static unw_rec_list *
2118 output_rnat_psprel (offset)
2119 unsigned int offset;
2121 unw_rec_list *ptr = alloc_record (rnat_psprel);
2122 ptr->r.record.p.pspoff = offset / 4;
2126 static unw_rec_list *
2127 output_rnat_sprel (offset)
2128 unsigned int offset;
2130 unw_rec_list *ptr = alloc_record (rnat_sprel);
2131 ptr->r.record.p.spoff = offset / 4;
2135 static unw_rec_list *
2136 output_unwabi (abi, context)
2138 unsigned long context;
2140 unw_rec_list *ptr = alloc_record (unwabi);
2141 ptr->r.record.p.abi = abi;
2142 ptr->r.record.p.context = context;
2146 static unw_rec_list *
2147 output_epilogue (unsigned long ecount)
2149 unw_rec_list *ptr = alloc_record (epilogue);
2150 ptr->r.record.b.ecount = ecount;
2154 static unw_rec_list *
2155 output_label_state (unsigned long label)
2157 unw_rec_list *ptr = alloc_record (label_state);
2158 ptr->r.record.b.label = label;
2162 static unw_rec_list *
2163 output_copy_state (unsigned long label)
2165 unw_rec_list *ptr = alloc_record (copy_state);
2166 ptr->r.record.b.label = label;
2170 static unw_rec_list *
2171 output_spill_psprel (ab, reg, offset)
2174 unsigned int offset;
2176 unw_rec_list *ptr = alloc_record (spill_psprel);
2177 ptr->r.record.x.ab = ab;
2178 ptr->r.record.x.reg = reg;
2179 ptr->r.record.x.pspoff = offset / 4;
2183 static unw_rec_list *
2184 output_spill_sprel (ab, reg, offset)
2187 unsigned int offset;
2189 unw_rec_list *ptr = alloc_record (spill_sprel);
2190 ptr->r.record.x.ab = ab;
2191 ptr->r.record.x.reg = reg;
2192 ptr->r.record.x.spoff = offset / 4;
2196 static unw_rec_list *
2197 output_spill_psprel_p (ab, reg, offset, predicate)
2200 unsigned int offset;
2201 unsigned int predicate;
2203 unw_rec_list *ptr = alloc_record (spill_psprel_p);
2204 ptr->r.record.x.ab = ab;
2205 ptr->r.record.x.reg = reg;
2206 ptr->r.record.x.pspoff = offset / 4;
2207 ptr->r.record.x.qp = predicate;
2211 static unw_rec_list *
2212 output_spill_sprel_p (ab, reg, offset, predicate)
2215 unsigned int offset;
2216 unsigned int predicate;
2218 unw_rec_list *ptr = alloc_record (spill_sprel_p);
2219 ptr->r.record.x.ab = ab;
2220 ptr->r.record.x.reg = reg;
2221 ptr->r.record.x.spoff = offset / 4;
2222 ptr->r.record.x.qp = predicate;
2226 static unw_rec_list *
2227 output_spill_reg (ab, reg, targ_reg, xy)
2230 unsigned int targ_reg;
2233 unw_rec_list *ptr = alloc_record (spill_reg);
2234 ptr->r.record.x.ab = ab;
2235 ptr->r.record.x.reg = reg;
2236 ptr->r.record.x.treg = targ_reg;
2237 ptr->r.record.x.xy = xy;
2241 static unw_rec_list *
2242 output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2245 unsigned int targ_reg;
2247 unsigned int predicate;
2249 unw_rec_list *ptr = alloc_record (spill_reg_p);
2250 ptr->r.record.x.ab = ab;
2251 ptr->r.record.x.reg = reg;
2252 ptr->r.record.x.treg = targ_reg;
2253 ptr->r.record.x.xy = xy;
2254 ptr->r.record.x.qp = predicate;
2258 /* Given a unw_rec_list process the correct format with the
2259 specified function. */
2262 process_one_record (ptr, f)
2266 unsigned long fr_mask, gr_mask;
2268 switch (ptr->r.type)
2274 /* These are taken care of by prologue/prologue_gr. */
2279 if (ptr->r.type == prologue_gr)
2280 output_R2_format (f, ptr->r.record.r.grmask,
2281 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2283 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2285 /* Output descriptor(s) for union of register spills (if any). */
2286 gr_mask = ptr->r.record.r.mask.gr_mem;
2287 fr_mask = ptr->r.record.r.mask.fr_mem;
2290 if ((fr_mask & ~0xfUL) == 0)
2291 output_P6_format (f, fr_mem, fr_mask);
2294 output_P5_format (f, gr_mask, fr_mask);
2299 output_P6_format (f, gr_mem, gr_mask);
2300 if (ptr->r.record.r.mask.br_mem)
2301 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2303 /* output imask descriptor if necessary: */
2304 if (ptr->r.record.r.mask.i)
2305 output_P4_format (f, ptr->r.record.r.mask.i,
2306 ptr->r.record.r.imask_size);
2310 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2314 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2315 ptr->r.record.p.size);
2328 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2331 output_P3_format (f, rp_br, ptr->r.record.p.br);
2334 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2342 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2351 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2361 case bspstore_sprel:
2363 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2366 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2369 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2372 as_bad ("spill_mask record unimplemented.");
2374 case priunat_when_gr:
2375 case priunat_when_mem:
2379 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2381 case priunat_psprel:
2383 case bspstore_psprel:
2385 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2388 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2391 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2395 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2398 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2399 ptr->r.record.x.reg, ptr->r.record.x.t,
2400 ptr->r.record.x.pspoff);
2403 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2404 ptr->r.record.x.reg, ptr->r.record.x.t,
2405 ptr->r.record.x.spoff);
2408 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2409 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2410 ptr->r.record.x.treg, ptr->r.record.x.t);
2412 case spill_psprel_p:
2413 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2414 ptr->r.record.x.ab, ptr->r.record.x.reg,
2415 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2418 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2419 ptr->r.record.x.ab, ptr->r.record.x.reg,
2420 ptr->r.record.x.t, ptr->r.record.x.spoff);
2423 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2424 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2425 ptr->r.record.x.xy, ptr->r.record.x.treg,
2429 as_bad ("record_type_not_valid");
2434 /* Given a unw_rec_list list, process all the records with
2435 the specified function. */
2437 process_unw_records (list, f)
2442 for (ptr = list; ptr; ptr = ptr->next)
2443 process_one_record (ptr, f);
2446 /* Determine the size of a record list in bytes. */
2448 calc_record_size (list)
2452 process_unw_records (list, count_output);
2456 /* Update IMASK bitmask to reflect the fact that one or more registers
2457 of type TYPE are saved starting at instruction with index T. If N
2458 bits are set in REGMASK, it is assumed that instructions T through
2459 T+N-1 save these registers.
2463 1: instruction saves next fp reg
2464 2: instruction saves next general reg
2465 3: instruction saves next branch reg */
2467 set_imask (region, regmask, t, type)
2468 unw_rec_list *region;
2469 unsigned long regmask;
2473 unsigned char *imask;
2474 unsigned long imask_size;
2478 imask = region->r.record.r.mask.i;
2479 imask_size = region->r.record.r.imask_size;
2482 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
2483 imask = xmalloc (imask_size);
2484 memset (imask, 0, imask_size);
2486 region->r.record.r.imask_size = imask_size;
2487 region->r.record.r.mask.i = imask;
2491 pos = 2 * (3 - t % 4);
2494 if (i >= imask_size)
2496 as_bad ("Ignoring attempt to spill beyond end of region");
2500 imask[i] |= (type & 0x3) << pos;
2502 regmask &= (regmask - 1);
2513 count_bits (unsigned long mask)
2525 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2526 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2527 containing FIRST_ADDR. */
2530 slot_index (slot_addr, slot_frag, first_addr, first_frag)
2531 unsigned long slot_addr;
2533 unsigned long first_addr;
2536 unsigned long index = 0;
2538 /* First time we are called, the initial address and frag are invalid. */
2539 if (first_addr == 0)
2542 /* If the two addresses are in different frags, then we need to add in
2543 the remaining size of this frag, and then the entire size of intermediate
2545 while (slot_frag != first_frag)
2547 unsigned long start_addr = (unsigned long) &first_frag->fr_literal;
2549 /* Add in the full size of the frag converted to instruction slots. */
2550 index += 3 * (first_frag->fr_fix >> 4);
2551 /* Subtract away the initial part before first_addr. */
2552 index -= (3 * ((first_addr >> 4) - (start_addr >> 4))
2553 + ((first_addr & 0x3) - (start_addr & 0x3)));
2555 /* Move to the beginning of the next frag. */
2556 first_frag = first_frag->fr_next;
2557 first_addr = (unsigned long) &first_frag->fr_literal;
2560 /* Add in the used part of the last frag. */
2561 index += (3 * ((slot_addr >> 4) - (first_addr >> 4))
2562 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2566 /* Optimize unwind record directives. */
2568 static unw_rec_list *
2569 optimize_unw_records (list)
2575 /* If the only unwind record is ".prologue" or ".prologue" followed
2576 by ".body", then we can optimize the unwind directives away. */
2577 if (list->r.type == prologue
2578 && (list->next == NULL
2579 || (list->next->r.type == body && list->next->next == NULL)))
2585 /* Given a complete record list, process any records which have
2586 unresolved fields, (ie length counts for a prologue). After
2587 this has been run, all neccessary information should be available
2588 within each record to generate an image. */
2591 fixup_unw_records (list)
2594 unw_rec_list *ptr, *region = 0;
2595 unsigned long first_addr = 0, rlen = 0, t;
2596 fragS *first_frag = 0;
2598 for (ptr = list; ptr; ptr = ptr->next)
2600 if (ptr->slot_number == SLOT_NUM_NOT_SET)
2601 as_bad (" Insn slot not set in unwind record.");
2602 t = slot_index (ptr->slot_number, ptr->slot_frag,
2603 first_addr, first_frag);
2604 switch (ptr->r.type)
2611 int size, dir_len = 0;
2612 unsigned long last_addr;
2615 first_addr = ptr->slot_number;
2616 first_frag = ptr->slot_frag;
2617 ptr->slot_number = 0;
2618 /* Find either the next body/prologue start, or the end of
2619 the list, and determine the size of the region. */
2620 last_addr = unwind.next_slot_number;
2621 last_frag = unwind.next_slot_frag;
2622 for (last = ptr->next; last != NULL; last = last->next)
2623 if (last->r.type == prologue || last->r.type == prologue_gr
2624 || last->r.type == body)
2626 last_addr = last->slot_number;
2627 last_frag = last->slot_frag;
2630 else if (!last->next)
2632 /* In the absence of an explicit .body directive,
2633 the prologue ends after the last instruction
2634 covered by an unwind directive. */
2635 if (ptr->r.type != body)
2637 last_addr = last->slot_number;
2638 last_frag = last->slot_frag;
2639 switch (last->r.type)
2642 dir_len = (count_bits (last->r.record.p.frmask)
2643 + count_bits (last->r.record.p.grmask));
2647 dir_len += count_bits (last->r.record.p.rmask);
2651 dir_len += count_bits (last->r.record.p.brmask);
2654 dir_len += count_bits (last->r.record.p.grmask);
2663 size = (slot_index (last_addr, last_frag, first_addr, first_frag)
2665 rlen = ptr->r.record.r.rlen = size;
2670 ptr->r.record.b.t = rlen - 1 - t;
2681 case priunat_when_gr:
2682 case priunat_when_mem:
2686 ptr->r.record.p.t = t;
2694 case spill_psprel_p:
2695 ptr->r.record.x.t = t;
2701 as_bad ("frgr_mem record before region record!\n");
2704 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2705 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2706 set_imask (region, ptr->r.record.p.frmask, t, 1);
2707 set_imask (region, ptr->r.record.p.grmask, t, 2);
2712 as_bad ("fr_mem record before region record!\n");
2715 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2716 set_imask (region, ptr->r.record.p.rmask, t, 1);
2721 as_bad ("gr_mem record before region record!\n");
2724 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2725 set_imask (region, ptr->r.record.p.rmask, t, 2);
2730 as_bad ("br_mem record before region record!\n");
2733 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2734 set_imask (region, ptr->r.record.p.brmask, t, 3);
2740 as_bad ("gr_gr record before region record!\n");
2743 set_imask (region, ptr->r.record.p.grmask, t, 2);
2748 as_bad ("br_gr record before region record!\n");
2751 set_imask (region, ptr->r.record.p.brmask, t, 3);
2760 /* Generate an unwind image from a record list. Returns the number of
2761 bytes in the resulting image. The memory image itselof is returned
2762 in the 'ptr' parameter. */
2764 output_unw_records (list, ptr)
2768 int size, x, extra = 0;
2773 list = optimize_unw_records (list);
2774 fixup_unw_records (list);
2775 size = calc_record_size (list);
2777 /* pad to 8 byte boundry. */
2782 if (size > 0 || unwind.force_unwind_entry)
2784 unwind.force_unwind_entry = 0;
2786 /* Add 8 for the header + 8 more bytes for the personality offset. */
2787 mem = xmalloc (size + extra + 16);
2789 vbyte_mem_ptr = mem + 8;
2790 /* Clear the padding area and personality. */
2791 memset (mem + 8 + size, 0 , extra + 8);
2792 /* Initialize the header area. */
2793 md_number_to_chars (mem,
2794 (((bfd_vma) 1 << 48) /* version */
2795 | (unwind.personality_routine
2796 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2798 | ((size + extra) / 8)), /* length (dwords) */
2801 process_unw_records (list, output_vbyte_mem);
2811 convert_expr_to_ab_reg (e, ab, regp)
2818 if (e->X_op != O_register)
2821 reg = e->X_add_number;
2822 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7))
2825 *regp = reg - REG_GR;
2827 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5))
2828 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31)))
2831 *regp = reg - REG_FR;
2833 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5))
2836 *regp = reg - REG_BR;
2843 case REG_PR: *regp = 0; break;
2844 case REG_PSP: *regp = 1; break;
2845 case REG_PRIUNAT: *regp = 2; break;
2846 case REG_BR + 0: *regp = 3; break;
2847 case REG_AR + AR_BSP: *regp = 4; break;
2848 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2849 case REG_AR + AR_RNAT: *regp = 6; break;
2850 case REG_AR + AR_UNAT: *regp = 7; break;
2851 case REG_AR + AR_FPSR: *regp = 8; break;
2852 case REG_AR + AR_PFS: *regp = 9; break;
2853 case REG_AR + AR_LC: *regp = 10; break;
2863 convert_expr_to_xy_reg (e, xy, regp)
2870 if (e->X_op != O_register)
2873 reg = e->X_add_number;
2875 if (/* reg >= REG_GR && */ reg <= (REG_GR + 127))
2878 *regp = reg - REG_GR;
2880 else if (reg >= REG_FR && reg <= (REG_FR + 127))
2883 *regp = reg - REG_FR;
2885 else if (reg >= REG_BR && reg <= (REG_BR + 7))
2888 *regp = reg - REG_BR;
2897 int dummy ATTRIBUTE_UNUSED;
2902 radix = *input_line_pointer++;
2904 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2906 as_bad ("Radix `%c' unsupported", *input_line_pointer);
2907 ignore_rest_of_line ();
2912 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2914 dot_special_section (which)
2917 set_section ((char *) special_section_name[which]);
2921 add_unwind_entry (ptr)
2925 unwind.tail->next = ptr;
2930 /* The current entry can in fact be a chain of unwind entries. */
2931 if (unwind.current_entry == NULL)
2932 unwind.current_entry = ptr;
2937 int dummy ATTRIBUTE_UNUSED;
2943 if (e.X_op != O_constant)
2944 as_bad ("Operand to .fframe must be a constant");
2946 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2951 int dummy ATTRIBUTE_UNUSED;
2957 reg = e.X_add_number - REG_GR;
2958 if (e.X_op == O_register && reg < 128)
2960 add_unwind_entry (output_mem_stack_v ());
2961 if (! (unwind.prologue_mask & 2))
2962 add_unwind_entry (output_psp_gr (reg));
2965 as_bad ("First operand to .vframe must be a general register");
2969 dot_vframesp (dummy)
2970 int dummy ATTRIBUTE_UNUSED;
2975 if (e.X_op == O_constant)
2977 add_unwind_entry (output_mem_stack_v ());
2978 add_unwind_entry (output_psp_sprel (e.X_add_number));
2981 as_bad ("First operand to .vframesp must be a general register");
2985 dot_vframepsp (dummy)
2986 int dummy ATTRIBUTE_UNUSED;
2991 if (e.X_op == O_constant)
2993 add_unwind_entry (output_mem_stack_v ());
2994 add_unwind_entry (output_psp_sprel (e.X_add_number));
2997 as_bad ("First operand to .vframepsp must be a general register");
3002 int dummy ATTRIBUTE_UNUSED;
3008 sep = parse_operand (&e1);
3010 as_bad ("No second operand to .save");
3011 sep = parse_operand (&e2);
3013 reg1 = e1.X_add_number;
3014 reg2 = e2.X_add_number - REG_GR;
3016 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3017 if (e1.X_op == O_register)
3019 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
3023 case REG_AR + AR_BSP:
3024 add_unwind_entry (output_bsp_when ());
3025 add_unwind_entry (output_bsp_gr (reg2));
3027 case REG_AR + AR_BSPSTORE:
3028 add_unwind_entry (output_bspstore_when ());
3029 add_unwind_entry (output_bspstore_gr (reg2));
3031 case REG_AR + AR_RNAT:
3032 add_unwind_entry (output_rnat_when ());
3033 add_unwind_entry (output_rnat_gr (reg2));
3035 case REG_AR + AR_UNAT:
3036 add_unwind_entry (output_unat_when ());
3037 add_unwind_entry (output_unat_gr (reg2));
3039 case REG_AR + AR_FPSR:
3040 add_unwind_entry (output_fpsr_when ());
3041 add_unwind_entry (output_fpsr_gr (reg2));
3043 case REG_AR + AR_PFS:
3044 add_unwind_entry (output_pfs_when ());
3045 if (! (unwind.prologue_mask & 4))
3046 add_unwind_entry (output_pfs_gr (reg2));
3048 case REG_AR + AR_LC:
3049 add_unwind_entry (output_lc_when ());
3050 add_unwind_entry (output_lc_gr (reg2));
3053 add_unwind_entry (output_rp_when ());
3054 if (! (unwind.prologue_mask & 8))
3055 add_unwind_entry (output_rp_gr (reg2));
3058 add_unwind_entry (output_preds_when ());
3059 if (! (unwind.prologue_mask & 1))
3060 add_unwind_entry (output_preds_gr (reg2));
3063 add_unwind_entry (output_priunat_when_gr ());
3064 add_unwind_entry (output_priunat_gr (reg2));
3067 as_bad ("First operand not a valid register");
3071 as_bad (" Second operand not a valid register");
3074 as_bad ("First operand not a register");
3079 int dummy ATTRIBUTE_UNUSED;
3082 unsigned long ecount; /* # of _additional_ regions to pop */
3085 sep = parse_operand (&e1);
3086 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
3088 as_bad ("First operand to .restore must be stack pointer (sp)");
3094 parse_operand (&e2);
3095 if (e2.X_op != O_constant || e2.X_add_number < 0)
3097 as_bad ("Second operand to .restore must be a constant >= 0");
3100 ecount = e2.X_add_number;
3103 ecount = unwind.prologue_count - 1;
3104 add_unwind_entry (output_epilogue (ecount));
3106 if (ecount < unwind.prologue_count)
3107 unwind.prologue_count -= ecount + 1;
3109 unwind.prologue_count = 0;
3113 dot_restorereg (dummy)
3114 int dummy ATTRIBUTE_UNUSED;
3116 unsigned int ab, reg;
3121 if (!convert_expr_to_ab_reg (&e, &ab, ®))
3123 as_bad ("First operand to .restorereg must be a preserved register");
3126 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
3130 dot_restorereg_p (dummy)
3131 int dummy ATTRIBUTE_UNUSED;
3133 unsigned int qp, ab, reg;
3137 sep = parse_operand (&e1);
3140 as_bad ("No second operand to .restorereg.p");
3144 parse_operand (&e2);
3146 qp = e1.X_add_number - REG_P;
3147 if (e1.X_op != O_register || qp > 63)
3149 as_bad ("First operand to .restorereg.p must be a predicate");
3153 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3155 as_bad ("Second operand to .restorereg.p must be a preserved register");
3158 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
3162 generate_unwind_image (text_name)
3163 const char *text_name;
3166 unsigned char *unw_rec;
3168 /* Force out pending instructions, to make sure all unwind records have
3169 a valid slot_number field. */
3170 ia64_flush_insns ();
3172 /* Generate the unwind record. */
3173 size = output_unw_records (unwind.list, (void **) &unw_rec);
3175 as_bad ("Unwind record is not a multiple of 8 bytes.");
3177 /* If there are unwind records, switch sections, and output the info. */
3180 unsigned char *where;
3184 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name);
3185 set_section (sec_name);
3186 bfd_set_section_flags (stdoutput, now_seg,
3187 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
3189 /* Make sure the section has 8 byte alignment. */
3190 frag_align (3, 0, 0);
3191 record_alignment (now_seg, 3);
3193 /* Set expression which points to start of unwind descriptor area. */
3194 unwind.info = expr_build_dot ();
3196 where = (unsigned char *) frag_more (size);
3198 /* Issue a label for this address, and keep track of it to put it
3199 in the unwind section. */
3201 /* Copy the information from the unwind record into this section. The
3202 data is already in the correct byte order. */
3203 memcpy (where, unw_rec, size);
3205 /* Add the personality address to the image. */
3206 if (unwind.personality_routine != 0)
3208 exp.X_op = O_symbol;
3209 exp.X_add_symbol = unwind.personality_routine;
3210 exp.X_add_number = 0;
3211 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
3212 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
3213 unwind.personality_routine = 0;
3217 free_list_records (unwind.list);
3218 unwind.list = unwind.tail = unwind.current_entry = NULL;
3224 dot_handlerdata (dummy)
3225 int dummy ATTRIBUTE_UNUSED;
3227 const char *text_name = segment_name (now_seg);
3229 /* If text section name starts with ".text" (which it should),
3230 strip this prefix off. */
3231 if (strcmp (text_name, ".text") == 0)
3234 unwind.force_unwind_entry = 1;
3236 /* Remember which segment we're in so we can switch back after .endp */
3237 unwind.saved_text_seg = now_seg;
3238 unwind.saved_text_subseg = now_subseg;
3240 /* Generate unwind info into unwind-info section and then leave that
3241 section as the currently active one so dataXX directives go into
3242 the language specific data area of the unwind info block. */
3243 generate_unwind_image (text_name);
3244 demand_empty_rest_of_line ();
3248 dot_unwentry (dummy)
3249 int dummy ATTRIBUTE_UNUSED;
3251 unwind.force_unwind_entry = 1;
3252 demand_empty_rest_of_line ();
3257 int dummy ATTRIBUTE_UNUSED;
3263 reg = e.X_add_number - REG_BR;
3264 if (e.X_op == O_register && reg < 8)
3265 add_unwind_entry (output_rp_br (reg));
3267 as_bad ("First operand not a valid branch register");
3271 dot_savemem (psprel)
3278 sep = parse_operand (&e1);
3280 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
3281 sep = parse_operand (&e2);
3283 reg1 = e1.X_add_number;
3284 val = e2.X_add_number;
3286 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3287 if (e1.X_op == O_register)
3289 if (e2.X_op == O_constant)
3293 case REG_AR + AR_BSP:
3294 add_unwind_entry (output_bsp_when ());
3295 add_unwind_entry ((psprel
3297 : output_bsp_sprel) (val));
3299 case REG_AR + AR_BSPSTORE:
3300 add_unwind_entry (output_bspstore_when ());
3301 add_unwind_entry ((psprel
3302 ? output_bspstore_psprel
3303 : output_bspstore_sprel) (val));
3305 case REG_AR + AR_RNAT:
3306 add_unwind_entry (output_rnat_when ());
3307 add_unwind_entry ((psprel
3308 ? output_rnat_psprel
3309 : output_rnat_sprel) (val));
3311 case REG_AR + AR_UNAT:
3312 add_unwind_entry (output_unat_when ());
3313 add_unwind_entry ((psprel
3314 ? output_unat_psprel
3315 : output_unat_sprel) (val));
3317 case REG_AR + AR_FPSR:
3318 add_unwind_entry (output_fpsr_when ());
3319 add_unwind_entry ((psprel
3320 ? output_fpsr_psprel
3321 : output_fpsr_sprel) (val));
3323 case REG_AR + AR_PFS:
3324 add_unwind_entry (output_pfs_when ());
3325 add_unwind_entry ((psprel
3327 : output_pfs_sprel) (val));
3329 case REG_AR + AR_LC:
3330 add_unwind_entry (output_lc_when ());
3331 add_unwind_entry ((psprel
3333 : output_lc_sprel) (val));
3336 add_unwind_entry (output_rp_when ());
3337 add_unwind_entry ((psprel
3339 : output_rp_sprel) (val));
3342 add_unwind_entry (output_preds_when ());
3343 add_unwind_entry ((psprel
3344 ? output_preds_psprel
3345 : output_preds_sprel) (val));
3348 add_unwind_entry (output_priunat_when_mem ());
3349 add_unwind_entry ((psprel
3350 ? output_priunat_psprel
3351 : output_priunat_sprel) (val));
3354 as_bad ("First operand not a valid register");
3358 as_bad (" Second operand not a valid constant");
3361 as_bad ("First operand not a register");
3366 int dummy ATTRIBUTE_UNUSED;
3370 sep = parse_operand (&e1);
3372 parse_operand (&e2);
3374 if (e1.X_op != O_constant)
3375 as_bad ("First operand to .save.g must be a constant.");
3378 int grmask = e1.X_add_number;
3380 add_unwind_entry (output_gr_mem (grmask));
3383 int reg = e2.X_add_number - REG_GR;
3384 if (e2.X_op == O_register && reg >= 0 && reg < 128)
3385 add_unwind_entry (output_gr_gr (grmask, reg));
3387 as_bad ("Second operand is an invalid register.");
3394 int dummy ATTRIBUTE_UNUSED;
3398 sep = parse_operand (&e1);
3400 if (e1.X_op != O_constant)
3401 as_bad ("Operand to .save.f must be a constant.");
3403 add_unwind_entry (output_fr_mem (e1.X_add_number));
3408 int dummy ATTRIBUTE_UNUSED;
3415 sep = parse_operand (&e1);
3416 if (e1.X_op != O_constant)
3418 as_bad ("First operand to .save.b must be a constant.");
3421 brmask = e1.X_add_number;
3425 sep = parse_operand (&e2);
3426 reg = e2.X_add_number - REG_GR;
3427 if (e2.X_op != O_register || reg > 127)
3429 as_bad ("Second operand to .save.b must be a general register.");
3432 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3435 add_unwind_entry (output_br_mem (brmask));
3437 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3438 ignore_rest_of_line ();
3443 int dummy ATTRIBUTE_UNUSED;
3447 sep = parse_operand (&e1);
3449 parse_operand (&e2);
3451 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3452 as_bad ("Both operands of .save.gf must be constants.");
3455 int grmask = e1.X_add_number;
3456 int frmask = e2.X_add_number;
3457 add_unwind_entry (output_frgr_mem (grmask, frmask));
3463 int dummy ATTRIBUTE_UNUSED;
3468 sep = parse_operand (&e);
3469 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3470 ignore_rest_of_line ();
3472 if (e.X_op != O_constant)
3473 as_bad ("Operand to .spill must be a constant");
3475 add_unwind_entry (output_spill_base (e.X_add_number));
3479 dot_spillreg (dummy)
3480 int dummy ATTRIBUTE_UNUSED;
3482 int sep, ab, xy, reg, treg;
3485 sep = parse_operand (&e1);
3488 as_bad ("No second operand to .spillreg");
3492 parse_operand (&e2);
3494 if (!convert_expr_to_ab_reg (&e1, &ab, ®))
3496 as_bad ("First operand to .spillreg must be a preserved register");
3500 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3502 as_bad ("Second operand to .spillreg must be a register");
3506 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3510 dot_spillmem (psprel)
3516 sep = parse_operand (&e1);
3519 as_bad ("Second operand missing");
3523 parse_operand (&e2);
3525 if (!convert_expr_to_ab_reg (&e1, &ab, ®))
3527 as_bad ("First operand to .spill%s must be a preserved register",
3528 psprel ? "psp" : "sp");
3532 if (e2.X_op != O_constant)
3534 as_bad ("Second operand to .spill%s must be a constant",
3535 psprel ? "psp" : "sp");
3540 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3542 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3546 dot_spillreg_p (dummy)
3547 int dummy ATTRIBUTE_UNUSED;
3549 int sep, ab, xy, reg, treg;
3550 expressionS e1, e2, e3;
3553 sep = parse_operand (&e1);
3556 as_bad ("No second and third operand to .spillreg.p");
3560 sep = parse_operand (&e2);
3563 as_bad ("No third operand to .spillreg.p");
3567 parse_operand (&e3);
3569 qp = e1.X_add_number - REG_P;
3571 if (e1.X_op != O_register || qp > 63)
3573 as_bad ("First operand to .spillreg.p must be a predicate");
3577 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3579 as_bad ("Second operand to .spillreg.p must be a preserved register");
3583 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3585 as_bad ("Third operand to .spillreg.p must be a register");
3589 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3593 dot_spillmem_p (psprel)
3596 expressionS e1, e2, e3;
3600 sep = parse_operand (&e1);
3603 as_bad ("Second operand missing");
3607 parse_operand (&e2);
3610 as_bad ("Second operand missing");
3614 parse_operand (&e3);
3616 qp = e1.X_add_number - REG_P;
3617 if (e1.X_op != O_register || qp > 63)
3619 as_bad ("First operand to .spill%s_p must be a predicate",
3620 psprel ? "psp" : "sp");
3624 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3626 as_bad ("Second operand to .spill%s_p must be a preserved register",
3627 psprel ? "psp" : "sp");
3631 if (e3.X_op != O_constant)
3633 as_bad ("Third operand to .spill%s_p must be a constant",
3634 psprel ? "psp" : "sp");
3639 add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp));
3641 add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp));
3645 dot_label_state (dummy)
3646 int dummy ATTRIBUTE_UNUSED;
3651 if (e.X_op != O_constant)
3653 as_bad ("Operand to .label_state must be a constant");
3656 add_unwind_entry (output_label_state (e.X_add_number));
3660 dot_copy_state (dummy)
3661 int dummy ATTRIBUTE_UNUSED;
3666 if (e.X_op != O_constant)
3668 as_bad ("Operand to .copy_state must be a constant");
3671 add_unwind_entry (output_copy_state (e.X_add_number));
3676 int dummy ATTRIBUTE_UNUSED;
3681 sep = parse_operand (&e1);
3684 as_bad ("Second operand to .unwabi missing");
3687 sep = parse_operand (&e2);
3688 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3689 ignore_rest_of_line ();
3691 if (e1.X_op != O_constant)
3693 as_bad ("First operand to .unwabi must be a constant");
3697 if (e2.X_op != O_constant)
3699 as_bad ("Second operand to .unwabi must be a constant");
3703 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
3707 dot_personality (dummy)
3708 int dummy ATTRIBUTE_UNUSED;
3712 name = input_line_pointer;
3713 c = get_symbol_end ();
3714 p = input_line_pointer;
3715 unwind.personality_routine = symbol_find_or_make (name);
3716 unwind.force_unwind_entry = 1;
3719 demand_empty_rest_of_line ();
3724 int dummy ATTRIBUTE_UNUSED;
3729 unwind.proc_start = expr_build_dot ();
3730 /* Parse names of main and alternate entry points and mark them as
3731 function symbols: */
3735 name = input_line_pointer;
3736 c = get_symbol_end ();
3737 p = input_line_pointer;
3738 sym = symbol_find_or_make (name);
3739 if (unwind.proc_start == 0)
3741 unwind.proc_start = sym;
3743 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3746 if (*input_line_pointer != ',')
3748 ++input_line_pointer;
3750 demand_empty_rest_of_line ();
3753 unwind.prologue_count = 0;
3754 unwind.list = unwind.tail = unwind.current_entry = NULL;
3755 unwind.personality_routine = 0;
3760 int dummy ATTRIBUTE_UNUSED;
3762 unwind.prologue = 0;
3763 unwind.prologue_mask = 0;
3765 add_unwind_entry (output_body ());
3766 demand_empty_rest_of_line ();
3770 dot_prologue (dummy)
3771 int dummy ATTRIBUTE_UNUSED;
3774 int mask = 0, grsave = 0;
3776 if (!is_it_end_of_statement ())
3779 sep = parse_operand (&e1);
3781 as_bad ("No second operand to .prologue");
3782 sep = parse_operand (&e2);
3783 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3784 ignore_rest_of_line ();
3786 if (e1.X_op == O_constant)
3788 mask = e1.X_add_number;
3790 if (e2.X_op == O_constant)
3791 grsave = e2.X_add_number;
3792 else if (e2.X_op == O_register
3793 && (grsave = e2.X_add_number - REG_GR) < 128)
3796 as_bad ("Second operand not a constant or general register");
3798 add_unwind_entry (output_prologue_gr (mask, grsave));
3801 as_bad ("First operand not a constant");
3804 add_unwind_entry (output_prologue ());
3806 unwind.prologue = 1;
3807 unwind.prologue_mask = mask;
3808 ++unwind.prologue_count;
3813 int dummy ATTRIBUTE_UNUSED;
3817 int bytes_per_address;
3820 subsegT saved_subseg;
3821 const char *sec_name, *text_name;
3823 if (unwind.saved_text_seg)
3825 saved_seg = unwind.saved_text_seg;
3826 saved_subseg = unwind.saved_text_subseg;
3827 unwind.saved_text_seg = NULL;
3831 saved_seg = now_seg;
3832 saved_subseg = now_subseg;
3836 Use a slightly ugly scheme to derive the unwind section names from
3837 the text section name:
3839 text sect. unwind table sect.
3840 name: name: comments:
3841 ---------- ----------------- --------------------------------
3843 .text.foo .IA_64.unwind.text.foo
3844 .foo .IA_64.unwind.foo
3846 .gnu.linkonce.ia64unw.foo
3847 _info .IA_64.unwind_info gas issues error message (ditto)
3848 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
3850 This mapping is done so that:
3852 (a) An object file with unwind info only in .text will use
3853 unwind section names .IA_64.unwind and .IA_64.unwind_info.
3854 This follows the letter of the ABI and also ensures backwards
3855 compatibility with older toolchains.
3857 (b) An object file with unwind info in multiple text sections
3858 will use separate unwind sections for each text section.
3859 This allows us to properly set the "sh_info" and "sh_link"
3860 fields in SHT_IA_64_UNWIND as required by the ABI and also
3861 lets GNU ld support programs with multiple segments
3862 containing unwind info (as might be the case for certain
3863 embedded applications).
3865 (c) An error is issued if there would be a name clash.
3867 text_name = segment_name (saved_seg);
3868 if (strncmp (text_name, "_info", 5) == 0)
3870 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
3872 ignore_rest_of_line ();
3875 if (strcmp (text_name, ".text") == 0)
3879 demand_empty_rest_of_line ();
3881 insn_group_break (1, 0, 0);
3883 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
3885 generate_unwind_image (text_name);
3887 if (unwind.info || unwind.force_unwind_entry)
3889 subseg_set (md.last_text_seg, 0);
3890 unwind.proc_end = expr_build_dot ();
3892 make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name);
3893 set_section ((char *) sec_name);
3894 bfd_set_section_flags (stdoutput, now_seg,
3895 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
3897 /* Make sure the section has 8 byte alignment. */
3898 record_alignment (now_seg, 3);
3900 ptr = frag_more (24);
3901 where = frag_now_fix () - 24;
3902 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
3904 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3905 e.X_op = O_pseudo_fixup;
3906 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3908 e.X_add_symbol = unwind.proc_start;
3909 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
3911 e.X_op = O_pseudo_fixup;
3912 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3914 e.X_add_symbol = unwind.proc_end;
3915 ia64_cons_fix_new (frag_now, where + bytes_per_address,
3916 bytes_per_address, &e);
3920 e.X_op = O_pseudo_fixup;
3921 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3923 e.X_add_symbol = unwind.info;
3924 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2),
3925 bytes_per_address, &e);
3928 md_number_to_chars (ptr + (bytes_per_address * 2), 0,
3932 subseg_set (saved_seg, saved_subseg);
3933 unwind.proc_start = unwind.proc_end = unwind.info = 0;
3937 dot_template (template)
3940 CURR_SLOT.user_template = template;
3945 int dummy ATTRIBUTE_UNUSED;
3947 int ins, locs, outs, rots;
3949 if (is_it_end_of_statement ())
3950 ins = locs = outs = rots = 0;
3953 ins = get_absolute_expression ();
3954 if (*input_line_pointer++ != ',')
3956 locs = get_absolute_expression ();
3957 if (*input_line_pointer++ != ',')
3959 outs = get_absolute_expression ();
3960 if (*input_line_pointer++ != ',')
3962 rots = get_absolute_expression ();
3964 set_regstack (ins, locs, outs, rots);
3968 as_bad ("Comma expected");
3969 ignore_rest_of_line ();
3976 unsigned num_regs, num_alloced = 0;
3977 struct dynreg **drpp, *dr;
3978 int ch, base_reg = 0;
3984 case DYNREG_GR: base_reg = REG_GR + 32; break;
3985 case DYNREG_FR: base_reg = REG_FR + 32; break;
3986 case DYNREG_PR: base_reg = REG_P + 16; break;
3990 /* First, remove existing names from hash table. */
3991 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3993 hash_delete (md.dynreg_hash, dr->name);
3997 drpp = &md.dynreg[type];
4000 start = input_line_pointer;
4001 ch = get_symbol_end ();
4002 *input_line_pointer = ch;
4003 len = (input_line_pointer - start);
4006 if (*input_line_pointer != '[')
4008 as_bad ("Expected '['");
4011 ++input_line_pointer; /* skip '[' */
4013 num_regs = get_absolute_expression ();
4015 if (*input_line_pointer++ != ']')
4017 as_bad ("Expected ']'");
4022 num_alloced += num_regs;
4026 if (num_alloced > md.rot.num_regs)
4028 as_bad ("Used more than the declared %d rotating registers",
4034 if (num_alloced > 96)
4036 as_bad ("Used more than the available 96 rotating registers");
4041 if (num_alloced > 48)
4043 as_bad ("Used more than the available 48 rotating registers");
4052 name = obstack_alloc (¬es, len + 1);
4053 memcpy (name, start, len);
4058 *drpp = obstack_alloc (¬es, sizeof (*dr));
4059 memset (*drpp, 0, sizeof (*dr));
4064 dr->num_regs = num_regs;
4065 dr->base = base_reg;
4067 base_reg += num_regs;
4069 if (hash_insert (md.dynreg_hash, name, dr))
4071 as_bad ("Attempt to redefine register set `%s'", name);
4075 if (*input_line_pointer != ',')
4077 ++input_line_pointer; /* skip comma */
4080 demand_empty_rest_of_line ();
4084 ignore_rest_of_line ();
4088 dot_byteorder (byteorder)
4091 target_big_endian = byteorder;
4096 int dummy ATTRIBUTE_UNUSED;
4103 option = input_line_pointer;
4104 ch = get_symbol_end ();
4105 if (strcmp (option, "lsb") == 0)
4106 md.flags &= ~EF_IA_64_BE;
4107 else if (strcmp (option, "msb") == 0)
4108 md.flags |= EF_IA_64_BE;
4109 else if (strcmp (option, "abi32") == 0)
4110 md.flags &= ~EF_IA_64_ABI64;
4111 else if (strcmp (option, "abi64") == 0)
4112 md.flags |= EF_IA_64_ABI64;
4114 as_bad ("Unknown psr option `%s'", option);
4115 *input_line_pointer = ch;
4118 if (*input_line_pointer != ',')
4121 ++input_line_pointer;
4124 demand_empty_rest_of_line ();
4129 int dummy ATTRIBUTE_UNUSED;
4131 as_bad (".alias not implemented yet");
4136 int dummy ATTRIBUTE_UNUSED;
4138 new_logical_line (0, get_absolute_expression ());
4139 demand_empty_rest_of_line ();
4143 parse_section_name ()
4149 if (*input_line_pointer != '"')
4151 as_bad ("Missing section name");
4152 ignore_rest_of_line ();
4155 name = demand_copy_C_string (&len);
4158 ignore_rest_of_line ();
4162 if (*input_line_pointer != ',')
4164 as_bad ("Comma expected after section name");
4165 ignore_rest_of_line ();
4168 ++input_line_pointer; /* skip comma */
4176 char *name = parse_section_name ();
4180 md.keep_pending_output = 1;
4183 obj_elf_previous (0);
4184 md.keep_pending_output = 0;
4187 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4190 stmt_float_cons (kind)
4197 case 'd': size = 8; break;
4198 case 'x': size = 10; break;
4205 ia64_do_align (size);
4213 int saved_auto_align = md.auto_align;
4217 md.auto_align = saved_auto_align;
4221 dot_xfloat_cons (kind)
4224 char *name = parse_section_name ();
4228 md.keep_pending_output = 1;
4230 stmt_float_cons (kind);
4231 obj_elf_previous (0);
4232 md.keep_pending_output = 0;
4236 dot_xstringer (zero)
4239 char *name = parse_section_name ();
4243 md.keep_pending_output = 1;
4246 obj_elf_previous (0);
4247 md.keep_pending_output = 0;
4254 int saved_auto_align = md.auto_align;
4255 char *name = parse_section_name ();
4259 md.keep_pending_output = 1;
4263 md.auto_align = saved_auto_align;
4264 obj_elf_previous (0);
4265 md.keep_pending_output = 0;
4269 dot_xfloat_cons_ua (kind)
4272 int saved_auto_align = md.auto_align;
4273 char *name = parse_section_name ();
4277 md.keep_pending_output = 1;
4280 stmt_float_cons (kind);
4281 md.auto_align = saved_auto_align;
4282 obj_elf_previous (0);
4283 md.keep_pending_output = 0;
4286 /* .reg.val <regname>,value */
4290 int dummy ATTRIBUTE_UNUSED;
4295 if (reg.X_op != O_register)
4297 as_bad (_("Register name expected"));
4298 ignore_rest_of_line ();
4300 else if (*input_line_pointer++ != ',')
4302 as_bad (_("Comma expected"));
4303 ignore_rest_of_line ();
4307 valueT value = get_absolute_expression ();
4308 int regno = reg.X_add_number;
4309 if (regno < REG_GR || regno > REG_GR + 128)
4310 as_warn (_("Register value annotation ignored"));
4313 gr_values[regno - REG_GR].known = 1;
4314 gr_values[regno - REG_GR].value = value;
4315 gr_values[regno - REG_GR].path = md.path;
4318 demand_empty_rest_of_line ();
4321 /* select dv checking mode
4326 A stop is inserted when changing modes
4333 if (md.manual_bundling)
4334 as_warn (_("Directive invalid within a bundle"));
4336 if (type == 'E' || type == 'A')
4337 md.mode_explicitly_set = 0;
4339 md.mode_explicitly_set = 1;
4346 if (md.explicit_mode)
4347 insn_group_break (1, 0, 0);
4348 md.explicit_mode = 0;
4352 if (!md.explicit_mode)
4353 insn_group_break (1, 0, 0);
4354 md.explicit_mode = 1;
4358 if (md.explicit_mode != md.default_explicit_mode)
4359 insn_group_break (1, 0, 0);
4360 md.explicit_mode = md.default_explicit_mode;
4361 md.mode_explicitly_set = 0;
4372 for (regno = 0; regno < 64; regno++)
4374 if (mask & ((valueT) 1 << regno))
4376 fprintf (stderr, "%s p%d", comma, regno);
4383 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4384 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4385 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4386 .pred.safe_across_calls p1 [, p2 [,...]]
4395 int p1 = -1, p2 = -1;
4399 if (*input_line_pointer != '"')
4401 as_bad (_("Missing predicate relation type"));
4402 ignore_rest_of_line ();
4408 char *form = demand_copy_C_string (&len);
4409 if (strcmp (form, "mutex") == 0)
4411 else if (strcmp (form, "clear") == 0)
4413 else if (strcmp (form, "imply") == 0)
4417 as_bad (_("Unrecognized predicate relation type"));
4418 ignore_rest_of_line ();
4422 if (*input_line_pointer == ',')
4423 ++input_line_pointer;
4433 if (toupper (*input_line_pointer) != 'P'
4434 || (regno = atoi (++input_line_pointer)) < 0
4437 as_bad (_("Predicate register expected"));
4438 ignore_rest_of_line ();
4441 while (isdigit (*input_line_pointer))
4442 ++input_line_pointer;
4449 as_warn (_("Duplicate predicate register ignored"));
4452 /* See if it's a range. */
4453 if (*input_line_pointer == '-')
4456 ++input_line_pointer;
4458 if (toupper (*input_line_pointer) != 'P'
4459 || (regno = atoi (++input_line_pointer)) < 0
4462 as_bad (_("Predicate register expected"));
4463 ignore_rest_of_line ();
4466 while (isdigit (*input_line_pointer))
4467 ++input_line_pointer;
4471 as_bad (_("Bad register range"));
4472 ignore_rest_of_line ();
4483 if (*input_line_pointer != ',')
4485 ++input_line_pointer;
4494 clear_qp_mutex (mask);
4495 clear_qp_implies (mask, (valueT) 0);
4498 if (count != 2 || p1 == -1 || p2 == -1)
4499 as_bad (_("Predicate source and target required"));
4500 else if (p1 == 0 || p2 == 0)
4501 as_bad (_("Use of p0 is not valid in this context"));
4503 add_qp_imply (p1, p2);
4508 as_bad (_("At least two PR arguments expected"));
4513 as_bad (_("Use of p0 is not valid in this context"));
4516 add_qp_mutex (mask);
4519 /* note that we don't override any existing relations */
4522 as_bad (_("At least one PR argument expected"));
4527 fprintf (stderr, "Safe across calls: ");
4528 print_prmask (mask);
4529 fprintf (stderr, "\n");
4531 qp_safe_across_calls = mask;
4534 demand_empty_rest_of_line ();
4537 /* .entry label [, label [, ...]]
4538 Hint to DV code that the given labels are to be considered entry points.
4539 Otherwise, only global labels are considered entry points. */
4543 int dummy ATTRIBUTE_UNUSED;
4552 name = input_line_pointer;
4553 c = get_symbol_end ();
4554 symbolP = symbol_find_or_make (name);
4556 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4558 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4561 *input_line_pointer = c;
4563 c = *input_line_pointer;
4566 input_line_pointer++;
4568 if (*input_line_pointer == '\n')
4574 demand_empty_rest_of_line ();
4577 /* .mem.offset offset, base
4578 "base" is used to distinguish between offsets from a different base. */
4581 dot_mem_offset (dummy)
4582 int dummy ATTRIBUTE_UNUSED;
4584 md.mem_offset.hint = 1;
4585 md.mem_offset.offset = get_absolute_expression ();
4586 if (*input_line_pointer != ',')
4588 as_bad (_("Comma expected"));
4589 ignore_rest_of_line ();
4592 ++input_line_pointer;
4593 md.mem_offset.base = get_absolute_expression ();
4594 demand_empty_rest_of_line ();
4597 /* ia64-specific pseudo-ops: */
4598 const pseudo_typeS md_pseudo_table[] =
4600 { "radix", dot_radix, 0 },
4601 { "lcomm", s_lcomm_bytes, 1 },
4602 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4603 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4604 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4605 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4606 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4607 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4608 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4609 { "proc", dot_proc, 0 },
4610 { "body", dot_body, 0 },
4611 { "prologue", dot_prologue, 0 },
4612 { "endp", dot_endp, 0 },
4613 { "file", dwarf2_directive_file, 0 },
4614 { "loc", dwarf2_directive_loc, 0 },
4616 { "fframe", dot_fframe, 0 },
4617 { "vframe", dot_vframe, 0 },
4618 { "vframesp", dot_vframesp, 0 },
4619 { "vframepsp", dot_vframepsp, 0 },
4620 { "save", dot_save, 0 },
4621 { "restore", dot_restore, 0 },
4622 { "restorereg", dot_restorereg, 0 },
4623 { "restorereg.p", dot_restorereg_p, 0 },
4624 { "handlerdata", dot_handlerdata, 0 },
4625 { "unwentry", dot_unwentry, 0 },
4626 { "altrp", dot_altrp, 0 },
4627 { "savesp", dot_savemem, 0 },
4628 { "savepsp", dot_savemem, 1 },
4629 { "save.g", dot_saveg, 0 },
4630 { "save.f", dot_savef, 0 },
4631 { "save.b", dot_saveb, 0 },
4632 { "save.gf", dot_savegf, 0 },
4633 { "spill", dot_spill, 0 },
4634 { "spillreg", dot_spillreg, 0 },
4635 { "spillsp", dot_spillmem, 0 },
4636 { "spillpsp", dot_spillmem, 1 },
4637 { "spillreg.p", dot_spillreg_p, 0 },
4638 { "spillsp.p", dot_spillmem_p, 0 },
4639 { "spillpsp.p", dot_spillmem_p, 1 },
4640 { "label_state", dot_label_state, 0 },
4641 { "copy_state", dot_copy_state, 0 },
4642 { "unwabi", dot_unwabi, 0 },
4643 { "personality", dot_personality, 0 },
4645 { "estate", dot_estate, 0 },
4647 { "mii", dot_template, 0x0 },
4648 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4649 { "mlx", dot_template, 0x2 },
4650 { "mmi", dot_template, 0x4 },
4651 { "mfi", dot_template, 0x6 },
4652 { "mmf", dot_template, 0x7 },
4653 { "mib", dot_template, 0x8 },
4654 { "mbb", dot_template, 0x9 },
4655 { "bbb", dot_template, 0xb },
4656 { "mmb", dot_template, 0xc },
4657 { "mfb", dot_template, 0xe },
4659 { "lb", dot_scope, 0 },
4660 { "le", dot_scope, 1 },
4662 { "align", s_align_bytes, 0 },
4663 { "regstk", dot_regstk, 0 },
4664 { "rotr", dot_rot, DYNREG_GR },
4665 { "rotf", dot_rot, DYNREG_FR },
4666 { "rotp", dot_rot, DYNREG_PR },
4667 { "lsb", dot_byteorder, 0 },
4668 { "msb", dot_byteorder, 1 },
4669 { "psr", dot_psr, 0 },
4670 { "alias", dot_alias, 0 },
4671 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4673 { "xdata1", dot_xdata, 1 },
4674 { "xdata2", dot_xdata, 2 },
4675 { "xdata4", dot_xdata, 4 },
4676 { "xdata8", dot_xdata, 8 },
4677 { "xreal4", dot_xfloat_cons, 'f' },
4678 { "xreal8", dot_xfloat_cons, 'd' },
4679 { "xreal10", dot_xfloat_cons, 'x' },
4680 { "xstring", dot_xstringer, 0 },
4681 { "xstringz", dot_xstringer, 1 },
4683 /* unaligned versions: */
4684 { "xdata2.ua", dot_xdata_ua, 2 },
4685 { "xdata4.ua", dot_xdata_ua, 4 },
4686 { "xdata8.ua", dot_xdata_ua, 8 },
4687 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4688 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4689 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4691 /* annotations/DV checking support */
4692 { "entry", dot_entry, 0 },
4693 { "mem.offset", dot_mem_offset, 0 },
4694 { "pred.rel", dot_pred_rel, 0 },
4695 { "pred.rel.clear", dot_pred_rel, 'c' },
4696 { "pred.rel.imply", dot_pred_rel, 'i' },
4697 { "pred.rel.mutex", dot_pred_rel, 'm' },
4698 { "pred.safe_across_calls", dot_pred_rel, 's' },
4699 { "reg.val", dot_reg_val, 0 },
4700 { "auto", dot_dv_mode, 'a' },
4701 { "explicit", dot_dv_mode, 'e' },
4702 { "default", dot_dv_mode, 'd' },
4707 static const struct pseudo_opcode
4710 void (*handler) (int);
4715 /* these are more like pseudo-ops, but don't start with a dot */
4716 { "data1", cons, 1 },
4717 { "data2", cons, 2 },
4718 { "data4", cons, 4 },
4719 { "data8", cons, 8 },
4720 { "real4", stmt_float_cons, 'f' },
4721 { "real8", stmt_float_cons, 'd' },
4722 { "real10", stmt_float_cons, 'x' },
4723 { "string", stringer, 0 },
4724 { "stringz", stringer, 1 },
4726 /* unaligned versions: */
4727 { "data2.ua", stmt_cons_ua, 2 },
4728 { "data4.ua", stmt_cons_ua, 4 },
4729 { "data8.ua", stmt_cons_ua, 8 },
4730 { "real4.ua", float_cons, 'f' },
4731 { "real8.ua", float_cons, 'd' },
4732 { "real10.ua", float_cons, 'x' },
4735 /* Declare a register by creating a symbol for it and entering it in
4736 the symbol table. */
4739 declare_register (name, regnum)
4746 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4748 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4750 as_fatal ("Inserting \"%s\" into register table failed: %s",
4757 declare_register_set (prefix, num_regs, base_regnum)
4765 for (i = 0; i < num_regs; ++i)
4767 sprintf (name, "%s%u", prefix, i);
4768 declare_register (name, base_regnum + i);
4773 operand_width (opnd)
4774 enum ia64_opnd opnd;
4776 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4777 unsigned int bits = 0;
4781 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4782 bits += odesc->field[i].bits;
4787 static enum operand_match_result
4788 operand_match (idesc, index, e)
4789 const struct ia64_opcode *idesc;
4793 enum ia64_opnd opnd = idesc->operands[index];
4794 int bits, relocatable = 0;
4795 struct insn_fix *fix;
4802 case IA64_OPND_AR_CCV:
4803 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4804 return OPERAND_MATCH;
4807 case IA64_OPND_AR_PFS:
4808 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4809 return OPERAND_MATCH;
4813 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4814 return OPERAND_MATCH;
4818 if (e->X_op == O_register && e->X_add_number == REG_IP)
4819 return OPERAND_MATCH;
4823 if (e->X_op == O_register && e->X_add_number == REG_PR)
4824 return OPERAND_MATCH;
4827 case IA64_OPND_PR_ROT:
4828 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4829 return OPERAND_MATCH;
4833 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4834 return OPERAND_MATCH;
4837 case IA64_OPND_PSR_L:
4838 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4839 return OPERAND_MATCH;
4842 case IA64_OPND_PSR_UM:
4843 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4844 return OPERAND_MATCH;
4848 if (e->X_op == O_constant)
4850 if (e->X_add_number == 1)
4851 return OPERAND_MATCH;
4853 return OPERAND_OUT_OF_RANGE;
4858 if (e->X_op == O_constant)
4860 if (e->X_add_number == 8)
4861 return OPERAND_MATCH;
4863 return OPERAND_OUT_OF_RANGE;
4868 if (e->X_op == O_constant)
4870 if (e->X_add_number == 16)
4871 return OPERAND_MATCH;
4873 return OPERAND_OUT_OF_RANGE;
4877 /* register operands: */
4880 if (e->X_op == O_register && e->X_add_number >= REG_AR
4881 && e->X_add_number < REG_AR + 128)
4882 return OPERAND_MATCH;
4887 if (e->X_op == O_register && e->X_add_number >= REG_BR
4888 && e->X_add_number < REG_BR + 8)
4889 return OPERAND_MATCH;
4893 if (e->X_op == O_register && e->X_add_number >= REG_CR
4894 && e->X_add_number < REG_CR + 128)
4895 return OPERAND_MATCH;
4902 if (e->X_op == O_register && e->X_add_number >= REG_FR
4903 && e->X_add_number < REG_FR + 128)
4904 return OPERAND_MATCH;
4909 if (e->X_op == O_register && e->X_add_number >= REG_P
4910 && e->X_add_number < REG_P + 64)
4911 return OPERAND_MATCH;
4917 if (e->X_op == O_register && e->X_add_number >= REG_GR
4918 && e->X_add_number < REG_GR + 128)
4919 return OPERAND_MATCH;
4922 case IA64_OPND_R3_2:
4923 if (e->X_op == O_register && e->X_add_number >= REG_GR)
4925 if (e->X_add_number < REG_GR + 4)
4926 return OPERAND_MATCH;
4927 else if (e->X_add_number < REG_GR + 128)
4928 return OPERAND_OUT_OF_RANGE;
4932 /* indirect operands: */
4933 case IA64_OPND_CPUID_R3:
4934 case IA64_OPND_DBR_R3:
4935 case IA64_OPND_DTR_R3:
4936 case IA64_OPND_ITR_R3:
4937 case IA64_OPND_IBR_R3:
4938 case IA64_OPND_MSR_R3:
4939 case IA64_OPND_PKR_R3:
4940 case IA64_OPND_PMC_R3:
4941 case IA64_OPND_PMD_R3:
4942 case IA64_OPND_RR_R3:
4943 if (e->X_op == O_index && e->X_op_symbol
4944 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4945 == opnd - IA64_OPND_CPUID_R3))
4946 return OPERAND_MATCH;
4950 if (e->X_op == O_index && !e->X_op_symbol)
4951 return OPERAND_MATCH;
4954 /* immediate operands: */
4955 case IA64_OPND_CNT2a:
4956 case IA64_OPND_LEN4:
4957 case IA64_OPND_LEN6:
4958 bits = operand_width (idesc->operands[index]);
4959 if (e->X_op == O_constant)
4961 if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4962 return OPERAND_MATCH;
4964 return OPERAND_OUT_OF_RANGE;
4968 case IA64_OPND_CNT2b:
4969 if (e->X_op == O_constant)
4971 if ((bfd_vma) (e->X_add_number - 1) < 3)
4972 return OPERAND_MATCH;
4974 return OPERAND_OUT_OF_RANGE;
4978 case IA64_OPND_CNT2c:
4979 val = e->X_add_number;
4980 if (e->X_op == O_constant)
4982 if ((val == 0 || val == 7 || val == 15 || val == 16))
4983 return OPERAND_MATCH;
4985 return OPERAND_OUT_OF_RANGE;
4990 /* SOR must be an integer multiple of 8 */
4991 if (e->X_op == O_constant && e->X_add_number & 0x7)
4992 return OPERAND_OUT_OF_RANGE;
4995 if (e->X_op == O_constant)
4997 if ((bfd_vma) e->X_add_number <= 96)
4998 return OPERAND_MATCH;
5000 return OPERAND_OUT_OF_RANGE;
5004 case IA64_OPND_IMMU62:
5005 if (e->X_op == O_constant)
5007 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
5008 return OPERAND_MATCH;
5010 return OPERAND_OUT_OF_RANGE;
5014 /* FIXME -- need 62-bit relocation type */
5015 as_bad (_("62-bit relocation not yet implemented"));
5019 case IA64_OPND_IMMU64:
5020 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
5021 || e->X_op == O_subtract)
5023 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5024 fix->code = BFD_RELOC_IA64_IMM64;
5025 if (e->X_op != O_subtract)
5027 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5028 if (e->X_op == O_pseudo_fixup)
5032 fix->opnd = idesc->operands[index];
5035 ++CURR_SLOT.num_fixups;
5036 return OPERAND_MATCH;
5038 else if (e->X_op == O_constant)
5039 return OPERAND_MATCH;
5042 case IA64_OPND_CCNT5:
5043 case IA64_OPND_CNT5:
5044 case IA64_OPND_CNT6:
5045 case IA64_OPND_CPOS6a:
5046 case IA64_OPND_CPOS6b:
5047 case IA64_OPND_CPOS6c:
5048 case IA64_OPND_IMMU2:
5049 case IA64_OPND_IMMU7a:
5050 case IA64_OPND_IMMU7b:
5051 case IA64_OPND_IMMU21:
5052 case IA64_OPND_IMMU24:
5053 case IA64_OPND_MBTYPE4:
5054 case IA64_OPND_MHTYPE8:
5055 case IA64_OPND_POS6:
5056 bits = operand_width (idesc->operands[index]);
5057 if (e->X_op == O_constant)
5059 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5060 return OPERAND_MATCH;
5062 return OPERAND_OUT_OF_RANGE;
5066 case IA64_OPND_IMMU9:
5067 bits = operand_width (idesc->operands[index]);
5068 if (e->X_op == O_constant)
5070 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5072 int lobits = e->X_add_number & 0x3;
5073 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
5074 e->X_add_number |= (bfd_vma) 0x3;
5075 return OPERAND_MATCH;
5078 return OPERAND_OUT_OF_RANGE;
5082 case IA64_OPND_IMM44:
5083 /* least 16 bits must be zero */
5084 if ((e->X_add_number & 0xffff) != 0)
5085 /* XXX technically, this is wrong: we should not be issuing warning
5086 messages until we're sure this instruction pattern is going to
5088 as_warn (_("lower 16 bits of mask ignored"));
5090 if (e->X_op == O_constant)
5092 if (((e->X_add_number >= 0
5093 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44))
5094 || (e->X_add_number < 0
5095 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44))))
5098 if (e->X_add_number >= 0
5099 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
5101 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
5103 return OPERAND_MATCH;
5106 return OPERAND_OUT_OF_RANGE;
5110 case IA64_OPND_IMM17:
5111 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5112 if (e->X_op == O_constant)
5114 if (((e->X_add_number >= 0
5115 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17))
5116 || (e->X_add_number < 0
5117 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17))))
5120 if (e->X_add_number >= 0
5121 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
5123 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
5125 return OPERAND_MATCH;
5128 return OPERAND_OUT_OF_RANGE;
5132 case IA64_OPND_IMM14:
5133 case IA64_OPND_IMM22:
5135 case IA64_OPND_IMM1:
5136 case IA64_OPND_IMM8:
5137 case IA64_OPND_IMM8U4:
5138 case IA64_OPND_IMM8M1:
5139 case IA64_OPND_IMM8M1U4:
5140 case IA64_OPND_IMM8M1U8:
5141 case IA64_OPND_IMM9a:
5142 case IA64_OPND_IMM9b:
5143 bits = operand_width (idesc->operands[index]);
5144 if (relocatable && (e->X_op == O_symbol
5145 || e->X_op == O_subtract
5146 || e->X_op == O_pseudo_fixup))
5148 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5150 if (idesc->operands[index] == IA64_OPND_IMM14)
5151 fix->code = BFD_RELOC_IA64_IMM14;
5153 fix->code = BFD_RELOC_IA64_IMM22;
5155 if (e->X_op != O_subtract)
5157 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5158 if (e->X_op == O_pseudo_fixup)
5162 fix->opnd = idesc->operands[index];
5165 ++CURR_SLOT.num_fixups;
5166 return OPERAND_MATCH;
5168 else if (e->X_op != O_constant
5169 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
5170 return OPERAND_MISMATCH;
5172 if (opnd == IA64_OPND_IMM8M1U4)
5174 /* Zero is not valid for unsigned compares that take an adjusted
5175 constant immediate range. */
5176 if (e->X_add_number == 0)
5177 return OPERAND_OUT_OF_RANGE;
5179 /* Sign-extend 32-bit unsigned numbers, so that the following range
5180 checks will work. */
5181 val = e->X_add_number;
5182 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5183 && ((val & ((bfd_vma) 1 << 31)) != 0))
5184 val = ((val << 32) >> 32);
5186 /* Check for 0x100000000. This is valid because
5187 0x100000000-1 is the same as ((uint32_t) -1). */
5188 if (val == ((bfd_signed_vma) 1 << 32))
5189 return OPERAND_MATCH;
5193 else if (opnd == IA64_OPND_IMM8M1U8)
5195 /* Zero is not valid for unsigned compares that take an adjusted
5196 constant immediate range. */
5197 if (e->X_add_number == 0)
5198 return OPERAND_OUT_OF_RANGE;
5200 /* Check for 0x10000000000000000. */
5201 if (e->X_op == O_big)
5203 if (generic_bignum[0] == 0
5204 && generic_bignum[1] == 0
5205 && generic_bignum[2] == 0
5206 && generic_bignum[3] == 0
5207 && generic_bignum[4] == 1)
5208 return OPERAND_MATCH;
5210 return OPERAND_OUT_OF_RANGE;
5213 val = e->X_add_number - 1;
5215 else if (opnd == IA64_OPND_IMM8M1)
5216 val = e->X_add_number - 1;
5217 else if (opnd == IA64_OPND_IMM8U4)
5219 /* Sign-extend 32-bit unsigned numbers, so that the following range
5220 checks will work. */
5221 val = e->X_add_number;
5222 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5223 && ((val & ((bfd_vma) 1 << 31)) != 0))
5224 val = ((val << 32) >> 32);
5227 val = e->X_add_number;
5229 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1)))
5230 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1))))
5231 return OPERAND_MATCH;
5233 return OPERAND_OUT_OF_RANGE;
5235 case IA64_OPND_INC3:
5236 /* +/- 1, 4, 8, 16 */
5237 val = e->X_add_number;
5240 if (e->X_op == O_constant)
5242 if ((val == 1 || val == 4 || val == 8 || val == 16))
5243 return OPERAND_MATCH;
5245 return OPERAND_OUT_OF_RANGE;
5249 case IA64_OPND_TGT25:
5250 case IA64_OPND_TGT25b:
5251 case IA64_OPND_TGT25c:
5252 case IA64_OPND_TGT64:
5253 if (e->X_op == O_symbol)
5255 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5256 if (opnd == IA64_OPND_TGT25)
5257 fix->code = BFD_RELOC_IA64_PCREL21F;
5258 else if (opnd == IA64_OPND_TGT25b)
5259 fix->code = BFD_RELOC_IA64_PCREL21M;
5260 else if (opnd == IA64_OPND_TGT25c)
5261 fix->code = BFD_RELOC_IA64_PCREL21B;
5262 else if (opnd == IA64_OPND_TGT64)
5263 fix->code = BFD_RELOC_IA64_PCREL60B;
5267 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5268 fix->opnd = idesc->operands[index];
5271 ++CURR_SLOT.num_fixups;
5272 return OPERAND_MATCH;
5274 case IA64_OPND_TAG13:
5275 case IA64_OPND_TAG13b:
5279 return OPERAND_MATCH;
5282 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5283 /* There are no external relocs for TAG13/TAG13b fields, so we
5284 create a dummy reloc. This will not live past md_apply_fix3. */
5285 fix->code = BFD_RELOC_UNUSED;
5286 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5287 fix->opnd = idesc->operands[index];
5290 ++CURR_SLOT.num_fixups;
5291 return OPERAND_MATCH;
5301 return OPERAND_MISMATCH;
5310 memset (e, 0, sizeof (*e));
5313 if (*input_line_pointer != '}')
5315 sep = *input_line_pointer++;
5319 if (!md.manual_bundling)
5320 as_warn ("Found '}' when manual bundling is off");
5322 CURR_SLOT.manual_bundling_off = 1;
5323 md.manual_bundling = 0;
5329 /* Returns the next entry in the opcode table that matches the one in
5330 IDESC, and frees the entry in IDESC. If no matching entry is
5331 found, NULL is returned instead. */
5333 static struct ia64_opcode *
5334 get_next_opcode (struct ia64_opcode *idesc)
5336 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
5337 ia64_free_opcode (idesc);
5341 /* Parse the operands for the opcode and find the opcode variant that
5342 matches the specified operands, or NULL if no match is possible. */
5344 static struct ia64_opcode *
5345 parse_operands (idesc)
5346 struct ia64_opcode *idesc;
5348 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
5349 int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0;
5350 enum ia64_opnd expected_operand = IA64_OPND_NIL;
5351 enum operand_match_result result;
5353 char *first_arg = 0, *end, *saved_input_pointer;
5356 assert (strlen (idesc->name) <= 128);
5358 strcpy (mnemonic, idesc->name);
5359 if (idesc->operands[2] == IA64_OPND_SOF)
5361 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5362 can't parse the first operand until we have parsed the
5363 remaining operands of the "alloc" instruction. */
5365 first_arg = input_line_pointer;
5366 end = strchr (input_line_pointer, '=');
5369 as_bad ("Expected separator `='");
5372 input_line_pointer = end + 1;
5377 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
5379 sep = parse_operand (CURR_SLOT.opnd + i);
5380 if (CURR_SLOT.opnd[i].X_op == O_absent)
5385 if (sep != '=' && sep != ',')
5390 if (num_outputs > 0)
5391 as_bad ("Duplicate equal sign (=) in instruction");
5393 num_outputs = i + 1;
5398 as_bad ("Illegal operand separator `%c'", sep);
5402 if (idesc->operands[2] == IA64_OPND_SOF)
5404 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5405 know (strcmp (idesc->name, "alloc") == 0);
5406 if (num_operands == 5 /* first_arg not included in this count! */
5407 && CURR_SLOT.opnd[2].X_op == O_constant
5408 && CURR_SLOT.opnd[3].X_op == O_constant
5409 && CURR_SLOT.opnd[4].X_op == O_constant
5410 && CURR_SLOT.opnd[5].X_op == O_constant)
5412 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5413 CURR_SLOT.opnd[3].X_add_number,
5414 CURR_SLOT.opnd[4].X_add_number,
5415 CURR_SLOT.opnd[5].X_add_number);
5417 /* now we can parse the first arg: */
5418 saved_input_pointer = input_line_pointer;
5419 input_line_pointer = first_arg;
5420 sep = parse_operand (CURR_SLOT.opnd + 0);
5422 --num_outputs; /* force error */
5423 input_line_pointer = saved_input_pointer;
5425 CURR_SLOT.opnd[2].X_add_number = sof;
5426 CURR_SLOT.opnd[3].X_add_number
5427 = sof - CURR_SLOT.opnd[4].X_add_number;
5428 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5432 highest_unmatched_operand = 0;
5433 curr_out_of_range_pos = -1;
5435 expected_operand = idesc->operands[0];
5436 for (; idesc; idesc = get_next_opcode (idesc))
5438 if (num_outputs != idesc->num_outputs)
5439 continue; /* mismatch in # of outputs */
5441 CURR_SLOT.num_fixups = 0;
5443 /* Try to match all operands. If we see an out-of-range operand,
5444 then continue trying to match the rest of the operands, since if
5445 the rest match, then this idesc will give the best error message. */
5447 out_of_range_pos = -1;
5448 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5450 result = operand_match (idesc, i, CURR_SLOT.opnd + i);
5451 if (result != OPERAND_MATCH)
5453 if (result != OPERAND_OUT_OF_RANGE)
5455 if (out_of_range_pos < 0)
5456 /* remember position of the first out-of-range operand: */
5457 out_of_range_pos = i;
5461 /* If we did not match all operands, or if at least one operand was
5462 out-of-range, then this idesc does not match. Keep track of which
5463 idesc matched the most operands before failing. If we have two
5464 idescs that failed at the same position, and one had an out-of-range
5465 operand, then prefer the out-of-range operand. Thus if we have
5466 "add r0=0x1000000,r1" we get an error saying the constant is out
5467 of range instead of an error saying that the constant should have been
5470 if (i != num_operands || out_of_range_pos >= 0)
5472 if (i > highest_unmatched_operand
5473 || (i == highest_unmatched_operand
5474 && out_of_range_pos > curr_out_of_range_pos))
5476 highest_unmatched_operand = i;
5477 if (out_of_range_pos >= 0)
5479 expected_operand = idesc->operands[out_of_range_pos];
5480 error_pos = out_of_range_pos;
5484 expected_operand = idesc->operands[i];
5487 curr_out_of_range_pos = out_of_range_pos;
5492 if (num_operands < NELEMS (idesc->operands)
5493 && idesc->operands[num_operands])
5494 continue; /* mismatch in number of arguments */
5500 if (expected_operand)
5501 as_bad ("Operand %u of `%s' should be %s",
5502 error_pos + 1, mnemonic,
5503 elf64_ia64_operands[expected_operand].desc);
5505 as_bad ("Operand mismatch");
5511 /* Keep track of state necessary to determine whether a NOP is necessary
5512 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5513 detect a case where additional NOPs may be necessary. */
5515 errata_nop_necessary_p (slot, insn_unit)
5517 enum ia64_unit insn_unit;
5520 struct group *this_group = md.last_groups + md.group_idx;
5521 struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3;
5522 struct ia64_opcode *idesc = slot->idesc;
5524 /* Test whether this could be the first insn in a problematic sequence. */
5525 if (insn_unit == IA64_UNIT_F)
5527 for (i = 0; i < idesc->num_outputs; i++)
5528 if (idesc->operands[i] == IA64_OPND_P1
5529 || idesc->operands[i] == IA64_OPND_P2)
5531 int regno = slot->opnd[i].X_add_number - REG_P;
5532 /* Ignore invalid operands; they generate errors elsewhere. */
5535 this_group->p_reg_set[regno] = 1;
5539 /* Test whether this could be the second insn in a problematic sequence. */
5540 if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0
5541 && prev_group->p_reg_set[slot->qp_regno])
5543 for (i = 0; i < idesc->num_outputs; i++)
5544 if (idesc->operands[i] == IA64_OPND_R1
5545 || idesc->operands[i] == IA64_OPND_R2
5546 || idesc->operands[i] == IA64_OPND_R3)
5548 int regno = slot->opnd[i].X_add_number - REG_GR;
5549 /* Ignore invalid operands; they generate errors elsewhere. */
5552 if (strncmp (idesc->name, "add", 3) != 0
5553 && strncmp (idesc->name, "sub", 3) != 0
5554 && strncmp (idesc->name, "shladd", 6) != 0
5555 && (idesc->flags & IA64_OPCODE_POSTINC) == 0)
5556 this_group->g_reg_set_conditionally[regno] = 1;
5560 /* Test whether this could be the third insn in a problematic sequence. */
5561 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++)
5563 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5564 idesc->operands[i] == IA64_OPND_R3
5565 /* For mov indirect. */
5566 || idesc->operands[i] == IA64_OPND_RR_R3
5567 || idesc->operands[i] == IA64_OPND_DBR_R3
5568 || idesc->operands[i] == IA64_OPND_IBR_R3
5569 || idesc->operands[i] == IA64_OPND_PKR_R3
5570 || idesc->operands[i] == IA64_OPND_PMC_R3
5571 || idesc->operands[i] == IA64_OPND_PMD_R3
5572 || idesc->operands[i] == IA64_OPND_MSR_R3
5573 || idesc->operands[i] == IA64_OPND_CPUID_R3
5575 || idesc->operands[i] == IA64_OPND_ITR_R3
5576 || idesc->operands[i] == IA64_OPND_DTR_R3
5577 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5578 || idesc->operands[i] == IA64_OPND_MR3)
5580 int regno = slot->opnd[i].X_add_number - REG_GR;
5581 /* Ignore invalid operands; they generate errors elsewhere. */
5584 if (idesc->operands[i] == IA64_OPND_R3)
5586 if (strcmp (idesc->name, "fc") != 0
5587 && strcmp (idesc->name, "tak") != 0
5588 && strcmp (idesc->name, "thash") != 0
5589 && strcmp (idesc->name, "tpa") != 0
5590 && strcmp (idesc->name, "ttag") != 0
5591 && strncmp (idesc->name, "ptr", 3) != 0
5592 && strncmp (idesc->name, "ptc", 3) != 0
5593 && strncmp (idesc->name, "probe", 5) != 0)
5596 if (prev_group->g_reg_set_conditionally[regno])
5604 build_insn (slot, insnp)
5608 const struct ia64_operand *odesc, *o2desc;
5609 struct ia64_opcode *idesc = slot->idesc;
5610 bfd_signed_vma insn, val;
5614 insn = idesc->opcode | slot->qp_regno;
5616 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5618 if (slot->opnd[i].X_op == O_register
5619 || slot->opnd[i].X_op == O_constant
5620 || slot->opnd[i].X_op == O_index)
5621 val = slot->opnd[i].X_add_number;
5622 else if (slot->opnd[i].X_op == O_big)
5624 /* This must be the value 0x10000000000000000. */
5625 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5631 switch (idesc->operands[i])
5633 case IA64_OPND_IMMU64:
5634 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5635 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5636 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5637 | (((val >> 63) & 0x1) << 36));
5640 case IA64_OPND_IMMU62:
5641 val &= 0x3fffffffffffffffULL;
5642 if (val != slot->opnd[i].X_add_number)
5643 as_warn (_("Value truncated to 62 bits"));
5644 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5645 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
5648 case IA64_OPND_TGT64:
5650 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5651 insn |= ((((val >> 59) & 0x1) << 36)
5652 | (((val >> 0) & 0xfffff) << 13));
5683 case IA64_OPND_R3_2:
5684 case IA64_OPND_CPUID_R3:
5685 case IA64_OPND_DBR_R3:
5686 case IA64_OPND_DTR_R3:
5687 case IA64_OPND_ITR_R3:
5688 case IA64_OPND_IBR_R3:
5690 case IA64_OPND_MSR_R3:
5691 case IA64_OPND_PKR_R3:
5692 case IA64_OPND_PMC_R3:
5693 case IA64_OPND_PMD_R3:
5694 case IA64_OPND_RR_R3:
5702 odesc = elf64_ia64_operands + idesc->operands[i];
5703 err = (*odesc->insert) (odesc, val, &insn);
5705 as_bad_where (slot->src_file, slot->src_line,
5706 "Bad operand value: %s", err);
5707 if (idesc->flags & IA64_OPCODE_PSEUDO)
5709 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5710 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5712 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5713 (*o2desc->insert) (o2desc, val, &insn);
5715 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5716 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5717 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
5719 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5720 (*o2desc->insert) (o2desc, 64 - val, &insn);
5730 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5731 unsigned int manual_bundling = 0;
5732 enum ia64_unit required_unit, insn_unit = 0;
5733 enum ia64_insn_type type[3], insn_type;
5734 unsigned int template, orig_template;
5735 bfd_vma insn[3] = { -1, -1, -1 };
5736 struct ia64_opcode *idesc;
5737 int end_of_insn_group = 0, user_template = -1;
5738 int n, i, j, first, curr;
5740 bfd_vma t0 = 0, t1 = 0;
5741 struct label_fix *lfix;
5742 struct insn_fix *ifix;
5747 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5748 know (first >= 0 & first < NUM_SLOTS);
5749 n = MIN (3, md.num_slots_in_use);
5751 /* Determine template: user user_template if specified, best match
5754 if (md.slot[first].user_template >= 0)
5755 user_template = template = md.slot[first].user_template;
5758 /* Auto select appropriate template. */
5759 memset (type, 0, sizeof (type));
5761 for (i = 0; i < n; ++i)
5763 if (md.slot[curr].label_fixups && i != 0)
5765 type[i] = md.slot[curr].idesc->type;
5766 curr = (curr + 1) % NUM_SLOTS;
5768 template = best_template[type[0]][type[1]][type[2]];
5771 /* initialize instructions with appropriate nops: */
5772 for (i = 0; i < 3; ++i)
5773 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5777 /* now fill in slots with as many insns as possible: */
5779 idesc = md.slot[curr].idesc;
5780 end_of_insn_group = 0;
5781 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5783 /* Set the slot number for prologue/body records now as those
5784 refer to the current point, not the point after the
5785 instruction has been issued: */
5786 /* Don't try to delete prologue/body records here, as that will cause
5787 them to also be deleted from the master list of unwind records. */
5788 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5789 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5790 || ptr->r.type == body)
5792 ptr->slot_number = (unsigned long) f + i;
5793 ptr->slot_frag = frag_now;
5796 if (idesc->flags & IA64_OPCODE_SLOT2)
5798 if (manual_bundling && i != 2)
5799 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5800 "`%s' must be last in bundle", idesc->name);
5804 if (idesc->flags & IA64_OPCODE_LAST)
5807 unsigned int required_template;
5809 /* If we need a stop bit after an M slot, our only choice is
5810 template 5 (M;;MI). If we need a stop bit after a B
5811 slot, our only choice is to place it at the end of the
5812 bundle, because the only available templates are MIB,
5813 MBB, BBB, MMB, and MFB. We don't handle anything other
5814 than M and B slots because these are the only kind of
5815 instructions that can have the IA64_OPCODE_LAST bit set. */
5816 required_template = template;
5817 switch (idesc->type)
5821 required_template = 5;
5829 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5830 "Internal error: don't know how to force %s to end"
5831 "of instruction group", idesc->name);
5835 if (manual_bundling && i != required_slot)
5836 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5837 "`%s' must be last in instruction group",
5839 if (required_slot < i)
5840 /* Can't fit this instruction. */
5844 if (required_template != template)
5846 /* If we switch the template, we need to reset the NOPs
5847 after slot i. The slot-types of the instructions ahead
5848 of i never change, so we don't need to worry about
5849 changing NOPs in front of this slot. */
5850 for (j = i; j < 3; ++j)
5851 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5853 template = required_template;
5855 if (curr != first && md.slot[curr].label_fixups)
5857 if (manual_bundling_on)
5858 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5859 "Label must be first in a bundle");
5860 /* This insn must go into the first slot of a bundle. */
5864 manual_bundling_on = md.slot[curr].manual_bundling_on;
5865 manual_bundling_off = md.slot[curr].manual_bundling_off;
5867 if (manual_bundling_on)
5870 manual_bundling = 1;
5872 break; /* need to start a new bundle */
5875 if (end_of_insn_group && md.num_slots_in_use >= 1)
5877 /* We need an instruction group boundary in the middle of a
5878 bundle. See if we can switch to an other template with
5879 an appropriate boundary. */
5881 orig_template = template;
5882 if (i == 1 && (user_template == 4
5883 || (user_template < 0
5884 && (ia64_templ_desc[template].exec_unit[0]
5888 end_of_insn_group = 0;
5890 else if (i == 2 && (user_template == 0
5891 || (user_template < 0
5892 && (ia64_templ_desc[template].exec_unit[1]
5894 /* This test makes sure we don't switch the template if
5895 the next instruction is one that needs to be first in
5896 an instruction group. Since all those instructions are
5897 in the M group, there is no way such an instruction can
5898 fit in this bundle even if we switch the template. The
5899 reason we have to check for this is that otherwise we
5900 may end up generating "MI;;I M.." which has the deadly
5901 effect that the second M instruction is no longer the
5902 first in the bundle! --davidm 99/12/16 */
5903 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5906 end_of_insn_group = 0;
5908 else if (curr != first)
5909 /* can't fit this insn */
5912 if (template != orig_template)
5913 /* if we switch the template, we need to reset the NOPs
5914 after slot i. The slot-types of the instructions ahead
5915 of i never change, so we don't need to worry about
5916 changing NOPs in front of this slot. */
5917 for (j = i; j < 3; ++j)
5918 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5920 required_unit = ia64_templ_desc[template].exec_unit[i];
5922 /* resolve dynamic opcodes such as "break" and "nop": */
5923 if (idesc->type == IA64_TYPE_DYN)
5925 if ((strcmp (idesc->name, "nop") == 0)
5926 || (strcmp (idesc->name, "break") == 0))
5927 insn_unit = required_unit;
5928 else if (strcmp (idesc->name, "chk.s") == 0)
5930 insn_unit = IA64_UNIT_M;
5931 if (required_unit == IA64_UNIT_I)
5932 insn_unit = IA64_UNIT_I;
5935 as_fatal ("emit_one_bundle: unexpected dynamic op");
5937 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
5938 ia64_free_opcode (idesc);
5939 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5941 know (!idesc->next); /* no resolved dynamic ops have collisions */
5946 insn_type = idesc->type;
5947 insn_unit = IA64_UNIT_NIL;
5951 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5952 insn_unit = required_unit;
5954 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
5955 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5956 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5957 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5958 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5963 if (insn_unit != required_unit)
5965 if (required_unit == IA64_UNIT_L
5966 && insn_unit == IA64_UNIT_I
5967 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5969 /* we got ourselves an MLX template but the current
5970 instruction isn't an X-unit, or an I-unit instruction
5971 that can go into the X slot of an MLX template. Duh. */
5972 if (md.num_slots_in_use >= NUM_SLOTS)
5974 as_bad_where (md.slot[curr].src_file,
5975 md.slot[curr].src_line,
5976 "`%s' can't go in X slot of "
5977 "MLX template", idesc->name);
5978 /* drop this insn so we don't livelock: */
5979 --md.num_slots_in_use;
5983 continue; /* try next slot */
5989 addr = frag_now->fr_address + frag_now_fix () - 16 + i;
5990 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5993 if (errata_nop_necessary_p (md.slot + curr, insn_unit))
5994 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
5996 build_insn (md.slot + curr, insn + i);
5998 /* Set slot counts for non prologue/body unwind records. */
5999 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
6000 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
6001 && ptr->r.type != body)
6003 ptr->slot_number = (unsigned long) f + i;
6004 ptr->slot_frag = frag_now;
6006 md.slot[curr].unwind_record = NULL;
6008 if (required_unit == IA64_UNIT_L)
6011 /* skip one slot for long/X-unit instructions */
6014 --md.num_slots_in_use;
6016 /* now is a good time to fix up the labels for this insn: */
6017 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
6019 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
6020 symbol_set_frag (lfix->sym, frag_now);
6022 /* and fix up the tags also. */
6023 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
6025 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
6026 symbol_set_frag (lfix->sym, frag_now);
6029 for (j = 0; j < md.slot[curr].num_fixups; ++j)
6031 ifix = md.slot[curr].fixup + j;
6032 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8,
6033 &ifix->expr, ifix->is_pcrel, ifix->code);
6034 fix->tc_fix_data.opnd = ifix->opnd;
6035 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
6036 fix->fx_file = md.slot[curr].src_file;
6037 fix->fx_line = md.slot[curr].src_line;
6040 end_of_insn_group = md.slot[curr].end_of_insn_group;
6042 if (end_of_insn_group)
6044 md.group_idx = (md.group_idx + 1) % 3;
6045 memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]);
6049 ia64_free_opcode (md.slot[curr].idesc);
6050 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
6051 md.slot[curr].user_template = -1;
6053 if (manual_bundling_off)
6055 manual_bundling = 0;
6058 curr = (curr + 1) % NUM_SLOTS;
6059 idesc = md.slot[curr].idesc;
6061 if (manual_bundling)
6063 if (md.num_slots_in_use > 0)
6064 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6065 "`%s' does not fit into %s template",
6066 idesc->name, ia64_templ_desc[template].name);
6068 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6069 "Missing '}' at end of file");
6071 know (md.num_slots_in_use < NUM_SLOTS);
6073 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
6074 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
6076 number_to_chars_littleendian (f + 0, t0, 8);
6077 number_to_chars_littleendian (f + 8, t1, 8);
6079 unwind.next_slot_number = (unsigned long) f + 16;
6080 unwind.next_slot_frag = frag_now;
6084 md_parse_option (c, arg)
6091 /* Switches from the Intel assembler. */
6093 if (strcmp (arg, "ilp64") == 0
6094 || strcmp (arg, "lp64") == 0
6095 || strcmp (arg, "p64") == 0)
6097 md.flags |= EF_IA_64_ABI64;
6099 else if (strcmp (arg, "ilp32") == 0)
6101 md.flags &= ~EF_IA_64_ABI64;
6103 else if (strcmp (arg, "le") == 0)
6105 md.flags &= ~EF_IA_64_BE;
6107 else if (strcmp (arg, "be") == 0)
6109 md.flags |= EF_IA_64_BE;
6116 if (strcmp (arg, "so") == 0)
6118 /* Suppress signon message. */
6120 else if (strcmp (arg, "pi") == 0)
6122 /* Reject privileged instructions. FIXME */
6124 else if (strcmp (arg, "us") == 0)
6126 /* Allow union of signed and unsigned range. FIXME */
6128 else if (strcmp (arg, "close_fcalls") == 0)
6130 /* Do not resolve global function calls. */
6137 /* temp[="prefix"] Insert temporary labels into the object file
6138 symbol table prefixed by "prefix".
6139 Default prefix is ":temp:".
6144 /* indirect=<tgt> Assume unannotated indirect branches behavior
6145 according to <tgt> --
6146 exit: branch out from the current context (default)
6147 labels: all labels in context may be branch targets
6149 if (strncmp (arg, "indirect=", 9) != 0)
6154 /* -X conflicts with an ignored option, use -x instead */
6156 if (!arg || strcmp (arg, "explicit") == 0)
6158 /* set default mode to explicit */
6159 md.default_explicit_mode = 1;
6162 else if (strcmp (arg, "auto") == 0)
6164 md.default_explicit_mode = 0;
6166 else if (strcmp (arg, "debug") == 0)
6170 else if (strcmp (arg, "debugx") == 0)
6172 md.default_explicit_mode = 1;
6177 as_bad (_("Unrecognized option '-x%s'"), arg);
6182 /* nops Print nops statistics. */
6185 /* GNU specific switches for gcc. */
6186 case OPTION_MCONSTANT_GP:
6187 md.flags |= EF_IA_64_CONS_GP;
6190 case OPTION_MAUTO_PIC:
6191 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
6202 md_show_usage (stream)
6207 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6208 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6209 -x | -xexplicit turn on dependency violation checking (default)\n\
6210 -xauto automagically remove dependency violations\n\
6211 -xdebug debug dependency violation checker\n"),
6215 /* Return true if TYPE fits in TEMPL at SLOT. */
6218 match (int templ, int type, int slot)
6220 enum ia64_unit unit;
6223 unit = ia64_templ_desc[templ].exec_unit[slot];
6226 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
6228 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
6230 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
6231 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
6232 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
6233 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
6234 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
6235 default: result = 0; break;
6240 /* Add a bit of extra goodness if a nop of type F or B would fit
6241 in TEMPL at SLOT. */
6244 extra_goodness (int templ, int slot)
6246 if (slot == 1 && match (templ, IA64_TYPE_F, slot))
6248 if (slot == 2 && match (templ, IA64_TYPE_B, slot))
6253 /* This function is called once, at assembler startup time. It sets
6254 up all the tables, etc. that the MD part of the assembler will need
6255 that can be determined before arguments are parsed. */
6259 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
6264 md.explicit_mode = md.default_explicit_mode;
6266 bfd_set_section_alignment (stdoutput, text_section, 4);
6268 target_big_endian = TARGET_BYTES_BIG_ENDIAN;
6269 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
6270 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
6271 &zero_address_frag);
6273 pseudo_func[FUNC_GP_RELATIVE].u.sym =
6274 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
6275 &zero_address_frag);
6277 pseudo_func[FUNC_LT_RELATIVE].u.sym =
6278 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
6279 &zero_address_frag);
6281 pseudo_func[FUNC_PC_RELATIVE].u.sym =
6282 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
6283 &zero_address_frag);
6285 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
6286 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
6287 &zero_address_frag);
6289 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
6290 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
6291 &zero_address_frag);
6293 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
6294 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
6295 &zero_address_frag);
6297 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
6298 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
6299 &zero_address_frag);
6301 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
6302 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
6303 &zero_address_frag);
6305 /* Compute the table of best templates. We compute goodness as a
6306 base 4 value, in which each match counts for 3, each F counts
6307 for 2, each B counts for 1. This should maximize the number of
6308 F and B nops in the chosen bundles, which is good because these
6309 pipelines are least likely to be overcommitted. */
6310 for (i = 0; i < IA64_NUM_TYPES; ++i)
6311 for (j = 0; j < IA64_NUM_TYPES; ++j)
6312 for (k = 0; k < IA64_NUM_TYPES; ++k)
6315 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
6318 if (match (t, i, 0))
6320 if (match (t, j, 1))
6322 if (match (t, k, 2))
6323 goodness = 3 + 3 + 3;
6325 goodness = 3 + 3 + extra_goodness (t, 2);
6327 else if (match (t, j, 2))
6328 goodness = 3 + 3 + extra_goodness (t, 1);
6332 goodness += extra_goodness (t, 1);
6333 goodness += extra_goodness (t, 2);
6336 else if (match (t, i, 1))
6338 if (match (t, j, 2))
6341 goodness = 3 + extra_goodness (t, 2);
6343 else if (match (t, i, 2))
6344 goodness = 3 + extra_goodness (t, 1);
6346 if (goodness > best)
6349 best_template[i][j][k] = t;
6354 for (i = 0; i < NUM_SLOTS; ++i)
6355 md.slot[i].user_template = -1;
6357 md.pseudo_hash = hash_new ();
6358 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
6360 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
6361 (void *) (pseudo_opcode + i));
6363 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6364 pseudo_opcode[i].name, err);
6367 md.reg_hash = hash_new ();
6368 md.dynreg_hash = hash_new ();
6369 md.const_hash = hash_new ();
6370 md.entry_hash = hash_new ();
6372 /* general registers: */
6375 for (i = 0; i < total; ++i)
6377 sprintf (name, "r%d", i - REG_GR);
6378 md.regsym[i] = declare_register (name, i);
6381 /* floating point registers: */
6383 for (; i < total; ++i)
6385 sprintf (name, "f%d", i - REG_FR);
6386 md.regsym[i] = declare_register (name, i);
6389 /* application registers: */
6392 for (; i < total; ++i)
6394 sprintf (name, "ar%d", i - REG_AR);
6395 md.regsym[i] = declare_register (name, i);
6398 /* control registers: */
6401 for (; i < total; ++i)
6403 sprintf (name, "cr%d", i - REG_CR);
6404 md.regsym[i] = declare_register (name, i);
6407 /* predicate registers: */
6409 for (; i < total; ++i)
6411 sprintf (name, "p%d", i - REG_P);
6412 md.regsym[i] = declare_register (name, i);
6415 /* branch registers: */
6417 for (; i < total; ++i)
6419 sprintf (name, "b%d", i - REG_BR);
6420 md.regsym[i] = declare_register (name, i);
6423 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
6424 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
6425 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
6426 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
6427 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
6428 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
6429 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
6431 for (i = 0; i < NELEMS (indirect_reg); ++i)
6433 regnum = indirect_reg[i].regnum;
6434 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
6437 /* define synonyms for application registers: */
6438 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
6439 md.regsym[i] = declare_register (ar[i - REG_AR].name,
6440 REG_AR + ar[i - REG_AR].regnum);
6442 /* define synonyms for control registers: */
6443 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
6444 md.regsym[i] = declare_register (cr[i - REG_CR].name,
6445 REG_CR + cr[i - REG_CR].regnum);
6447 declare_register ("gp", REG_GR + 1);
6448 declare_register ("sp", REG_GR + 12);
6449 declare_register ("rp", REG_BR + 0);
6451 /* pseudo-registers used to specify unwind info: */
6452 declare_register ("psp", REG_PSP);
6454 declare_register_set ("ret", 4, REG_GR + 8);
6455 declare_register_set ("farg", 8, REG_FR + 8);
6456 declare_register_set ("fret", 8, REG_FR + 8);
6458 for (i = 0; i < NELEMS (const_bits); ++i)
6460 err = hash_insert (md.const_hash, const_bits[i].name,
6461 (PTR) (const_bits + i));
6463 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6467 /* Set the architecture and machine depending on defaults and command line
6469 if (md.flags & EF_IA_64_ABI64)
6470 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64);
6472 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32);
6475 as_warn (_("Could not set architecture and machine"));
6477 md.mem_offset.hint = 0;
6480 md.entry_labels = NULL;
6483 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6484 because that is called after md_parse_option which is where we do the
6485 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6486 default endianness. */
6489 ia64_init (argc, argv)
6490 int argc ATTRIBUTE_UNUSED;
6491 char **argv ATTRIBUTE_UNUSED;
6493 md.flags = EF_IA_64_ABI64;
6494 if (TARGET_BYTES_BIG_ENDIAN)
6495 md.flags |= EF_IA_64_BE;
6498 /* Return a string for the target object file format. */
6501 ia64_target_format ()
6503 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6505 if (md.flags & EF_IA_64_BE)
6507 if (md.flags & EF_IA_64_ABI64)
6509 return "elf64-ia64-aix-big";
6511 return "elf64-ia64-big";
6515 return "elf32-ia64-aix-big";
6517 return "elf32-ia64-big";
6522 if (md.flags & EF_IA_64_ABI64)
6524 return "elf64-ia64-aix-little";
6526 return "elf64-ia64-little";
6530 return "elf32-ia64-aix-little";
6532 return "elf32-ia64-little";
6537 return "unknown-format";
6541 ia64_end_of_source ()
6543 /* terminate insn group upon reaching end of file: */
6544 insn_group_break (1, 0, 0);
6546 /* emits slots we haven't written yet: */
6547 ia64_flush_insns ();
6549 bfd_set_private_flags (stdoutput, md.flags);
6551 md.mem_offset.hint = 0;
6557 if (md.qp.X_op == O_register)
6558 as_bad ("qualifying predicate not followed by instruction");
6559 md.qp.X_op = O_absent;
6561 if (ignore_input ())
6564 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
6566 if (md.detect_dv && !md.explicit_mode)
6567 as_warn (_("Explicit stops are ignored in auto mode"));
6569 insn_group_break (1, 0, 0);
6573 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6575 static int defining_tag = 0;
6578 ia64_unrecognized_line (ch)
6584 expression (&md.qp);
6585 if (*input_line_pointer++ != ')')
6587 as_bad ("Expected ')'");
6590 if (md.qp.X_op != O_register)
6592 as_bad ("Qualifying predicate expected");
6595 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
6597 as_bad ("Predicate register expected");
6603 if (md.manual_bundling)
6604 as_warn ("Found '{' when manual bundling is already turned on");
6606 CURR_SLOT.manual_bundling_on = 1;
6607 md.manual_bundling = 1;
6609 /* Bundling is only acceptable in explicit mode
6610 or when in default automatic mode. */
6611 if (md.detect_dv && !md.explicit_mode)
6613 if (!md.mode_explicitly_set
6614 && !md.default_explicit_mode)
6617 as_warn (_("Found '{' after explicit switch to automatic mode"));
6622 if (!md.manual_bundling)
6623 as_warn ("Found '}' when manual bundling is off");
6625 PREV_SLOT.manual_bundling_off = 1;
6626 md.manual_bundling = 0;
6628 /* switch back to automatic mode, if applicable */
6631 && !md.mode_explicitly_set
6632 && !md.default_explicit_mode)
6635 /* Allow '{' to follow on the same line. We also allow ";;", but that
6636 happens automatically because ';' is an end of line marker. */
6638 if (input_line_pointer[0] == '{')
6640 input_line_pointer++;
6641 return ia64_unrecognized_line ('{');
6644 demand_empty_rest_of_line ();
6654 if (md.qp.X_op == O_register)
6656 as_bad ("Tag must come before qualifying predicate.");
6660 /* This implements just enough of read_a_source_file in read.c to
6661 recognize labels. */
6662 if (is_name_beginner (*input_line_pointer))
6664 s = input_line_pointer;
6665 c = get_symbol_end ();
6667 else if (LOCAL_LABELS_FB
6668 && isdigit ((unsigned char) *input_line_pointer))
6671 while (isdigit ((unsigned char) *input_line_pointer))
6672 temp = (temp * 10) + *input_line_pointer++ - '0';
6673 fb_label_instance_inc (temp);
6674 s = fb_label_name (temp, 0);
6675 c = *input_line_pointer;
6684 /* Put ':' back for error messages' sake. */
6685 *input_line_pointer++ = ':';
6686 as_bad ("Expected ':'");
6693 /* Put ':' back for error messages' sake. */
6694 *input_line_pointer++ = ':';
6695 if (*input_line_pointer++ != ']')
6697 as_bad ("Expected ']'");
6702 as_bad ("Tag name expected");
6712 /* Not a valid line. */
6717 ia64_frob_label (sym)
6720 struct label_fix *fix;
6722 /* Tags need special handling since they are not bundle breaks like
6726 fix = obstack_alloc (¬es, sizeof (*fix));
6728 fix->next = CURR_SLOT.tag_fixups;
6729 CURR_SLOT.tag_fixups = fix;
6734 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6736 md.last_text_seg = now_seg;
6737 fix = obstack_alloc (¬es, sizeof (*fix));
6739 fix->next = CURR_SLOT.label_fixups;
6740 CURR_SLOT.label_fixups = fix;
6742 /* Keep track of how many code entry points we've seen. */
6743 if (md.path == md.maxpaths)
6746 md.entry_labels = (const char **)
6747 xrealloc ((void *) md.entry_labels,
6748 md.maxpaths * sizeof (char *));
6750 md.entry_labels[md.path++] = S_GET_NAME (sym);
6755 ia64_flush_pending_output ()
6757 if (!md.keep_pending_output
6758 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6760 /* ??? This causes many unnecessary stop bits to be emitted.
6761 Unfortunately, it isn't clear if it is safe to remove this. */
6762 insn_group_break (1, 0, 0);
6763 ia64_flush_insns ();
6767 /* Do ia64-specific expression optimization. All that's done here is
6768 to transform index expressions that are either due to the indexing
6769 of rotating registers or due to the indexing of indirect register
6772 ia64_optimize_expr (l, op, r)
6781 if (l->X_op == O_register && r->X_op == O_constant)
6783 num_regs = (l->X_add_number >> 16);
6784 if ((unsigned) r->X_add_number >= num_regs)
6787 as_bad ("No current frame");
6789 as_bad ("Index out of range 0..%u", num_regs - 1);
6790 r->X_add_number = 0;
6792 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6795 else if (l->X_op == O_register && r->X_op == O_register)
6797 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6798 || l->X_add_number == IND_MEM)
6800 as_bad ("Indirect register set name expected");
6801 l->X_add_number = IND_CPUID;
6804 l->X_op_symbol = md.regsym[l->X_add_number];
6805 l->X_add_number = r->X_add_number;
6813 ia64_parse_name (name, e)
6817 struct const_desc *cdesc;
6818 struct dynreg *dr = 0;
6819 unsigned int regnum;
6823 /* first see if NAME is a known register name: */
6824 sym = hash_find (md.reg_hash, name);
6827 e->X_op = O_register;
6828 e->X_add_number = S_GET_VALUE (sym);
6832 cdesc = hash_find (md.const_hash, name);
6835 e->X_op = O_constant;
6836 e->X_add_number = cdesc->value;
6840 /* check for inN, locN, or outN: */
6844 if (name[1] == 'n' && isdigit (name[2]))
6852 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6860 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6873 /* The name is inN, locN, or outN; parse the register number. */
6874 regnum = strtoul (name, &end, 10);
6875 if (end > name && *end == '\0')
6877 if ((unsigned) regnum >= dr->num_regs)
6880 as_bad ("No current frame");
6882 as_bad ("Register number out of range 0..%u",
6886 e->X_op = O_register;
6887 e->X_add_number = dr->base + regnum;
6892 if ((dr = hash_find (md.dynreg_hash, name)))
6894 /* We've got ourselves the name of a rotating register set.
6895 Store the base register number in the low 16 bits of
6896 X_add_number and the size of the register set in the top 16
6898 e->X_op = O_register;
6899 e->X_add_number = dr->base | (dr->num_regs << 16);
6905 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6908 ia64_canonicalize_symbol_name (name)
6911 size_t len = strlen (name);
6912 if (len > 1 && name[len - 1] == '#')
6913 name[len - 1] = '\0';
6917 /* Return true if idesc is a conditional branch instruction. This excludes
6918 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
6919 because they always read/write resources regardless of the value of the
6920 qualifying predicate. br.ia must always use p0, and hence is always
6921 taken. Thus this function returns true for branches which can fall
6922 through, and which use no resources if they do fall through. */
6925 is_conditional_branch (idesc)
6926 struct ia64_opcode *idesc;
6928 /* br is a conditional branch. Everything that starts with br. except
6929 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
6930 Everything that starts with brl is a conditional branch. */
6931 return (idesc->name[0] == 'b' && idesc->name[1] == 'r'
6932 && (idesc->name[2] == '\0'
6933 || (idesc->name[2] == '.' && idesc->name[3] != 'i'
6934 && idesc->name[3] != 'c' && idesc->name[3] != 'w')
6935 || idesc->name[2] == 'l'
6936 /* br.cond, br.call, br.clr */
6937 || (idesc->name[2] == '.' && idesc->name[3] == 'c'
6938 && (idesc->name[4] == 'a' || idesc->name[4] == 'o'
6939 || (idesc->name[4] == 'l' && idesc->name[5] == 'r')))));
6942 /* Return whether the given opcode is a taken branch. If there's any doubt,
6946 is_taken_branch (idesc)
6947 struct ia64_opcode *idesc;
6949 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
6950 || strncmp (idesc->name, "br.ia", 5) == 0);
6953 /* Return whether the given opcode is an interruption or rfi. If there's any
6954 doubt, returns zero. */
6957 is_interruption_or_rfi (idesc)
6958 struct ia64_opcode *idesc;
6960 if (strcmp (idesc->name, "rfi") == 0)
6965 /* Returns the index of the given dependency in the opcode's list of chks, or
6966 -1 if there is no dependency. */
6969 depends_on (depind, idesc)
6971 struct ia64_opcode *idesc;
6974 const struct ia64_opcode_dependency *dep = idesc->dependencies;
6975 for (i = 0; i < dep->nchks; i++)
6977 if (depind == DEP (dep->chks[i]))
6983 /* Determine a set of specific resources used for a particular resource
6984 class. Returns the number of specific resources identified For those
6985 cases which are not determinable statically, the resource returned is
6988 Meanings of value in 'NOTE':
6989 1) only read/write when the register number is explicitly encoded in the
6991 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6992 accesses CFM when qualifying predicate is in the rotating region.
6993 3) general register value is used to specify an indirect register; not
6994 determinable statically.
6995 4) only read the given resource when bits 7:0 of the indirect index
6996 register value does not match the register number of the resource; not
6997 determinable statically.
6998 5) all rules are implementation specific.
6999 6) only when both the index specified by the reader and the index specified
7000 by the writer have the same value in bits 63:61; not determinable
7002 7) only access the specified resource when the corresponding mask bit is
7004 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7005 only read when these insns reference FR2-31
7006 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7007 written when these insns write FR32-127
7008 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7010 11) The target predicates are written independently of PR[qp], but source
7011 registers are only read if PR[qp] is true. Since the state of PR[qp]
7012 cannot statically be determined, all source registers are marked used.
7013 12) This insn only reads the specified predicate register when that
7014 register is the PR[qp].
7015 13) This reference to ld-c only applies to teh GR whose value is loaded
7016 with data returned from memory, not the post-incremented address register.
7017 14) The RSE resource includes the implementation-specific RSE internal
7018 state resources. At least one (and possibly more) of these resources are
7019 read by each instruction listed in IC:rse-readers. At least one (and
7020 possibly more) of these resources are written by each insn listed in
7022 15+16) Represents reserved instructions, which the assembler does not
7025 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7026 this code; there are no dependency violations based on memory access.
7029 #define MAX_SPECS 256
7034 specify_resource (dep, idesc, type, specs, note, path)
7035 const struct ia64_dependency *dep;
7036 struct ia64_opcode *idesc;
7037 int type; /* is this a DV chk or a DV reg? */
7038 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
7039 int note; /* resource note for this insn's usage */
7040 int path; /* which execution path to examine */
7047 if (dep->mode == IA64_DV_WAW
7048 || (dep->mode == IA64_DV_RAW && type == DV_REG)
7049 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
7052 /* template for any resources we identify */
7053 tmpl.dependency = dep;
7055 tmpl.insn_srlz = tmpl.data_srlz = 0;
7056 tmpl.qp_regno = CURR_SLOT.qp_regno;
7057 tmpl.link_to_qp_branch = 1;
7058 tmpl.mem_offset.hint = 0;
7061 tmpl.cmp_type = CMP_NONE;
7064 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7065 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7066 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7068 /* we don't need to track these */
7069 if (dep->semantics == IA64_DVS_NONE)
7072 switch (dep->specifier)
7077 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7079 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7080 if (regno >= 0 && regno <= 7)
7082 specs[count] = tmpl;
7083 specs[count++].index = regno;
7089 for (i = 0; i < 8; i++)
7091 specs[count] = tmpl;
7092 specs[count++].index = i;
7101 case IA64_RS_AR_UNAT:
7102 /* This is a mov =AR or mov AR= instruction. */
7103 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7105 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7106 if (regno == AR_UNAT)
7108 specs[count++] = tmpl;
7113 /* This is a spill/fill, or other instruction that modifies the
7116 /* Unless we can determine the specific bits used, mark the whole
7117 thing; bits 8:3 of the memory address indicate the bit used in
7118 UNAT. The .mem.offset hint may be used to eliminate a small
7119 subset of conflicts. */
7120 specs[count] = tmpl;
7121 if (md.mem_offset.hint)
7124 fprintf (stderr, " Using hint for spill/fill\n");
7125 /* The index isn't actually used, just set it to something
7126 approximating the bit index. */
7127 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
7128 specs[count].mem_offset.hint = 1;
7129 specs[count].mem_offset.offset = md.mem_offset.offset;
7130 specs[count++].mem_offset.base = md.mem_offset.base;
7134 specs[count++].specific = 0;
7142 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7144 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7145 if ((regno >= 8 && regno <= 15)
7146 || (regno >= 20 && regno <= 23)
7147 || (regno >= 31 && regno <= 39)
7148 || (regno >= 41 && regno <= 47)
7149 || (regno >= 67 && regno <= 111))
7151 specs[count] = tmpl;
7152 specs[count++].index = regno;
7165 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7167 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7168 if ((regno >= 48 && regno <= 63)
7169 || (regno >= 112 && regno <= 127))
7171 specs[count] = tmpl;
7172 specs[count++].index = regno;
7178 for (i = 48; i < 64; i++)
7180 specs[count] = tmpl;
7181 specs[count++].index = i;
7183 for (i = 112; i < 128; i++)
7185 specs[count] = tmpl;
7186 specs[count++].index = i;
7204 for (i = 0; i < idesc->num_outputs; i++)
7205 if (idesc->operands[i] == IA64_OPND_B1
7206 || idesc->operands[i] == IA64_OPND_B2)
7208 specs[count] = tmpl;
7209 specs[count++].index =
7210 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7215 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++)
7216 if (idesc->operands[i] == IA64_OPND_B1
7217 || idesc->operands[i] == IA64_OPND_B2)
7219 specs[count] = tmpl;
7220 specs[count++].index =
7221 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7227 case IA64_RS_CPUID: /* four or more registers */
7230 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
7232 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7233 if (regno >= 0 && regno < NELEMS (gr_values)
7236 specs[count] = tmpl;
7237 specs[count++].index = gr_values[regno].value & 0xFF;
7241 specs[count] = tmpl;
7242 specs[count++].specific = 0;
7252 case IA64_RS_DBR: /* four or more registers */
7255 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
7257 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7258 if (regno >= 0 && regno < NELEMS (gr_values)
7261 specs[count] = tmpl;
7262 specs[count++].index = gr_values[regno].value & 0xFF;
7266 specs[count] = tmpl;
7267 specs[count++].specific = 0;
7271 else if (note == 0 && !rsrc_write)
7273 specs[count] = tmpl;
7274 specs[count++].specific = 0;
7282 case IA64_RS_IBR: /* four or more registers */
7285 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
7287 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7288 if (regno >= 0 && regno < NELEMS (gr_values)
7291 specs[count] = tmpl;
7292 specs[count++].index = gr_values[regno].value & 0xFF;
7296 specs[count] = tmpl;
7297 specs[count++].specific = 0;
7310 /* These are implementation specific. Force all references to
7311 conflict with all other references. */
7312 specs[count] = tmpl;
7313 specs[count++].specific = 0;
7321 case IA64_RS_PKR: /* 16 or more registers */
7322 if (note == 3 || note == 4)
7324 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
7326 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7327 if (regno >= 0 && regno < NELEMS (gr_values)
7332 specs[count] = tmpl;
7333 specs[count++].index = gr_values[regno].value & 0xFF;
7336 for (i = 0; i < NELEMS (gr_values); i++)
7338 /* Uses all registers *except* the one in R3. */
7339 if ((unsigned)i != (gr_values[regno].value & 0xFF))
7341 specs[count] = tmpl;
7342 specs[count++].index = i;
7348 specs[count] = tmpl;
7349 specs[count++].specific = 0;
7356 specs[count] = tmpl;
7357 specs[count++].specific = 0;
7361 case IA64_RS_PMC: /* four or more registers */
7364 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
7365 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
7368 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
7370 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
7371 if (regno >= 0 && regno < NELEMS (gr_values)
7374 specs[count] = tmpl;
7375 specs[count++].index = gr_values[regno].value & 0xFF;
7379 specs[count] = tmpl;
7380 specs[count++].specific = 0;
7390 case IA64_RS_PMD: /* four or more registers */
7393 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
7395 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7396 if (regno >= 0 && regno < NELEMS (gr_values)
7399 specs[count] = tmpl;
7400 specs[count++].index = gr_values[regno].value & 0xFF;
7404 specs[count] = tmpl;
7405 specs[count++].specific = 0;
7415 case IA64_RS_RR: /* eight registers */
7418 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
7420 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7421 if (regno >= 0 && regno < NELEMS (gr_values)
7424 specs[count] = tmpl;
7425 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
7429 specs[count] = tmpl;
7430 specs[count++].specific = 0;
7434 else if (note == 0 && !rsrc_write)
7436 specs[count] = tmpl;
7437 specs[count++].specific = 0;
7445 case IA64_RS_CR_IRR:
7448 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7449 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
7451 && idesc->operands[1] == IA64_OPND_CR3
7454 for (i = 0; i < 4; i++)
7456 specs[count] = tmpl;
7457 specs[count++].index = CR_IRR0 + i;
7463 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7464 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7466 && regno <= CR_IRR3)
7468 specs[count] = tmpl;
7469 specs[count++].index = regno;
7478 case IA64_RS_CR_LRR:
7485 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7486 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7487 && (regno == CR_LRR0 || regno == CR_LRR1))
7489 specs[count] = tmpl;
7490 specs[count++].index = regno;
7498 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7500 specs[count] = tmpl;
7501 specs[count++].index =
7502 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7517 else if (rsrc_write)
7519 if (dep->specifier == IA64_RS_FRb
7520 && idesc->operands[0] == IA64_OPND_F1)
7522 specs[count] = tmpl;
7523 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
7528 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
7530 if (idesc->operands[i] == IA64_OPND_F2
7531 || idesc->operands[i] == IA64_OPND_F3
7532 || idesc->operands[i] == IA64_OPND_F4)
7534 specs[count] = tmpl;
7535 specs[count++].index =
7536 CURR_SLOT.opnd[i].X_add_number - REG_FR;
7545 /* This reference applies only to the GR whose value is loaded with
7546 data returned from memory. */
7547 specs[count] = tmpl;
7548 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7554 for (i = 0; i < idesc->num_outputs; i++)
7555 if (idesc->operands[i] == IA64_OPND_R1
7556 || idesc->operands[i] == IA64_OPND_R2
7557 || idesc->operands[i] == IA64_OPND_R3)
7559 specs[count] = tmpl;
7560 specs[count++].index =
7561 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7563 if (idesc->flags & IA64_OPCODE_POSTINC)
7564 for (i = 0; i < NELEMS (idesc->operands); i++)
7565 if (idesc->operands[i] == IA64_OPND_MR3)
7567 specs[count] = tmpl;
7568 specs[count++].index =
7569 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7574 /* Look for anything that reads a GR. */
7575 for (i = 0; i < NELEMS (idesc->operands); i++)
7577 if (idesc->operands[i] == IA64_OPND_MR3
7578 || idesc->operands[i] == IA64_OPND_CPUID_R3
7579 || idesc->operands[i] == IA64_OPND_DBR_R3
7580 || idesc->operands[i] == IA64_OPND_IBR_R3
7581 || idesc->operands[i] == IA64_OPND_MSR_R3
7582 || idesc->operands[i] == IA64_OPND_PKR_R3
7583 || idesc->operands[i] == IA64_OPND_PMC_R3
7584 || idesc->operands[i] == IA64_OPND_PMD_R3
7585 || idesc->operands[i] == IA64_OPND_RR_R3
7586 || ((i >= idesc->num_outputs)
7587 && (idesc->operands[i] == IA64_OPND_R1
7588 || idesc->operands[i] == IA64_OPND_R2
7589 || idesc->operands[i] == IA64_OPND_R3
7590 /* addl source register. */
7591 || idesc->operands[i] == IA64_OPND_R3_2)))
7593 specs[count] = tmpl;
7594 specs[count++].index =
7595 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7606 /* This is the same as IA64_RS_PRr, except that the register range is
7607 from 1 - 15, and there are no rotating register reads/writes here. */
7611 for (i = 1; i < 16; i++)
7613 specs[count] = tmpl;
7614 specs[count++].index = i;
7620 /* Mark only those registers indicated by the mask. */
7623 mask = CURR_SLOT.opnd[2].X_add_number;
7624 for (i = 1; i < 16; i++)
7625 if (mask & ((valueT) 1 << i))
7627 specs[count] = tmpl;
7628 specs[count++].index = i;
7636 else if (note == 11) /* note 11 implies note 1 as well */
7640 for (i = 0; i < idesc->num_outputs; i++)
7642 if (idesc->operands[i] == IA64_OPND_P1
7643 || idesc->operands[i] == IA64_OPND_P2)
7645 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7646 if (regno >= 1 && regno < 16)
7648 specs[count] = tmpl;
7649 specs[count++].index = regno;
7659 else if (note == 12)
7661 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7663 specs[count] = tmpl;
7664 specs[count++].index = CURR_SLOT.qp_regno;
7671 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7672 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7673 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7674 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7676 if ((idesc->operands[0] == IA64_OPND_P1
7677 || idesc->operands[0] == IA64_OPND_P2)
7678 && p1 >= 1 && p1 < 16)
7680 specs[count] = tmpl;
7681 specs[count].cmp_type =
7682 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7683 specs[count++].index = p1;
7685 if ((idesc->operands[1] == IA64_OPND_P1
7686 || idesc->operands[1] == IA64_OPND_P2)
7687 && p2 >= 1 && p2 < 16)
7689 specs[count] = tmpl;
7690 specs[count].cmp_type =
7691 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7692 specs[count++].index = p2;
7697 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7699 specs[count] = tmpl;
7700 specs[count++].index = CURR_SLOT.qp_regno;
7702 if (idesc->operands[1] == IA64_OPND_PR)
7704 for (i = 1; i < 16; i++)
7706 specs[count] = tmpl;
7707 specs[count++].index = i;
7718 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7719 simplified cases of this. */
7723 for (i = 16; i < 63; i++)
7725 specs[count] = tmpl;
7726 specs[count++].index = i;
7732 /* Mark only those registers indicated by the mask. */
7734 && idesc->operands[0] == IA64_OPND_PR)
7736 mask = CURR_SLOT.opnd[2].X_add_number;
7737 if (mask & ((valueT) 1<<16))
7738 for (i = 16; i < 63; i++)
7740 specs[count] = tmpl;
7741 specs[count++].index = i;
7745 && idesc->operands[0] == IA64_OPND_PR_ROT)
7747 for (i = 16; i < 63; i++)
7749 specs[count] = tmpl;
7750 specs[count++].index = i;
7758 else if (note == 11) /* note 11 implies note 1 as well */
7762 for (i = 0; i < idesc->num_outputs; i++)
7764 if (idesc->operands[i] == IA64_OPND_P1
7765 || idesc->operands[i] == IA64_OPND_P2)
7767 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7768 if (regno >= 16 && regno < 63)
7770 specs[count] = tmpl;
7771 specs[count++].index = regno;
7781 else if (note == 12)
7783 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
7785 specs[count] = tmpl;
7786 specs[count++].index = CURR_SLOT.qp_regno;
7793 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7794 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7795 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7796 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7798 if ((idesc->operands[0] == IA64_OPND_P1
7799 || idesc->operands[0] == IA64_OPND_P2)
7800 && p1 >= 16 && p1 < 63)
7802 specs[count] = tmpl;
7803 specs[count].cmp_type =
7804 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7805 specs[count++].index = p1;
7807 if ((idesc->operands[1] == IA64_OPND_P1
7808 || idesc->operands[1] == IA64_OPND_P2)
7809 && p2 >= 16 && p2 < 63)
7811 specs[count] = tmpl;
7812 specs[count].cmp_type =
7813 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7814 specs[count++].index = p2;
7819 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
7821 specs[count] = tmpl;
7822 specs[count++].index = CURR_SLOT.qp_regno;
7824 if (idesc->operands[1] == IA64_OPND_PR)
7826 for (i = 16; i < 63; i++)
7828 specs[count] = tmpl;
7829 specs[count++].index = i;
7841 /* Verify that the instruction is using the PSR bit indicated in
7845 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7847 if (dep->regindex < 6)
7849 specs[count++] = tmpl;
7852 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7854 if (dep->regindex < 32
7855 || dep->regindex == 35
7856 || dep->regindex == 36
7857 || (!rsrc_write && dep->regindex == PSR_CPL))
7859 specs[count++] = tmpl;
7862 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7864 if (dep->regindex < 32
7865 || dep->regindex == 35
7866 || dep->regindex == 36
7867 || (rsrc_write && dep->regindex == PSR_CPL))
7869 specs[count++] = tmpl;
7874 /* Several PSR bits have very specific dependencies. */
7875 switch (dep->regindex)
7878 specs[count++] = tmpl;
7883 specs[count++] = tmpl;
7887 /* Only certain CR accesses use PSR.ic */
7888 if (idesc->operands[0] == IA64_OPND_CR3
7889 || idesc->operands[1] == IA64_OPND_CR3)
7892 ((idesc->operands[0] == IA64_OPND_CR3)
7895 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7910 specs[count++] = tmpl;
7919 specs[count++] = tmpl;
7923 /* Only some AR accesses use cpl */
7924 if (idesc->operands[0] == IA64_OPND_AR3
7925 || idesc->operands[1] == IA64_OPND_AR3)
7928 ((idesc->operands[0] == IA64_OPND_AR3)
7931 CURR_SLOT.opnd[index].X_add_number - REG_AR;
7938 && regno <= AR_K7))))
7940 specs[count++] = tmpl;
7945 specs[count++] = tmpl;
7955 if (idesc->operands[0] == IA64_OPND_IMMU24)
7957 mask = CURR_SLOT.opnd[0].X_add_number;
7963 if (mask & ((valueT) 1 << dep->regindex))
7965 specs[count++] = tmpl;
7970 int min = dep->regindex == PSR_DFL ? 2 : 32;
7971 int max = dep->regindex == PSR_DFL ? 31 : 127;
7972 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7973 for (i = 0; i < NELEMS (idesc->operands); i++)
7975 if (idesc->operands[i] == IA64_OPND_F1
7976 || idesc->operands[i] == IA64_OPND_F2
7977 || idesc->operands[i] == IA64_OPND_F3
7978 || idesc->operands[i] == IA64_OPND_F4)
7980 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7981 if (reg >= min && reg <= max)
7983 specs[count++] = tmpl;
7990 int min = dep->regindex == PSR_MFL ? 2 : 32;
7991 int max = dep->regindex == PSR_MFL ? 31 : 127;
7992 /* mfh is read on writes to FR32-127; mfl is read on writes to
7994 for (i = 0; i < idesc->num_outputs; i++)
7996 if (idesc->operands[i] == IA64_OPND_F1)
7998 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7999 if (reg >= min && reg <= max)
8001 specs[count++] = tmpl;
8006 else if (note == 10)
8008 for (i = 0; i < NELEMS (idesc->operands); i++)
8010 if (idesc->operands[i] == IA64_OPND_R1
8011 || idesc->operands[i] == IA64_OPND_R2
8012 || idesc->operands[i] == IA64_OPND_R3)
8014 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8015 if (regno >= 16 && regno <= 31)
8017 specs[count++] = tmpl;
8028 case IA64_RS_AR_FPSR:
8029 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
8031 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8032 if (regno == AR_FPSR)
8034 specs[count++] = tmpl;
8039 specs[count++] = tmpl;
8044 /* Handle all AR[REG] resources */
8045 if (note == 0 || note == 1)
8047 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8048 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
8049 && regno == dep->regindex)
8051 specs[count++] = tmpl;
8053 /* other AR[REG] resources may be affected by AR accesses */
8054 else if (idesc->operands[0] == IA64_OPND_AR3)
8057 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
8058 switch (dep->regindex)
8064 if (regno == AR_BSPSTORE)
8066 specs[count++] = tmpl;
8070 (regno == AR_BSPSTORE
8071 || regno == AR_RNAT))
8073 specs[count++] = tmpl;
8078 else if (idesc->operands[1] == IA64_OPND_AR3)
8081 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
8082 switch (dep->regindex)
8087 if (regno == AR_BSPSTORE || regno == AR_RNAT)
8089 specs[count++] = tmpl;
8096 specs[count++] = tmpl;
8106 /* Handle all CR[REG] resources */
8107 if (note == 0 || note == 1)
8109 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
8111 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
8112 if (regno == dep->regindex)
8114 specs[count++] = tmpl;
8116 else if (!rsrc_write)
8118 /* Reads from CR[IVR] affect other resources. */
8119 if (regno == CR_IVR)
8121 if ((dep->regindex >= CR_IRR0
8122 && dep->regindex <= CR_IRR3)
8123 || dep->regindex == CR_TPR)
8125 specs[count++] = tmpl;
8132 specs[count++] = tmpl;
8141 case IA64_RS_INSERVICE:
8142 /* look for write of EOI (67) or read of IVR (65) */
8143 if ((idesc->operands[0] == IA64_OPND_CR3
8144 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
8145 || (idesc->operands[1] == IA64_OPND_CR3
8146 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
8148 specs[count++] = tmpl;
8155 specs[count++] = tmpl;
8166 specs[count++] = tmpl;
8170 /* Check if any of the registers accessed are in the rotating region.
8171 mov to/from pr accesses CFM only when qp_regno is in the rotating
8173 for (i = 0; i < NELEMS (idesc->operands); i++)
8175 if (idesc->operands[i] == IA64_OPND_R1
8176 || idesc->operands[i] == IA64_OPND_R2
8177 || idesc->operands[i] == IA64_OPND_R3)
8179 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8180 /* Assumes that md.rot.num_regs is always valid */
8181 if (md.rot.num_regs > 0
8183 && num < 31 + md.rot.num_regs)
8185 specs[count] = tmpl;
8186 specs[count++].specific = 0;
8189 else if (idesc->operands[i] == IA64_OPND_F1
8190 || idesc->operands[i] == IA64_OPND_F2
8191 || idesc->operands[i] == IA64_OPND_F3
8192 || idesc->operands[i] == IA64_OPND_F4)
8194 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8197 specs[count] = tmpl;
8198 specs[count++].specific = 0;
8201 else if (idesc->operands[i] == IA64_OPND_P1
8202 || idesc->operands[i] == IA64_OPND_P2)
8204 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
8207 specs[count] = tmpl;
8208 specs[count++].specific = 0;
8212 if (CURR_SLOT.qp_regno > 15)
8214 specs[count] = tmpl;
8215 specs[count++].specific = 0;
8220 /* This is the same as IA64_RS_PRr, except simplified to account for
8221 the fact that there is only one register. */
8225 specs[count++] = tmpl;
8230 if (idesc->operands[2] == IA64_OPND_IMM17)
8231 mask = CURR_SLOT.opnd[2].X_add_number;
8232 if (mask & ((valueT) 1 << 63))
8233 specs[count++] = tmpl;
8235 else if (note == 11)
8237 if ((idesc->operands[0] == IA64_OPND_P1
8238 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
8239 || (idesc->operands[1] == IA64_OPND_P2
8240 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
8242 specs[count++] = tmpl;
8245 else if (note == 12)
8247 if (CURR_SLOT.qp_regno == 63)
8249 specs[count++] = tmpl;
8256 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8257 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8258 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
8259 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
8262 && (idesc->operands[0] == IA64_OPND_P1
8263 || idesc->operands[0] == IA64_OPND_P2))
8265 specs[count] = tmpl;
8266 specs[count++].cmp_type =
8267 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
8270 && (idesc->operands[1] == IA64_OPND_P1
8271 || idesc->operands[1] == IA64_OPND_P2))
8273 specs[count] = tmpl;
8274 specs[count++].cmp_type =
8275 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
8280 if (CURR_SLOT.qp_regno == 63)
8282 specs[count++] = tmpl;
8293 /* FIXME we can identify some individual RSE written resources, but RSE
8294 read resources have not yet been completely identified, so for now
8295 treat RSE as a single resource */
8296 if (strncmp (idesc->name, "mov", 3) == 0)
8300 if (idesc->operands[0] == IA64_OPND_AR3
8301 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
8303 specs[count] = tmpl;
8304 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8309 if (idesc->operands[0] == IA64_OPND_AR3)
8311 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
8312 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
8314 specs[count++] = tmpl;
8317 else if (idesc->operands[1] == IA64_OPND_AR3)
8319 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
8320 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
8321 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
8323 specs[count++] = tmpl;
8330 specs[count++] = tmpl;
8335 /* FIXME -- do any of these need to be non-specific? */
8336 specs[count++] = tmpl;
8340 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
8347 /* Clear branch flags on marked resources. This breaks the link between the
8348 QP of the marking instruction and a subsequent branch on the same QP. */
8351 clear_qp_branch_flag (mask)
8355 for (i = 0; i < regdepslen; i++)
8357 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
8358 if ((bit & mask) != 0)
8360 regdeps[i].link_to_qp_branch = 0;
8365 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8367 Any changes to a PR clears the mutex relations which include that PR. */
8370 clear_qp_mutex (mask)
8376 while (i < qp_mutexeslen)
8378 if ((qp_mutexes[i].prmask & mask) != 0)
8382 fprintf (stderr, " Clearing mutex relation");
8383 print_prmask (qp_mutexes[i].prmask);
8384 fprintf (stderr, "\n");
8386 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
8393 /* Clear implies relations which contain PRs in the given masks.
8394 P1_MASK indicates the source of the implies relation, while P2_MASK
8395 indicates the implied PR. */
8398 clear_qp_implies (p1_mask, p2_mask)
8405 while (i < qp_implieslen)
8407 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
8408 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
8411 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
8412 qp_implies[i].p1, qp_implies[i].p2);
8413 qp_implies[i] = qp_implies[--qp_implieslen];
8420 /* Add the PRs specified to the list of implied relations. */
8423 add_qp_imply (p1, p2)
8430 /* p0 is not meaningful here. */
8431 if (p1 == 0 || p2 == 0)
8437 /* If it exists already, ignore it. */
8438 for (i = 0; i < qp_implieslen; i++)
8440 if (qp_implies[i].p1 == p1
8441 && qp_implies[i].p2 == p2
8442 && qp_implies[i].path == md.path
8443 && !qp_implies[i].p2_branched)
8447 if (qp_implieslen == qp_impliestotlen)
8449 qp_impliestotlen += 20;
8450 qp_implies = (struct qp_imply *)
8451 xrealloc ((void *) qp_implies,
8452 qp_impliestotlen * sizeof (struct qp_imply));
8455 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
8456 qp_implies[qp_implieslen].p1 = p1;
8457 qp_implies[qp_implieslen].p2 = p2;
8458 qp_implies[qp_implieslen].path = md.path;
8459 qp_implies[qp_implieslen++].p2_branched = 0;
8461 /* Add in the implied transitive relations; for everything that p2 implies,
8462 make p1 imply that, too; for everything that implies p1, make it imply p2
8464 for (i = 0; i < qp_implieslen; i++)
8466 if (qp_implies[i].p1 == p2)
8467 add_qp_imply (p1, qp_implies[i].p2);
8468 if (qp_implies[i].p2 == p1)
8469 add_qp_imply (qp_implies[i].p1, p2);
8471 /* Add in mutex relations implied by this implies relation; for each mutex
8472 relation containing p2, duplicate it and replace p2 with p1. */
8473 bit = (valueT) 1 << p1;
8474 mask = (valueT) 1 << p2;
8475 for (i = 0; i < qp_mutexeslen; i++)
8477 if (qp_mutexes[i].prmask & mask)
8478 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
8482 /* Add the PRs specified in the mask to the mutex list; this means that only
8483 one of the PRs can be true at any time. PR0 should never be included in
8493 if (qp_mutexeslen == qp_mutexestotlen)
8495 qp_mutexestotlen += 20;
8496 qp_mutexes = (struct qpmutex *)
8497 xrealloc ((void *) qp_mutexes,
8498 qp_mutexestotlen * sizeof (struct qpmutex));
8502 fprintf (stderr, " Registering mutex on");
8503 print_prmask (mask);
8504 fprintf (stderr, "\n");
8506 qp_mutexes[qp_mutexeslen].path = md.path;
8507 qp_mutexes[qp_mutexeslen++].prmask = mask;
8511 clear_register_values ()
8515 fprintf (stderr, " Clearing register values\n");
8516 for (i = 1; i < NELEMS (gr_values); i++)
8517 gr_values[i].known = 0;
8520 /* Keep track of register values/changes which affect DV tracking.
8522 optimization note: should add a flag to classes of insns where otherwise we
8523 have to examine a group of strings to identify them. */
8526 note_register_values (idesc)
8527 struct ia64_opcode *idesc;
8529 valueT qp_changemask = 0;
8532 /* Invalidate values for registers being written to. */
8533 for (i = 0; i < idesc->num_outputs; i++)
8535 if (idesc->operands[i] == IA64_OPND_R1
8536 || idesc->operands[i] == IA64_OPND_R2
8537 || idesc->operands[i] == IA64_OPND_R3)
8539 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8540 if (regno > 0 && regno < NELEMS (gr_values))
8541 gr_values[regno].known = 0;
8543 else if (idesc->operands[i] == IA64_OPND_R3_2)
8545 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8546 if (regno > 0 && regno < 4)
8547 gr_values[regno].known = 0;
8549 else if (idesc->operands[i] == IA64_OPND_P1
8550 || idesc->operands[i] == IA64_OPND_P2)
8552 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
8553 qp_changemask |= (valueT) 1 << regno;
8555 else if (idesc->operands[i] == IA64_OPND_PR)
8557 if (idesc->operands[2] & (valueT) 0x10000)
8558 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
8560 qp_changemask = idesc->operands[2];
8563 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
8565 if (idesc->operands[1] & ((valueT) 1 << 43))
8566 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
8568 qp_changemask = idesc->operands[1];
8569 qp_changemask &= ~(valueT) 0xFFFF;
8574 /* Always clear qp branch flags on any PR change. */
8575 /* FIXME there may be exceptions for certain compares. */
8576 clear_qp_branch_flag (qp_changemask);
8578 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8579 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
8581 qp_changemask |= ~(valueT) 0xFFFF;
8582 if (strcmp (idesc->name, "clrrrb.pr") != 0)
8584 for (i = 32; i < 32 + md.rot.num_regs; i++)
8585 gr_values[i].known = 0;
8587 clear_qp_mutex (qp_changemask);
8588 clear_qp_implies (qp_changemask, qp_changemask);
8590 /* After a call, all register values are undefined, except those marked
8592 else if (strncmp (idesc->name, "br.call", 6) == 0
8593 || strncmp (idesc->name, "brl.call", 7) == 0)
8595 /* FIXME keep GR values which are marked as "safe_across_calls" */
8596 clear_register_values ();
8597 clear_qp_mutex (~qp_safe_across_calls);
8598 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
8599 clear_qp_branch_flag (~qp_safe_across_calls);
8601 else if (is_interruption_or_rfi (idesc)
8602 || is_taken_branch (idesc))
8604 clear_register_values ();
8605 clear_qp_mutex (~(valueT) 0);
8606 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
8608 /* Look for mutex and implies relations. */
8609 else if ((idesc->operands[0] == IA64_OPND_P1
8610 || idesc->operands[0] == IA64_OPND_P2)
8611 && (idesc->operands[1] == IA64_OPND_P1
8612 || idesc->operands[1] == IA64_OPND_P2))
8614 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8615 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8616 valueT p1mask = (valueT) 1 << p1;
8617 valueT p2mask = (valueT) 1 << p2;
8619 /* If one of the PRs is PR0, we can't really do anything. */
8620 if (p1 == 0 || p2 == 0)
8623 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
8625 /* In general, clear mutexes and implies which include P1 or P2,
8626 with the following exceptions. */
8627 else if (strstr (idesc->name, ".or.andcm") != NULL)
8629 add_qp_mutex (p1mask | p2mask);
8630 clear_qp_implies (p2mask, p1mask);
8632 else if (strstr (idesc->name, ".and.orcm") != NULL)
8634 add_qp_mutex (p1mask | p2mask);
8635 clear_qp_implies (p1mask, p2mask);
8637 else if (strstr (idesc->name, ".and") != NULL)
8639 clear_qp_implies (0, p1mask | p2mask);
8641 else if (strstr (idesc->name, ".or") != NULL)
8643 clear_qp_mutex (p1mask | p2mask);
8644 clear_qp_implies (p1mask | p2mask, 0);
8648 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
8649 if (strstr (idesc->name, ".unc") != NULL)
8651 add_qp_mutex (p1mask | p2mask);
8652 if (CURR_SLOT.qp_regno != 0)
8654 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
8655 CURR_SLOT.qp_regno);
8656 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
8657 CURR_SLOT.qp_regno);
8660 else if (CURR_SLOT.qp_regno == 0)
8662 add_qp_mutex (p1mask | p2mask);
8666 clear_qp_mutex (p1mask | p2mask);
8670 /* Look for mov imm insns into GRs. */
8671 else if (idesc->operands[0] == IA64_OPND_R1
8672 && (idesc->operands[1] == IA64_OPND_IMM22
8673 || idesc->operands[1] == IA64_OPND_IMMU64)
8674 && (strcmp (idesc->name, "mov") == 0
8675 || strcmp (idesc->name, "movl") == 0))
8677 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
8678 if (regno > 0 && regno < NELEMS (gr_values))
8680 gr_values[regno].known = 1;
8681 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
8682 gr_values[regno].path = md.path;
8685 fprintf (stderr, " Know gr%d = ", regno);
8686 fprintf_vma (stderr, gr_values[regno].value);
8687 fputs ("\n", stderr);
8693 clear_qp_mutex (qp_changemask);
8694 clear_qp_implies (qp_changemask, qp_changemask);
8698 /* Return whether the given predicate registers are currently mutex. */
8701 qp_mutex (p1, p2, path)
8711 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
8712 for (i = 0; i < qp_mutexeslen; i++)
8714 if (qp_mutexes[i].path >= path
8715 && (qp_mutexes[i].prmask & mask) == mask)
8722 /* Return whether the given resource is in the given insn's list of chks
8723 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8727 resources_match (rs, idesc, note, qp_regno, path)
8729 struct ia64_opcode *idesc;
8734 struct rsrc specs[MAX_SPECS];
8737 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8738 we don't need to check. One exception is note 11, which indicates that
8739 target predicates are written regardless of PR[qp]. */
8740 if (qp_mutex (rs->qp_regno, qp_regno, path)
8744 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
8747 /* UNAT checking is a bit more specific than other resources */
8748 if (rs->dependency->specifier == IA64_RS_AR_UNAT
8749 && specs[count].mem_offset.hint
8750 && rs->mem_offset.hint)
8752 if (rs->mem_offset.base == specs[count].mem_offset.base)
8754 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
8755 ((specs[count].mem_offset.offset >> 3) & 0x3F))
8762 /* Skip apparent PR write conflicts where both writes are an AND or both
8763 writes are an OR. */
8764 if (rs->dependency->specifier == IA64_RS_PR
8765 || rs->dependency->specifier == IA64_RS_PRr
8766 || rs->dependency->specifier == IA64_RS_PR63)
8768 if (specs[count].cmp_type != CMP_NONE
8769 && specs[count].cmp_type == rs->cmp_type)
8772 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
8773 dv_mode[rs->dependency->mode],
8774 rs->dependency->specifier != IA64_RS_PR63 ?
8775 specs[count].index : 63);
8780 " %s on parallel compare conflict %s vs %s on PR%d\n",
8781 dv_mode[rs->dependency->mode],
8782 dv_cmp_type[rs->cmp_type],
8783 dv_cmp_type[specs[count].cmp_type],
8784 rs->dependency->specifier != IA64_RS_PR63 ?
8785 specs[count].index : 63);
8789 /* If either resource is not specific, conservatively assume a conflict
8791 if (!specs[count].specific || !rs->specific)
8793 else if (specs[count].index == rs->index)
8798 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
8804 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8805 insert a stop to create the break. Update all resource dependencies
8806 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8807 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8808 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8812 insn_group_break (insert_stop, qp_regno, save_current)
8819 if (insert_stop && md.num_slots_in_use > 0)
8820 PREV_SLOT.end_of_insn_group = 1;
8824 fprintf (stderr, " Insn group break%s",
8825 (insert_stop ? " (w/stop)" : ""));
8827 fprintf (stderr, " effective for QP=%d", qp_regno);
8828 fprintf (stderr, "\n");
8832 while (i < regdepslen)
8834 const struct ia64_dependency *dep = regdeps[i].dependency;
8837 && regdeps[i].qp_regno != qp_regno)
8844 && CURR_SLOT.src_file == regdeps[i].file
8845 && CURR_SLOT.src_line == regdeps[i].line)
8851 /* clear dependencies which are automatically cleared by a stop, or
8852 those that have reached the appropriate state of insn serialization */
8853 if (dep->semantics == IA64_DVS_IMPLIED
8854 || dep->semantics == IA64_DVS_IMPLIEDF
8855 || regdeps[i].insn_srlz == STATE_SRLZ)
8857 print_dependency ("Removing", i);
8858 regdeps[i] = regdeps[--regdepslen];
8862 if (dep->semantics == IA64_DVS_DATA
8863 || dep->semantics == IA64_DVS_INSTR
8864 || dep->semantics == IA64_DVS_SPECIFIC)
8866 if (regdeps[i].insn_srlz == STATE_NONE)
8867 regdeps[i].insn_srlz = STATE_STOP;
8868 if (regdeps[i].data_srlz == STATE_NONE)
8869 regdeps[i].data_srlz = STATE_STOP;
8876 /* Add the given resource usage spec to the list of active dependencies. */
8879 mark_resource (idesc, dep, spec, depind, path)
8880 struct ia64_opcode *idesc ATTRIBUTE_UNUSED;
8881 const struct ia64_dependency *dep ATTRIBUTE_UNUSED;
8886 if (regdepslen == regdepstotlen)
8888 regdepstotlen += 20;
8889 regdeps = (struct rsrc *)
8890 xrealloc ((void *) regdeps,
8891 regdepstotlen * sizeof (struct rsrc));
8894 regdeps[regdepslen] = *spec;
8895 regdeps[regdepslen].depind = depind;
8896 regdeps[regdepslen].path = path;
8897 regdeps[regdepslen].file = CURR_SLOT.src_file;
8898 regdeps[regdepslen].line = CURR_SLOT.src_line;
8900 print_dependency ("Adding", regdepslen);
8906 print_dependency (action, depind)
8912 fprintf (stderr, " %s %s '%s'",
8913 action, dv_mode[(regdeps[depind].dependency)->mode],
8914 (regdeps[depind].dependency)->name);
8915 if (regdeps[depind].specific && regdeps[depind].index != 0)
8916 fprintf (stderr, " (%d)", regdeps[depind].index);
8917 if (regdeps[depind].mem_offset.hint)
8919 fputs (" ", stderr);
8920 fprintf_vma (stderr, regdeps[depind].mem_offset.base);
8921 fputs ("+", stderr);
8922 fprintf_vma (stderr, regdeps[depind].mem_offset.offset);
8924 fprintf (stderr, "\n");
8929 instruction_serialization ()
8933 fprintf (stderr, " Instruction serialization\n");
8934 for (i = 0; i < regdepslen; i++)
8935 if (regdeps[i].insn_srlz == STATE_STOP)
8936 regdeps[i].insn_srlz = STATE_SRLZ;
8940 data_serialization ()
8944 fprintf (stderr, " Data serialization\n");
8945 while (i < regdepslen)
8947 if (regdeps[i].data_srlz == STATE_STOP
8948 /* Note: as of 991210, all "other" dependencies are cleared by a
8949 data serialization. This might change with new tables */
8950 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
8952 print_dependency ("Removing", i);
8953 regdeps[i] = regdeps[--regdepslen];
8960 /* Insert stops and serializations as needed to avoid DVs. */
8963 remove_marked_resource (rs)
8966 switch (rs->dependency->semantics)
8968 case IA64_DVS_SPECIFIC:
8970 fprintf (stderr, "Implementation-specific, assume worst case...\n");
8971 /* ...fall through... */
8972 case IA64_DVS_INSTR:
8974 fprintf (stderr, "Inserting instr serialization\n");
8975 if (rs->insn_srlz < STATE_STOP)
8976 insn_group_break (1, 0, 0);
8977 if (rs->insn_srlz < STATE_SRLZ)
8979 int oldqp = CURR_SLOT.qp_regno;
8980 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8981 /* Manually jam a srlz.i insn into the stream */
8982 CURR_SLOT.qp_regno = 0;
8983 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
8984 instruction_serialization ();
8985 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8986 if (++md.num_slots_in_use >= NUM_SLOTS)
8988 CURR_SLOT.qp_regno = oldqp;
8989 CURR_SLOT.idesc = oldidesc;
8991 insn_group_break (1, 0, 0);
8993 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
8994 "other" types of DV are eliminated
8995 by a data serialization */
8998 fprintf (stderr, "Inserting data serialization\n");
8999 if (rs->data_srlz < STATE_STOP)
9000 insn_group_break (1, 0, 0);
9002 int oldqp = CURR_SLOT.qp_regno;
9003 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
9004 /* Manually jam a srlz.d insn into the stream */
9005 CURR_SLOT.qp_regno = 0;
9006 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
9007 data_serialization ();
9008 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9009 if (++md.num_slots_in_use >= NUM_SLOTS)
9011 CURR_SLOT.qp_regno = oldqp;
9012 CURR_SLOT.idesc = oldidesc;
9015 case IA64_DVS_IMPLIED:
9016 case IA64_DVS_IMPLIEDF:
9018 fprintf (stderr, "Inserting stop\n");
9019 insn_group_break (1, 0, 0);
9026 /* Check the resources used by the given opcode against the current dependency
9029 The check is run once for each execution path encountered. In this case,
9030 a unique execution path is the sequence of instructions following a code
9031 entry point, e.g. the following has three execution paths, one starting
9032 at L0, one at L1, and one at L2.
9041 check_dependencies (idesc)
9042 struct ia64_opcode *idesc;
9044 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9048 /* Note that the number of marked resources may change within the
9049 loop if in auto mode. */
9051 while (i < regdepslen)
9053 struct rsrc *rs = ®deps[i];
9054 const struct ia64_dependency *dep = rs->dependency;
9059 if (dep->semantics == IA64_DVS_NONE
9060 || (chkind = depends_on (rs->depind, idesc)) == -1)
9066 note = NOTE (opdeps->chks[chkind]);
9068 /* Check this resource against each execution path seen thus far. */
9069 for (path = 0; path <= md.path; path++)
9073 /* If the dependency wasn't on the path being checked, ignore it. */
9074 if (rs->path < path)
9077 /* If the QP for this insn implies a QP which has branched, don't
9078 bother checking. Ed. NOTE: I don't think this check is terribly
9079 useful; what's the point of generating code which will only be
9080 reached if its QP is zero?
9081 This code was specifically inserted to handle the following code,
9082 based on notes from Intel's DV checking code, where p1 implies p2.
9088 if (CURR_SLOT.qp_regno != 0)
9092 for (implies = 0; implies < qp_implieslen; implies++)
9094 if (qp_implies[implies].path >= path
9095 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
9096 && qp_implies[implies].p2_branched)
9106 if ((matchtype = resources_match (rs, idesc, note,
9107 CURR_SLOT.qp_regno, path)) != 0)
9110 char pathmsg[256] = "";
9111 char indexmsg[256] = "";
9112 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
9115 sprintf (pathmsg, " when entry is at label '%s'",
9116 md.entry_labels[path - 1]);
9117 if (rs->specific && rs->index != 0)
9118 sprintf (indexmsg, ", specific resource number is %d",
9120 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9122 (certain ? "violates" : "may violate"),
9123 dv_mode[dep->mode], dep->name,
9124 dv_sem[dep->semantics],
9127 if (md.explicit_mode)
9129 as_warn ("%s", msg);
9131 as_warn (_("Only the first path encountering the conflict "
9133 as_warn_where (rs->file, rs->line,
9134 _("This is the location of the "
9135 "conflicting usage"));
9136 /* Don't bother checking other paths, to avoid duplicating
9143 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
9145 remove_marked_resource (rs);
9147 /* since the set of dependencies has changed, start over */
9148 /* FIXME -- since we're removing dvs as we go, we
9149 probably don't really need to start over... */
9162 /* Register new dependencies based on the given opcode. */
9165 mark_resources (idesc)
9166 struct ia64_opcode *idesc;
9169 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9170 int add_only_qp_reads = 0;
9172 /* A conditional branch only uses its resources if it is taken; if it is
9173 taken, we stop following that path. The other branch types effectively
9174 *always* write their resources. If it's not taken, register only QP
9176 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
9178 add_only_qp_reads = 1;
9182 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
9184 for (i = 0; i < opdeps->nregs; i++)
9186 const struct ia64_dependency *dep;
9187 struct rsrc specs[MAX_SPECS];
9192 dep = ia64_find_dependency (opdeps->regs[i]);
9193 note = NOTE (opdeps->regs[i]);
9195 if (add_only_qp_reads
9196 && !(dep->mode == IA64_DV_WAR
9197 && (dep->specifier == IA64_RS_PR
9198 || dep->specifier == IA64_RS_PRr
9199 || dep->specifier == IA64_RS_PR63)))
9202 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
9205 if (md.debug_dv && !count)
9206 fprintf (stderr, " No %s %s usage found (path %d)\n",
9207 dv_mode[dep->mode], dep->name, md.path);
9212 mark_resource (idesc, dep, &specs[count],
9213 DEP (opdeps->regs[i]), md.path);
9216 /* The execution path may affect register values, which may in turn
9217 affect which indirect-access resources are accessed. */
9218 switch (dep->specifier)
9230 for (path = 0; path < md.path; path++)
9232 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
9234 mark_resource (idesc, dep, &specs[count],
9235 DEP (opdeps->regs[i]), path);
9242 /* Remove dependencies when they no longer apply. */
9245 update_dependencies (idesc)
9246 struct ia64_opcode *idesc;
9250 if (strcmp (idesc->name, "srlz.i") == 0)
9252 instruction_serialization ();
9254 else if (strcmp (idesc->name, "srlz.d") == 0)
9256 data_serialization ();
9258 else if (is_interruption_or_rfi (idesc)
9259 || is_taken_branch (idesc))
9261 /* Although technically the taken branch doesn't clear dependencies
9262 which require a srlz.[id], we don't follow the branch; the next
9263 instruction is assumed to start with a clean slate. */
9267 else if (is_conditional_branch (idesc)
9268 && CURR_SLOT.qp_regno != 0)
9270 int is_call = strstr (idesc->name, ".call") != NULL;
9272 for (i = 0; i < qp_implieslen; i++)
9274 /* If the conditional branch's predicate is implied by the predicate
9275 in an existing dependency, remove that dependency. */
9276 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
9279 /* Note that this implied predicate takes a branch so that if
9280 a later insn generates a DV but its predicate implies this
9281 one, we can avoid the false DV warning. */
9282 qp_implies[i].p2_branched = 1;
9283 while (depind < regdepslen)
9285 if (regdeps[depind].qp_regno == qp_implies[i].p1)
9287 print_dependency ("Removing", depind);
9288 regdeps[depind] = regdeps[--regdepslen];
9295 /* Any marked resources which have this same predicate should be
9296 cleared, provided that the QP hasn't been modified between the
9297 marking instruction and the branch. */
9300 insn_group_break (0, CURR_SLOT.qp_regno, 1);
9305 while (i < regdepslen)
9307 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
9308 && regdeps[i].link_to_qp_branch
9309 && (regdeps[i].file != CURR_SLOT.src_file
9310 || regdeps[i].line != CURR_SLOT.src_line))
9312 /* Treat like a taken branch */
9313 print_dependency ("Removing", i);
9314 regdeps[i] = regdeps[--regdepslen];
9323 /* Examine the current instruction for dependency violations. */
9327 struct ia64_opcode *idesc;
9331 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
9332 idesc->name, CURR_SLOT.src_line,
9333 idesc->dependencies->nchks,
9334 idesc->dependencies->nregs);
9337 /* Look through the list of currently marked resources; if the current
9338 instruction has the dependency in its chks list which uses that resource,
9339 check against the specific resources used. */
9340 check_dependencies (idesc);
9342 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9343 then add them to the list of marked resources. */
9344 mark_resources (idesc);
9346 /* There are several types of dependency semantics, and each has its own
9347 requirements for being cleared
9349 Instruction serialization (insns separated by interruption, rfi, or
9350 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9352 Data serialization (instruction serialization, or writer + srlz.d +
9353 reader, where writer and srlz.d are in separate groups) clears
9354 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9355 always be the case).
9357 Instruction group break (groups separated by stop, taken branch,
9358 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9360 update_dependencies (idesc);
9362 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9363 warning. Keep track of as many as possible that are useful. */
9364 note_register_values (idesc);
9366 /* We don't need or want this anymore. */
9367 md.mem_offset.hint = 0;
9372 /* Translate one line of assembly. Pseudo ops and labels do not show
9378 char *saved_input_line_pointer, *mnemonic;
9379 const struct pseudo_opcode *pdesc;
9380 struct ia64_opcode *idesc;
9381 unsigned char qp_regno;
9385 saved_input_line_pointer = input_line_pointer;
9386 input_line_pointer = str;
9388 /* extract the opcode (mnemonic): */
9390 mnemonic = input_line_pointer;
9391 ch = get_symbol_end ();
9392 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
9395 *input_line_pointer = ch;
9396 (*pdesc->handler) (pdesc->arg);
9400 /* Find the instruction descriptor matching the arguments. */
9402 idesc = ia64_find_opcode (mnemonic);
9403 *input_line_pointer = ch;
9406 as_bad ("Unknown opcode `%s'", mnemonic);
9410 idesc = parse_operands (idesc);
9414 /* Handle the dynamic ops we can handle now: */
9415 if (idesc->type == IA64_TYPE_DYN)
9417 if (strcmp (idesc->name, "add") == 0)
9419 if (CURR_SLOT.opnd[2].X_op == O_register
9420 && CURR_SLOT.opnd[2].X_add_number < 4)
9424 ia64_free_opcode (idesc);
9425 idesc = ia64_find_opcode (mnemonic);
9427 know (!idesc->next);
9430 else if (strcmp (idesc->name, "mov") == 0)
9432 enum ia64_opnd opnd1, opnd2;
9435 opnd1 = idesc->operands[0];
9436 opnd2 = idesc->operands[1];
9437 if (opnd1 == IA64_OPND_AR3)
9439 else if (opnd2 == IA64_OPND_AR3)
9443 if (CURR_SLOT.opnd[rop].X_op == O_register
9444 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
9448 ia64_free_opcode (idesc);
9449 idesc = ia64_find_opcode (mnemonic);
9450 while (idesc != NULL
9451 && (idesc->operands[0] != opnd1
9452 || idesc->operands[1] != opnd2))
9453 idesc = get_next_opcode (idesc);
9458 if (md.qp.X_op == O_register)
9460 qp_regno = md.qp.X_add_number - REG_P;
9461 md.qp.X_op = O_absent;
9464 flags = idesc->flags;
9466 if ((flags & IA64_OPCODE_FIRST) != 0)
9467 insn_group_break (1, 0, 0);
9469 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
9471 as_bad ("`%s' cannot be predicated", idesc->name);
9475 /* Build the instruction. */
9476 CURR_SLOT.qp_regno = qp_regno;
9477 CURR_SLOT.idesc = idesc;
9478 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
9479 dwarf2_where (&CURR_SLOT.debug_line);
9481 /* Add unwind entry, if there is one. */
9482 if (unwind.current_entry)
9484 CURR_SLOT.unwind_record = unwind.current_entry;
9485 unwind.current_entry = NULL;
9488 /* Check for dependency violations. */
9492 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9493 if (++md.num_slots_in_use >= NUM_SLOTS)
9496 if ((flags & IA64_OPCODE_LAST) != 0)
9497 insn_group_break (1, 0, 0);
9499 md.last_text_seg = now_seg;
9502 input_line_pointer = saved_input_line_pointer;
9505 /* Called when symbol NAME cannot be found in the symbol table.
9506 Should be used for dynamic valued symbols only. */
9509 md_undefined_symbol (name)
9510 char *name ATTRIBUTE_UNUSED;
9515 /* Called for any expression that can not be recognized. When the
9516 function is called, `input_line_pointer' will point to the start of
9523 enum pseudo_type pseudo_type;
9528 switch (*input_line_pointer)
9531 /* Find what relocation pseudo-function we're dealing with. */
9533 ch = *++input_line_pointer;
9534 for (i = 0; i < NELEMS (pseudo_func); ++i)
9535 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
9537 len = strlen (pseudo_func[i].name);
9538 if (strncmp (pseudo_func[i].name + 1,
9539 input_line_pointer + 1, len - 1) == 0
9540 && !is_part_of_name (input_line_pointer[len]))
9542 input_line_pointer += len;
9543 pseudo_type = pseudo_func[i].type;
9547 switch (pseudo_type)
9549 case PSEUDO_FUNC_RELOC:
9551 if (*input_line_pointer != '(')
9553 as_bad ("Expected '('");
9557 ++input_line_pointer;
9559 if (*input_line_pointer++ != ')')
9561 as_bad ("Missing ')'");
9564 if (e->X_op != O_symbol)
9566 if (e->X_op != O_pseudo_fixup)
9568 as_bad ("Not a symbolic expression");
9571 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
9572 && i == FUNC_LT_RELATIVE)
9573 i = FUNC_LT_FPTR_RELATIVE;
9576 as_bad ("Illegal combination of relocation functions");
9580 /* Make sure gas doesn't get rid of local symbols that are used
9582 e->X_op = O_pseudo_fixup;
9583 e->X_op_symbol = pseudo_func[i].u.sym;
9586 case PSEUDO_FUNC_CONST:
9587 e->X_op = O_constant;
9588 e->X_add_number = pseudo_func[i].u.ival;
9591 case PSEUDO_FUNC_REG:
9592 e->X_op = O_register;
9593 e->X_add_number = pseudo_func[i].u.ival;
9597 name = input_line_pointer - 1;
9599 as_bad ("Unknown pseudo function `%s'", name);
9605 ++input_line_pointer;
9607 if (*input_line_pointer != ']')
9609 as_bad ("Closing bracket misssing");
9614 if (e->X_op != O_register)
9615 as_bad ("Register expected as index");
9617 ++input_line_pointer;
9628 ignore_rest_of_line ();
9631 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9632 a section symbol plus some offset. For relocs involving @fptr(),
9633 directives we don't want such adjustments since we need to have the
9634 original symbol's name in the reloc. */
9636 ia64_fix_adjustable (fix)
9639 /* Prevent all adjustments to global symbols */
9640 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
9643 switch (fix->fx_r_type)
9645 case BFD_RELOC_IA64_FPTR64I:
9646 case BFD_RELOC_IA64_FPTR32MSB:
9647 case BFD_RELOC_IA64_FPTR32LSB:
9648 case BFD_RELOC_IA64_FPTR64MSB:
9649 case BFD_RELOC_IA64_FPTR64LSB:
9650 case BFD_RELOC_IA64_LTOFF_FPTR22:
9651 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9661 ia64_force_relocation (fix)
9664 switch (fix->fx_r_type)
9666 case BFD_RELOC_IA64_FPTR64I:
9667 case BFD_RELOC_IA64_FPTR32MSB:
9668 case BFD_RELOC_IA64_FPTR32LSB:
9669 case BFD_RELOC_IA64_FPTR64MSB:
9670 case BFD_RELOC_IA64_FPTR64LSB:
9672 case BFD_RELOC_IA64_LTOFF22:
9673 case BFD_RELOC_IA64_LTOFF64I:
9674 case BFD_RELOC_IA64_LTOFF_FPTR22:
9675 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9676 case BFD_RELOC_IA64_PLTOFF22:
9677 case BFD_RELOC_IA64_PLTOFF64I:
9678 case BFD_RELOC_IA64_PLTOFF64MSB:
9679 case BFD_RELOC_IA64_PLTOFF64LSB:
9688 /* Decide from what point a pc-relative relocation is relative to,
9689 relative to the pc-relative fixup. Er, relatively speaking. */
9691 ia64_pcrel_from_section (fix, sec)
9695 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
9697 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
9703 /* This is called whenever some data item (not an instruction) needs a
9704 fixup. We pick the right reloc code depending on the byteorder
9705 currently in effect. */
9707 ia64_cons_fix_new (f, where, nbytes, exp)
9713 bfd_reloc_code_real_type code;
9718 /* There are no reloc for 8 and 16 bit quantities, but we allow
9719 them here since they will work fine as long as the expression
9720 is fully defined at the end of the pass over the source file. */
9721 case 1: code = BFD_RELOC_8; break;
9722 case 2: code = BFD_RELOC_16; break;
9724 if (target_big_endian)
9725 code = BFD_RELOC_IA64_DIR32MSB;
9727 code = BFD_RELOC_IA64_DIR32LSB;
9731 if (target_big_endian)
9732 code = BFD_RELOC_IA64_DIR64MSB;
9734 code = BFD_RELOC_IA64_DIR64LSB;
9738 as_bad ("Unsupported fixup size %d", nbytes);
9739 ignore_rest_of_line ();
9742 if (exp->X_op == O_pseudo_fixup)
9745 exp->X_op = O_symbol;
9746 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
9748 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
9749 /* We need to store the byte order in effect in case we're going
9750 to fix an 8 or 16 bit relocation (for which there no real
9751 relocs available). See md_apply_fix(). */
9752 fix->tc_fix_data.bigendian = target_big_endian;
9755 /* Return the actual relocation we wish to associate with the pseudo
9756 reloc described by SYM and R_TYPE. SYM should be one of the
9757 symbols in the pseudo_func array, or NULL. */
9759 static bfd_reloc_code_real_type
9760 ia64_gen_real_reloc_type (sym, r_type)
9762 bfd_reloc_code_real_type r_type;
9764 bfd_reloc_code_real_type new = 0;
9771 switch (S_GET_VALUE (sym))
9773 case FUNC_FPTR_RELATIVE:
9776 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
9777 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
9778 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
9779 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
9780 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
9785 case FUNC_GP_RELATIVE:
9788 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
9789 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
9790 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
9791 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
9792 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
9793 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
9798 case FUNC_LT_RELATIVE:
9801 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
9802 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
9807 case FUNC_PC_RELATIVE:
9810 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
9811 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
9812 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
9813 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
9814 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
9815 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
9820 case FUNC_PLT_RELATIVE:
9823 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
9824 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
9825 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
9826 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
9831 case FUNC_SEC_RELATIVE:
9834 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
9835 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
9836 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
9837 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
9842 case FUNC_SEG_RELATIVE:
9845 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
9846 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
9847 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
9848 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
9853 case FUNC_LTV_RELATIVE:
9856 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
9857 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
9858 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
9859 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
9864 case FUNC_LT_FPTR_RELATIVE:
9867 case BFD_RELOC_IA64_IMM22:
9868 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
9869 case BFD_RELOC_IA64_IMM64:
9870 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
9878 /* Hmmmm. Should this ever occur? */
9885 /* Here is where generate the appropriate reloc for pseudo relocation
9888 ia64_validate_fix (fix)
9891 switch (fix->fx_r_type)
9893 case BFD_RELOC_IA64_FPTR64I:
9894 case BFD_RELOC_IA64_FPTR32MSB:
9895 case BFD_RELOC_IA64_FPTR64LSB:
9896 case BFD_RELOC_IA64_LTOFF_FPTR22:
9897 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9898 if (fix->fx_offset != 0)
9899 as_bad_where (fix->fx_file, fix->fx_line,
9900 "No addend allowed in @fptr() relocation");
9910 fix_insn (fix, odesc, value)
9912 const struct ia64_operand *odesc;
9915 bfd_vma insn[3], t0, t1, control_bits;
9920 slot = fix->fx_where & 0x3;
9921 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9923 /* Bundles are always in little-endian byte order */
9924 t0 = bfd_getl64 (fixpos);
9925 t1 = bfd_getl64 (fixpos + 8);
9926 control_bits = t0 & 0x1f;
9927 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9928 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9929 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9932 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
9934 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9935 insn[2] |= (((value & 0x7f) << 13)
9936 | (((value >> 7) & 0x1ff) << 27)
9937 | (((value >> 16) & 0x1f) << 22)
9938 | (((value >> 21) & 0x1) << 21)
9939 | (((value >> 63) & 0x1) << 36));
9941 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9943 if (value & ~0x3fffffffffffffffULL)
9944 err = "integer operand out of range";
9945 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9946 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9948 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9951 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
9952 insn[2] |= ((((value >> 59) & 0x1) << 36)
9953 | (((value >> 0) & 0xfffff) << 13));
9956 err = (*odesc->insert) (odesc, value, insn + slot);
9959 as_bad_where (fix->fx_file, fix->fx_line, err);
9961 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
9962 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
9963 number_to_chars_littleendian (fixpos + 0, t0, 8);
9964 number_to_chars_littleendian (fixpos + 8, t1, 8);
9967 /* Attempt to simplify or even eliminate a fixup. The return value is
9968 ignored; perhaps it was once meaningful, but now it is historical.
9969 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9971 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9974 md_apply_fix3 (fix, valuep, seg)
9977 segT seg ATTRIBUTE_UNUSED;
9980 valueT value = *valuep;
9983 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
9987 switch (fix->fx_r_type)
9989 case BFD_RELOC_IA64_DIR32MSB:
9990 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
9994 case BFD_RELOC_IA64_DIR32LSB:
9995 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
9999 case BFD_RELOC_IA64_DIR64MSB:
10000 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
10004 case BFD_RELOC_IA64_DIR64LSB:
10005 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
10015 if (fix->fx_r_type == (int) BFD_RELOC_UNUSED)
10017 /* This must be a TAG13 or TAG13b operand. There are no external
10018 relocs defined for them, so we must give an error. */
10019 as_bad_where (fix->fx_file, fix->fx_line,
10020 "%s must have a constant value",
10021 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
10026 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
10027 work. There should be a better way to handle this. */
10029 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
10031 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
10033 if (fix->tc_fix_data.bigendian)
10034 number_to_chars_bigendian (fixpos, value, fix->fx_size);
10036 number_to_chars_littleendian (fixpos, value, fix->fx_size);
10042 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
10049 /* Generate the BFD reloc to be stuck in the object file from the
10050 fixup used internally in the assembler. */
10053 tc_gen_reloc (sec, fixp)
10054 asection *sec ATTRIBUTE_UNUSED;
10059 reloc = xmalloc (sizeof (*reloc));
10060 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10061 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10062 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
10063 reloc->addend = fixp->fx_offset;
10064 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
10068 as_bad_where (fixp->fx_file, fixp->fx_line,
10069 "Cannot represent %s relocation in object file",
10070 bfd_get_reloc_code_name (fixp->fx_r_type));
10075 /* Turn a string in input_line_pointer into a floating point constant
10076 of type TYPE, and store the appropriate bytes in *LIT. The number
10077 of LITTLENUMS emitted is stored in *SIZE. An error message is
10078 returned, or NULL on OK. */
10080 #define MAX_LITTLENUMS 5
10083 md_atof (type, lit, size)
10088 LITTLENUM_TYPE words[MAX_LITTLENUMS];
10089 LITTLENUM_TYPE *word;
10119 return "Bad call to MD_ATOF()";
10121 t = atof_ieee (input_line_pointer, type, words);
10123 input_line_pointer = t;
10124 *size = prec * sizeof (LITTLENUM_TYPE);
10126 for (word = words + prec - 1; prec--;)
10128 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
10129 lit += sizeof (LITTLENUM_TYPE);
10134 /* Round up a section's size to the appropriate boundary. */
10136 md_section_align (seg, size)
10140 int align = bfd_get_section_alignment (stdoutput, seg);
10141 valueT mask = ((valueT) 1 << align) - 1;
10143 return (size + mask) & ~mask;
10146 /* Handle ia64 specific semantics of the align directive. */
10149 ia64_md_do_align (n, fill, len, max)
10150 int n ATTRIBUTE_UNUSED;
10151 const char *fill ATTRIBUTE_UNUSED;
10152 int len ATTRIBUTE_UNUSED;
10153 int max ATTRIBUTE_UNUSED;
10155 if (subseg_text_p (now_seg))
10156 ia64_flush_insns ();
10159 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10160 of an rs_align_code fragment. */
10163 ia64_handle_align (fragp)
10166 /* Use mfi bundle of nops with no stop bits. */
10167 static const unsigned char be_nop[]
10168 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10169 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10170 static const unsigned char le_nop[]
10171 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10172 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10177 if (fragp->fr_type != rs_align_code)
10180 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
10181 p = fragp->fr_literal + fragp->fr_fix;
10183 /* Make sure we are on a 16-byte boundary, in case someone has been
10184 putting data into a text section. */
10187 int fix = bytes & 15;
10188 memset (p, 0, fix);
10191 fragp->fr_fix += fix;
10194 memcpy (p, (target_big_endian ? be_nop : le_nop), 16);
10195 fragp->fr_var = 16;