1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS = 0,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
127 enum operand_match_result
130 OPERAND_OUT_OF_RANGE,
134 /* On the ia64, we can't know the address of a text label until the
135 instructions are packed into a bundle. To handle this, we keep
136 track of the list of labels that appear in front of each
140 struct label_fix *next;
144 extern int target_big_endian;
146 /* Characters which always start a comment. */
147 const char comment_chars[] = "";
149 /* Characters which start a comment at the beginning of a line. */
150 const char line_comment_chars[] = "#";
152 /* Characters which may be used to separate multiple commands on a
154 const char line_separator_chars[] = ";";
156 /* Characters which are used to indicate an exponent in a floating
158 const char EXP_CHARS[] = "eE";
160 /* Characters which mean that a number is a floating point constant,
162 const char FLT_CHARS[] = "rRsSfFdDxXpP";
164 /* ia64-specific option processing: */
166 const char *md_shortopts = "m:N:x::";
168 struct option md_longopts[] =
170 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
171 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
172 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
173 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
176 size_t md_longopts_size = sizeof (md_longopts);
180 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
181 struct hash_control *reg_hash; /* register name hash table */
182 struct hash_control *dynreg_hash; /* dynamic register hash table */
183 struct hash_control *const_hash; /* constant hash table */
184 struct hash_control *entry_hash; /* code entry hint hash table */
186 symbolS *regsym[REG_NUM];
188 /* If X_op is != O_absent, the registername for the instruction's
189 qualifying predicate. If NULL, p0 is assumed for instructions
190 that are predicatable. */
197 explicit_mode : 1, /* which mode we're in */
198 default_explicit_mode : 1, /* which mode is the default */
199 mode_explicitly_set : 1, /* was the current mode explicitly set? */
201 keep_pending_output : 1;
203 /* Each bundle consists of up to three instructions. We keep
204 track of four most recent instructions so we can correctly set
205 the end_of_insn_group for the last instruction in a bundle. */
207 int num_slots_in_use;
211 end_of_insn_group : 1,
212 manual_bundling_on : 1,
213 manual_bundling_off : 1;
214 signed char user_template; /* user-selected template, if any */
215 unsigned char qp_regno; /* qualifying predicate */
216 /* This duplicates a good fraction of "struct fix" but we
217 can't use a "struct fix" instead since we can't call
218 fix_new_exp() until we know the address of the instruction. */
222 bfd_reloc_code_real_type code;
223 enum ia64_opnd opnd; /* type of operand in need of fix */
224 unsigned int is_pcrel : 1; /* is operand pc-relative? */
225 expressionS expr; /* the value to be inserted */
227 fixup[2]; /* at most two fixups per insn */
228 struct ia64_opcode *idesc;
229 struct label_fix *label_fixups;
230 struct label_fix *tag_fixups;
231 struct unw_rec_list *unwind_record; /* Unwind directive. */
234 unsigned int src_line;
235 struct dwarf2_line_info debug_line;
243 struct dynreg *next; /* next dynamic register */
245 unsigned short base; /* the base register number */
246 unsigned short num_regs; /* # of registers in this set */
248 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
250 flagword flags; /* ELF-header flags */
253 unsigned hint:1; /* is this hint currently valid? */
254 bfd_vma offset; /* mem.offset offset */
255 bfd_vma base; /* mem.offset base */
258 int path; /* number of alt. entry points seen */
259 const char **entry_labels; /* labels of all alternate paths in
260 the current DV-checking block. */
261 int maxpaths; /* size currently allocated for
263 /* Support for hardware errata workarounds. */
265 /* Record data about the last three insn groups. */
268 /* B-step workaround.
269 For each predicate register, this is set if the corresponding insn
270 group conditionally sets this register with one of the affected
273 /* B-step workaround.
274 For each general register, this is set if the corresponding insn
275 a) is conditional one one of the predicate registers for which
276 P_REG_SET is 1 in the corresponding entry of the previous group,
277 b) sets this general register with one of the affected
279 int g_reg_set_conditionally[128];
285 /* application registers: */
291 #define AR_BSPSTORE 18
306 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
307 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
308 {"ar.rsc", 16}, {"ar.bsp", 17},
309 {"ar.bspstore", 18}, {"ar.rnat", 19},
310 {"ar.fcr", 21}, {"ar.eflag", 24},
311 {"ar.csd", 25}, {"ar.ssd", 26},
312 {"ar.cflg", 27}, {"ar.fsr", 28},
313 {"ar.fir", 29}, {"ar.fdr", 30},
314 {"ar.ccv", 32}, {"ar.unat", 36},
315 {"ar.fpsr", 40}, {"ar.itc", 44},
316 {"ar.pfs", 64}, {"ar.lc", 65},
337 /* control registers: */
379 static const struct const_desc
386 /* PSR constant masks: */
389 {"psr.be", ((valueT) 1) << 1},
390 {"psr.up", ((valueT) 1) << 2},
391 {"psr.ac", ((valueT) 1) << 3},
392 {"psr.mfl", ((valueT) 1) << 4},
393 {"psr.mfh", ((valueT) 1) << 5},
395 {"psr.ic", ((valueT) 1) << 13},
396 {"psr.i", ((valueT) 1) << 14},
397 {"psr.pk", ((valueT) 1) << 15},
399 {"psr.dt", ((valueT) 1) << 17},
400 {"psr.dfl", ((valueT) 1) << 18},
401 {"psr.dfh", ((valueT) 1) << 19},
402 {"psr.sp", ((valueT) 1) << 20},
403 {"psr.pp", ((valueT) 1) << 21},
404 {"psr.di", ((valueT) 1) << 22},
405 {"psr.si", ((valueT) 1) << 23},
406 {"psr.db", ((valueT) 1) << 24},
407 {"psr.lp", ((valueT) 1) << 25},
408 {"psr.tb", ((valueT) 1) << 26},
409 {"psr.rt", ((valueT) 1) << 27},
410 /* 28-31: reserved */
411 /* 32-33: cpl (current privilege level) */
412 {"psr.is", ((valueT) 1) << 34},
413 {"psr.mc", ((valueT) 1) << 35},
414 {"psr.it", ((valueT) 1) << 36},
415 {"psr.id", ((valueT) 1) << 37},
416 {"psr.da", ((valueT) 1) << 38},
417 {"psr.dd", ((valueT) 1) << 39},
418 {"psr.ss", ((valueT) 1) << 40},
419 /* 41-42: ri (restart instruction) */
420 {"psr.ed", ((valueT) 1) << 43},
421 {"psr.bn", ((valueT) 1) << 44},
424 /* indirect register-sets/memory: */
433 { "CPUID", IND_CPUID },
434 { "cpuid", IND_CPUID },
446 /* Pseudo functions used to indicate relocation types (these functions
447 start with an at sign (@). */
469 /* reloc pseudo functions (these must come first!): */
470 { "fptr", PSEUDO_FUNC_RELOC, { 0 } },
471 { "gprel", PSEUDO_FUNC_RELOC, { 0 } },
472 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } },
473 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } },
474 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } },
475 { "secrel", PSEUDO_FUNC_RELOC, { 0 } },
476 { "segrel", PSEUDO_FUNC_RELOC, { 0 } },
477 { "ltv", PSEUDO_FUNC_RELOC, { 0 } },
478 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
480 /* mbtype4 constants: */
481 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
482 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
483 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
484 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
485 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
487 /* fclass constants: */
488 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
489 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
490 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
491 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
492 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
493 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
494 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
495 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
496 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
498 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
500 /* unwind-related constants: */
501 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
502 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
503 { "nt", PSEUDO_FUNC_CONST, { 2 } },
505 /* unwind-related registers: */
506 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
509 /* 41-bit nop opcodes (one per unit): */
510 static const bfd_vma nop[IA64_NUM_UNITS] =
512 0x0000000000LL, /* NIL => break 0 */
513 0x0008000000LL, /* I-unit nop */
514 0x0008000000LL, /* M-unit nop */
515 0x4000000000LL, /* B-unit nop */
516 0x0008000000LL, /* F-unit nop */
517 0x0008000000LL, /* L-"unit" nop */
518 0x0008000000LL, /* X-unit nop */
521 /* Can't be `const' as it's passed to input routines (which have the
522 habit of setting temporary sentinels. */
523 static char special_section_name[][20] =
525 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
526 {".IA_64.unwind"}, {".IA_64.unwind_info"}
529 /* The best template for a particular sequence of up to three
531 #define N IA64_NUM_TYPES
532 static unsigned char best_template[N][N][N];
535 /* Resource dependencies currently in effect */
537 int depind; /* dependency index */
538 const struct ia64_dependency *dependency; /* actual dependency */
539 unsigned specific:1, /* is this a specific bit/regno? */
540 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
541 int index; /* specific regno/bit within dependency */
542 int note; /* optional qualifying note (0 if none) */
546 int insn_srlz; /* current insn serialization state */
547 int data_srlz; /* current data serialization state */
548 int qp_regno; /* qualifying predicate for this usage */
549 char *file; /* what file marked this dependency */
550 unsigned int line; /* what line marked this dependency */
551 struct mem_offset mem_offset; /* optional memory offset hint */
552 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
553 int path; /* corresponding code entry index */
555 static int regdepslen = 0;
556 static int regdepstotlen = 0;
557 static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
558 static const char *dv_sem[] = { "none", "implied", "impliedf",
559 "data", "instr", "specific", "stop", "other" };
560 static const char *dv_cmp_type[] = { "none", "OR", "AND" };
562 /* Current state of PR mutexation */
563 static struct qpmutex {
566 } *qp_mutexes = NULL; /* QP mutex bitmasks */
567 static int qp_mutexeslen = 0;
568 static int qp_mutexestotlen = 0;
569 static valueT qp_safe_across_calls = 0;
571 /* Current state of PR implications */
572 static struct qp_imply {
575 unsigned p2_branched:1;
577 } *qp_implies = NULL;
578 static int qp_implieslen = 0;
579 static int qp_impliestotlen = 0;
581 /* Keep track of static GR values so that indirect register usage can
582 sometimes be tracked. */
587 } gr_values[128] = {{ 1, 0, 0 }};
589 /* These are the routines required to output the various types of
592 /* A slot_number is a frag address plus the slot index (0-2). We use the
593 frag address here so that if there is a section switch in the middle of
594 a function, then instructions emitted to a different section are not
595 counted. Since there may be more than one frag for a function, this
596 means we also need to keep track of which frag this address belongs to
597 so we can compute inter-frag distances. This also nicely solves the
598 problem with nops emitted for align directives, which can't easily be
599 counted, but can easily be derived from frag sizes. */
601 typedef struct unw_rec_list {
603 unsigned long slot_number;
605 struct unw_rec_list *next;
608 #define SLOT_NUM_NOT_SET (unsigned)-1
612 unsigned long next_slot_number;
613 fragS *next_slot_frag;
615 /* Maintain a list of unwind entries for the current function. */
619 /* Any unwind entires that should be attached to the current slot
620 that an insn is being constructed for. */
621 unw_rec_list *current_entry;
623 /* These are used to create the unwind table entry for this function. */
626 symbolS *info; /* pointer to unwind info */
627 symbolS *personality_routine;
629 subsegT saved_text_subseg;
630 unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */
632 /* TRUE if processing unwind directives in a prologue region. */
635 unsigned int prologue_count; /* number of .prologues seen so far */
638 typedef void (*vbyte_func) PARAMS ((int, char *, char *));
640 /* Forward delarations: */
641 static int ar_is_in_integer_unit PARAMS ((int regnum));
642 static void set_section PARAMS ((char *name));
643 static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
644 unsigned int, unsigned int));
645 static void dot_radix PARAMS ((int));
646 static void dot_special_section PARAMS ((int));
647 static void dot_proc PARAMS ((int));
648 static void dot_fframe PARAMS ((int));
649 static void dot_vframe PARAMS ((int));
650 static void dot_vframesp PARAMS ((int));
651 static void dot_vframepsp PARAMS ((int));
652 static void dot_save PARAMS ((int));
653 static void dot_restore PARAMS ((int));
654 static void dot_restorereg PARAMS ((int));
655 static void dot_restorereg_p PARAMS ((int));
656 static void dot_handlerdata PARAMS ((int));
657 static void dot_unwentry PARAMS ((int));
658 static void dot_altrp PARAMS ((int));
659 static void dot_savemem PARAMS ((int));
660 static void dot_saveg PARAMS ((int));
661 static void dot_savef PARAMS ((int));
662 static void dot_saveb PARAMS ((int));
663 static void dot_savegf PARAMS ((int));
664 static void dot_spill PARAMS ((int));
665 static void dot_spillreg PARAMS ((int));
666 static void dot_spillmem PARAMS ((int));
667 static void dot_spillreg_p PARAMS ((int));
668 static void dot_spillmem_p PARAMS ((int));
669 static void dot_label_state PARAMS ((int));
670 static void dot_copy_state PARAMS ((int));
671 static void dot_unwabi PARAMS ((int));
672 static void dot_personality PARAMS ((int));
673 static void dot_body PARAMS ((int));
674 static void dot_prologue PARAMS ((int));
675 static void dot_endp PARAMS ((int));
676 static void dot_template PARAMS ((int));
677 static void dot_regstk PARAMS ((int));
678 static void dot_rot PARAMS ((int));
679 static void dot_byteorder PARAMS ((int));
680 static void dot_psr PARAMS ((int));
681 static void dot_alias PARAMS ((int));
682 static void dot_ln PARAMS ((int));
683 static char *parse_section_name PARAMS ((void));
684 static void dot_xdata PARAMS ((int));
685 static void stmt_float_cons PARAMS ((int));
686 static void stmt_cons_ua PARAMS ((int));
687 static void dot_xfloat_cons PARAMS ((int));
688 static void dot_xstringer PARAMS ((int));
689 static void dot_xdata_ua PARAMS ((int));
690 static void dot_xfloat_cons_ua PARAMS ((int));
691 static void print_prmask PARAMS ((valueT mask));
692 static void dot_pred_rel PARAMS ((int));
693 static void dot_reg_val PARAMS ((int));
694 static void dot_dv_mode PARAMS ((int));
695 static void dot_entry PARAMS ((int));
696 static void dot_mem_offset PARAMS ((int));
697 static void add_unwind_entry PARAMS((unw_rec_list *ptr));
698 static symbolS *declare_register PARAMS ((const char *name, int regnum));
699 static void declare_register_set PARAMS ((const char *, int, int));
700 static unsigned int operand_width PARAMS ((enum ia64_opnd));
701 static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc,
704 static int parse_operand PARAMS ((expressionS *e));
705 static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
706 static void build_insn PARAMS ((struct slot *, bfd_vma *));
707 static void emit_one_bundle PARAMS ((void));
708 static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
709 static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
710 bfd_reloc_code_real_type r_type));
711 static void insn_group_break PARAMS ((int, int, int));
712 static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
713 struct rsrc *, int depind, int path));
714 static void add_qp_mutex PARAMS((valueT mask));
715 static void add_qp_imply PARAMS((int p1, int p2));
716 static void clear_qp_branch_flag PARAMS((valueT mask));
717 static void clear_qp_mutex PARAMS((valueT mask));
718 static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
719 static void clear_register_values PARAMS ((void));
720 static void print_dependency PARAMS ((const char *action, int depind));
721 static void instruction_serialization PARAMS ((void));
722 static void data_serialization PARAMS ((void));
723 static void remove_marked_resource PARAMS ((struct rsrc *));
724 static int is_conditional_branch PARAMS ((struct ia64_opcode *));
725 static int is_taken_branch PARAMS ((struct ia64_opcode *));
726 static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
727 static int depends_on PARAMS ((int, struct ia64_opcode *));
728 static int specify_resource PARAMS ((const struct ia64_dependency *,
729 struct ia64_opcode *, int, struct rsrc [], int, int));
730 static int check_dv PARAMS((struct ia64_opcode *idesc));
731 static void check_dependencies PARAMS((struct ia64_opcode *));
732 static void mark_resources PARAMS((struct ia64_opcode *));
733 static void update_dependencies PARAMS((struct ia64_opcode *));
734 static void note_register_values PARAMS((struct ia64_opcode *));
735 static int qp_mutex PARAMS ((int, int, int));
736 static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
737 static void output_vbyte_mem PARAMS ((int, char *, char *));
738 static void count_output PARAMS ((int, char *, char *));
739 static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
740 static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
741 static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
742 static void output_P1_format PARAMS ((vbyte_func, int));
743 static void output_P2_format PARAMS ((vbyte_func, int, int));
744 static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
745 static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
746 static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
747 static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
748 static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
749 static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
750 static void output_P9_format PARAMS ((vbyte_func, int, int));
751 static void output_P10_format PARAMS ((vbyte_func, int, int));
752 static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
753 static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
754 static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
755 static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
756 static char format_ab_reg PARAMS ((int, int));
757 static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
759 static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
760 static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
762 static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
763 static void free_list_records PARAMS ((unw_rec_list *));
764 static unw_rec_list *output_prologue PARAMS ((void));
765 static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
766 static unw_rec_list *output_body PARAMS ((void));
767 static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
768 static unw_rec_list *output_mem_stack_v PARAMS ((void));
769 static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
770 static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
771 static unw_rec_list *output_rp_when PARAMS ((void));
772 static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
773 static unw_rec_list *output_rp_br PARAMS ((unsigned int));
774 static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
775 static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
776 static unw_rec_list *output_pfs_when PARAMS ((void));
777 static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
778 static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
779 static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
780 static unw_rec_list *output_preds_when PARAMS ((void));
781 static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
782 static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
783 static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
784 static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
785 static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
786 static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
787 static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
788 static unw_rec_list *output_br_mem PARAMS ((unsigned int));
789 static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
790 static unw_rec_list *output_spill_base PARAMS ((unsigned int));
791 static unw_rec_list *output_unat_when PARAMS ((void));
792 static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
793 static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
794 static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
795 static unw_rec_list *output_lc_when PARAMS ((void));
796 static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
797 static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
798 static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
799 static unw_rec_list *output_fpsr_when PARAMS ((void));
800 static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
801 static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
802 static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
803 static unw_rec_list *output_priunat_when_gr PARAMS ((void));
804 static unw_rec_list *output_priunat_when_mem PARAMS ((void));
805 static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
806 static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
807 static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
808 static unw_rec_list *output_bsp_when PARAMS ((void));
809 static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
810 static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
811 static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
812 static unw_rec_list *output_bspstore_when PARAMS ((void));
813 static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
814 static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
815 static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
816 static unw_rec_list *output_rnat_when PARAMS ((void));
817 static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
818 static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
819 static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
820 static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
821 static unw_rec_list *output_epilogue PARAMS ((unsigned long));
822 static unw_rec_list *output_label_state PARAMS ((unsigned long));
823 static unw_rec_list *output_copy_state PARAMS ((unsigned long));
824 static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
825 static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
826 static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
828 static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
830 static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
832 static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
833 unsigned int, unsigned int));
834 static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
835 static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
836 static int calc_record_size PARAMS ((unw_rec_list *));
837 static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
838 static int count_bits PARAMS ((unsigned long));
839 static unsigned long slot_index PARAMS ((unsigned long, fragS *,
840 unsigned long, fragS *));
841 static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *));
842 static void fixup_unw_records PARAMS ((unw_rec_list *));
843 static int output_unw_records PARAMS ((unw_rec_list *, void **));
844 static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
845 static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
846 static int generate_unwind_image PARAMS ((const char *));
848 /* Build the unwind section name by appending the (possibly stripped)
849 text section NAME to the unwind PREFIX. The resulting string
850 pointer is assigned to RESULT. The string is allocated on the
851 stack, so this must be a macro... */
852 #define make_unw_section_name(special, text_name, result) \
854 char *_prefix = special_section_name[special]; \
855 size_t _prefix_len = strlen (_prefix), _text_len = strlen (text_name); \
856 char *_result = alloca (_prefix_len + _text_len + 1); \
857 memcpy(_result, _prefix, _prefix_len); \
858 memcpy(_result + _prefix_len, text_name, _text_len); \
859 _result[_prefix_len + _text_len] = '\0'; \
864 /* Determine if application register REGNUM resides in the integer
865 unit (as opposed to the memory unit). */
867 ar_is_in_integer_unit (reg)
872 return (reg == 64 /* pfs */
873 || reg == 65 /* lc */
874 || reg == 66 /* ec */
875 /* ??? ias accepts and puts these in the integer unit. */
876 || (reg >= 112 && reg <= 127));
879 /* Switch to section NAME and create section if necessary. It's
880 rather ugly that we have to manipulate input_line_pointer but I
881 don't see any other way to accomplish the same thing without
882 changing obj-elf.c (which may be the Right Thing, in the end). */
887 char *saved_input_line_pointer;
889 saved_input_line_pointer = input_line_pointer;
890 input_line_pointer = name;
892 input_line_pointer = saved_input_line_pointer;
895 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
898 ia64_elf_section_flags (flags, attr, type)
900 int attr, type ATTRIBUTE_UNUSED;
902 if (attr & SHF_IA_64_SHORT)
903 flags |= SEC_SMALL_DATA;
908 ia64_elf_section_type (str, len)
912 len = sizeof (ELF_STRING_ia64_unwind_info) - 1;
913 if (strncmp (str, ELF_STRING_ia64_unwind_info, len) == 0)
916 len = sizeof (ELF_STRING_ia64_unwind) - 1;
917 if (strncmp (str, ELF_STRING_ia64_unwind, len) == 0)
918 return SHT_IA_64_UNWIND;
924 set_regstack (ins, locs, outs, rots)
925 unsigned int ins, locs, outs, rots;
930 sof = ins + locs + outs;
933 as_bad ("Size of frame exceeds maximum of 96 registers");
938 as_warn ("Size of rotating registers exceeds frame size");
941 md.in.base = REG_GR + 32;
942 md.loc.base = md.in.base + ins;
943 md.out.base = md.loc.base + locs;
945 md.in.num_regs = ins;
946 md.loc.num_regs = locs;
947 md.out.num_regs = outs;
948 md.rot.num_regs = rots;
955 struct label_fix *lfix;
957 subsegT saved_subseg;
960 if (!md.last_text_seg)
964 saved_subseg = now_subseg;
966 subseg_set (md.last_text_seg, 0);
968 while (md.num_slots_in_use > 0)
969 emit_one_bundle (); /* force out queued instructions */
971 /* In case there are labels following the last instruction, resolve
973 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
975 S_SET_VALUE (lfix->sym, frag_now_fix ());
976 symbol_set_frag (lfix->sym, frag_now);
978 CURR_SLOT.label_fixups = 0;
979 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
981 S_SET_VALUE (lfix->sym, frag_now_fix ());
982 symbol_set_frag (lfix->sym, frag_now);
984 CURR_SLOT.tag_fixups = 0;
986 /* In case there are unwind directives following the last instruction,
987 resolve those now. We only handle body and prologue directives here.
988 Give an error for others. */
989 for (ptr = unwind.current_entry; ptr; ptr = ptr->next)
991 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
992 || ptr->r.type == body)
994 ptr->slot_number = (unsigned long) frag_more (0);
995 ptr->slot_frag = frag_now;
998 as_bad (_("Unwind directive not followed by an instruction."));
1000 unwind.current_entry = NULL;
1002 subseg_set (saved_seg, saved_subseg);
1004 if (md.qp.X_op == O_register)
1005 as_bad ("qualifying predicate not followed by instruction");
1009 ia64_do_align (nbytes)
1012 char *saved_input_line_pointer = input_line_pointer;
1014 input_line_pointer = "";
1015 s_align_bytes (nbytes);
1016 input_line_pointer = saved_input_line_pointer;
1020 ia64_cons_align (nbytes)
1025 char *saved_input_line_pointer = input_line_pointer;
1026 input_line_pointer = "";
1027 s_align_bytes (nbytes);
1028 input_line_pointer = saved_input_line_pointer;
1032 /* Output COUNT bytes to a memory location. */
1033 static unsigned char *vbyte_mem_ptr = NULL;
1036 output_vbyte_mem (count, ptr, comment)
1039 char *comment ATTRIBUTE_UNUSED;
1042 if (vbyte_mem_ptr == NULL)
1047 for (x = 0; x < count; x++)
1048 *(vbyte_mem_ptr++) = ptr[x];
1051 /* Count the number of bytes required for records. */
1052 static int vbyte_count = 0;
1054 count_output (count, ptr, comment)
1056 char *ptr ATTRIBUTE_UNUSED;
1057 char *comment ATTRIBUTE_UNUSED;
1059 vbyte_count += count;
1063 output_R1_format (f, rtype, rlen)
1065 unw_record_type rtype;
1072 output_R3_format (f, rtype, rlen);
1078 else if (rtype != prologue)
1079 as_bad ("record type is not valid");
1081 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
1082 (*f) (1, &byte, NULL);
1086 output_R2_format (f, mask, grsave, rlen)
1093 mask = (mask & 0x0f);
1094 grsave = (grsave & 0x7f);
1096 bytes[0] = (UNW_R2 | (mask >> 1));
1097 bytes[1] = (((mask & 0x01) << 7) | grsave);
1098 count += output_leb128 (bytes + 2, rlen, 0);
1099 (*f) (count, bytes, NULL);
1103 output_R3_format (f, rtype, rlen)
1105 unw_record_type rtype;
1112 output_R1_format (f, rtype, rlen);
1118 else if (rtype != prologue)
1119 as_bad ("record type is not valid");
1120 bytes[0] = (UNW_R3 | r);
1121 count = output_leb128 (bytes + 1, rlen, 0);
1122 (*f) (count + 1, bytes, NULL);
1126 output_P1_format (f, brmask)
1131 byte = UNW_P1 | (brmask & 0x1f);
1132 (*f) (1, &byte, NULL);
1136 output_P2_format (f, brmask, gr)
1142 brmask = (brmask & 0x1f);
1143 bytes[0] = UNW_P2 | (brmask >> 1);
1144 bytes[1] = (((brmask & 1) << 7) | gr);
1145 (*f) (2, bytes, NULL);
1149 output_P3_format (f, rtype, reg)
1151 unw_record_type rtype;
1196 as_bad ("Invalid record type for P3 format.");
1198 bytes[0] = (UNW_P3 | (r >> 1));
1199 bytes[1] = (((r & 1) << 7) | reg);
1200 (*f) (2, bytes, NULL);
1204 output_P4_format (f, imask, imask_size)
1206 unsigned char *imask;
1207 unsigned long imask_size;
1210 (*f) (imask_size, imask, NULL);
1214 output_P5_format (f, grmask, frmask)
1217 unsigned long frmask;
1220 grmask = (grmask & 0x0f);
1223 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1224 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1225 bytes[3] = (frmask & 0x000000ff);
1226 (*f) (4, bytes, NULL);
1230 output_P6_format (f, rtype, rmask)
1232 unw_record_type rtype;
1238 if (rtype == gr_mem)
1240 else if (rtype != fr_mem)
1241 as_bad ("Invalid record type for format P6");
1242 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1243 (*f) (1, &byte, NULL);
1247 output_P7_format (f, rtype, w1, w2)
1249 unw_record_type rtype;
1256 count += output_leb128 (bytes + 1, w1, 0);
1261 count += output_leb128 (bytes + count, w2 >> 4, 0);
1311 bytes[0] = (UNW_P7 | r);
1312 (*f) (count, bytes, NULL);
1316 output_P8_format (f, rtype, t)
1318 unw_record_type rtype;
1357 case bspstore_psprel:
1360 case bspstore_sprel:
1372 case priunat_when_gr:
1375 case priunat_psprel:
1381 case priunat_when_mem:
1388 count += output_leb128 (bytes + 2, t, 0);
1389 (*f) (count, bytes, NULL);
1393 output_P9_format (f, grmask, gr)
1400 bytes[1] = (grmask & 0x0f);
1401 bytes[2] = (gr & 0x7f);
1402 (*f) (3, bytes, NULL);
1406 output_P10_format (f, abi, context)
1413 bytes[1] = (abi & 0xff);
1414 bytes[2] = (context & 0xff);
1415 (*f) (3, bytes, NULL);
1419 output_B1_format (f, rtype, label)
1421 unw_record_type rtype;
1422 unsigned long label;
1428 output_B4_format (f, rtype, label);
1431 if (rtype == copy_state)
1433 else if (rtype != label_state)
1434 as_bad ("Invalid record type for format B1");
1436 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1437 (*f) (1, &byte, NULL);
1441 output_B2_format (f, ecount, t)
1443 unsigned long ecount;
1450 output_B3_format (f, ecount, t);
1453 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1454 count += output_leb128 (bytes + 1, t, 0);
1455 (*f) (count, bytes, NULL);
1459 output_B3_format (f, ecount, t)
1461 unsigned long ecount;
1468 output_B2_format (f, ecount, t);
1472 count += output_leb128 (bytes + 1, t, 0);
1473 count += output_leb128 (bytes + count, ecount, 0);
1474 (*f) (count, bytes, NULL);
1478 output_B4_format (f, rtype, label)
1480 unw_record_type rtype;
1481 unsigned long label;
1488 output_B1_format (f, rtype, label);
1492 if (rtype == copy_state)
1494 else if (rtype != label_state)
1495 as_bad ("Invalid record type for format B1");
1497 bytes[0] = (UNW_B4 | (r << 3));
1498 count += output_leb128 (bytes + 1, label, 0);
1499 (*f) (count, bytes, NULL);
1503 format_ab_reg (ab, reg)
1510 ret = (ab << 5) | reg;
1515 output_X1_format (f, rtype, ab, reg, t, w1)
1517 unw_record_type rtype;
1527 if (rtype == spill_sprel)
1529 else if (rtype != spill_psprel)
1530 as_bad ("Invalid record type for format X1");
1531 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
1532 count += output_leb128 (bytes + 2, t, 0);
1533 count += output_leb128 (bytes + count, w1, 0);
1534 (*f) (count, bytes, NULL);
1538 output_X2_format (f, ab, reg, x, y, treg, t)
1547 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1548 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1549 count += output_leb128 (bytes + 3, t, 0);
1550 (*f) (count, bytes, NULL);
1554 output_X3_format (f, rtype, qp, ab, reg, t, w1)
1556 unw_record_type rtype;
1567 if (rtype == spill_sprel_p)
1569 else if (rtype != spill_psprel_p)
1570 as_bad ("Invalid record type for format X3");
1571 bytes[1] = ((r << 7) | (qp & 0x3f));
1572 bytes[2] = format_ab_reg (ab, reg);
1573 count += output_leb128 (bytes + 3, t, 0);
1574 count += output_leb128 (bytes + count, w1, 0);
1575 (*f) (count, bytes, NULL);
1579 output_X4_format (f, qp, ab, reg, x, y, treg, t)
1589 bytes[1] = (qp & 0x3f);
1590 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1591 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1592 count += output_leb128 (bytes + 4, t, 0);
1593 (*f) (count, bytes, NULL);
1596 /* This function allocates a record list structure, and initializes fields. */
1598 static unw_rec_list *
1599 alloc_record (unw_record_type t)
1602 ptr = xmalloc (sizeof (*ptr));
1604 ptr->slot_number = SLOT_NUM_NOT_SET;
1609 /* This function frees an entire list of record structures. */
1612 free_list_records (unw_rec_list *first)
1615 for (ptr = first; ptr != NULL;)
1617 unw_rec_list *tmp = ptr;
1619 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1620 && tmp->r.record.r.mask.i)
1621 free (tmp->r.record.r.mask.i);
1628 static unw_rec_list *
1631 unw_rec_list *ptr = alloc_record (prologue);
1632 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1636 static unw_rec_list *
1637 output_prologue_gr (saved_mask, reg)
1638 unsigned int saved_mask;
1641 unw_rec_list *ptr = alloc_record (prologue_gr);
1642 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1643 ptr->r.record.r.grmask = saved_mask;
1644 ptr->r.record.r.grsave = reg;
1648 static unw_rec_list *
1651 unw_rec_list *ptr = alloc_record (body);
1655 static unw_rec_list *
1656 output_mem_stack_f (size)
1659 unw_rec_list *ptr = alloc_record (mem_stack_f);
1660 ptr->r.record.p.size = size;
1664 static unw_rec_list *
1665 output_mem_stack_v ()
1667 unw_rec_list *ptr = alloc_record (mem_stack_v);
1671 static unw_rec_list *
1675 unw_rec_list *ptr = alloc_record (psp_gr);
1676 ptr->r.record.p.gr = gr;
1680 static unw_rec_list *
1681 output_psp_sprel (offset)
1682 unsigned int offset;
1684 unw_rec_list *ptr = alloc_record (psp_sprel);
1685 ptr->r.record.p.spoff = offset / 4;
1689 static unw_rec_list *
1692 unw_rec_list *ptr = alloc_record (rp_when);
1696 static unw_rec_list *
1700 unw_rec_list *ptr = alloc_record (rp_gr);
1701 ptr->r.record.p.gr = gr;
1705 static unw_rec_list *
1709 unw_rec_list *ptr = alloc_record (rp_br);
1710 ptr->r.record.p.br = br;
1714 static unw_rec_list *
1715 output_rp_psprel (offset)
1716 unsigned int offset;
1718 unw_rec_list *ptr = alloc_record (rp_psprel);
1719 ptr->r.record.p.pspoff = offset / 4;
1723 static unw_rec_list *
1724 output_rp_sprel (offset)
1725 unsigned int offset;
1727 unw_rec_list *ptr = alloc_record (rp_sprel);
1728 ptr->r.record.p.spoff = offset / 4;
1732 static unw_rec_list *
1735 unw_rec_list *ptr = alloc_record (pfs_when);
1739 static unw_rec_list *
1743 unw_rec_list *ptr = alloc_record (pfs_gr);
1744 ptr->r.record.p.gr = gr;
1748 static unw_rec_list *
1749 output_pfs_psprel (offset)
1750 unsigned int offset;
1752 unw_rec_list *ptr = alloc_record (pfs_psprel);
1753 ptr->r.record.p.pspoff = offset / 4;
1757 static unw_rec_list *
1758 output_pfs_sprel (offset)
1759 unsigned int offset;
1761 unw_rec_list *ptr = alloc_record (pfs_sprel);
1762 ptr->r.record.p.spoff = offset / 4;
1766 static unw_rec_list *
1767 output_preds_when ()
1769 unw_rec_list *ptr = alloc_record (preds_when);
1773 static unw_rec_list *
1774 output_preds_gr (gr)
1777 unw_rec_list *ptr = alloc_record (preds_gr);
1778 ptr->r.record.p.gr = gr;
1782 static unw_rec_list *
1783 output_preds_psprel (offset)
1784 unsigned int offset;
1786 unw_rec_list *ptr = alloc_record (preds_psprel);
1787 ptr->r.record.p.pspoff = offset / 4;
1791 static unw_rec_list *
1792 output_preds_sprel (offset)
1793 unsigned int offset;
1795 unw_rec_list *ptr = alloc_record (preds_sprel);
1796 ptr->r.record.p.spoff = offset / 4;
1800 static unw_rec_list *
1801 output_fr_mem (mask)
1804 unw_rec_list *ptr = alloc_record (fr_mem);
1805 ptr->r.record.p.rmask = mask;
1809 static unw_rec_list *
1810 output_frgr_mem (gr_mask, fr_mask)
1811 unsigned int gr_mask;
1812 unsigned int fr_mask;
1814 unw_rec_list *ptr = alloc_record (frgr_mem);
1815 ptr->r.record.p.grmask = gr_mask;
1816 ptr->r.record.p.frmask = fr_mask;
1820 static unw_rec_list *
1821 output_gr_gr (mask, reg)
1825 unw_rec_list *ptr = alloc_record (gr_gr);
1826 ptr->r.record.p.grmask = mask;
1827 ptr->r.record.p.gr = reg;
1831 static unw_rec_list *
1832 output_gr_mem (mask)
1835 unw_rec_list *ptr = alloc_record (gr_mem);
1836 ptr->r.record.p.rmask = mask;
1840 static unw_rec_list *
1841 output_br_mem (unsigned int mask)
1843 unw_rec_list *ptr = alloc_record (br_mem);
1844 ptr->r.record.p.brmask = mask;
1848 static unw_rec_list *
1849 output_br_gr (save_mask, reg)
1850 unsigned int save_mask;
1853 unw_rec_list *ptr = alloc_record (br_gr);
1854 ptr->r.record.p.brmask = save_mask;
1855 ptr->r.record.p.gr = reg;
1859 static unw_rec_list *
1860 output_spill_base (offset)
1861 unsigned int offset;
1863 unw_rec_list *ptr = alloc_record (spill_base);
1864 ptr->r.record.p.pspoff = offset / 4;
1868 static unw_rec_list *
1871 unw_rec_list *ptr = alloc_record (unat_when);
1875 static unw_rec_list *
1879 unw_rec_list *ptr = alloc_record (unat_gr);
1880 ptr->r.record.p.gr = gr;
1884 static unw_rec_list *
1885 output_unat_psprel (offset)
1886 unsigned int offset;
1888 unw_rec_list *ptr = alloc_record (unat_psprel);
1889 ptr->r.record.p.pspoff = offset / 4;
1893 static unw_rec_list *
1894 output_unat_sprel (offset)
1895 unsigned int offset;
1897 unw_rec_list *ptr = alloc_record (unat_sprel);
1898 ptr->r.record.p.spoff = offset / 4;
1902 static unw_rec_list *
1905 unw_rec_list *ptr = alloc_record (lc_when);
1909 static unw_rec_list *
1913 unw_rec_list *ptr = alloc_record (lc_gr);
1914 ptr->r.record.p.gr = gr;
1918 static unw_rec_list *
1919 output_lc_psprel (offset)
1920 unsigned int offset;
1922 unw_rec_list *ptr = alloc_record (lc_psprel);
1923 ptr->r.record.p.pspoff = offset / 4;
1927 static unw_rec_list *
1928 output_lc_sprel (offset)
1929 unsigned int offset;
1931 unw_rec_list *ptr = alloc_record (lc_sprel);
1932 ptr->r.record.p.spoff = offset / 4;
1936 static unw_rec_list *
1939 unw_rec_list *ptr = alloc_record (fpsr_when);
1943 static unw_rec_list *
1947 unw_rec_list *ptr = alloc_record (fpsr_gr);
1948 ptr->r.record.p.gr = gr;
1952 static unw_rec_list *
1953 output_fpsr_psprel (offset)
1954 unsigned int offset;
1956 unw_rec_list *ptr = alloc_record (fpsr_psprel);
1957 ptr->r.record.p.pspoff = offset / 4;
1961 static unw_rec_list *
1962 output_fpsr_sprel (offset)
1963 unsigned int offset;
1965 unw_rec_list *ptr = alloc_record (fpsr_sprel);
1966 ptr->r.record.p.spoff = offset / 4;
1970 static unw_rec_list *
1971 output_priunat_when_gr ()
1973 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1977 static unw_rec_list *
1978 output_priunat_when_mem ()
1980 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1984 static unw_rec_list *
1985 output_priunat_gr (gr)
1988 unw_rec_list *ptr = alloc_record (priunat_gr);
1989 ptr->r.record.p.gr = gr;
1993 static unw_rec_list *
1994 output_priunat_psprel (offset)
1995 unsigned int offset;
1997 unw_rec_list *ptr = alloc_record (priunat_psprel);
1998 ptr->r.record.p.pspoff = offset / 4;
2002 static unw_rec_list *
2003 output_priunat_sprel (offset)
2004 unsigned int offset;
2006 unw_rec_list *ptr = alloc_record (priunat_sprel);
2007 ptr->r.record.p.spoff = offset / 4;
2011 static unw_rec_list *
2014 unw_rec_list *ptr = alloc_record (bsp_when);
2018 static unw_rec_list *
2022 unw_rec_list *ptr = alloc_record (bsp_gr);
2023 ptr->r.record.p.gr = gr;
2027 static unw_rec_list *
2028 output_bsp_psprel (offset)
2029 unsigned int offset;
2031 unw_rec_list *ptr = alloc_record (bsp_psprel);
2032 ptr->r.record.p.pspoff = offset / 4;
2036 static unw_rec_list *
2037 output_bsp_sprel (offset)
2038 unsigned int offset;
2040 unw_rec_list *ptr = alloc_record (bsp_sprel);
2041 ptr->r.record.p.spoff = offset / 4;
2045 static unw_rec_list *
2046 output_bspstore_when ()
2048 unw_rec_list *ptr = alloc_record (bspstore_when);
2052 static unw_rec_list *
2053 output_bspstore_gr (gr)
2056 unw_rec_list *ptr = alloc_record (bspstore_gr);
2057 ptr->r.record.p.gr = gr;
2061 static unw_rec_list *
2062 output_bspstore_psprel (offset)
2063 unsigned int offset;
2065 unw_rec_list *ptr = alloc_record (bspstore_psprel);
2066 ptr->r.record.p.pspoff = offset / 4;
2070 static unw_rec_list *
2071 output_bspstore_sprel (offset)
2072 unsigned int offset;
2074 unw_rec_list *ptr = alloc_record (bspstore_sprel);
2075 ptr->r.record.p.spoff = offset / 4;
2079 static unw_rec_list *
2082 unw_rec_list *ptr = alloc_record (rnat_when);
2086 static unw_rec_list *
2090 unw_rec_list *ptr = alloc_record (rnat_gr);
2091 ptr->r.record.p.gr = gr;
2095 static unw_rec_list *
2096 output_rnat_psprel (offset)
2097 unsigned int offset;
2099 unw_rec_list *ptr = alloc_record (rnat_psprel);
2100 ptr->r.record.p.pspoff = offset / 4;
2104 static unw_rec_list *
2105 output_rnat_sprel (offset)
2106 unsigned int offset;
2108 unw_rec_list *ptr = alloc_record (rnat_sprel);
2109 ptr->r.record.p.spoff = offset / 4;
2113 static unw_rec_list *
2114 output_unwabi (abi, context)
2116 unsigned long context;
2118 unw_rec_list *ptr = alloc_record (unwabi);
2119 ptr->r.record.p.abi = abi;
2120 ptr->r.record.p.context = context;
2124 static unw_rec_list *
2125 output_epilogue (unsigned long ecount)
2127 unw_rec_list *ptr = alloc_record (epilogue);
2128 ptr->r.record.b.ecount = ecount;
2132 static unw_rec_list *
2133 output_label_state (unsigned long label)
2135 unw_rec_list *ptr = alloc_record (label_state);
2136 ptr->r.record.b.label = label;
2140 static unw_rec_list *
2141 output_copy_state (unsigned long label)
2143 unw_rec_list *ptr = alloc_record (copy_state);
2144 ptr->r.record.b.label = label;
2148 static unw_rec_list *
2149 output_spill_psprel (ab, reg, offset)
2152 unsigned int offset;
2154 unw_rec_list *ptr = alloc_record (spill_psprel);
2155 ptr->r.record.x.ab = ab;
2156 ptr->r.record.x.reg = reg;
2157 ptr->r.record.x.pspoff = offset / 4;
2161 static unw_rec_list *
2162 output_spill_sprel (ab, reg, offset)
2165 unsigned int offset;
2167 unw_rec_list *ptr = alloc_record (spill_sprel);
2168 ptr->r.record.x.ab = ab;
2169 ptr->r.record.x.reg = reg;
2170 ptr->r.record.x.spoff = offset / 4;
2174 static unw_rec_list *
2175 output_spill_psprel_p (ab, reg, offset, predicate)
2178 unsigned int offset;
2179 unsigned int predicate;
2181 unw_rec_list *ptr = alloc_record (spill_psprel_p);
2182 ptr->r.record.x.ab = ab;
2183 ptr->r.record.x.reg = reg;
2184 ptr->r.record.x.pspoff = offset / 4;
2185 ptr->r.record.x.qp = predicate;
2189 static unw_rec_list *
2190 output_spill_sprel_p (ab, reg, offset, predicate)
2193 unsigned int offset;
2194 unsigned int predicate;
2196 unw_rec_list *ptr = alloc_record (spill_sprel_p);
2197 ptr->r.record.x.ab = ab;
2198 ptr->r.record.x.reg = reg;
2199 ptr->r.record.x.spoff = offset / 4;
2200 ptr->r.record.x.qp = predicate;
2204 static unw_rec_list *
2205 output_spill_reg (ab, reg, targ_reg, xy)
2208 unsigned int targ_reg;
2211 unw_rec_list *ptr = alloc_record (spill_reg);
2212 ptr->r.record.x.ab = ab;
2213 ptr->r.record.x.reg = reg;
2214 ptr->r.record.x.treg = targ_reg;
2215 ptr->r.record.x.xy = xy;
2219 static unw_rec_list *
2220 output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2223 unsigned int targ_reg;
2225 unsigned int predicate;
2227 unw_rec_list *ptr = alloc_record (spill_reg_p);
2228 ptr->r.record.x.ab = ab;
2229 ptr->r.record.x.reg = reg;
2230 ptr->r.record.x.treg = targ_reg;
2231 ptr->r.record.x.xy = xy;
2232 ptr->r.record.x.qp = predicate;
2236 /* Given a unw_rec_list process the correct format with the
2237 specified function. */
2240 process_one_record (ptr, f)
2244 unsigned long fr_mask, gr_mask;
2246 switch (ptr->r.type)
2252 /* These are taken care of by prologue/prologue_gr. */
2257 if (ptr->r.type == prologue_gr)
2258 output_R2_format (f, ptr->r.record.r.grmask,
2259 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2261 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2263 /* Output descriptor(s) for union of register spills (if any). */
2264 gr_mask = ptr->r.record.r.mask.gr_mem;
2265 fr_mask = ptr->r.record.r.mask.fr_mem;
2268 if ((fr_mask & ~0xfUL) == 0)
2269 output_P6_format (f, fr_mem, fr_mask);
2272 output_P5_format (f, gr_mask, fr_mask);
2277 output_P6_format (f, gr_mem, gr_mask);
2278 if (ptr->r.record.r.mask.br_mem)
2279 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2281 /* output imask descriptor if necessary: */
2282 if (ptr->r.record.r.mask.i)
2283 output_P4_format (f, ptr->r.record.r.mask.i,
2284 ptr->r.record.r.imask_size);
2288 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2292 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2293 ptr->r.record.p.size);
2306 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2309 output_P3_format (f, rp_br, ptr->r.record.p.br);
2312 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2320 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2329 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2339 case bspstore_sprel:
2341 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2344 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2347 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2350 as_bad ("spill_mask record unimplemented.");
2352 case priunat_when_gr:
2353 case priunat_when_mem:
2357 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2359 case priunat_psprel:
2361 case bspstore_psprel:
2363 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2366 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2369 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2373 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2376 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2377 ptr->r.record.x.reg, ptr->r.record.x.t,
2378 ptr->r.record.x.pspoff);
2381 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2382 ptr->r.record.x.reg, ptr->r.record.x.t,
2383 ptr->r.record.x.spoff);
2386 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2387 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2388 ptr->r.record.x.treg, ptr->r.record.x.t);
2390 case spill_psprel_p:
2391 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2392 ptr->r.record.x.ab, ptr->r.record.x.reg,
2393 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2396 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2397 ptr->r.record.x.ab, ptr->r.record.x.reg,
2398 ptr->r.record.x.t, ptr->r.record.x.spoff);
2401 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2402 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2403 ptr->r.record.x.xy, ptr->r.record.x.treg,
2407 as_bad ("record_type_not_valid");
2412 /* Given a unw_rec_list list, process all the records with
2413 the specified function. */
2415 process_unw_records (list, f)
2420 for (ptr = list; ptr; ptr = ptr->next)
2421 process_one_record (ptr, f);
2424 /* Determine the size of a record list in bytes. */
2426 calc_record_size (list)
2430 process_unw_records (list, count_output);
2434 /* Update IMASK bitmask to reflect the fact that one or more registers
2435 of type TYPE are saved starting at instruction with index T. If N
2436 bits are set in REGMASK, it is assumed that instructions T through
2437 T+N-1 save these registers.
2441 1: instruction saves next fp reg
2442 2: instruction saves next general reg
2443 3: instruction saves next branch reg */
2445 set_imask (region, regmask, t, type)
2446 unw_rec_list *region;
2447 unsigned long regmask;
2451 unsigned char *imask;
2452 unsigned long imask_size;
2456 imask = region->r.record.r.mask.i;
2457 imask_size = region->r.record.r.imask_size;
2460 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
2461 imask = xmalloc (imask_size);
2462 memset (imask, 0, imask_size);
2464 region->r.record.r.imask_size = imask_size;
2465 region->r.record.r.mask.i = imask;
2469 pos = 2 * (3 - t % 4);
2472 if (i >= imask_size)
2474 as_bad ("Ignoring attempt to spill beyond end of region");
2478 imask[i] |= (type & 0x3) << pos;
2480 regmask &= (regmask - 1);
2491 count_bits (unsigned long mask)
2503 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2504 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2505 containing FIRST_ADDR. */
2508 slot_index (slot_addr, slot_frag, first_addr, first_frag)
2509 unsigned long slot_addr;
2511 unsigned long first_addr;
2514 unsigned long index = 0;
2516 /* First time we are called, the initial address and frag are invalid. */
2517 if (first_addr == 0)
2520 /* If the two addresses are in different frags, then we need to add in
2521 the remaining size of this frag, and then the entire size of intermediate
2523 while (slot_frag != first_frag)
2525 unsigned long start_addr = (unsigned long) &first_frag->fr_literal;
2527 /* Add in the full size of the frag converted to instruction slots. */
2528 index += 3 * (first_frag->fr_fix >> 4);
2529 /* Subtract away the initial part before first_addr. */
2530 index -= (3 * ((first_addr >> 4) - (start_addr >> 4))
2531 + ((first_addr & 0x3) - (start_addr & 0x3)));
2533 /* Move to the beginning of the next frag. */
2534 first_frag = first_frag->fr_next;
2535 first_addr = (unsigned long) &first_frag->fr_literal;
2538 /* Add in the used part of the last frag. */
2539 index += (3 * ((slot_addr >> 4) - (first_addr >> 4))
2540 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2544 /* Optimize unwind record directives. */
2546 static unw_rec_list *
2547 optimize_unw_records (list)
2553 /* If the only unwind record is ".prologue" or ".prologue" followed
2554 by ".body", then we can optimize the unwind directives away. */
2555 if (list->r.type == prologue
2556 && (list->next == NULL
2557 || (list->next->r.type == body && list->next->next == NULL)))
2563 /* Given a complete record list, process any records which have
2564 unresolved fields, (ie length counts for a prologue). After
2565 this has been run, all neccessary information should be available
2566 within each record to generate an image. */
2569 fixup_unw_records (list)
2572 unw_rec_list *ptr, *region = 0;
2573 unsigned long first_addr = 0, rlen = 0, t;
2574 fragS *first_frag = 0;
2576 for (ptr = list; ptr; ptr = ptr->next)
2578 if (ptr->slot_number == SLOT_NUM_NOT_SET)
2579 as_bad (" Insn slot not set in unwind record.");
2580 t = slot_index (ptr->slot_number, ptr->slot_frag,
2581 first_addr, first_frag);
2582 switch (ptr->r.type)
2589 int size, dir_len = 0;
2590 unsigned long last_addr;
2593 first_addr = ptr->slot_number;
2594 first_frag = ptr->slot_frag;
2595 ptr->slot_number = 0;
2596 /* Find either the next body/prologue start, or the end of
2597 the list, and determine the size of the region. */
2598 last_addr = unwind.next_slot_number;
2599 last_frag = unwind.next_slot_frag;
2600 for (last = ptr->next; last != NULL; last = last->next)
2601 if (last->r.type == prologue || last->r.type == prologue_gr
2602 || last->r.type == body)
2604 last_addr = last->slot_number;
2605 last_frag = last->slot_frag;
2608 else if (!last->next)
2610 /* In the absence of an explicit .body directive,
2611 the prologue ends after the last instruction
2612 covered by an unwind directive. */
2613 if (ptr->r.type != body)
2615 last_addr = last->slot_number;
2616 last_frag = last->slot_frag;
2617 switch (last->r.type)
2620 dir_len = (count_bits (last->r.record.p.frmask)
2621 + count_bits (last->r.record.p.grmask));
2625 dir_len += count_bits (last->r.record.p.rmask);
2629 dir_len += count_bits (last->r.record.p.brmask);
2632 dir_len += count_bits (last->r.record.p.grmask);
2641 size = (slot_index (last_addr, last_frag, first_addr, first_frag)
2643 rlen = ptr->r.record.r.rlen = size;
2648 ptr->r.record.b.t = rlen - 1 - t;
2659 case priunat_when_gr:
2660 case priunat_when_mem:
2664 ptr->r.record.p.t = t;
2672 case spill_psprel_p:
2673 ptr->r.record.x.t = t;
2679 as_bad ("frgr_mem record before region record!\n");
2682 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2683 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2684 set_imask (region, ptr->r.record.p.frmask, t, 1);
2685 set_imask (region, ptr->r.record.p.grmask, t, 2);
2690 as_bad ("fr_mem record before region record!\n");
2693 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2694 set_imask (region, ptr->r.record.p.rmask, t, 1);
2699 as_bad ("gr_mem record before region record!\n");
2702 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2703 set_imask (region, ptr->r.record.p.rmask, t, 2);
2708 as_bad ("br_mem record before region record!\n");
2711 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2712 set_imask (region, ptr->r.record.p.brmask, t, 3);
2718 as_bad ("gr_gr record before region record!\n");
2721 set_imask (region, ptr->r.record.p.grmask, t, 2);
2726 as_bad ("br_gr record before region record!\n");
2729 set_imask (region, ptr->r.record.p.brmask, t, 3);
2738 /* Generate an unwind image from a record list. Returns the number of
2739 bytes in the resulting image. The memory image itselof is returned
2740 in the 'ptr' parameter. */
2742 output_unw_records (list, ptr)
2746 int size, x, extra = 0;
2751 list = optimize_unw_records (list);
2752 fixup_unw_records (list);
2753 size = calc_record_size (list);
2755 /* pad to 8 byte boundry. */
2760 if (size > 0 || unwind.force_unwind_entry)
2762 unwind.force_unwind_entry = 0;
2764 /* Add 8 for the header + 8 more bytes for the personality offset. */
2765 mem = xmalloc (size + extra + 16);
2767 vbyte_mem_ptr = mem + 8;
2768 /* Clear the padding area and personality. */
2769 memset (mem + 8 + size, 0 , extra + 8);
2770 /* Initialize the header area. */
2771 md_number_to_chars (mem,
2772 (((bfd_vma) 1 << 48) /* version */
2773 | (unwind.personality_routine
2774 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2776 | ((size + extra) / 8)), /* length (dwords) */
2779 process_unw_records (list, output_vbyte_mem);
2789 convert_expr_to_ab_reg (e, ab, regp)
2796 if (e->X_op != O_register)
2799 reg = e->X_add_number;
2800 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7))
2803 *regp = reg - REG_GR;
2805 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5))
2806 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31)))
2809 *regp = reg - REG_FR;
2811 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5))
2814 *regp = reg - REG_BR;
2821 case REG_PR: *regp = 0; break;
2822 case REG_PSP: *regp = 1; break;
2823 case REG_PRIUNAT: *regp = 2; break;
2824 case REG_BR + 0: *regp = 3; break;
2825 case REG_AR + AR_BSP: *regp = 4; break;
2826 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2827 case REG_AR + AR_RNAT: *regp = 6; break;
2828 case REG_AR + AR_UNAT: *regp = 7; break;
2829 case REG_AR + AR_FPSR: *regp = 8; break;
2830 case REG_AR + AR_PFS: *regp = 9; break;
2831 case REG_AR + AR_LC: *regp = 10; break;
2841 convert_expr_to_xy_reg (e, xy, regp)
2848 if (e->X_op != O_register)
2851 reg = e->X_add_number;
2853 if (/* reg >= REG_GR && */ reg <= (REG_GR + 127))
2856 *regp = reg - REG_GR;
2858 else if (reg >= REG_FR && reg <= (REG_FR + 127))
2861 *regp = reg - REG_FR;
2863 else if (reg >= REG_BR && reg <= (REG_BR + 7))
2866 *regp = reg - REG_BR;
2875 int dummy ATTRIBUTE_UNUSED;
2880 radix = *input_line_pointer++;
2882 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2884 as_bad ("Radix `%c' unsupported", *input_line_pointer);
2885 ignore_rest_of_line ();
2890 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2892 dot_special_section (which)
2895 set_section ((char *) special_section_name[which]);
2899 add_unwind_entry (ptr)
2903 unwind.tail->next = ptr;
2908 /* The current entry can in fact be a chain of unwind entries. */
2909 if (unwind.current_entry == NULL)
2910 unwind.current_entry = ptr;
2915 int dummy ATTRIBUTE_UNUSED;
2921 if (e.X_op != O_constant)
2922 as_bad ("Operand to .fframe must be a constant");
2924 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2929 int dummy ATTRIBUTE_UNUSED;
2935 reg = e.X_add_number - REG_GR;
2936 if (e.X_op == O_register && reg < 128)
2938 add_unwind_entry (output_mem_stack_v ());
2939 if (! (unwind.prologue_mask & 2))
2940 add_unwind_entry (output_psp_gr (reg));
2943 as_bad ("First operand to .vframe must be a general register");
2947 dot_vframesp (dummy)
2948 int dummy ATTRIBUTE_UNUSED;
2953 if (e.X_op == O_constant)
2955 add_unwind_entry (output_mem_stack_v ());
2956 add_unwind_entry (output_psp_sprel (e.X_add_number));
2959 as_bad ("First operand to .vframesp must be a general register");
2963 dot_vframepsp (dummy)
2964 int dummy ATTRIBUTE_UNUSED;
2969 if (e.X_op == O_constant)
2971 add_unwind_entry (output_mem_stack_v ());
2972 add_unwind_entry (output_psp_sprel (e.X_add_number));
2975 as_bad ("First operand to .vframepsp must be a general register");
2980 int dummy ATTRIBUTE_UNUSED;
2986 sep = parse_operand (&e1);
2988 as_bad ("No second operand to .save");
2989 sep = parse_operand (&e2);
2991 reg1 = e1.X_add_number;
2992 reg2 = e2.X_add_number - REG_GR;
2994 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2995 if (e1.X_op == O_register)
2997 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
3001 case REG_AR + AR_BSP:
3002 add_unwind_entry (output_bsp_when ());
3003 add_unwind_entry (output_bsp_gr (reg2));
3005 case REG_AR + AR_BSPSTORE:
3006 add_unwind_entry (output_bspstore_when ());
3007 add_unwind_entry (output_bspstore_gr (reg2));
3009 case REG_AR + AR_RNAT:
3010 add_unwind_entry (output_rnat_when ());
3011 add_unwind_entry (output_rnat_gr (reg2));
3013 case REG_AR + AR_UNAT:
3014 add_unwind_entry (output_unat_when ());
3015 add_unwind_entry (output_unat_gr (reg2));
3017 case REG_AR + AR_FPSR:
3018 add_unwind_entry (output_fpsr_when ());
3019 add_unwind_entry (output_fpsr_gr (reg2));
3021 case REG_AR + AR_PFS:
3022 add_unwind_entry (output_pfs_when ());
3023 if (! (unwind.prologue_mask & 4))
3024 add_unwind_entry (output_pfs_gr (reg2));
3026 case REG_AR + AR_LC:
3027 add_unwind_entry (output_lc_when ());
3028 add_unwind_entry (output_lc_gr (reg2));
3031 add_unwind_entry (output_rp_when ());
3032 if (! (unwind.prologue_mask & 8))
3033 add_unwind_entry (output_rp_gr (reg2));
3036 add_unwind_entry (output_preds_when ());
3037 if (! (unwind.prologue_mask & 1))
3038 add_unwind_entry (output_preds_gr (reg2));
3041 add_unwind_entry (output_priunat_when_gr ());
3042 add_unwind_entry (output_priunat_gr (reg2));
3045 as_bad ("First operand not a valid register");
3049 as_bad (" Second operand not a valid register");
3052 as_bad ("First operand not a register");
3057 int dummy ATTRIBUTE_UNUSED;
3060 unsigned long ecount; /* # of _additional_ regions to pop */
3063 sep = parse_operand (&e1);
3064 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
3066 as_bad ("First operand to .restore must be stack pointer (sp)");
3072 parse_operand (&e2);
3073 if (e2.X_op != O_constant || e2.X_add_number < 0)
3075 as_bad ("Second operand to .restore must be a constant >= 0");
3078 ecount = e2.X_add_number;
3081 ecount = unwind.prologue_count - 1;
3082 add_unwind_entry (output_epilogue (ecount));
3084 if (ecount < unwind.prologue_count)
3085 unwind.prologue_count -= ecount + 1;
3087 unwind.prologue_count = 0;
3091 dot_restorereg (dummy)
3092 int dummy ATTRIBUTE_UNUSED;
3094 unsigned int ab, reg;
3099 if (!convert_expr_to_ab_reg (&e, &ab, ®))
3101 as_bad ("First operand to .restorereg must be a preserved register");
3104 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
3108 dot_restorereg_p (dummy)
3109 int dummy ATTRIBUTE_UNUSED;
3111 unsigned int qp, ab, reg;
3115 sep = parse_operand (&e1);
3118 as_bad ("No second operand to .restorereg.p");
3122 parse_operand (&e2);
3124 qp = e1.X_add_number - REG_P;
3125 if (e1.X_op != O_register || qp > 63)
3127 as_bad ("First operand to .restorereg.p must be a predicate");
3131 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3133 as_bad ("Second operand to .restorereg.p must be a preserved register");
3136 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
3140 generate_unwind_image (text_name)
3141 const char *text_name;
3144 unsigned char *unw_rec;
3146 /* Force out pending instructions, to make sure all unwind records have
3147 a valid slot_number field. */
3148 ia64_flush_insns ();
3150 /* Generate the unwind record. */
3151 size = output_unw_records (unwind.list, (void **) &unw_rec);
3153 as_bad ("Unwind record is not a multiple of 8 bytes.");
3155 /* If there are unwind records, switch sections, and output the info. */
3158 unsigned char *where;
3162 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name);
3163 set_section (sec_name);
3164 bfd_set_section_flags (stdoutput, now_seg,
3165 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
3167 /* Make sure the section has 8 byte alignment. */
3168 record_alignment (now_seg, 3);
3170 /* Set expression which points to start of unwind descriptor area. */
3171 unwind.info = expr_build_dot ();
3173 where = (unsigned char *) frag_more (size);
3175 /* Issue a label for this address, and keep track of it to put it
3176 in the unwind section. */
3178 /* Copy the information from the unwind record into this section. The
3179 data is already in the correct byte order. */
3180 memcpy (where, unw_rec, size);
3182 /* Add the personality address to the image. */
3183 if (unwind.personality_routine != 0)
3185 exp.X_op = O_symbol;
3186 exp.X_add_symbol = unwind.personality_routine;
3187 exp.X_add_number = 0;
3188 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
3189 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
3190 unwind.personality_routine = 0;
3194 free_list_records (unwind.list);
3195 unwind.list = unwind.tail = unwind.current_entry = NULL;
3201 dot_handlerdata (dummy)
3202 int dummy ATTRIBUTE_UNUSED;
3204 const char *text_name = segment_name (now_seg);
3206 /* If text section name starts with ".text" (which it should),
3207 strip this prefix off. */
3208 if (strcmp (text_name, ".text") == 0)
3211 unwind.force_unwind_entry = 1;
3213 /* Remember which segment we're in so we can switch back after .endp */
3214 unwind.saved_text_seg = now_seg;
3215 unwind.saved_text_subseg = now_subseg;
3217 /* Generate unwind info into unwind-info section and then leave that
3218 section as the currently active one so dataXX directives go into
3219 the language specific data area of the unwind info block. */
3220 generate_unwind_image (text_name);
3221 demand_empty_rest_of_line ();
3225 dot_unwentry (dummy)
3226 int dummy ATTRIBUTE_UNUSED;
3228 unwind.force_unwind_entry = 1;
3229 demand_empty_rest_of_line ();
3234 int dummy ATTRIBUTE_UNUSED;
3240 reg = e.X_add_number - REG_BR;
3241 if (e.X_op == O_register && reg < 8)
3242 add_unwind_entry (output_rp_br (reg));
3244 as_bad ("First operand not a valid branch register");
3248 dot_savemem (psprel)
3255 sep = parse_operand (&e1);
3257 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
3258 sep = parse_operand (&e2);
3260 reg1 = e1.X_add_number;
3261 val = e2.X_add_number;
3263 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3264 if (e1.X_op == O_register)
3266 if (e2.X_op == O_constant)
3270 case REG_AR + AR_BSP:
3271 add_unwind_entry (output_bsp_when ());
3272 add_unwind_entry ((psprel
3274 : output_bsp_sprel) (val));
3276 case REG_AR + AR_BSPSTORE:
3277 add_unwind_entry (output_bspstore_when ());
3278 add_unwind_entry ((psprel
3279 ? output_bspstore_psprel
3280 : output_bspstore_sprel) (val));
3282 case REG_AR + AR_RNAT:
3283 add_unwind_entry (output_rnat_when ());
3284 add_unwind_entry ((psprel
3285 ? output_rnat_psprel
3286 : output_rnat_sprel) (val));
3288 case REG_AR + AR_UNAT:
3289 add_unwind_entry (output_unat_when ());
3290 add_unwind_entry ((psprel
3291 ? output_unat_psprel
3292 : output_unat_sprel) (val));
3294 case REG_AR + AR_FPSR:
3295 add_unwind_entry (output_fpsr_when ());
3296 add_unwind_entry ((psprel
3297 ? output_fpsr_psprel
3298 : output_fpsr_sprel) (val));
3300 case REG_AR + AR_PFS:
3301 add_unwind_entry (output_pfs_when ());
3302 add_unwind_entry ((psprel
3304 : output_pfs_sprel) (val));
3306 case REG_AR + AR_LC:
3307 add_unwind_entry (output_lc_when ());
3308 add_unwind_entry ((psprel
3310 : output_lc_sprel) (val));
3313 add_unwind_entry (output_rp_when ());
3314 add_unwind_entry ((psprel
3316 : output_rp_sprel) (val));
3319 add_unwind_entry (output_preds_when ());
3320 add_unwind_entry ((psprel
3321 ? output_preds_psprel
3322 : output_preds_sprel) (val));
3325 add_unwind_entry (output_priunat_when_mem ());
3326 add_unwind_entry ((psprel
3327 ? output_priunat_psprel
3328 : output_priunat_sprel) (val));
3331 as_bad ("First operand not a valid register");
3335 as_bad (" Second operand not a valid constant");
3338 as_bad ("First operand not a register");
3343 int dummy ATTRIBUTE_UNUSED;
3347 sep = parse_operand (&e1);
3349 parse_operand (&e2);
3351 if (e1.X_op != O_constant)
3352 as_bad ("First operand to .save.g must be a constant.");
3355 int grmask = e1.X_add_number;
3357 add_unwind_entry (output_gr_mem (grmask));
3360 int reg = e2.X_add_number - REG_GR;
3361 if (e2.X_op == O_register && reg >= 0 && reg < 128)
3362 add_unwind_entry (output_gr_gr (grmask, reg));
3364 as_bad ("Second operand is an invalid register.");
3371 int dummy ATTRIBUTE_UNUSED;
3375 sep = parse_operand (&e1);
3377 if (e1.X_op != O_constant)
3378 as_bad ("Operand to .save.f must be a constant.");
3380 add_unwind_entry (output_fr_mem (e1.X_add_number));
3385 int dummy ATTRIBUTE_UNUSED;
3392 sep = parse_operand (&e1);
3393 if (e1.X_op != O_constant)
3395 as_bad ("First operand to .save.b must be a constant.");
3398 brmask = e1.X_add_number;
3402 sep = parse_operand (&e2);
3403 reg = e2.X_add_number - REG_GR;
3404 if (e2.X_op != O_register || reg > 127)
3406 as_bad ("Second operand to .save.b must be a general register.");
3409 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3412 add_unwind_entry (output_br_mem (brmask));
3414 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3415 ignore_rest_of_line ();
3420 int dummy ATTRIBUTE_UNUSED;
3424 sep = parse_operand (&e1);
3426 parse_operand (&e2);
3428 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3429 as_bad ("Both operands of .save.gf must be constants.");
3432 int grmask = e1.X_add_number;
3433 int frmask = e2.X_add_number;
3434 add_unwind_entry (output_frgr_mem (grmask, frmask));
3440 int dummy ATTRIBUTE_UNUSED;
3445 sep = parse_operand (&e);
3446 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3447 ignore_rest_of_line ();
3449 if (e.X_op != O_constant)
3450 as_bad ("Operand to .spill must be a constant");
3452 add_unwind_entry (output_spill_base (e.X_add_number));
3456 dot_spillreg (dummy)
3457 int dummy ATTRIBUTE_UNUSED;
3459 int sep, ab, xy, reg, treg;
3462 sep = parse_operand (&e1);
3465 as_bad ("No second operand to .spillreg");
3469 parse_operand (&e2);
3471 if (!convert_expr_to_ab_reg (&e1, &ab, ®))
3473 as_bad ("First operand to .spillreg must be a preserved register");
3477 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3479 as_bad ("Second operand to .spillreg must be a register");
3483 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3487 dot_spillmem (psprel)
3493 sep = parse_operand (&e1);
3496 as_bad ("Second operand missing");
3500 parse_operand (&e2);
3502 if (!convert_expr_to_ab_reg (&e1, &ab, ®))
3504 as_bad ("First operand to .spill%s must be a preserved register",
3505 psprel ? "psp" : "sp");
3509 if (e2.X_op != O_constant)
3511 as_bad ("Second operand to .spill%s must be a constant",
3512 psprel ? "psp" : "sp");
3517 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3519 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3523 dot_spillreg_p (dummy)
3524 int dummy ATTRIBUTE_UNUSED;
3526 int sep, ab, xy, reg, treg;
3527 expressionS e1, e2, e3;
3530 sep = parse_operand (&e1);
3533 as_bad ("No second and third operand to .spillreg.p");
3537 sep = parse_operand (&e2);
3540 as_bad ("No third operand to .spillreg.p");
3544 parse_operand (&e3);
3546 qp = e1.X_add_number - REG_P;
3548 if (e1.X_op != O_register || qp > 63)
3550 as_bad ("First operand to .spillreg.p must be a predicate");
3554 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3556 as_bad ("Second operand to .spillreg.p must be a preserved register");
3560 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3562 as_bad ("Third operand to .spillreg.p must be a register");
3566 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3570 dot_spillmem_p (psprel)
3573 expressionS e1, e2, e3;
3577 sep = parse_operand (&e1);
3580 as_bad ("Second operand missing");
3584 parse_operand (&e2);
3587 as_bad ("Second operand missing");
3591 parse_operand (&e3);
3593 qp = e1.X_add_number - REG_P;
3594 if (e1.X_op != O_register || qp > 63)
3596 as_bad ("First operand to .spill%s_p must be a predicate",
3597 psprel ? "psp" : "sp");
3601 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3603 as_bad ("Second operand to .spill%s_p must be a preserved register",
3604 psprel ? "psp" : "sp");
3608 if (e3.X_op != O_constant)
3610 as_bad ("Third operand to .spill%s_p must be a constant",
3611 psprel ? "psp" : "sp");
3616 add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
3618 add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
3622 dot_label_state (dummy)
3623 int dummy ATTRIBUTE_UNUSED;
3628 if (e.X_op != O_constant)
3630 as_bad ("Operand to .label_state must be a constant");
3633 add_unwind_entry (output_label_state (e.X_add_number));
3637 dot_copy_state (dummy)
3638 int dummy ATTRIBUTE_UNUSED;
3643 if (e.X_op != O_constant)
3645 as_bad ("Operand to .copy_state must be a constant");
3648 add_unwind_entry (output_copy_state (e.X_add_number));
3653 int dummy ATTRIBUTE_UNUSED;
3658 sep = parse_operand (&e1);
3661 as_bad ("Second operand to .unwabi missing");
3664 sep = parse_operand (&e2);
3665 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3666 ignore_rest_of_line ();
3668 if (e1.X_op != O_constant)
3670 as_bad ("First operand to .unwabi must be a constant");
3674 if (e2.X_op != O_constant)
3676 as_bad ("Second operand to .unwabi must be a constant");
3680 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
3684 dot_personality (dummy)
3685 int dummy ATTRIBUTE_UNUSED;
3689 name = input_line_pointer;
3690 c = get_symbol_end ();
3691 p = input_line_pointer;
3692 unwind.personality_routine = symbol_find_or_make (name);
3693 unwind.force_unwind_entry = 1;
3696 demand_empty_rest_of_line ();
3701 int dummy ATTRIBUTE_UNUSED;
3706 unwind.proc_start = expr_build_dot ();
3707 /* Parse names of main and alternate entry points and mark them as
3708 function symbols: */
3712 name = input_line_pointer;
3713 c = get_symbol_end ();
3714 p = input_line_pointer;
3715 sym = symbol_find_or_make (name);
3716 if (unwind.proc_start == 0)
3718 unwind.proc_start = sym;
3720 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3723 if (*input_line_pointer != ',')
3725 ++input_line_pointer;
3727 demand_empty_rest_of_line ();
3730 unwind.prologue_count = 0;
3731 unwind.list = unwind.tail = unwind.current_entry = NULL;
3732 unwind.personality_routine = 0;
3737 int dummy ATTRIBUTE_UNUSED;
3739 unwind.prologue = 0;
3740 unwind.prologue_mask = 0;
3742 add_unwind_entry (output_body ());
3743 demand_empty_rest_of_line ();
3747 dot_prologue (dummy)
3748 int dummy ATTRIBUTE_UNUSED;
3751 int mask = 0, grsave = 0;
3753 if (!is_it_end_of_statement ())
3756 sep = parse_operand (&e1);
3758 as_bad ("No second operand to .prologue");
3759 sep = parse_operand (&e2);
3760 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3761 ignore_rest_of_line ();
3763 if (e1.X_op == O_constant)
3765 mask = e1.X_add_number;
3767 if (e2.X_op == O_constant)
3768 grsave = e2.X_add_number;
3769 else if (e2.X_op == O_register
3770 && (grsave = e2.X_add_number - REG_GR) < 128)
3773 as_bad ("Second operand not a constant or general register");
3775 add_unwind_entry (output_prologue_gr (mask, grsave));
3778 as_bad ("First operand not a constant");
3781 add_unwind_entry (output_prologue ());
3783 unwind.prologue = 1;
3784 unwind.prologue_mask = mask;
3785 ++unwind.prologue_count;
3790 int dummy ATTRIBUTE_UNUSED;
3794 int bytes_per_address;
3797 subsegT saved_subseg;
3798 const char *sec_name, *text_name;
3800 if (unwind.saved_text_seg)
3802 saved_seg = unwind.saved_text_seg;
3803 saved_subseg = unwind.saved_text_subseg;
3804 unwind.saved_text_seg = NULL;
3808 saved_seg = now_seg;
3809 saved_subseg = now_subseg;
3813 Use a slightly ugly scheme to derive the unwind section names from
3814 the text section name:
3816 text sect. unwind table sect.
3817 name: name: comments:
3818 ---------- ----------------- --------------------------------
3820 .text.foo .IA_64.unwind.text.foo
3821 .foo .IA_64.unwind.foo
3822 _info .IA_64.unwind_info gas issues error message (ditto)
3823 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
3825 This mapping is done so that:
3827 (a) An object file with unwind info only in .text will use
3828 unwind section names .IA_64.unwind and .IA_64.unwind_info.
3829 This follows the letter of the ABI and also ensures backwards
3830 compatibility with older toolchains.
3832 (b) An object file with unwind info in multiple text sections
3833 will use separate unwind sections for each text section.
3834 This allows us to properly set the "sh_info" and "sh_link"
3835 fields in SHT_IA_64_UNWIND as required by the ABI and also
3836 lets GNU ld support programs with multiple segments
3837 containing unwind info (as might be the case for certain
3838 embedded applications).
3840 (c) An error is issued if there would be a name clash.
3842 text_name = segment_name (saved_seg);
3843 if (strncmp (text_name, "_info", 5) == 0)
3845 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
3847 ignore_rest_of_line ();
3850 if (strcmp (text_name, ".text") == 0)
3854 demand_empty_rest_of_line ();
3856 insn_group_break (1, 0, 0);
3858 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
3860 generate_unwind_image (text_name);
3862 if (unwind.info || unwind.force_unwind_entry)
3864 subseg_set (md.last_text_seg, 0);
3865 unwind.proc_end = expr_build_dot ();
3867 make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name);
3868 set_section ((char *) sec_name);
3869 bfd_set_section_flags (stdoutput, now_seg,
3870 SEC_LOAD | SEC_ALLOC | SEC_READONLY);
3872 /* Make sure the section has 8 byte alignment. */
3873 record_alignment (now_seg, 3);
3875 ptr = frag_more (24);
3876 where = frag_now_fix () - 24;
3877 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
3879 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3880 e.X_op = O_pseudo_fixup;
3881 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3883 e.X_add_symbol = unwind.proc_start;
3884 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
3886 e.X_op = O_pseudo_fixup;
3887 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3889 e.X_add_symbol = unwind.proc_end;
3890 ia64_cons_fix_new (frag_now, where + bytes_per_address,
3891 bytes_per_address, &e);
3895 e.X_op = O_pseudo_fixup;
3896 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3898 e.X_add_symbol = unwind.info;
3899 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2),
3900 bytes_per_address, &e);
3903 md_number_to_chars (ptr + (bytes_per_address * 2), 0,
3907 subseg_set (saved_seg, saved_subseg);
3908 unwind.proc_start = unwind.proc_end = unwind.info = 0;
3912 dot_template (template)
3915 CURR_SLOT.user_template = template;
3920 int dummy ATTRIBUTE_UNUSED;
3922 int ins, locs, outs, rots;
3924 if (is_it_end_of_statement ())
3925 ins = locs = outs = rots = 0;
3928 ins = get_absolute_expression ();
3929 if (*input_line_pointer++ != ',')
3931 locs = get_absolute_expression ();
3932 if (*input_line_pointer++ != ',')
3934 outs = get_absolute_expression ();
3935 if (*input_line_pointer++ != ',')
3937 rots = get_absolute_expression ();
3939 set_regstack (ins, locs, outs, rots);
3943 as_bad ("Comma expected");
3944 ignore_rest_of_line ();
3951 unsigned num_regs, num_alloced = 0;
3952 struct dynreg **drpp, *dr;
3953 int ch, base_reg = 0;
3959 case DYNREG_GR: base_reg = REG_GR + 32; break;
3960 case DYNREG_FR: base_reg = REG_FR + 32; break;
3961 case DYNREG_PR: base_reg = REG_P + 16; break;
3965 /* First, remove existing names from hash table. */
3966 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3968 hash_delete (md.dynreg_hash, dr->name);
3972 drpp = &md.dynreg[type];
3975 start = input_line_pointer;
3976 ch = get_symbol_end ();
3977 *input_line_pointer = ch;
3978 len = (input_line_pointer - start);
3981 if (*input_line_pointer != '[')
3983 as_bad ("Expected '['");
3986 ++input_line_pointer; /* skip '[' */
3988 num_regs = get_absolute_expression ();
3990 if (*input_line_pointer++ != ']')
3992 as_bad ("Expected ']'");
3997 num_alloced += num_regs;
4001 if (num_alloced > md.rot.num_regs)
4003 as_bad ("Used more than the declared %d rotating registers",
4009 if (num_alloced > 96)
4011 as_bad ("Used more than the available 96 rotating registers");
4016 if (num_alloced > 48)
4018 as_bad ("Used more than the available 48 rotating registers");
4027 name = obstack_alloc (¬es, len + 1);
4028 memcpy (name, start, len);
4033 *drpp = obstack_alloc (¬es, sizeof (*dr));
4034 memset (*drpp, 0, sizeof (*dr));
4039 dr->num_regs = num_regs;
4040 dr->base = base_reg;
4042 base_reg += num_regs;
4044 if (hash_insert (md.dynreg_hash, name, dr))
4046 as_bad ("Attempt to redefine register set `%s'", name);
4050 if (*input_line_pointer != ',')
4052 ++input_line_pointer; /* skip comma */
4055 demand_empty_rest_of_line ();
4059 ignore_rest_of_line ();
4063 dot_byteorder (byteorder)
4066 target_big_endian = byteorder;
4071 int dummy ATTRIBUTE_UNUSED;
4078 option = input_line_pointer;
4079 ch = get_symbol_end ();
4080 if (strcmp (option, "lsb") == 0)
4081 md.flags &= ~EF_IA_64_BE;
4082 else if (strcmp (option, "msb") == 0)
4083 md.flags |= EF_IA_64_BE;
4084 else if (strcmp (option, "abi32") == 0)
4085 md.flags &= ~EF_IA_64_ABI64;
4086 else if (strcmp (option, "abi64") == 0)
4087 md.flags |= EF_IA_64_ABI64;
4089 as_bad ("Unknown psr option `%s'", option);
4090 *input_line_pointer = ch;
4093 if (*input_line_pointer != ',')
4096 ++input_line_pointer;
4099 demand_empty_rest_of_line ();
4104 int dummy ATTRIBUTE_UNUSED;
4106 as_bad (".alias not implemented yet");
4111 int dummy ATTRIBUTE_UNUSED;
4113 new_logical_line (0, get_absolute_expression ());
4114 demand_empty_rest_of_line ();
4118 parse_section_name ()
4124 if (*input_line_pointer != '"')
4126 as_bad ("Missing section name");
4127 ignore_rest_of_line ();
4130 name = demand_copy_C_string (&len);
4133 ignore_rest_of_line ();
4137 if (*input_line_pointer != ',')
4139 as_bad ("Comma expected after section name");
4140 ignore_rest_of_line ();
4143 ++input_line_pointer; /* skip comma */
4151 char *name = parse_section_name ();
4155 md.keep_pending_output = 1;
4158 obj_elf_previous (0);
4159 md.keep_pending_output = 0;
4162 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4165 stmt_float_cons (kind)
4172 case 'd': size = 8; break;
4173 case 'x': size = 10; break;
4180 ia64_do_align (size);
4188 int saved_auto_align = md.auto_align;
4192 md.auto_align = saved_auto_align;
4196 dot_xfloat_cons (kind)
4199 char *name = parse_section_name ();
4203 md.keep_pending_output = 1;
4205 stmt_float_cons (kind);
4206 obj_elf_previous (0);
4207 md.keep_pending_output = 0;
4211 dot_xstringer (zero)
4214 char *name = parse_section_name ();
4218 md.keep_pending_output = 1;
4221 obj_elf_previous (0);
4222 md.keep_pending_output = 0;
4229 int saved_auto_align = md.auto_align;
4230 char *name = parse_section_name ();
4234 md.keep_pending_output = 1;
4238 md.auto_align = saved_auto_align;
4239 obj_elf_previous (0);
4240 md.keep_pending_output = 0;
4244 dot_xfloat_cons_ua (kind)
4247 int saved_auto_align = md.auto_align;
4248 char *name = parse_section_name ();
4252 md.keep_pending_output = 1;
4255 stmt_float_cons (kind);
4256 md.auto_align = saved_auto_align;
4257 obj_elf_previous (0);
4258 md.keep_pending_output = 0;
4261 /* .reg.val <regname>,value */
4265 int dummy ATTRIBUTE_UNUSED;
4270 if (reg.X_op != O_register)
4272 as_bad (_("Register name expected"));
4273 ignore_rest_of_line ();
4275 else if (*input_line_pointer++ != ',')
4277 as_bad (_("Comma expected"));
4278 ignore_rest_of_line ();
4282 valueT value = get_absolute_expression ();
4283 int regno = reg.X_add_number;
4284 if (regno < REG_GR || regno > REG_GR + 128)
4285 as_warn (_("Register value annotation ignored"));
4288 gr_values[regno - REG_GR].known = 1;
4289 gr_values[regno - REG_GR].value = value;
4290 gr_values[regno - REG_GR].path = md.path;
4293 demand_empty_rest_of_line ();
4296 /* select dv checking mode
4301 A stop is inserted when changing modes
4308 if (md.manual_bundling)
4309 as_warn (_("Directive invalid within a bundle"));
4311 if (type == 'E' || type == 'A')
4312 md.mode_explicitly_set = 0;
4314 md.mode_explicitly_set = 1;
4321 if (md.explicit_mode)
4322 insn_group_break (1, 0, 0);
4323 md.explicit_mode = 0;
4327 if (!md.explicit_mode)
4328 insn_group_break (1, 0, 0);
4329 md.explicit_mode = 1;
4333 if (md.explicit_mode != md.default_explicit_mode)
4334 insn_group_break (1, 0, 0);
4335 md.explicit_mode = md.default_explicit_mode;
4336 md.mode_explicitly_set = 0;
4347 for (regno = 0; regno < 64; regno++)
4349 if (mask & ((valueT) 1 << regno))
4351 fprintf (stderr, "%s p%d", comma, regno);
4358 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4359 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4360 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4361 .pred.safe_across_calls p1 [, p2 [,...]]
4370 int p1 = -1, p2 = -1;
4374 if (*input_line_pointer != '"')
4376 as_bad (_("Missing predicate relation type"));
4377 ignore_rest_of_line ();
4383 char *form = demand_copy_C_string (&len);
4384 if (strcmp (form, "mutex") == 0)
4386 else if (strcmp (form, "clear") == 0)
4388 else if (strcmp (form, "imply") == 0)
4392 as_bad (_("Unrecognized predicate relation type"));
4393 ignore_rest_of_line ();
4397 if (*input_line_pointer == ',')
4398 ++input_line_pointer;
4408 if (toupper (*input_line_pointer) != 'P'
4409 || (regno = atoi (++input_line_pointer)) < 0
4412 as_bad (_("Predicate register expected"));
4413 ignore_rest_of_line ();
4416 while (isdigit (*input_line_pointer))
4417 ++input_line_pointer;
4424 as_warn (_("Duplicate predicate register ignored"));
4427 /* See if it's a range. */
4428 if (*input_line_pointer == '-')
4431 ++input_line_pointer;
4433 if (toupper (*input_line_pointer) != 'P'
4434 || (regno = atoi (++input_line_pointer)) < 0
4437 as_bad (_("Predicate register expected"));
4438 ignore_rest_of_line ();
4441 while (isdigit (*input_line_pointer))
4442 ++input_line_pointer;
4446 as_bad (_("Bad register range"));
4447 ignore_rest_of_line ();
4458 if (*input_line_pointer != ',')
4460 ++input_line_pointer;
4469 clear_qp_mutex (mask);
4470 clear_qp_implies (mask, (valueT) 0);
4473 if (count != 2 || p1 == -1 || p2 == -1)
4474 as_bad (_("Predicate source and target required"));
4475 else if (p1 == 0 || p2 == 0)
4476 as_bad (_("Use of p0 is not valid in this context"));
4478 add_qp_imply (p1, p2);
4483 as_bad (_("At least two PR arguments expected"));
4488 as_bad (_("Use of p0 is not valid in this context"));
4491 add_qp_mutex (mask);
4494 /* note that we don't override any existing relations */
4497 as_bad (_("At least one PR argument expected"));
4502 fprintf (stderr, "Safe across calls: ");
4503 print_prmask (mask);
4504 fprintf (stderr, "\n");
4506 qp_safe_across_calls = mask;
4509 demand_empty_rest_of_line ();
4512 /* .entry label [, label [, ...]]
4513 Hint to DV code that the given labels are to be considered entry points.
4514 Otherwise, only global labels are considered entry points. */
4518 int dummy ATTRIBUTE_UNUSED;
4527 name = input_line_pointer;
4528 c = get_symbol_end ();
4529 symbolP = symbol_find_or_make (name);
4531 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4533 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4536 *input_line_pointer = c;
4538 c = *input_line_pointer;
4541 input_line_pointer++;
4543 if (*input_line_pointer == '\n')
4549 demand_empty_rest_of_line ();
4552 /* .mem.offset offset, base
4553 "base" is used to distinguish between offsets from a different base. */
4556 dot_mem_offset (dummy)
4557 int dummy ATTRIBUTE_UNUSED;
4559 md.mem_offset.hint = 1;
4560 md.mem_offset.offset = get_absolute_expression ();
4561 if (*input_line_pointer != ',')
4563 as_bad (_("Comma expected"));
4564 ignore_rest_of_line ();
4567 ++input_line_pointer;
4568 md.mem_offset.base = get_absolute_expression ();
4569 demand_empty_rest_of_line ();
4572 /* ia64-specific pseudo-ops: */
4573 const pseudo_typeS md_pseudo_table[] =
4575 { "radix", dot_radix, 0 },
4576 { "lcomm", s_lcomm_bytes, 1 },
4577 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4578 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4579 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4580 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4581 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4582 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4583 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4584 { "proc", dot_proc, 0 },
4585 { "body", dot_body, 0 },
4586 { "prologue", dot_prologue, 0 },
4587 { "endp", dot_endp, 0 },
4588 { "file", dwarf2_directive_file, 0 },
4589 { "loc", dwarf2_directive_loc, 0 },
4591 { "fframe", dot_fframe, 0 },
4592 { "vframe", dot_vframe, 0 },
4593 { "vframesp", dot_vframesp, 0 },
4594 { "vframepsp", dot_vframepsp, 0 },
4595 { "save", dot_save, 0 },
4596 { "restore", dot_restore, 0 },
4597 { "restorereg", dot_restorereg, 0 },
4598 { "restorereg.p", dot_restorereg_p, 0 },
4599 { "handlerdata", dot_handlerdata, 0 },
4600 { "unwentry", dot_unwentry, 0 },
4601 { "altrp", dot_altrp, 0 },
4602 { "savesp", dot_savemem, 0 },
4603 { "savepsp", dot_savemem, 1 },
4604 { "save.g", dot_saveg, 0 },
4605 { "save.f", dot_savef, 0 },
4606 { "save.b", dot_saveb, 0 },
4607 { "save.gf", dot_savegf, 0 },
4608 { "spill", dot_spill, 0 },
4609 { "spillreg", dot_spillreg, 0 },
4610 { "spillsp", dot_spillmem, 0 },
4611 { "spillpsp", dot_spillmem, 1 },
4612 { "spillreg.p", dot_spillreg_p, 0 },
4613 { "spillsp.p", dot_spillmem_p, 0 },
4614 { "spillpsp.p", dot_spillmem_p, 1 },
4615 { "label_state", dot_label_state, 0 },
4616 { "copy_state", dot_copy_state, 0 },
4617 { "unwabi", dot_unwabi, 0 },
4618 { "personality", dot_personality, 0 },
4620 { "estate", dot_estate, 0 },
4622 { "mii", dot_template, 0x0 },
4623 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4624 { "mlx", dot_template, 0x2 },
4625 { "mmi", dot_template, 0x4 },
4626 { "mfi", dot_template, 0x6 },
4627 { "mmf", dot_template, 0x7 },
4628 { "mib", dot_template, 0x8 },
4629 { "mbb", dot_template, 0x9 },
4630 { "bbb", dot_template, 0xb },
4631 { "mmb", dot_template, 0xc },
4632 { "mfb", dot_template, 0xe },
4634 { "lb", dot_scope, 0 },
4635 { "le", dot_scope, 1 },
4637 { "align", s_align_bytes, 0 },
4638 { "regstk", dot_regstk, 0 },
4639 { "rotr", dot_rot, DYNREG_GR },
4640 { "rotf", dot_rot, DYNREG_FR },
4641 { "rotp", dot_rot, DYNREG_PR },
4642 { "lsb", dot_byteorder, 0 },
4643 { "msb", dot_byteorder, 1 },
4644 { "psr", dot_psr, 0 },
4645 { "alias", dot_alias, 0 },
4646 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4648 { "xdata1", dot_xdata, 1 },
4649 { "xdata2", dot_xdata, 2 },
4650 { "xdata4", dot_xdata, 4 },
4651 { "xdata8", dot_xdata, 8 },
4652 { "xreal4", dot_xfloat_cons, 'f' },
4653 { "xreal8", dot_xfloat_cons, 'd' },
4654 { "xreal10", dot_xfloat_cons, 'x' },
4655 { "xstring", dot_xstringer, 0 },
4656 { "xstringz", dot_xstringer, 1 },
4658 /* unaligned versions: */
4659 { "xdata2.ua", dot_xdata_ua, 2 },
4660 { "xdata4.ua", dot_xdata_ua, 4 },
4661 { "xdata8.ua", dot_xdata_ua, 8 },
4662 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4663 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4664 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4666 /* annotations/DV checking support */
4667 { "entry", dot_entry, 0 },
4668 { "mem.offset", dot_mem_offset, 0 },
4669 { "pred.rel", dot_pred_rel, 0 },
4670 { "pred.rel.clear", dot_pred_rel, 'c' },
4671 { "pred.rel.imply", dot_pred_rel, 'i' },
4672 { "pred.rel.mutex", dot_pred_rel, 'm' },
4673 { "pred.safe_across_calls", dot_pred_rel, 's' },
4674 { "reg.val", dot_reg_val, 0 },
4675 { "auto", dot_dv_mode, 'a' },
4676 { "explicit", dot_dv_mode, 'e' },
4677 { "default", dot_dv_mode, 'd' },
4682 static const struct pseudo_opcode
4685 void (*handler) (int);
4690 /* these are more like pseudo-ops, but don't start with a dot */
4691 { "data1", cons, 1 },
4692 { "data2", cons, 2 },
4693 { "data4", cons, 4 },
4694 { "data8", cons, 8 },
4695 { "real4", stmt_float_cons, 'f' },
4696 { "real8", stmt_float_cons, 'd' },
4697 { "real10", stmt_float_cons, 'x' },
4698 { "string", stringer, 0 },
4699 { "stringz", stringer, 1 },
4701 /* unaligned versions: */
4702 { "data2.ua", stmt_cons_ua, 2 },
4703 { "data4.ua", stmt_cons_ua, 4 },
4704 { "data8.ua", stmt_cons_ua, 8 },
4705 { "real4.ua", float_cons, 'f' },
4706 { "real8.ua", float_cons, 'd' },
4707 { "real10.ua", float_cons, 'x' },
4710 /* Declare a register by creating a symbol for it and entering it in
4711 the symbol table. */
4714 declare_register (name, regnum)
4721 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4723 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4725 as_fatal ("Inserting \"%s\" into register table failed: %s",
4732 declare_register_set (prefix, num_regs, base_regnum)
4740 for (i = 0; i < num_regs; ++i)
4742 sprintf (name, "%s%u", prefix, i);
4743 declare_register (name, base_regnum + i);
4748 operand_width (opnd)
4749 enum ia64_opnd opnd;
4751 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4752 unsigned int bits = 0;
4756 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4757 bits += odesc->field[i].bits;
4762 static enum operand_match_result
4763 operand_match (idesc, index, e)
4764 const struct ia64_opcode *idesc;
4768 enum ia64_opnd opnd = idesc->operands[index];
4769 int bits, relocatable = 0;
4770 struct insn_fix *fix;
4777 case IA64_OPND_AR_CCV:
4778 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4779 return OPERAND_MATCH;
4782 case IA64_OPND_AR_PFS:
4783 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4784 return OPERAND_MATCH;
4788 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4789 return OPERAND_MATCH;
4793 if (e->X_op == O_register && e->X_add_number == REG_IP)
4794 return OPERAND_MATCH;
4798 if (e->X_op == O_register && e->X_add_number == REG_PR)
4799 return OPERAND_MATCH;
4802 case IA64_OPND_PR_ROT:
4803 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4804 return OPERAND_MATCH;
4808 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4809 return OPERAND_MATCH;
4812 case IA64_OPND_PSR_L:
4813 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4814 return OPERAND_MATCH;
4817 case IA64_OPND_PSR_UM:
4818 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4819 return OPERAND_MATCH;
4823 if (e->X_op == O_constant)
4825 if (e->X_add_number == 1)
4826 return OPERAND_MATCH;
4828 return OPERAND_OUT_OF_RANGE;
4833 if (e->X_op == O_constant)
4835 if (e->X_add_number == 8)
4836 return OPERAND_MATCH;
4838 return OPERAND_OUT_OF_RANGE;
4843 if (e->X_op == O_constant)
4845 if (e->X_add_number == 16)
4846 return OPERAND_MATCH;
4848 return OPERAND_OUT_OF_RANGE;
4852 /* register operands: */
4855 if (e->X_op == O_register && e->X_add_number >= REG_AR
4856 && e->X_add_number < REG_AR + 128)
4857 return OPERAND_MATCH;
4862 if (e->X_op == O_register && e->X_add_number >= REG_BR
4863 && e->X_add_number < REG_BR + 8)
4864 return OPERAND_MATCH;
4868 if (e->X_op == O_register && e->X_add_number >= REG_CR
4869 && e->X_add_number < REG_CR + 128)
4870 return OPERAND_MATCH;
4877 if (e->X_op == O_register && e->X_add_number >= REG_FR
4878 && e->X_add_number < REG_FR + 128)
4879 return OPERAND_MATCH;
4884 if (e->X_op == O_register && e->X_add_number >= REG_P
4885 && e->X_add_number < REG_P + 64)
4886 return OPERAND_MATCH;
4892 if (e->X_op == O_register && e->X_add_number >= REG_GR
4893 && e->X_add_number < REG_GR + 128)
4894 return OPERAND_MATCH;
4897 case IA64_OPND_R3_2:
4898 if (e->X_op == O_register && e->X_add_number >= REG_GR)
4900 if (e->X_add_number < REG_GR + 4)
4901 return OPERAND_MATCH;
4902 else if (e->X_add_number < REG_GR + 128)
4903 return OPERAND_OUT_OF_RANGE;
4907 /* indirect operands: */
4908 case IA64_OPND_CPUID_R3:
4909 case IA64_OPND_DBR_R3:
4910 case IA64_OPND_DTR_R3:
4911 case IA64_OPND_ITR_R3:
4912 case IA64_OPND_IBR_R3:
4913 case IA64_OPND_MSR_R3:
4914 case IA64_OPND_PKR_R3:
4915 case IA64_OPND_PMC_R3:
4916 case IA64_OPND_PMD_R3:
4917 case IA64_OPND_RR_R3:
4918 if (e->X_op == O_index && e->X_op_symbol
4919 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4920 == opnd - IA64_OPND_CPUID_R3))
4921 return OPERAND_MATCH;
4925 if (e->X_op == O_index && !e->X_op_symbol)
4926 return OPERAND_MATCH;
4929 /* immediate operands: */
4930 case IA64_OPND_CNT2a:
4931 case IA64_OPND_LEN4:
4932 case IA64_OPND_LEN6:
4933 bits = operand_width (idesc->operands[index]);
4934 if (e->X_op == O_constant)
4936 if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4937 return OPERAND_MATCH;
4939 return OPERAND_OUT_OF_RANGE;
4943 case IA64_OPND_CNT2b:
4944 if (e->X_op == O_constant)
4946 if ((bfd_vma) (e->X_add_number - 1) < 3)
4947 return OPERAND_MATCH;
4949 return OPERAND_OUT_OF_RANGE;
4953 case IA64_OPND_CNT2c:
4954 val = e->X_add_number;
4955 if (e->X_op == O_constant)
4957 if ((val == 0 || val == 7 || val == 15 || val == 16))
4958 return OPERAND_MATCH;
4960 return OPERAND_OUT_OF_RANGE;
4965 /* SOR must be an integer multiple of 8 */
4966 if (e->X_op == O_constant && e->X_add_number & 0x7)
4967 return OPERAND_OUT_OF_RANGE;
4970 if (e->X_op == O_constant)
4972 if ((bfd_vma) e->X_add_number <= 96)
4973 return OPERAND_MATCH;
4975 return OPERAND_OUT_OF_RANGE;
4979 case IA64_OPND_IMMU62:
4980 if (e->X_op == O_constant)
4982 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
4983 return OPERAND_MATCH;
4985 return OPERAND_OUT_OF_RANGE;
4989 /* FIXME -- need 62-bit relocation type */
4990 as_bad (_("62-bit relocation not yet implemented"));
4994 case IA64_OPND_IMMU64:
4995 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
4996 || e->X_op == O_subtract)
4998 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4999 fix->code = BFD_RELOC_IA64_IMM64;
5000 if (e->X_op != O_subtract)
5002 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5003 if (e->X_op == O_pseudo_fixup)
5007 fix->opnd = idesc->operands[index];
5010 ++CURR_SLOT.num_fixups;
5011 return OPERAND_MATCH;
5013 else if (e->X_op == O_constant)
5014 return OPERAND_MATCH;
5017 case IA64_OPND_CCNT5:
5018 case IA64_OPND_CNT5:
5019 case IA64_OPND_CNT6:
5020 case IA64_OPND_CPOS6a:
5021 case IA64_OPND_CPOS6b:
5022 case IA64_OPND_CPOS6c:
5023 case IA64_OPND_IMMU2:
5024 case IA64_OPND_IMMU7a:
5025 case IA64_OPND_IMMU7b:
5026 case IA64_OPND_IMMU21:
5027 case IA64_OPND_IMMU24:
5028 case IA64_OPND_MBTYPE4:
5029 case IA64_OPND_MHTYPE8:
5030 case IA64_OPND_POS6:
5031 bits = operand_width (idesc->operands[index]);
5032 if (e->X_op == O_constant)
5034 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5035 return OPERAND_MATCH;
5037 return OPERAND_OUT_OF_RANGE;
5041 case IA64_OPND_IMMU9:
5042 bits = operand_width (idesc->operands[index]);
5043 if (e->X_op == O_constant)
5045 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
5047 int lobits = e->X_add_number & 0x3;
5048 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
5049 e->X_add_number |= (bfd_vma) 0x3;
5050 return OPERAND_MATCH;
5053 return OPERAND_OUT_OF_RANGE;
5057 case IA64_OPND_IMM44:
5058 /* least 16 bits must be zero */
5059 if ((e->X_add_number & 0xffff) != 0)
5060 /* XXX technically, this is wrong: we should not be issuing warning
5061 messages until we're sure this instruction pattern is going to
5063 as_warn (_("lower 16 bits of mask ignored"));
5065 if (e->X_op == O_constant)
5067 if (((e->X_add_number >= 0
5068 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44))
5069 || (e->X_add_number < 0
5070 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44))))
5073 if (e->X_add_number >= 0
5074 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
5076 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
5078 return OPERAND_MATCH;
5081 return OPERAND_OUT_OF_RANGE;
5085 case IA64_OPND_IMM17:
5086 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5087 if (e->X_op == O_constant)
5089 if (((e->X_add_number >= 0
5090 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17))
5091 || (e->X_add_number < 0
5092 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17))))
5095 if (e->X_add_number >= 0
5096 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
5098 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
5100 return OPERAND_MATCH;
5103 return OPERAND_OUT_OF_RANGE;
5107 case IA64_OPND_IMM14:
5108 case IA64_OPND_IMM22:
5110 case IA64_OPND_IMM1:
5111 case IA64_OPND_IMM8:
5112 case IA64_OPND_IMM8U4:
5113 case IA64_OPND_IMM8M1:
5114 case IA64_OPND_IMM8M1U4:
5115 case IA64_OPND_IMM8M1U8:
5116 case IA64_OPND_IMM9a:
5117 case IA64_OPND_IMM9b:
5118 bits = operand_width (idesc->operands[index]);
5119 if (relocatable && (e->X_op == O_symbol
5120 || e->X_op == O_subtract
5121 || e->X_op == O_pseudo_fixup))
5123 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5125 if (idesc->operands[index] == IA64_OPND_IMM14)
5126 fix->code = BFD_RELOC_IA64_IMM14;
5128 fix->code = BFD_RELOC_IA64_IMM22;
5130 if (e->X_op != O_subtract)
5132 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5133 if (e->X_op == O_pseudo_fixup)
5137 fix->opnd = idesc->operands[index];
5140 ++CURR_SLOT.num_fixups;
5141 return OPERAND_MATCH;
5143 else if (e->X_op != O_constant
5144 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
5145 return OPERAND_MISMATCH;
5147 if (opnd == IA64_OPND_IMM8M1U4)
5149 /* Zero is not valid for unsigned compares that take an adjusted
5150 constant immediate range. */
5151 if (e->X_add_number == 0)
5152 return OPERAND_OUT_OF_RANGE;
5154 /* Sign-extend 32-bit unsigned numbers, so that the following range
5155 checks will work. */
5156 val = e->X_add_number;
5157 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5158 && ((val & ((bfd_vma) 1 << 31)) != 0))
5159 val = ((val << 32) >> 32);
5161 /* Check for 0x100000000. This is valid because
5162 0x100000000-1 is the same as ((uint32_t) -1). */
5163 if (val == ((bfd_signed_vma) 1 << 32))
5164 return OPERAND_MATCH;
5168 else if (opnd == IA64_OPND_IMM8M1U8)
5170 /* Zero is not valid for unsigned compares that take an adjusted
5171 constant immediate range. */
5172 if (e->X_add_number == 0)
5173 return OPERAND_OUT_OF_RANGE;
5175 /* Check for 0x10000000000000000. */
5176 if (e->X_op == O_big)
5178 if (generic_bignum[0] == 0
5179 && generic_bignum[1] == 0
5180 && generic_bignum[2] == 0
5181 && generic_bignum[3] == 0
5182 && generic_bignum[4] == 1)
5183 return OPERAND_MATCH;
5185 return OPERAND_OUT_OF_RANGE;
5188 val = e->X_add_number - 1;
5190 else if (opnd == IA64_OPND_IMM8M1)
5191 val = e->X_add_number - 1;
5192 else if (opnd == IA64_OPND_IMM8U4)
5194 /* Sign-extend 32-bit unsigned numbers, so that the following range
5195 checks will work. */
5196 val = e->X_add_number;
5197 if (((val & (~(bfd_vma) 0 << 32)) == 0)
5198 && ((val & ((bfd_vma) 1 << 31)) != 0))
5199 val = ((val << 32) >> 32);
5202 val = e->X_add_number;
5204 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1)))
5205 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1))))
5206 return OPERAND_MATCH;
5208 return OPERAND_OUT_OF_RANGE;
5210 case IA64_OPND_INC3:
5211 /* +/- 1, 4, 8, 16 */
5212 val = e->X_add_number;
5215 if (e->X_op == O_constant)
5217 if ((val == 1 || val == 4 || val == 8 || val == 16))
5218 return OPERAND_MATCH;
5220 return OPERAND_OUT_OF_RANGE;
5224 case IA64_OPND_TGT25:
5225 case IA64_OPND_TGT25b:
5226 case IA64_OPND_TGT25c:
5227 case IA64_OPND_TGT64:
5228 if (e->X_op == O_symbol)
5230 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5231 if (opnd == IA64_OPND_TGT25)
5232 fix->code = BFD_RELOC_IA64_PCREL21F;
5233 else if (opnd == IA64_OPND_TGT25b)
5234 fix->code = BFD_RELOC_IA64_PCREL21M;
5235 else if (opnd == IA64_OPND_TGT25c)
5236 fix->code = BFD_RELOC_IA64_PCREL21B;
5237 else if (opnd == IA64_OPND_TGT64)
5238 fix->code = BFD_RELOC_IA64_PCREL60B;
5242 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5243 fix->opnd = idesc->operands[index];
5246 ++CURR_SLOT.num_fixups;
5247 return OPERAND_MATCH;
5249 case IA64_OPND_TAG13:
5250 case IA64_OPND_TAG13b:
5254 return OPERAND_MATCH;
5257 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
5258 /* There are no external relocs for TAG13/TAG13b fields, so we
5259 create a dummy reloc. This will not live past md_apply_fix3. */
5260 fix->code = BFD_RELOC_UNUSED;
5261 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
5262 fix->opnd = idesc->operands[index];
5265 ++CURR_SLOT.num_fixups;
5266 return OPERAND_MATCH;
5276 return OPERAND_MISMATCH;
5285 memset (e, 0, sizeof (*e));
5288 if (*input_line_pointer != '}')
5290 sep = *input_line_pointer++;
5294 if (!md.manual_bundling)
5295 as_warn ("Found '}' when manual bundling is off");
5297 CURR_SLOT.manual_bundling_off = 1;
5298 md.manual_bundling = 0;
5304 /* Returns the next entry in the opcode table that matches the one in
5305 IDESC, and frees the entry in IDESC. If no matching entry is
5306 found, NULL is returned instead. */
5308 static struct ia64_opcode *
5309 get_next_opcode (struct ia64_opcode *idesc)
5311 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
5312 ia64_free_opcode (idesc);
5316 /* Parse the operands for the opcode and find the opcode variant that
5317 matches the specified operands, or NULL if no match is possible. */
5319 static struct ia64_opcode *
5320 parse_operands (idesc)
5321 struct ia64_opcode *idesc;
5323 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
5324 int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0;
5325 enum ia64_opnd expected_operand = IA64_OPND_NIL;
5326 enum operand_match_result result;
5328 char *first_arg = 0, *end, *saved_input_pointer;
5331 assert (strlen (idesc->name) <= 128);
5333 strcpy (mnemonic, idesc->name);
5334 if (idesc->operands[2] == IA64_OPND_SOF)
5336 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5337 can't parse the first operand until we have parsed the
5338 remaining operands of the "alloc" instruction. */
5340 first_arg = input_line_pointer;
5341 end = strchr (input_line_pointer, '=');
5344 as_bad ("Expected separator `='");
5347 input_line_pointer = end + 1;
5352 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
5354 sep = parse_operand (CURR_SLOT.opnd + i);
5355 if (CURR_SLOT.opnd[i].X_op == O_absent)
5360 if (sep != '=' && sep != ',')
5365 if (num_outputs > 0)
5366 as_bad ("Duplicate equal sign (=) in instruction");
5368 num_outputs = i + 1;
5373 as_bad ("Illegal operand separator `%c'", sep);
5377 if (idesc->operands[2] == IA64_OPND_SOF)
5379 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5380 know (strcmp (idesc->name, "alloc") == 0);
5381 if (num_operands == 5 /* first_arg not included in this count! */
5382 && CURR_SLOT.opnd[2].X_op == O_constant
5383 && CURR_SLOT.opnd[3].X_op == O_constant
5384 && CURR_SLOT.opnd[4].X_op == O_constant
5385 && CURR_SLOT.opnd[5].X_op == O_constant)
5387 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5388 CURR_SLOT.opnd[3].X_add_number,
5389 CURR_SLOT.opnd[4].X_add_number,
5390 CURR_SLOT.opnd[5].X_add_number);
5392 /* now we can parse the first arg: */
5393 saved_input_pointer = input_line_pointer;
5394 input_line_pointer = first_arg;
5395 sep = parse_operand (CURR_SLOT.opnd + 0);
5397 --num_outputs; /* force error */
5398 input_line_pointer = saved_input_pointer;
5400 CURR_SLOT.opnd[2].X_add_number = sof;
5401 CURR_SLOT.opnd[3].X_add_number
5402 = sof - CURR_SLOT.opnd[4].X_add_number;
5403 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5407 highest_unmatched_operand = 0;
5408 curr_out_of_range_pos = -1;
5410 expected_operand = idesc->operands[0];
5411 for (; idesc; idesc = get_next_opcode (idesc))
5413 if (num_outputs != idesc->num_outputs)
5414 continue; /* mismatch in # of outputs */
5416 CURR_SLOT.num_fixups = 0;
5418 /* Try to match all operands. If we see an out-of-range operand,
5419 then continue trying to match the rest of the operands, since if
5420 the rest match, then this idesc will give the best error message. */
5422 out_of_range_pos = -1;
5423 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5425 result = operand_match (idesc, i, CURR_SLOT.opnd + i);
5426 if (result != OPERAND_MATCH)
5428 if (result != OPERAND_OUT_OF_RANGE)
5430 if (out_of_range_pos < 0)
5431 /* remember position of the first out-of-range operand: */
5432 out_of_range_pos = i;
5436 /* If we did not match all operands, or if at least one operand was
5437 out-of-range, then this idesc does not match. Keep track of which
5438 idesc matched the most operands before failing. If we have two
5439 idescs that failed at the same position, and one had an out-of-range
5440 operand, then prefer the out-of-range operand. Thus if we have
5441 "add r0=0x1000000,r1" we get an error saying the constant is out
5442 of range instead of an error saying that the constant should have been
5445 if (i != num_operands || out_of_range_pos >= 0)
5447 if (i > highest_unmatched_operand
5448 || (i == highest_unmatched_operand
5449 && out_of_range_pos > curr_out_of_range_pos))
5451 highest_unmatched_operand = i;
5452 if (out_of_range_pos >= 0)
5454 expected_operand = idesc->operands[out_of_range_pos];
5455 error_pos = out_of_range_pos;
5459 expected_operand = idesc->operands[i];
5462 curr_out_of_range_pos = out_of_range_pos;
5467 if (num_operands < NELEMS (idesc->operands)
5468 && idesc->operands[num_operands])
5469 continue; /* mismatch in number of arguments */
5475 if (expected_operand)
5476 as_bad ("Operand %u of `%s' should be %s",
5477 error_pos + 1, mnemonic,
5478 elf64_ia64_operands[expected_operand].desc);
5480 as_bad ("Operand mismatch");
5486 /* Keep track of state necessary to determine whether a NOP is necessary
5487 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5488 detect a case where additional NOPs may be necessary. */
5490 errata_nop_necessary_p (slot, insn_unit)
5492 enum ia64_unit insn_unit;
5495 struct group *this_group = md.last_groups + md.group_idx;
5496 struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3;
5497 struct ia64_opcode *idesc = slot->idesc;
5499 /* Test whether this could be the first insn in a problematic sequence. */
5500 if (insn_unit == IA64_UNIT_F)
5502 for (i = 0; i < idesc->num_outputs; i++)
5503 if (idesc->operands[i] == IA64_OPND_P1
5504 || idesc->operands[i] == IA64_OPND_P2)
5506 int regno = slot->opnd[i].X_add_number - REG_P;
5507 /* Ignore invalid operands; they generate errors elsewhere. */
5510 this_group->p_reg_set[regno] = 1;
5514 /* Test whether this could be the second insn in a problematic sequence. */
5515 if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0
5516 && prev_group->p_reg_set[slot->qp_regno])
5518 for (i = 0; i < idesc->num_outputs; i++)
5519 if (idesc->operands[i] == IA64_OPND_R1
5520 || idesc->operands[i] == IA64_OPND_R2
5521 || idesc->operands[i] == IA64_OPND_R3)
5523 int regno = slot->opnd[i].X_add_number - REG_GR;
5524 /* Ignore invalid operands; they generate errors elsewhere. */
5527 if (strncmp (idesc->name, "add", 3) != 0
5528 && strncmp (idesc->name, "sub", 3) != 0
5529 && strncmp (idesc->name, "shladd", 6) != 0
5530 && (idesc->flags & IA64_OPCODE_POSTINC) == 0)
5531 this_group->g_reg_set_conditionally[regno] = 1;
5535 /* Test whether this could be the third insn in a problematic sequence. */
5536 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++)
5538 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5539 idesc->operands[i] == IA64_OPND_R3
5540 /* For mov indirect. */
5541 || idesc->operands[i] == IA64_OPND_RR_R3
5542 || idesc->operands[i] == IA64_OPND_DBR_R3
5543 || idesc->operands[i] == IA64_OPND_IBR_R3
5544 || idesc->operands[i] == IA64_OPND_PKR_R3
5545 || idesc->operands[i] == IA64_OPND_PMC_R3
5546 || idesc->operands[i] == IA64_OPND_PMD_R3
5547 || idesc->operands[i] == IA64_OPND_MSR_R3
5548 || idesc->operands[i] == IA64_OPND_CPUID_R3
5550 || idesc->operands[i] == IA64_OPND_ITR_R3
5551 || idesc->operands[i] == IA64_OPND_DTR_R3
5552 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5553 || idesc->operands[i] == IA64_OPND_MR3)
5555 int regno = slot->opnd[i].X_add_number - REG_GR;
5556 /* Ignore invalid operands; they generate errors elsewhere. */
5559 if (idesc->operands[i] == IA64_OPND_R3)
5561 if (strcmp (idesc->name, "fc") != 0
5562 && strcmp (idesc->name, "tak") != 0
5563 && strcmp (idesc->name, "thash") != 0
5564 && strcmp (idesc->name, "tpa") != 0
5565 && strcmp (idesc->name, "ttag") != 0
5566 && strncmp (idesc->name, "ptr", 3) != 0
5567 && strncmp (idesc->name, "ptc", 3) != 0
5568 && strncmp (idesc->name, "probe", 5) != 0)
5571 if (prev_group->g_reg_set_conditionally[regno])
5579 build_insn (slot, insnp)
5583 const struct ia64_operand *odesc, *o2desc;
5584 struct ia64_opcode *idesc = slot->idesc;
5585 bfd_signed_vma insn, val;
5589 insn = idesc->opcode | slot->qp_regno;
5591 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5593 if (slot->opnd[i].X_op == O_register
5594 || slot->opnd[i].X_op == O_constant
5595 || slot->opnd[i].X_op == O_index)
5596 val = slot->opnd[i].X_add_number;
5597 else if (slot->opnd[i].X_op == O_big)
5599 /* This must be the value 0x10000000000000000. */
5600 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5606 switch (idesc->operands[i])
5608 case IA64_OPND_IMMU64:
5609 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5610 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5611 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5612 | (((val >> 63) & 0x1) << 36));
5615 case IA64_OPND_IMMU62:
5616 val &= 0x3fffffffffffffffULL;
5617 if (val != slot->opnd[i].X_add_number)
5618 as_warn (_("Value truncated to 62 bits"));
5619 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5620 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
5623 case IA64_OPND_TGT64:
5625 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5626 insn |= ((((val >> 59) & 0x1) << 36)
5627 | (((val >> 0) & 0xfffff) << 13));
5658 case IA64_OPND_R3_2:
5659 case IA64_OPND_CPUID_R3:
5660 case IA64_OPND_DBR_R3:
5661 case IA64_OPND_DTR_R3:
5662 case IA64_OPND_ITR_R3:
5663 case IA64_OPND_IBR_R3:
5665 case IA64_OPND_MSR_R3:
5666 case IA64_OPND_PKR_R3:
5667 case IA64_OPND_PMC_R3:
5668 case IA64_OPND_PMD_R3:
5669 case IA64_OPND_RR_R3:
5677 odesc = elf64_ia64_operands + idesc->operands[i];
5678 err = (*odesc->insert) (odesc, val, &insn);
5680 as_bad_where (slot->src_file, slot->src_line,
5681 "Bad operand value: %s", err);
5682 if (idesc->flags & IA64_OPCODE_PSEUDO)
5684 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5685 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5687 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5688 (*o2desc->insert) (o2desc, val, &insn);
5690 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5691 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5692 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
5694 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5695 (*o2desc->insert) (o2desc, 64 - val, &insn);
5705 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5706 unsigned int manual_bundling = 0;
5707 enum ia64_unit required_unit, insn_unit = 0;
5708 enum ia64_insn_type type[3], insn_type;
5709 unsigned int template, orig_template;
5710 bfd_vma insn[3] = { -1, -1, -1 };
5711 struct ia64_opcode *idesc;
5712 int end_of_insn_group = 0, user_template = -1;
5713 int n, i, j, first, curr;
5715 bfd_vma t0 = 0, t1 = 0;
5716 struct label_fix *lfix;
5717 struct insn_fix *ifix;
5722 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5723 know (first >= 0 & first < NUM_SLOTS);
5724 n = MIN (3, md.num_slots_in_use);
5726 /* Determine template: user user_template if specified, best match
5729 if (md.slot[first].user_template >= 0)
5730 user_template = template = md.slot[first].user_template;
5733 /* Auto select appropriate template. */
5734 memset (type, 0, sizeof (type));
5736 for (i = 0; i < n; ++i)
5738 if (md.slot[curr].label_fixups && i != 0)
5740 type[i] = md.slot[curr].idesc->type;
5741 curr = (curr + 1) % NUM_SLOTS;
5743 template = best_template[type[0]][type[1]][type[2]];
5746 /* initialize instructions with appropriate nops: */
5747 for (i = 0; i < 3; ++i)
5748 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5752 /* now fill in slots with as many insns as possible: */
5754 idesc = md.slot[curr].idesc;
5755 end_of_insn_group = 0;
5756 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5758 /* Set the slot number for prologue/body records now as those
5759 refer to the current point, not the point after the
5760 instruction has been issued: */
5761 /* Don't try to delete prologue/body records here, as that will cause
5762 them to also be deleted from the master list of unwind records. */
5763 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5764 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5765 || ptr->r.type == body)
5767 ptr->slot_number = (unsigned long) f + i;
5768 ptr->slot_frag = frag_now;
5771 if (idesc->flags & IA64_OPCODE_SLOT2)
5773 if (manual_bundling && i != 2)
5774 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5775 "`%s' must be last in bundle", idesc->name);
5779 if (idesc->flags & IA64_OPCODE_LAST)
5782 unsigned int required_template;
5784 /* If we need a stop bit after an M slot, our only choice is
5785 template 5 (M;;MI). If we need a stop bit after a B
5786 slot, our only choice is to place it at the end of the
5787 bundle, because the only available templates are MIB,
5788 MBB, BBB, MMB, and MFB. We don't handle anything other
5789 than M and B slots because these are the only kind of
5790 instructions that can have the IA64_OPCODE_LAST bit set. */
5791 required_template = template;
5792 switch (idesc->type)
5796 required_template = 5;
5804 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5805 "Internal error: don't know how to force %s to end"
5806 "of instruction group", idesc->name);
5810 if (manual_bundling && i != required_slot)
5811 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5812 "`%s' must be last in instruction group",
5814 if (required_slot < i)
5815 /* Can't fit this instruction. */
5819 if (required_template != template)
5821 /* If we switch the template, we need to reset the NOPs
5822 after slot i. The slot-types of the instructions ahead
5823 of i never change, so we don't need to worry about
5824 changing NOPs in front of this slot. */
5825 for (j = i; j < 3; ++j)
5826 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5828 template = required_template;
5830 if (curr != first && md.slot[curr].label_fixups)
5832 if (manual_bundling_on)
5833 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5834 "Label must be first in a bundle");
5835 /* This insn must go into the first slot of a bundle. */
5839 manual_bundling_on = md.slot[curr].manual_bundling_on;
5840 manual_bundling_off = md.slot[curr].manual_bundling_off;
5842 if (manual_bundling_on)
5845 manual_bundling = 1;
5847 break; /* need to start a new bundle */
5850 if (end_of_insn_group && md.num_slots_in_use >= 1)
5852 /* We need an instruction group boundary in the middle of a
5853 bundle. See if we can switch to an other template with
5854 an appropriate boundary. */
5856 orig_template = template;
5857 if (i == 1 && (user_template == 4
5858 || (user_template < 0
5859 && (ia64_templ_desc[template].exec_unit[0]
5863 end_of_insn_group = 0;
5865 else if (i == 2 && (user_template == 0
5866 || (user_template < 0
5867 && (ia64_templ_desc[template].exec_unit[1]
5869 /* This test makes sure we don't switch the template if
5870 the next instruction is one that needs to be first in
5871 an instruction group. Since all those instructions are
5872 in the M group, there is no way such an instruction can
5873 fit in this bundle even if we switch the template. The
5874 reason we have to check for this is that otherwise we
5875 may end up generating "MI;;I M.." which has the deadly
5876 effect that the second M instruction is no longer the
5877 first in the bundle! --davidm 99/12/16 */
5878 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5881 end_of_insn_group = 0;
5883 else if (curr != first)
5884 /* can't fit this insn */
5887 if (template != orig_template)
5888 /* if we switch the template, we need to reset the NOPs
5889 after slot i. The slot-types of the instructions ahead
5890 of i never change, so we don't need to worry about
5891 changing NOPs in front of this slot. */
5892 for (j = i; j < 3; ++j)
5893 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5895 required_unit = ia64_templ_desc[template].exec_unit[i];
5897 /* resolve dynamic opcodes such as "break" and "nop": */
5898 if (idesc->type == IA64_TYPE_DYN)
5900 if ((strcmp (idesc->name, "nop") == 0)
5901 || (strcmp (idesc->name, "break") == 0))
5902 insn_unit = required_unit;
5903 else if (strcmp (idesc->name, "chk.s") == 0)
5905 insn_unit = IA64_UNIT_M;
5906 if (required_unit == IA64_UNIT_I)
5907 insn_unit = IA64_UNIT_I;
5910 as_fatal ("emit_one_bundle: unexpected dynamic op");
5912 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
5913 ia64_free_opcode (idesc);
5914 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5916 know (!idesc->next); /* no resolved dynamic ops have collisions */
5921 insn_type = idesc->type;
5922 insn_unit = IA64_UNIT_NIL;
5926 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5927 insn_unit = required_unit;
5929 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
5930 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5931 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5932 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5933 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5938 if (insn_unit != required_unit)
5940 if (required_unit == IA64_UNIT_L
5941 && insn_unit == IA64_UNIT_I
5942 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5944 /* we got ourselves an MLX template but the current
5945 instruction isn't an X-unit, or an I-unit instruction
5946 that can go into the X slot of an MLX template. Duh. */
5947 if (md.num_slots_in_use >= NUM_SLOTS)
5949 as_bad_where (md.slot[curr].src_file,
5950 md.slot[curr].src_line,
5951 "`%s' can't go in X slot of "
5952 "MLX template", idesc->name);
5953 /* drop this insn so we don't livelock: */
5954 --md.num_slots_in_use;
5958 continue; /* try next slot */
5964 addr = frag_now->fr_address + frag_now_fix () - 16 + i;
5965 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5968 if (errata_nop_necessary_p (md.slot + curr, insn_unit))
5969 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
5971 build_insn (md.slot + curr, insn + i);
5973 /* Set slot counts for non prologue/body unwind records. */
5974 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5975 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
5976 && ptr->r.type != body)
5978 ptr->slot_number = (unsigned long) f + i;
5979 ptr->slot_frag = frag_now;
5981 md.slot[curr].unwind_record = NULL;
5983 if (required_unit == IA64_UNIT_L)
5986 /* skip one slot for long/X-unit instructions */
5989 --md.num_slots_in_use;
5991 /* now is a good time to fix up the labels for this insn: */
5992 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
5994 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
5995 symbol_set_frag (lfix->sym, frag_now);
5997 /* and fix up the tags also. */
5998 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
6000 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
6001 symbol_set_frag (lfix->sym, frag_now);
6004 for (j = 0; j < md.slot[curr].num_fixups; ++j)
6006 ifix = md.slot[curr].fixup + j;
6007 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8,
6008 &ifix->expr, ifix->is_pcrel, ifix->code);
6009 fix->tc_fix_data.opnd = ifix->opnd;
6010 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
6011 fix->fx_file = md.slot[curr].src_file;
6012 fix->fx_line = md.slot[curr].src_line;
6015 end_of_insn_group = md.slot[curr].end_of_insn_group;
6017 if (end_of_insn_group)
6019 md.group_idx = (md.group_idx + 1) % 3;
6020 memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]);
6024 ia64_free_opcode (md.slot[curr].idesc);
6025 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
6026 md.slot[curr].user_template = -1;
6028 if (manual_bundling_off)
6030 manual_bundling = 0;
6033 curr = (curr + 1) % NUM_SLOTS;
6034 idesc = md.slot[curr].idesc;
6036 if (manual_bundling)
6038 if (md.num_slots_in_use > 0)
6039 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6040 "`%s' does not fit into %s template",
6041 idesc->name, ia64_templ_desc[template].name);
6043 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
6044 "Missing '}' at end of file");
6046 know (md.num_slots_in_use < NUM_SLOTS);
6048 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
6049 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
6051 number_to_chars_littleendian (f + 0, t0, 8);
6052 number_to_chars_littleendian (f + 8, t1, 8);
6054 unwind.next_slot_number = (unsigned long) f + 16;
6055 unwind.next_slot_frag = frag_now;
6059 md_parse_option (c, arg)
6066 /* Switches from the Intel assembler. */
6068 if (strcmp (arg, "ilp64") == 0
6069 || strcmp (arg, "lp64") == 0
6070 || strcmp (arg, "p64") == 0)
6072 md.flags |= EF_IA_64_ABI64;
6074 else if (strcmp (arg, "ilp32") == 0)
6076 md.flags &= ~EF_IA_64_ABI64;
6078 else if (strcmp (arg, "le") == 0)
6080 md.flags &= ~EF_IA_64_BE;
6082 else if (strcmp (arg, "be") == 0)
6084 md.flags |= EF_IA_64_BE;
6091 if (strcmp (arg, "so") == 0)
6093 /* Suppress signon message. */
6095 else if (strcmp (arg, "pi") == 0)
6097 /* Reject privileged instructions. FIXME */
6099 else if (strcmp (arg, "us") == 0)
6101 /* Allow union of signed and unsigned range. FIXME */
6103 else if (strcmp (arg, "close_fcalls") == 0)
6105 /* Do not resolve global function calls. */
6112 /* temp[="prefix"] Insert temporary labels into the object file
6113 symbol table prefixed by "prefix".
6114 Default prefix is ":temp:".
6119 /* indirect=<tgt> Assume unannotated indirect branches behavior
6120 according to <tgt> --
6121 exit: branch out from the current context (default)
6122 labels: all labels in context may be branch targets
6124 if (strncmp (arg, "indirect=", 9) != 0)
6129 /* -X conflicts with an ignored option, use -x instead */
6131 if (!arg || strcmp (arg, "explicit") == 0)
6133 /* set default mode to explicit */
6134 md.default_explicit_mode = 1;
6137 else if (strcmp (arg, "auto") == 0)
6139 md.default_explicit_mode = 0;
6141 else if (strcmp (arg, "debug") == 0)
6145 else if (strcmp (arg, "debugx") == 0)
6147 md.default_explicit_mode = 1;
6152 as_bad (_("Unrecognized option '-x%s'"), arg);
6157 /* nops Print nops statistics. */
6160 /* GNU specific switches for gcc. */
6161 case OPTION_MCONSTANT_GP:
6162 md.flags |= EF_IA_64_CONS_GP;
6165 case OPTION_MAUTO_PIC:
6166 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
6177 md_show_usage (stream)
6182 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6183 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6184 -x | -xexplicit turn on dependency violation checking (default)\n\
6185 -xauto automagically remove dependency violations\n\
6186 -xdebug debug dependency violation checker\n"),
6190 /* Return true if TYPE fits in TEMPL at SLOT. */
6193 match (int templ, int type, int slot)
6195 enum ia64_unit unit;
6198 unit = ia64_templ_desc[templ].exec_unit[slot];
6201 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
6203 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
6205 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
6206 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
6207 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
6208 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
6209 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
6210 default: result = 0; break;
6215 /* Add a bit of extra goodness if a nop of type F or B would fit
6216 in TEMPL at SLOT. */
6219 extra_goodness (int templ, int slot)
6221 if (slot == 1 && match (templ, IA64_TYPE_F, slot))
6223 if (slot == 2 && match (templ, IA64_TYPE_B, slot))
6228 /* This function is called once, at assembler startup time. It sets
6229 up all the tables, etc. that the MD part of the assembler will need
6230 that can be determined before arguments are parsed. */
6234 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
6239 md.explicit_mode = md.default_explicit_mode;
6241 bfd_set_section_alignment (stdoutput, text_section, 4);
6243 target_big_endian = TARGET_BYTES_BIG_ENDIAN;
6244 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
6245 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
6246 &zero_address_frag);
6248 pseudo_func[FUNC_GP_RELATIVE].u.sym =
6249 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
6250 &zero_address_frag);
6252 pseudo_func[FUNC_LT_RELATIVE].u.sym =
6253 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
6254 &zero_address_frag);
6256 pseudo_func[FUNC_PC_RELATIVE].u.sym =
6257 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
6258 &zero_address_frag);
6260 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
6261 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
6262 &zero_address_frag);
6264 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
6265 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
6266 &zero_address_frag);
6268 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
6269 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
6270 &zero_address_frag);
6272 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
6273 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
6274 &zero_address_frag);
6276 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
6277 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
6278 &zero_address_frag);
6280 /* Compute the table of best templates. We compute goodness as a
6281 base 4 value, in which each match counts for 3, each F counts
6282 for 2, each B counts for 1. This should maximize the number of
6283 F and B nops in the chosen bundles, which is good because these
6284 pipelines are least likely to be overcommitted. */
6285 for (i = 0; i < IA64_NUM_TYPES; ++i)
6286 for (j = 0; j < IA64_NUM_TYPES; ++j)
6287 for (k = 0; k < IA64_NUM_TYPES; ++k)
6290 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
6293 if (match (t, i, 0))
6295 if (match (t, j, 1))
6297 if (match (t, k, 2))
6298 goodness = 3 + 3 + 3;
6300 goodness = 3 + 3 + extra_goodness (t, 2);
6302 else if (match (t, j, 2))
6303 goodness = 3 + 3 + extra_goodness (t, 1);
6307 goodness += extra_goodness (t, 1);
6308 goodness += extra_goodness (t, 2);
6311 else if (match (t, i, 1))
6313 if (match (t, j, 2))
6316 goodness = 3 + extra_goodness (t, 2);
6318 else if (match (t, i, 2))
6319 goodness = 3 + extra_goodness (t, 1);
6321 if (goodness > best)
6324 best_template[i][j][k] = t;
6329 for (i = 0; i < NUM_SLOTS; ++i)
6330 md.slot[i].user_template = -1;
6332 md.pseudo_hash = hash_new ();
6333 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
6335 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
6336 (void *) (pseudo_opcode + i));
6338 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6339 pseudo_opcode[i].name, err);
6342 md.reg_hash = hash_new ();
6343 md.dynreg_hash = hash_new ();
6344 md.const_hash = hash_new ();
6345 md.entry_hash = hash_new ();
6347 /* general registers: */
6350 for (i = 0; i < total; ++i)
6352 sprintf (name, "r%d", i - REG_GR);
6353 md.regsym[i] = declare_register (name, i);
6356 /* floating point registers: */
6358 for (; i < total; ++i)
6360 sprintf (name, "f%d", i - REG_FR);
6361 md.regsym[i] = declare_register (name, i);
6364 /* application registers: */
6367 for (; i < total; ++i)
6369 sprintf (name, "ar%d", i - REG_AR);
6370 md.regsym[i] = declare_register (name, i);
6373 /* control registers: */
6376 for (; i < total; ++i)
6378 sprintf (name, "cr%d", i - REG_CR);
6379 md.regsym[i] = declare_register (name, i);
6382 /* predicate registers: */
6384 for (; i < total; ++i)
6386 sprintf (name, "p%d", i - REG_P);
6387 md.regsym[i] = declare_register (name, i);
6390 /* branch registers: */
6392 for (; i < total; ++i)
6394 sprintf (name, "b%d", i - REG_BR);
6395 md.regsym[i] = declare_register (name, i);
6398 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
6399 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
6400 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
6401 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
6402 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
6403 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
6404 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
6406 for (i = 0; i < NELEMS (indirect_reg); ++i)
6408 regnum = indirect_reg[i].regnum;
6409 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
6412 /* define synonyms for application registers: */
6413 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
6414 md.regsym[i] = declare_register (ar[i - REG_AR].name,
6415 REG_AR + ar[i - REG_AR].regnum);
6417 /* define synonyms for control registers: */
6418 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
6419 md.regsym[i] = declare_register (cr[i - REG_CR].name,
6420 REG_CR + cr[i - REG_CR].regnum);
6422 declare_register ("gp", REG_GR + 1);
6423 declare_register ("sp", REG_GR + 12);
6424 declare_register ("rp", REG_BR + 0);
6426 /* pseudo-registers used to specify unwind info: */
6427 declare_register ("psp", REG_PSP);
6429 declare_register_set ("ret", 4, REG_GR + 8);
6430 declare_register_set ("farg", 8, REG_FR + 8);
6431 declare_register_set ("fret", 8, REG_FR + 8);
6433 for (i = 0; i < NELEMS (const_bits); ++i)
6435 err = hash_insert (md.const_hash, const_bits[i].name,
6436 (PTR) (const_bits + i));
6438 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6442 /* Set the architecture and machine depending on defaults and command line
6444 if (md.flags & EF_IA_64_ABI64)
6445 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64);
6447 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32);
6450 as_warn (_("Could not set architecture and machine"));
6452 md.mem_offset.hint = 0;
6455 md.entry_labels = NULL;
6458 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6459 because that is called after md_parse_option which is where we do the
6460 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6461 default endianness. */
6464 ia64_init (argc, argv)
6465 int argc ATTRIBUTE_UNUSED;
6466 char **argv ATTRIBUTE_UNUSED;
6468 md.flags = EF_IA_64_ABI64;
6469 if (TARGET_BYTES_BIG_ENDIAN)
6470 md.flags |= EF_IA_64_BE;
6473 /* Return a string for the target object file format. */
6476 ia64_target_format ()
6478 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6480 if (md.flags & EF_IA_64_BE)
6482 if (md.flags & EF_IA_64_ABI64)
6484 return "elf64-ia64-aix-big";
6486 return "elf64-ia64-big";
6490 return "elf32-ia64-aix-big";
6492 return "elf32-ia64-big";
6497 if (md.flags & EF_IA_64_ABI64)
6499 return "elf64-ia64-aix-little";
6501 return "elf64-ia64-little";
6505 return "elf32-ia64-aix-little";
6507 return "elf32-ia64-little";
6512 return "unknown-format";
6516 ia64_end_of_source ()
6518 /* terminate insn group upon reaching end of file: */
6519 insn_group_break (1, 0, 0);
6521 /* emits slots we haven't written yet: */
6522 ia64_flush_insns ();
6524 bfd_set_private_flags (stdoutput, md.flags);
6526 md.mem_offset.hint = 0;
6532 if (md.qp.X_op == O_register)
6533 as_bad ("qualifying predicate not followed by instruction");
6534 md.qp.X_op = O_absent;
6536 if (ignore_input ())
6539 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
6541 if (md.detect_dv && !md.explicit_mode)
6542 as_warn (_("Explicit stops are ignored in auto mode"));
6544 insn_group_break (1, 0, 0);
6548 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6550 static int defining_tag = 0;
6553 ia64_unrecognized_line (ch)
6559 expression (&md.qp);
6560 if (*input_line_pointer++ != ')')
6562 as_bad ("Expected ')'");
6565 if (md.qp.X_op != O_register)
6567 as_bad ("Qualifying predicate expected");
6570 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
6572 as_bad ("Predicate register expected");
6578 if (md.manual_bundling)
6579 as_warn ("Found '{' when manual bundling is already turned on");
6581 CURR_SLOT.manual_bundling_on = 1;
6582 md.manual_bundling = 1;
6584 /* Bundling is only acceptable in explicit mode
6585 or when in default automatic mode. */
6586 if (md.detect_dv && !md.explicit_mode)
6588 if (!md.mode_explicitly_set
6589 && !md.default_explicit_mode)
6592 as_warn (_("Found '{' after explicit switch to automatic mode"));
6597 if (!md.manual_bundling)
6598 as_warn ("Found '}' when manual bundling is off");
6600 PREV_SLOT.manual_bundling_off = 1;
6601 md.manual_bundling = 0;
6603 /* switch back to automatic mode, if applicable */
6606 && !md.mode_explicitly_set
6607 && !md.default_explicit_mode)
6610 /* Allow '{' to follow on the same line. We also allow ";;", but that
6611 happens automatically because ';' is an end of line marker. */
6613 if (input_line_pointer[0] == '{')
6615 input_line_pointer++;
6616 return ia64_unrecognized_line ('{');
6619 demand_empty_rest_of_line ();
6629 if (md.qp.X_op == O_register)
6631 as_bad ("Tag must come before qualifying predicate.");
6635 /* This implements just enough of read_a_source_file in read.c to
6636 recognize labels. */
6637 if (is_name_beginner (*input_line_pointer))
6639 s = input_line_pointer;
6640 c = get_symbol_end ();
6642 else if (LOCAL_LABELS_FB
6643 && isdigit ((unsigned char) *input_line_pointer))
6646 while (isdigit ((unsigned char) *input_line_pointer))
6647 temp = (temp * 10) + *input_line_pointer++ - '0';
6648 fb_label_instance_inc (temp);
6649 s = fb_label_name (temp, 0);
6650 c = *input_line_pointer;
6659 /* Put ':' back for error messages' sake. */
6660 *input_line_pointer++ = ':';
6661 as_bad ("Expected ':'");
6668 /* Put ':' back for error messages' sake. */
6669 *input_line_pointer++ = ':';
6670 if (*input_line_pointer++ != ']')
6672 as_bad ("Expected ']'");
6677 as_bad ("Tag name expected");
6687 /* Not a valid line. */
6692 ia64_frob_label (sym)
6695 struct label_fix *fix;
6697 /* Tags need special handling since they are not bundle breaks like
6701 fix = obstack_alloc (¬es, sizeof (*fix));
6703 fix->next = CURR_SLOT.tag_fixups;
6704 CURR_SLOT.tag_fixups = fix;
6709 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6711 md.last_text_seg = now_seg;
6712 fix = obstack_alloc (¬es, sizeof (*fix));
6714 fix->next = CURR_SLOT.label_fixups;
6715 CURR_SLOT.label_fixups = fix;
6717 /* Keep track of how many code entry points we've seen. */
6718 if (md.path == md.maxpaths)
6721 md.entry_labels = (const char **)
6722 xrealloc ((void *) md.entry_labels,
6723 md.maxpaths * sizeof (char *));
6725 md.entry_labels[md.path++] = S_GET_NAME (sym);
6730 ia64_flush_pending_output ()
6732 if (!md.keep_pending_output
6733 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6735 /* ??? This causes many unnecessary stop bits to be emitted.
6736 Unfortunately, it isn't clear if it is safe to remove this. */
6737 insn_group_break (1, 0, 0);
6738 ia64_flush_insns ();
6742 /* Do ia64-specific expression optimization. All that's done here is
6743 to transform index expressions that are either due to the indexing
6744 of rotating registers or due to the indexing of indirect register
6747 ia64_optimize_expr (l, op, r)
6756 if (l->X_op == O_register && r->X_op == O_constant)
6758 num_regs = (l->X_add_number >> 16);
6759 if ((unsigned) r->X_add_number >= num_regs)
6762 as_bad ("No current frame");
6764 as_bad ("Index out of range 0..%u", num_regs - 1);
6765 r->X_add_number = 0;
6767 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6770 else if (l->X_op == O_register && r->X_op == O_register)
6772 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6773 || l->X_add_number == IND_MEM)
6775 as_bad ("Indirect register set name expected");
6776 l->X_add_number = IND_CPUID;
6779 l->X_op_symbol = md.regsym[l->X_add_number];
6780 l->X_add_number = r->X_add_number;
6788 ia64_parse_name (name, e)
6792 struct const_desc *cdesc;
6793 struct dynreg *dr = 0;
6794 unsigned int regnum;
6798 /* first see if NAME is a known register name: */
6799 sym = hash_find (md.reg_hash, name);
6802 e->X_op = O_register;
6803 e->X_add_number = S_GET_VALUE (sym);
6807 cdesc = hash_find (md.const_hash, name);
6810 e->X_op = O_constant;
6811 e->X_add_number = cdesc->value;
6815 /* check for inN, locN, or outN: */
6819 if (name[1] == 'n' && isdigit (name[2]))
6827 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6835 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6848 /* The name is inN, locN, or outN; parse the register number. */
6849 regnum = strtoul (name, &end, 10);
6850 if (end > name && *end == '\0')
6852 if ((unsigned) regnum >= dr->num_regs)
6855 as_bad ("No current frame");
6857 as_bad ("Register number out of range 0..%u",
6861 e->X_op = O_register;
6862 e->X_add_number = dr->base + regnum;
6867 if ((dr = hash_find (md.dynreg_hash, name)))
6869 /* We've got ourselves the name of a rotating register set.
6870 Store the base register number in the low 16 bits of
6871 X_add_number and the size of the register set in the top 16
6873 e->X_op = O_register;
6874 e->X_add_number = dr->base | (dr->num_regs << 16);
6880 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6883 ia64_canonicalize_symbol_name (name)
6886 size_t len = strlen (name);
6887 if (len > 1 && name[len - 1] == '#')
6888 name[len - 1] = '\0';
6893 is_conditional_branch (idesc)
6894 struct ia64_opcode *idesc;
6896 return (strncmp (idesc->name, "br", 2) == 0
6897 && (strcmp (idesc->name, "br") == 0
6898 || strncmp (idesc->name, "br.cond", 7) == 0
6899 || strncmp (idesc->name, "br.call", 7) == 0
6900 || strncmp (idesc->name, "br.ret", 6) == 0
6901 || strcmp (idesc->name, "brl") == 0
6902 || strncmp (idesc->name, "brl.cond", 7) == 0
6903 || strncmp (idesc->name, "brl.call", 7) == 0
6904 || strncmp (idesc->name, "brl.ret", 6) == 0));
6907 /* Return whether the given opcode is a taken branch. If there's any doubt,
6911 is_taken_branch (idesc)
6912 struct ia64_opcode *idesc;
6914 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
6915 || strncmp (idesc->name, "br.ia", 5) == 0);
6918 /* Return whether the given opcode is an interruption or rfi. If there's any
6919 doubt, returns zero. */
6922 is_interruption_or_rfi (idesc)
6923 struct ia64_opcode *idesc;
6925 if (strcmp (idesc->name, "rfi") == 0)
6930 /* Returns the index of the given dependency in the opcode's list of chks, or
6931 -1 if there is no dependency. */
6934 depends_on (depind, idesc)
6936 struct ia64_opcode *idesc;
6939 const struct ia64_opcode_dependency *dep = idesc->dependencies;
6940 for (i = 0; i < dep->nchks; i++)
6942 if (depind == DEP (dep->chks[i]))
6948 /* Determine a set of specific resources used for a particular resource
6949 class. Returns the number of specific resources identified For those
6950 cases which are not determinable statically, the resource returned is
6953 Meanings of value in 'NOTE':
6954 1) only read/write when the register number is explicitly encoded in the
6956 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6957 accesses CFM when qualifying predicate is in the rotating region.
6958 3) general register value is used to specify an indirect register; not
6959 determinable statically.
6960 4) only read the given resource when bits 7:0 of the indirect index
6961 register value does not match the register number of the resource; not
6962 determinable statically.
6963 5) all rules are implementation specific.
6964 6) only when both the index specified by the reader and the index specified
6965 by the writer have the same value in bits 63:61; not determinable
6967 7) only access the specified resource when the corresponding mask bit is
6969 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6970 only read when these insns reference FR2-31
6971 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6972 written when these insns write FR32-127
6973 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6975 11) The target predicates are written independently of PR[qp], but source
6976 registers are only read if PR[qp] is true. Since the state of PR[qp]
6977 cannot statically be determined, all source registers are marked used.
6978 12) This insn only reads the specified predicate register when that
6979 register is the PR[qp].
6980 13) This reference to ld-c only applies to teh GR whose value is loaded
6981 with data returned from memory, not the post-incremented address register.
6982 14) The RSE resource includes the implementation-specific RSE internal
6983 state resources. At least one (and possibly more) of these resources are
6984 read by each instruction listed in IC:rse-readers. At least one (and
6985 possibly more) of these resources are written by each insn listed in
6987 15+16) Represents reserved instructions, which the assembler does not
6990 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6991 this code; there are no dependency violations based on memory access.
6994 #define MAX_SPECS 256
6999 specify_resource (dep, idesc, type, specs, note, path)
7000 const struct ia64_dependency *dep;
7001 struct ia64_opcode *idesc;
7002 int type; /* is this a DV chk or a DV reg? */
7003 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
7004 int note; /* resource note for this insn's usage */
7005 int path; /* which execution path to examine */
7012 if (dep->mode == IA64_DV_WAW
7013 || (dep->mode == IA64_DV_RAW && type == DV_REG)
7014 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
7017 /* template for any resources we identify */
7018 tmpl.dependency = dep;
7020 tmpl.insn_srlz = tmpl.data_srlz = 0;
7021 tmpl.qp_regno = CURR_SLOT.qp_regno;
7022 tmpl.link_to_qp_branch = 1;
7023 tmpl.mem_offset.hint = 0;
7026 tmpl.cmp_type = CMP_NONE;
7029 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7030 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7031 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7033 /* we don't need to track these */
7034 if (dep->semantics == IA64_DVS_NONE)
7037 switch (dep->specifier)
7042 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7044 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7045 if (regno >= 0 && regno <= 7)
7047 specs[count] = tmpl;
7048 specs[count++].index = regno;
7054 for (i = 0; i < 8; i++)
7056 specs[count] = tmpl;
7057 specs[count++].index = i;
7066 case IA64_RS_AR_UNAT:
7067 /* This is a mov =AR or mov AR= instruction. */
7068 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7070 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7071 if (regno == AR_UNAT)
7073 specs[count++] = tmpl;
7078 /* This is a spill/fill, or other instruction that modifies the
7081 /* Unless we can determine the specific bits used, mark the whole
7082 thing; bits 8:3 of the memory address indicate the bit used in
7083 UNAT. The .mem.offset hint may be used to eliminate a small
7084 subset of conflicts. */
7085 specs[count] = tmpl;
7086 if (md.mem_offset.hint)
7089 fprintf (stderr, " Using hint for spill/fill\n");
7090 /* The index isn't actually used, just set it to something
7091 approximating the bit index. */
7092 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
7093 specs[count].mem_offset.hint = 1;
7094 specs[count].mem_offset.offset = md.mem_offset.offset;
7095 specs[count++].mem_offset.base = md.mem_offset.base;
7099 specs[count++].specific = 0;
7107 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7109 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7110 if ((regno >= 8 && regno <= 15)
7111 || (regno >= 20 && regno <= 23)
7112 || (regno >= 31 && regno <= 39)
7113 || (regno >= 41 && regno <= 47)
7114 || (regno >= 67 && regno <= 111))
7116 specs[count] = tmpl;
7117 specs[count++].index = regno;
7130 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7132 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7133 if ((regno >= 48 && regno <= 63)
7134 || (regno >= 112 && regno <= 127))
7136 specs[count] = tmpl;
7137 specs[count++].index = regno;
7143 for (i = 48; i < 64; i++)
7145 specs[count] = tmpl;
7146 specs[count++].index = i;
7148 for (i = 112; i < 128; i++)
7150 specs[count] = tmpl;
7151 specs[count++].index = i;
7169 for (i = 0; i < idesc->num_outputs; i++)
7170 if (idesc->operands[i] == IA64_OPND_B1
7171 || idesc->operands[i] == IA64_OPND_B2)
7173 specs[count] = tmpl;
7174 specs[count++].index =
7175 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7180 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++)
7181 if (idesc->operands[i] == IA64_OPND_B1
7182 || idesc->operands[i] == IA64_OPND_B2)
7184 specs[count] = tmpl;
7185 specs[count++].index =
7186 CURR_SLOT.opnd[i].X_add_number - REG_BR;
7192 case IA64_RS_CPUID: /* four or more registers */
7195 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
7197 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7198 if (regno >= 0 && regno < NELEMS (gr_values)
7201 specs[count] = tmpl;
7202 specs[count++].index = gr_values[regno].value & 0xFF;
7206 specs[count] = tmpl;
7207 specs[count++].specific = 0;
7217 case IA64_RS_DBR: /* four or more registers */
7220 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
7222 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7223 if (regno >= 0 && regno < NELEMS (gr_values)
7226 specs[count] = tmpl;
7227 specs[count++].index = gr_values[regno].value & 0xFF;
7231 specs[count] = tmpl;
7232 specs[count++].specific = 0;
7236 else if (note == 0 && !rsrc_write)
7238 specs[count] = tmpl;
7239 specs[count++].specific = 0;
7247 case IA64_RS_IBR: /* four or more registers */
7250 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
7252 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7253 if (regno >= 0 && regno < NELEMS (gr_values)
7256 specs[count] = tmpl;
7257 specs[count++].index = gr_values[regno].value & 0xFF;
7261 specs[count] = tmpl;
7262 specs[count++].specific = 0;
7275 /* These are implementation specific. Force all references to
7276 conflict with all other references. */
7277 specs[count] = tmpl;
7278 specs[count++].specific = 0;
7286 case IA64_RS_PKR: /* 16 or more registers */
7287 if (note == 3 || note == 4)
7289 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
7291 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7292 if (regno >= 0 && regno < NELEMS (gr_values)
7297 specs[count] = tmpl;
7298 specs[count++].index = gr_values[regno].value & 0xFF;
7301 for (i = 0; i < NELEMS (gr_values); i++)
7303 /* Uses all registers *except* the one in R3. */
7304 if ((unsigned)i != (gr_values[regno].value & 0xFF))
7306 specs[count] = tmpl;
7307 specs[count++].index = i;
7313 specs[count] = tmpl;
7314 specs[count++].specific = 0;
7321 specs[count] = tmpl;
7322 specs[count++].specific = 0;
7326 case IA64_RS_PMC: /* four or more registers */
7329 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
7330 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
7333 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
7335 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
7336 if (regno >= 0 && regno < NELEMS (gr_values)
7339 specs[count] = tmpl;
7340 specs[count++].index = gr_values[regno].value & 0xFF;
7344 specs[count] = tmpl;
7345 specs[count++].specific = 0;
7355 case IA64_RS_PMD: /* four or more registers */
7358 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
7360 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7361 if (regno >= 0 && regno < NELEMS (gr_values)
7364 specs[count] = tmpl;
7365 specs[count++].index = gr_values[regno].value & 0xFF;
7369 specs[count] = tmpl;
7370 specs[count++].specific = 0;
7380 case IA64_RS_RR: /* eight registers */
7383 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
7385 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
7386 if (regno >= 0 && regno < NELEMS (gr_values)
7389 specs[count] = tmpl;
7390 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
7394 specs[count] = tmpl;
7395 specs[count++].specific = 0;
7399 else if (note == 0 && !rsrc_write)
7401 specs[count] = tmpl;
7402 specs[count++].specific = 0;
7410 case IA64_RS_CR_IRR:
7413 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7414 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
7416 && idesc->operands[1] == IA64_OPND_CR3
7419 for (i = 0; i < 4; i++)
7421 specs[count] = tmpl;
7422 specs[count++].index = CR_IRR0 + i;
7428 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7429 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7431 && regno <= CR_IRR3)
7433 specs[count] = tmpl;
7434 specs[count++].index = regno;
7443 case IA64_RS_CR_LRR:
7450 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7451 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
7452 && (regno == CR_LRR0 || regno == CR_LRR1))
7454 specs[count] = tmpl;
7455 specs[count++].index = regno;
7463 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7465 specs[count] = tmpl;
7466 specs[count++].index =
7467 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7482 else if (rsrc_write)
7484 if (dep->specifier == IA64_RS_FRb
7485 && idesc->operands[0] == IA64_OPND_F1)
7487 specs[count] = tmpl;
7488 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
7493 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
7495 if (idesc->operands[i] == IA64_OPND_F2
7496 || idesc->operands[i] == IA64_OPND_F3
7497 || idesc->operands[i] == IA64_OPND_F4)
7499 specs[count] = tmpl;
7500 specs[count++].index =
7501 CURR_SLOT.opnd[i].X_add_number - REG_FR;
7510 /* This reference applies only to the GR whose value is loaded with
7511 data returned from memory. */
7512 specs[count] = tmpl;
7513 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7519 for (i = 0; i < idesc->num_outputs; i++)
7520 if (idesc->operands[i] == IA64_OPND_R1
7521 || idesc->operands[i] == IA64_OPND_R2
7522 || idesc->operands[i] == IA64_OPND_R3)
7524 specs[count] = tmpl;
7525 specs[count++].index =
7526 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7528 if (idesc->flags & IA64_OPCODE_POSTINC)
7529 for (i = 0; i < NELEMS (idesc->operands); i++)
7530 if (idesc->operands[i] == IA64_OPND_MR3)
7532 specs[count] = tmpl;
7533 specs[count++].index =
7534 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7539 /* Look for anything that reads a GR. */
7540 for (i = 0; i < NELEMS (idesc->operands); i++)
7542 if (idesc->operands[i] == IA64_OPND_MR3
7543 || idesc->operands[i] == IA64_OPND_CPUID_R3
7544 || idesc->operands[i] == IA64_OPND_DBR_R3
7545 || idesc->operands[i] == IA64_OPND_IBR_R3
7546 || idesc->operands[i] == IA64_OPND_MSR_R3
7547 || idesc->operands[i] == IA64_OPND_PKR_R3
7548 || idesc->operands[i] == IA64_OPND_PMC_R3
7549 || idesc->operands[i] == IA64_OPND_PMD_R3
7550 || idesc->operands[i] == IA64_OPND_RR_R3
7551 || ((i >= idesc->num_outputs)
7552 && (idesc->operands[i] == IA64_OPND_R1
7553 || idesc->operands[i] == IA64_OPND_R2
7554 || idesc->operands[i] == IA64_OPND_R3
7555 /* addl source register. */
7556 || idesc->operands[i] == IA64_OPND_R3_2)))
7558 specs[count] = tmpl;
7559 specs[count++].index =
7560 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7571 /* This is the same as IA64_RS_PRr, except that the register range is
7572 from 1 - 15, and there are no rotating register reads/writes here. */
7576 for (i = 1; i < 16; i++)
7578 specs[count] = tmpl;
7579 specs[count++].index = i;
7585 /* Mark only those registers indicated by the mask. */
7588 mask = CURR_SLOT.opnd[2].X_add_number;
7589 for (i = 1; i < 16; i++)
7590 if (mask & ((valueT) 1 << i))
7592 specs[count] = tmpl;
7593 specs[count++].index = i;
7601 else if (note == 11) /* note 11 implies note 1 as well */
7605 for (i = 0; i < idesc->num_outputs; i++)
7607 if (idesc->operands[i] == IA64_OPND_P1
7608 || idesc->operands[i] == IA64_OPND_P2)
7610 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7611 if (regno >= 1 && regno < 16)
7613 specs[count] = tmpl;
7614 specs[count++].index = regno;
7624 else if (note == 12)
7626 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7628 specs[count] = tmpl;
7629 specs[count++].index = CURR_SLOT.qp_regno;
7636 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7637 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7638 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7639 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7641 if ((idesc->operands[0] == IA64_OPND_P1
7642 || idesc->operands[0] == IA64_OPND_P2)
7643 && p1 >= 1 && p1 < 16)
7645 specs[count] = tmpl;
7646 specs[count].cmp_type =
7647 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7648 specs[count++].index = p1;
7650 if ((idesc->operands[1] == IA64_OPND_P1
7651 || idesc->operands[1] == IA64_OPND_P2)
7652 && p2 >= 1 && p2 < 16)
7654 specs[count] = tmpl;
7655 specs[count].cmp_type =
7656 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7657 specs[count++].index = p2;
7662 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7664 specs[count] = tmpl;
7665 specs[count++].index = CURR_SLOT.qp_regno;
7667 if (idesc->operands[1] == IA64_OPND_PR)
7669 for (i = 1; i < 16; i++)
7671 specs[count] = tmpl;
7672 specs[count++].index = i;
7683 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7684 simplified cases of this. */
7688 for (i = 16; i < 63; i++)
7690 specs[count] = tmpl;
7691 specs[count++].index = i;
7697 /* Mark only those registers indicated by the mask. */
7699 && idesc->operands[0] == IA64_OPND_PR)
7701 mask = CURR_SLOT.opnd[2].X_add_number;
7702 if (mask & ((valueT) 1<<16))
7703 for (i = 16; i < 63; i++)
7705 specs[count] = tmpl;
7706 specs[count++].index = i;
7710 && idesc->operands[0] == IA64_OPND_PR_ROT)
7712 for (i = 16; i < 63; i++)
7714 specs[count] = tmpl;
7715 specs[count++].index = i;
7723 else if (note == 11) /* note 11 implies note 1 as well */
7727 for (i = 0; i < idesc->num_outputs; i++)
7729 if (idesc->operands[i] == IA64_OPND_P1
7730 || idesc->operands[i] == IA64_OPND_P2)
7732 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7733 if (regno >= 16 && regno < 63)
7735 specs[count] = tmpl;
7736 specs[count++].index = regno;
7746 else if (note == 12)
7748 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
7750 specs[count] = tmpl;
7751 specs[count++].index = CURR_SLOT.qp_regno;
7758 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7759 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7760 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7761 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7763 if ((idesc->operands[0] == IA64_OPND_P1
7764 || idesc->operands[0] == IA64_OPND_P2)
7765 && p1 >= 16 && p1 < 63)
7767 specs[count] = tmpl;
7768 specs[count].cmp_type =
7769 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7770 specs[count++].index = p1;
7772 if ((idesc->operands[1] == IA64_OPND_P1
7773 || idesc->operands[1] == IA64_OPND_P2)
7774 && p2 >= 16 && p2 < 63)
7776 specs[count] = tmpl;
7777 specs[count].cmp_type =
7778 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7779 specs[count++].index = p2;
7784 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
7786 specs[count] = tmpl;
7787 specs[count++].index = CURR_SLOT.qp_regno;
7789 if (idesc->operands[1] == IA64_OPND_PR)
7791 for (i = 16; i < 63; i++)
7793 specs[count] = tmpl;
7794 specs[count++].index = i;
7806 /* Verify that the instruction is using the PSR bit indicated in
7810 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7812 if (dep->regindex < 6)
7814 specs[count++] = tmpl;
7817 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7819 if (dep->regindex < 32
7820 || dep->regindex == 35
7821 || dep->regindex == 36
7822 || (!rsrc_write && dep->regindex == PSR_CPL))
7824 specs[count++] = tmpl;
7827 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7829 if (dep->regindex < 32
7830 || dep->regindex == 35
7831 || dep->regindex == 36
7832 || (rsrc_write && dep->regindex == PSR_CPL))
7834 specs[count++] = tmpl;
7839 /* Several PSR bits have very specific dependencies. */
7840 switch (dep->regindex)
7843 specs[count++] = tmpl;
7848 specs[count++] = tmpl;
7852 /* Only certain CR accesses use PSR.ic */
7853 if (idesc->operands[0] == IA64_OPND_CR3
7854 || idesc->operands[1] == IA64_OPND_CR3)
7857 ((idesc->operands[0] == IA64_OPND_CR3)
7860 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7875 specs[count++] = tmpl;
7884 specs[count++] = tmpl;
7888 /* Only some AR accesses use cpl */
7889 if (idesc->operands[0] == IA64_OPND_AR3
7890 || idesc->operands[1] == IA64_OPND_AR3)
7893 ((idesc->operands[0] == IA64_OPND_AR3)
7896 CURR_SLOT.opnd[index].X_add_number - REG_AR;
7903 && regno <= AR_K7))))
7905 specs[count++] = tmpl;
7910 specs[count++] = tmpl;
7920 if (idesc->operands[0] == IA64_OPND_IMMU24)
7922 mask = CURR_SLOT.opnd[0].X_add_number;
7928 if (mask & ((valueT) 1 << dep->regindex))
7930 specs[count++] = tmpl;
7935 int min = dep->regindex == PSR_DFL ? 2 : 32;
7936 int max = dep->regindex == PSR_DFL ? 31 : 127;
7937 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7938 for (i = 0; i < NELEMS (idesc->operands); i++)
7940 if (idesc->operands[i] == IA64_OPND_F1
7941 || idesc->operands[i] == IA64_OPND_F2
7942 || idesc->operands[i] == IA64_OPND_F3
7943 || idesc->operands[i] == IA64_OPND_F4)
7945 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7946 if (reg >= min && reg <= max)
7948 specs[count++] = tmpl;
7955 int min = dep->regindex == PSR_MFL ? 2 : 32;
7956 int max = dep->regindex == PSR_MFL ? 31 : 127;
7957 /* mfh is read on writes to FR32-127; mfl is read on writes to
7959 for (i = 0; i < idesc->num_outputs; i++)
7961 if (idesc->operands[i] == IA64_OPND_F1)
7963 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7964 if (reg >= min && reg <= max)
7966 specs[count++] = tmpl;
7971 else if (note == 10)
7973 for (i = 0; i < NELEMS (idesc->operands); i++)
7975 if (idesc->operands[i] == IA64_OPND_R1
7976 || idesc->operands[i] == IA64_OPND_R2
7977 || idesc->operands[i] == IA64_OPND_R3)
7979 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7980 if (regno >= 16 && regno <= 31)
7982 specs[count++] = tmpl;
7993 case IA64_RS_AR_FPSR:
7994 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7996 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7997 if (regno == AR_FPSR)
7999 specs[count++] = tmpl;
8004 specs[count++] = tmpl;
8009 /* Handle all AR[REG] resources */
8010 if (note == 0 || note == 1)
8012 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
8013 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
8014 && regno == dep->regindex)
8016 specs[count++] = tmpl;
8018 /* other AR[REG] resources may be affected by AR accesses */
8019 else if (idesc->operands[0] == IA64_OPND_AR3)
8022 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
8023 switch (dep->regindex)
8029 if (regno == AR_BSPSTORE)
8031 specs[count++] = tmpl;
8035 (regno == AR_BSPSTORE
8036 || regno == AR_RNAT))
8038 specs[count++] = tmpl;
8043 else if (idesc->operands[1] == IA64_OPND_AR3)
8046 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
8047 switch (dep->regindex)
8052 if (regno == AR_BSPSTORE || regno == AR_RNAT)
8054 specs[count++] = tmpl;
8061 specs[count++] = tmpl;
8071 /* Handle all CR[REG] resources */
8072 if (note == 0 || note == 1)
8074 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
8076 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
8077 if (regno == dep->regindex)
8079 specs[count++] = tmpl;
8081 else if (!rsrc_write)
8083 /* Reads from CR[IVR] affect other resources. */
8084 if (regno == CR_IVR)
8086 if ((dep->regindex >= CR_IRR0
8087 && dep->regindex <= CR_IRR3)
8088 || dep->regindex == CR_TPR)
8090 specs[count++] = tmpl;
8097 specs[count++] = tmpl;
8106 case IA64_RS_INSERVICE:
8107 /* look for write of EOI (67) or read of IVR (65) */
8108 if ((idesc->operands[0] == IA64_OPND_CR3
8109 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
8110 || (idesc->operands[1] == IA64_OPND_CR3
8111 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
8113 specs[count++] = tmpl;
8120 specs[count++] = tmpl;
8131 specs[count++] = tmpl;
8135 /* Check if any of the registers accessed are in the rotating region.
8136 mov to/from pr accesses CFM only when qp_regno is in the rotating
8138 for (i = 0; i < NELEMS (idesc->operands); i++)
8140 if (idesc->operands[i] == IA64_OPND_R1
8141 || idesc->operands[i] == IA64_OPND_R2
8142 || idesc->operands[i] == IA64_OPND_R3)
8144 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8145 /* Assumes that md.rot.num_regs is always valid */
8146 if (md.rot.num_regs > 0
8148 && num < 31 + md.rot.num_regs)
8150 specs[count] = tmpl;
8151 specs[count++].specific = 0;
8154 else if (idesc->operands[i] == IA64_OPND_F1
8155 || idesc->operands[i] == IA64_OPND_F2
8156 || idesc->operands[i] == IA64_OPND_F3
8157 || idesc->operands[i] == IA64_OPND_F4)
8159 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
8162 specs[count] = tmpl;
8163 specs[count++].specific = 0;
8166 else if (idesc->operands[i] == IA64_OPND_P1
8167 || idesc->operands[i] == IA64_OPND_P2)
8169 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
8172 specs[count] = tmpl;
8173 specs[count++].specific = 0;
8177 if (CURR_SLOT.qp_regno > 15)
8179 specs[count] = tmpl;
8180 specs[count++].specific = 0;
8185 /* This is the same as IA64_RS_PRr, except simplified to account for
8186 the fact that there is only one register. */
8190 specs[count++] = tmpl;
8195 if (idesc->operands[2] == IA64_OPND_IMM17)
8196 mask = CURR_SLOT.opnd[2].X_add_number;
8197 if (mask & ((valueT) 1 << 63))
8198 specs[count++] = tmpl;
8200 else if (note == 11)
8202 if ((idesc->operands[0] == IA64_OPND_P1
8203 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
8204 || (idesc->operands[1] == IA64_OPND_P2
8205 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
8207 specs[count++] = tmpl;
8210 else if (note == 12)
8212 if (CURR_SLOT.qp_regno == 63)
8214 specs[count++] = tmpl;
8221 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8222 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8223 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
8224 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
8227 && (idesc->operands[0] == IA64_OPND_P1
8228 || idesc->operands[0] == IA64_OPND_P2))
8230 specs[count] = tmpl;
8231 specs[count++].cmp_type =
8232 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
8235 && (idesc->operands[1] == IA64_OPND_P1
8236 || idesc->operands[1] == IA64_OPND_P2))
8238 specs[count] = tmpl;
8239 specs[count++].cmp_type =
8240 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
8245 if (CURR_SLOT.qp_regno == 63)
8247 specs[count++] = tmpl;
8258 /* FIXME we can identify some individual RSE written resources, but RSE
8259 read resources have not yet been completely identified, so for now
8260 treat RSE as a single resource */
8261 if (strncmp (idesc->name, "mov", 3) == 0)
8265 if (idesc->operands[0] == IA64_OPND_AR3
8266 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
8268 specs[count] = tmpl;
8269 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8274 if (idesc->operands[0] == IA64_OPND_AR3)
8276 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
8277 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
8279 specs[count++] = tmpl;
8282 else if (idesc->operands[1] == IA64_OPND_AR3)
8284 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
8285 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
8286 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
8288 specs[count++] = tmpl;
8295 specs[count++] = tmpl;
8300 /* FIXME -- do any of these need to be non-specific? */
8301 specs[count++] = tmpl;
8305 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
8312 /* Clear branch flags on marked resources. This breaks the link between the
8313 QP of the marking instruction and a subsequent branch on the same QP. */
8316 clear_qp_branch_flag (mask)
8320 for (i = 0; i < regdepslen; i++)
8322 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
8323 if ((bit & mask) != 0)
8325 regdeps[i].link_to_qp_branch = 0;
8330 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8332 Any changes to a PR clears the mutex relations which include that PR. */
8335 clear_qp_mutex (mask)
8341 while (i < qp_mutexeslen)
8343 if ((qp_mutexes[i].prmask & mask) != 0)
8347 fprintf (stderr, " Clearing mutex relation");
8348 print_prmask (qp_mutexes[i].prmask);
8349 fprintf (stderr, "\n");
8351 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
8358 /* Clear implies relations which contain PRs in the given masks.
8359 P1_MASK indicates the source of the implies relation, while P2_MASK
8360 indicates the implied PR. */
8363 clear_qp_implies (p1_mask, p2_mask)
8370 while (i < qp_implieslen)
8372 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
8373 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
8376 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
8377 qp_implies[i].p1, qp_implies[i].p2);
8378 qp_implies[i] = qp_implies[--qp_implieslen];
8385 /* Add the PRs specified to the list of implied relations. */
8388 add_qp_imply (p1, p2)
8395 /* p0 is not meaningful here. */
8396 if (p1 == 0 || p2 == 0)
8402 /* If it exists already, ignore it. */
8403 for (i = 0; i < qp_implieslen; i++)
8405 if (qp_implies[i].p1 == p1
8406 && qp_implies[i].p2 == p2
8407 && qp_implies[i].path == md.path
8408 && !qp_implies[i].p2_branched)
8412 if (qp_implieslen == qp_impliestotlen)
8414 qp_impliestotlen += 20;
8415 qp_implies = (struct qp_imply *)
8416 xrealloc ((void *) qp_implies,
8417 qp_impliestotlen * sizeof (struct qp_imply));
8420 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
8421 qp_implies[qp_implieslen].p1 = p1;
8422 qp_implies[qp_implieslen].p2 = p2;
8423 qp_implies[qp_implieslen].path = md.path;
8424 qp_implies[qp_implieslen++].p2_branched = 0;
8426 /* Add in the implied transitive relations; for everything that p2 implies,
8427 make p1 imply that, too; for everything that implies p1, make it imply p2
8429 for (i = 0; i < qp_implieslen; i++)
8431 if (qp_implies[i].p1 == p2)
8432 add_qp_imply (p1, qp_implies[i].p2);
8433 if (qp_implies[i].p2 == p1)
8434 add_qp_imply (qp_implies[i].p1, p2);
8436 /* Add in mutex relations implied by this implies relation; for each mutex
8437 relation containing p2, duplicate it and replace p2 with p1. */
8438 bit = (valueT) 1 << p1;
8439 mask = (valueT) 1 << p2;
8440 for (i = 0; i < qp_mutexeslen; i++)
8442 if (qp_mutexes[i].prmask & mask)
8443 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
8447 /* Add the PRs specified in the mask to the mutex list; this means that only
8448 one of the PRs can be true at any time. PR0 should never be included in
8458 if (qp_mutexeslen == qp_mutexestotlen)
8460 qp_mutexestotlen += 20;
8461 qp_mutexes = (struct qpmutex *)
8462 xrealloc ((void *) qp_mutexes,
8463 qp_mutexestotlen * sizeof (struct qpmutex));
8467 fprintf (stderr, " Registering mutex on");
8468 print_prmask (mask);
8469 fprintf (stderr, "\n");
8471 qp_mutexes[qp_mutexeslen].path = md.path;
8472 qp_mutexes[qp_mutexeslen++].prmask = mask;
8476 clear_register_values ()
8480 fprintf (stderr, " Clearing register values\n");
8481 for (i = 1; i < NELEMS (gr_values); i++)
8482 gr_values[i].known = 0;
8485 /* Keep track of register values/changes which affect DV tracking.
8487 optimization note: should add a flag to classes of insns where otherwise we
8488 have to examine a group of strings to identify them. */
8491 note_register_values (idesc)
8492 struct ia64_opcode *idesc;
8494 valueT qp_changemask = 0;
8497 /* Invalidate values for registers being written to. */
8498 for (i = 0; i < idesc->num_outputs; i++)
8500 if (idesc->operands[i] == IA64_OPND_R1
8501 || idesc->operands[i] == IA64_OPND_R2
8502 || idesc->operands[i] == IA64_OPND_R3)
8504 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8505 if (regno > 0 && regno < NELEMS (gr_values))
8506 gr_values[regno].known = 0;
8508 else if (idesc->operands[i] == IA64_OPND_R3_2)
8510 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8511 if (regno > 0 && regno < 4)
8512 gr_values[regno].known = 0;
8514 else if (idesc->operands[i] == IA64_OPND_P1
8515 || idesc->operands[i] == IA64_OPND_P2)
8517 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
8518 qp_changemask |= (valueT) 1 << regno;
8520 else if (idesc->operands[i] == IA64_OPND_PR)
8522 if (idesc->operands[2] & (valueT) 0x10000)
8523 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
8525 qp_changemask = idesc->operands[2];
8528 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
8530 if (idesc->operands[1] & ((valueT) 1 << 43))
8531 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
8533 qp_changemask = idesc->operands[1];
8534 qp_changemask &= ~(valueT) 0xFFFF;
8539 /* Always clear qp branch flags on any PR change. */
8540 /* FIXME there may be exceptions for certain compares. */
8541 clear_qp_branch_flag (qp_changemask);
8543 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8544 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
8546 qp_changemask |= ~(valueT) 0xFFFF;
8547 if (strcmp (idesc->name, "clrrrb.pr") != 0)
8549 for (i = 32; i < 32 + md.rot.num_regs; i++)
8550 gr_values[i].known = 0;
8552 clear_qp_mutex (qp_changemask);
8553 clear_qp_implies (qp_changemask, qp_changemask);
8555 /* After a call, all register values are undefined, except those marked
8557 else if (strncmp (idesc->name, "br.call", 6) == 0
8558 || strncmp (idesc->name, "brl.call", 7) == 0)
8560 /* FIXME keep GR values which are marked as "safe_across_calls" */
8561 clear_register_values ();
8562 clear_qp_mutex (~qp_safe_across_calls);
8563 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
8564 clear_qp_branch_flag (~qp_safe_across_calls);
8566 else if (is_interruption_or_rfi (idesc)
8567 || is_taken_branch (idesc))
8569 clear_register_values ();
8570 clear_qp_mutex (~(valueT) 0);
8571 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
8573 /* Look for mutex and implies relations. */
8574 else if ((idesc->operands[0] == IA64_OPND_P1
8575 || idesc->operands[0] == IA64_OPND_P2)
8576 && (idesc->operands[1] == IA64_OPND_P1
8577 || idesc->operands[1] == IA64_OPND_P2))
8579 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8580 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8581 valueT p1mask = (valueT) 1 << p1;
8582 valueT p2mask = (valueT) 1 << p2;
8584 /* If one of the PRs is PR0, we can't really do anything. */
8585 if (p1 == 0 || p2 == 0)
8588 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
8590 /* In general, clear mutexes and implies which include P1 or P2,
8591 with the following exceptions. */
8592 else if (strstr (idesc->name, ".or.andcm") != NULL)
8594 add_qp_mutex (p1mask | p2mask);
8595 clear_qp_implies (p2mask, p1mask);
8597 else if (strstr (idesc->name, ".and.orcm") != NULL)
8599 add_qp_mutex (p1mask | p2mask);
8600 clear_qp_implies (p1mask, p2mask);
8602 else if (strstr (idesc->name, ".and") != NULL)
8604 clear_qp_implies (0, p1mask | p2mask);
8606 else if (strstr (idesc->name, ".or") != NULL)
8608 clear_qp_mutex (p1mask | p2mask);
8609 clear_qp_implies (p1mask | p2mask, 0);
8613 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
8614 if (strstr (idesc->name, ".unc") != NULL)
8616 add_qp_mutex (p1mask | p2mask);
8617 if (CURR_SLOT.qp_regno != 0)
8619 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
8620 CURR_SLOT.qp_regno);
8621 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
8622 CURR_SLOT.qp_regno);
8625 else if (CURR_SLOT.qp_regno == 0)
8627 add_qp_mutex (p1mask | p2mask);
8631 clear_qp_mutex (p1mask | p2mask);
8635 /* Look for mov imm insns into GRs. */
8636 else if (idesc->operands[0] == IA64_OPND_R1
8637 && (idesc->operands[1] == IA64_OPND_IMM22
8638 || idesc->operands[1] == IA64_OPND_IMMU64)
8639 && (strcmp (idesc->name, "mov") == 0
8640 || strcmp (idesc->name, "movl") == 0))
8642 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
8643 if (regno > 0 && regno < NELEMS (gr_values))
8645 gr_values[regno].known = 1;
8646 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
8647 gr_values[regno].path = md.path;
8650 fprintf (stderr, " Know gr%d = ", regno);
8651 fprintf_vma (stderr, gr_values[regno].value);
8652 fputs ("\n", stderr);
8658 clear_qp_mutex (qp_changemask);
8659 clear_qp_implies (qp_changemask, qp_changemask);
8663 /* Return whether the given predicate registers are currently mutex. */
8666 qp_mutex (p1, p2, path)
8676 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
8677 for (i = 0; i < qp_mutexeslen; i++)
8679 if (qp_mutexes[i].path >= path
8680 && (qp_mutexes[i].prmask & mask) == mask)
8687 /* Return whether the given resource is in the given insn's list of chks
8688 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8692 resources_match (rs, idesc, note, qp_regno, path)
8694 struct ia64_opcode *idesc;
8699 struct rsrc specs[MAX_SPECS];
8702 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8703 we don't need to check. One exception is note 11, which indicates that
8704 target predicates are written regardless of PR[qp]. */
8705 if (qp_mutex (rs->qp_regno, qp_regno, path)
8709 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
8712 /* UNAT checking is a bit more specific than other resources */
8713 if (rs->dependency->specifier == IA64_RS_AR_UNAT
8714 && specs[count].mem_offset.hint
8715 && rs->mem_offset.hint)
8717 if (rs->mem_offset.base == specs[count].mem_offset.base)
8719 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
8720 ((specs[count].mem_offset.offset >> 3) & 0x3F))
8727 /* Skip apparent PR write conflicts where both writes are an AND or both
8728 writes are an OR. */
8729 if (rs->dependency->specifier == IA64_RS_PR
8730 || rs->dependency->specifier == IA64_RS_PRr
8731 || rs->dependency->specifier == IA64_RS_PR63)
8733 if (specs[count].cmp_type != CMP_NONE
8734 && specs[count].cmp_type == rs->cmp_type)
8737 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
8738 dv_mode[rs->dependency->mode],
8739 rs->dependency->specifier != IA64_RS_PR63 ?
8740 specs[count].index : 63);
8745 " %s on parallel compare conflict %s vs %s on PR%d\n",
8746 dv_mode[rs->dependency->mode],
8747 dv_cmp_type[rs->cmp_type],
8748 dv_cmp_type[specs[count].cmp_type],
8749 rs->dependency->specifier != IA64_RS_PR63 ?
8750 specs[count].index : 63);
8754 /* If either resource is not specific, conservatively assume a conflict
8756 if (!specs[count].specific || !rs->specific)
8758 else if (specs[count].index == rs->index)
8763 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
8769 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8770 insert a stop to create the break. Update all resource dependencies
8771 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8772 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8773 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8777 insn_group_break (insert_stop, qp_regno, save_current)
8784 if (insert_stop && md.num_slots_in_use > 0)
8785 PREV_SLOT.end_of_insn_group = 1;
8789 fprintf (stderr, " Insn group break%s",
8790 (insert_stop ? " (w/stop)" : ""));
8792 fprintf (stderr, " effective for QP=%d", qp_regno);
8793 fprintf (stderr, "\n");
8797 while (i < regdepslen)
8799 const struct ia64_dependency *dep = regdeps[i].dependency;
8802 && regdeps[i].qp_regno != qp_regno)
8809 && CURR_SLOT.src_file == regdeps[i].file
8810 && CURR_SLOT.src_line == regdeps[i].line)
8816 /* clear dependencies which are automatically cleared by a stop, or
8817 those that have reached the appropriate state of insn serialization */
8818 if (dep->semantics == IA64_DVS_IMPLIED
8819 || dep->semantics == IA64_DVS_IMPLIEDF
8820 || regdeps[i].insn_srlz == STATE_SRLZ)
8822 print_dependency ("Removing", i);
8823 regdeps[i] = regdeps[--regdepslen];
8827 if (dep->semantics == IA64_DVS_DATA
8828 || dep->semantics == IA64_DVS_INSTR
8829 || dep->semantics == IA64_DVS_SPECIFIC)
8831 if (regdeps[i].insn_srlz == STATE_NONE)
8832 regdeps[i].insn_srlz = STATE_STOP;
8833 if (regdeps[i].data_srlz == STATE_NONE)
8834 regdeps[i].data_srlz = STATE_STOP;
8841 /* Add the given resource usage spec to the list of active dependencies. */
8844 mark_resource (idesc, dep, spec, depind, path)
8845 struct ia64_opcode *idesc ATTRIBUTE_UNUSED;
8846 const struct ia64_dependency *dep ATTRIBUTE_UNUSED;
8851 if (regdepslen == regdepstotlen)
8853 regdepstotlen += 20;
8854 regdeps = (struct rsrc *)
8855 xrealloc ((void *) regdeps,
8856 regdepstotlen * sizeof (struct rsrc));
8859 regdeps[regdepslen] = *spec;
8860 regdeps[regdepslen].depind = depind;
8861 regdeps[regdepslen].path = path;
8862 regdeps[regdepslen].file = CURR_SLOT.src_file;
8863 regdeps[regdepslen].line = CURR_SLOT.src_line;
8865 print_dependency ("Adding", regdepslen);
8871 print_dependency (action, depind)
8877 fprintf (stderr, " %s %s '%s'",
8878 action, dv_mode[(regdeps[depind].dependency)->mode],
8879 (regdeps[depind].dependency)->name);
8880 if (regdeps[depind].specific && regdeps[depind].index != 0)
8881 fprintf (stderr, " (%d)", regdeps[depind].index);
8882 if (regdeps[depind].mem_offset.hint)
8884 fputs (" ", stderr);
8885 fprintf_vma (stderr, regdeps[depind].mem_offset.base);
8886 fputs ("+", stderr);
8887 fprintf_vma (stderr, regdeps[depind].mem_offset.offset);
8889 fprintf (stderr, "\n");
8894 instruction_serialization ()
8898 fprintf (stderr, " Instruction serialization\n");
8899 for (i = 0; i < regdepslen; i++)
8900 if (regdeps[i].insn_srlz == STATE_STOP)
8901 regdeps[i].insn_srlz = STATE_SRLZ;
8905 data_serialization ()
8909 fprintf (stderr, " Data serialization\n");
8910 while (i < regdepslen)
8912 if (regdeps[i].data_srlz == STATE_STOP
8913 /* Note: as of 991210, all "other" dependencies are cleared by a
8914 data serialization. This might change with new tables */
8915 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
8917 print_dependency ("Removing", i);
8918 regdeps[i] = regdeps[--regdepslen];
8925 /* Insert stops and serializations as needed to avoid DVs. */
8928 remove_marked_resource (rs)
8931 switch (rs->dependency->semantics)
8933 case IA64_DVS_SPECIFIC:
8935 fprintf (stderr, "Implementation-specific, assume worst case...\n");
8936 /* ...fall through... */
8937 case IA64_DVS_INSTR:
8939 fprintf (stderr, "Inserting instr serialization\n");
8940 if (rs->insn_srlz < STATE_STOP)
8941 insn_group_break (1, 0, 0);
8942 if (rs->insn_srlz < STATE_SRLZ)
8944 int oldqp = CURR_SLOT.qp_regno;
8945 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8946 /* Manually jam a srlz.i insn into the stream */
8947 CURR_SLOT.qp_regno = 0;
8948 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
8949 instruction_serialization ();
8950 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8951 if (++md.num_slots_in_use >= NUM_SLOTS)
8953 CURR_SLOT.qp_regno = oldqp;
8954 CURR_SLOT.idesc = oldidesc;
8956 insn_group_break (1, 0, 0);
8958 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
8959 "other" types of DV are eliminated
8960 by a data serialization */
8963 fprintf (stderr, "Inserting data serialization\n");
8964 if (rs->data_srlz < STATE_STOP)
8965 insn_group_break (1, 0, 0);
8967 int oldqp = CURR_SLOT.qp_regno;
8968 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8969 /* Manually jam a srlz.d insn into the stream */
8970 CURR_SLOT.qp_regno = 0;
8971 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
8972 data_serialization ();
8973 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8974 if (++md.num_slots_in_use >= NUM_SLOTS)
8976 CURR_SLOT.qp_regno = oldqp;
8977 CURR_SLOT.idesc = oldidesc;
8980 case IA64_DVS_IMPLIED:
8981 case IA64_DVS_IMPLIEDF:
8983 fprintf (stderr, "Inserting stop\n");
8984 insn_group_break (1, 0, 0);
8991 /* Check the resources used by the given opcode against the current dependency
8994 The check is run once for each execution path encountered. In this case,
8995 a unique execution path is the sequence of instructions following a code
8996 entry point, e.g. the following has three execution paths, one starting
8997 at L0, one at L1, and one at L2.
9006 check_dependencies (idesc)
9007 struct ia64_opcode *idesc;
9009 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9013 /* Note that the number of marked resources may change within the
9014 loop if in auto mode. */
9016 while (i < regdepslen)
9018 struct rsrc *rs = ®deps[i];
9019 const struct ia64_dependency *dep = rs->dependency;
9024 if (dep->semantics == IA64_DVS_NONE
9025 || (chkind = depends_on (rs->depind, idesc)) == -1)
9031 note = NOTE (opdeps->chks[chkind]);
9033 /* Check this resource against each execution path seen thus far. */
9034 for (path = 0; path <= md.path; path++)
9038 /* If the dependency wasn't on the path being checked, ignore it. */
9039 if (rs->path < path)
9042 /* If the QP for this insn implies a QP which has branched, don't
9043 bother checking. Ed. NOTE: I don't think this check is terribly
9044 useful; what's the point of generating code which will only be
9045 reached if its QP is zero?
9046 This code was specifically inserted to handle the following code,
9047 based on notes from Intel's DV checking code, where p1 implies p2.
9053 if (CURR_SLOT.qp_regno != 0)
9057 for (implies = 0; implies < qp_implieslen; implies++)
9059 if (qp_implies[implies].path >= path
9060 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
9061 && qp_implies[implies].p2_branched)
9071 if ((matchtype = resources_match (rs, idesc, note,
9072 CURR_SLOT.qp_regno, path)) != 0)
9075 char pathmsg[256] = "";
9076 char indexmsg[256] = "";
9077 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
9080 sprintf (pathmsg, " when entry is at label '%s'",
9081 md.entry_labels[path - 1]);
9082 if (rs->specific && rs->index != 0)
9083 sprintf (indexmsg, ", specific resource number is %d",
9085 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9087 (certain ? "violates" : "may violate"),
9088 dv_mode[dep->mode], dep->name,
9089 dv_sem[dep->semantics],
9092 if (md.explicit_mode)
9094 as_warn ("%s", msg);
9096 as_warn (_("Only the first path encountering the conflict "
9098 as_warn_where (rs->file, rs->line,
9099 _("This is the location of the "
9100 "conflicting usage"));
9101 /* Don't bother checking other paths, to avoid duplicating
9108 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
9110 remove_marked_resource (rs);
9112 /* since the set of dependencies has changed, start over */
9113 /* FIXME -- since we're removing dvs as we go, we
9114 probably don't really need to start over... */
9127 /* Register new dependencies based on the given opcode. */
9130 mark_resources (idesc)
9131 struct ia64_opcode *idesc;
9134 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
9135 int add_only_qp_reads = 0;
9137 /* A conditional branch only uses its resources if it is taken; if it is
9138 taken, we stop following that path. The other branch types effectively
9139 *always* write their resources. If it's not taken, register only QP
9141 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
9143 add_only_qp_reads = 1;
9147 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
9149 for (i = 0; i < opdeps->nregs; i++)
9151 const struct ia64_dependency *dep;
9152 struct rsrc specs[MAX_SPECS];
9157 dep = ia64_find_dependency (opdeps->regs[i]);
9158 note = NOTE (opdeps->regs[i]);
9160 if (add_only_qp_reads
9161 && !(dep->mode == IA64_DV_WAR
9162 && (dep->specifier == IA64_RS_PR
9163 || dep->specifier == IA64_RS_PRr
9164 || dep->specifier == IA64_RS_PR63)))
9167 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
9170 if (md.debug_dv && !count)
9171 fprintf (stderr, " No %s %s usage found (path %d)\n",
9172 dv_mode[dep->mode], dep->name, md.path);
9177 mark_resource (idesc, dep, &specs[count],
9178 DEP (opdeps->regs[i]), md.path);
9181 /* The execution path may affect register values, which may in turn
9182 affect which indirect-access resources are accessed. */
9183 switch (dep->specifier)
9195 for (path = 0; path < md.path; path++)
9197 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
9199 mark_resource (idesc, dep, &specs[count],
9200 DEP (opdeps->regs[i]), path);
9207 /* Remove dependencies when they no longer apply. */
9210 update_dependencies (idesc)
9211 struct ia64_opcode *idesc;
9215 if (strcmp (idesc->name, "srlz.i") == 0)
9217 instruction_serialization ();
9219 else if (strcmp (idesc->name, "srlz.d") == 0)
9221 data_serialization ();
9223 else if (is_interruption_or_rfi (idesc)
9224 || is_taken_branch (idesc))
9226 /* Although technically the taken branch doesn't clear dependencies
9227 which require a srlz.[id], we don't follow the branch; the next
9228 instruction is assumed to start with a clean slate. */
9232 else if (is_conditional_branch (idesc)
9233 && CURR_SLOT.qp_regno != 0)
9235 int is_call = strstr (idesc->name, ".call") != NULL;
9237 for (i = 0; i < qp_implieslen; i++)
9239 /* If the conditional branch's predicate is implied by the predicate
9240 in an existing dependency, remove that dependency. */
9241 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
9244 /* Note that this implied predicate takes a branch so that if
9245 a later insn generates a DV but its predicate implies this
9246 one, we can avoid the false DV warning. */
9247 qp_implies[i].p2_branched = 1;
9248 while (depind < regdepslen)
9250 if (regdeps[depind].qp_regno == qp_implies[i].p1)
9252 print_dependency ("Removing", depind);
9253 regdeps[depind] = regdeps[--regdepslen];
9260 /* Any marked resources which have this same predicate should be
9261 cleared, provided that the QP hasn't been modified between the
9262 marking instruction and the branch. */
9265 insn_group_break (0, CURR_SLOT.qp_regno, 1);
9270 while (i < regdepslen)
9272 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
9273 && regdeps[i].link_to_qp_branch
9274 && (regdeps[i].file != CURR_SLOT.src_file
9275 || regdeps[i].line != CURR_SLOT.src_line))
9277 /* Treat like a taken branch */
9278 print_dependency ("Removing", i);
9279 regdeps[i] = regdeps[--regdepslen];
9288 /* Examine the current instruction for dependency violations. */
9292 struct ia64_opcode *idesc;
9296 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
9297 idesc->name, CURR_SLOT.src_line,
9298 idesc->dependencies->nchks,
9299 idesc->dependencies->nregs);
9302 /* Look through the list of currently marked resources; if the current
9303 instruction has the dependency in its chks list which uses that resource,
9304 check against the specific resources used. */
9305 check_dependencies (idesc);
9307 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9308 then add them to the list of marked resources. */
9309 mark_resources (idesc);
9311 /* There are several types of dependency semantics, and each has its own
9312 requirements for being cleared
9314 Instruction serialization (insns separated by interruption, rfi, or
9315 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9317 Data serialization (instruction serialization, or writer + srlz.d +
9318 reader, where writer and srlz.d are in separate groups) clears
9319 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9320 always be the case).
9322 Instruction group break (groups separated by stop, taken branch,
9323 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9325 update_dependencies (idesc);
9327 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9328 warning. Keep track of as many as possible that are useful. */
9329 note_register_values (idesc);
9331 /* We don't need or want this anymore. */
9332 md.mem_offset.hint = 0;
9337 /* Translate one line of assembly. Pseudo ops and labels do not show
9343 char *saved_input_line_pointer, *mnemonic;
9344 const struct pseudo_opcode *pdesc;
9345 struct ia64_opcode *idesc;
9346 unsigned char qp_regno;
9350 saved_input_line_pointer = input_line_pointer;
9351 input_line_pointer = str;
9353 /* extract the opcode (mnemonic): */
9355 mnemonic = input_line_pointer;
9356 ch = get_symbol_end ();
9357 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
9360 *input_line_pointer = ch;
9361 (*pdesc->handler) (pdesc->arg);
9365 /* Find the instruction descriptor matching the arguments. */
9367 idesc = ia64_find_opcode (mnemonic);
9368 *input_line_pointer = ch;
9371 as_bad ("Unknown opcode `%s'", mnemonic);
9375 idesc = parse_operands (idesc);
9379 /* Handle the dynamic ops we can handle now: */
9380 if (idesc->type == IA64_TYPE_DYN)
9382 if (strcmp (idesc->name, "add") == 0)
9384 if (CURR_SLOT.opnd[2].X_op == O_register
9385 && CURR_SLOT.opnd[2].X_add_number < 4)
9389 ia64_free_opcode (idesc);
9390 idesc = ia64_find_opcode (mnemonic);
9392 know (!idesc->next);
9395 else if (strcmp (idesc->name, "mov") == 0)
9397 enum ia64_opnd opnd1, opnd2;
9400 opnd1 = idesc->operands[0];
9401 opnd2 = idesc->operands[1];
9402 if (opnd1 == IA64_OPND_AR3)
9404 else if (opnd2 == IA64_OPND_AR3)
9408 if (CURR_SLOT.opnd[rop].X_op == O_register
9409 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
9413 ia64_free_opcode (idesc);
9414 idesc = ia64_find_opcode (mnemonic);
9415 while (idesc != NULL
9416 && (idesc->operands[0] != opnd1
9417 || idesc->operands[1] != opnd2))
9418 idesc = get_next_opcode (idesc);
9423 if (md.qp.X_op == O_register)
9425 qp_regno = md.qp.X_add_number - REG_P;
9426 md.qp.X_op = O_absent;
9429 flags = idesc->flags;
9431 if ((flags & IA64_OPCODE_FIRST) != 0)
9432 insn_group_break (1, 0, 0);
9434 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
9436 as_bad ("`%s' cannot be predicated", idesc->name);
9440 /* Build the instruction. */
9441 CURR_SLOT.qp_regno = qp_regno;
9442 CURR_SLOT.idesc = idesc;
9443 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
9444 dwarf2_where (&CURR_SLOT.debug_line);
9446 /* Add unwind entry, if there is one. */
9447 if (unwind.current_entry)
9449 CURR_SLOT.unwind_record = unwind.current_entry;
9450 unwind.current_entry = NULL;
9453 /* Check for dependency violations. */
9457 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
9458 if (++md.num_slots_in_use >= NUM_SLOTS)
9461 if ((flags & IA64_OPCODE_LAST) != 0)
9462 insn_group_break (1, 0, 0);
9464 md.last_text_seg = now_seg;
9467 input_line_pointer = saved_input_line_pointer;
9470 /* Called when symbol NAME cannot be found in the symbol table.
9471 Should be used for dynamic valued symbols only. */
9474 md_undefined_symbol (name)
9475 char *name ATTRIBUTE_UNUSED;
9480 /* Called for any expression that can not be recognized. When the
9481 function is called, `input_line_pointer' will point to the start of
9488 enum pseudo_type pseudo_type;
9493 switch (*input_line_pointer)
9496 /* Find what relocation pseudo-function we're dealing with. */
9498 ch = *++input_line_pointer;
9499 for (i = 0; i < NELEMS (pseudo_func); ++i)
9500 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
9502 len = strlen (pseudo_func[i].name);
9503 if (strncmp (pseudo_func[i].name + 1,
9504 input_line_pointer + 1, len - 1) == 0
9505 && !is_part_of_name (input_line_pointer[len]))
9507 input_line_pointer += len;
9508 pseudo_type = pseudo_func[i].type;
9512 switch (pseudo_type)
9514 case PSEUDO_FUNC_RELOC:
9516 if (*input_line_pointer != '(')
9518 as_bad ("Expected '('");
9522 ++input_line_pointer;
9524 if (*input_line_pointer++ != ')')
9526 as_bad ("Missing ')'");
9529 if (e->X_op != O_symbol)
9531 if (e->X_op != O_pseudo_fixup)
9533 as_bad ("Not a symbolic expression");
9536 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
9537 && i == FUNC_LT_RELATIVE)
9538 i = FUNC_LT_FPTR_RELATIVE;
9541 as_bad ("Illegal combination of relocation functions");
9545 /* Make sure gas doesn't get rid of local symbols that are used
9547 e->X_op = O_pseudo_fixup;
9548 e->X_op_symbol = pseudo_func[i].u.sym;
9551 case PSEUDO_FUNC_CONST:
9552 e->X_op = O_constant;
9553 e->X_add_number = pseudo_func[i].u.ival;
9556 case PSEUDO_FUNC_REG:
9557 e->X_op = O_register;
9558 e->X_add_number = pseudo_func[i].u.ival;
9562 name = input_line_pointer - 1;
9564 as_bad ("Unknown pseudo function `%s'", name);
9570 ++input_line_pointer;
9572 if (*input_line_pointer != ']')
9574 as_bad ("Closing bracket misssing");
9579 if (e->X_op != O_register)
9580 as_bad ("Register expected as index");
9582 ++input_line_pointer;
9593 ignore_rest_of_line ();
9596 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9597 a section symbol plus some offset. For relocs involving @fptr(),
9598 directives we don't want such adjustments since we need to have the
9599 original symbol's name in the reloc. */
9601 ia64_fix_adjustable (fix)
9604 /* Prevent all adjustments to global symbols */
9605 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
9608 switch (fix->fx_r_type)
9610 case BFD_RELOC_IA64_FPTR64I:
9611 case BFD_RELOC_IA64_FPTR32MSB:
9612 case BFD_RELOC_IA64_FPTR32LSB:
9613 case BFD_RELOC_IA64_FPTR64MSB:
9614 case BFD_RELOC_IA64_FPTR64LSB:
9615 case BFD_RELOC_IA64_LTOFF_FPTR22:
9616 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9626 ia64_force_relocation (fix)
9629 switch (fix->fx_r_type)
9631 case BFD_RELOC_IA64_FPTR64I:
9632 case BFD_RELOC_IA64_FPTR32MSB:
9633 case BFD_RELOC_IA64_FPTR32LSB:
9634 case BFD_RELOC_IA64_FPTR64MSB:
9635 case BFD_RELOC_IA64_FPTR64LSB:
9637 case BFD_RELOC_IA64_LTOFF22:
9638 case BFD_RELOC_IA64_LTOFF64I:
9639 case BFD_RELOC_IA64_LTOFF_FPTR22:
9640 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9641 case BFD_RELOC_IA64_PLTOFF22:
9642 case BFD_RELOC_IA64_PLTOFF64I:
9643 case BFD_RELOC_IA64_PLTOFF64MSB:
9644 case BFD_RELOC_IA64_PLTOFF64LSB:
9653 /* Decide from what point a pc-relative relocation is relative to,
9654 relative to the pc-relative fixup. Er, relatively speaking. */
9656 ia64_pcrel_from_section (fix, sec)
9660 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
9662 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
9668 /* This is called whenever some data item (not an instruction) needs a
9669 fixup. We pick the right reloc code depending on the byteorder
9670 currently in effect. */
9672 ia64_cons_fix_new (f, where, nbytes, exp)
9678 bfd_reloc_code_real_type code;
9683 /* There are no reloc for 8 and 16 bit quantities, but we allow
9684 them here since they will work fine as long as the expression
9685 is fully defined at the end of the pass over the source file. */
9686 case 1: code = BFD_RELOC_8; break;
9687 case 2: code = BFD_RELOC_16; break;
9689 if (target_big_endian)
9690 code = BFD_RELOC_IA64_DIR32MSB;
9692 code = BFD_RELOC_IA64_DIR32LSB;
9696 if (target_big_endian)
9697 code = BFD_RELOC_IA64_DIR64MSB;
9699 code = BFD_RELOC_IA64_DIR64LSB;
9703 as_bad ("Unsupported fixup size %d", nbytes);
9704 ignore_rest_of_line ();
9707 if (exp->X_op == O_pseudo_fixup)
9710 exp->X_op = O_symbol;
9711 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
9713 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
9714 /* We need to store the byte order in effect in case we're going
9715 to fix an 8 or 16 bit relocation (for which there no real
9716 relocs available). See md_apply_fix(). */
9717 fix->tc_fix_data.bigendian = target_big_endian;
9720 /* Return the actual relocation we wish to associate with the pseudo
9721 reloc described by SYM and R_TYPE. SYM should be one of the
9722 symbols in the pseudo_func array, or NULL. */
9724 static bfd_reloc_code_real_type
9725 ia64_gen_real_reloc_type (sym, r_type)
9727 bfd_reloc_code_real_type r_type;
9729 bfd_reloc_code_real_type new = 0;
9736 switch (S_GET_VALUE (sym))
9738 case FUNC_FPTR_RELATIVE:
9741 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
9742 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
9743 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
9744 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
9745 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
9750 case FUNC_GP_RELATIVE:
9753 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
9754 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
9755 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
9756 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
9757 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
9758 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
9763 case FUNC_LT_RELATIVE:
9766 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
9767 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
9772 case FUNC_PC_RELATIVE:
9775 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
9776 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
9777 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
9778 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
9779 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
9780 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
9785 case FUNC_PLT_RELATIVE:
9788 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
9789 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
9790 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
9791 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
9796 case FUNC_SEC_RELATIVE:
9799 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
9800 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
9801 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
9802 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
9807 case FUNC_SEG_RELATIVE:
9810 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
9811 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
9812 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
9813 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
9818 case FUNC_LTV_RELATIVE:
9821 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
9822 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
9823 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
9824 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
9829 case FUNC_LT_FPTR_RELATIVE:
9832 case BFD_RELOC_IA64_IMM22:
9833 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
9834 case BFD_RELOC_IA64_IMM64:
9835 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
9843 /* Hmmmm. Should this ever occur? */
9850 /* Here is where generate the appropriate reloc for pseudo relocation
9853 ia64_validate_fix (fix)
9856 switch (fix->fx_r_type)
9858 case BFD_RELOC_IA64_FPTR64I:
9859 case BFD_RELOC_IA64_FPTR32MSB:
9860 case BFD_RELOC_IA64_FPTR64LSB:
9861 case BFD_RELOC_IA64_LTOFF_FPTR22:
9862 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9863 if (fix->fx_offset != 0)
9864 as_bad_where (fix->fx_file, fix->fx_line,
9865 "No addend allowed in @fptr() relocation");
9875 fix_insn (fix, odesc, value)
9877 const struct ia64_operand *odesc;
9880 bfd_vma insn[3], t0, t1, control_bits;
9885 slot = fix->fx_where & 0x3;
9886 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9888 /* Bundles are always in little-endian byte order */
9889 t0 = bfd_getl64 (fixpos);
9890 t1 = bfd_getl64 (fixpos + 8);
9891 control_bits = t0 & 0x1f;
9892 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9893 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9894 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9897 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
9899 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9900 insn[2] |= (((value & 0x7f) << 13)
9901 | (((value >> 7) & 0x1ff) << 27)
9902 | (((value >> 16) & 0x1f) << 22)
9903 | (((value >> 21) & 0x1) << 21)
9904 | (((value >> 63) & 0x1) << 36));
9906 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9908 if (value & ~0x3fffffffffffffffULL)
9909 err = "integer operand out of range";
9910 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9911 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9913 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9916 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
9917 insn[2] |= ((((value >> 59) & 0x1) << 36)
9918 | (((value >> 0) & 0xfffff) << 13));
9921 err = (*odesc->insert) (odesc, value, insn + slot);
9924 as_bad_where (fix->fx_file, fix->fx_line, err);
9926 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
9927 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
9928 number_to_chars_littleendian (fixpos + 0, t0, 8);
9929 number_to_chars_littleendian (fixpos + 8, t1, 8);
9932 /* Attempt to simplify or even eliminate a fixup. The return value is
9933 ignored; perhaps it was once meaningful, but now it is historical.
9934 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9936 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9939 md_apply_fix3 (fix, valuep, seg)
9942 segT seg ATTRIBUTE_UNUSED;
9945 valueT value = *valuep;
9948 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
9952 switch (fix->fx_r_type)
9954 case BFD_RELOC_IA64_DIR32MSB:
9955 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
9959 case BFD_RELOC_IA64_DIR32LSB:
9960 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
9964 case BFD_RELOC_IA64_DIR64MSB:
9965 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
9969 case BFD_RELOC_IA64_DIR64LSB:
9970 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
9980 if (fix->fx_r_type == (int) BFD_RELOC_UNUSED)
9982 /* This must be a TAG13 or TAG13b operand. There are no external
9983 relocs defined for them, so we must give an error. */
9984 as_bad_where (fix->fx_file, fix->fx_line,
9985 "%s must have a constant value",
9986 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
9991 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9992 work. There should be a better way to handle this. */
9994 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
9996 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
9998 if (fix->tc_fix_data.bigendian)
9999 number_to_chars_bigendian (fixpos, value, fix->fx_size);
10001 number_to_chars_littleendian (fixpos, value, fix->fx_size);
10007 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
10014 /* Generate the BFD reloc to be stuck in the object file from the
10015 fixup used internally in the assembler. */
10018 tc_gen_reloc (sec, fixp)
10019 asection *sec ATTRIBUTE_UNUSED;
10024 reloc = xmalloc (sizeof (*reloc));
10025 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10026 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10027 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
10028 reloc->addend = fixp->fx_offset;
10029 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
10033 as_bad_where (fixp->fx_file, fixp->fx_line,
10034 "Cannot represent %s relocation in object file",
10035 bfd_get_reloc_code_name (fixp->fx_r_type));
10040 /* Turn a string in input_line_pointer into a floating point constant
10041 of type TYPE, and store the appropriate bytes in *LIT. The number
10042 of LITTLENUMS emitted is stored in *SIZE. An error message is
10043 returned, or NULL on OK. */
10045 #define MAX_LITTLENUMS 5
10048 md_atof (type, lit, size)
10053 LITTLENUM_TYPE words[MAX_LITTLENUMS];
10054 LITTLENUM_TYPE *word;
10084 return "Bad call to MD_ATOF()";
10086 t = atof_ieee (input_line_pointer, type, words);
10088 input_line_pointer = t;
10089 *size = prec * sizeof (LITTLENUM_TYPE);
10091 for (word = words + prec - 1; prec--;)
10093 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
10094 lit += sizeof (LITTLENUM_TYPE);
10099 /* Round up a section's size to the appropriate boundary. */
10101 md_section_align (seg, size)
10105 int align = bfd_get_section_alignment (stdoutput, seg);
10106 valueT mask = ((valueT) 1 << align) - 1;
10108 return (size + mask) & ~mask;
10111 /* Handle ia64 specific semantics of the align directive. */
10114 ia64_md_do_align (n, fill, len, max)
10115 int n ATTRIBUTE_UNUSED;
10116 const char *fill ATTRIBUTE_UNUSED;
10117 int len ATTRIBUTE_UNUSED;
10118 int max ATTRIBUTE_UNUSED;
10120 if (subseg_text_p (now_seg))
10121 ia64_flush_insns ();
10124 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10125 of an rs_align_code fragment. */
10128 ia64_handle_align (fragp)
10131 /* Use mfi bundle of nops with no stop bits. */
10132 static const unsigned char be_nop[]
10133 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10134 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10135 static const unsigned char le_nop[]
10136 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10137 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10142 if (fragp->fr_type != rs_align_code)
10145 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
10146 p = fragp->fr_literal + fragp->fr_fix;
10148 /* Make sure we are on a 16-byte boundary, in case someone has been
10149 putting data into a text section. */
10152 int fix = bytes & 15;
10153 memset (p, 0, fix);
10156 fragp->fr_fix += fix;
10159 memcpy (p, (target_big_endian ? be_nop : le_nop), 16);
10160 fragp->fr_var = 16;