1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS = 0,
66 SPECIAL_SECTION_SDATA,
67 SPECIAL_SECTION_RODATA,
68 SPECIAL_SECTION_COMMENT,
69 SPECIAL_SECTION_UNWIND,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE,
89 REG_FR = (REG_GR + 128),
90 REG_AR = (REG_FR + 128),
91 REG_CR = (REG_AR + 128),
92 REG_P = (REG_CR + 128),
93 REG_BR = (REG_P + 64),
94 REG_IP = (REG_BR + 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR = 0, /* dynamic general purpose register */
122 DYNREG_FR, /* dynamic floating point register */
123 DYNREG_PR, /* dynamic predicate register */
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
133 struct label_fix *next;
137 extern int target_big_endian;
139 /* Characters which always start a comment. */
140 const char comment_chars[] = "";
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars[] = "#";
145 /* Characters which may be used to separate multiple commands on a
147 const char line_separator_chars[] = ";";
149 /* Characters which are used to indicate an exponent in a floating
151 const char EXP_CHARS[] = "eE";
153 /* Characters which mean that a number is a floating point constant,
155 const char FLT_CHARS[] = "rRsSfFdDxXpP";
157 /* ia64-specific option processing: */
159 const char *md_shortopts = "m:N:x::";
161 struct option md_longopts[] =
163 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP},
165 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC}
169 size_t md_longopts_size = sizeof (md_longopts);
173 struct hash_control *pseudo_hash; /* pseudo opcode hash table */
174 struct hash_control *reg_hash; /* register name hash table */
175 struct hash_control *dynreg_hash; /* dynamic register hash table */
176 struct hash_control *const_hash; /* constant hash table */
177 struct hash_control *entry_hash; /* code entry hint hash table */
179 symbolS *regsym[REG_NUM];
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
190 explicit_mode : 1, /* which mode we're in */
191 default_explicit_mode : 1, /* which mode is the default */
192 mode_explicitly_set : 1, /* was the current mode explicitly set? */
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
199 int num_slots_in_use;
203 end_of_insn_group : 1,
204 manual_bundling_on : 1,
205 manual_bundling_off : 1;
206 signed char user_template; /* user-selected template, if any */
207 unsigned char qp_regno; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
214 bfd_reloc_code_real_type code;
215 enum ia64_opnd opnd; /* type of operand in need of fix */
216 unsigned int is_pcrel : 1; /* is operand pc-relative? */
217 expressionS expr; /* the value to be inserted */
219 fixup[2]; /* at most two fixups per insn */
220 struct ia64_opcode *idesc;
221 struct label_fix *label_fixups;
222 struct label_fix *tag_fixups;
223 struct unw_rec_list *unwind_record; /* Unwind directive. */
226 unsigned int src_line;
227 struct dwarf2_line_info debug_line;
235 struct dynreg *next; /* next dynamic register */
237 unsigned short base; /* the base register number */
238 unsigned short num_regs; /* # of registers in this set */
240 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot;
242 flagword flags; /* ELF-header flags */
245 unsigned hint:1; /* is this hint currently valid? */
246 bfd_vma offset; /* mem.offset offset */
247 bfd_vma base; /* mem.offset base */
250 int path; /* number of alt. entry points seen */
251 const char **entry_labels; /* labels of all alternate paths in
252 the current DV-checking block. */
253 int maxpaths; /* size currently allocated for
258 /* application registers: */
264 #define AR_BSPSTORE 18
279 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
280 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
281 {"ar.rsc", 16}, {"ar.bsp", 17},
282 {"ar.bspstore", 18}, {"ar.rnat", 19},
283 {"ar.fcr", 21}, {"ar.eflag", 24},
284 {"ar.csd", 25}, {"ar.ssd", 26},
285 {"ar.cflg", 27}, {"ar.fsr", 28},
286 {"ar.fir", 29}, {"ar.fdr", 30},
287 {"ar.ccv", 32}, {"ar.unat", 36},
288 {"ar.fpsr", 40}, {"ar.itc", 44},
289 {"ar.pfs", 64}, {"ar.lc", 65},
310 /* control registers: */
352 static const struct const_desc
359 /* PSR constant masks: */
362 {"psr.be", ((valueT) 1) << 1},
363 {"psr.up", ((valueT) 1) << 2},
364 {"psr.ac", ((valueT) 1) << 3},
365 {"psr.mfl", ((valueT) 1) << 4},
366 {"psr.mfh", ((valueT) 1) << 5},
368 {"psr.ic", ((valueT) 1) << 13},
369 {"psr.i", ((valueT) 1) << 14},
370 {"psr.pk", ((valueT) 1) << 15},
372 {"psr.dt", ((valueT) 1) << 17},
373 {"psr.dfl", ((valueT) 1) << 18},
374 {"psr.dfh", ((valueT) 1) << 19},
375 {"psr.sp", ((valueT) 1) << 20},
376 {"psr.pp", ((valueT) 1) << 21},
377 {"psr.di", ((valueT) 1) << 22},
378 {"psr.si", ((valueT) 1) << 23},
379 {"psr.db", ((valueT) 1) << 24},
380 {"psr.lp", ((valueT) 1) << 25},
381 {"psr.tb", ((valueT) 1) << 26},
382 {"psr.rt", ((valueT) 1) << 27},
383 /* 28-31: reserved */
384 /* 32-33: cpl (current privilege level) */
385 {"psr.is", ((valueT) 1) << 34},
386 {"psr.mc", ((valueT) 1) << 35},
387 {"psr.it", ((valueT) 1) << 36},
388 {"psr.id", ((valueT) 1) << 37},
389 {"psr.da", ((valueT) 1) << 38},
390 {"psr.dd", ((valueT) 1) << 39},
391 {"psr.ss", ((valueT) 1) << 40},
392 /* 41-42: ri (restart instruction) */
393 {"psr.ed", ((valueT) 1) << 43},
394 {"psr.bn", ((valueT) 1) << 44},
397 /* indirect register-sets/memory: */
406 { "CPUID", IND_CPUID },
407 { "cpuid", IND_CPUID },
419 /* Pseudo functions used to indicate relocation types (these functions
420 start with an at sign (@). */
442 /* reloc pseudo functions (these must come first!): */
443 { "fptr", PSEUDO_FUNC_RELOC },
444 { "gprel", PSEUDO_FUNC_RELOC },
445 { "ltoff", PSEUDO_FUNC_RELOC },
446 { "pcrel", PSEUDO_FUNC_RELOC },
447 { "pltoff", PSEUDO_FUNC_RELOC },
448 { "secrel", PSEUDO_FUNC_RELOC },
449 { "segrel", PSEUDO_FUNC_RELOC },
450 { "ltv", PSEUDO_FUNC_RELOC },
451 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
453 /* mbtype4 constants: */
454 { "alt", PSEUDO_FUNC_CONST, { 0xa } },
455 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } },
456 { "mix", PSEUDO_FUNC_CONST, { 0x8 } },
457 { "rev", PSEUDO_FUNC_CONST, { 0xb } },
458 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } },
460 /* fclass constants: */
461 { "nat", PSEUDO_FUNC_CONST, { 0x100 } },
462 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } },
463 { "snan", PSEUDO_FUNC_CONST, { 0x040 } },
464 { "pos", PSEUDO_FUNC_CONST, { 0x001 } },
465 { "neg", PSEUDO_FUNC_CONST, { 0x002 } },
466 { "zero", PSEUDO_FUNC_CONST, { 0x004 } },
467 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } },
468 { "norm", PSEUDO_FUNC_CONST, { 0x010 } },
469 { "inf", PSEUDO_FUNC_CONST, { 0x020 } },
471 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
473 /* unwind-related constants: */
474 { "svr4", PSEUDO_FUNC_CONST, { 0 } },
475 { "hpux", PSEUDO_FUNC_CONST, { 1 } },
476 { "nt", PSEUDO_FUNC_CONST, { 2 } },
478 /* unwind-related registers: */
479 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } }
482 /* 41-bit nop opcodes (one per unit): */
483 static const bfd_vma nop[IA64_NUM_UNITS] =
485 0x0000000000LL, /* NIL => break 0 */
486 0x0008000000LL, /* I-unit nop */
487 0x0008000000LL, /* M-unit nop */
488 0x4000000000LL, /* B-unit nop */
489 0x0008000000LL, /* F-unit nop */
490 0x0008000000LL, /* L-"unit" nop */
491 0x0008000000LL, /* X-unit nop */
494 /* Can't be `const' as it's passed to input routines (which have the
495 habit of setting temporary sentinels. */
496 static char special_section_name[][20] =
498 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
499 {".IA_64.unwind"}, {".IA_64.unwind_info"}
502 /* The best template for a particular sequence of up to three
504 #define N IA64_NUM_TYPES
505 static unsigned char best_template[N][N][N];
508 /* Resource dependencies currently in effect */
510 int depind; /* dependency index */
511 const struct ia64_dependency *dependency; /* actual dependency */
512 unsigned specific:1, /* is this a specific bit/regno? */
513 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/
514 int index; /* specific regno/bit within dependency */
515 int note; /* optional qualifying note (0 if none) */
519 int insn_srlz; /* current insn serialization state */
520 int data_srlz; /* current data serialization state */
521 int qp_regno; /* qualifying predicate for this usage */
522 char *file; /* what file marked this dependency */
523 int line; /* what line marked this dependency */
524 struct mem_offset mem_offset; /* optional memory offset hint */
525 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */
526 int path; /* corresponding code entry index */
528 static int regdepslen = 0;
529 static int regdepstotlen = 0;
530 static const char *dv_mode[] = { "RAW", "WAW", "WAR" };
531 static const char *dv_sem[] = { "none", "implied", "impliedf",
532 "data", "instr", "specific", "stop", "other" };
533 static const char *dv_cmp_type[] = { "none", "OR", "AND" };
535 /* Current state of PR mutexation */
536 static struct qpmutex {
539 } *qp_mutexes = NULL; /* QP mutex bitmasks */
540 static int qp_mutexeslen = 0;
541 static int qp_mutexestotlen = 0;
542 static valueT qp_safe_across_calls = 0;
544 /* Current state of PR implications */
545 static struct qp_imply {
548 unsigned p2_branched:1;
550 } *qp_implies = NULL;
551 static int qp_implieslen = 0;
552 static int qp_impliestotlen = 0;
554 /* Keep track of static GR values so that indirect register usage can
555 sometimes be tracked. */
560 } gr_values[128] = {{ 1, 0 }};
562 /* These are the routines required to output the various types of
565 /* A slot_number is a frag address plus the slot index (0-2). We use the
566 frag address here so that if there is a section switch in the middle of
567 a function, then instructions emitted to a different section are not
568 counted. Since there may be more than one frag for a function, this
569 means we also need to keep track of which frag this address belongs to
570 so we can compute inter-frag distances. This also nicely solves the
571 problem with nops emitted for align directives, which can't easily be
572 counted, but can easily be derived from frag sizes. */
574 typedef struct unw_rec_list {
576 unsigned long slot_number;
578 struct unw_rec_list *next;
581 #define SLOT_NUM_NOT_SET -1
585 unsigned long next_slot_number;
586 fragS *next_slot_frag;
588 /* Maintain a list of unwind entries for the current function. */
592 /* Any unwind entires that should be attached to the current slot
593 that an insn is being constructed for. */
594 unw_rec_list *current_entry;
596 /* These are used to create the unwind table entry for this function. */
599 symbolS *info; /* pointer to unwind info */
600 symbolS *personality_routine;
602 /* TRUE if processing unwind directives in a prologue region. */
607 typedef void (*vbyte_func) PARAMS ((int, char *, char *));
609 /* Forward delarations: */
610 static int ar_is_in_integer_unit PARAMS ((int regnum));
611 static void set_section PARAMS ((char *name));
612 static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
613 unsigned int, unsigned int));
614 static void dot_radix PARAMS ((int));
615 static void dot_special_section PARAMS ((int));
616 static void dot_proc PARAMS ((int));
617 static void dot_fframe PARAMS ((int));
618 static void dot_vframe PARAMS ((int));
619 static void dot_vframesp PARAMS ((int));
620 static void dot_vframepsp PARAMS ((int));
621 static void dot_save PARAMS ((int));
622 static void dot_restore PARAMS ((int));
623 static void dot_restorereg PARAMS ((int));
624 static void dot_restorereg_p PARAMS ((int));
625 static void dot_handlerdata PARAMS ((int));
626 static void dot_unwentry PARAMS ((int));
627 static void dot_altrp PARAMS ((int));
628 static void dot_savemem PARAMS ((int));
629 static void dot_saveg PARAMS ((int));
630 static void dot_savef PARAMS ((int));
631 static void dot_saveb PARAMS ((int));
632 static void dot_savegf PARAMS ((int));
633 static void dot_spill PARAMS ((int));
634 static void dot_spillreg PARAMS ((int));
635 static void dot_spillmem PARAMS ((int));
636 static void dot_spillreg_p PARAMS ((int));
637 static void dot_spillmem_p PARAMS ((int));
638 static void dot_label_state PARAMS ((int));
639 static void dot_copy_state PARAMS ((int));
640 static void dot_unwabi PARAMS ((int));
641 static void dot_personality PARAMS ((int));
642 static void dot_body PARAMS ((int));
643 static void dot_prologue PARAMS ((int));
644 static void dot_endp PARAMS ((int));
645 static void dot_template PARAMS ((int));
646 static void dot_regstk PARAMS ((int));
647 static void dot_rot PARAMS ((int));
648 static void dot_byteorder PARAMS ((int));
649 static void dot_psr PARAMS ((int));
650 static void dot_alias PARAMS ((int));
651 static void dot_ln PARAMS ((int));
652 static char *parse_section_name PARAMS ((void));
653 static void dot_xdata PARAMS ((int));
654 static void stmt_float_cons PARAMS ((int));
655 static void stmt_cons_ua PARAMS ((int));
656 static void dot_xfloat_cons PARAMS ((int));
657 static void dot_xstringer PARAMS ((int));
658 static void dot_xdata_ua PARAMS ((int));
659 static void dot_xfloat_cons_ua PARAMS ((int));
660 static void print_prmask PARAMS ((valueT mask));
661 static void dot_pred_rel PARAMS ((int));
662 static void dot_reg_val PARAMS ((int));
663 static void dot_dv_mode PARAMS ((int));
664 static void dot_entry PARAMS ((int));
665 static void dot_mem_offset PARAMS ((int));
666 static void add_unwind_entry PARAMS((unw_rec_list *ptr));
667 static symbolS *declare_register PARAMS ((const char *name, int regnum));
668 static void declare_register_set PARAMS ((const char *, int, int));
669 static unsigned int operand_width PARAMS ((enum ia64_opnd));
670 static int operand_match PARAMS ((const struct ia64_opcode *idesc,
671 int index, expressionS *e));
672 static int parse_operand PARAMS ((expressionS *e));
673 static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
674 static void build_insn PARAMS ((struct slot *, bfd_vma *));
675 static void emit_one_bundle PARAMS ((void));
676 static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
677 static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym,
678 bfd_reloc_code_real_type r_type));
679 static void insn_group_break PARAMS ((int, int, int));
680 static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *,
681 struct rsrc *, int depind, int path));
682 static void add_qp_mutex PARAMS((valueT mask));
683 static void add_qp_imply PARAMS((int p1, int p2));
684 static void clear_qp_branch_flag PARAMS((valueT mask));
685 static void clear_qp_mutex PARAMS((valueT mask));
686 static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask));
687 static void clear_register_values PARAMS ((void));
688 static void print_dependency PARAMS ((const char *action, int depind));
689 static void instruction_serialization PARAMS ((void));
690 static void data_serialization PARAMS ((void));
691 static void remove_marked_resource PARAMS ((struct rsrc *));
692 static int is_conditional_branch PARAMS ((struct ia64_opcode *));
693 static int is_taken_branch PARAMS ((struct ia64_opcode *));
694 static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *));
695 static int depends_on PARAMS ((int, struct ia64_opcode *));
696 static int specify_resource PARAMS ((const struct ia64_dependency *,
697 struct ia64_opcode *, int, struct rsrc [], int, int));
698 static int check_dv PARAMS((struct ia64_opcode *idesc));
699 static void check_dependencies PARAMS((struct ia64_opcode *));
700 static void mark_resources PARAMS((struct ia64_opcode *));
701 static void update_dependencies PARAMS((struct ia64_opcode *));
702 static void note_register_values PARAMS((struct ia64_opcode *));
703 static int qp_mutex PARAMS ((int, int, int));
704 static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int));
705 static void output_vbyte_mem PARAMS ((int, char *, char *));
706 static void count_output PARAMS ((int, char *, char *));
707 static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int));
708 static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long));
709 static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
710 static void output_P1_format PARAMS ((vbyte_func, int));
711 static void output_P2_format PARAMS ((vbyte_func, int, int));
712 static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int));
713 static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long));
714 static void output_P5_format PARAMS ((vbyte_func, int, unsigned long));
715 static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int));
716 static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long));
717 static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
718 static void output_P9_format PARAMS ((vbyte_func, int, int));
719 static void output_P10_format PARAMS ((vbyte_func, int, int));
720 static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
721 static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long));
722 static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long));
723 static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long));
724 static char format_ab_reg PARAMS ((int, int));
725 static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long,
727 static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long));
728 static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long,
730 static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long));
731 static void free_list_records PARAMS ((unw_rec_list *));
732 static unw_rec_list *output_prologue PARAMS ((void));
733 static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int));
734 static unw_rec_list *output_body PARAMS ((void));
735 static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int));
736 static unw_rec_list *output_mem_stack_v PARAMS ((void));
737 static unw_rec_list *output_psp_gr PARAMS ((unsigned int));
738 static unw_rec_list *output_psp_sprel PARAMS ((unsigned int));
739 static unw_rec_list *output_rp_when PARAMS ((void));
740 static unw_rec_list *output_rp_gr PARAMS ((unsigned int));
741 static unw_rec_list *output_rp_br PARAMS ((unsigned int));
742 static unw_rec_list *output_rp_psprel PARAMS ((unsigned int));
743 static unw_rec_list *output_rp_sprel PARAMS ((unsigned int));
744 static unw_rec_list *output_pfs_when PARAMS ((void));
745 static unw_rec_list *output_pfs_gr PARAMS ((unsigned int));
746 static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int));
747 static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int));
748 static unw_rec_list *output_preds_when PARAMS ((void));
749 static unw_rec_list *output_preds_gr PARAMS ((unsigned int));
750 static unw_rec_list *output_preds_psprel PARAMS ((unsigned int));
751 static unw_rec_list *output_preds_sprel PARAMS ((unsigned int));
752 static unw_rec_list *output_fr_mem PARAMS ((unsigned int));
753 static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int));
754 static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int));
755 static unw_rec_list *output_gr_mem PARAMS ((unsigned int));
756 static unw_rec_list *output_br_mem PARAMS ((unsigned int));
757 static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int));
758 static unw_rec_list *output_spill_base PARAMS ((unsigned int));
759 static unw_rec_list *output_unat_when PARAMS ((void));
760 static unw_rec_list *output_unat_gr PARAMS ((unsigned int));
761 static unw_rec_list *output_unat_psprel PARAMS ((unsigned int));
762 static unw_rec_list *output_unat_sprel PARAMS ((unsigned int));
763 static unw_rec_list *output_lc_when PARAMS ((void));
764 static unw_rec_list *output_lc_gr PARAMS ((unsigned int));
765 static unw_rec_list *output_lc_psprel PARAMS ((unsigned int));
766 static unw_rec_list *output_lc_sprel PARAMS ((unsigned int));
767 static unw_rec_list *output_fpsr_when PARAMS ((void));
768 static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int));
769 static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int));
770 static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int));
771 static unw_rec_list *output_priunat_when_gr PARAMS ((void));
772 static unw_rec_list *output_priunat_when_mem PARAMS ((void));
773 static unw_rec_list *output_priunat_gr PARAMS ((unsigned int));
774 static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int));
775 static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int));
776 static unw_rec_list *output_bsp_when PARAMS ((void));
777 static unw_rec_list *output_bsp_gr PARAMS ((unsigned int));
778 static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int));
779 static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int));
780 static unw_rec_list *output_bspstore_when PARAMS ((void));
781 static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int));
782 static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int));
783 static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int));
784 static unw_rec_list *output_rnat_when PARAMS ((void));
785 static unw_rec_list *output_rnat_gr PARAMS ((unsigned int));
786 static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int));
787 static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int));
788 static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
789 static unw_rec_list *output_epilogue PARAMS ((unsigned long));
790 static unw_rec_list *output_label_state PARAMS ((unsigned long));
791 static unw_rec_list *output_copy_state PARAMS ((unsigned long));
792 static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
793 static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
794 static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
796 static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
798 static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
800 static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
801 unsigned int, unsigned int));
802 static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
803 static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
804 static int calc_record_size PARAMS ((unw_rec_list *));
805 static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int));
806 static int count_bits PARAMS ((unsigned long));
807 static unsigned long slot_index PARAMS ((unsigned long, fragS *,
808 unsigned long, fragS *));
809 static void fixup_unw_records PARAMS ((unw_rec_list *));
810 static int output_unw_records PARAMS ((unw_rec_list *, void **));
811 static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
812 static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
813 static int generate_unwind_image PARAMS ((void));
815 /* Determine if application register REGNUM resides in the integer
816 unit (as opposed to the memory unit). */
818 ar_is_in_integer_unit (reg)
823 return (reg == 64 /* pfs */
824 || reg == 65 /* lc */
825 || reg == 66 /* ec */
826 /* ??? ias accepts and puts these in the integer unit. */
827 || (reg >= 112 && reg <= 127));
830 /* Switch to section NAME and create section if necessary. It's
831 rather ugly that we have to manipulate input_line_pointer but I
832 don't see any other way to accomplish the same thing without
833 changing obj-elf.c (which may be the Right Thing, in the end). */
838 char *saved_input_line_pointer;
840 saved_input_line_pointer = input_line_pointer;
841 input_line_pointer = name;
843 input_line_pointer = saved_input_line_pointer;
846 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
849 ia64_elf_section_flags (flags, attr, type)
853 if (attr & SHF_IA_64_SHORT)
854 flags |= SEC_SMALL_DATA;
859 set_regstack (ins, locs, outs, rots)
860 unsigned int ins, locs, outs, rots;
865 sof = ins + locs + outs;
868 as_bad ("Size of frame exceeds maximum of 96 registers");
873 as_warn ("Size of rotating registers exceeds frame size");
876 md.in.base = REG_GR + 32;
877 md.loc.base = md.in.base + ins;
878 md.out.base = md.loc.base + locs;
880 md.in.num_regs = ins;
881 md.loc.num_regs = locs;
882 md.out.num_regs = outs;
883 md.rot.num_regs = rots;
890 struct label_fix *lfix;
892 subsegT saved_subseg;
894 if (!md.last_text_seg)
898 saved_subseg = now_subseg;
900 subseg_set (md.last_text_seg, 0);
902 while (md.num_slots_in_use > 0)
903 emit_one_bundle (); /* force out queued instructions */
905 /* In case there are labels following the last instruction, resolve
907 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
909 S_SET_VALUE (lfix->sym, frag_now_fix ());
910 symbol_set_frag (lfix->sym, frag_now);
912 CURR_SLOT.label_fixups = 0;
913 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
915 S_SET_VALUE (lfix->sym, frag_now_fix ());
916 symbol_set_frag (lfix->sym, frag_now);
918 CURR_SLOT.tag_fixups = 0;
920 subseg_set (saved_seg, saved_subseg);
922 if (md.qp.X_op == O_register)
923 as_bad ("qualifying predicate not followed by instruction");
927 ia64_do_align (nbytes)
930 char *saved_input_line_pointer = input_line_pointer;
932 input_line_pointer = "";
933 s_align_bytes (nbytes);
934 input_line_pointer = saved_input_line_pointer;
938 ia64_cons_align (nbytes)
943 char *saved_input_line_pointer = input_line_pointer;
944 input_line_pointer = "";
945 s_align_bytes (nbytes);
946 input_line_pointer = saved_input_line_pointer;
950 /* Output COUNT bytes to a memory location. */
951 static unsigned char *vbyte_mem_ptr = NULL;
954 output_vbyte_mem (count, ptr, comment)
960 if (vbyte_mem_ptr == NULL)
965 for (x = 0; x < count; x++)
966 *(vbyte_mem_ptr++) = ptr[x];
969 /* Count the number of bytes required for records. */
970 static int vbyte_count = 0;
972 count_output (count, ptr, comment)
977 vbyte_count += count;
981 output_R1_format (f, rtype, rlen)
983 unw_record_type rtype;
990 output_R3_format (f, rtype, rlen);
996 else if (rtype != prologue)
997 as_bad ("record type is not valid");
999 byte = UNW_R1 | (r << 5) | (rlen & 0x1f);
1000 (*f) (1, &byte, NULL);
1004 output_R2_format (f, mask, grsave, rlen)
1011 mask = (mask & 0x0f);
1012 grsave = (grsave & 0x7f);
1014 bytes[0] = (UNW_R2 | (mask >> 1));
1015 bytes[1] = (((mask & 0x01) << 7) | grsave);
1016 count += output_leb128 (bytes + 2, rlen, 0);
1017 (*f) (count, bytes, NULL);
1021 output_R3_format (f, rtype, rlen)
1023 unw_record_type rtype;
1030 output_R1_format (f, rtype, rlen);
1036 else if (rtype != prologue)
1037 as_bad ("record type is not valid");
1038 bytes[0] = (UNW_R3 | r);
1039 count = output_leb128 (bytes + 1, rlen, 0);
1040 (*f) (count + 1, bytes, NULL);
1044 output_P1_format (f, brmask)
1049 byte = UNW_P1 | (brmask & 0x1f);
1050 (*f) (1, &byte, NULL);
1054 output_P2_format (f, brmask, gr)
1060 brmask = (brmask & 0x1f);
1061 bytes[0] = UNW_P2 | (brmask >> 1);
1062 bytes[1] = (((brmask & 1) << 7) | gr);
1063 (*f) (2, bytes, NULL);
1067 output_P3_format (f, rtype, reg)
1069 unw_record_type rtype;
1114 as_bad ("Invalid record type for P3 format.");
1116 bytes[0] = (UNW_P3 | (r >> 1));
1117 bytes[1] = (((r & 1) << 7) | reg);
1118 (*f) (2, bytes, NULL);
1122 output_P4_format (f, imask, imask_size)
1124 unsigned char *imask;
1125 unsigned long imask_size;
1128 (*f) (imask_size, imask, NULL);
1132 output_P5_format (f, grmask, frmask)
1135 unsigned long frmask;
1138 grmask = (grmask & 0x0f);
1141 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16));
1142 bytes[2] = ((frmask & 0x0000ff00) >> 8);
1143 bytes[3] = (frmask & 0x000000ff);
1144 (*f) (4, bytes, NULL);
1148 output_P6_format (f, rtype, rmask)
1150 unw_record_type rtype;
1156 if (rtype == gr_mem)
1158 else if (rtype != fr_mem)
1159 as_bad ("Invalid record type for format P6");
1160 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f));
1161 (*f) (1, &byte, NULL);
1165 output_P7_format (f, rtype, w1, w2)
1167 unw_record_type rtype;
1174 count += output_leb128 (bytes + 1, w1, 0);
1179 count += output_leb128 (bytes + count, w2 >> 4, 0);
1229 bytes[0] = (UNW_P7 | r);
1230 (*f) (count, bytes, NULL);
1234 output_P8_format (f, rtype, t)
1236 unw_record_type rtype;
1275 case bspstore_psprel:
1278 case bspstore_sprel:
1290 case priunat_when_gr:
1293 case priunat_psprel:
1299 case priunat_when_mem:
1306 count += output_leb128 (bytes + 2, t, 0);
1307 (*f) (count, bytes, NULL);
1311 output_P9_format (f, grmask, gr)
1318 bytes[1] = (grmask & 0x0f);
1319 bytes[2] = (gr & 0x7f);
1320 (*f) (3, bytes, NULL);
1324 output_P10_format (f, abi, context)
1331 bytes[1] = (abi & 0xff);
1332 bytes[2] = (context & 0xff);
1333 (*f) (3, bytes, NULL);
1337 output_B1_format (f, rtype, label)
1339 unw_record_type rtype;
1340 unsigned long label;
1346 output_B4_format (f, rtype, label);
1349 if (rtype == copy_state)
1351 else if (rtype != label_state)
1352 as_bad ("Invalid record type for format B1");
1354 byte = (UNW_B1 | (r << 5) | (label & 0x1f));
1355 (*f) (1, &byte, NULL);
1359 output_B2_format (f, ecount, t)
1361 unsigned long ecount;
1368 output_B3_format (f, ecount, t);
1371 bytes[0] = (UNW_B2 | (ecount & 0x1f));
1372 count += output_leb128 (bytes + 1, t, 0);
1373 (*f) (count, bytes, NULL);
1377 output_B3_format (f, ecount, t)
1379 unsigned long ecount;
1386 output_B2_format (f, ecount, t);
1390 count += output_leb128 (bytes + 1, t, 0);
1391 count += output_leb128 (bytes + count, ecount, 0);
1392 (*f) (count, bytes, NULL);
1396 output_B4_format (f, rtype, label)
1398 unw_record_type rtype;
1399 unsigned long label;
1406 output_B1_format (f, rtype, label);
1410 if (rtype == copy_state)
1412 else if (rtype != label_state)
1413 as_bad ("Invalid record type for format B1");
1415 bytes[0] = (UNW_B4 | (r << 3));
1416 count += output_leb128 (bytes + 1, label, 0);
1417 (*f) (count, bytes, NULL);
1421 format_ab_reg (ab, reg)
1428 ret = (ab << 5) | reg;
1433 output_X1_format (f, rtype, ab, reg, t, w1)
1435 unw_record_type rtype;
1445 if (rtype == spill_sprel)
1447 else if (rtype != spill_psprel)
1448 as_bad ("Invalid record type for format X1");
1449 bytes[1] = ((r << 7) | format_ab_reg (ab, reg));
1450 count += output_leb128 (bytes + 2, t, 0);
1451 count += output_leb128 (bytes + count, w1, 0);
1452 (*f) (count, bytes, NULL);
1456 output_X2_format (f, ab, reg, x, y, treg, t)
1465 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1466 bytes[2] = (((y & 1) << 7) | (treg & 0x7f));
1467 count += output_leb128 (bytes + 3, t, 0);
1468 (*f) (count, bytes, NULL);
1472 output_X3_format (f, rtype, qp, ab, reg, t, w1)
1474 unw_record_type rtype;
1485 if (rtype == spill_sprel_p)
1487 else if (rtype != spill_psprel_p)
1488 as_bad ("Invalid record type for format X3");
1489 bytes[1] = ((r << 7) | (qp & 0x3f));
1490 bytes[2] = format_ab_reg (ab, reg);
1491 count += output_leb128 (bytes + 3, t, 0);
1492 count += output_leb128 (bytes + count, w1, 0);
1493 (*f) (count, bytes, NULL);
1497 output_X4_format (f, qp, ab, reg, x, y, treg, t)
1507 bytes[1] = (qp & 0x3f);
1508 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg));
1509 bytes[3] = (((y & 1) << 7) | (treg & 0x7f));
1510 count += output_leb128 (bytes + 4, t, 0);
1511 (*f) (count, bytes, NULL);
1514 /* This function allocates a record list structure, and initializes fields. */
1516 static unw_rec_list *
1517 alloc_record (unw_record_type t)
1520 ptr = xmalloc (sizeof (*ptr));
1522 ptr->slot_number = SLOT_NUM_NOT_SET;
1527 /* This function frees an entire list of record structures. */
1530 free_list_records (unw_rec_list *first)
1533 for (ptr = first; ptr != NULL;)
1535 unw_rec_list *tmp = ptr;
1537 if ((tmp->r.type == prologue || tmp->r.type == prologue_gr)
1538 && tmp->r.record.r.mask.i)
1539 free (tmp->r.record.r.mask.i);
1546 static unw_rec_list *
1549 unw_rec_list *ptr = alloc_record (prologue);
1550 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1554 static unw_rec_list *
1555 output_prologue_gr (saved_mask, reg)
1556 unsigned int saved_mask;
1559 unw_rec_list *ptr = alloc_record (prologue_gr);
1560 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask));
1561 ptr->r.record.r.grmask = saved_mask;
1562 ptr->r.record.r.grsave = reg;
1566 static unw_rec_list *
1569 unw_rec_list *ptr = alloc_record (body);
1573 static unw_rec_list *
1574 output_mem_stack_f (size)
1577 unw_rec_list *ptr = alloc_record (mem_stack_f);
1578 ptr->r.record.p.size = size;
1582 static unw_rec_list *
1583 output_mem_stack_v ()
1585 unw_rec_list *ptr = alloc_record (mem_stack_v);
1589 static unw_rec_list *
1593 unw_rec_list *ptr = alloc_record (psp_gr);
1594 ptr->r.record.p.gr = gr;
1598 static unw_rec_list *
1599 output_psp_sprel (offset)
1600 unsigned int offset;
1602 unw_rec_list *ptr = alloc_record (psp_sprel);
1603 ptr->r.record.p.spoff = offset / 4;
1607 static unw_rec_list *
1610 unw_rec_list *ptr = alloc_record (rp_when);
1614 static unw_rec_list *
1618 unw_rec_list *ptr = alloc_record (rp_gr);
1619 ptr->r.record.p.gr = gr;
1623 static unw_rec_list *
1627 unw_rec_list *ptr = alloc_record (rp_br);
1628 ptr->r.record.p.br = br;
1632 static unw_rec_list *
1633 output_rp_psprel (offset)
1634 unsigned int offset;
1636 unw_rec_list *ptr = alloc_record (rp_psprel);
1637 ptr->r.record.p.pspoff = offset / 4;
1641 static unw_rec_list *
1642 output_rp_sprel (offset)
1643 unsigned int offset;
1645 unw_rec_list *ptr = alloc_record (rp_sprel);
1646 ptr->r.record.p.spoff = offset / 4;
1650 static unw_rec_list *
1653 unw_rec_list *ptr = alloc_record (pfs_when);
1657 static unw_rec_list *
1661 unw_rec_list *ptr = alloc_record (pfs_gr);
1662 ptr->r.record.p.gr = gr;
1666 static unw_rec_list *
1667 output_pfs_psprel (offset)
1668 unsigned int offset;
1670 unw_rec_list *ptr = alloc_record (pfs_psprel);
1671 ptr->r.record.p.pspoff = offset / 4;
1675 static unw_rec_list *
1676 output_pfs_sprel (offset)
1677 unsigned int offset;
1679 unw_rec_list *ptr = alloc_record (pfs_sprel);
1680 ptr->r.record.p.spoff = offset / 4;
1684 static unw_rec_list *
1685 output_preds_when ()
1687 unw_rec_list *ptr = alloc_record (preds_when);
1691 static unw_rec_list *
1692 output_preds_gr (gr)
1695 unw_rec_list *ptr = alloc_record (preds_gr);
1696 ptr->r.record.p.gr = gr;
1700 static unw_rec_list *
1701 output_preds_psprel (offset)
1702 unsigned int offset;
1704 unw_rec_list *ptr = alloc_record (preds_psprel);
1705 ptr->r.record.p.pspoff = offset / 4;
1709 static unw_rec_list *
1710 output_preds_sprel (offset)
1711 unsigned int offset;
1713 unw_rec_list *ptr = alloc_record (preds_sprel);
1714 ptr->r.record.p.spoff = offset / 4;
1718 static unw_rec_list *
1719 output_fr_mem (mask)
1722 unw_rec_list *ptr = alloc_record (fr_mem);
1723 ptr->r.record.p.rmask = mask;
1727 static unw_rec_list *
1728 output_frgr_mem (gr_mask, fr_mask)
1729 unsigned int gr_mask;
1730 unsigned int fr_mask;
1732 unw_rec_list *ptr = alloc_record (frgr_mem);
1733 ptr->r.record.p.grmask = gr_mask;
1734 ptr->r.record.p.frmask = fr_mask;
1738 static unw_rec_list *
1739 output_gr_gr (mask, reg)
1743 unw_rec_list *ptr = alloc_record (gr_gr);
1744 ptr->r.record.p.grmask = mask;
1745 ptr->r.record.p.gr = reg;
1749 static unw_rec_list *
1750 output_gr_mem (mask)
1753 unw_rec_list *ptr = alloc_record (gr_mem);
1754 ptr->r.record.p.rmask = mask;
1758 static unw_rec_list *
1759 output_br_mem (unsigned int mask)
1761 unw_rec_list *ptr = alloc_record (br_mem);
1762 ptr->r.record.p.brmask = mask;
1766 static unw_rec_list *
1767 output_br_gr (save_mask, reg)
1768 unsigned int save_mask;
1771 unw_rec_list *ptr = alloc_record (br_gr);
1772 ptr->r.record.p.brmask = save_mask;
1773 ptr->r.record.p.gr = reg;
1777 static unw_rec_list *
1778 output_spill_base (offset)
1779 unsigned int offset;
1781 unw_rec_list *ptr = alloc_record (spill_base);
1782 ptr->r.record.p.pspoff = offset / 4;
1786 static unw_rec_list *
1789 unw_rec_list *ptr = alloc_record (unat_when);
1793 static unw_rec_list *
1797 unw_rec_list *ptr = alloc_record (unat_gr);
1798 ptr->r.record.p.gr = gr;
1802 static unw_rec_list *
1803 output_unat_psprel (offset)
1804 unsigned int offset;
1806 unw_rec_list *ptr = alloc_record (unat_psprel);
1807 ptr->r.record.p.pspoff = offset / 4;
1811 static unw_rec_list *
1812 output_unat_sprel (offset)
1813 unsigned int offset;
1815 unw_rec_list *ptr = alloc_record (unat_sprel);
1816 ptr->r.record.p.spoff = offset / 4;
1820 static unw_rec_list *
1823 unw_rec_list *ptr = alloc_record (lc_when);
1827 static unw_rec_list *
1831 unw_rec_list *ptr = alloc_record (lc_gr);
1832 ptr->r.record.p.gr = gr;
1836 static unw_rec_list *
1837 output_lc_psprel (offset)
1838 unsigned int offset;
1840 unw_rec_list *ptr = alloc_record (lc_psprel);
1841 ptr->r.record.p.pspoff = offset / 4;
1845 static unw_rec_list *
1846 output_lc_sprel (offset)
1847 unsigned int offset;
1849 unw_rec_list *ptr = alloc_record (lc_sprel);
1850 ptr->r.record.p.spoff = offset / 4;
1854 static unw_rec_list *
1857 unw_rec_list *ptr = alloc_record (fpsr_when);
1861 static unw_rec_list *
1865 unw_rec_list *ptr = alloc_record (fpsr_gr);
1866 ptr->r.record.p.gr = gr;
1870 static unw_rec_list *
1871 output_fpsr_psprel (offset)
1872 unsigned int offset;
1874 unw_rec_list *ptr = alloc_record (fpsr_psprel);
1875 ptr->r.record.p.pspoff = offset / 4;
1879 static unw_rec_list *
1880 output_fpsr_sprel (offset)
1881 unsigned int offset;
1883 unw_rec_list *ptr = alloc_record (fpsr_sprel);
1884 ptr->r.record.p.spoff = offset / 4;
1888 static unw_rec_list *
1889 output_priunat_when_gr ()
1891 unw_rec_list *ptr = alloc_record (priunat_when_gr);
1895 static unw_rec_list *
1896 output_priunat_when_mem ()
1898 unw_rec_list *ptr = alloc_record (priunat_when_mem);
1902 static unw_rec_list *
1903 output_priunat_gr (gr)
1906 unw_rec_list *ptr = alloc_record (priunat_gr);
1907 ptr->r.record.p.gr = gr;
1911 static unw_rec_list *
1912 output_priunat_psprel (offset)
1913 unsigned int offset;
1915 unw_rec_list *ptr = alloc_record (priunat_psprel);
1916 ptr->r.record.p.pspoff = offset / 4;
1920 static unw_rec_list *
1921 output_priunat_sprel (offset)
1922 unsigned int offset;
1924 unw_rec_list *ptr = alloc_record (priunat_sprel);
1925 ptr->r.record.p.spoff = offset / 4;
1929 static unw_rec_list *
1932 unw_rec_list *ptr = alloc_record (bsp_when);
1936 static unw_rec_list *
1940 unw_rec_list *ptr = alloc_record (bsp_gr);
1941 ptr->r.record.p.gr = gr;
1945 static unw_rec_list *
1946 output_bsp_psprel (offset)
1947 unsigned int offset;
1949 unw_rec_list *ptr = alloc_record (bsp_psprel);
1950 ptr->r.record.p.pspoff = offset / 4;
1954 static unw_rec_list *
1955 output_bsp_sprel (offset)
1956 unsigned int offset;
1958 unw_rec_list *ptr = alloc_record (bsp_sprel);
1959 ptr->r.record.p.spoff = offset / 4;
1963 static unw_rec_list *
1964 output_bspstore_when ()
1966 unw_rec_list *ptr = alloc_record (bspstore_when);
1970 static unw_rec_list *
1971 output_bspstore_gr (gr)
1974 unw_rec_list *ptr = alloc_record (bspstore_gr);
1975 ptr->r.record.p.gr = gr;
1979 static unw_rec_list *
1980 output_bspstore_psprel (offset)
1981 unsigned int offset;
1983 unw_rec_list *ptr = alloc_record (bspstore_psprel);
1984 ptr->r.record.p.pspoff = offset / 4;
1988 static unw_rec_list *
1989 output_bspstore_sprel (offset)
1990 unsigned int offset;
1992 unw_rec_list *ptr = alloc_record (bspstore_sprel);
1993 ptr->r.record.p.spoff = offset / 4;
1997 static unw_rec_list *
2000 unw_rec_list *ptr = alloc_record (rnat_when);
2004 static unw_rec_list *
2008 unw_rec_list *ptr = alloc_record (rnat_gr);
2009 ptr->r.record.p.gr = gr;
2013 static unw_rec_list *
2014 output_rnat_psprel (offset)
2015 unsigned int offset;
2017 unw_rec_list *ptr = alloc_record (rnat_psprel);
2018 ptr->r.record.p.pspoff = offset / 4;
2022 static unw_rec_list *
2023 output_rnat_sprel (offset)
2024 unsigned int offset;
2026 unw_rec_list *ptr = alloc_record (rnat_sprel);
2027 ptr->r.record.p.spoff = offset / 4;
2031 static unw_rec_list *
2032 output_unwabi (abi, context)
2034 unsigned long context;
2036 unw_rec_list *ptr = alloc_record (unwabi);
2037 ptr->r.record.p.abi = abi;
2038 ptr->r.record.p.context = context;
2042 static unw_rec_list *
2043 output_epilogue (unsigned long ecount)
2045 unw_rec_list *ptr = alloc_record (epilogue);
2046 ptr->r.record.b.ecount = ecount;
2050 static unw_rec_list *
2051 output_label_state (unsigned long label)
2053 unw_rec_list *ptr = alloc_record (label_state);
2054 ptr->r.record.b.label = label;
2058 static unw_rec_list *
2059 output_copy_state (unsigned long label)
2061 unw_rec_list *ptr = alloc_record (copy_state);
2062 ptr->r.record.b.label = label;
2066 static unw_rec_list *
2067 output_spill_psprel (ab, reg, offset)
2070 unsigned int offset;
2072 unw_rec_list *ptr = alloc_record (spill_psprel);
2073 ptr->r.record.x.ab = ab;
2074 ptr->r.record.x.reg = reg;
2075 ptr->r.record.x.pspoff = offset / 4;
2079 static unw_rec_list *
2080 output_spill_sprel (ab, reg, offset)
2083 unsigned int offset;
2085 unw_rec_list *ptr = alloc_record (spill_sprel);
2086 ptr->r.record.x.ab = ab;
2087 ptr->r.record.x.reg = reg;
2088 ptr->r.record.x.spoff = offset / 4;
2092 static unw_rec_list *
2093 output_spill_psprel_p (ab, reg, offset, predicate)
2096 unsigned int offset;
2097 unsigned int predicate;
2099 unw_rec_list *ptr = alloc_record (spill_psprel_p);
2100 ptr->r.record.x.ab = ab;
2101 ptr->r.record.x.reg = reg;
2102 ptr->r.record.x.pspoff = offset / 4;
2103 ptr->r.record.x.qp = predicate;
2107 static unw_rec_list *
2108 output_spill_sprel_p (ab, reg, offset, predicate)
2111 unsigned int offset;
2112 unsigned int predicate;
2114 unw_rec_list *ptr = alloc_record (spill_sprel_p);
2115 ptr->r.record.x.ab = ab;
2116 ptr->r.record.x.reg = reg;
2117 ptr->r.record.x.spoff = offset / 4;
2118 ptr->r.record.x.qp = predicate;
2122 static unw_rec_list *
2123 output_spill_reg (ab, reg, targ_reg, xy)
2126 unsigned int targ_reg;
2129 unw_rec_list *ptr = alloc_record (spill_reg);
2130 ptr->r.record.x.ab = ab;
2131 ptr->r.record.x.reg = reg;
2132 ptr->r.record.x.treg = targ_reg;
2133 ptr->r.record.x.xy = xy;
2137 static unw_rec_list *
2138 output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
2141 unsigned int targ_reg;
2143 unsigned int predicate;
2145 unw_rec_list *ptr = alloc_record (spill_reg_p);
2146 ptr->r.record.x.ab = ab;
2147 ptr->r.record.x.reg = reg;
2148 ptr->r.record.x.treg = targ_reg;
2149 ptr->r.record.x.xy = xy;
2150 ptr->r.record.x.qp = predicate;
2154 /* Given a unw_rec_list process the correct format with the
2155 specified function. */
2158 process_one_record (ptr, f)
2162 unsigned long fr_mask, gr_mask;
2164 switch (ptr->r.type)
2170 /* These are taken care of by prologue/prologue_gr. */
2175 if (ptr->r.type == prologue_gr)
2176 output_R2_format (f, ptr->r.record.r.grmask,
2177 ptr->r.record.r.grsave, ptr->r.record.r.rlen);
2179 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2181 /* Output descriptor(s) for union of register spills (if any). */
2182 gr_mask = ptr->r.record.r.mask.gr_mem;
2183 fr_mask = ptr->r.record.r.mask.fr_mem;
2186 if ((fr_mask & ~0xfUL) == 0)
2187 output_P6_format (f, fr_mem, fr_mask);
2190 output_P5_format (f, gr_mask, fr_mask);
2195 output_P6_format (f, gr_mem, gr_mask);
2196 if (ptr->r.record.r.mask.br_mem)
2197 output_P1_format (f, ptr->r.record.r.mask.br_mem);
2199 /* output imask descriptor if necessary: */
2200 if (ptr->r.record.r.mask.i)
2201 output_P4_format (f, ptr->r.record.r.mask.i,
2202 ptr->r.record.r.imask_size);
2206 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen);
2210 output_P7_format (f, ptr->r.type, ptr->r.record.p.t,
2211 ptr->r.record.p.size);
2224 output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
2227 output_P3_format (f, rp_br, ptr->r.record.p.br);
2230 output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
2238 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0);
2247 output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
2257 case bspstore_sprel:
2259 output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
2262 output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
2265 output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
2268 as_bad ("spill_mask record unimplemented.");
2270 case priunat_when_gr:
2271 case priunat_when_mem:
2275 output_P8_format (f, ptr->r.type, ptr->r.record.p.t);
2277 case priunat_psprel:
2279 case bspstore_psprel:
2281 output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
2284 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
2287 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t);
2291 output_B4_format (f, ptr->r.type, ptr->r.record.b.label);
2294 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2295 ptr->r.record.x.reg, ptr->r.record.x.t,
2296 ptr->r.record.x.pspoff);
2299 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
2300 ptr->r.record.x.reg, ptr->r.record.x.t,
2301 ptr->r.record.x.spoff);
2304 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
2305 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
2306 ptr->r.record.x.treg, ptr->r.record.x.t);
2308 case spill_psprel_p:
2309 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2310 ptr->r.record.x.ab, ptr->r.record.x.reg,
2311 ptr->r.record.x.t, ptr->r.record.x.pspoff);
2314 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
2315 ptr->r.record.x.ab, ptr->r.record.x.reg,
2316 ptr->r.record.x.t, ptr->r.record.x.spoff);
2319 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
2320 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
2321 ptr->r.record.x.xy, ptr->r.record.x.treg,
2325 as_bad ("record_type_not_valid");
2330 /* Given a unw_rec_list list, process all the records with
2331 the specified function. */
2333 process_unw_records (list, f)
2338 for (ptr = list; ptr; ptr = ptr->next)
2339 process_one_record (ptr, f);
2342 /* Determine the size of a record list in bytes. */
2344 calc_record_size (list)
2348 process_unw_records (list, count_output);
2352 /* Update IMASK bitmask to reflect the fact that one or more registers
2353 of type TYPE are saved starting at instruction with index T. If N
2354 bits are set in REGMASK, it is assumed that instructions T through
2355 T+N-1 save these registers.
2359 1: instruction saves next fp reg
2360 2: instruction saves next general reg
2361 3: instruction saves next branch reg */
2363 set_imask (region, regmask, t, type)
2364 unw_rec_list *region;
2365 unsigned long regmask;
2369 unsigned char *imask;
2370 unsigned long imask_size;
2374 imask = region->r.record.r.mask.i;
2375 imask_size = region->r.record.r.imask_size;
2378 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1;
2379 imask = xmalloc (imask_size);
2380 memset (imask, 0, imask_size);
2382 region->r.record.r.imask_size = imask_size;
2383 region->r.record.r.mask.i = imask;
2387 pos = 2 * (3 - t % 4);
2390 if (i >= imask_size)
2392 as_bad ("Ignoring attempt to spill beyond end of region");
2396 imask[i] |= (type & 0x3) << pos;
2398 regmask &= (regmask - 1);
2409 count_bits (unsigned long mask)
2421 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2422 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2423 containing FIRST_ADDR. */
2426 slot_index (slot_addr, slot_frag, first_addr, first_frag)
2427 unsigned long slot_addr;
2429 unsigned long first_addr;
2432 unsigned long index = 0;
2434 /* First time we are called, the initial address and frag are invalid. */
2435 if (first_addr == 0)
2438 /* If the two addresses are in different frags, then we need to add in
2439 the remaining size of this frag, and then the entire size of intermediate
2441 while (slot_frag != first_frag)
2443 unsigned long start_addr = (unsigned long) &first_frag->fr_literal;
2445 /* Add in the full size of the frag converted to instruction slots. */
2446 index += 3 * (first_frag->fr_fix >> 4);
2447 /* Subtract away the initial part before first_addr. */
2448 index -= (3 * ((first_addr >> 4) - (start_addr >> 4))
2449 + ((first_addr & 0x3) - (start_addr & 0x3)));
2451 /* Move to the beginning of the next frag. */
2452 first_frag = first_frag->fr_next;
2453 first_addr = (unsigned long) &first_frag->fr_literal;
2456 /* Add in the used part of the last frag. */
2457 index += (3 * ((slot_addr >> 4) - (first_addr >> 4))
2458 + ((slot_addr & 0x3) - (first_addr & 0x3)));
2462 /* Given a complete record list, process any records which have
2463 unresolved fields, (ie length counts for a prologue). After
2464 this has been run, all neccessary information should be available
2465 within each record to generate an image. */
2468 fixup_unw_records (list)
2471 unw_rec_list *ptr, *region = 0;
2472 unsigned long first_addr = 0, rlen = 0, t;
2473 fragS *first_frag = 0;
2475 for (ptr = list; ptr; ptr = ptr->next)
2477 if (ptr->slot_number == SLOT_NUM_NOT_SET)
2478 as_bad (" Insn slot not set in unwind record.");
2479 t = slot_index (ptr->slot_number, ptr->slot_frag,
2480 first_addr, first_frag);
2481 switch (ptr->r.type)
2488 int size, dir_len = 0;
2489 unsigned long last_addr;
2492 first_addr = ptr->slot_number;
2493 first_frag = ptr->slot_frag;
2494 ptr->slot_number = 0;
2495 /* Find either the next body/prologue start, or the end of
2496 the list, and determine the size of the region. */
2497 last_addr = unwind.next_slot_number;
2498 last_frag = unwind.next_slot_frag;
2499 for (last = ptr->next; last != NULL; last = last->next)
2500 if (last->r.type == prologue || last->r.type == prologue_gr
2501 || last->r.type == body)
2503 last_addr = last->slot_number;
2504 last_frag = last->slot_frag;
2507 else if (!last->next)
2509 /* In the absence of an explicit .body directive,
2510 the prologue ends after the last instruction
2511 covered by an unwind directive. */
2512 if (ptr->r.type != body)
2514 last_addr = last->slot_number;
2515 last_frag = last->slot_frag;
2516 switch (last->r.type)
2519 dir_len = (count_bits (last->r.record.p.frmask)
2520 + count_bits (last->r.record.p.grmask));
2524 dir_len += count_bits (last->r.record.p.rmask);
2528 dir_len += count_bits (last->r.record.p.brmask);
2531 dir_len += count_bits (last->r.record.p.grmask);
2540 size = (slot_index (last_addr, last_frag, first_addr, first_frag)
2542 rlen = ptr->r.record.r.rlen = size;
2547 ptr->r.record.b.t = rlen - 1 - t;
2558 case priunat_when_gr:
2559 case priunat_when_mem:
2563 ptr->r.record.p.t = t;
2571 case spill_psprel_p:
2572 ptr->r.record.x.t = t;
2578 as_bad ("frgr_mem record before region record!\n");
2581 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
2582 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
2583 set_imask (region, ptr->r.record.p.frmask, t, 1);
2584 set_imask (region, ptr->r.record.p.grmask, t, 2);
2589 as_bad ("fr_mem record before region record!\n");
2592 region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
2593 set_imask (region, ptr->r.record.p.rmask, t, 1);
2598 as_bad ("gr_mem record before region record!\n");
2601 region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
2602 set_imask (region, ptr->r.record.p.rmask, t, 2);
2607 as_bad ("br_mem record before region record!\n");
2610 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
2611 set_imask (region, ptr->r.record.p.brmask, t, 3);
2617 as_bad ("gr_gr record before region record!\n");
2620 set_imask (region, ptr->r.record.p.grmask, t, 2);
2625 as_bad ("br_gr record before region record!\n");
2628 set_imask (region, ptr->r.record.p.brmask, t, 3);
2637 /* Generate an unwind image from a record list. Returns the number of
2638 bytes in the resulting image. The memory image itselof is returned
2639 in the 'ptr' parameter. */
2641 output_unw_records (list, ptr)
2645 int size, x, extra = 0;
2648 fixup_unw_records (list);
2649 size = calc_record_size (list);
2651 /* pad to 8 byte boundry. */
2655 /* Add 8 for the header + 8 more bytes for the personality offset. */
2656 mem = xmalloc (size + extra + 16);
2658 vbyte_mem_ptr = mem + 8;
2659 /* Clear the padding area and personality. */
2660 memset (mem + 8 + size, 0 , extra + 8);
2661 /* Initialize the header area. */
2662 md_number_to_chars (mem, (((bfd_vma) 1 << 48) /* version */
2663 | (unwind.personality_routine
2664 ? ((bfd_vma) 3 << 32) /* U & E handler flags */
2666 | ((size + extra) / 8)), /* length (dwords) */
2669 process_unw_records (list, output_vbyte_mem);
2672 return size + extra + 16;
2676 convert_expr_to_ab_reg (e, ab, regp)
2683 if (e->X_op != O_register)
2686 reg = e->X_add_number;
2687 if (reg >= REG_GR + 4 && reg <= REG_GR + 7)
2690 *regp = reg - REG_GR;
2692 else if ((reg >= REG_FR + 2 && reg <= REG_FR + 5)
2693 || (reg >= REG_FR + 16 && reg <= REG_FR + 31))
2696 *regp = reg - REG_FR;
2698 else if (reg >= REG_BR + 1 && reg <= REG_BR + 5)
2701 *regp = reg - REG_BR;
2708 case REG_PR: *regp = 0; break;
2709 case REG_PSP: *regp = 1; break;
2710 case REG_PRIUNAT: *regp = 2; break;
2711 case REG_BR + 0: *regp = 3; break;
2712 case REG_AR + AR_BSP: *regp = 4; break;
2713 case REG_AR + AR_BSPSTORE: *regp = 5; break;
2714 case REG_AR + AR_RNAT: *regp = 6; break;
2715 case REG_AR + AR_UNAT: *regp = 7; break;
2716 case REG_AR + AR_FPSR: *regp = 8; break;
2717 case REG_AR + AR_PFS: *regp = 9; break;
2718 case REG_AR + AR_LC: *regp = 10; break;
2728 convert_expr_to_xy_reg (e, xy, regp)
2735 if (e->X_op != O_register)
2738 reg = e->X_add_number;
2740 if (reg >= REG_GR && reg <= REG_GR + 127)
2743 *regp = reg - REG_GR;
2745 else if (reg >= REG_FR && reg <= REG_FR + 127)
2748 *regp = reg - REG_FR;
2750 else if (reg >= REG_BR && reg <= REG_BR + 7)
2753 *regp = reg - REG_BR;
2767 radix = *input_line_pointer++;
2769 if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
2771 as_bad ("Radix `%c' unsupported", *input_line_pointer);
2772 ignore_rest_of_line ();
2777 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2779 dot_special_section (which)
2782 set_section ((char *) special_section_name[which]);
2786 add_unwind_entry (ptr)
2790 unwind.tail->next = ptr;
2795 /* The current entry can in fact be a chain of unwind entries. */
2796 if (unwind.current_entry == NULL)
2797 unwind.current_entry = ptr;
2808 if (e.X_op != O_constant)
2809 as_bad ("Operand to .fframe must be a constant");
2811 add_unwind_entry (output_mem_stack_f (e.X_add_number));
2822 reg = e.X_add_number - REG_GR;
2823 if (e.X_op == O_register && reg < 128)
2825 add_unwind_entry (output_mem_stack_v ());
2826 if (! (unwind.prologue_mask & 2))
2827 add_unwind_entry (output_psp_gr (reg));
2830 as_bad ("First operand to .vframe must be a general register");
2834 dot_vframesp (dummy)
2840 if (e.X_op == O_constant)
2842 add_unwind_entry (output_mem_stack_v ());
2843 add_unwind_entry (output_psp_sprel (e.X_add_number));
2846 as_bad ("First operand to .vframesp must be a general register");
2850 dot_vframepsp (dummy)
2856 if (e.X_op == O_constant)
2858 add_unwind_entry (output_mem_stack_v ());
2859 add_unwind_entry (output_psp_sprel (e.X_add_number));
2862 as_bad ("First operand to .vframepsp must be a general register");
2873 sep = parse_operand (&e1);
2875 as_bad ("No second operand to .save");
2876 sep = parse_operand (&e2);
2878 reg1 = e1.X_add_number;
2879 reg2 = e2.X_add_number - REG_GR;
2881 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2882 if (e1.X_op == O_register)
2884 if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
2888 case REG_AR + AR_BSP:
2889 add_unwind_entry (output_bsp_when ());
2890 add_unwind_entry (output_bsp_gr (reg2));
2892 case REG_AR + AR_BSPSTORE:
2893 add_unwind_entry (output_bspstore_when ());
2894 add_unwind_entry (output_bspstore_gr (reg2));
2896 case REG_AR + AR_RNAT:
2897 add_unwind_entry (output_rnat_when ());
2898 add_unwind_entry (output_rnat_gr (reg2));
2900 case REG_AR + AR_UNAT:
2901 add_unwind_entry (output_unat_when ());
2902 add_unwind_entry (output_unat_gr (reg2));
2904 case REG_AR + AR_FPSR:
2905 add_unwind_entry (output_fpsr_when ());
2906 add_unwind_entry (output_fpsr_gr (reg2));
2908 case REG_AR + AR_PFS:
2909 add_unwind_entry (output_pfs_when ());
2910 if (! (unwind.prologue_mask & 4))
2911 add_unwind_entry (output_pfs_gr (reg2));
2913 case REG_AR + AR_LC:
2914 add_unwind_entry (output_lc_when ());
2915 add_unwind_entry (output_lc_gr (reg2));
2918 add_unwind_entry (output_rp_when ());
2919 if (! (unwind.prologue_mask & 8))
2920 add_unwind_entry (output_rp_gr (reg2));
2923 add_unwind_entry (output_preds_when ());
2924 if (! (unwind.prologue_mask & 1))
2925 add_unwind_entry (output_preds_gr (reg2));
2928 add_unwind_entry (output_priunat_when_gr ());
2929 add_unwind_entry (output_priunat_gr (reg2));
2932 as_bad ("First operand not a valid register");
2936 as_bad (" Second operand not a valid register");
2939 as_bad ("First operand not a register");
2947 unsigned long ecount = 0;
2950 sep = parse_operand (&e1);
2951 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
2953 as_bad ("First operand to .restore must be stack pointer (sp)");
2959 parse_operand (&e2);
2960 if (e1.X_op != O_constant)
2962 as_bad ("Second operand to .restore must be constant");
2967 add_unwind_entry (output_epilogue (ecount));
2971 dot_restorereg (dummy)
2974 unsigned int ab, reg;
2979 if (!convert_expr_to_ab_reg (&e, &ab, ®))
2981 as_bad ("First operand to .restorereg must be a preserved register");
2984 add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
2988 dot_restorereg_p (dummy)
2991 unsigned int qp, ab, reg;
2995 sep = parse_operand (&e1);
2998 as_bad ("No second operand to .restorereg.p");
3002 parse_operand (&e2);
3004 qp = e1.X_add_number - REG_P;
3005 if (e1.X_op != O_register || qp > 63)
3007 as_bad ("First operand to .restorereg.p must be a predicate");
3011 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3013 as_bad ("Second operand to .restorereg.p must be a preserved register");
3016 add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
3020 generate_unwind_image ()
3023 unsigned char *unw_rec;
3025 /* Force out pending instructions, to make sure all unwind records have
3026 a valid slot_number field. */
3027 ia64_flush_insns ();
3029 /* Generate the unwind record. */
3030 size = output_unw_records (unwind.list, (void **) &unw_rec);
3032 as_bad ("Unwind record is not a multiple of 8 bytes.");
3034 /* If there are unwind records, switch sections, and output the info. */
3037 unsigned char *where;
3039 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND_INFO]);
3041 /* Set expression which points to start of unwind descriptor area. */
3042 unwind.info = expr_build_dot ();
3044 where = (unsigned char *) frag_more (size);
3046 /* Issue a label for this address, and keep track of it to put it
3047 in the unwind section. */
3049 /* Copy the information from the unwind record into this section. The
3050 data is already in the correct byte order. */
3051 memcpy (where, unw_rec, size);
3052 /* Add the personality address to the image. */
3053 if (unwind.personality_routine != 0)
3055 exp.X_op = O_symbol;
3056 exp.X_add_symbol = unwind.personality_routine;
3057 exp.X_add_number = 0;
3058 fix_new_exp (frag_now, frag_now_fix () - 8, 8,
3059 &exp, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB);
3060 unwind.personality_routine = 0;
3062 obj_elf_previous (0);
3065 free_list_records (unwind.list);
3066 unwind.list = unwind.tail = unwind.current_entry = NULL;
3072 dot_handlerdata (dummy)
3075 generate_unwind_image ();
3076 demand_empty_rest_of_line ();
3080 dot_unwentry (dummy)
3083 demand_empty_rest_of_line ();
3094 reg = e.X_add_number - REG_BR;
3095 if (e.X_op == O_register && reg < 8)
3096 add_unwind_entry (output_rp_br (reg));
3098 as_bad ("First operand not a valid branch register");
3102 dot_savemem (psprel)
3109 sep = parse_operand (&e1);
3111 as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
3112 sep = parse_operand (&e2);
3114 reg1 = e1.X_add_number;
3115 val = e2.X_add_number;
3117 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3118 if (e1.X_op == O_register)
3120 if (e2.X_op == O_constant)
3124 case REG_AR + AR_BSP:
3125 add_unwind_entry (output_bsp_when ());
3126 add_unwind_entry ((psprel
3128 : output_bsp_sprel) (val));
3130 case REG_AR + AR_BSPSTORE:
3131 add_unwind_entry (output_bspstore_when ());
3132 add_unwind_entry ((psprel
3133 ? output_bspstore_psprel
3134 : output_bspstore_sprel) (val));
3136 case REG_AR + AR_RNAT:
3137 add_unwind_entry (output_rnat_when ());
3138 add_unwind_entry ((psprel
3139 ? output_rnat_psprel
3140 : output_rnat_sprel) (val));
3142 case REG_AR + AR_UNAT:
3143 add_unwind_entry (output_unat_when ());
3144 add_unwind_entry ((psprel
3145 ? output_unat_psprel
3146 : output_unat_sprel) (val));
3148 case REG_AR + AR_FPSR:
3149 add_unwind_entry (output_fpsr_when ());
3150 add_unwind_entry ((psprel
3151 ? output_fpsr_psprel
3152 : output_fpsr_sprel) (val));
3154 case REG_AR + AR_PFS:
3155 add_unwind_entry (output_pfs_when ());
3156 add_unwind_entry ((psprel
3158 : output_pfs_sprel) (val));
3160 case REG_AR + AR_LC:
3161 add_unwind_entry (output_lc_when ());
3162 add_unwind_entry ((psprel
3164 : output_lc_sprel) (val));
3167 add_unwind_entry (output_rp_when ());
3168 add_unwind_entry ((psprel
3170 : output_rp_sprel) (val));
3173 add_unwind_entry (output_preds_when ());
3174 add_unwind_entry ((psprel
3175 ? output_preds_psprel
3176 : output_preds_sprel) (val));
3179 add_unwind_entry (output_priunat_when_mem ());
3180 add_unwind_entry ((psprel
3181 ? output_priunat_psprel
3182 : output_priunat_sprel) (val));
3185 as_bad ("First operand not a valid register");
3189 as_bad (" Second operand not a valid constant");
3192 as_bad ("First operand not a register");
3201 sep = parse_operand (&e1);
3203 parse_operand (&e2);
3205 if (e1.X_op != O_constant)
3206 as_bad ("First operand to .save.g must be a constant.");
3209 int grmask = e1.X_add_number;
3211 add_unwind_entry (output_gr_mem (grmask));
3214 int reg = e2.X_add_number - REG_GR;
3215 if (e2.X_op == O_register && reg >= 0 && reg < 128)
3216 add_unwind_entry (output_gr_gr (grmask, reg));
3218 as_bad ("Second operand is an invalid register.");
3229 sep = parse_operand (&e1);
3231 if (e1.X_op != O_constant)
3232 as_bad ("Operand to .save.f must be a constant.");
3234 add_unwind_entry (output_fr_mem (e1.X_add_number));
3246 sep = parse_operand (&e1);
3247 if (e1.X_op != O_constant)
3249 as_bad ("First operand to .save.b must be a constant.");
3252 brmask = e1.X_add_number;
3256 sep = parse_operand (&e2);
3257 reg = e2.X_add_number - REG_GR;
3258 if (e2.X_op != O_register || reg > 127)
3260 as_bad ("Second operand to .save.b must be a general register.");
3263 add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
3266 add_unwind_entry (output_br_mem (brmask));
3268 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3269 ignore_rest_of_line ();
3278 sep = parse_operand (&e1);
3280 parse_operand (&e2);
3282 if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
3283 as_bad ("Both operands of .save.gf must be constants.");
3286 int grmask = e1.X_add_number;
3287 int frmask = e2.X_add_number;
3288 add_unwind_entry (output_frgr_mem (grmask, frmask));
3299 sep = parse_operand (&e);
3300 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3301 ignore_rest_of_line ();
3303 if (e.X_op != O_constant)
3304 as_bad ("Operand to .spill must be a constant");
3306 add_unwind_entry (output_spill_base (e.X_add_number));
3310 dot_spillreg (dummy)
3313 int sep, ab, xy, reg, treg;
3316 sep = parse_operand (&e1);
3319 as_bad ("No second operand to .spillreg");
3323 parse_operand (&e2);
3325 if (!convert_expr_to_ab_reg (&e1, &ab, ®))
3327 as_bad ("First operand to .spillreg must be a preserved register");
3331 if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
3333 as_bad ("Second operand to .spillreg must be a register");
3337 add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
3341 dot_spillmem (psprel)
3347 sep = parse_operand (&e1);
3350 as_bad ("Second operand missing");
3354 parse_operand (&e2);
3356 if (!convert_expr_to_ab_reg (&e1, &ab, ®))
3358 as_bad ("First operand to .spill%s must be a preserved register",
3359 psprel ? "psp" : "sp");
3363 if (e2.X_op != O_constant)
3365 as_bad ("Second operand to .spill%s must be a constant",
3366 psprel ? "psp" : "sp");
3371 add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
3373 add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
3377 dot_spillreg_p (dummy)
3380 int sep, ab, xy, reg, treg;
3381 expressionS e1, e2, e3;
3384 sep = parse_operand (&e1);
3387 as_bad ("No second and third operand to .spillreg.p");
3391 sep = parse_operand (&e2);
3394 as_bad ("No third operand to .spillreg.p");
3398 parse_operand (&e3);
3400 qp = e1.X_add_number - REG_P;
3402 if (e1.X_op != O_register || qp > 63)
3404 as_bad ("First operand to .spillreg.p must be a predicate");
3408 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3410 as_bad ("Second operand to .spillreg.p must be a preserved register");
3414 if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
3416 as_bad ("Third operand to .spillreg.p must be a register");
3420 add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
3424 dot_spillmem_p (psprel)
3427 expressionS e1, e2, e3;
3431 sep = parse_operand (&e1);
3434 as_bad ("Second operand missing");
3438 parse_operand (&e2);
3441 as_bad ("Second operand missing");
3445 parse_operand (&e3);
3447 qp = e1.X_add_number - REG_P;
3448 if (e1.X_op != O_register || qp > 63)
3450 as_bad ("First operand to .spill%s_p must be a predicate",
3451 psprel ? "psp" : "sp");
3455 if (!convert_expr_to_ab_reg (&e2, &ab, ®))
3457 as_bad ("Second operand to .spill%s_p must be a preserved register",
3458 psprel ? "psp" : "sp");
3462 if (e3.X_op != O_constant)
3464 as_bad ("Third operand to .spill%s_p must be a constant",
3465 psprel ? "psp" : "sp");
3470 add_unwind_entry (output_spill_psprel_p (qp, ab, reg, e3.X_add_number));
3472 add_unwind_entry (output_spill_sprel_p (qp, ab, reg, e3.X_add_number));
3476 dot_label_state (dummy)
3482 if (e.X_op != O_constant)
3484 as_bad ("Operand to .label_state must be a constant");
3487 add_unwind_entry (output_label_state (e.X_add_number));
3491 dot_copy_state (dummy)
3497 if (e.X_op != O_constant)
3499 as_bad ("Operand to .copy_state must be a constant");
3502 add_unwind_entry (output_copy_state (e.X_add_number));
3512 sep = parse_operand (&e1);
3515 as_bad ("Second operand to .unwabi missing");
3518 sep = parse_operand (&e2);
3519 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3520 ignore_rest_of_line ();
3522 if (e1.X_op != O_constant)
3524 as_bad ("First operand to .unwabi must be a constant");
3528 if (e2.X_op != O_constant)
3530 as_bad ("Second operand to .unwabi must be a constant");
3534 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
3538 dot_personality (dummy)
3543 name = input_line_pointer;
3544 c = get_symbol_end ();
3545 p = input_line_pointer;
3546 unwind.personality_routine = symbol_find_or_make (name);
3549 demand_empty_rest_of_line ();
3559 unwind.proc_start = expr_build_dot ();
3560 /* Parse names of main and alternate entry points and mark them as
3561 function symbols: */
3565 name = input_line_pointer;
3566 c = get_symbol_end ();
3567 p = input_line_pointer;
3568 sym = symbol_find_or_make (name);
3569 if (unwind.proc_start == 0)
3571 unwind.proc_start = sym;
3573 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
3576 if (*input_line_pointer != ',')
3578 ++input_line_pointer;
3580 demand_empty_rest_of_line ();
3583 unwind.list = unwind.tail = unwind.current_entry = NULL;
3584 unwind.personality_routine = 0;
3591 unwind.prologue = 0;
3592 unwind.prologue_mask = 0;
3594 add_unwind_entry (output_body ());
3595 demand_empty_rest_of_line ();
3599 dot_prologue (dummy)
3603 int mask = 0, grsave;
3605 if (!is_it_end_of_statement ())
3608 sep = parse_operand (&e1);
3610 as_bad ("No second operand to .prologue");
3611 sep = parse_operand (&e2);
3612 if (!is_end_of_line[sep] && !is_it_end_of_statement ())
3613 ignore_rest_of_line ();
3615 if (e1.X_op == O_constant)
3617 mask = e1.X_add_number;
3619 if (e2.X_op == O_constant)
3620 grsave = e2.X_add_number;
3621 else if (e2.X_op == O_register
3622 && (grsave = e2.X_add_number - REG_GR) < 128)
3625 as_bad ("Second operand not a constant or general register");
3627 add_unwind_entry (output_prologue_gr (mask, grsave));
3630 as_bad ("First operand not a constant");
3633 add_unwind_entry (output_prologue ());
3635 unwind.prologue = 1;
3636 unwind.prologue_mask = mask;
3645 int bytes_per_address;
3648 subsegT saved_subseg;
3650 saved_seg = now_seg;
3651 saved_subseg = now_subseg;
3654 demand_empty_rest_of_line ();
3656 insn_group_break (1, 0, 0);
3658 /* If there was a .handlerdata, we haven't generated an image yet. */
3659 if (unwind.info == 0)
3661 generate_unwind_image ();
3664 subseg_set (md.last_text_seg, 0);
3665 unwind.proc_end = expr_build_dot ();
3667 set_section ((char *) special_section_name[SPECIAL_SECTION_UNWIND]);
3668 ptr = frag_more (24);
3669 where = frag_now_fix () - 24;
3670 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
3672 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3673 e.X_op = O_pseudo_fixup;
3674 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3676 e.X_add_symbol = unwind.proc_start;
3677 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
3679 e.X_op = O_pseudo_fixup;
3680 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3682 e.X_add_symbol = unwind.proc_end;
3683 ia64_cons_fix_new (frag_now, where + bytes_per_address, bytes_per_address, &e);
3685 if (unwind.info != 0)
3687 e.X_op = O_pseudo_fixup;
3688 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
3690 e.X_add_symbol = unwind.info;
3691 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), bytes_per_address, &e);
3694 md_number_to_chars (ptr + (bytes_per_address * 2), 0, bytes_per_address);
3696 subseg_set (saved_seg, saved_subseg);
3697 unwind.proc_start = unwind.proc_end = unwind.info = 0;
3701 dot_template (template)
3704 CURR_SLOT.user_template = template;
3711 int ins, locs, outs, rots;
3713 if (is_it_end_of_statement ())
3714 ins = locs = outs = rots = 0;
3717 ins = get_absolute_expression ();
3718 if (*input_line_pointer++ != ',')
3720 locs = get_absolute_expression ();
3721 if (*input_line_pointer++ != ',')
3723 outs = get_absolute_expression ();
3724 if (*input_line_pointer++ != ',')
3726 rots = get_absolute_expression ();
3728 set_regstack (ins, locs, outs, rots);
3732 as_bad ("Comma expected");
3733 ignore_rest_of_line ();
3740 unsigned num_regs, num_alloced = 0;
3741 struct dynreg **drpp, *dr;
3742 int ch, base_reg = 0;
3748 case DYNREG_GR: base_reg = REG_GR + 32; break;
3749 case DYNREG_FR: base_reg = REG_FR + 32; break;
3750 case DYNREG_PR: base_reg = REG_P + 16; break;
3754 /* First, remove existing names from hash table. */
3755 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
3757 hash_delete (md.dynreg_hash, dr->name);
3761 drpp = &md.dynreg[type];
3764 start = input_line_pointer;
3765 ch = get_symbol_end ();
3766 *input_line_pointer = ch;
3767 len = (input_line_pointer - start);
3770 if (*input_line_pointer != '[')
3772 as_bad ("Expected '['");
3775 ++input_line_pointer; /* skip '[' */
3777 num_regs = get_absolute_expression ();
3779 if (*input_line_pointer++ != ']')
3781 as_bad ("Expected ']'");
3786 num_alloced += num_regs;
3790 if (num_alloced > md.rot.num_regs)
3792 as_bad ("Used more than the declared %d rotating registers",
3798 if (num_alloced > 96)
3800 as_bad ("Used more than the available 96 rotating registers");
3805 if (num_alloced > 48)
3807 as_bad ("Used more than the available 48 rotating registers");
3816 name = obstack_alloc (¬es, len + 1);
3817 memcpy (name, start, len);
3822 *drpp = obstack_alloc (¬es, sizeof (*dr));
3823 memset (*drpp, 0, sizeof (*dr));
3828 dr->num_regs = num_regs;
3829 dr->base = base_reg;
3831 base_reg += num_regs;
3833 if (hash_insert (md.dynreg_hash, name, dr))
3835 as_bad ("Attempt to redefine register set `%s'", name);
3839 if (*input_line_pointer != ',')
3841 ++input_line_pointer; /* skip comma */
3844 demand_empty_rest_of_line ();
3848 ignore_rest_of_line ();
3852 dot_byteorder (byteorder)
3855 target_big_endian = byteorder;
3867 option = input_line_pointer;
3868 ch = get_symbol_end ();
3869 if (strcmp (option, "lsb") == 0)
3870 md.flags &= ~EF_IA_64_BE;
3871 else if (strcmp (option, "msb") == 0)
3872 md.flags |= EF_IA_64_BE;
3873 else if (strcmp (option, "abi32") == 0)
3874 md.flags &= ~EF_IA_64_ABI64;
3875 else if (strcmp (option, "abi64") == 0)
3876 md.flags |= EF_IA_64_ABI64;
3878 as_bad ("Unknown psr option `%s'", option);
3879 *input_line_pointer = ch;
3882 if (*input_line_pointer != ',')
3885 ++input_line_pointer;
3888 demand_empty_rest_of_line ();
3895 as_bad (".alias not implemented yet");
3902 new_logical_line (0, get_absolute_expression ());
3903 demand_empty_rest_of_line ();
3907 parse_section_name ()
3913 if (*input_line_pointer != '"')
3915 as_bad ("Missing section name");
3916 ignore_rest_of_line ();
3919 name = demand_copy_C_string (&len);
3922 ignore_rest_of_line ();
3926 if (*input_line_pointer != ',')
3928 as_bad ("Comma expected after section name");
3929 ignore_rest_of_line ();
3932 ++input_line_pointer; /* skip comma */
3940 char *name = parse_section_name ();
3946 obj_elf_previous (0);
3949 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3952 stmt_float_cons (kind)
3959 case 'd': size = 8; break;
3960 case 'x': size = 10; break;
3967 ia64_do_align (size);
3975 int saved_auto_align = md.auto_align;
3979 md.auto_align = saved_auto_align;
3983 dot_xfloat_cons (kind)
3986 char *name = parse_section_name ();
3991 stmt_float_cons (kind);
3992 obj_elf_previous (0);
3996 dot_xstringer (zero)
3999 char *name = parse_section_name ();
4005 obj_elf_previous (0);
4012 int saved_auto_align = md.auto_align;
4013 char *name = parse_section_name ();
4020 md.auto_align = saved_auto_align;
4021 obj_elf_previous (0);
4025 dot_xfloat_cons_ua (kind)
4028 int saved_auto_align = md.auto_align;
4029 char *name = parse_section_name ();
4035 stmt_float_cons (kind);
4036 md.auto_align = saved_auto_align;
4037 obj_elf_previous (0);
4040 /* .reg.val <regname>,value */
4049 if (reg.X_op != O_register)
4051 as_bad (_("Register name expected"));
4052 ignore_rest_of_line ();
4054 else if (*input_line_pointer++ != ',')
4056 as_bad (_("Comma expected"));
4057 ignore_rest_of_line ();
4061 valueT value = get_absolute_expression ();
4062 int regno = reg.X_add_number;
4063 if (regno < REG_GR || regno > REG_GR + 128)
4064 as_warn (_("Register value annotation ignored"));
4067 gr_values[regno - REG_GR].known = 1;
4068 gr_values[regno - REG_GR].value = value;
4069 gr_values[regno - REG_GR].path = md.path;
4072 demand_empty_rest_of_line ();
4075 /* select dv checking mode
4080 A stop is inserted when changing modes
4087 if (md.manual_bundling)
4088 as_warn (_("Directive invalid within a bundle"));
4090 if (type == 'E' || type == 'A')
4091 md.mode_explicitly_set = 0;
4093 md.mode_explicitly_set = 1;
4100 if (md.explicit_mode)
4101 insn_group_break (1, 0, 0);
4102 md.explicit_mode = 0;
4106 if (!md.explicit_mode)
4107 insn_group_break (1, 0, 0);
4108 md.explicit_mode = 1;
4112 if (md.explicit_mode != md.default_explicit_mode)
4113 insn_group_break (1, 0, 0);
4114 md.explicit_mode = md.default_explicit_mode;
4115 md.mode_explicitly_set = 0;
4126 for (regno = 0; regno < 64; regno++)
4128 if (mask & ((valueT) 1 << regno))
4130 fprintf (stderr, "%s p%d", comma, regno);
4137 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4138 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4139 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4140 .pred.safe_across_calls p1 [, p2 [,...]]
4149 int p1 = -1, p2 = -1;
4153 if (*input_line_pointer != '"')
4155 as_bad (_("Missing predicate relation type"));
4156 ignore_rest_of_line ();
4162 char *form = demand_copy_C_string (&len);
4163 if (strcmp (form, "mutex") == 0)
4165 else if (strcmp (form, "clear") == 0)
4167 else if (strcmp (form, "imply") == 0)
4171 as_bad (_("Unrecognized predicate relation type"));
4172 ignore_rest_of_line ();
4176 if (*input_line_pointer == ',')
4177 ++input_line_pointer;
4187 if (toupper (*input_line_pointer) != 'P'
4188 || (regno = atoi (++input_line_pointer)) < 0
4191 as_bad (_("Predicate register expected"));
4192 ignore_rest_of_line ();
4195 while (isdigit (*input_line_pointer))
4196 ++input_line_pointer;
4203 as_warn (_("Duplicate predicate register ignored"));
4206 /* See if it's a range. */
4207 if (*input_line_pointer == '-')
4210 ++input_line_pointer;
4212 if (toupper (*input_line_pointer) != 'P'
4213 || (regno = atoi (++input_line_pointer)) < 0
4216 as_bad (_("Predicate register expected"));
4217 ignore_rest_of_line ();
4220 while (isdigit (*input_line_pointer))
4221 ++input_line_pointer;
4225 as_bad (_("Bad register range"));
4226 ignore_rest_of_line ();
4237 if (*input_line_pointer != ',')
4239 ++input_line_pointer;
4248 clear_qp_mutex (mask);
4249 clear_qp_implies (mask, (valueT) 0);
4252 if (count != 2 || p1 == -1 || p2 == -1)
4253 as_bad (_("Predicate source and target required"));
4254 else if (p1 == 0 || p2 == 0)
4255 as_bad (_("Use of p0 is not valid in this context"));
4257 add_qp_imply (p1, p2);
4262 as_bad (_("At least two PR arguments expected"));
4267 as_bad (_("Use of p0 is not valid in this context"));
4270 add_qp_mutex (mask);
4273 /* note that we don't override any existing relations */
4276 as_bad (_("At least one PR argument expected"));
4281 fprintf (stderr, "Safe across calls: ");
4282 print_prmask (mask);
4283 fprintf (stderr, "\n");
4285 qp_safe_across_calls = mask;
4288 demand_empty_rest_of_line ();
4291 /* .entry label [, label [, ...]]
4292 Hint to DV code that the given labels are to be considered entry points.
4293 Otherwise, only global labels are considered entry points. */
4306 name = input_line_pointer;
4307 c = get_symbol_end ();
4308 symbolP = symbol_find_or_make (name);
4310 err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP);
4312 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4315 *input_line_pointer = c;
4317 c = *input_line_pointer;
4320 input_line_pointer++;
4322 if (*input_line_pointer == '\n')
4328 demand_empty_rest_of_line ();
4331 /* .mem.offset offset, base
4332 "base" is used to distinguish between offsets from a different base. */
4335 dot_mem_offset (dummy)
4338 md.mem_offset.hint = 1;
4339 md.mem_offset.offset = get_absolute_expression ();
4340 if (*input_line_pointer != ',')
4342 as_bad (_("Comma expected"));
4343 ignore_rest_of_line ();
4346 ++input_line_pointer;
4347 md.mem_offset.base = get_absolute_expression ();
4348 demand_empty_rest_of_line ();
4351 /* ia64-specific pseudo-ops: */
4352 const pseudo_typeS md_pseudo_table[] =
4354 { "radix", dot_radix, 0 },
4355 { "lcomm", s_lcomm_bytes, 1 },
4356 { "bss", dot_special_section, SPECIAL_SECTION_BSS },
4357 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
4358 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
4359 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA },
4360 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT },
4361 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND },
4362 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO },
4363 { "proc", dot_proc, 0 },
4364 { "body", dot_body, 0 },
4365 { "prologue", dot_prologue, 0 },
4366 { "endp", dot_endp },
4367 { "file", dwarf2_directive_file },
4368 { "loc", dwarf2_directive_loc },
4370 { "fframe", dot_fframe },
4371 { "vframe", dot_vframe },
4372 { "vframesp", dot_vframesp },
4373 { "vframepsp", dot_vframepsp },
4374 { "save", dot_save },
4375 { "restore", dot_restore },
4376 { "restorereg", dot_restorereg },
4377 { "restorereg.p", dot_restorereg_p },
4378 { "handlerdata", dot_handlerdata },
4379 { "unwentry", dot_unwentry },
4380 { "altrp", dot_altrp },
4381 { "savesp", dot_savemem, 0 },
4382 { "savepsp", dot_savemem, 1 },
4383 { "save.g", dot_saveg },
4384 { "save.f", dot_savef },
4385 { "save.b", dot_saveb },
4386 { "save.gf", dot_savegf },
4387 { "spill", dot_spill },
4388 { "spillreg", dot_spillreg },
4389 { "spillsp", dot_spillmem, 0 },
4390 { "spillpsp", dot_spillmem, 1 },
4391 { "spillreg.p", dot_spillreg_p },
4392 { "spillsp.p", dot_spillmem_p, 0 },
4393 { "spillpsp.p", dot_spillmem_p, 1 },
4394 { "label_state", dot_label_state },
4395 { "copy_state", dot_copy_state },
4396 { "unwabi", dot_unwabi },
4397 { "personality", dot_personality },
4399 { "estate", dot_estate },
4401 { "mii", dot_template, 0x0 },
4402 { "mli", dot_template, 0x2 }, /* old format, for compatibility */
4403 { "mlx", dot_template, 0x2 },
4404 { "mmi", dot_template, 0x4 },
4405 { "mfi", dot_template, 0x6 },
4406 { "mmf", dot_template, 0x7 },
4407 { "mib", dot_template, 0x8 },
4408 { "mbb", dot_template, 0x9 },
4409 { "bbb", dot_template, 0xb },
4410 { "mmb", dot_template, 0xc },
4411 { "mfb", dot_template, 0xe },
4413 { "lb", dot_scope, 0 },
4414 { "le", dot_scope, 1 },
4416 { "align", s_align_bytes, 0 },
4417 { "regstk", dot_regstk, 0 },
4418 { "rotr", dot_rot, DYNREG_GR },
4419 { "rotf", dot_rot, DYNREG_FR },
4420 { "rotp", dot_rot, DYNREG_PR },
4421 { "lsb", dot_byteorder, 0 },
4422 { "msb", dot_byteorder, 1 },
4423 { "psr", dot_psr, 0 },
4424 { "alias", dot_alias, 0 },
4425 { "ln", dot_ln, 0 }, /* source line info (for debugging) */
4427 { "xdata1", dot_xdata, 1 },
4428 { "xdata2", dot_xdata, 2 },
4429 { "xdata4", dot_xdata, 4 },
4430 { "xdata8", dot_xdata, 8 },
4431 { "xreal4", dot_xfloat_cons, 'f' },
4432 { "xreal8", dot_xfloat_cons, 'd' },
4433 { "xreal10", dot_xfloat_cons, 'x' },
4434 { "xstring", dot_xstringer, 0 },
4435 { "xstringz", dot_xstringer, 1 },
4437 /* unaligned versions: */
4438 { "xdata2.ua", dot_xdata_ua, 2 },
4439 { "xdata4.ua", dot_xdata_ua, 4 },
4440 { "xdata8.ua", dot_xdata_ua, 8 },
4441 { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
4442 { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
4443 { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
4445 /* annotations/DV checking support */
4446 { "entry", dot_entry, 0 },
4447 { "mem.offset", dot_mem_offset },
4448 { "pred.rel", dot_pred_rel, 0 },
4449 { "pred.rel.clear", dot_pred_rel, 'c' },
4450 { "pred.rel.imply", dot_pred_rel, 'i' },
4451 { "pred.rel.mutex", dot_pred_rel, 'm' },
4452 { "pred.safe_across_calls", dot_pred_rel, 's' },
4453 { "reg.val", dot_reg_val },
4454 { "auto", dot_dv_mode, 'a' },
4455 { "explicit", dot_dv_mode, 'e' },
4456 { "default", dot_dv_mode, 'd' },
4461 static const struct pseudo_opcode
4464 void (*handler) (int);
4469 /* these are more like pseudo-ops, but don't start with a dot */
4470 { "data1", cons, 1 },
4471 { "data2", cons, 2 },
4472 { "data4", cons, 4 },
4473 { "data8", cons, 8 },
4474 { "real4", stmt_float_cons, 'f' },
4475 { "real8", stmt_float_cons, 'd' },
4476 { "real10", stmt_float_cons, 'x' },
4477 { "string", stringer, 0 },
4478 { "stringz", stringer, 1 },
4480 /* unaligned versions: */
4481 { "data2.ua", stmt_cons_ua, 2 },
4482 { "data4.ua", stmt_cons_ua, 4 },
4483 { "data8.ua", stmt_cons_ua, 8 },
4484 { "real4.ua", float_cons, 'f' },
4485 { "real8.ua", float_cons, 'd' },
4486 { "real10.ua", float_cons, 'x' },
4489 /* Declare a register by creating a symbol for it and entering it in
4490 the symbol table. */
4493 declare_register (name, regnum)
4500 sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
4502 err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
4504 as_fatal ("Inserting \"%s\" into register table failed: %s",
4511 declare_register_set (prefix, num_regs, base_regnum)
4519 for (i = 0; i < num_regs; ++i)
4521 sprintf (name, "%s%u", prefix, i);
4522 declare_register (name, base_regnum + i);
4527 operand_width (opnd)
4528 enum ia64_opnd opnd;
4530 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd];
4531 unsigned int bits = 0;
4535 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i)
4536 bits += odesc->field[i].bits;
4542 operand_match (idesc, index, e)
4543 const struct ia64_opcode *idesc;
4547 enum ia64_opnd opnd = idesc->operands[index];
4548 int bits, relocatable = 0;
4549 struct insn_fix *fix;
4556 case IA64_OPND_AR_CCV:
4557 if (e->X_op == O_register && e->X_add_number == REG_AR + 32)
4561 case IA64_OPND_AR_PFS:
4562 if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
4567 if (e->X_op == O_register && e->X_add_number == REG_GR + 0)
4572 if (e->X_op == O_register && e->X_add_number == REG_IP)
4577 if (e->X_op == O_register && e->X_add_number == REG_PR)
4581 case IA64_OPND_PR_ROT:
4582 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT)
4587 if (e->X_op == O_register && e->X_add_number == REG_PSR)
4591 case IA64_OPND_PSR_L:
4592 if (e->X_op == O_register && e->X_add_number == REG_PSR_L)
4596 case IA64_OPND_PSR_UM:
4597 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM)
4602 if (e->X_op == O_constant && e->X_add_number == 1)
4607 if (e->X_op == O_constant && e->X_add_number == 8)
4612 if (e->X_op == O_constant && e->X_add_number == 16)
4616 /* register operands: */
4619 if (e->X_op == O_register && e->X_add_number >= REG_AR
4620 && e->X_add_number < REG_AR + 128)
4626 if (e->X_op == O_register && e->X_add_number >= REG_BR
4627 && e->X_add_number < REG_BR + 8)
4632 if (e->X_op == O_register && e->X_add_number >= REG_CR
4633 && e->X_add_number < REG_CR + 128)
4641 if (e->X_op == O_register && e->X_add_number >= REG_FR
4642 && e->X_add_number < REG_FR + 128)
4648 if (e->X_op == O_register && e->X_add_number >= REG_P
4649 && e->X_add_number < REG_P + 64)
4656 if (e->X_op == O_register && e->X_add_number >= REG_GR
4657 && e->X_add_number < REG_GR + 128)
4661 case IA64_OPND_R3_2:
4662 if (e->X_op == O_register && e->X_add_number >= REG_GR
4663 && e->X_add_number < REG_GR + 4)
4667 /* indirect operands: */
4668 case IA64_OPND_CPUID_R3:
4669 case IA64_OPND_DBR_R3:
4670 case IA64_OPND_DTR_R3:
4671 case IA64_OPND_ITR_R3:
4672 case IA64_OPND_IBR_R3:
4673 case IA64_OPND_MSR_R3:
4674 case IA64_OPND_PKR_R3:
4675 case IA64_OPND_PMC_R3:
4676 case IA64_OPND_PMD_R3:
4677 case IA64_OPND_RR_R3:
4678 if (e->X_op == O_index && e->X_op_symbol
4679 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
4680 == opnd - IA64_OPND_CPUID_R3))
4685 if (e->X_op == O_index && !e->X_op_symbol)
4689 /* immediate operands: */
4690 case IA64_OPND_CNT2a:
4691 case IA64_OPND_LEN4:
4692 case IA64_OPND_LEN6:
4693 bits = operand_width (idesc->operands[index]);
4694 if (e->X_op == O_constant
4695 && (bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits))
4699 case IA64_OPND_CNT2b:
4700 if (e->X_op == O_constant
4701 && (bfd_vma) (e->X_add_number - 1) < 3)
4705 case IA64_OPND_CNT2c:
4706 val = e->X_add_number;
4707 if (e->X_op == O_constant
4708 && (val == 0 || val == 7 || val == 15 || val == 16))
4713 /* SOR must be an integer multiple of 8 */
4714 if (e->X_add_number & 0x7)
4718 if (e->X_op == O_constant &&
4719 (bfd_vma) e->X_add_number <= 96)
4723 case IA64_OPND_IMMU62:
4724 if (e->X_op == O_constant)
4726 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62))
4731 /* FIXME -- need 62-bit relocation type */
4732 as_bad (_("62-bit relocation not yet implemented"));
4736 case IA64_OPND_IMMU64:
4737 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup
4738 || e->X_op == O_subtract)
4740 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4741 fix->code = BFD_RELOC_IA64_IMM64;
4742 if (e->X_op != O_subtract)
4744 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4745 if (e->X_op == O_pseudo_fixup)
4749 fix->opnd = idesc->operands[index];
4752 ++CURR_SLOT.num_fixups;
4755 else if (e->X_op == O_constant)
4759 case IA64_OPND_CCNT5:
4760 case IA64_OPND_CNT5:
4761 case IA64_OPND_CNT6:
4762 case IA64_OPND_CPOS6a:
4763 case IA64_OPND_CPOS6b:
4764 case IA64_OPND_CPOS6c:
4765 case IA64_OPND_IMMU2:
4766 case IA64_OPND_IMMU7a:
4767 case IA64_OPND_IMMU7b:
4768 case IA64_OPND_IMMU21:
4769 case IA64_OPND_IMMU24:
4770 case IA64_OPND_MBTYPE4:
4771 case IA64_OPND_MHTYPE8:
4772 case IA64_OPND_POS6:
4773 bits = operand_width (idesc->operands[index]);
4774 if (e->X_op == O_constant
4775 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4779 case IA64_OPND_IMMU9:
4780 bits = operand_width (idesc->operands[index]);
4781 if (e->X_op == O_constant
4782 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits))
4784 int lobits = e->X_add_number & 0x3;
4785 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0)
4786 e->X_add_number |= (bfd_vma) 0x3;
4791 case IA64_OPND_IMM44:
4792 /* least 16 bits must be zero */
4793 if ((e->X_add_number & 0xffff) != 0)
4794 as_warn (_("lower 16 bits of mask ignored"));
4796 if (e->X_op == O_constant
4797 && ((e->X_add_number >= 0
4798 && e->X_add_number < ((bfd_vma) 1 << 44))
4799 || (e->X_add_number < 0
4800 && -e->X_add_number <= ((bfd_vma) 1 << 44))))
4803 if (e->X_add_number >= 0
4804 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0)
4806 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1);
4812 case IA64_OPND_IMM17:
4813 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4814 if (e->X_op == O_constant
4815 && ((e->X_add_number >= 0
4816 && e->X_add_number < ((bfd_vma) 1 << 17))
4817 || (e->X_add_number < 0
4818 && -e->X_add_number <= ((bfd_vma) 1 << 17))))
4821 if (e->X_add_number >= 0
4822 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0)
4824 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1);
4830 case IA64_OPND_IMM14:
4831 case IA64_OPND_IMM22:
4833 case IA64_OPND_IMM1:
4834 case IA64_OPND_IMM8:
4835 case IA64_OPND_IMM8U4:
4836 case IA64_OPND_IMM8M1:
4837 case IA64_OPND_IMM8M1U4:
4838 case IA64_OPND_IMM8M1U8:
4839 case IA64_OPND_IMM9a:
4840 case IA64_OPND_IMM9b:
4841 bits = operand_width (idesc->operands[index]);
4842 if (relocatable && (e->X_op == O_symbol
4843 || e->X_op == O_subtract
4844 || e->X_op == O_pseudo_fixup))
4846 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4848 if (idesc->operands[index] == IA64_OPND_IMM14)
4849 fix->code = BFD_RELOC_IA64_IMM14;
4851 fix->code = BFD_RELOC_IA64_IMM22;
4853 if (e->X_op != O_subtract)
4855 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4856 if (e->X_op == O_pseudo_fixup)
4860 fix->opnd = idesc->operands[index];
4863 ++CURR_SLOT.num_fixups;
4866 else if (e->X_op != O_constant
4867 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8))
4870 if (opnd == IA64_OPND_IMM8M1U4)
4872 /* Zero is not valid for unsigned compares that take an adjusted
4873 constant immediate range. */
4874 if (e->X_add_number == 0)
4877 /* Sign-extend 32-bit unsigned numbers, so that the following range
4878 checks will work. */
4879 val = e->X_add_number;
4880 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4881 && ((val & ((bfd_vma) 1 << 31)) != 0))
4882 val = ((val << 32) >> 32);
4884 /* Check for 0x100000000. This is valid because
4885 0x100000000-1 is the same as ((uint32_t) -1). */
4886 if (val == ((bfd_signed_vma) 1 << 32))
4891 else if (opnd == IA64_OPND_IMM8M1U8)
4893 /* Zero is not valid for unsigned compares that take an adjusted
4894 constant immediate range. */
4895 if (e->X_add_number == 0)
4898 /* Check for 0x10000000000000000. */
4899 if (e->X_op == O_big)
4901 if (generic_bignum[0] == 0
4902 && generic_bignum[1] == 0
4903 && generic_bignum[2] == 0
4904 && generic_bignum[3] == 0
4905 && generic_bignum[4] == 1)
4911 val = e->X_add_number - 1;
4913 else if (opnd == IA64_OPND_IMM8M1)
4914 val = e->X_add_number - 1;
4915 else if (opnd == IA64_OPND_IMM8U4)
4917 /* Sign-extend 32-bit unsigned numbers, so that the following range
4918 checks will work. */
4919 val = e->X_add_number;
4920 if (((val & (~(bfd_vma) 0 << 32)) == 0)
4921 && ((val & ((bfd_vma) 1 << 31)) != 0))
4922 val = ((val << 32) >> 32);
4925 val = e->X_add_number;
4927 if ((val >= 0 && val < ((bfd_vma) 1 << (bits - 1)))
4928 || (val < 0 && -val <= ((bfd_vma) 1 << (bits - 1))))
4932 case IA64_OPND_INC3:
4933 /* +/- 1, 4, 8, 16 */
4934 val = e->X_add_number;
4937 if (e->X_op == O_constant
4938 && (val == 1 || val == 4 || val == 8 || val == 16))
4942 case IA64_OPND_TGT25:
4943 case IA64_OPND_TGT25b:
4944 case IA64_OPND_TGT25c:
4945 case IA64_OPND_TGT64:
4946 if (e->X_op == O_symbol)
4948 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4949 if (opnd == IA64_OPND_TGT25)
4950 fix->code = BFD_RELOC_IA64_PCREL21F;
4951 else if (opnd == IA64_OPND_TGT25b)
4952 fix->code = BFD_RELOC_IA64_PCREL21M;
4953 else if (opnd == IA64_OPND_TGT25c)
4954 fix->code = BFD_RELOC_IA64_PCREL21B;
4955 else if (opnd == IA64_OPND_TGT64)
4956 fix->code = BFD_RELOC_IA64_PCREL60B;
4960 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
4961 fix->opnd = idesc->operands[index];
4964 ++CURR_SLOT.num_fixups;
4967 case IA64_OPND_TAG13:
4968 case IA64_OPND_TAG13b:
4975 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
4976 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, 0);
4977 fix->opnd = idesc->operands[index];
4980 ++CURR_SLOT.num_fixups;
5000 memset (e, 0, sizeof (*e));
5003 if (*input_line_pointer != '}')
5005 sep = *input_line_pointer++;
5009 if (!md.manual_bundling)
5010 as_warn ("Found '}' when manual bundling is off");
5012 CURR_SLOT.manual_bundling_off = 1;
5013 md.manual_bundling = 0;
5019 /* Returns the next entry in the opcode table that matches the one in
5020 IDESC, and frees the entry in IDESC. If no matching entry is
5021 found, NULL is returned instead. */
5023 static struct ia64_opcode *
5024 get_next_opcode (struct ia64_opcode *idesc)
5026 struct ia64_opcode *next = ia64_find_next_opcode (idesc);
5027 ia64_free_opcode (idesc);
5031 /* Parse the operands for the opcode and find the opcode variant that
5032 matches the specified operands, or NULL if no match is possible. */
5034 static struct ia64_opcode *
5035 parse_operands (idesc)
5036 struct ia64_opcode *idesc;
5038 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
5040 enum ia64_opnd expected_operand = IA64_OPND_NIL;
5042 char *first_arg = 0, *end, *saved_input_pointer;
5045 assert (strlen (idesc->name) <= 128);
5047 strcpy (mnemonic, idesc->name);
5048 if (idesc->operands[2] == IA64_OPND_SOF)
5050 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5051 can't parse the first operand until we have parsed the
5052 remaining operands of the "alloc" instruction. */
5054 first_arg = input_line_pointer;
5055 end = strchr (input_line_pointer, '=');
5058 as_bad ("Expected separator `='");
5061 input_line_pointer = end + 1;
5066 for (; i < NELEMS (CURR_SLOT.opnd); ++i)
5068 sep = parse_operand (CURR_SLOT.opnd + i);
5069 if (CURR_SLOT.opnd[i].X_op == O_absent)
5074 if (sep != '=' && sep != ',')
5079 if (num_outputs > 0)
5080 as_bad ("Duplicate equal sign (=) in instruction");
5082 num_outputs = i + 1;
5087 as_bad ("Illegal operand separator `%c'", sep);
5091 if (idesc->operands[2] == IA64_OPND_SOF)
5093 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5094 know (strcmp (idesc->name, "alloc") == 0);
5095 if (num_operands == 5 /* first_arg not included in this count! */
5096 && CURR_SLOT.opnd[2].X_op == O_constant
5097 && CURR_SLOT.opnd[3].X_op == O_constant
5098 && CURR_SLOT.opnd[4].X_op == O_constant
5099 && CURR_SLOT.opnd[5].X_op == O_constant)
5101 sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
5102 CURR_SLOT.opnd[3].X_add_number,
5103 CURR_SLOT.opnd[4].X_add_number,
5104 CURR_SLOT.opnd[5].X_add_number);
5106 /* now we can parse the first arg: */
5107 saved_input_pointer = input_line_pointer;
5108 input_line_pointer = first_arg;
5109 sep = parse_operand (CURR_SLOT.opnd + 0);
5111 --num_outputs; /* force error */
5112 input_line_pointer = saved_input_pointer;
5114 CURR_SLOT.opnd[2].X_add_number = sof;
5115 CURR_SLOT.opnd[3].X_add_number
5116 = sof - CURR_SLOT.opnd[4].X_add_number;
5117 CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
5121 highest_unmatched_operand = 0;
5122 expected_operand = idesc->operands[0];
5123 for (; idesc; idesc = get_next_opcode (idesc))
5125 if (num_outputs != idesc->num_outputs)
5126 continue; /* mismatch in # of outputs */
5128 CURR_SLOT.num_fixups = 0;
5129 for (i = 0; i < num_operands && idesc->operands[i]; ++i)
5130 if (!operand_match (idesc, i, CURR_SLOT.opnd + i))
5133 if (i != num_operands)
5135 if (i > highest_unmatched_operand)
5137 highest_unmatched_operand = i;
5138 expected_operand = idesc->operands[i];
5143 if (num_operands < NELEMS (idesc->operands)
5144 && idesc->operands[num_operands])
5145 continue; /* mismatch in number of arguments */
5151 if (expected_operand)
5152 as_bad ("Operand %u of `%s' should be %s",
5153 highest_unmatched_operand + 1, mnemonic,
5154 elf64_ia64_operands[expected_operand].desc);
5156 as_bad ("Operand mismatch");
5163 build_insn (slot, insnp)
5167 const struct ia64_operand *odesc, *o2desc;
5168 struct ia64_opcode *idesc = slot->idesc;
5169 bfd_signed_vma insn, val;
5173 insn = idesc->opcode | slot->qp_regno;
5175 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i)
5177 if (slot->opnd[i].X_op == O_register
5178 || slot->opnd[i].X_op == O_constant
5179 || slot->opnd[i].X_op == O_index)
5180 val = slot->opnd[i].X_add_number;
5181 else if (slot->opnd[i].X_op == O_big)
5183 /* This must be the value 0x10000000000000000. */
5184 assert (idesc->operands[i] == IA64_OPND_IMM8M1U8);
5190 switch (idesc->operands[i])
5192 case IA64_OPND_IMMU64:
5193 *insnp++ = (val >> 22) & 0x1ffffffffffLL;
5194 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27)
5195 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21)
5196 | (((val >> 63) & 0x1) << 36));
5199 case IA64_OPND_IMMU62:
5200 val &= 0x3fffffffffffffffULL;
5201 if (val != slot->opnd[i].X_add_number)
5202 as_warn (_("Value truncated to 62 bits"));
5203 *insnp++ = (val >> 21) & 0x1ffffffffffLL;
5204 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36));
5207 case IA64_OPND_TGT64:
5209 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2;
5210 insn |= ((((val >> 59) & 0x1) << 36)
5211 | (((val >> 0) & 0xfffff) << 13));
5242 case IA64_OPND_R3_2:
5243 case IA64_OPND_CPUID_R3:
5244 case IA64_OPND_DBR_R3:
5245 case IA64_OPND_DTR_R3:
5246 case IA64_OPND_ITR_R3:
5247 case IA64_OPND_IBR_R3:
5249 case IA64_OPND_MSR_R3:
5250 case IA64_OPND_PKR_R3:
5251 case IA64_OPND_PMC_R3:
5252 case IA64_OPND_PMD_R3:
5253 case IA64_OPND_RR_R3:
5261 odesc = elf64_ia64_operands + idesc->operands[i];
5262 err = (*odesc->insert) (odesc, val, &insn);
5264 as_bad_where (slot->src_file, slot->src_line,
5265 "Bad operand value: %s", err);
5266 if (idesc->flags & IA64_OPCODE_PSEUDO)
5268 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3)
5269 && odesc == elf64_ia64_operands + IA64_OPND_F3)
5271 o2desc = elf64_ia64_operands + IA64_OPND_F2;
5272 (*o2desc->insert) (o2desc, val, &insn);
5274 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT)
5275 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a
5276 || odesc == elf64_ia64_operands + IA64_OPND_POS6))
5278 o2desc = elf64_ia64_operands + IA64_OPND_LEN6;
5279 (*o2desc->insert) (o2desc, 64 - val, &insn);
5289 unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
5290 unsigned int manual_bundling = 0;
5291 enum ia64_unit required_unit, insn_unit = 0;
5292 enum ia64_insn_type type[3], insn_type;
5293 unsigned int template, orig_template;
5294 bfd_vma insn[3] = { -1, -1, -1 };
5295 struct ia64_opcode *idesc;
5296 int end_of_insn_group = 0, user_template = -1;
5297 int n, i, j, first, curr;
5298 unw_rec_list *ptr, *prev;
5299 bfd_vma t0 = 0, t1 = 0;
5300 struct label_fix *lfix;
5301 struct insn_fix *ifix;
5306 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
5307 know (first >= 0 & first < NUM_SLOTS);
5308 n = MIN (3, md.num_slots_in_use);
5310 /* Determine template: user user_template if specified, best match
5313 if (md.slot[first].user_template >= 0)
5314 user_template = template = md.slot[first].user_template;
5317 /* Auto select appropriate template. */
5318 memset (type, 0, sizeof (type));
5320 for (i = 0; i < n; ++i)
5322 if (md.slot[curr].label_fixups && i != 0)
5324 type[i] = md.slot[curr].idesc->type;
5325 curr = (curr + 1) % NUM_SLOTS;
5327 template = best_template[type[0]][type[1]][type[2]];
5330 /* initialize instructions with appropriate nops: */
5331 for (i = 0; i < 3; ++i)
5332 insn[i] = nop[ia64_templ_desc[template].exec_unit[i]];
5336 /* now fill in slots with as many insns as possible: */
5338 idesc = md.slot[curr].idesc;
5339 end_of_insn_group = 0;
5340 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
5342 /* Set the slot number for prologue/body records now as those
5343 refer to the current point, not the point after the
5344 instruction has been issued: */
5345 /* Don't try to delete prologue/body records here, as that will cause
5346 them to also be deleted from the master list of unwind records. */
5347 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5348 if (ptr->r.type == prologue || ptr->r.type == prologue_gr
5349 || ptr->r.type == body)
5351 ptr->slot_number = (unsigned long) f + i;
5352 ptr->slot_frag = frag_now;
5355 if (idesc->flags & IA64_OPCODE_SLOT2)
5357 if (manual_bundling && i != 2)
5358 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5359 "`%s' must be last in bundle", idesc->name);
5363 if (idesc->flags & IA64_OPCODE_LAST)
5365 int required_slot, required_template;
5367 /* If we need a stop bit after an M slot, our only choice is
5368 template 5 (M;;MI). If we need a stop bit after a B
5369 slot, our only choice is to place it at the end of the
5370 bundle, because the only available templates are MIB,
5371 MBB, BBB, MMB, and MFB. We don't handle anything other
5372 than M and B slots because these are the only kind of
5373 instructions that can have the IA64_OPCODE_LAST bit set. */
5374 required_template = template;
5375 switch (idesc->type)
5379 required_template = 5;
5387 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5388 "Internal error: don't know how to force %s to end"
5389 "of instruction group", idesc->name);
5393 if (manual_bundling && i != required_slot)
5394 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5395 "`%s' must be last in instruction group",
5397 if (required_slot < i)
5398 /* Can't fit this instruction. */
5402 if (required_template != template)
5404 /* If we switch the template, we need to reset the NOPs
5405 after slot i. The slot-types of the instructions ahead
5406 of i never change, so we don't need to worry about
5407 changing NOPs in front of this slot. */
5408 for (j = i; j < 3; ++j)
5409 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
5411 template = required_template;
5413 if (curr != first && md.slot[curr].label_fixups)
5415 if (manual_bundling_on)
5416 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5417 "Label must be first in a bundle");
5418 /* This insn must go into the first slot of a bundle. */
5422 manual_bundling_on = md.slot[curr].manual_bundling_on;
5423 manual_bundling_off = md.slot[curr].manual_bundling_off;
5425 if (manual_bundling_on)
5428 manual_bundling = 1;
5430 break; /* need to start a new bundle */
5433 if (end_of_insn_group && md.num_slots_in_use >= 1)
5435 /* We need an instruction group boundary in the middle of a
5436 bundle. See if we can switch to an other template with
5437 an appropriate boundary. */
5439 orig_template = template;
5440 if (i == 1 && (user_template == 4
5441 || (user_template < 0
5442 && (ia64_templ_desc[template].exec_unit[0]
5446 end_of_insn_group = 0;
5448 else if (i == 2 && (user_template == 0
5449 || (user_template < 0
5450 && (ia64_templ_desc[template].exec_unit[1]
5452 /* This test makes sure we don't switch the template if
5453 the next instruction is one that needs to be first in
5454 an instruction group. Since all those instructions are
5455 in the M group, there is no way such an instruction can
5456 fit in this bundle even if we switch the template. The
5457 reason we have to check for this is that otherwise we
5458 may end up generating "MI;;I M.." which has the deadly
5459 effect that the second M instruction is no longer the
5460 first in the bundle! --davidm 99/12/16 */
5461 && (idesc->flags & IA64_OPCODE_FIRST) == 0)
5464 end_of_insn_group = 0;
5466 else if (curr != first)
5467 /* can't fit this insn */
5470 if (template != orig_template)
5471 /* if we switch the template, we need to reset the NOPs
5472 after slot i. The slot-types of the instructions ahead
5473 of i never change, so we don't need to worry about
5474 changing NOPs in front of this slot. */
5475 for (j = i; j < 3; ++j)
5476 insn[j] = nop[ia64_templ_desc[template].exec_unit[j]];
5478 required_unit = ia64_templ_desc[template].exec_unit[i];
5480 /* resolve dynamic opcodes such as "break" and "nop": */
5481 if (idesc->type == IA64_TYPE_DYN)
5483 if ((strcmp (idesc->name, "nop") == 0)
5484 || (strcmp (idesc->name, "break") == 0))
5485 insn_unit = required_unit;
5486 else if (strcmp (idesc->name, "chk.s") == 0)
5488 insn_unit = IA64_UNIT_M;
5489 if (required_unit == IA64_UNIT_I)
5490 insn_unit = IA64_UNIT_I;
5493 as_fatal ("emit_one_bundle: unexpected dynamic op");
5495 sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
5496 ia64_free_opcode (idesc);
5497 md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
5499 know (!idesc->next); /* no resolved dynamic ops have collisions */
5504 insn_type = idesc->type;
5505 insn_unit = IA64_UNIT_NIL;
5509 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M)
5510 insn_unit = required_unit;
5512 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break;
5513 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break;
5514 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break;
5515 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break;
5516 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break;
5521 if (insn_unit != required_unit)
5523 if (required_unit == IA64_UNIT_L
5524 && insn_unit == IA64_UNIT_I
5525 && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
5527 /* we got ourselves an MLX template but the current
5528 instruction isn't an X-unit, or an I-unit instruction
5529 that can go into the X slot of an MLX template. Duh. */
5530 if (md.num_slots_in_use >= NUM_SLOTS)
5532 as_bad_where (md.slot[curr].src_file,
5533 md.slot[curr].src_line,
5534 "`%s' can't go in X slot of "
5535 "MLX template", idesc->name);
5536 /* drop this insn so we don't livelock: */
5537 --md.num_slots_in_use;
5541 continue; /* try next slot */
5544 if (debug_type == DEBUG_DWARF2)
5548 addr = frag_now->fr_address + frag_now_fix () - 16 + i;
5549 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
5552 build_insn (md.slot + curr, insn + i);
5554 /* Set slot counts for non prologue/body unwind records. */
5555 for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next)
5556 if (ptr->r.type != prologue && ptr->r.type != prologue_gr
5557 && ptr->r.type != body)
5559 ptr->slot_number = (unsigned long) f + i;
5560 ptr->slot_frag = frag_now;
5562 md.slot[curr].unwind_record = NULL;
5564 if (required_unit == IA64_UNIT_L)
5567 /* skip one slot for long/X-unit instructions */
5570 --md.num_slots_in_use;
5572 /* now is a good time to fix up the labels for this insn: */
5573 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
5575 S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
5576 symbol_set_frag (lfix->sym, frag_now);
5578 /* and fix up the tags also. */
5579 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
5581 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
5582 symbol_set_frag (lfix->sym, frag_now);
5585 for (j = 0; j < md.slot[curr].num_fixups; ++j)
5587 ifix = md.slot[curr].fixup + j;
5588 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 4,
5589 &ifix->expr, ifix->is_pcrel, ifix->code);
5590 fix->tc_fix_data.opnd = ifix->opnd;
5591 fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22);
5592 fix->fx_file = md.slot[curr].src_file;
5593 fix->fx_line = md.slot[curr].src_line;
5596 end_of_insn_group = md.slot[curr].end_of_insn_group;
5599 ia64_free_opcode (md.slot[curr].idesc);
5600 memset (md.slot + curr, 0, sizeof (md.slot[curr]));
5601 md.slot[curr].user_template = -1;
5603 if (manual_bundling_off)
5605 manual_bundling = 0;
5608 curr = (curr + 1) % NUM_SLOTS;
5609 idesc = md.slot[curr].idesc;
5611 if (manual_bundling)
5613 if (md.num_slots_in_use > 0)
5614 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5615 "`%s' does not fit into %s template",
5616 idesc->name, ia64_templ_desc[template].name);
5618 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
5619 "Missing '}' at end of file");
5621 know (md.num_slots_in_use < NUM_SLOTS);
5623 t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
5624 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
5626 number_to_chars_littleendian (f + 0, t0, 8);
5627 number_to_chars_littleendian (f + 8, t1, 8);
5629 unwind.next_slot_number = (unsigned long) f + 16;
5630 unwind.next_slot_frag = frag_now;
5634 md_parse_option (c, arg)
5640 /* Switches from the Intel assembler. */
5642 if (strcmp (arg, "ilp64") == 0
5643 || strcmp (arg, "lp64") == 0
5644 || strcmp (arg, "p64") == 0)
5646 md.flags |= EF_IA_64_ABI64;
5648 else if (strcmp (arg, "ilp32") == 0)
5650 md.flags &= ~EF_IA_64_ABI64;
5652 else if (strcmp (arg, "le") == 0)
5654 md.flags &= ~EF_IA_64_BE;
5656 else if (strcmp (arg, "be") == 0)
5658 md.flags |= EF_IA_64_BE;
5665 if (strcmp (arg, "so") == 0)
5667 /* Suppress signon message. */
5669 else if (strcmp (arg, "pi") == 0)
5671 /* Reject privileged instructions. FIXME */
5673 else if (strcmp (arg, "us") == 0)
5675 /* Allow union of signed and unsigned range. FIXME */
5677 else if (strcmp (arg, "close_fcalls") == 0)
5679 /* Do not resolve global function calls. */
5686 /* temp[="prefix"] Insert temporary labels into the object file
5687 symbol table prefixed by "prefix".
5688 Default prefix is ":temp:".
5693 /* ??? Conflicts with gas' listing option. */
5694 /* indirect=<tgt> Assume unannotated indirect branches behavior
5695 according to <tgt> --
5696 exit: branch out from the current context (default)
5697 labels: all labels in context may be branch targets
5702 /* -X conflicts with an ignored option, use -x instead */
5704 if (!arg || strcmp (arg, "explicit") == 0)
5706 /* set default mode to explicit */
5707 md.default_explicit_mode = 1;
5710 else if (strcmp (arg, "auto") == 0)
5712 md.default_explicit_mode = 0;
5714 else if (strcmp (arg, "debug") == 0)
5718 else if (strcmp (arg, "debugx") == 0)
5720 md.default_explicit_mode = 1;
5725 as_bad (_("Unrecognized option '-x%s'"), arg);
5730 /* nops Print nops statistics. */
5733 /* GNU specific switches for gcc. */
5734 case OPTION_MCONSTANT_GP:
5735 md.flags |= EF_IA_64_CONS_GP;
5738 case OPTION_MAUTO_PIC:
5739 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP;
5750 md_show_usage (stream)
5755 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
5756 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
5757 -x | -xexplicit turn on dependency violation checking (default)\n\
5758 -xauto automagically remove dependency violations\n\
5759 -xdebug debug dependency violation checker\n"),
5763 /* Return true if TYPE fits in TEMPL at SLOT. */
5766 match (int templ, int type, int slot)
5768 enum ia64_unit unit;
5771 unit = ia64_templ_desc[templ].exec_unit[slot];
5774 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */
5776 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M);
5778 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break;
5779 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break;
5780 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break;
5781 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break;
5782 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break;
5783 default: result = 0; break;
5788 /* Add a bit of extra goodness if a nop of type F or B would fit
5789 in TEMPL at SLOT. */
5792 extra_goodness (int templ, int slot)
5794 if (slot == 1 && match (templ, IA64_TYPE_F, slot))
5796 if (slot == 2 && match (templ, IA64_TYPE_B, slot))
5801 /* This function is called once, at assembler startup time. It sets
5802 up all the tables, etc. that the MD part of the assembler will need
5803 that can be determined before arguments are parsed. */
5807 int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
5812 md.explicit_mode = md.default_explicit_mode;
5814 bfd_set_section_alignment (stdoutput, text_section, 4);
5816 target_big_endian = TARGET_BYTES_BIG_ENDIAN;
5817 pseudo_func[FUNC_FPTR_RELATIVE].u.sym =
5818 symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE,
5819 &zero_address_frag);
5821 pseudo_func[FUNC_GP_RELATIVE].u.sym =
5822 symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE,
5823 &zero_address_frag);
5825 pseudo_func[FUNC_LT_RELATIVE].u.sym =
5826 symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE,
5827 &zero_address_frag);
5829 pseudo_func[FUNC_PC_RELATIVE].u.sym =
5830 symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE,
5831 &zero_address_frag);
5833 pseudo_func[FUNC_PLT_RELATIVE].u.sym =
5834 symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE,
5835 &zero_address_frag);
5837 pseudo_func[FUNC_SEC_RELATIVE].u.sym =
5838 symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE,
5839 &zero_address_frag);
5841 pseudo_func[FUNC_SEG_RELATIVE].u.sym =
5842 symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE,
5843 &zero_address_frag);
5845 pseudo_func[FUNC_LTV_RELATIVE].u.sym =
5846 symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE,
5847 &zero_address_frag);
5849 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =
5850 symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE,
5851 &zero_address_frag);
5853 /* Compute the table of best templates. We compute goodness as a
5854 base 4 value, in which each match counts for 3, each F counts
5855 for 2, each B counts for 1. This should maximize the number of
5856 F and B nops in the chosen bundles, which is good because these
5857 pipelines are least likely to be overcommitted. */
5858 for (i = 0; i < IA64_NUM_TYPES; ++i)
5859 for (j = 0; j < IA64_NUM_TYPES; ++j)
5860 for (k = 0; k < IA64_NUM_TYPES; ++k)
5863 for (t = 0; t < NELEMS (ia64_templ_desc); ++t)
5866 if (match (t, i, 0))
5868 if (match (t, j, 1))
5870 if (match (t, k, 2))
5871 goodness = 3 + 3 + 3;
5873 goodness = 3 + 3 + extra_goodness (t, 2);
5875 else if (match (t, j, 2))
5876 goodness = 3 + 3 + extra_goodness (t, 1);
5880 goodness += extra_goodness (t, 1);
5881 goodness += extra_goodness (t, 2);
5884 else if (match (t, i, 1))
5886 if (match (t, j, 2))
5889 goodness = 3 + extra_goodness (t, 2);
5891 else if (match (t, i, 2))
5892 goodness = 3 + extra_goodness (t, 1);
5894 if (goodness > best)
5897 best_template[i][j][k] = t;
5902 for (i = 0; i < NUM_SLOTS; ++i)
5903 md.slot[i].user_template = -1;
5905 md.pseudo_hash = hash_new ();
5906 for (i = 0; i < NELEMS (pseudo_opcode); ++i)
5908 err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name,
5909 (void *) (pseudo_opcode + i));
5911 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5912 pseudo_opcode[i].name, err);
5915 md.reg_hash = hash_new ();
5916 md.dynreg_hash = hash_new ();
5917 md.const_hash = hash_new ();
5918 md.entry_hash = hash_new ();
5920 /* general registers: */
5923 for (i = 0; i < total; ++i)
5925 sprintf (name, "r%d", i - REG_GR);
5926 md.regsym[i] = declare_register (name, i);
5929 /* floating point registers: */
5931 for (; i < total; ++i)
5933 sprintf (name, "f%d", i - REG_FR);
5934 md.regsym[i] = declare_register (name, i);
5937 /* application registers: */
5940 for (; i < total; ++i)
5942 sprintf (name, "ar%d", i - REG_AR);
5943 md.regsym[i] = declare_register (name, i);
5946 /* control registers: */
5949 for (; i < total; ++i)
5951 sprintf (name, "cr%d", i - REG_CR);
5952 md.regsym[i] = declare_register (name, i);
5955 /* predicate registers: */
5957 for (; i < total; ++i)
5959 sprintf (name, "p%d", i - REG_P);
5960 md.regsym[i] = declare_register (name, i);
5963 /* branch registers: */
5965 for (; i < total; ++i)
5967 sprintf (name, "b%d", i - REG_BR);
5968 md.regsym[i] = declare_register (name, i);
5971 md.regsym[REG_IP] = declare_register ("ip", REG_IP);
5972 md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
5973 md.regsym[REG_PR] = declare_register ("pr", REG_PR);
5974 md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
5975 md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
5976 md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
5977 md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
5979 for (i = 0; i < NELEMS (indirect_reg); ++i)
5981 regnum = indirect_reg[i].regnum;
5982 md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
5985 /* define synonyms for application registers: */
5986 for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
5987 md.regsym[i] = declare_register (ar[i - REG_AR].name,
5988 REG_AR + ar[i - REG_AR].regnum);
5990 /* define synonyms for control registers: */
5991 for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
5992 md.regsym[i] = declare_register (cr[i - REG_CR].name,
5993 REG_CR + cr[i - REG_CR].regnum);
5995 declare_register ("gp", REG_GR + 1);
5996 declare_register ("sp", REG_GR + 12);
5997 declare_register ("rp", REG_BR + 0);
5999 /* pseudo-registers used to specify unwind info: */
6000 declare_register ("psp", REG_PSP);
6002 declare_register_set ("ret", 4, REG_GR + 8);
6003 declare_register_set ("farg", 8, REG_FR + 8);
6004 declare_register_set ("fret", 8, REG_FR + 8);
6006 for (i = 0; i < NELEMS (const_bits); ++i)
6008 err = hash_insert (md.const_hash, const_bits[i].name,
6009 (PTR) (const_bits + i));
6011 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6015 /* Set the architecture and machine depending on defaults and command line
6017 if (md.flags & EF_IA_64_ABI64)
6018 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64);
6020 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32);
6023 as_warn (_("Could not set architecture and machine"));
6025 md.mem_offset.hint = 0;
6028 md.entry_labels = NULL;
6031 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6032 because that is called after md_parse_option which is where we do the
6033 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6034 default endianness. */
6037 ia64_init (argc, argv)
6041 md.flags = EF_IA_64_ABI64;
6042 if (TARGET_BYTES_BIG_ENDIAN)
6043 md.flags |= EF_IA_64_BE;
6046 /* Return a string for the target object file format. */
6049 ia64_target_format ()
6051 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
6053 if (md.flags & EF_IA_64_BE)
6055 if (md.flags & EF_IA_64_ABI64)
6056 return "elf64-ia64-big";
6058 return "elf32-ia64-big";
6062 if (md.flags & EF_IA_64_ABI64)
6063 return "elf64-ia64-little";
6065 return "elf32-ia64-little";
6069 return "unknown-format";
6073 ia64_end_of_source ()
6075 /* terminate insn group upon reaching end of file: */
6076 insn_group_break (1, 0, 0);
6078 /* emits slots we haven't written yet: */
6079 ia64_flush_insns ();
6081 bfd_set_private_flags (stdoutput, md.flags);
6083 if (debug_type == DEBUG_DWARF2)
6086 md.mem_offset.hint = 0;
6092 if (md.qp.X_op == O_register)
6093 as_bad ("qualifying predicate not followed by instruction");
6094 md.qp.X_op = O_absent;
6096 if (ignore_input ())
6099 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
6101 if (md.detect_dv && !md.explicit_mode)
6102 as_warn (_("Explicit stops are ignored in auto mode"));
6104 insn_group_break (1, 0, 0);
6108 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6110 static int defining_tag = 0;
6113 ia64_unrecognized_line (ch)
6119 expression (&md.qp);
6120 if (*input_line_pointer++ != ')')
6122 as_bad ("Expected ')'");
6125 if (md.qp.X_op != O_register)
6127 as_bad ("Qualifying predicate expected");
6130 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
6132 as_bad ("Predicate register expected");
6138 if (md.manual_bundling)
6139 as_warn ("Found '{' when manual bundling is already turned on");
6141 CURR_SLOT.manual_bundling_on = 1;
6142 md.manual_bundling = 1;
6144 /* Bundling is only acceptable in explicit mode
6145 or when in default automatic mode. */
6146 if (md.detect_dv && !md.explicit_mode)
6148 if (!md.mode_explicitly_set
6149 && !md.default_explicit_mode)
6152 as_warn (_("Found '{' after explicit switch to automatic mode"));
6157 if (!md.manual_bundling)
6158 as_warn ("Found '}' when manual bundling is off");
6160 PREV_SLOT.manual_bundling_off = 1;
6161 md.manual_bundling = 0;
6163 /* switch back to automatic mode, if applicable */
6166 && !md.mode_explicitly_set
6167 && !md.default_explicit_mode)
6170 /* Allow '{' to follow on the same line. We also allow ";;", but that
6171 happens automatically because ';' is an end of line marker. */
6173 if (input_line_pointer[0] == '{')
6175 input_line_pointer++;
6176 return ia64_unrecognized_line ('{');
6179 demand_empty_rest_of_line ();
6188 if (md.qp.X_op == O_register)
6190 as_bad ("Tag must come before qualifying predicate.");
6193 s = input_line_pointer;
6194 c = get_symbol_end ();
6197 /* Put ':' back for error messages' sake. */
6198 *input_line_pointer++ = ':';
6199 as_bad ("Expected ':'");
6205 /* Put ':' back for error messages' sake. */
6206 *input_line_pointer++ = ':';
6207 if (*input_line_pointer++ != ']')
6209 as_bad ("Expected ']'");
6214 as_bad ("Tag name expected");
6224 /* Not a valid line. */
6229 ia64_frob_label (sym)
6232 struct label_fix *fix;
6234 /* Tags need special handling since they are not bundle breaks like
6238 fix = obstack_alloc (¬es, sizeof (*fix));
6240 fix->next = CURR_SLOT.tag_fixups;
6241 CURR_SLOT.tag_fixups = fix;
6246 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6248 md.last_text_seg = now_seg;
6249 fix = obstack_alloc (¬es, sizeof (*fix));
6251 fix->next = CURR_SLOT.label_fixups;
6252 CURR_SLOT.label_fixups = fix;
6254 /* Keep track of how many code entry points we've seen. */
6255 if (md.path == md.maxpaths)
6258 md.entry_labels = (const char **)
6259 xrealloc ((void *) md.entry_labels,
6260 md.maxpaths * sizeof (char *));
6262 md.entry_labels[md.path++] = S_GET_NAME (sym);
6267 ia64_flush_pending_output ()
6269 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
6271 /* ??? This causes many unnecessary stop bits to be emitted.
6272 Unfortunately, it isn't clear if it is safe to remove this. */
6273 insn_group_break (1, 0, 0);
6274 ia64_flush_insns ();
6278 /* Do ia64-specific expression optimization. All that's done here is
6279 to transform index expressions that are either due to the indexing
6280 of rotating registers or due to the indexing of indirect register
6283 ia64_optimize_expr (l, op, r)
6292 if (l->X_op == O_register && r->X_op == O_constant)
6294 num_regs = (l->X_add_number >> 16);
6295 if ((unsigned) r->X_add_number >= num_regs)
6298 as_bad ("No current frame");
6300 as_bad ("Index out of range 0..%u", num_regs - 1);
6301 r->X_add_number = 0;
6303 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
6306 else if (l->X_op == O_register && r->X_op == O_register)
6308 if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
6309 || l->X_add_number == IND_MEM)
6311 as_bad ("Indirect register set name expected");
6312 l->X_add_number = IND_CPUID;
6315 l->X_op_symbol = md.regsym[l->X_add_number];
6316 l->X_add_number = r->X_add_number;
6324 ia64_parse_name (name, e)
6328 struct const_desc *cdesc;
6329 struct dynreg *dr = 0;
6330 unsigned int regnum;
6334 /* first see if NAME is a known register name: */
6335 sym = hash_find (md.reg_hash, name);
6338 e->X_op = O_register;
6339 e->X_add_number = S_GET_VALUE (sym);
6343 cdesc = hash_find (md.const_hash, name);
6346 e->X_op = O_constant;
6347 e->X_add_number = cdesc->value;
6351 /* check for inN, locN, or outN: */
6355 if (name[1] == 'n' && isdigit (name[2]))
6363 if (name[1] == 'o' && name[2] == 'c' && isdigit (name[3]))
6371 if (name[1] == 'u' && name[2] == 't' && isdigit (name[3]))
6384 /* The name is inN, locN, or outN; parse the register number. */
6385 regnum = strtoul (name, &end, 10);
6386 if (end > name && *end == '\0')
6388 if ((unsigned) regnum >= dr->num_regs)
6391 as_bad ("No current frame");
6393 as_bad ("Register number out of range 0..%u",
6397 e->X_op = O_register;
6398 e->X_add_number = dr->base + regnum;
6403 if ((dr = hash_find (md.dynreg_hash, name)))
6405 /* We've got ourselves the name of a rotating register set.
6406 Store the base register number in the low 16 bits of
6407 X_add_number and the size of the register set in the top 16
6409 e->X_op = O_register;
6410 e->X_add_number = dr->base | (dr->num_regs << 16);
6416 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6419 ia64_canonicalize_symbol_name (name)
6422 size_t len = strlen (name);
6423 if (len > 1 && name[len - 1] == '#')
6424 name[len - 1] = '\0';
6429 is_conditional_branch (idesc)
6430 struct ia64_opcode *idesc;
6432 return (strncmp (idesc->name, "br", 2) == 0
6433 && (strcmp (idesc->name, "br") == 0
6434 || strncmp (idesc->name, "br.cond", 7) == 0
6435 || strncmp (idesc->name, "br.call", 7) == 0
6436 || strncmp (idesc->name, "br.ret", 6) == 0
6437 || strcmp (idesc->name, "brl") == 0
6438 || strncmp (idesc->name, "brl.cond", 7) == 0
6439 || strncmp (idesc->name, "brl.call", 7) == 0
6440 || strncmp (idesc->name, "brl.ret", 6) == 0));
6443 /* Return whether the given opcode is a taken branch. If there's any doubt,
6447 is_taken_branch (idesc)
6448 struct ia64_opcode *idesc;
6450 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0)
6451 || strncmp (idesc->name, "br.ia", 5) == 0);
6454 /* Return whether the given opcode is an interruption or rfi. If there's any
6455 doubt, returns zero. */
6458 is_interruption_or_rfi (idesc)
6459 struct ia64_opcode *idesc;
6461 if (strcmp (idesc->name, "rfi") == 0)
6466 /* Returns the index of the given dependency in the opcode's list of chks, or
6467 -1 if there is no dependency. */
6470 depends_on (depind, idesc)
6472 struct ia64_opcode *idesc;
6475 const struct ia64_opcode_dependency *dep = idesc->dependencies;
6476 for (i = 0; i < dep->nchks; i++)
6478 if (depind == DEP (dep->chks[i]))
6484 /* Determine a set of specific resources used for a particular resource
6485 class. Returns the number of specific resources identified For those
6486 cases which are not determinable statically, the resource returned is
6489 Meanings of value in 'NOTE':
6490 1) only read/write when the register number is explicitly encoded in the
6492 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6493 accesses CFM when qualifying predicate is in the rotating region.
6494 3) general register value is used to specify an indirect register; not
6495 determinable statically.
6496 4) only read the given resource when bits 7:0 of the indirect index
6497 register value does not match the register number of the resource; not
6498 determinable statically.
6499 5) all rules are implementation specific.
6500 6) only when both the index specified by the reader and the index specified
6501 by the writer have the same value in bits 63:61; not determinable
6503 7) only access the specified resource when the corresponding mask bit is
6505 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6506 only read when these insns reference FR2-31
6507 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6508 written when these insns write FR32-127
6509 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6511 11) The target predicates are written independently of PR[qp], but source
6512 registers are only read if PR[qp] is true. Since the state of PR[qp]
6513 cannot statically be determined, all source registers are marked used.
6514 12) This insn only reads the specified predicate register when that
6515 register is the PR[qp].
6516 13) This reference to ld-c only applies to teh GR whose value is loaded
6517 with data returned from memory, not the post-incremented address register.
6518 14) The RSE resource includes the implementation-specific RSE internal
6519 state resources. At least one (and possibly more) of these resources are
6520 read by each instruction listed in IC:rse-readers. At least one (and
6521 possibly more) of these resources are written by each insn listed in
6523 15+16) Represents reserved instructions, which the assembler does not
6526 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6527 this code; there are no dependency violations based on memory access.
6530 #define MAX_SPECS 256
6535 specify_resource (dep, idesc, type, specs, note, path)
6536 const struct ia64_dependency *dep;
6537 struct ia64_opcode *idesc;
6538 int type; /* is this a DV chk or a DV reg? */
6539 struct rsrc specs[MAX_SPECS]; /* returned specific resources */
6540 int note; /* resource note for this insn's usage */
6541 int path; /* which execution path to examine */
6548 if (dep->mode == IA64_DV_WAW
6549 || (dep->mode == IA64_DV_RAW && type == DV_REG)
6550 || (dep->mode == IA64_DV_WAR && type == DV_CHK))
6553 /* template for any resources we identify */
6554 tmpl.dependency = dep;
6556 tmpl.insn_srlz = tmpl.data_srlz = 0;
6557 tmpl.qp_regno = CURR_SLOT.qp_regno;
6558 tmpl.link_to_qp_branch = 1;
6559 tmpl.mem_offset.hint = 0;
6562 tmpl.cmp_type = CMP_NONE;
6565 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6566 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6567 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6569 /* we don't need to track these */
6570 if (dep->semantics == IA64_DVS_NONE)
6573 switch (dep->specifier)
6578 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6580 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6581 if (regno >= 0 && regno <= 7)
6583 specs[count] = tmpl;
6584 specs[count++].index = regno;
6590 for (i = 0; i < 8; i++)
6592 specs[count] = tmpl;
6593 specs[count++].index = i;
6602 case IA64_RS_AR_UNAT:
6603 /* This is a mov =AR or mov AR= instruction. */
6604 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6606 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6607 if (regno == AR_UNAT)
6609 specs[count++] = tmpl;
6614 /* This is a spill/fill, or other instruction that modifies the
6617 /* Unless we can determine the specific bits used, mark the whole
6618 thing; bits 8:3 of the memory address indicate the bit used in
6619 UNAT. The .mem.offset hint may be used to eliminate a small
6620 subset of conflicts. */
6621 specs[count] = tmpl;
6622 if (md.mem_offset.hint)
6625 fprintf (stderr, " Using hint for spill/fill\n");
6626 /* The index isn't actually used, just set it to something
6627 approximating the bit index. */
6628 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F;
6629 specs[count].mem_offset.hint = 1;
6630 specs[count].mem_offset.offset = md.mem_offset.offset;
6631 specs[count++].mem_offset.base = md.mem_offset.base;
6635 specs[count++].specific = 0;
6643 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6645 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6646 if ((regno >= 8 && regno <= 15)
6647 || (regno >= 20 && regno <= 23)
6648 || (regno >= 31 && regno <= 39)
6649 || (regno >= 41 && regno <= 47)
6650 || (regno >= 67 && regno <= 111))
6652 specs[count] = tmpl;
6653 specs[count++].index = regno;
6666 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
6668 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
6669 if ((regno >= 48 && regno <= 63)
6670 || (regno >= 112 && regno <= 127))
6672 specs[count] = tmpl;
6673 specs[count++].index = regno;
6679 for (i = 48; i < 64; i++)
6681 specs[count] = tmpl;
6682 specs[count++].index = i;
6684 for (i = 112; i < 128; i++)
6686 specs[count] = tmpl;
6687 specs[count++].index = i;
6705 for (i = 0; i < idesc->num_outputs; i++)
6706 if (idesc->operands[i] == IA64_OPND_B1
6707 || idesc->operands[i] == IA64_OPND_B2)
6709 specs[count] = tmpl;
6710 specs[count++].index =
6711 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6716 for (i = idesc->num_outputs;i < NELEMS (idesc->operands); i++)
6717 if (idesc->operands[i] == IA64_OPND_B1
6718 || idesc->operands[i] == IA64_OPND_B2)
6720 specs[count] = tmpl;
6721 specs[count++].index =
6722 CURR_SLOT.opnd[i].X_add_number - REG_BR;
6728 case IA64_RS_CPUID: /* four or more registers */
6731 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3)
6733 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6734 if (regno >= 0 && regno < NELEMS (gr_values)
6737 specs[count] = tmpl;
6738 specs[count++].index = gr_values[regno].value & 0xFF;
6742 specs[count] = tmpl;
6743 specs[count++].specific = 0;
6753 case IA64_RS_DBR: /* four or more registers */
6756 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3)
6758 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6759 if (regno >= 0 && regno < NELEMS (gr_values)
6762 specs[count] = tmpl;
6763 specs[count++].index = gr_values[regno].value & 0xFF;
6767 specs[count] = tmpl;
6768 specs[count++].specific = 0;
6772 else if (note == 0 && !rsrc_write)
6774 specs[count] = tmpl;
6775 specs[count++].specific = 0;
6783 case IA64_RS_IBR: /* four or more registers */
6786 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3)
6788 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6789 if (regno >= 0 && regno < NELEMS (gr_values)
6792 specs[count] = tmpl;
6793 specs[count++].index = gr_values[regno].value & 0xFF;
6797 specs[count] = tmpl;
6798 specs[count++].specific = 0;
6811 /* These are implementation specific. Force all references to
6812 conflict with all other references. */
6813 specs[count] = tmpl;
6814 specs[count++].specific = 0;
6822 case IA64_RS_PKR: /* 16 or more registers */
6823 if (note == 3 || note == 4)
6825 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3)
6827 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6828 if (regno >= 0 && regno < NELEMS (gr_values)
6833 specs[count] = tmpl;
6834 specs[count++].index = gr_values[regno].value & 0xFF;
6837 for (i = 0; i < NELEMS (gr_values); i++)
6839 /* Uses all registers *except* the one in R3. */
6840 if (i != (gr_values[regno].value & 0xFF))
6842 specs[count] = tmpl;
6843 specs[count++].index = i;
6849 specs[count] = tmpl;
6850 specs[count++].specific = 0;
6857 specs[count] = tmpl;
6858 specs[count++].specific = 0;
6862 case IA64_RS_PMC: /* four or more registers */
6865 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3
6866 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3))
6869 int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write)
6871 int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR;
6872 if (regno >= 0 && regno < NELEMS (gr_values)
6875 specs[count] = tmpl;
6876 specs[count++].index = gr_values[regno].value & 0xFF;
6880 specs[count] = tmpl;
6881 specs[count++].specific = 0;
6891 case IA64_RS_PMD: /* four or more registers */
6894 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3)
6896 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6897 if (regno >= 0 && regno < NELEMS (gr_values)
6900 specs[count] = tmpl;
6901 specs[count++].index = gr_values[regno].value & 0xFF;
6905 specs[count] = tmpl;
6906 specs[count++].specific = 0;
6916 case IA64_RS_RR: /* eight registers */
6919 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3)
6921 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR;
6922 if (regno >= 0 && regno < NELEMS (gr_values)
6925 specs[count] = tmpl;
6926 specs[count++].index = (gr_values[regno].value >> 61) & 0x7;
6930 specs[count] = tmpl;
6931 specs[count++].specific = 0;
6935 else if (note == 0 && !rsrc_write)
6937 specs[count] = tmpl;
6938 specs[count++].specific = 0;
6946 case IA64_RS_CR_IRR:
6949 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6950 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR;
6952 && idesc->operands[1] == IA64_OPND_CR3
6955 for (i = 0; i < 4; i++)
6957 specs[count] = tmpl;
6958 specs[count++].index = CR_IRR0 + i;
6964 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6965 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6967 && regno <= CR_IRR3)
6969 specs[count] = tmpl;
6970 specs[count++].index = regno;
6979 case IA64_RS_CR_LRR:
6986 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
6987 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3
6988 && (regno == CR_LRR0 || regno == CR_LRR1))
6990 specs[count] = tmpl;
6991 specs[count++].index = regno;
6999 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7001 specs[count] = tmpl;
7002 specs[count++].index =
7003 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7018 else if (rsrc_write)
7020 if (dep->specifier == IA64_RS_FRb
7021 && idesc->operands[0] == IA64_OPND_F1)
7023 specs[count] = tmpl;
7024 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR;
7029 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++)
7031 if (idesc->operands[i] == IA64_OPND_F2
7032 || idesc->operands[i] == IA64_OPND_F3
7033 || idesc->operands[i] == IA64_OPND_F4)
7035 specs[count] = tmpl;
7036 specs[count++].index =
7037 CURR_SLOT.opnd[i].X_add_number - REG_FR;
7046 /* This reference applies only to the GR whose value is loaded with
7047 data returned from memory. */
7048 specs[count] = tmpl;
7049 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR;
7055 for (i = 0; i < idesc->num_outputs; i++)
7056 if (idesc->operands[i] == IA64_OPND_R1
7057 || idesc->operands[i] == IA64_OPND_R2
7058 || idesc->operands[i] == IA64_OPND_R3)
7060 specs[count] = tmpl;
7061 specs[count++].index =
7062 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7064 if (idesc->flags & IA64_OPCODE_POSTINC)
7065 for (i = 0; i < NELEMS (idesc->operands); i++)
7066 if (idesc->operands[i] == IA64_OPND_MR3)
7068 specs[count] = tmpl;
7069 specs[count++].index =
7070 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7075 /* Look for anything that reads a GR. */
7076 for (i = 0; i < NELEMS (idesc->operands); i++)
7078 if (idesc->operands[i] == IA64_OPND_MR3
7079 || idesc->operands[i] == IA64_OPND_CPUID_R3
7080 || idesc->operands[i] == IA64_OPND_DBR_R3
7081 || idesc->operands[i] == IA64_OPND_IBR_R3
7082 || idesc->operands[i] == IA64_OPND_MSR_R3
7083 || idesc->operands[i] == IA64_OPND_PKR_R3
7084 || idesc->operands[i] == IA64_OPND_PMC_R3
7085 || idesc->operands[i] == IA64_OPND_PMD_R3
7086 || idesc->operands[i] == IA64_OPND_RR_R3
7087 || ((i >= idesc->num_outputs)
7088 && (idesc->operands[i] == IA64_OPND_R1
7089 || idesc->operands[i] == IA64_OPND_R2
7090 || idesc->operands[i] == IA64_OPND_R3
7091 /* addl source register. */
7092 || idesc->operands[i] == IA64_OPND_R3_2)))
7094 specs[count] = tmpl;
7095 specs[count++].index =
7096 CURR_SLOT.opnd[i].X_add_number - REG_GR;
7107 /* This is the same as IA64_RS_PRr, except that the register range is
7108 from 1 - 15, and there are no rotating register reads/writes here. */
7112 for (i = 1; i < 16; i++)
7114 specs[count] = tmpl;
7115 specs[count++].index = i;
7121 /* Mark only those registers indicated by the mask. */
7124 mask = CURR_SLOT.opnd[2].X_add_number;
7125 for (i = 1; i < 16; i++)
7126 if (mask & ((valueT) 1 << i))
7128 specs[count] = tmpl;
7129 specs[count++].index = i;
7137 else if (note == 11) /* note 11 implies note 1 as well */
7141 for (i = 0; i < idesc->num_outputs; i++)
7143 if (idesc->operands[i] == IA64_OPND_P1
7144 || idesc->operands[i] == IA64_OPND_P2)
7146 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7147 if (regno >= 1 && regno < 16)
7149 specs[count] = tmpl;
7150 specs[count++].index = regno;
7160 else if (note == 12)
7162 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7164 specs[count] = tmpl;
7165 specs[count++].index = CURR_SLOT.qp_regno;
7172 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7173 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7174 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7175 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7177 if ((idesc->operands[0] == IA64_OPND_P1
7178 || idesc->operands[0] == IA64_OPND_P2)
7179 && p1 >= 1 && p1 < 16)
7181 specs[count] = tmpl;
7182 specs[count].cmp_type =
7183 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7184 specs[count++].index = p1;
7186 if ((idesc->operands[1] == IA64_OPND_P1
7187 || idesc->operands[1] == IA64_OPND_P2)
7188 && p2 >= 1 && p2 < 16)
7190 specs[count] = tmpl;
7191 specs[count].cmp_type =
7192 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7193 specs[count++].index = p2;
7198 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16)
7200 specs[count] = tmpl;
7201 specs[count++].index = CURR_SLOT.qp_regno;
7203 if (idesc->operands[1] == IA64_OPND_PR)
7205 for (i = 1; i < 16; i++)
7207 specs[count] = tmpl;
7208 specs[count++].index = i;
7219 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7220 simplified cases of this. */
7224 for (i = 16; i < 63; i++)
7226 specs[count] = tmpl;
7227 specs[count++].index = i;
7233 /* Mark only those registers indicated by the mask. */
7235 && idesc->operands[0] == IA64_OPND_PR)
7237 mask = CURR_SLOT.opnd[2].X_add_number;
7238 if (mask & ((valueT) 1<<16))
7239 for (i = 16; i < 63; i++)
7241 specs[count] = tmpl;
7242 specs[count++].index = i;
7246 && idesc->operands[0] == IA64_OPND_PR_ROT)
7248 for (i = 16; i < 63; i++)
7250 specs[count] = tmpl;
7251 specs[count++].index = i;
7259 else if (note == 11) /* note 11 implies note 1 as well */
7263 for (i = 0; i < idesc->num_outputs; i++)
7265 if (idesc->operands[i] == IA64_OPND_P1
7266 || idesc->operands[i] == IA64_OPND_P2)
7268 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
7269 if (regno >= 16 && regno < 63)
7271 specs[count] = tmpl;
7272 specs[count++].index = regno;
7282 else if (note == 12)
7284 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
7286 specs[count] = tmpl;
7287 specs[count++].index = CURR_SLOT.qp_regno;
7294 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7295 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7296 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7297 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7299 if ((idesc->operands[0] == IA64_OPND_P1
7300 || idesc->operands[0] == IA64_OPND_P2)
7301 && p1 >= 16 && p1 < 63)
7303 specs[count] = tmpl;
7304 specs[count].cmp_type =
7305 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7306 specs[count++].index = p1;
7308 if ((idesc->operands[1] == IA64_OPND_P1
7309 || idesc->operands[1] == IA64_OPND_P2)
7310 && p2 >= 16 && p2 < 63)
7312 specs[count] = tmpl;
7313 specs[count].cmp_type =
7314 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7315 specs[count++].index = p2;
7320 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63)
7322 specs[count] = tmpl;
7323 specs[count++].index = CURR_SLOT.qp_regno;
7325 if (idesc->operands[1] == IA64_OPND_PR)
7327 for (i = 16; i < 63; i++)
7329 specs[count] = tmpl;
7330 specs[count++].index = i;
7342 /* Verify that the instruction is using the PSR bit indicated in
7346 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM)
7348 if (dep->regindex < 6)
7350 specs[count++] = tmpl;
7353 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR)
7355 if (dep->regindex < 32
7356 || dep->regindex == 35
7357 || dep->regindex == 36
7358 || (!rsrc_write && dep->regindex == PSR_CPL))
7360 specs[count++] = tmpl;
7363 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L)
7365 if (dep->regindex < 32
7366 || dep->regindex == 35
7367 || dep->regindex == 36
7368 || (rsrc_write && dep->regindex == PSR_CPL))
7370 specs[count++] = tmpl;
7375 /* Several PSR bits have very specific dependencies. */
7376 switch (dep->regindex)
7379 specs[count++] = tmpl;
7384 specs[count++] = tmpl;
7388 /* Only certain CR accesses use PSR.ic */
7389 if (idesc->operands[0] == IA64_OPND_CR3
7390 || idesc->operands[1] == IA64_OPND_CR3)
7393 ((idesc->operands[0] == IA64_OPND_CR3)
7396 CURR_SLOT.opnd[index].X_add_number - REG_CR;
7411 specs[count++] = tmpl;
7420 specs[count++] = tmpl;
7424 /* Only some AR accesses use cpl */
7425 if (idesc->operands[0] == IA64_OPND_AR3
7426 || idesc->operands[1] == IA64_OPND_AR3)
7429 ((idesc->operands[0] == IA64_OPND_AR3)
7432 CURR_SLOT.opnd[index].X_add_number - REG_AR;
7439 && regno <= AR_K7))))
7441 specs[count++] = tmpl;
7446 specs[count++] = tmpl;
7456 if (idesc->operands[0] == IA64_OPND_IMMU24)
7458 mask = CURR_SLOT.opnd[0].X_add_number;
7464 if (mask & ((valueT) 1 << dep->regindex))
7466 specs[count++] = tmpl;
7471 int min = dep->regindex == PSR_DFL ? 2 : 32;
7472 int max = dep->regindex == PSR_DFL ? 31 : 127;
7473 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7474 for (i = 0; i < NELEMS (idesc->operands); i++)
7476 if (idesc->operands[i] == IA64_OPND_F1
7477 || idesc->operands[i] == IA64_OPND_F2
7478 || idesc->operands[i] == IA64_OPND_F3
7479 || idesc->operands[i] == IA64_OPND_F4)
7481 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7482 if (reg >= min && reg <= max)
7484 specs[count++] = tmpl;
7491 int min = dep->regindex == PSR_MFL ? 2 : 32;
7492 int max = dep->regindex == PSR_MFL ? 31 : 127;
7493 /* mfh is read on writes to FR32-127; mfl is read on writes to
7495 for (i = 0; i < idesc->num_outputs; i++)
7497 if (idesc->operands[i] == IA64_OPND_F1)
7499 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7500 if (reg >= min && reg <= max)
7502 specs[count++] = tmpl;
7507 else if (note == 10)
7509 for (i = 0; i < NELEMS (idesc->operands); i++)
7511 if (idesc->operands[i] == IA64_OPND_R1
7512 || idesc->operands[i] == IA64_OPND_R2
7513 || idesc->operands[i] == IA64_OPND_R3)
7515 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7516 if (regno >= 16 && regno <= 31)
7518 specs[count++] = tmpl;
7529 case IA64_RS_AR_FPSR:
7530 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3)
7532 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7533 if (regno == AR_FPSR)
7535 specs[count++] = tmpl;
7540 specs[count++] = tmpl;
7545 /* Handle all AR[REG] resources */
7546 if (note == 0 || note == 1)
7548 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR;
7549 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3
7550 && regno == dep->regindex)
7552 specs[count++] = tmpl;
7554 /* other AR[REG] resources may be affected by AR accesses */
7555 else if (idesc->operands[0] == IA64_OPND_AR3)
7558 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR;
7559 switch (dep->regindex)
7565 if (regno == AR_BSPSTORE)
7567 specs[count++] = tmpl;
7571 (regno == AR_BSPSTORE
7572 || regno == AR_RNAT))
7574 specs[count++] = tmpl;
7579 else if (idesc->operands[1] == IA64_OPND_AR3)
7582 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR;
7583 switch (dep->regindex)
7588 if (regno == AR_BSPSTORE || regno == AR_RNAT)
7590 specs[count++] = tmpl;
7597 specs[count++] = tmpl;
7607 /* Handle all CR[REG] resources */
7608 if (note == 0 || note == 1)
7610 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
7612 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR;
7613 if (regno == dep->regindex)
7615 specs[count++] = tmpl;
7617 else if (!rsrc_write)
7619 /* Reads from CR[IVR] affect other resources. */
7620 if (regno == CR_IVR)
7622 if ((dep->regindex >= CR_IRR0
7623 && dep->regindex <= CR_IRR3)
7624 || dep->regindex == CR_TPR)
7626 specs[count++] = tmpl;
7633 specs[count++] = tmpl;
7642 case IA64_RS_INSERVICE:
7643 /* look for write of EOI (67) or read of IVR (65) */
7644 if ((idesc->operands[0] == IA64_OPND_CR3
7645 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI)
7646 || (idesc->operands[1] == IA64_OPND_CR3
7647 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR))
7649 specs[count++] = tmpl;
7656 specs[count++] = tmpl;
7667 specs[count++] = tmpl;
7671 /* Check if any of the registers accessed are in the rotating region.
7672 mov to/from pr accesses CFM only when qp_regno is in the rotating
7674 for (i = 0; i < NELEMS (idesc->operands); i++)
7676 if (idesc->operands[i] == IA64_OPND_R1
7677 || idesc->operands[i] == IA64_OPND_R2
7678 || idesc->operands[i] == IA64_OPND_R3)
7680 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR;
7681 /* Assumes that md.rot.num_regs is always valid */
7682 if (md.rot.num_regs > 0
7684 && num < 31 + md.rot.num_regs)
7686 specs[count] = tmpl;
7687 specs[count++].specific = 0;
7690 else if (idesc->operands[i] == IA64_OPND_F1
7691 || idesc->operands[i] == IA64_OPND_F2
7692 || idesc->operands[i] == IA64_OPND_F3
7693 || idesc->operands[i] == IA64_OPND_F4)
7695 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR;
7698 specs[count] = tmpl;
7699 specs[count++].specific = 0;
7702 else if (idesc->operands[i] == IA64_OPND_P1
7703 || idesc->operands[i] == IA64_OPND_P2)
7705 int num = CURR_SLOT.opnd[i].X_add_number - REG_P;
7708 specs[count] = tmpl;
7709 specs[count++].specific = 0;
7713 if (CURR_SLOT.qp_regno > 15)
7715 specs[count] = tmpl;
7716 specs[count++].specific = 0;
7721 /* This is the same as IA64_RS_PRr, except simplified to account for
7722 the fact that there is only one register. */
7726 specs[count++] = tmpl;
7731 if (idesc->operands[2] == IA64_OPND_IMM17)
7732 mask = CURR_SLOT.opnd[2].X_add_number;
7733 if (mask & ((valueT) 1 << 63))
7734 specs[count++] = tmpl;
7736 else if (note == 11)
7738 if ((idesc->operands[0] == IA64_OPND_P1
7739 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63)
7740 || (idesc->operands[1] == IA64_OPND_P2
7741 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63))
7743 specs[count++] = tmpl;
7746 else if (note == 12)
7748 if (CURR_SLOT.qp_regno == 63)
7750 specs[count++] = tmpl;
7757 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
7758 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
7759 int or_andcm = strstr(idesc->name, "or.andcm") != NULL;
7760 int and_orcm = strstr(idesc->name, "and.orcm") != NULL;
7763 && (idesc->operands[0] == IA64_OPND_P1
7764 || idesc->operands[0] == IA64_OPND_P2))
7766 specs[count] = tmpl;
7767 specs[count++].cmp_type =
7768 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE));
7771 && (idesc->operands[1] == IA64_OPND_P1
7772 || idesc->operands[1] == IA64_OPND_P2))
7774 specs[count] = tmpl;
7775 specs[count++].cmp_type =
7776 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE));
7781 if (CURR_SLOT.qp_regno == 63)
7783 specs[count++] = tmpl;
7794 /* FIXME we can identify some individual RSE written resources, but RSE
7795 read resources have not yet been completely identified, so for now
7796 treat RSE as a single resource */
7797 if (strncmp (idesc->name, "mov", 3) == 0)
7801 if (idesc->operands[0] == IA64_OPND_AR3
7802 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
7804 specs[count] = tmpl;
7805 specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7810 if (idesc->operands[0] == IA64_OPND_AR3)
7812 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE
7813 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT)
7815 specs[count++] = tmpl;
7818 else if (idesc->operands[1] == IA64_OPND_AR3)
7820 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP
7821 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE
7822 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT)
7824 specs[count++] = tmpl;
7831 specs[count++] = tmpl;
7836 /* FIXME -- do any of these need to be non-specific? */
7837 specs[count++] = tmpl;
7841 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier);
7848 /* Clear branch flags on marked resources. This breaks the link between the
7849 QP of the marking instruction and a subsequent branch on the same QP. */
7852 clear_qp_branch_flag (mask)
7856 for (i = 0; i < regdepslen; i++)
7858 valueT bit = ((valueT) 1 << regdeps[i].qp_regno);
7859 if ((bit & mask) != 0)
7861 regdeps[i].link_to_qp_branch = 0;
7866 /* Remove any mutexes which contain any of the PRs indicated in the mask.
7868 Any changes to a PR clears the mutex relations which include that PR. */
7871 clear_qp_mutex (mask)
7877 while (i < qp_mutexeslen)
7879 if ((qp_mutexes[i].prmask & mask) != 0)
7883 fprintf (stderr, " Clearing mutex relation");
7884 print_prmask (qp_mutexes[i].prmask);
7885 fprintf (stderr, "\n");
7887 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen];
7894 /* Clear implies relations which contain PRs in the given masks.
7895 P1_MASK indicates the source of the implies relation, while P2_MASK
7896 indicates the implied PR. */
7899 clear_qp_implies (p1_mask, p2_mask)
7906 while (i < qp_implieslen)
7908 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0
7909 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0)
7912 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n",
7913 qp_implies[i].p1, qp_implies[i].p2);
7914 qp_implies[i] = qp_implies[--qp_implieslen];
7921 /* Add the PRs specified to the list of implied relations. */
7924 add_qp_imply (p1, p2)
7931 /* p0 is not meaningful here. */
7932 if (p1 == 0 || p2 == 0)
7938 /* If it exists already, ignore it. */
7939 for (i = 0; i < qp_implieslen; i++)
7941 if (qp_implies[i].p1 == p1
7942 && qp_implies[i].p2 == p2
7943 && qp_implies[i].path == md.path
7944 && !qp_implies[i].p2_branched)
7948 if (qp_implieslen == qp_impliestotlen)
7950 qp_impliestotlen += 20;
7951 qp_implies = (struct qp_imply *)
7952 xrealloc ((void *) qp_implies,
7953 qp_impliestotlen * sizeof (struct qp_imply));
7956 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2);
7957 qp_implies[qp_implieslen].p1 = p1;
7958 qp_implies[qp_implieslen].p2 = p2;
7959 qp_implies[qp_implieslen].path = md.path;
7960 qp_implies[qp_implieslen++].p2_branched = 0;
7962 /* Add in the implied transitive relations; for everything that p2 implies,
7963 make p1 imply that, too; for everything that implies p1, make it imply p2
7965 for (i = 0; i < qp_implieslen; i++)
7967 if (qp_implies[i].p1 == p2)
7968 add_qp_imply (p1, qp_implies[i].p2);
7969 if (qp_implies[i].p2 == p1)
7970 add_qp_imply (qp_implies[i].p1, p2);
7972 /* Add in mutex relations implied by this implies relation; for each mutex
7973 relation containing p2, duplicate it and replace p2 with p1. */
7974 bit = (valueT) 1 << p1;
7975 mask = (valueT) 1 << p2;
7976 for (i = 0; i < qp_mutexeslen; i++)
7978 if (qp_mutexes[i].prmask & mask)
7979 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit);
7983 /* Add the PRs specified in the mask to the mutex list; this means that only
7984 one of the PRs can be true at any time. PR0 should never be included in
7994 if (qp_mutexeslen == qp_mutexestotlen)
7996 qp_mutexestotlen += 20;
7997 qp_mutexes = (struct qpmutex *)
7998 xrealloc ((void *) qp_mutexes,
7999 qp_mutexestotlen * sizeof (struct qpmutex));
8003 fprintf (stderr, " Registering mutex on");
8004 print_prmask (mask);
8005 fprintf (stderr, "\n");
8007 qp_mutexes[qp_mutexeslen].path = md.path;
8008 qp_mutexes[qp_mutexeslen++].prmask = mask;
8012 clear_register_values ()
8016 fprintf (stderr, " Clearing register values\n");
8017 for (i = 1; i < NELEMS (gr_values); i++)
8018 gr_values[i].known = 0;
8021 /* Keep track of register values/changes which affect DV tracking.
8023 optimization note: should add a flag to classes of insns where otherwise we
8024 have to examine a group of strings to identify them. */
8027 note_register_values (idesc)
8028 struct ia64_opcode *idesc;
8030 valueT qp_changemask = 0;
8033 /* Invalidate values for registers being written to. */
8034 for (i = 0; i < idesc->num_outputs; i++)
8036 if (idesc->operands[i] == IA64_OPND_R1
8037 || idesc->operands[i] == IA64_OPND_R2
8038 || idesc->operands[i] == IA64_OPND_R3)
8040 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8041 if (regno > 0 && regno < NELEMS (gr_values))
8042 gr_values[regno].known = 0;
8044 else if (idesc->operands[i] == IA64_OPND_R3_2)
8046 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR;
8047 if (regno > 0 && regno < 4)
8048 gr_values[regno].known = 0;
8050 else if (idesc->operands[i] == IA64_OPND_P1
8051 || idesc->operands[i] == IA64_OPND_P2)
8053 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P;
8054 qp_changemask |= (valueT) 1 << regno;
8056 else if (idesc->operands[i] == IA64_OPND_PR)
8058 if (idesc->operands[2] & (valueT) 0x10000)
8059 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2];
8061 qp_changemask = idesc->operands[2];
8064 else if (idesc->operands[i] == IA64_OPND_PR_ROT)
8066 if (idesc->operands[1] & ((valueT) 1 << 43))
8067 qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1];
8069 qp_changemask = idesc->operands[1];
8070 qp_changemask &= ~(valueT) 0xFFFF;
8075 /* Always clear qp branch flags on any PR change. */
8076 /* FIXME there may be exceptions for certain compares. */
8077 clear_qp_branch_flag (qp_changemask);
8079 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8080 if (idesc->flags & IA64_OPCODE_MOD_RRBS)
8082 qp_changemask |= ~(valueT) 0xFFFF;
8083 if (strcmp (idesc->name, "clrrrb.pr") != 0)
8085 for (i = 32; i < 32 + md.rot.num_regs; i++)
8086 gr_values[i].known = 0;
8088 clear_qp_mutex (qp_changemask);
8089 clear_qp_implies (qp_changemask, qp_changemask);
8091 /* After a call, all register values are undefined, except those marked
8093 else if (strncmp (idesc->name, "br.call", 6) == 0
8094 || strncmp (idesc->name, "brl.call", 7) == 0)
8096 /* FIXME keep GR values which are marked as "safe_across_calls" */
8097 clear_register_values ();
8098 clear_qp_mutex (~qp_safe_across_calls);
8099 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls);
8100 clear_qp_branch_flag (~qp_safe_across_calls);
8102 else if (is_interruption_or_rfi (idesc)
8103 || is_taken_branch (idesc))
8105 clear_register_values ();
8106 clear_qp_mutex (~(valueT) 0);
8107 clear_qp_implies (~(valueT) 0, ~(valueT) 0);
8109 /* Look for mutex and implies relations. */
8110 else if ((idesc->operands[0] == IA64_OPND_P1
8111 || idesc->operands[0] == IA64_OPND_P2)
8112 && (idesc->operands[1] == IA64_OPND_P1
8113 || idesc->operands[1] == IA64_OPND_P2))
8115 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P;
8116 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P;
8117 valueT p1mask = (valueT) 1 << p1;
8118 valueT p2mask = (valueT) 1 << p2;
8120 /* If one of the PRs is PR0, we can't really do anything. */
8121 if (p1 == 0 || p2 == 0)
8124 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n");
8126 /* In general, clear mutexes and implies which include P1 or P2,
8127 with the following exceptions. */
8128 else if (strstr (idesc->name, ".or.andcm") != NULL)
8130 add_qp_mutex (p1mask | p2mask);
8131 clear_qp_implies (p2mask, p1mask);
8133 else if (strstr (idesc->name, ".and.orcm") != NULL)
8135 add_qp_mutex (p1mask | p2mask);
8136 clear_qp_implies (p1mask, p2mask);
8138 else if (strstr (idesc->name, ".and") != NULL)
8140 clear_qp_implies (0, p1mask | p2mask);
8142 else if (strstr (idesc->name, ".or") != NULL)
8144 clear_qp_mutex (p1mask | p2mask);
8145 clear_qp_implies (p1mask | p2mask, 0);
8149 clear_qp_implies (p1mask | p2mask, p1mask | p2mask);
8150 if (strstr (idesc->name, ".unc") != NULL)
8152 add_qp_mutex (p1mask | p2mask);
8153 if (CURR_SLOT.qp_regno != 0)
8155 add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P,
8156 CURR_SLOT.qp_regno);
8157 add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P,
8158 CURR_SLOT.qp_regno);
8161 else if (CURR_SLOT.qp_regno == 0)
8163 add_qp_mutex (p1mask | p2mask);
8167 clear_qp_mutex (p1mask | p2mask);
8171 /* Look for mov imm insns into GRs. */
8172 else if (idesc->operands[0] == IA64_OPND_R1
8173 && (idesc->operands[1] == IA64_OPND_IMM22
8174 || idesc->operands[1] == IA64_OPND_IMMU64)
8175 && (strcmp (idesc->name, "mov") == 0
8176 || strcmp (idesc->name, "movl") == 0))
8178 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
8179 if (regno > 0 && regno < NELEMS (gr_values))
8181 gr_values[regno].known = 1;
8182 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number;
8183 gr_values[regno].path = md.path;
8185 fprintf (stderr, " Know gr%d = 0x%llx\n",
8186 regno, gr_values[regno].value);
8191 clear_qp_mutex (qp_changemask);
8192 clear_qp_implies (qp_changemask, qp_changemask);
8196 /* Return whether the given predicate registers are currently mutex. */
8199 qp_mutex (p1, p2, path)
8209 mask = ((valueT) 1 << p1) | (valueT) 1 << p2;
8210 for (i = 0; i < qp_mutexeslen; i++)
8212 if (qp_mutexes[i].path >= path
8213 && (qp_mutexes[i].prmask & mask) == mask)
8220 /* Return whether the given resource is in the given insn's list of chks
8221 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8225 resources_match (rs, idesc, note, qp_regno, path)
8227 struct ia64_opcode *idesc;
8232 struct rsrc specs[MAX_SPECS];
8235 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8236 we don't need to check. One exception is note 11, which indicates that
8237 target predicates are written regardless of PR[qp]. */
8238 if (qp_mutex (rs->qp_regno, qp_regno, path)
8242 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path);
8245 /* UNAT checking is a bit more specific than other resources */
8246 if (rs->dependency->specifier == IA64_RS_AR_UNAT
8247 && specs[count].mem_offset.hint
8248 && rs->mem_offset.hint)
8250 if (rs->mem_offset.base == specs[count].mem_offset.base)
8252 if (((rs->mem_offset.offset >> 3) & 0x3F) ==
8253 ((specs[count].mem_offset.offset >> 3) & 0x3F))
8260 /* Skip apparent PR write conflicts where both writes are an AND or both
8261 writes are an OR. */
8262 if (rs->dependency->specifier == IA64_RS_PR
8263 || rs->dependency->specifier == IA64_RS_PRr
8264 || rs->dependency->specifier == IA64_RS_PR63)
8266 if (specs[count].cmp_type != CMP_NONE
8267 && specs[count].cmp_type == rs->cmp_type)
8270 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n",
8271 dv_mode[rs->dependency->mode],
8272 rs->dependency->specifier != IA64_RS_PR63 ?
8273 specs[count].index : 63);
8278 " %s on parallel compare conflict %s vs %s on PR%d\n",
8279 dv_mode[rs->dependency->mode],
8280 dv_cmp_type[rs->cmp_type],
8281 dv_cmp_type[specs[count].cmp_type],
8282 rs->dependency->specifier != IA64_RS_PR63 ?
8283 specs[count].index : 63);
8287 /* If either resource is not specific, conservatively assume a conflict
8289 if (!specs[count].specific || !rs->specific)
8291 else if (specs[count].index == rs->index)
8296 fprintf (stderr, " No %s conflicts\n", rs->dependency->name);
8302 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8303 insert a stop to create the break. Update all resource dependencies
8304 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8305 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8306 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8310 insn_group_break (insert_stop, qp_regno, save_current)
8317 if (insert_stop && md.num_slots_in_use > 0)
8318 PREV_SLOT.end_of_insn_group = 1;
8322 fprintf (stderr, " Insn group break%s",
8323 (insert_stop ? " (w/stop)" : ""));
8325 fprintf (stderr, " effective for QP=%d", qp_regno);
8326 fprintf (stderr, "\n");
8330 while (i < regdepslen)
8332 const struct ia64_dependency *dep = regdeps[i].dependency;
8335 && regdeps[i].qp_regno != qp_regno)
8342 && CURR_SLOT.src_file == regdeps[i].file
8343 && CURR_SLOT.src_line == regdeps[i].line)
8349 /* clear dependencies which are automatically cleared by a stop, or
8350 those that have reached the appropriate state of insn serialization */
8351 if (dep->semantics == IA64_DVS_IMPLIED
8352 || dep->semantics == IA64_DVS_IMPLIEDF
8353 || regdeps[i].insn_srlz == STATE_SRLZ)
8355 print_dependency ("Removing", i);
8356 regdeps[i] = regdeps[--regdepslen];
8360 if (dep->semantics == IA64_DVS_DATA
8361 || dep->semantics == IA64_DVS_INSTR
8362 || dep->semantics == IA64_DVS_SPECIFIC)
8364 if (regdeps[i].insn_srlz == STATE_NONE)
8365 regdeps[i].insn_srlz = STATE_STOP;
8366 if (regdeps[i].data_srlz == STATE_NONE)
8367 regdeps[i].data_srlz = STATE_STOP;
8374 /* Add the given resource usage spec to the list of active dependencies. */
8377 mark_resource (idesc, dep, spec, depind, path)
8378 struct ia64_opcode *idesc;
8379 const struct ia64_dependency *dep;
8384 if (regdepslen == regdepstotlen)
8386 regdepstotlen += 20;
8387 regdeps = (struct rsrc *)
8388 xrealloc ((void *) regdeps,
8389 regdepstotlen * sizeof(struct rsrc));
8392 regdeps[regdepslen] = *spec;
8393 regdeps[regdepslen].depind = depind;
8394 regdeps[regdepslen].path = path;
8395 regdeps[regdepslen].file = CURR_SLOT.src_file;
8396 regdeps[regdepslen].line = CURR_SLOT.src_line;
8398 print_dependency ("Adding", regdepslen);
8404 print_dependency (action, depind)
8410 fprintf (stderr, " %s %s '%s'",
8411 action, dv_mode[(regdeps[depind].dependency)->mode],
8412 (regdeps[depind].dependency)->name);
8413 if (regdeps[depind].specific && regdeps[depind].index != 0)
8414 fprintf (stderr, " (%d)", regdeps[depind].index);
8415 if (regdeps[depind].mem_offset.hint)
8416 fprintf (stderr, " 0x%llx+0x%llx",
8417 regdeps[depind].mem_offset.base,
8418 regdeps[depind].mem_offset.offset);
8419 fprintf (stderr, "\n");
8424 instruction_serialization ()
8428 fprintf (stderr, " Instruction serialization\n");
8429 for (i = 0; i < regdepslen; i++)
8430 if (regdeps[i].insn_srlz == STATE_STOP)
8431 regdeps[i].insn_srlz = STATE_SRLZ;
8435 data_serialization ()
8439 fprintf (stderr, " Data serialization\n");
8440 while (i < regdepslen)
8442 if (regdeps[i].data_srlz == STATE_STOP
8443 /* Note: as of 991210, all "other" dependencies are cleared by a
8444 data serialization. This might change with new tables */
8445 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER)
8447 print_dependency ("Removing", i);
8448 regdeps[i] = regdeps[--regdepslen];
8455 /* Insert stops and serializations as needed to avoid DVs. */
8458 remove_marked_resource (rs)
8461 switch (rs->dependency->semantics)
8463 case IA64_DVS_SPECIFIC:
8465 fprintf (stderr, "Implementation-specific, assume worst case...\n");
8466 /* ...fall through... */
8467 case IA64_DVS_INSTR:
8469 fprintf (stderr, "Inserting instr serialization\n");
8470 if (rs->insn_srlz < STATE_STOP)
8471 insn_group_break (1, 0, 0);
8472 if (rs->insn_srlz < STATE_SRLZ)
8474 int oldqp = CURR_SLOT.qp_regno;
8475 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8476 /* Manually jam a srlz.i insn into the stream */
8477 CURR_SLOT.qp_regno = 0;
8478 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
8479 instruction_serialization ();
8480 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8481 if (++md.num_slots_in_use >= NUM_SLOTS)
8483 CURR_SLOT.qp_regno = oldqp;
8484 CURR_SLOT.idesc = oldidesc;
8486 insn_group_break (1, 0, 0);
8488 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all
8489 "other" types of DV are eliminated
8490 by a data serialization */
8493 fprintf (stderr, "Inserting data serialization\n");
8494 if (rs->data_srlz < STATE_STOP)
8495 insn_group_break (1, 0, 0);
8497 int oldqp = CURR_SLOT.qp_regno;
8498 struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
8499 /* Manually jam a srlz.d insn into the stream */
8500 CURR_SLOT.qp_regno = 0;
8501 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
8502 data_serialization ();
8503 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8504 if (++md.num_slots_in_use >= NUM_SLOTS)
8506 CURR_SLOT.qp_regno = oldqp;
8507 CURR_SLOT.idesc = oldidesc;
8510 case IA64_DVS_IMPLIED:
8511 case IA64_DVS_IMPLIEDF:
8513 fprintf (stderr, "Inserting stop\n");
8514 insn_group_break (1, 0, 0);
8521 /* Check the resources used by the given opcode against the current dependency
8524 The check is run once for each execution path encountered. In this case,
8525 a unique execution path is the sequence of instructions following a code
8526 entry point, e.g. the following has three execution paths, one starting
8527 at L0, one at L1, and one at L2.
8536 check_dependencies (idesc)
8537 struct ia64_opcode *idesc;
8539 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8543 /* Note that the number of marked resources may change within the
8544 loop if in auto mode. */
8546 while (i < regdepslen)
8548 struct rsrc *rs = ®deps[i];
8549 const struct ia64_dependency *dep = rs->dependency;
8554 if (dep->semantics == IA64_DVS_NONE
8555 || (chkind = depends_on (rs->depind, idesc)) == -1)
8561 note = NOTE (opdeps->chks[chkind]);
8563 /* Check this resource against each execution path seen thus far. */
8564 for (path = 0; path <= md.path; path++)
8568 /* If the dependency wasn't on the path being checked, ignore it. */
8569 if (rs->path < path)
8572 /* If the QP for this insn implies a QP which has branched, don't
8573 bother checking. Ed. NOTE: I don't think this check is terribly
8574 useful; what's the point of generating code which will only be
8575 reached if its QP is zero?
8576 This code was specifically inserted to handle the following code,
8577 based on notes from Intel's DV checking code, where p1 implies p2.
8583 if (CURR_SLOT.qp_regno != 0)
8587 for (implies = 0; implies < qp_implieslen; implies++)
8589 if (qp_implies[implies].path >= path
8590 && qp_implies[implies].p1 == CURR_SLOT.qp_regno
8591 && qp_implies[implies].p2_branched)
8601 if ((matchtype = resources_match (rs, idesc, note,
8602 CURR_SLOT.qp_regno, path)) != 0)
8605 char pathmsg[256] = "";
8606 char indexmsg[256] = "";
8607 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0);
8610 sprintf (pathmsg, " when entry is at label '%s'",
8611 md.entry_labels[path - 1]);
8612 if (rs->specific && rs->index != 0)
8613 sprintf (indexmsg, ", specific resource number is %d",
8615 sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8617 (certain ? "violates" : "may violate"),
8618 dv_mode[dep->mode], dep->name,
8619 dv_sem[dep->semantics],
8622 if (md.explicit_mode)
8624 as_warn ("%s", msg);
8626 as_warn (_("Only the first path encountering the conflict "
8628 as_warn_where (rs->file, rs->line,
8629 _("This is the location of the "
8630 "conflicting usage"));
8631 /* Don't bother checking other paths, to avoid duplicating
8638 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line);
8640 remove_marked_resource (rs);
8642 /* since the set of dependencies has changed, start over */
8643 /* FIXME -- since we're removing dvs as we go, we
8644 probably don't really need to start over... */
8657 /* Register new dependencies based on the given opcode. */
8660 mark_resources (idesc)
8661 struct ia64_opcode *idesc;
8664 const struct ia64_opcode_dependency *opdeps = idesc->dependencies;
8665 int add_only_qp_reads = 0;
8667 /* A conditional branch only uses its resources if it is taken; if it is
8668 taken, we stop following that path. The other branch types effectively
8669 *always* write their resources. If it's not taken, register only QP
8671 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc))
8673 add_only_qp_reads = 1;
8677 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name);
8679 for (i = 0; i < opdeps->nregs; i++)
8681 const struct ia64_dependency *dep;
8682 struct rsrc specs[MAX_SPECS];
8687 dep = ia64_find_dependency (opdeps->regs[i]);
8688 note = NOTE (opdeps->regs[i]);
8690 if (add_only_qp_reads
8691 && !(dep->mode == IA64_DV_WAR
8692 && (dep->specifier == IA64_RS_PR
8693 || dep->specifier == IA64_RS_PRr
8694 || dep->specifier == IA64_RS_PR63)))
8697 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
8700 if (md.debug_dv && !count)
8701 fprintf (stderr, " No %s %s usage found (path %d)\n",
8702 dv_mode[dep->mode], dep->name, md.path);
8707 mark_resource (idesc, dep, &specs[count],
8708 DEP (opdeps->regs[i]), md.path);
8711 /* The execution path may affect register values, which may in turn
8712 affect which indirect-access resources are accessed. */
8713 switch (dep->specifier)
8725 for (path = 0; path < md.path; path++)
8727 count = specify_resource (dep, idesc, DV_REG, specs, note, path);
8729 mark_resource (idesc, dep, &specs[count],
8730 DEP (opdeps->regs[i]), path);
8737 /* Remove dependencies when they no longer apply. */
8740 update_dependencies (idesc)
8741 struct ia64_opcode *idesc;
8745 if (strcmp (idesc->name, "srlz.i") == 0)
8747 instruction_serialization ();
8749 else if (strcmp (idesc->name, "srlz.d") == 0)
8751 data_serialization ();
8753 else if (is_interruption_or_rfi (idesc)
8754 || is_taken_branch (idesc))
8756 /* Although technically the taken branch doesn't clear dependencies
8757 which require a srlz.[id], we don't follow the branch; the next
8758 instruction is assumed to start with a clean slate. */
8762 else if (is_conditional_branch (idesc)
8763 && CURR_SLOT.qp_regno != 0)
8765 int is_call = strstr (idesc->name, ".call") != NULL;
8767 for (i = 0; i < qp_implieslen; i++)
8769 /* If the conditional branch's predicate is implied by the predicate
8770 in an existing dependency, remove that dependency. */
8771 if (qp_implies[i].p2 == CURR_SLOT.qp_regno)
8774 /* Note that this implied predicate takes a branch so that if
8775 a later insn generates a DV but its predicate implies this
8776 one, we can avoid the false DV warning. */
8777 qp_implies[i].p2_branched = 1;
8778 while (depind < regdepslen)
8780 if (regdeps[depind].qp_regno == qp_implies[i].p1)
8782 print_dependency ("Removing", depind);
8783 regdeps[depind] = regdeps[--regdepslen];
8790 /* Any marked resources which have this same predicate should be
8791 cleared, provided that the QP hasn't been modified between the
8792 marking instruction and the branch. */
8795 insn_group_break (0, CURR_SLOT.qp_regno, 1);
8800 while (i < regdepslen)
8802 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno
8803 && regdeps[i].link_to_qp_branch
8804 && (regdeps[i].file != CURR_SLOT.src_file
8805 || regdeps[i].line != CURR_SLOT.src_line))
8807 /* Treat like a taken branch */
8808 print_dependency ("Removing", i);
8809 regdeps[i] = regdeps[--regdepslen];
8818 /* Examine the current instruction for dependency violations. */
8822 struct ia64_opcode *idesc;
8826 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n",
8827 idesc->name, CURR_SLOT.src_line,
8828 idesc->dependencies->nchks,
8829 idesc->dependencies->nregs);
8832 /* Look through the list of currently marked resources; if the current
8833 instruction has the dependency in its chks list which uses that resource,
8834 check against the specific resources used. */
8835 check_dependencies (idesc);
8837 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8838 then add them to the list of marked resources. */
8839 mark_resources (idesc);
8841 /* There are several types of dependency semantics, and each has its own
8842 requirements for being cleared
8844 Instruction serialization (insns separated by interruption, rfi, or
8845 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8847 Data serialization (instruction serialization, or writer + srlz.d +
8848 reader, where writer and srlz.d are in separate groups) clears
8849 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8850 always be the case).
8852 Instruction group break (groups separated by stop, taken branch,
8853 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8855 update_dependencies (idesc);
8857 /* Sometimes, knowing a register value allows us to avoid giving a false DV
8858 warning. Keep track of as many as possible that are useful. */
8859 note_register_values (idesc);
8861 /* We don't need or want this anymore. */
8862 md.mem_offset.hint = 0;
8867 /* Translate one line of assembly. Pseudo ops and labels do not show
8873 char *saved_input_line_pointer, *mnemonic;
8874 const struct pseudo_opcode *pdesc;
8875 struct ia64_opcode *idesc;
8876 unsigned char qp_regno;
8880 saved_input_line_pointer = input_line_pointer;
8881 input_line_pointer = str;
8883 /* extract the opcode (mnemonic): */
8885 mnemonic = input_line_pointer;
8886 ch = get_symbol_end ();
8887 pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic);
8890 *input_line_pointer = ch;
8891 (*pdesc->handler) (pdesc->arg);
8895 /* Find the instruction descriptor matching the arguments. */
8897 idesc = ia64_find_opcode (mnemonic);
8898 *input_line_pointer = ch;
8901 as_bad ("Unknown opcode `%s'", mnemonic);
8905 idesc = parse_operands (idesc);
8909 /* Handle the dynamic ops we can handle now: */
8910 if (idesc->type == IA64_TYPE_DYN)
8912 if (strcmp (idesc->name, "add") == 0)
8914 if (CURR_SLOT.opnd[2].X_op == O_register
8915 && CURR_SLOT.opnd[2].X_add_number < 4)
8919 ia64_free_opcode (idesc);
8920 idesc = ia64_find_opcode (mnemonic);
8922 know (!idesc->next);
8925 else if (strcmp (idesc->name, "mov") == 0)
8927 enum ia64_opnd opnd1, opnd2;
8930 opnd1 = idesc->operands[0];
8931 opnd2 = idesc->operands[1];
8932 if (opnd1 == IA64_OPND_AR3)
8934 else if (opnd2 == IA64_OPND_AR3)
8938 if (CURR_SLOT.opnd[rop].X_op == O_register
8939 && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
8943 ia64_free_opcode (idesc);
8944 idesc = ia64_find_opcode (mnemonic);
8945 while (idesc != NULL
8946 && (idesc->operands[0] != opnd1
8947 || idesc->operands[1] != opnd2))
8948 idesc = get_next_opcode (idesc);
8953 if (md.qp.X_op == O_register)
8955 qp_regno = md.qp.X_add_number - REG_P;
8956 md.qp.X_op = O_absent;
8959 flags = idesc->flags;
8961 if ((flags & IA64_OPCODE_FIRST) != 0)
8962 insn_group_break (1, 0, 0);
8964 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0)
8966 as_bad ("`%s' cannot be predicated", idesc->name);
8970 /* Build the instruction. */
8971 CURR_SLOT.qp_regno = qp_regno;
8972 CURR_SLOT.idesc = idesc;
8973 as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
8974 if (debug_type == DEBUG_DWARF2)
8975 dwarf2_where (&CURR_SLOT.debug_line);
8977 /* Add unwind entry, if there is one. */
8978 if (unwind.current_entry)
8980 CURR_SLOT.unwind_record = unwind.current_entry;
8981 unwind.current_entry = NULL;
8984 /* Check for dependency violations. */
8988 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
8989 if (++md.num_slots_in_use >= NUM_SLOTS)
8992 if ((flags & IA64_OPCODE_LAST) != 0)
8993 insn_group_break (1, 0, 0);
8995 md.last_text_seg = now_seg;
8998 input_line_pointer = saved_input_line_pointer;
9001 /* Called when symbol NAME cannot be found in the symbol table.
9002 Should be used for dynamic valued symbols only. */
9005 md_undefined_symbol (name)
9011 /* Called for any expression that can not be recognized. When the
9012 function is called, `input_line_pointer' will point to the start of
9019 enum pseudo_type pseudo_type;
9024 switch (*input_line_pointer)
9027 /* Find what relocation pseudo-function we're dealing with. */
9029 ch = *++input_line_pointer;
9030 for (i = 0; i < NELEMS (pseudo_func); ++i)
9031 if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
9033 len = strlen (pseudo_func[i].name);
9034 if (strncmp (pseudo_func[i].name + 1,
9035 input_line_pointer + 1, len - 1) == 0
9036 && !is_part_of_name (input_line_pointer[len]))
9038 input_line_pointer += len;
9039 pseudo_type = pseudo_func[i].type;
9043 switch (pseudo_type)
9045 case PSEUDO_FUNC_RELOC:
9047 if (*input_line_pointer != '(')
9049 as_bad ("Expected '('");
9053 ++input_line_pointer;
9055 if (*input_line_pointer++ != ')')
9057 as_bad ("Missing ')'");
9060 if (e->X_op != O_symbol)
9062 if (e->X_op != O_pseudo_fixup)
9064 as_bad ("Not a symbolic expression");
9067 if (S_GET_VALUE (e->X_op_symbol) == FUNC_FPTR_RELATIVE
9068 && i == FUNC_LT_RELATIVE)
9069 i = FUNC_LT_FPTR_RELATIVE;
9072 as_bad ("Illegal combination of relocation functions");
9076 /* Make sure gas doesn't get rid of local symbols that are used
9078 e->X_op = O_pseudo_fixup;
9079 e->X_op_symbol = pseudo_func[i].u.sym;
9082 case PSEUDO_FUNC_CONST:
9083 e->X_op = O_constant;
9084 e->X_add_number = pseudo_func[i].u.ival;
9087 case PSEUDO_FUNC_REG:
9088 e->X_op = O_register;
9089 e->X_add_number = pseudo_func[i].u.ival;
9093 name = input_line_pointer - 1;
9095 as_bad ("Unknown pseudo function `%s'", name);
9101 ++input_line_pointer;
9103 if (*input_line_pointer != ']')
9105 as_bad ("Closing bracket misssing");
9110 if (e->X_op != O_register)
9111 as_bad ("Register expected as index");
9113 ++input_line_pointer;
9124 ignore_rest_of_line ();
9127 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9128 a section symbol plus some offset. For relocs involving @fptr(),
9129 directives we don't want such adjustments since we need to have the
9130 original symbol's name in the reloc. */
9132 ia64_fix_adjustable (fix)
9135 /* Prevent all adjustments to global symbols */
9136 if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
9139 switch (fix->fx_r_type)
9141 case BFD_RELOC_IA64_FPTR64I:
9142 case BFD_RELOC_IA64_FPTR32MSB:
9143 case BFD_RELOC_IA64_FPTR32LSB:
9144 case BFD_RELOC_IA64_FPTR64MSB:
9145 case BFD_RELOC_IA64_FPTR64LSB:
9146 case BFD_RELOC_IA64_LTOFF_FPTR22:
9147 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9157 ia64_force_relocation (fix)
9160 switch (fix->fx_r_type)
9162 case BFD_RELOC_IA64_FPTR64I:
9163 case BFD_RELOC_IA64_FPTR32MSB:
9164 case BFD_RELOC_IA64_FPTR32LSB:
9165 case BFD_RELOC_IA64_FPTR64MSB:
9166 case BFD_RELOC_IA64_FPTR64LSB:
9168 case BFD_RELOC_IA64_LTOFF22:
9169 case BFD_RELOC_IA64_LTOFF64I:
9170 case BFD_RELOC_IA64_LTOFF_FPTR22:
9171 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9172 case BFD_RELOC_IA64_PLTOFF22:
9173 case BFD_RELOC_IA64_PLTOFF64I:
9174 case BFD_RELOC_IA64_PLTOFF64MSB:
9175 case BFD_RELOC_IA64_PLTOFF64LSB:
9184 /* Decide from what point a pc-relative relocation is relative to,
9185 relative to the pc-relative fixup. Er, relatively speaking. */
9187 ia64_pcrel_from_section (fix, sec)
9191 unsigned long off = fix->fx_frag->fr_address + fix->fx_where;
9193 if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE)
9199 /* This is called whenever some data item (not an instruction) needs a
9200 fixup. We pick the right reloc code depending on the byteorder
9201 currently in effect. */
9203 ia64_cons_fix_new (f, where, nbytes, exp)
9209 bfd_reloc_code_real_type code;
9214 /* There are no reloc for 8 and 16 bit quantities, but we allow
9215 them here since they will work fine as long as the expression
9216 is fully defined at the end of the pass over the source file. */
9217 case 1: code = BFD_RELOC_8; break;
9218 case 2: code = BFD_RELOC_16; break;
9220 if (target_big_endian)
9221 code = BFD_RELOC_IA64_DIR32MSB;
9223 code = BFD_RELOC_IA64_DIR32LSB;
9227 if (target_big_endian)
9228 code = BFD_RELOC_IA64_DIR64MSB;
9230 code = BFD_RELOC_IA64_DIR64LSB;
9234 as_bad ("Unsupported fixup size %d", nbytes);
9235 ignore_rest_of_line ();
9238 if (exp->X_op == O_pseudo_fixup)
9241 exp->X_op = O_symbol;
9242 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code);
9244 fix = fix_new_exp (f, where, nbytes, exp, 0, code);
9245 /* We need to store the byte order in effect in case we're going
9246 to fix an 8 or 16 bit relocation (for which there no real
9247 relocs available). See md_apply_fix(). */
9248 fix->tc_fix_data.bigendian = target_big_endian;
9251 /* Return the actual relocation we wish to associate with the pseudo
9252 reloc described by SYM and R_TYPE. SYM should be one of the
9253 symbols in the pseudo_func array, or NULL. */
9255 static bfd_reloc_code_real_type
9256 ia64_gen_real_reloc_type (sym, r_type)
9258 bfd_reloc_code_real_type r_type;
9260 bfd_reloc_code_real_type new = 0;
9267 switch (S_GET_VALUE (sym))
9269 case FUNC_FPTR_RELATIVE:
9272 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break;
9273 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break;
9274 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break;
9275 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break;
9276 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break;
9281 case FUNC_GP_RELATIVE:
9284 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break;
9285 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break;
9286 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break;
9287 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break;
9288 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break;
9289 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break;
9294 case FUNC_LT_RELATIVE:
9297 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break;
9298 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break;
9303 case FUNC_PC_RELATIVE:
9306 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break;
9307 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break;
9308 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break;
9309 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break;
9310 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break;
9311 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break;
9316 case FUNC_PLT_RELATIVE:
9319 case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break;
9320 case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break;
9321 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break;
9322 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break;
9327 case FUNC_SEC_RELATIVE:
9330 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break;
9331 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break;
9332 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break;
9333 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break;
9338 case FUNC_SEG_RELATIVE:
9341 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break;
9342 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break;
9343 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break;
9344 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break;
9349 case FUNC_LTV_RELATIVE:
9352 case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break;
9353 case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break;
9354 case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break;
9355 case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break;
9360 case FUNC_LT_FPTR_RELATIVE:
9363 case BFD_RELOC_IA64_IMM22:
9364 new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
9365 case BFD_RELOC_IA64_IMM64:
9366 new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
9374 /* Hmmmm. Should this ever occur? */
9381 /* Here is where generate the appropriate reloc for pseudo relocation
9384 ia64_validate_fix (fix)
9387 switch (fix->fx_r_type)
9389 case BFD_RELOC_IA64_FPTR64I:
9390 case BFD_RELOC_IA64_FPTR32MSB:
9391 case BFD_RELOC_IA64_FPTR64LSB:
9392 case BFD_RELOC_IA64_LTOFF_FPTR22:
9393 case BFD_RELOC_IA64_LTOFF_FPTR64I:
9394 if (fix->fx_offset != 0)
9395 as_bad_where (fix->fx_file, fix->fx_line,
9396 "No addend allowed in @fptr() relocation");
9406 fix_insn (fix, odesc, value)
9408 const struct ia64_operand *odesc;
9411 bfd_vma insn[3], t0, t1, control_bits;
9416 slot = fix->fx_where & 0x3;
9417 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot);
9419 /* Bundles are always in little-endian byte order */
9420 t0 = bfd_getl64 (fixpos);
9421 t1 = bfd_getl64 (fixpos + 8);
9422 control_bits = t0 & 0x1f;
9423 insn[0] = (t0 >> 5) & 0x1ffffffffffLL;
9424 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
9425 insn[2] = (t1 >> 23) & 0x1ffffffffffLL;
9428 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
9430 insn[1] = (value >> 22) & 0x1ffffffffffLL;
9431 insn[2] |= (((value & 0x7f) << 13)
9432 | (((value >> 7) & 0x1ff) << 27)
9433 | (((value >> 16) & 0x1f) << 22)
9434 | (((value >> 21) & 0x1) << 21)
9435 | (((value >> 63) & 0x1) << 36));
9437 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
9439 if (value & ~0x3fffffffffffffffULL)
9440 err = "integer operand out of range";
9441 insn[1] = (value >> 21) & 0x1ffffffffffLL;
9442 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36));
9444 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
9447 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2;
9448 insn[2] |= ((((value >> 59) & 0x1) << 36)
9449 | (((value >> 0) & 0xfffff) << 13));
9452 err = (*odesc->insert) (odesc, value, insn + slot);
9455 as_bad_where (fix->fx_file, fix->fx_line, err);
9457 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46);
9458 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23);
9459 number_to_chars_littleendian (fixpos + 0, t0, 8);
9460 number_to_chars_littleendian (fixpos + 8, t1, 8);
9463 /* Attempt to simplify or even eliminate a fixup. The return value is
9464 ignored; perhaps it was once meaningful, but now it is historical.
9465 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9467 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9470 md_apply_fix3 (fix, valuep, seg)
9476 valueT value = *valuep;
9479 fixpos = fix->fx_frag->fr_literal + fix->fx_where;
9483 switch (fix->fx_r_type)
9485 case BFD_RELOC_IA64_DIR32MSB:
9486 fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
9490 case BFD_RELOC_IA64_DIR32LSB:
9491 fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
9495 case BFD_RELOC_IA64_DIR64MSB:
9496 fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
9500 case BFD_RELOC_IA64_DIR64LSB:
9501 fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
9511 switch (fix->fx_r_type)
9514 as_bad_where (fix->fx_file, fix->fx_line,
9515 "%s must have a constant value",
9516 elf64_ia64_operands[fix->tc_fix_data.opnd].desc);
9523 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9524 work. There should be a better way to handle this. */
9526 fix->fx_offset += fix->fx_where + fix->fx_frag->fr_address;
9528 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL)
9530 if (fix->tc_fix_data.bigendian)
9531 number_to_chars_bigendian (fixpos, value, fix->fx_size);
9533 number_to_chars_littleendian (fixpos, value, fix->fx_size);
9539 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value);
9546 /* Generate the BFD reloc to be stuck in the object file from the
9547 fixup used internally in the assembler. */
9550 tc_gen_reloc (sec, fixp)
9556 reloc = xmalloc (sizeof (*reloc));
9557 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9558 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
9559 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
9560 reloc->addend = fixp->fx_offset;
9561 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
9565 as_bad_where (fixp->fx_file, fixp->fx_line,
9566 "Cannot represent %s relocation in object file",
9567 bfd_get_reloc_code_name (fixp->fx_r_type));
9572 /* Turn a string in input_line_pointer into a floating point constant
9573 of type TYPE, and store the appropriate bytes in *LIT. The number
9574 of LITTLENUMS emitted is stored in *SIZE. An error message is
9575 returned, or NULL on OK. */
9577 #define MAX_LITTLENUMS 5
9580 md_atof (type, lit, size)
9585 LITTLENUM_TYPE words[MAX_LITTLENUMS];
9586 LITTLENUM_TYPE *word;
9616 return "Bad call to MD_ATOF()";
9618 t = atof_ieee (input_line_pointer, type, words);
9620 input_line_pointer = t;
9621 *size = prec * sizeof (LITTLENUM_TYPE);
9623 for (word = words + prec - 1; prec--;)
9625 md_number_to_chars (lit, (long) (*word--), sizeof (LITTLENUM_TYPE));
9626 lit += sizeof (LITTLENUM_TYPE);
9631 /* Round up a section's size to the appropriate boundary. */
9633 md_section_align (seg, size)
9637 int align = bfd_get_section_alignment (stdoutput, seg);
9638 valueT mask = ((valueT) 1 << align) - 1;
9640 return (size + mask) & ~mask;
9643 /* Handle ia64 specific semantics of the align directive. */
9646 ia64_md_do_align (n, fill, len, max)
9652 /* Fill any pending bundle with nops. */
9653 if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
9654 ia64_flush_insns ();
9656 /* When we align code in a text section, emit a bundle of 3 nops instead of
9657 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9658 N is log base 2 of the requested alignment. */
9660 && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE
9663 /* Use mfi bundle of nops with no stop bits. */
9664 static const unsigned char be_nop[]
9665 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9666 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9667 static const unsigned char le_nop[]
9668 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9669 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9671 /* Make sure we are on a 16-byte boundary, in case someone has been
9672 putting data into a text section. */
9673 frag_align (4, 0, 0);
9675 if (target_big_endian)
9676 frag_align_pattern (n, be_nop, 16, max);
9678 frag_align_pattern (n, le_nop, 16, max);