1 /* to sanitize : grep -v XL */
2 /* tc-i960.c - All the i80960-specific stuff
3 Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
5 This file is part of GAS.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 /* See comment on md_parse_option for 80960-specific invocation options. */
23 /* There are 4 different lengths of (potentially) symbol-based displacements
24 in the 80960 instruction set, each of which could require address fix-ups
25 and (in the case of external symbols) emission of relocation directives:
28 This is a standard length for the base assembler and requires no
32 This is a non-standard length, but the base assembler has a
33 hook for bit field address fixups: the fixS structure can
34 point to a descriptor of the field, in which case our
35 md_number_to_field() routine gets called to process it.
37 I made the hook a little cleaner by having fix_new() (in the base
38 assembler) return a pointer to the fixS in question. And I made it a
39 little simpler by storing the field size (in this case 13) instead of
40 of a pointer to another structure: 80960 displacements are ALWAYS
41 stored in the low-order bits of a 4-byte word.
43 Since the target of a COBR cannot be external, no relocation
44 directives for this size displacement have to be generated.
45 But the base assembler had to be modified to issue error
46 messages if the symbol did turn out to be external.
49 Fixups are handled as for the 13-bit case (except that 24 is stored
52 The relocation directive generated is the same as that for the 32-bit
53 displacement, except that it's PC-relative (the 32-bit displacement
54 never is). The i80960 version of the linker needs a mod to
55 distinguish and handle the 24-bit case.
58 MEMA formats are always promoted to MEMB (32-bit) if the displacement
59 is based on a symbol, because it could be relocated at link time.
60 The only time we use the 12-bit format is if an absolute value of
61 less than 4096 is specified, in which case we need neither a fixup nor
62 a relocation directive. */
71 #include "opcode/i960.h"
73 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
75 #define TC_S_IS_SYSPROC(s) ((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
76 #define TC_S_IS_BALNAME(s) (S_GET_OTHER(s) == N_BALNAME)
77 #define TC_S_IS_CALLNAME(s) (S_GET_OTHER(s) == N_CALLNAME)
78 #define TC_S_IS_BADPROC(s) ((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
80 #define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER((s), (p)+1))
81 #define TC_S_GET_SYSPROC(s) (S_GET_OTHER(s)-1)
83 #define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER((s), N_BALNAME))
84 #define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER((s), N_CALLNAME))
85 #define TC_S_FORCE_TO_SYSPROC(s) {;}
87 #else /* ! OBJ_A/BOUT */
90 #define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS(s) == C_SCALL)
91 #define TC_S_IS_BALNAME(s) (SF_GET_BALNAME(s))
92 #define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME(s))
93 #define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
95 #define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
96 #define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
98 #define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME(s))
99 #define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME(s))
100 #define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS((s), C_SCALL))
102 #else /* ! OBJ_COFF */
104 #endif /* ! OBJ_COFF */
105 #endif /* ! OBJ_A/BOUT */
107 extern char *input_line_pointer;
109 #if !defined (BFD_ASSEMBLER) && !defined (BFD)
111 const int md_reloc_size = sizeof (struct reloc);
113 const int md_reloc_size = sizeof (struct relocation_info);
114 #endif /* OBJ_COFF */
117 /* Local i80960 routines. */
119 static void brcnt_emit (); /* Emit branch-prediction instrumentation code */
120 static char *brlab_next (); /* Return next branch local label */
121 void brtab_emit (); /* Emit br-predict instrumentation table */
122 static void cobr_fmt (); /* Generate COBR instruction */
123 static void ctrl_fmt (); /* Generate CTRL instruction */
124 static char *emit (); /* Emit (internally) binary */
125 static int get_args (); /* Break arguments out of comma-separated list */
126 static void get_cdisp (); /* Handle COBR or CTRL displacement */
127 static char *get_ispec (); /* Find index specification string */
128 static int get_regnum (); /* Translate text to register number */
129 static int i_scan (); /* Lexical scan of instruction source */
130 static void mem_fmt (); /* Generate MEMA or MEMB instruction */
131 static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */
132 static void parse_expr (); /* Parse an expression */
133 static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */
134 static void parse_memop (); /* Parse a memory operand */
135 static void parse_po (); /* Parse machine-dependent pseudo-op */
136 static void parse_regop (); /* Parse a register operand */
137 static void reg_fmt (); /* Generate a REG format instruction */
138 void reloc_callj (); /* Relocate a 'callj' instruction */
139 static void relax_cobr (); /* "De-optimize" cobr into compare/branch */
140 static void s_leafproc (); /* Process '.leafproc' pseudo-op */
141 static void s_sysproc (); /* Process '.sysproc' pseudo-op */
142 static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */
143 static void syntax (); /* Give syntax error */
144 static int targ_has_sfr (); /* Target chip supports spec-func register? */
145 static int targ_has_iclass (); /* Target chip supports instruction set? */
147 /* See md_parse_option() for meanings of these options */
148 static char norelax; /* True if -norelax switch seen */
149 static char instrument_branches; /* True if -b switch seen */
151 /* Characters that always start a comment.
152 If the pre-processor is disabled, these aren't very useful.
154 const char comment_chars[] = "#";
156 /* Characters that only start a comment at the beginning of
157 a line. If the line seems to have the form '# 123 filename'
158 .line and .file directives will appear in the pre-processed output.
160 Note that input_file.c hand checks for '#' at the beginning of the
161 first line of the input file. This is because the compiler outputs
162 #NO_APP at the beginning of its output.
165 /* Also note that comments started like this one will always work. */
167 const char line_comment_chars[1];
169 const char line_separator_chars[1];
171 /* Chars that can be used to separate mant from exp in floating point nums */
172 const char EXP_CHARS[] = "eE";
174 /* Chars that mean this number is a floating point constant,
175 as in 0f12.456 or 0d1.2345e12
177 const char FLT_CHARS[] = "fFdDtT";
180 /* Table used by base assembler to relax addresses based on varying length
181 instructions. The fields are:
182 1) most positive reach of this state,
183 2) most negative reach of this state,
184 3) how many bytes this mode will add to the size of the current frag
185 4) which index into the table to try if we can't fit into this one.
187 For i80960, the only application is the (de-)optimization of cobr
188 instructions into separate compare and branch instructions when a 13-bit
189 displacement won't hack it.
191 const relax_typeS md_relax_table[] =
193 {0, 0, 0, 0}, /* State 0 => no more relaxation possible */
194 {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */
195 {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */
198 static void s_endian PARAMS ((int));
200 /* These are the machine dependent pseudo-ops.
202 This table describes all the machine specific pseudo-ops the assembler
203 has to support. The fields are:
204 pseudo-op name without dot
205 function to call to execute this pseudo-op
206 integer arg to pass to the function
211 const pseudo_typeS md_pseudo_table[] =
214 {"endian", s_endian, 0},
215 {"extended", float_cons, 't'},
216 {"leafproc", parse_po, S_LEAFPROC},
217 {"sysproc", parse_po, S_SYSPROC},
225 /* Macros to extract info from an 'expressionS' structure 'e' */
226 #define adds(e) e.X_add_symbol
227 #define offs(e) e.X_add_number
230 /* Branch-prediction bits for CTRL/COBR format opcodes */
231 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
232 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
233 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
236 /* Some instruction opcodes that we need explicitly */
237 #define BE 0x12000000
238 #define BG 0x11000000
239 #define BGE 0x13000000
240 #define BL 0x14000000
241 #define BLE 0x16000000
242 #define BNE 0x15000000
243 #define BNO 0x10000000
244 #define BO 0x17000000
245 #define CHKBIT 0x5a002700
246 #define CMPI 0x5a002080
247 #define CMPO 0x5a002000
250 #define BAL 0x0b000000
251 #define CALL 0x09000000
252 #define CALLS 0x66003800
253 #define RET 0x0a000000
256 /* These masks are used to build up a set of MEMB mode bits. */
259 #define MEMB_BIT 0x1000
263 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
265 #define MEMA_ABASE 0x2000
267 /* Info from which a MEMA or MEMB format instruction can be generated */
270 /* (First) 32 bits of instruction */
272 /* 0-(none), 12- or, 32-bit displacement needed */
274 /* The expression in the source instruction from which the
275 displacement should be determined. */
282 /* The two pieces of info we need to generate a register operand */
285 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
286 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
287 int n; /* Register number or literal value */
291 /* Number and assembler mnemonic for all registers that can appear in
333 /* Numbers for special-function registers are for assembler internal
334 use only: they are scaled back to range [0-31] for binary output. */
370 /* Numbers for floating point registers are for assembler internal
371 use only: they are scaled back to [0-3] for binary output. */
379 { NULL, 0 }, /* END OF LIST */
382 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
383 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
384 #define IS_FP_REG(n) ((n) >= FP0)
386 /* Number and assembler mnemonic for all registers that can appear as
387 'abase' (indirect addressing) registers. */
429 /* For assembler internal use only: this number never appears in binary
433 { NULL, 0 }, /* END OF LIST */
438 static struct hash_control *op_hash; /* Opcode mnemonics */
439 static struct hash_control *reg_hash; /* Register name hash table */
440 static struct hash_control *areg_hash; /* Abase register hash table */
443 /* Architecture for which we are assembling */
444 #define ARCH_ANY 0 /* Default: no architecture checking done */
451 int architecture = ARCH_ANY; /* Architecture requested on invocation line */
452 int iclasses_seen; /* OR of instruction classes (I_* constants)
453 * for which we've actually assembled
458 /* BRANCH-PREDICTION INSTRUMENTATION
460 The following supports generation of branch-prediction instrumentation
461 (turned on by -b switch). The instrumentation collects counts
462 of branches taken/not-taken for later input to a utility that will
463 set the branch prediction bits of the instructions in accordance with
464 the behavior observed. (Note that the KX series does not have
467 The instrumentation consists of:
469 (1) before and after each conditional branch, a call to an external
470 routine that increments and steps over an inline counter. The
471 counter itself, initialized to 0, immediately follows the call
472 instruction. For each branch, the counter following the branch
473 is the number of times the branch was not taken, and the difference
474 between the counters is the number of times it was taken. An
475 example of an instrumented conditional branch:
483 (2) a table of pointers to the instrumented branches, so that an
484 external postprocessing routine can locate all of the counters.
485 the table begins with a 2-word header: a pointer to the next in
486 a linked list of such tables (initialized to 0); and a count
487 of the number of entries in the table (exclusive of the header.
489 Note that input source code is expected to already contain calls
490 an external routine that will link the branch local table into a
494 /* Number of branches instrumented so far. Also used to generate
495 unique local labels for each instrumented branch. */
498 #define BR_LABEL_BASE "LBRANCH"
499 /* Basename of local labels on instrumented branches, to avoid
500 conflict with compiler- generated local labels. */
502 #define BR_CNT_FUNC "__inc_branch"
503 /* Name of the external routine that will increment (and step over) an
506 #define BR_TAB_NAME "__BRANCH_TABLE__"
507 /* Name of the table of pointers to branches. A local (i.e.,
508 non-external) symbol. */
510 /*****************************************************************************
511 md_begin: One-time initialization.
515 *************************************************************************** */
519 int i; /* Loop counter */
520 const struct i960_opcode *oP; /* Pointer into opcode table */
521 const char *retval; /* Value returned by hash functions */
523 op_hash = hash_new ();
524 reg_hash = hash_new ();
525 areg_hash = hash_new ();
527 /* For some reason, the base assembler uses an empty string for "no
528 error message", instead of a NULL pointer. */
531 for (oP = i960_opcodes; oP->name && !retval; oP++)
532 retval = hash_insert (op_hash, oP->name, (PTR) oP);
534 for (i = 0; regnames[i].reg_name && !retval; i++)
535 retval = hash_insert (reg_hash, regnames[i].reg_name,
536 (char *) ®names[i].reg_num);
538 for (i = 0; aregs[i].areg_name && !retval; i++)
539 retval = hash_insert (areg_hash, aregs[i].areg_name,
540 (char *) &aregs[i].areg_num);
543 as_fatal ("Hashing returned \"%s\".", retval);
546 /*****************************************************************************
547 md_assemble: Assemble an instruction
549 Assumptions about the passed-in text:
550 - all comments, labels removed
551 - text is an instruction
552 - all white space compressed to single blanks
553 - all character constants have been replaced with decimal
555 *************************************************************************** */
558 char *textP; /* Source text of instruction */
560 /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
561 mnemonic arg[1-3]->operands, with char constants replaced by
565 int n_ops; /* Number of instruction operands */
566 /* Pointer to instruction description */
567 struct i960_opcode *oP;
568 /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
571 /* Setting of branch-prediction bit(s) to be OR'd into instruction
572 opcode of CTRL/COBR format instructions. */
575 int n; /* Offset of last character in opcode mnemonic */
577 static const char bp_error_msg[] = "branch prediction invalid on this opcode";
580 /* Parse instruction into opcode and operands */
581 memset (args, '\0', sizeof (args));
582 n_ops = i_scan (textP, args);
585 return; /* Error message already issued */
588 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
589 if (!strcmp (args[0], "ldconst"))
591 n_ops = parse_ldconst (args);
600 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
601 n = strlen (args[0]) - 1;
604 if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
606 /* We could check here to see if the target architecture
607 supports branch prediction, but why bother? The bit will
608 just be ignored by processors that don't use it. */
610 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
611 args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
614 /* Look up opcode mnemonic in table and check number of operands.
615 Check that opcode is legal for the target architecture. If all
616 looks good, assemble instruction. */
617 oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
618 if (!oP || !targ_has_iclass (oP->iclass))
620 as_bad ("invalid opcode, \"%s\".", args[0]);
623 else if (n_ops != oP->num_ops)
625 as_bad ("improper number of operands. expecting %d, got %d",
634 ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
635 if (oP->format == FBRA)
637 /* Now generate a 'bno' to same arg */
638 ctrl_fmt (args[1], BNO | bp_bits, 1);
643 cobr_fmt (args, oP->opcode | bp_bits, oP);
648 as_warn (bp_error_msg);
653 if (args[0][0] == 'c' && args[0][1] == 'a')
657 as_warn (bp_error_msg);
659 mem_fmt (args, oP, 1);
669 as_warn (bp_error_msg);
671 mem_fmt (args, oP, 0);
676 as_warn (bp_error_msg);
678 /* Output opcode & set up "fixup" (relocation); flag
679 relocation as 'callj' type. */
680 know (oP->num_ops == 1);
681 get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
684 BAD_CASE (oP->format);
688 } /* md_assemble() */
690 /*****************************************************************************
691 md_number_to_chars: convert a number to target byte order
693 *************************************************************************** */
695 md_number_to_chars (buf, value, n)
700 number_to_chars_littleendian (buf, value, n);
703 /*****************************************************************************
704 md_chars_to_number: convert from target byte order to host byte order.
706 *************************************************************************** */
708 md_chars_to_number (val, n)
709 unsigned char *val; /* Value in target byte order */
710 int n; /* Number of bytes in the input */
714 for (retval = 0; n--;)
723 #define MAX_LITTLENUMS 6
724 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
726 /*****************************************************************************
727 md_atof: convert ascii to floating point
729 Turn a string at input_line_pointer into a floating point constant of type
730 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
731 emitted is returned at 'sizeP'. An error message is returned, or a pointer
732 to an empty message if OK.
734 Note we call the i386 floating point routine, rather than complicating
735 things with more files or symbolic links.
737 *************************************************************************** */
739 md_atof (type, litP, sizeP)
744 LITTLENUM_TYPE words[MAX_LITTLENUMS];
745 LITTLENUM_TYPE *wordP;
765 type = 'x'; /* That's what atof_ieee() understands */
770 return "Bad call to md_atof()";
773 t = atof_ieee (input_line_pointer, type, words);
776 input_line_pointer = t;
779 *sizeP = prec * LNUM_SIZE;
781 /* Output the LITTLENUMs in REVERSE order in accord with i80960
782 word-order. (Dunno why atof_ieee doesn't do it in the right
783 order in the first place -- probably because it's a hack of
786 for (wordP = words + prec - 1; prec--;)
788 md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
789 litP += sizeof (LITTLENUM_TYPE);
796 /*****************************************************************************
799 *************************************************************************** */
801 md_number_to_imm (buf, val, n)
806 md_number_to_chars (buf, val, n);
810 /*****************************************************************************
813 *************************************************************************** */
815 md_number_to_disp (buf, val, n)
820 md_number_to_chars (buf, val, n);
823 /*****************************************************************************
826 Stick a value (an address fixup) into a bit field of
827 previously-generated instruction.
829 *************************************************************************** */
831 md_number_to_field (instrP, val, bfixP)
832 char *instrP; /* Pointer to instruction to be fixed */
833 long val; /* Address fixup value */
834 bit_fixS *bfixP; /* Description of bit field to be fixed up */
836 int numbits; /* Length of bit field to be fixed */
837 long instr; /* 32-bit instruction to be fixed-up */
838 long sign; /* 0 or -1, according to sign bit of 'val' */
840 /* Convert instruction back to host byte order. */
841 instr = md_chars_to_number (instrP, 4);
843 /* Surprise! -- we stored the number of bits to be modified rather
844 than a pointer to a structure. */
845 numbits = (int) bfixP;
848 /* This is a no-op, stuck here by reloc_callj() */
852 know ((numbits == 13) || (numbits == 24));
854 /* Propagate sign bit of 'val' for the given number of bits. Result
855 should be all 0 or all 1. */
856 sign = val >> ((int) numbits - 1);
857 if (((val < 0) && (sign != -1))
858 || ((val > 0) && (sign != 0)))
860 as_bad ("Fixup of %ld too large for field width of %d",
865 /* Put bit field into instruction and write back in target
868 val &= ~(-1 << (int) numbits); /* Clear unused sign bits */
870 md_number_to_chars (instrP, instr, 4);
872 } /* md_number_to_field() */
875 /*****************************************************************************
877 Invocation line includes a switch not recognized by the base assembler.
878 See if it's a processor-specific option. For the 960, these are:
881 Conditional branch instructions that require displacements
882 greater than 13 bits (or that have external targets) should
883 generate errors. The default is to replace each such
884 instruction with the corresponding compare (or chkbit) and
885 branch instructions. Note that the Intel "j" cobr directives
886 are ALWAYS "de-optimized" in this way when necessary,
887 regardless of the setting of this option.
890 Add code to collect information about branches taken, for
891 later optimization of branch prediction bits by a separate
892 tool. COBR and CNTL format instructions have branch
893 prediction bits (in the CX architecture); if "BR" represents
894 an instruction in one of these classes, the following rep-
895 resents the code generated by the assembler:
897 call <increment routine>
898 .word 0 # pre-counter
900 call <increment routine>
901 .word 0 # post-counter
903 A table of all such "Labels" is also generated.
906 -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
907 Select the 80960 architecture. Instructions or features not
908 supported by the selected architecture cause fatal errors.
909 The default is to generate code for any instruction or feature
910 that is supported by SOME version of the 960 (even if this
911 means mixing architectures!).
913 ****************************************************************************/
915 CONST char *md_shortopts = "A:b";
916 struct option md_longopts[] =
918 #define OPTION_LINKRELAX (OPTION_MD_BASE)
919 {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
920 {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
921 #define OPTION_NORELAX (OPTION_MD_BASE + 1)
922 {"norelax", no_argument, NULL, OPTION_NORELAX},
923 {"no-relax", no_argument, NULL, OPTION_NORELAX},
924 {NULL, no_argument, NULL, 0}
926 size_t md_longopts_size = sizeof (md_longopts);
933 static const struct tabentry arch_tab[] =
937 {"SA", ARCH_KA}, /* Synonym for KA */
938 {"SB", ARCH_KB}, /* Synonym for KB */
939 {"KC", ARCH_MC}, /* Synonym for MC */
948 md_parse_option (c, arg)
954 case OPTION_LINKRELAX:
956 flag_keep_locals = 1;
964 instrument_branches = 1;
969 const struct tabentry *tp;
972 for (tp = arch_tab; tp->flag != NULL; tp++)
973 if (!strcmp (p, tp->flag))
976 if (tp->flag == NULL)
978 as_bad ("invalid architecture %s", p);
982 architecture = tp->arch;
994 md_show_usage (stream)
998 fprintf (stream, "I960 options:\n");
999 for (i = 0; arch_tab[i].flag; i++)
1000 fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
1001 fprintf (stream, "\n\
1002 specify variant of 960 architecture\n\
1003 -b add code to collect statistics about branches taken\n\
1004 -link-relax preserve individual alignment directives so linker\n\
1005 can do relaxing (b.out format only)\n\
1006 -no-relax don't alter compare-and-branch instructions for\n\
1007 long displacements\n");
1011 #ifndef BFD_ASSEMBLER
1012 /*****************************************************************************
1014 Called by base assembler after address relaxation is finished: modify
1015 variable fragments according to how much relaxation was done.
1017 If the fragment substate is still 1, a 13-bit displacement was enough
1018 to reach the symbol in question. Set up an address fixup, but otherwise
1019 leave the cobr instruction alone.
1021 If the fragment substate is 2, a 13-bit displacement was not enough.
1022 Replace the cobr with a two instructions (a compare and a branch).
1024 *************************************************************************** */
1026 md_convert_frag (headers, seg, fragP)
1027 object_headers *headers;
1031 fixS *fixP; /* Structure describing needed address fix */
1033 switch (fragP->fr_subtype)
1036 /* LEAVE SINGLE COBR INSTRUCTION */
1037 fixP = fix_new (fragP,
1038 fragP->fr_opcode - fragP->fr_literal,
1045 fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */
1048 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
1052 BAD_CASE (fragP->fr_subtype);
1057 /*****************************************************************************
1058 md_estimate_size_before_relax: How much does it look like *fragP will grow?
1060 Called by base assembler just before address relaxation.
1061 Return the amount by which the fragment will grow.
1063 Any symbol that is now undefined will not become defined; cobr's
1064 based on undefined symbols will have to be replaced with a compare
1065 instruction and a branch instruction, and the code fragment will grow
1068 *************************************************************************** */
1070 md_estimate_size_before_relax (fragP, segment_type)
1071 register fragS *fragP;
1072 register segT segment_type;
1074 /* If symbol is undefined in this segment, go to "relaxed" state
1075 (compare and branch instructions instead of cobr) right now. */
1076 if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
1082 } /* md_estimate_size_before_relax() */
1085 /*****************************************************************************
1087 This routine exists in order to overcome machine byte-order problems
1088 when dealing with bit-field entries in the relocation_info struct.
1090 But relocation info will be used on the host machine only (only
1091 executable code is actually downloaded to the i80960). Therefore,
1092 we leave it in host byte order.
1094 The above comment is no longer true. This routine now really
1095 does do the reordering (Ian Taylor 28 Aug 92).
1097 *************************************************************************** */
1099 md_ri_to_chars (where, ri)
1101 struct relocation_info *ri;
1103 md_number_to_chars (where, ri->r_address,
1104 sizeof (ri->r_address));
1105 where[4] = ri->r_index & 0x0ff;
1106 where[5] = (ri->r_index >> 8) & 0x0ff;
1107 where[6] = (ri->r_index >> 16) & 0x0ff;
1108 where[7] = ((ri->r_pcrel << 0)
1109 | (ri->r_length << 1)
1110 | (ri->r_extern << 3)
1113 | (ri->r_callj << 6));
1116 #ifndef WORKING_DOT_WORD
1118 int md_short_jump_size = 0;
1119 int md_long_jump_size = 0;
1122 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
1129 as_fatal ("failed sanity check.");
1133 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
1135 addressT from_addr, to_addr;
1139 as_fatal ("failed sanity check.");
1143 #endif /* BFD_ASSEMBLER */
1145 /* FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER */
1147 /*****************************************************************************
1148 brcnt_emit: Emit code to increment inline branch counter.
1150 See the comments above the declaration of 'br_cnt' for details on
1151 branch-prediction instrumentation.
1152 *************************************************************************** */
1156 ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */
1157 emit (0); /* Emit inline counter to be incremented */
1160 /*****************************************************************************
1161 brlab_next: generate the next branch local label
1163 See the comments above the declaration of 'br_cnt' for details on
1164 branch-prediction instrumentation.
1165 *************************************************************************** */
1169 static char buf[20];
1171 sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1175 /*****************************************************************************
1176 brtab_emit: generate the fetch-prediction branch table.
1178 See the comments above the declaration of 'br_cnt' for details on
1179 branch-prediction instrumentation.
1181 The code emitted here would be functionally equivalent to the following
1182 example assembler source.
1187 .word 0 # link to next table
1188 .word 3 # length of table
1189 .word LBRANCH0 # 1st entry in table proper
1192 **************************************************************************** */
1198 char *p; /* Where the binary was output to */
1199 /* Pointer to description of deferred address fixup. */
1202 if (!instrument_branches)
1207 subseg_set (data_section, 0); /* .data */
1208 frag_align (2, 0); /* .align 2 */
1209 record_alignment (now_seg, 2);
1210 colon (BR_TAB_NAME); /* BR_TAB_NAME: */
1211 emit (0); /* .word 0 #link to next table */
1212 emit (br_cnt); /* .word n #length of table */
1214 for (i = 0; i < br_cnt; i++)
1216 sprintf (buf, "%s%d", BR_LABEL_BASE, i);
1218 fixP = fix_new (frag_now,
1219 p - frag_now->fr_literal,
1225 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1229 /*****************************************************************************
1230 cobr_fmt: generate a COBR-format instruction
1232 *************************************************************************** */
1235 cobr_fmt (arg, opcode, oP)
1236 /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1238 /* Opcode, with branch-prediction bits already set if necessary. */
1240 /* Pointer to description of instruction. */
1241 struct i960_opcode *oP;
1243 long instr; /* 32-bit instruction */
1244 struct regop regop; /* Description of register operand */
1245 int n; /* Number of operands */
1246 int var_frag; /* 1 if varying length code fragment should
1247 * be emitted; 0 if an address fix
1248 * should be emitted.
1256 /* First operand (if any) of a COBR is always a register
1257 operand. Parse it. */
1258 parse_regop (®op, arg[1], oP->operand[0]);
1259 instr |= (regop.n << 19) | (regop.mode << 13);
1263 /* Second operand (if any) of a COBR is always a register
1264 operand. Parse it. */
1265 parse_regop (®op, arg[2], oP->operand[1]);
1266 instr |= (regop.n << 14) | regop.special;
1277 if (instrument_branches)
1280 colon (brlab_next ());
1283 /* A third operand to a COBR is always a displacement. Parse
1284 it; if it's relaxable (a cobr "j" directive, or any cobr
1285 other than bbs/bbc when the "-norelax" option is not in use)
1286 set up a variable code fragment; otherwise set up an address
1288 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1289 get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1291 if (instrument_branches)
1299 /*****************************************************************************
1300 ctrl_fmt: generate a CTRL-format instruction
1302 *************************************************************************** */
1305 ctrl_fmt (targP, opcode, num_ops)
1306 char *targP; /* Pointer to text of lone operand (if any) */
1307 long opcode; /* Template of instruction */
1308 int num_ops; /* Number of operands */
1310 int instrument; /* TRUE iff we should add instrumentation to track
1311 * how often the branch is taken
1317 emit (opcode); /* Output opcode */
1322 instrument = instrument_branches && (opcode != CALL)
1323 && (opcode != B) && (opcode != RET) && (opcode != BAL);
1328 colon (brlab_next ());
1331 /* The operand MUST be an ip-relative displacment. Parse it
1332 * and set up address fix for the instruction we just output.
1334 get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1345 /*****************************************************************************
1346 emit: output instruction binary
1348 Output instruction binary, in target byte order, 4 bytes at a time.
1349 Return pointer to where it was placed.
1351 *************************************************************************** */
1355 long instr; /* Word to be output, host byte order */
1357 char *toP; /* Where to output it */
1359 toP = frag_more (4); /* Allocate storage */
1360 md_number_to_chars (toP, instr, 4); /* Convert to target byte order */
1365 /*****************************************************************************
1366 get_args: break individual arguments out of comma-separated list
1369 - all comments and labels have been removed
1370 - all strings of whitespace have been collapsed to a single blank.
1371 - all character constants ('x') have been replaced with decimal
1374 args[0] is untouched. args[1] points to first operand, etc. All args:
1375 - are NULL-terminated
1376 - contain no whitespace
1379 Number of operands (0,1,2, or 3) or -1 on error.
1381 *************************************************************************** */
1384 /* Pointer to comma-separated operands; MUCKED BY US */
1386 /* Output arg: pointers to operands placed in args[1-3]. MUST
1387 ACCOMMODATE 4 ENTRIES (args[0-3]). */
1390 register int n; /* Number of operands */
1393 /* Skip lead white space */
1407 /* Squeze blanks out by moving non-blanks toward start of string.
1408 * Isolate operands, whenever comma is found.
1415 && (! isalnum (p[1]) || ! isalnum (p[-1])))
1423 /* Start of operand */
1426 as_bad ("too many operands");
1429 *to++ = '\0'; /* Terminate argument */
1430 args[++n] = to; /* Start next argument */
1444 /*****************************************************************************
1445 get_cdisp: handle displacement for a COBR or CTRL instruction.
1447 Parse displacement for a COBR or CTRL instruction.
1449 If successful, output the instruction opcode and set up for it,
1450 depending on the arg 'var_frag', either:
1451 o an address fixup to be done when all symbol values are known, or
1452 o a varying length code fragment, with address fixup info. This
1453 will be done for cobr instructions that may have to be relaxed
1454 in to compare/branch instructions (8 bytes) if the final
1455 address displacement is greater than 13 bits.
1457 ****************************************************************************/
1460 get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
1461 /* displacement as specified in source instruction */
1463 /* "COBR" or "CTRL" (for use in error message) */
1465 /* Instruction needing the displacement */
1467 /* # bits of displacement (13 for COBR, 24 for CTRL) */
1469 /* 1 if varying length code fragment should be emitted;
1470 * 0 if an address fix should be emitted.
1473 /* 1 if callj relocation should be done; else 0 */
1476 expressionS e; /* Parsed expression */
1477 fixS *fixP; /* Structure describing needed address fix */
1478 char *outP; /* Where instruction binary is output to */
1482 parse_expr (dispP, &e);
1486 as_bad ("expression syntax error");
1489 if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
1490 || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
1494 outP = frag_more (8); /* Allocate worst-case storage */
1495 md_number_to_chars (outP, instr, 4);
1496 frag_variant (rs_machine_dependent, 4, 4, 1,
1497 adds (e), offs (e), outP);
1501 /* Set up a new fix structure, so address can be updated
1502 * when all symbol values are known.
1504 outP = emit (instr);
1505 fixP = fix_new (frag_now,
1506 outP - frag_now->fr_literal,
1513 fixP->fx_tcbit = callj;
1515 /* We want to modify a bit field when the address is
1516 * known. But we don't need all the garbage in the
1517 * bit_fix structure. So we're going to lie and store
1518 * the number of bits affected instead of a pointer.
1520 fixP->fx_bit_fixP = (bit_fixS *) numbits;
1524 as_bad ("attempt to branch into different segment");
1528 as_bad ("target of %s instruction must be a label", ifmtP);
1534 /*****************************************************************************
1535 get_ispec: parse a memory operand for an index specification
1537 Here, an "index specification" is taken to be anything surrounded
1538 by square brackets and NOT followed by anything else.
1540 If it's found, detach it from the input string, remove the surrounding
1541 square brackets, and return a pointer to it. Otherwise, return NULL.
1543 *************************************************************************** */
1547 /* Pointer to memory operand from source instruction, no white space. */
1550 /* Points to start of index specification. */
1552 /* Points to end of index specification. */
1555 /* Find opening square bracket, if any. */
1556 start = strchr (textP, '[');
1561 /* Eliminate '[', detach from rest of operand */
1564 end = strchr (start, ']');
1568 as_bad ("unmatched '['");
1573 /* Eliminate ']' and make sure it was the last thing
1577 if (*(end + 1) != '\0')
1579 as_bad ("garbage after index spec ignored");
1586 /*****************************************************************************
1589 Look up a (suspected) register name in the register table and return the
1590 associated register number (or -1 if not found).
1592 *************************************************************************** */
1595 get_regnum (regname)
1596 char *regname; /* Suspected register name */
1600 rP = (int *) hash_find (reg_hash, regname);
1601 return (rP == NULL) ? -1 : *rP;
1605 /*****************************************************************************
1606 i_scan: perform lexical scan of ascii assembler instruction.
1609 - input string is an i80960 instruction (not a pseudo-op)
1610 - all comments and labels have been removed
1611 - all strings of whitespace have been collapsed to a single blank.
1614 args[0] points to opcode, other entries point to operands. All strings:
1615 - are NULL-terminated
1616 - contain no whitespace
1617 - have character constants ('x') replaced with a decimal number
1620 Number of operands (0,1,2, or 3) or -1 on error.
1622 *************************************************************************** */
1625 /* Pointer to ascii instruction; MUCKED BY US. */
1627 /* Output arg: pointers to opcode and operands placed here. MUST
1628 ACCOMMODATE 4 ENTRIES. */
1632 /* Isolate opcode */
1636 } /* Skip lead space, if any */
1638 for (; *iP != ' '; iP++)
1642 /* There are no operands */
1645 /* We never moved: there was no opcode either! */
1646 as_bad ("missing opcode");
1652 *iP++ = '\0'; /* Terminate opcode */
1653 return (get_args (iP, args));
1657 /*****************************************************************************
1658 mem_fmt: generate a MEMA- or MEMB-format instruction
1660 *************************************************************************** */
1662 mem_fmt (args, oP, callx)
1663 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1664 struct i960_opcode *oP; /* Pointer to description of instruction */
1665 int callx; /* Is this a callx opcode */
1667 int i; /* Loop counter */
1668 struct regop regop; /* Description of register operand */
1669 char opdesc; /* Operand descriptor byte */
1670 memS instr; /* Description of binary to be output */
1671 char *outP; /* Where the binary was output to */
1672 expressionS expr; /* Parsed expression */
1673 /* ->description of deferred address fixup */
1677 /* COFF support isn't in place yet for callx relaxing. */
1681 memset (&instr, '\0', sizeof (memS));
1682 instr.opcode = oP->opcode;
1684 /* Process operands. */
1685 for (i = 1; i <= oP->num_ops; i++)
1687 opdesc = oP->operand[i - 1];
1691 parse_memop (&instr, args[i], oP->format);
1695 parse_regop (®op, args[i], opdesc);
1696 instr.opcode |= regop.n << 19;
1701 outP = emit (instr.opcode);
1703 if (instr.disp == 0)
1708 /* Parse and process the displacement */
1709 parse_expr (instr.e, &expr);
1713 as_bad ("expression syntax error");
1717 if (instr.disp == 32)
1719 (void) emit (offs (expr)); /* Output displacement */
1723 /* 12-bit displacement */
1724 if (offs (expr) & ~0xfff)
1726 /* Won't fit in 12 bits: convert already-output
1727 * instruction to MEMB format, output
1730 mema_to_memb (outP);
1731 (void) emit (offs (expr));
1735 /* WILL fit in 12 bits: OR into opcode and
1736 * overwrite the binary we already put out
1738 instr.opcode |= offs (expr);
1739 md_number_to_chars (outP, instr.opcode, 4);
1745 if (instr.disp == 12)
1747 /* Displacement is dependent on a symbol, whose value
1748 * may change at link time. We HAVE to reserve 32 bits.
1749 * Convert already-output opcode to MEMB format.
1751 mema_to_memb (outP);
1754 /* Output 0 displacement and set up address fixup for when
1755 * this symbol's value becomes known.
1757 outP = emit ((long) 0);
1758 fixP = fix_new_exp (frag_now,
1759 outP - frag_now->fr_literal,
1764 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1765 /* Steve's linker relaxing hack. Mark this 32-bit relocation as
1766 being in the instruction stream, specifically as part of a callx
1768 fixP->fx_bsr = callx;
1774 /*****************************************************************************
1775 mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1777 There are 2 possible MEMA formats:
1779 - displacement + abase
1781 They are distinguished by the setting of the MEMA_ABASE bit.
1783 *************************************************************************** */
1785 mema_to_memb (opcodeP)
1786 char *opcodeP; /* Where to find the opcode, in target byte order */
1788 long opcode; /* Opcode in host byte order */
1789 long mode; /* Mode bits for MEMB instruction */
1791 opcode = md_chars_to_number (opcodeP, 4);
1792 know (!(opcode & MEMB_BIT));
1794 mode = MEMB_BIT | D_BIT;
1795 if (opcode & MEMA_ABASE)
1800 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */
1801 opcode |= mode; /* Set MEMB mode bits */
1803 md_number_to_chars (opcodeP, opcode, 4);
1804 } /* mema_to_memb() */
1807 /*****************************************************************************
1808 parse_expr: parse an expression
1810 Use base assembler's expression parser to parse an expression.
1811 It, unfortunately, runs off a global which we have to save/restore
1812 in order to make it work for us.
1814 An empty expression string is treated as an absolute 0.
1816 Sets O_illegal regardless of expression evaluation if entire input
1817 string is not consumed in the evaluation -- tolerate no dangling junk!
1819 *************************************************************************** */
1821 parse_expr (textP, expP)
1822 char *textP; /* Text of expression to be parsed */
1823 expressionS *expP; /* Where to put the results of parsing */
1825 char *save_in; /* Save global here */
1832 /* Treat empty string as absolute 0 */
1833 expP->X_add_symbol = expP->X_op_symbol = NULL;
1834 expP->X_add_number = 0;
1835 expP->X_op = O_constant;
1839 save_in = input_line_pointer; /* Save global */
1840 input_line_pointer = textP; /* Make parser work for us */
1842 (void) expression (expP);
1843 if (input_line_pointer - textP != strlen (textP))
1845 /* Did not consume all of the input */
1846 expP->X_op = O_illegal;
1848 symP = expP->X_add_symbol;
1849 if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
1851 /* Register name in an expression */
1852 /* FIXME: this isn't much of a check any more. */
1853 expP->X_op = O_illegal;
1856 input_line_pointer = save_in; /* Restore global */
1861 /*****************************************************************************
1863 Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1866 Assumes the input consists of:
1867 arg[0] opcode mnemonic ('ldconst')
1868 arg[1] first operand (constant)
1869 arg[2] name of register to be loaded
1871 Replaces opcode and/or operands as appropriate.
1873 Returns the new number of arguments, or -1 on failure.
1875 *************************************************************************** */
1879 char *arg[]; /* See above */
1881 int n; /* Constant to be loaded */
1882 int shift; /* Shift count for "shlo" instruction */
1883 static char buf[5]; /* Literal for first operand */
1884 static char buf2[5]; /* Literal for second operand */
1885 expressionS e; /* Parsed expression */
1888 arg[3] = NULL; /* So we can tell at the end if it got used or not */
1890 parse_expr (arg[1], &e);
1894 /* We're dependent on one or more symbols -- use "lda" */
1899 /* Try the following mappings:
1900 * ldconst 0,<reg> ->mov 0,<reg>
1901 * ldconst 31,<reg> ->mov 31,<reg>
1902 * ldconst 32,<reg> ->addo 1,31,<reg>
1903 * ldconst 62,<reg> ->addo 31,31,<reg>
1904 * ldconst 64,<reg> ->shlo 8,3,<reg>
1905 * ldconst -1,<reg> ->subo 1,0,<reg>
1906 * ldconst -31,<reg>->subo 31,0,<reg>
1908 * anthing else becomes:
1912 if ((0 <= n) && (n <= 31))
1917 else if ((-31 <= n) && (n <= -1))
1921 sprintf (buf, "%d", -n);
1926 else if ((32 <= n) && (n <= 62))
1931 sprintf (buf, "%d", n - 31);
1935 else if ((shift = shift_ok (n)) != 0)
1939 sprintf (buf, "%d", shift);
1941 sprintf (buf2, "%d", n >> shift);
1952 as_bad ("invalid constant");
1956 return (arg[3] == 0) ? 2 : 3;
1959 /*****************************************************************************
1960 parse_memop: parse a memory operand
1962 This routine is based on the observation that the 4 mode bits of the
1963 MEMB format, taken individually, have fairly consistent meaning:
1965 M3 (bit 13): 1 if displacement is present (D_BIT)
1966 M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1967 M1 (bit 11): 1 if index is present (I_BIT)
1968 M0 (bit 10): 1 if abase is present (A_BIT)
1970 So we parse the memory operand and set bits in the mode as we find
1971 things. Then at the end, if we go to MEMB format, we need only set
1972 the MEMB bit (M2) and our mode is built for us.
1974 Unfortunately, I said "fairly consistent". The exceptions:
1977 0100 Would seem illegal, but means "abase-only".
1979 0101 Would seem to mean "abase-only" -- it means IP-relative.
1980 Must be converted to 0100.
1982 0110 Would seem to mean "index-only", but is reserved.
1983 We turn on the D bit and provide a 0 displacement.
1985 The other thing to observe is that we parse from the right, peeling
1986 things * off as we go: first any index spec, then any abase, then
1989 *************************************************************************** */
1992 parse_memop (memP, argP, optype)
1993 memS *memP; /* Where to put the results */
1994 char *argP; /* Text of the operand to be parsed */
1995 int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
1997 char *indexP; /* Pointer to index specification with "[]" removed */
1998 char *p; /* Temp char pointer */
1999 char iprel_flag; /* True if this is an IP-relative operand */
2000 int regnum; /* Register number */
2001 /* Scale factor: 1,2,4,8, or 16. Later converted to internal format
2002 (0,1,2,3,4 respectively). */
2004 int mode; /* MEMB mode bits */
2005 int *intP; /* Pointer to register number */
2007 /* The following table contains the default scale factors for each
2008 type of memory instruction. It is accessed using (optype-MEM1)
2009 as an index -- thus it assumes the 'optype' constants are
2010 assigned consecutive values, in the order they appear in this
2012 static const int def_scale[] =
2018 -1, /* MEM12 -- no valid default */
2023 iprel_flag = mode = 0;
2025 /* Any index present? */
2026 indexP = get_ispec (argP);
2029 p = strchr (indexP, '*');
2032 /* No explicit scale -- use default for this instruction
2033 type and assembler mode. */
2037 /* GNU960 compatibility */
2038 scale = def_scale[optype - MEM1];
2042 *p++ = '\0'; /* Eliminate '*' */
2044 /* Now indexP->a '\0'-terminated register name,
2045 * and p->a scale factor.
2048 if (!strcmp (p, "16"))
2052 else if (strchr ("1248", *p) && (p[1] == '\0'))
2062 regnum = get_regnum (indexP); /* Get index reg. # */
2063 if (!IS_RG_REG (regnum))
2065 as_bad ("invalid index register");
2069 /* Convert scale to its binary encoding */
2088 as_bad ("invalid scale factor");
2092 memP->opcode |= scale | regnum; /* Set index bits in opcode */
2093 mode |= I_BIT; /* Found a valid index spec */
2096 /* Any abase (Register Indirect) specification present? */
2097 if ((p = strrchr (argP, '(')) != NULL)
2099 /* "(" is there -- does it start a legal abase spec? If not, it
2100 could be part of a displacement expression. */
2101 intP = (int *) hash_find (areg_hash, p);
2104 /* Got an abase here */
2106 *p = '\0'; /* discard register spec */
2107 if (regnum == IPREL)
2109 /* We have to specialcase ip-rel mode */
2114 memP->opcode |= regnum << 14;
2120 /* Any expression present? */
2127 /* Special-case ip-relative addressing */
2136 memP->opcode |= 5 << 10; /* IP-relative mode */
2142 /* Handle all other modes */
2146 /* Go with MEMA instruction format for now (grow to MEMB later
2147 if 12 bits is not enough for the displacement). MEMA format
2148 has a single mode bit: set it to indicate that abase is
2150 memP->opcode |= MEMA_ABASE;
2155 /* Go with MEMA instruction format for now (grow to MEMB later
2156 if 12 bits is not enough for the displacement). */
2161 /* For some reason, the bit string for this mode is not
2162 consistent: it should be 0 (exclusive of the MEMB bit), so we
2163 set it "by hand" here. */
2164 memP->opcode |= MEMB_BIT;
2168 /* set MEMB bit in mode, and OR in mode bits */
2169 memP->opcode |= mode | MEMB_BIT;
2173 /* Treat missing displacement as displacement of 0. */
2175 /* Fall into next case. */
2176 case D_BIT | A_BIT | I_BIT:
2178 /* set MEMB bit in mode, and OR in mode bits */
2179 memP->opcode |= mode | MEMB_BIT;
2189 /*****************************************************************************
2190 parse_po: parse machine-dependent pseudo-op
2192 This is a top-level routine for machine-dependent pseudo-ops. It slurps
2193 up the rest of the input line, breaks out the individual arguments,
2194 and dispatches them to the correct handler.
2195 *************************************************************************** */
2199 int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
2201 /* Pointers operands, with no embedded whitespace.
2202 arg[0] unused, arg[1-3]->operands */
2204 int n_ops; /* Number of operands */
2205 char *p; /* Pointer to beginning of unparsed argument string */
2206 char eol; /* Character that indicated end of line */
2208 extern char is_end_of_line[];
2210 /* Advance input pointer to end of line. */
2211 p = input_line_pointer;
2212 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2214 input_line_pointer++;
2216 eol = *input_line_pointer; /* Save end-of-line char */
2217 *input_line_pointer = '\0'; /* Terminate argument list */
2219 /* Parse out operands */
2220 n_ops = get_args (p, args);
2226 /* Dispatch to correct handler */
2230 s_sysproc (n_ops, args);
2233 s_leafproc (n_ops, args);
2240 /* Restore eol, so line numbers get updated correctly. Base
2241 assembler assumes we leave input pointer pointing at char
2242 following the eol. */
2243 *input_line_pointer++ = eol;
2246 /*****************************************************************************
2247 parse_regop: parse a register operand.
2249 In case of illegal operand, issue a message and return some valid
2250 information so instruction processing can continue.
2251 *************************************************************************** */
2254 parse_regop (regopP, optext, opdesc)
2255 struct regop *regopP; /* Where to put description of register operand */
2256 char *optext; /* Text of operand */
2257 char opdesc; /* Descriptor byte: what's legal for this operand */
2259 int n; /* Register number */
2260 expressionS e; /* Parsed expression */
2262 /* See if operand is a register */
2263 n = get_regnum (optext);
2268 /* global or local register */
2269 if (!REG_ALIGN (opdesc, n))
2271 as_bad ("unaligned register");
2275 regopP->special = 0;
2278 else if (IS_FP_REG (n) && FP_OK (opdesc))
2280 /* Floating point register, and it's allowed */
2281 regopP->n = n - FP0;
2283 regopP->special = 0;
2286 else if (IS_SF_REG (n) && SFR_OK (opdesc))
2288 /* Special-function register, and it's allowed */
2289 regopP->n = n - SF0;
2291 regopP->special = 1;
2292 if (!targ_has_sfr (regopP->n))
2294 as_bad ("no such sfr in this architecture");
2299 else if (LIT_OK (opdesc))
2301 /* How about a literal? */
2303 regopP->special = 0;
2305 { /* floating point literal acceptable */
2306 /* Skip over 0f, 0d, or 0e prefix */
2307 if ((optext[0] == '0')
2308 && (optext[1] >= 'd')
2309 && (optext[1] <= 'f'))
2314 if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
2319 if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
2327 { /* fixed point literal acceptable */
2328 parse_expr (optext, &e);
2329 if (e.X_op != O_constant
2330 || (offs (e) < 0) || (offs (e) > 31))
2332 as_bad ("illegal literal");
2335 regopP->n = offs (e);
2340 /* Nothing worked */
2342 regopP->mode = 0; /* Register r0 is always a good one */
2344 regopP->special = 0;
2345 } /* parse_regop() */
2347 /*****************************************************************************
2348 reg_fmt: generate a REG-format instruction
2350 *************************************************************************** */
2353 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2354 struct i960_opcode *oP; /* Pointer to description of instruction */
2356 long instr; /* Binary to be output */
2357 struct regop regop; /* Description of register operand */
2358 int n_ops; /* Number of operands */
2362 n_ops = oP->num_ops;
2366 parse_regop (®op, args[1], oP->operand[0]);
2368 if ((n_ops == 1) && !(instr & M3))
2370 /* 1-operand instruction in which the dst field should
2371 * be used (instead of src1).
2376 regop.mode = regop.special;
2383 /* regop.n goes in bit 0, needs no shifting */
2385 regop.special <<= 5;
2387 instr |= regop.n | regop.mode | regop.special;
2392 parse_regop (®op, args[2], oP->operand[1]);
2394 if ((n_ops == 2) && !(instr & M3))
2396 /* 2-operand instruction in which the dst field should
2397 * be used instead of src2).
2402 regop.mode = regop.special;
2411 regop.special <<= 6;
2413 instr |= regop.n | regop.mode | regop.special;
2417 parse_regop (®op, args[3], oP->operand[2]);
2420 regop.mode = regop.special;
2422 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2428 /*****************************************************************************
2430 Replace cobr instruction in a code fragment with equivalent branch and
2431 compare instructions, so it can reach beyond a 13-bit displacement.
2432 Set up an address fix/relocation for the new branch instruction.
2434 *************************************************************************** */
2436 /* This "conditional jump" table maps cobr instructions into
2437 equivalent compare and branch opcodes. */
2446 { /* COBR OPCODE: */
2447 { CHKBIT, BNO }, /* 0x30 - bbc */
2448 { CMPO, BG }, /* 0x31 - cmpobg */
2449 { CMPO, BE }, /* 0x32 - cmpobe */
2450 { CMPO, BGE }, /* 0x33 - cmpobge */
2451 { CMPO, BL }, /* 0x34 - cmpobl */
2452 { CMPO, BNE }, /* 0x35 - cmpobne */
2453 { CMPO, BLE }, /* 0x36 - cmpoble */
2454 { CHKBIT, BO }, /* 0x37 - bbs */
2455 { CMPI, BNO }, /* 0x38 - cmpibno */
2456 { CMPI, BG }, /* 0x39 - cmpibg */
2457 { CMPI, BE }, /* 0x3a - cmpibe */
2458 { CMPI, BGE }, /* 0x3b - cmpibge */
2459 { CMPI, BL }, /* 0x3c - cmpibl */
2460 { CMPI, BNE }, /* 0x3d - cmpibne */
2461 { CMPI, BLE }, /* 0x3e - cmpible */
2462 { CMPI, BO }, /* 0x3f - cmpibo */
2468 register fragS *fragP; /* fragP->fr_opcode is assumed to point to
2469 * the cobr instruction, which comes at the
2470 * end of the code fragment.
2473 int opcode, src1, src2, m1, s2;
2474 /* Bit fields from cobr instruction */
2475 long bp_bits; /* Branch prediction bits from cobr instruction */
2476 long instr; /* A single i960 instruction */
2477 /* ->instruction to be replaced */
2479 fixS *fixP; /* Relocation that can be done at assembly time */
2481 /* PICK UP & PARSE COBR INSTRUCTION */
2482 iP = fragP->fr_opcode;
2483 instr = md_chars_to_number (iP, 4);
2484 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2485 src1 = (instr >> 19) & 0x1f;
2486 m1 = (instr >> 13) & 1;
2488 src2 = (instr >> 14) & 0x1f;
2489 bp_bits = instr & BP_MASK;
2491 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2492 instr = coj[opcode].compare
2493 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2494 md_number_to_chars (iP, instr, 4);
2496 /* OUTPUT BRANCH INSTRUCTION */
2497 md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
2499 /* SET UP ADDRESS FIXUP/RELOCATION */
2500 fixP = fix_new (fragP,
2501 iP + 4 - fragP->fr_literal,
2508 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */
2515 /*****************************************************************************
2516 reloc_callj: Relocate a 'callj' instruction
2518 This is a "non-(GNU)-standard" machine-dependent hook. The base
2519 assembler calls it when it decides it can relocate an address at
2520 assembly time instead of emitting a relocation directive.
2522 Check to see if the relocation involves a 'callj' instruction to a:
2523 sysproc: Replace the default 'call' instruction with a 'calls'
2524 leafproc: Replace the default 'call' instruction with a 'bal'.
2525 other proc: Do nothing.
2527 See b.out.h for details on the 'n_other' field in a symbol structure.
2530 Assumes the caller has already figured out, in the case of a leafproc,
2531 to use the 'bal' entry point, and has substituted that symbol into the
2532 passed fixup structure.
2534 *************************************************************************** */
2537 /* Relocation that can be done at assembly time */
2540 /* Points to the binary for the instruction being relocated. */
2543 if (!fixP->fx_tcbit)
2545 /* This wasn't a callj instruction in the first place */
2549 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2551 if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2553 /* Symbol is a .sysproc: replace 'call' with 'calls'. System
2554 procedure number is (other-1). */
2555 md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2557 /* Nothing else needs to be done for this instruction. Make
2558 sure 'md_number_to_field()' will perform a no-op. */
2559 fixP->fx_bit_fixP = (bit_fixS *) 1;
2562 else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2564 /* Should not happen: see block comment above */
2565 as_fatal ("Trying to 'bal' to %s", S_GET_NAME (fixP->fx_addsy));
2567 else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2569 /* Replace 'call' with 'bal'; both instructions have the same
2570 format, so calling code should complete relocation as if
2571 nothing happened here. */
2572 md_number_to_chars (where, BAL, 4);
2574 else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2576 as_bad ("Looks like a proc, but can't tell what kind.\n");
2577 } /* switch on proc type */
2579 /* else Symbol is neither a sysproc nor a leafproc */
2583 /*****************************************************************************
2584 s_leafproc: process .leafproc pseudo-op
2586 .leafproc takes two arguments, the second one is optional:
2587 arg[1]: name of 'call' entry point to leaf procedure
2588 arg[2]: name of 'bal' entry point to leaf procedure
2590 If the two arguments are identical, or if the second one is missing,
2591 the first argument is taken to be the 'bal' entry point.
2593 If there are 2 distinct arguments, we must make sure that the 'bal'
2594 entry point immediately follows the 'call' entry point in the linked
2597 *************************************************************************** */
2599 s_leafproc (n_ops, args)
2600 int n_ops; /* Number of operands */
2601 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2603 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */
2604 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */
2606 if ((n_ops != 1) && (n_ops != 2))
2608 as_bad ("should have 1 or 2 operands");
2610 } /* Check number of arguments */
2612 /* Find or create symbol for 'call' entry point. */
2613 callP = symbol_find_or_make (args[1]);
2615 if (TC_S_IS_CALLNAME (callP))
2617 as_warn ("Redefining leafproc %s", S_GET_NAME (callP));
2620 /* If that was the only argument, use it as the 'bal' entry point.
2621 * Otherwise, mark it as the 'call' entry point and find or create
2622 * another symbol for the 'bal' entry point.
2624 if ((n_ops == 1) || !strcmp (args[1], args[2]))
2626 TC_S_FORCE_TO_BALNAME (callP);
2631 TC_S_FORCE_TO_CALLNAME (callP);
2633 balP = symbol_find_or_make (args[2]);
2634 if (TC_S_IS_CALLNAME (balP))
2636 as_warn ("Redefining leafproc %s", S_GET_NAME (balP));
2638 TC_S_FORCE_TO_BALNAME (balP);
2640 tc_set_bal_of_call (callP, balP);
2641 } /* if only one arg, or the args are the same */
2646 s_sysproc: process .sysproc pseudo-op
2648 .sysproc takes two arguments:
2649 arg[1]: name of entry point to system procedure
2650 arg[2]: 'entry_num' (index) of system procedure in the range
2653 For [ab].out, we store the 'entrynum' in the 'n_other' field of
2654 the symbol. Since that entry is normally 0, we bias 'entrynum'
2655 by adding 1 to it. It must be unbiased before it is used. */
2657 s_sysproc (n_ops, args)
2658 int n_ops; /* Number of operands */
2659 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2666 as_bad ("should have two operands");
2668 } /* bad arg count */
2670 /* Parse "entry_num" argument and check it for validity. */
2671 parse_expr (args[2], &exp);
2672 if (exp.X_op != O_constant
2674 || (offs (exp) > 31))
2676 as_bad ("'entry_num' must be absolute number in [0,31]");
2680 /* Find/make symbol and stick entry number (biased by +1) into it */
2681 symP = symbol_find_or_make (args[1]);
2683 if (TC_S_IS_SYSPROC (symP))
2685 as_warn ("Redefining entrynum for sysproc %s", S_GET_NAME (symP));
2688 TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */
2689 TC_S_FORCE_TO_SYSPROC (symP);
2693 /*****************************************************************************
2695 Determine if a "shlo" instruction can be used to implement a "ldconst".
2696 This means that some number X < 32 can be shifted left to produce the
2697 constant of interest.
2699 Return the shift count, or 0 if we can't do it.
2700 Caller calculates X by shifting original constant right 'shift' places.
2702 *************************************************************************** */
2706 int n; /* The constant of interest */
2708 int shift; /* The shift count */
2712 /* Can't do it for negative numbers */
2716 /* Shift 'n' right until a 1 is about to be lost */
2717 for (shift = 0; (n & 1) == 0; shift++)
2730 /* syntax: issue syntax error */
2735 as_bad ("syntax error");
2741 Return TRUE iff the target architecture supports the specified
2742 special-function register (sfr). */
2747 int n; /* Number (0-31) of sfr */
2749 switch (architecture)
2757 return ((0 <= n) && (n <= 4));
2760 return ((0 <= n) && (n <= 2));
2767 Return TRUE iff the target architecture supports the indicated
2768 class of instructions. */
2771 targ_has_iclass (ic)
2772 /* Instruction class; one of:
2773 I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2
2777 iclasses_seen |= ic;
2778 switch (architecture)
2781 return ic & (I_BASE | I_KX);
2783 return ic & (I_BASE | I_KX | I_FP | I_DEC);
2785 return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2787 return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
2789 return ic & (I_BASE | I_CX2 | I_HX | I_HX2);
2791 return ic & (I_BASE | I_CX2 | I_HX2); /* XL */
2793 if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
2794 && (iclasses_seen & (I_CX | I_CX2)))
2796 as_warn ("architecture of opcode conflicts with that of earlier instruction(s)");
2797 iclasses_seen &= ~ic;
2803 /* Handle the MRI .endian pseudo-op. */
2812 name = input_line_pointer;
2813 c = get_symbol_end ();
2814 if (strcasecmp (name, "little") == 0)
2816 else if (strcasecmp (name, "big") == 0)
2817 as_bad ("big endian mode is not supported");
2819 as_warn ("ignoring unrecognized .endian type `%s'", name);
2821 *input_line_pointer = c;
2823 demand_empty_rest_of_line ();
2826 /* We have no need to default values of symbols. */
2830 md_undefined_symbol (name)
2836 /* Exactly what point is a PC-relative offset relative TO?
2837 On the i960, they're relative to the address of the instruction,
2838 which we have set up as the address of the fixup too. */
2840 md_pcrel_from (fixP)
2843 return fixP->fx_where + fixP->fx_frag->fr_address;
2847 md_apply_fix (fixP, val)
2851 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2853 if (!fixP->fx_bit_fixP)
2854 switch (fixP->fx_im_disp)
2857 /* For callx, we always want to write out zero, and emit a
2858 symbolic relocation. */
2862 fixP->fx_addnumber = val;
2863 md_number_to_imm (place, val, fixP->fx_size, fixP);
2866 md_number_to_disp (place,
2868 ? val + fixP->fx_pcrel_adjust
2872 case 2: /* fix requested for .long .word etc */
2873 md_number_to_chars (place, val, fixP->fx_size);
2876 as_fatal ("Internal error in md_apply_fix() in file \"%s\"",
2880 md_number_to_field (place, val, fixP->fx_bit_fixP);
2883 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2885 tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
2888 relax_addressT segment_address_in_file;
2890 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
2891 struct relocation_info ri;
2894 memset ((char *) &ri, '\0', sizeof (ri));
2895 symbolP = fixP->fx_addsy;
2896 know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2897 ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2898 /* These two 'cuz of NS32K */
2899 ri.r_callj = fixP->fx_tcbit;
2900 if (fixP->fx_bit_fixP)
2903 ri.r_length = nbytes_r_length[fixP->fx_size];
2904 ri.r_pcrel = fixP->fx_pcrel;
2905 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2907 if (fixP->fx_r_type != NO_RELOC)
2909 switch (fixP->fx_r_type)
2914 ri.r_length = fixP->fx_size - 1;
2928 else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
2931 ri.r_index = symbolP->sy_number;
2936 ri.r_index = S_GET_TYPE (symbolP);
2939 /* Output the relocation information in machine-dependent form. */
2940 md_ri_to_chars (where, &ri);
2943 #endif /* OBJ_AOUT or OBJ_BOUT */
2945 #if defined (OBJ_COFF) && defined (BFD)
2947 tc_coff_fix2rtype (fixP)
2953 if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
2956 if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
2964 tc_coff_sizemachdep (frag)
2968 return frag->fr_next->fr_address - frag->fr_address;
2974 /* Align an address by rounding it up to the specified boundary. */
2976 md_section_align (seg, addr)
2978 valueT addr; /* Address to be rounded up */
2980 return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
2981 } /* md_section_align() */
2983 extern int coff_flags;
2987 tc_headers_hook (headers)
2988 object_headers *headers;
2990 switch (architecture)
2993 coff_flags |= F_I960KA;
2997 coff_flags |= F_I960KB;
3001 coff_flags |= F_I960MC;
3005 coff_flags |= F_I960CA;
3009 coff_flags |= F_I960HX;
3013 coff_flags |= F_I960XL;
3017 if (iclasses_seen == I_BASE)
3018 coff_flags |= F_I960CORE;
3019 else if (iclasses_seen & I_CX)
3020 coff_flags |= F_I960CA;
3021 else if (iclasses_seen & (I_HX | I_HX2))
3022 coff_flags |= F_I960HX;
3023 else if (iclasses_seen & I_CX2)
3024 coff_flags |= F_I960CA;
3025 else if (iclasses_seen & I_MIL)
3026 coff_flags |= F_I960MC;
3027 else if (iclasses_seen & (I_DEC | I_FP))
3028 coff_flags |= F_I960KB;
3030 coff_flags |= F_I960KA;
3034 if (flag_readonly_data_in_text)
3036 headers->filehdr.f_magic = I960RWMAGIC;
3037 headers->aouthdr.magic = OMAGIC;
3041 headers->filehdr.f_magic = I960ROMAGIC;
3042 headers->aouthdr.magic = NMAGIC;
3043 } /* set magic numbers */
3046 #endif /* OBJ_COFF */
3048 /* Things going on here:
3050 For bout, We need to assure a couple of simplifying
3051 assumptions about leafprocs for the linker: the leafproc
3052 entry symbols will be defined in the same assembly in
3053 which they're declared with the '.leafproc' directive;
3054 and if a leafproc has both 'call' and 'bal' entry points
3055 they are both global or both local.
3057 For coff, the call symbol has a second aux entry that
3058 contains the bal entry point. The bal symbol becomes a
3061 For coff representation, the call symbol has a second aux entry that
3062 contains the bal entry point. The bal symbol becomes a label. */
3065 tc_crawl_symbol_chain (headers)
3066 object_headers *headers;
3070 for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
3073 if (TC_S_IS_SYSPROC (symbolP))
3075 /* second aux entry already contains the sysproc number */
3076 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3077 S_SET_STORAGE_CLASS (symbolP, C_SCALL);
3078 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3080 } /* rewrite sysproc */
3081 #endif /* OBJ_COFF */
3083 if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
3086 } /* Not a leafproc symbol */
3088 if (!S_IS_DEFINED (symbolP))
3090 as_bad ("leafproc symbol '%s' undefined", S_GET_NAME (symbolP));
3091 } /* undefined leaf */
3093 if (TC_S_IS_CALLNAME (symbolP))
3095 symbolS *balP = tc_get_bal_of_call (symbolP);
3096 if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
3098 S_SET_EXTERNAL (symbolP);
3099 S_SET_EXTERNAL (balP);
3100 as_warn ("Warning: making leafproc entries %s and %s both global\n",
3101 S_GET_NAME (symbolP), S_GET_NAME (balP));
3102 } /* externality mismatch */
3104 } /* walk the symbol chain */
3107 /* For aout or bout, the bal immediately follows the call.
3109 For coff, we cheat and store a pointer to the bal symbol in the
3110 second aux entry of the call. */
3121 tc_set_bal_of_call (callP, balP)
3125 know (TC_S_IS_CALLNAME (callP));
3126 know (TC_S_IS_BALNAME (balP));
3130 callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP;
3131 S_SET_NUMBER_AUXILIARY (callP, 2);
3133 #else /* ! OBJ_COFF */
3136 /* If the 'bal' entry doesn't immediately follow the 'call'
3137 * symbol, unlink it from the symbol list and re-insert it.
3139 if (symbol_next (callP) != balP)
3141 symbol_remove (balP, &symbol_rootP, &symbol_lastP);
3142 symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
3143 } /* if not in order */
3145 #else /* ! OBJ_ABOUT */
3146 (as yet unwritten.);
3147 #endif /* ! OBJ_ABOUT */
3148 #endif /* ! OBJ_COFF */
3152 _tc_get_bal_of_call (callP)
3157 know (TC_S_IS_CALLNAME (callP));
3160 retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry);
3163 retval = symbol_next (callP);
3165 (as yet unwritten.);
3166 #endif /* ! OBJ_ABOUT */
3167 #endif /* ! OBJ_COFF */
3169 know (TC_S_IS_BALNAME (retval));
3170 return ((char *) retval);
3171 } /* _tc_get_bal_of_call() */
3174 tc_coff_symbol_emit_hook (symbolP)
3177 if (TC_S_IS_CALLNAME (symbolP))
3180 symbolS *balP = tc_get_bal_of_call (symbolP);
3183 /* second aux entry contains the bal entry point */
3184 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3186 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
3187 S_SET_STORAGE_CLASS (symbolP, (!SF_GET_LOCAL (symbolP) ? C_LEAFEXT : C_LEAFSTAT));
3188 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3189 /* fix up the bal symbol */
3190 S_SET_STORAGE_CLASS (balP, C_LABEL);
3191 #endif /* OBJ_COFF */
3192 } /* only on calls */
3196 i960_handle_align (fragp)
3204 as_bad ("option --link-relax is only supported in b.out format");
3210 /* The text section "ends" with another alignment reloc, to which we
3211 aren't adding padding. */
3212 if (fragp->fr_next == text_last_frag
3213 || fragp->fr_next == data_last_frag)
3216 /* alignment directive */
3217 fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
3218 (int) fragp->fr_type);
3219 #endif /* OBJ_BOUT */
3223 i960_validate_fix (fixP, this_segment_type, add_symbolPP)
3225 segT this_segment_type;
3226 symbolS **add_symbolPP;
3228 #define add_symbolP (*add_symbolPP)
3229 if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP))
3231 /* Relocation should be done via the associated 'bal'
3232 entry point symbol. */
3234 if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP)))
3236 as_bad ("No 'bal' entry point for leafproc %s",
3237 S_GET_NAME (add_symbolP));
3240 fixP->fx_addsy = add_symbolP = tc_get_bal_of_call (add_symbolP);
3243 /* Still have to work out other conditions for these tests. */
3247 as_bad ("callj to difference of two symbols");
3251 if ((int) fixP->fx_bit_fixP == 13)
3253 /* This is a COBR instruction. They have only a 13-bit
3254 displacement and are only to be used for local branches:
3255 flag as error, don't generate relocation. */
3256 as_bad ("can't use COBR format with external label");
3257 fixP->fx_addsy = NULL; /* No relocations please. */
3266 /* end of tc-i960.c */