1 /* tc-i960.c - All the i80960-specific stuff
2 Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
4 This file is part of GAS.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20 /* See comment on md_parse_option for 80960-specific invocation options. */
22 /******************************************************************************
24 * Header, symbol, and relocation info will be used on the host machine
25 * only -- only executable code is actually downloaded to the i80960.
26 * Therefore, leave all such information in host byte order.
28 * (That's a slight lie -- we DO download some header information, but
29 * the downloader converts the file format and corrects the byte-ordering
30 * of the relevant fields while doing so.)
32 * ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER
33 * FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO
34 * USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <==
36 ***************************************************************************** */
38 /* There are 4 different lengths of (potentially) symbol-based displacements
39 * in the 80960 instruction set, each of which could require address fix-ups
40 * and (in the case of external symbols) emission of relocation directives:
43 * This is a standard length for the base assembler and requires no
47 * This is a non-standard length, but the base assembler has a hook for
48 * bit field address fixups: the fixS structure can point to a descriptor
49 * of the field, in which case our md_number_to_field() routine gets called
52 * I made the hook a little cleaner by having fix_new() (in the base
53 * assembler) return a pointer to the fixS in question. And I made it a
54 * little simpler by storing the field size (in this case 13) instead of
55 * of a pointer to another structure: 80960 displacements are ALWAYS
56 * stored in the low-order bits of a 4-byte word.
58 * Since the target of a COBR cannot be external, no relocation directives
59 * for this size displacement have to be generated. But the base assembler
60 * had to be modified to issue error messages if the symbol did turn out
64 * Fixups are handled as for the 13-bit case (except that 24 is stored
67 * The relocation directive generated is the same as that for the 32-bit
68 * displacement, except that it's PC-relative (the 32-bit displacement
69 * never is). The i80960 version of the linker needs a mod to
70 * distinguish and handle the 24-bit case.
73 * MEMA formats are always promoted to MEMB (32-bit) if the displacement
74 * is based on a symbol, because it could be relocated at link time.
75 * The only time we use the 12-bit format is if an absolute value of
76 * less than 4096 is specified, in which case we need neither a fixup nor
77 * a relocation directive.
87 #include "opcode/i960.h"
89 extern char *strchr ();
91 extern char *input_line_pointer;
92 extern struct hash_control *po_hash;
93 extern char *next_object_file_charP;
95 #if !defined (BFD_ASSEMBLER) && !defined (BFD)
97 const int md_reloc_size = sizeof (struct reloc);
99 const int md_reloc_size = sizeof (struct relocation_info);
100 #endif /* OBJ_COFF */
103 /***************************
104 * Local i80960 routines *
105 ************************** */
107 static void brcnt_emit (); /* Emit branch-prediction instrumentation code */
108 static char *brlab_next (); /* Return next branch local label */
109 void brtab_emit (); /* Emit br-predict instrumentation table */
110 static void cobr_fmt (); /* Generate COBR instruction */
111 static void ctrl_fmt (); /* Generate CTRL instruction */
112 static char *emit (); /* Emit (internally) binary */
113 static int get_args (); /* Break arguments out of comma-separated list */
114 static void get_cdisp (); /* Handle COBR or CTRL displacement */
115 static char *get_ispec (); /* Find index specification string */
116 static int get_regnum (); /* Translate text to register number */
117 static int i_scan (); /* Lexical scan of instruction source */
118 static void mem_fmt (); /* Generate MEMA or MEMB instruction */
119 static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */
120 static void parse_expr (); /* Parse an expression */
121 static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */
122 static void parse_memop (); /* Parse a memory operand */
123 static void parse_po (); /* Parse machine-dependent pseudo-op */
124 static void parse_regop (); /* Parse a register operand */
125 static void reg_fmt (); /* Generate a REG format instruction */
126 void reloc_callj (); /* Relocate a 'callj' instruction */
127 static void relax_cobr (); /* "De-optimize" cobr into compare/branch */
128 static void s_leafproc (); /* Process '.leafproc' pseudo-op */
129 static void s_sysproc (); /* Process '.sysproc' pseudo-op */
130 static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */
131 static void syntax (); /* Give syntax error */
132 static int targ_has_sfr (); /* Target chip supports spec-func register? */
133 static int targ_has_iclass (); /* Target chip supports instruction set? */
134 /* static void unlink_sym(); *//* Remove a symbol from the symbol list */
136 /* See md_parse_option() for meanings of these options */
137 static char norelax; /* True if -norelax switch seen */
138 static char instrument_branches;/* True if -b switch seen */
140 /* Characters that always start a comment.
141 * If the pre-processor is disabled, these aren't very useful.
143 const char comment_chars[] = "#";
145 /* Characters that only start a comment at the beginning of
146 * a line. If the line seems to have the form '# 123 filename'
147 * .line and .file directives will appear in the pre-processed output.
149 * Note that input_file.c hand checks for '#' at the beginning of the
150 * first line of the input file. This is because the compiler outputs
151 * #NO_APP at the beginning of its output.
154 /* Also note that comments started like this one will always work. */
156 const char line_comment_chars[1];
158 const char line_separator_chars[1];
160 /* Chars that can be used to separate mant from exp in floating point nums */
161 const char EXP_CHARS[] = "eE";
163 /* Chars that mean this number is a floating point constant,
164 * as in 0f12.456 or 0d1.2345e12
166 const char FLT_CHARS[] = "fFdDtT";
169 /* Table used by base assembler to relax addresses based on varying length
170 * instructions. The fields are:
171 * 1) most positive reach of this state,
172 * 2) most negative reach of this state,
173 * 3) how many bytes this mode will add to the size of the current frag
174 * 4) which index into the table to try if we can't fit into this one.
176 * For i80960, the only application is the (de-)optimization of cobr
177 * instructions into separate compare and branch instructions when a 13-bit
178 * displacement won't hack it.
183 {0, 0, 0, 0}, /* State 0 => no more relaxation possible */
184 {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */
185 {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */
189 /* These are the machine dependent pseudo-ops.
191 * This table describes all the machine specific pseudo-ops the assembler
192 * has to support. The fields are:
193 * pseudo-op name without dot
194 * function to call to execute this pseudo-op
195 * integer arg to pass to the function
200 const pseudo_typeS md_pseudo_table[] =
203 {"extended", float_cons, 't'},
204 {"leafproc", parse_po, S_LEAFPROC},
205 {"sysproc", parse_po, S_SYSPROC},
213 /* Macros to extract info from an 'expressionS' structure 'e' */
214 #define adds(e) e.X_add_symbol
215 #define offs(e) e.X_add_number
218 /* Branch-prediction bits for CTRL/COBR format opcodes */
219 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
220 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
221 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
224 /* Some instruction opcodes that we need explicitly */
225 #define BE 0x12000000
226 #define BG 0x11000000
227 #define BGE 0x13000000
228 #define BL 0x14000000
229 #define BLE 0x16000000
230 #define BNE 0x15000000
231 #define BNO 0x10000000
232 #define BO 0x17000000
233 #define CHKBIT 0x5a002700
234 #define CMPI 0x5a002080
235 #define CMPO 0x5a002000
238 #define BAL 0x0b000000
239 #define CALL 0x09000000
240 #define CALLS 0x66003800
241 #define RET 0x0a000000
244 /* These masks are used to build up a set of MEMB mode bits. */
247 #define MEMB_BIT 0x1000
251 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
253 #define MEMA_ABASE 0x2000
255 /* Info from which a MEMA or MEMB format instruction can be generated */
258 /* (First) 32 bits of instruction */
260 /* 0-(none), 12- or, 32-bit displacement needed */
262 /* The expression in the source instruction from which the
263 displacement should be determined. */
270 /* The two pieces of info we need to generate a register operand */
273 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
274 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
275 int n; /* Register number or literal value */
279 /* Number and assembler mnemonic for all registers that can appear in operands */
321 /* Numbers for special-function registers are for assembler internal
322 use only: they are scaled back to range [0-31] for binary output. */
358 /* Numbers for floating point registers are for assembler internal use
359 * only: they are scaled back to [0-3] for binary output.
368 { NULL, 0 }, /* END OF LIST */
371 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
372 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
373 #define IS_FP_REG(n) ((n) >= FP0)
375 /* Number and assembler mnemonic for all registers that can appear as 'abase'
376 * (indirect addressing) registers.
420 /* For assembler internal use only: this number never appears in binary
424 { NULL, 0 }, /* END OF LIST */
429 static struct hash_control *op_hash; /* Opcode mnemonics */
430 static struct hash_control *reg_hash; /* Register name hash table */
431 static struct hash_control *areg_hash; /* Abase register hash table */
434 /* Architecture for which we are assembling */
435 #define ARCH_ANY 0 /* Default: no architecture checking done */
440 int architecture = ARCH_ANY; /* Architecture requested on invocation line */
441 int iclasses_seen; /* OR of instruction classes (I_* constants)
442 * for which we've actually assembled
447 /* BRANCH-PREDICTION INSTRUMENTATION
449 * The following supports generation of branch-prediction instrumentation
450 * (turned on by -b switch). The instrumentation collects counts
451 * of branches taken/not-taken for later input to a utility that will
452 * set the branch prediction bits of the instructions in accordance with
453 * the behavior observed. (Note that the KX series does not have
456 * The instrumentation consists of:
458 * (1) before and after each conditional branch, a call to an external
459 * routine that increments and steps over an inline counter. The
460 * counter itself, initialized to 0, immediately follows the call
461 * instruction. For each branch, the counter following the branch
462 * is the number of times the branch was not taken, and the difference
463 * between the counters is the number of times it was taken. An
464 * example of an instrumented conditional branch:
468 * LBRANCH23: be label
472 * (2) a table of pointers to the instrumented branches, so that an
473 * external postprocessing routine can locate all of the counters.
474 * the table begins with a 2-word header: a pointer to the next in
475 * a linked list of such tables (initialized to 0); and a count
476 * of the number of entries in the table (exclusive of the header.
478 * Note that input source code is expected to already contain calls
479 * an external routine that will link the branch local table into a
480 * list of such tables.
483 static int br_cnt; /* Number of branches instrumented so far.
484 * Also used to generate unique local labels
485 * for each instrumented branch
488 #define BR_LABEL_BASE "LBRANCH"
489 /* Basename of local labels on instrumented
490 * branches, to avoid conflict with compiler-
491 * generated local labels.
494 #define BR_CNT_FUNC "__inc_branch"
495 /* Name of the external routine that will
496 * increment (and step over) an inline counter.
499 #define BR_TAB_NAME "__BRANCH_TABLE__"
500 /* Name of the table of pointers to branches.
501 * A local (i.e., non-external) symbol.
504 /*****************************************************************************
505 * md_begin: One-time initialization.
507 * Set up hash tables.
509 **************************************************************************** */
513 int i; /* Loop counter */
514 const struct i960_opcode *oP; /* Pointer into opcode table */
515 const char *retval; /* Value returned by hash functions */
517 op_hash = hash_new ();
518 reg_hash = hash_new ();
519 areg_hash = hash_new ();
521 /* For some reason, the base assembler uses an empty string for "no
522 error message", instead of a NULL pointer. */
525 for (oP = i960_opcodes; oP->name && !retval; oP++)
526 retval = hash_insert (op_hash, oP->name, (PTR) oP);
528 for (i = 0; regnames[i].reg_name && !retval; i++)
529 retval = hash_insert (reg_hash, regnames[i].reg_name,
530 ®names[i].reg_num);
532 for (i = 0; aregs[i].areg_name && !retval; i++)
533 retval = hash_insert (areg_hash, aregs[i].areg_name,
537 as_fatal ("Hashing returned \"%s\".", retval);
540 /*****************************************************************************
541 * md_assemble: Assemble an instruction
543 * Assumptions about the passed-in text:
544 * - all comments, labels removed
545 * - text is an instruction
546 * - all white space compressed to single blanks
547 * - all character constants have been replaced with decimal
549 **************************************************************************** */
552 char *textP; /* Source text of instruction */
554 /* Parsed instruction text, containing NO whitespace:
555 * arg[0]->opcode mnemonic
556 * arg[1-3]->operands, with char constants
557 * replaced by decimal numbers
561 int n_ops; /* Number of instruction operands */
562 /* Pointer to instruction description */
563 struct i960_opcode *oP;
564 /* TRUE iff opcode mnemonic included branch-prediction
565 * suffix (".f" or ".t")
568 /* Setting of branch-prediction bit(s) to be OR'd
569 * into instruction opcode of CTRL/COBR format
574 int n; /* Offset of last character in opcode mnemonic */
576 static const char bp_error_msg[] = "branch prediction invalid on this opcode";
579 /* Parse instruction into opcode and operands */
580 memset (args, '\0', sizeof (args));
581 n_ops = i_scan (textP, args);
584 return; /* Error message already issued */
587 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
588 if (!strcmp (args[0], "ldconst"))
590 n_ops = parse_ldconst (args);
599 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
600 n = strlen (args[0]) - 1;
603 if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
605 /* We could check here to see if the target architecture
606 * supports branch prediction, but why bother? The bit
607 * will just be ignored by processors that don't use it.
610 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
611 args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
614 /* Look up opcode mnemonic in table and check number of operands.
615 * Check that opcode is legal for the target architecture.
616 * If all looks good, assemble instruction.
618 oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
619 if (!oP || !targ_has_iclass (oP->iclass))
621 as_bad ("invalid opcode, \"%s\".", args[0]);
624 else if (n_ops != oP->num_ops)
626 as_bad ("improper number of operands. expecting %d, got %d",
635 ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
636 if (oP->format == FBRA)
638 /* Now generate a 'bno' to same arg */
639 ctrl_fmt (args[1], BNO | bp_bits, 1);
644 cobr_fmt (args, oP->opcode | bp_bits, oP);
649 as_warn (bp_error_msg);
654 if (args[0][0] == 'c' && args[0][1] == 'a')
658 as_warn (bp_error_msg);
660 mem_fmt (args, oP, 1);
670 as_warn (bp_error_msg);
672 mem_fmt (args, oP, 0);
677 as_warn (bp_error_msg);
679 /* Output opcode & set up "fixup" (relocation); flag
680 relocation as 'callj' type. */
681 know (oP->num_ops == 1);
682 get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
685 BAD_CASE (oP->format);
689 } /* md_assemble() */
691 /*****************************************************************************
692 * md_number_to_chars: convert a number to target byte order
694 **************************************************************************** */
696 md_number_to_chars (buf, value, n)
701 number_to_chars_littleendian (buf, value, n);
704 /*****************************************************************************
705 * md_chars_to_number: convert from target byte order to host byte order.
707 **************************************************************************** */
709 md_chars_to_number (val, n)
710 unsigned char *val; /* Value in target byte order */
711 int n; /* Number of bytes in the input */
715 for (retval = 0; n--;)
724 #define MAX_LITTLENUMS 6
725 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
727 /*****************************************************************************
728 * md_atof: convert ascii to floating point
730 * Turn a string at input_line_pointer into a floating point constant of type
731 * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
732 * emitted is returned at 'sizeP'. An error message is returned, or a pointer
733 * to an empty message if OK.
735 * Note we call the i386 floating point routine, rather than complicating
736 * things with more files or symbolic links.
738 **************************************************************************** */
740 md_atof (type, litP, sizeP)
745 LITTLENUM_TYPE words[MAX_LITTLENUMS];
746 LITTLENUM_TYPE *wordP;
766 type = 'x'; /* That's what atof_ieee() understands */
771 return "Bad call to md_atof()";
774 t = atof_ieee (input_line_pointer, type, words);
777 input_line_pointer = t;
780 *sizeP = prec * LNUM_SIZE;
782 /* Output the LITTLENUMs in REVERSE order in accord with i80960
783 word-order. (Dunno why atof_ieee doesn't do it in the right
784 order in the first place -- probably because it's a hack of
787 for (wordP = words + prec - 1; prec--;)
789 md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
790 litP += sizeof (LITTLENUM_TYPE);
797 /*****************************************************************************
800 **************************************************************************** */
802 md_number_to_imm (buf, val, n)
807 md_number_to_chars (buf, val, n);
811 /*****************************************************************************
814 **************************************************************************** */
816 md_number_to_disp (buf, val, n)
821 md_number_to_chars (buf, val, n);
824 /*****************************************************************************
825 * md_number_to_field:
827 * Stick a value (an address fixup) into a bit field of
828 * previously-generated instruction.
830 **************************************************************************** */
832 md_number_to_field (instrP, val, bfixP)
833 char *instrP; /* Pointer to instruction to be fixed */
834 long val; /* Address fixup value */
835 bit_fixS *bfixP; /* Description of bit field to be fixed up */
837 int numbits; /* Length of bit field to be fixed */
838 long instr; /* 32-bit instruction to be fixed-up */
839 long sign; /* 0 or -1, according to sign bit of 'val' */
841 /* Convert instruction back to host byte order
843 instr = md_chars_to_number (instrP, 4);
845 /* Surprise! -- we stored the number of bits
846 * to be modified rather than a pointer to a structure.
848 numbits = (int) bfixP;
851 /* This is a no-op, stuck here by reloc_callj() */
855 know ((numbits == 13) || (numbits == 24));
857 /* Propagate sign bit of 'val' for the given number of bits.
858 * Result should be all 0 or all 1
860 sign = val >> ((int) numbits - 1);
861 if (((val < 0) && (sign != -1))
862 || ((val > 0) && (sign != 0)))
864 as_bad ("Fixup of %ld too large for field width of %d",
869 /* Put bit field into instruction and write back in target
872 val &= ~(-1 << (int) numbits); /* Clear unused sign bits */
874 md_number_to_chars (instrP, instr, 4);
876 } /* md_number_to_field() */
879 /*****************************************************************************
881 * Invocation line includes a switch not recognized by the base assembler.
882 * See if it's a processor-specific option. For the 960, these are:
885 * Conditional branch instructions that require displacements
886 * greater than 13 bits (or that have external targets) should
887 * generate errors. The default is to replace each such
888 * instruction with the corresponding compare (or chkbit) and
889 * branch instructions. Note that the Intel "j" cobr directives
890 * are ALWAYS "de-optimized" in this way when necessary,
891 * regardless of the setting of this option.
894 * Add code to collect information about branches taken, for
895 * later optimization of branch prediction bits by a separate
896 * tool. COBR and CNTL format instructions have branch
897 * prediction bits (in the CX architecture); if "BR" represents
898 * an instruction in one of these classes, the following rep-
899 * resents the code generated by the assembler:
901 * call <increment routine>
902 * .word 0 # pre-counter
904 * call <increment routine>
905 * .word 0 # post-counter
907 * A table of all such "Labels" is also generated.
910 * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
911 * Select the 80960 architecture. Instructions or features not
912 * supported by the selected architecture cause fatal errors.
913 * The default is to generate code for any instruction or feature
914 * that is supported by SOME version of the 960 (even if this
915 * means mixing architectures!).
917 *****************************************************************************/
919 CONST char *md_shortopts = "A:b";
920 struct option md_longopts[] = {
921 #define OPTION_LINKRELAX (OPTION_MD_BASE)
922 {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
923 #define OPTION_NORELAX (OPTION_MD_BASE + 1)
924 {"norelax", no_argument, NULL, OPTION_NORELAX},
925 {NULL, no_argument, NULL, 0}
927 size_t md_longopts_size = sizeof(md_longopts);
930 md_parse_option (c, arg)
939 static struct tabentry arch_tab[] =
943 { "SA", ARCH_KA }, /* Synonym for KA */
944 { "SB", ARCH_KB }, /* Synonym for KB */
945 { "KC", ARCH_MC }, /* Synonym for MC */
953 case OPTION_LINKRELAX:
963 instrument_branches = 1;
971 for (tp = arch_tab; tp->flag != NULL; tp++)
973 if (!strcmp (p, tp->flag))
979 if (tp->flag == NULL)
981 as_bad ("invalid architecture %s", p);
986 architecture = tp->arch;
999 md_show_usage (stream)
1004 -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC\n\
1005 specify variant of 960 architecture\n\
1006 -b add code to collect statistics about branches taken\n\
1007 -linkrelax make relocatable instructions undefined (?)\n\
1008 -norelax don't alter compare-and-branch instructions for\n\
1009 long displacements\n");
1013 /*****************************************************************************
1015 * Called by base assembler after address relaxation is finished: modify
1016 * variable fragments according to how much relaxation was done.
1018 * If the fragment substate is still 1, a 13-bit displacement was enough
1019 * to reach the symbol in question. Set up an address fixup, but otherwise
1020 * leave the cobr instruction alone.
1022 * If the fragment substate is 2, a 13-bit displacement was not enough.
1023 * Replace the cobr with a two instructions (a compare and a branch).
1025 **************************************************************************** */
1027 md_convert_frag (headers, fragP)
1028 object_headers *headers;
1031 fixS *fixP; /* Structure describing needed address fix */
1033 switch (fragP->fr_subtype)
1036 /* LEAVE SINGLE COBR INSTRUCTION */
1037 fixP = fix_new (fragP,
1038 fragP->fr_opcode - fragP->fr_literal,
1045 fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */
1048 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
1052 BAD_CASE (fragP->fr_subtype);
1057 /*****************************************************************************
1058 * md_estimate_size_before_relax: How much does it look like *fragP will grow?
1060 * Called by base assembler just before address relaxation.
1061 * Return the amount by which the fragment will grow.
1063 * Any symbol that is now undefined will not become defined; cobr's
1064 * based on undefined symbols will have to be replaced with a compare
1065 * instruction and a branch instruction, and the code fragment will grow
1068 **************************************************************************** */
1070 md_estimate_size_before_relax (fragP, segment_type)
1071 register fragS *fragP;
1072 register segT segment_type;
1074 /* If symbol is undefined in this segment, go to "relaxed" state
1075 * (compare and branch instructions instead of cobr) right now.
1077 if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
1083 } /* md_estimate_size_before_relax() */
1086 /*****************************************************************************
1088 * This routine exists in order to overcome machine byte-order problems
1089 * when dealing with bit-field entries in the relocation_info struct.
1091 * But relocation info will be used on the host machine only (only
1092 * executable code is actually downloaded to the i80960). Therefore,
1093 * we leave it in host byte order.
1095 * The above comment is no longer true. This routine now really
1096 * does do the reordering (Ian Taylor 28 Aug 92).
1098 **************************************************************************** */
1100 md_ri_to_chars (where, ri)
1102 struct relocation_info *ri;
1104 md_number_to_chars (where, ri->r_address,
1105 sizeof (ri->r_address));
1106 where[4] = ri->r_index & 0x0ff;
1107 where[5] = (ri->r_index >> 8) & 0x0ff;
1108 where[6] = (ri->r_index >> 16) & 0x0ff;
1109 where[7] = ((ri->r_pcrel << 0)
1110 | (ri->r_length << 1)
1111 | (ri->r_extern << 3)
1114 | (ri->r_callj << 6));
1117 #ifndef WORKING_DOT_WORD
1119 int md_short_jump_size = 0;
1120 int md_long_jump_size = 0;
1123 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
1130 as_fatal ("failed sanity check.");
1134 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
1136 addressT from_addr, to_addr;
1140 as_fatal ("failed sanity check.");
1145 /*************************************************************
1147 * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER *
1149 ************************************************************ */
1153 /*****************************************************************************
1154 * brcnt_emit: Emit code to increment inline branch counter.
1156 * See the comments above the declaration of 'br_cnt' for details on
1157 * branch-prediction instrumentation.
1158 **************************************************************************** */
1162 ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */
1163 emit (0); /* Emit inline counter to be incremented */
1166 /*****************************************************************************
1167 * brlab_next: generate the next branch local label
1169 * See the comments above the declaration of 'br_cnt' for details on
1170 * branch-prediction instrumentation.
1171 **************************************************************************** */
1175 static char buf[20];
1177 sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1181 /*****************************************************************************
1182 * brtab_emit: generate the fetch-prediction branch table.
1184 * See the comments above the declaration of 'br_cnt' for details on
1185 * branch-prediction instrumentation.
1187 * The code emitted here would be functionally equivalent to the following
1188 * example assembler source.
1193 * .word 0 # link to next table
1194 * .word 3 # length of table
1195 * .word LBRANCH0 # 1st entry in table proper
1198 ***************************************************************************** */
1204 char *p; /* Where the binary was output to */
1205 fixS *fixP; /*->description of deferred address fixup */
1207 if (!instrument_branches)
1212 subseg_set (SEG_DATA, 0); /* .data */
1213 frag_align (2, 0); /* .align 2 */
1214 record_alignment (now_seg, 2);
1215 colon (BR_TAB_NAME); /* BR_TAB_NAME: */
1216 emit (0); /* .word 0 #link to next table */
1217 emit (br_cnt); /* .word n #length of table */
1219 for (i = 0; i < br_cnt; i++)
1221 sprintf (buf, "%s%d", BR_LABEL_BASE, i);
1223 fixP = fix_new (frag_now,
1224 p - frag_now->fr_literal,
1230 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1234 /*****************************************************************************
1235 * cobr_fmt: generate a COBR-format instruction
1237 **************************************************************************** */
1240 cobr_fmt (arg, opcode, oP)
1241 char *arg[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1242 long opcode; /* Opcode, with branch-prediction bits already set
1245 struct i960_opcode *oP;
1246 /*->description of instruction */
1248 long instr; /* 32-bit instruction */
1249 struct regop regop; /* Description of register operand */
1250 int n; /* Number of operands */
1251 int var_frag; /* 1 if varying length code fragment should
1252 * be emitted; 0 if an address fix
1253 * should be emitted.
1261 /* First operand (if any) of a COBR is always a register
1262 * operand. Parse it.
1264 parse_regop (®op, arg[1], oP->operand[0]);
1265 instr |= (regop.n << 19) | (regop.mode << 13);
1269 /* Second operand (if any) of a COBR is always a register
1270 * operand. Parse it.
1272 parse_regop (®op, arg[2], oP->operand[1]);
1273 instr |= (regop.n << 14) | regop.special;
1284 if (instrument_branches)
1287 colon (brlab_next ());
1290 /* A third operand to a COBR is always a displacement.
1291 * Parse it; if it's relaxable (a cobr "j" directive, or any
1292 * cobr other than bbs/bbc when the "-norelax" option is not in
1293 * use) set up a variable code fragment; otherwise set up an
1296 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1297 get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1299 if (instrument_branches)
1307 /*****************************************************************************
1308 * ctrl_fmt: generate a CTRL-format instruction
1310 **************************************************************************** */
1313 ctrl_fmt (targP, opcode, num_ops)
1314 char *targP; /* Pointer to text of lone operand (if any) */
1315 long opcode; /* Template of instruction */
1316 int num_ops; /* Number of operands */
1318 int instrument; /* TRUE iff we should add instrumentation to track
1319 * how often the branch is taken
1325 emit (opcode); /* Output opcode */
1330 instrument = instrument_branches && (opcode != CALL)
1331 && (opcode != B) && (opcode != RET) && (opcode != BAL);
1336 colon (brlab_next ());
1339 /* The operand MUST be an ip-relative displacment. Parse it
1340 * and set up address fix for the instruction we just output.
1342 get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1353 /*****************************************************************************
1354 * emit: output instruction binary
1356 * Output instruction binary, in target byte order, 4 bytes at a time.
1357 * Return pointer to where it was placed.
1359 **************************************************************************** */
1363 long instr; /* Word to be output, host byte order */
1365 char *toP; /* Where to output it */
1367 toP = frag_more (4); /* Allocate storage */
1368 md_number_to_chars (toP, instr, 4); /* Convert to target byte order */
1373 /*****************************************************************************
1374 * get_args: break individual arguments out of comma-separated list
1376 * Input assumptions:
1377 * - all comments and labels have been removed
1378 * - all strings of whitespace have been collapsed to a single blank.
1379 * - all character constants ('x') have been replaced with decimal
1382 * args[0] is untouched. args[1] points to first operand, etc. All args:
1383 * - are NULL-terminated
1384 * - contain no whitespace
1387 * Number of operands (0,1,2, or 3) or -1 on error.
1389 **************************************************************************** */
1392 register char *p; /* Pointer to comma-separated operands; MUCKED BY US */
1393 char *args[]; /* Output arg: pointers to operands placed in args[1-3].
1394 * MUST ACCOMMODATE 4 ENTRIES (args[0-3]).
1397 register int n; /* Number of operands */
1403 /* Skip lead white space */
1417 /* Squeze blanks out by moving non-blanks toward start of string.
1418 * Isolate operands, whenever comma is found.
1432 /* Start of operand */
1435 as_bad ("too many operands");
1438 *to++ = '\0'; /* Terminate argument */
1439 args[++n] = to; /* Start next argument */
1453 /*****************************************************************************
1454 * get_cdisp: handle displacement for a COBR or CTRL instruction.
1456 * Parse displacement for a COBR or CTRL instruction.
1458 * If successful, output the instruction opcode and set up for it,
1459 * depending on the arg 'var_frag', either:
1460 * o an address fixup to be done when all symbol values are known, or
1461 * o a varying length code fragment, with address fixup info. This
1462 * will be done for cobr instructions that may have to be relaxed
1463 * in to compare/branch instructions (8 bytes) if the final
1464 * address displacement is greater than 13 bits.
1466 *****************************************************************************/
1469 get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
1470 /* displacement as specified in source instruction */
1472 /* "COBR" or "CTRL" (for use in error message) */
1474 /* Instruction needing the displacement */
1476 /* # bits of displacement (13 for COBR, 24 for CTRL) */
1478 /* 1 if varying length code fragment should be emitted;
1479 * 0 if an address fix should be emitted.
1482 /* 1 if callj relocation should be done; else 0 */
1485 expressionS e; /* Parsed expression */
1486 fixS *fixP; /* Structure describing needed address fix */
1487 char *outP; /* Where instruction binary is output to */
1491 parse_expr (dispP, &e);
1495 as_bad ("expression syntax error");
1498 if (S_GET_SEGMENT (e.X_add_symbol) == text_section
1499 || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
1503 outP = frag_more (8); /* Allocate worst-case storage */
1504 md_number_to_chars (outP, instr, 4);
1505 frag_variant (rs_machine_dependent, 4, 4, 1,
1506 adds (e), offs (e), outP, 0, 0);
1510 /* Set up a new fix structure, so address can be updated
1511 * when all symbol values are known.
1513 outP = emit (instr);
1514 fixP = fix_new (frag_now,
1515 outP - frag_now->fr_literal,
1522 fixP->fx_tcbit = callj;
1524 /* We want to modify a bit field when the address is
1525 * known. But we don't need all the garbage in the
1526 * bit_fix structure. So we're going to lie and store
1527 * the number of bits affected instead of a pointer.
1529 fixP->fx_bit_fixP = (bit_fixS *) numbits;
1533 as_bad ("attempt to branch into different segment");
1537 as_bad ("target of %s instruction must be a label", ifmtP);
1543 /*****************************************************************************
1544 * get_ispec: parse a memory operand for an index specification
1546 * Here, an "index specification" is taken to be anything surrounded
1547 * by square brackets and NOT followed by anything else.
1549 * If it's found, detach it from the input string, remove the surrounding
1550 * square brackets, and return a pointer to it. Otherwise, return NULL.
1552 **************************************************************************** */
1556 char *textP; /*->memory operand from source instruction, no white space */
1558 char *start; /*->start of index specification */
1559 char *end; /*->end of index specification */
1561 /* Find opening square bracket, if any
1563 start = strchr (textP, '[');
1568 /* Eliminate '[', detach from rest of operand */
1571 end = strchr (start, ']');
1575 as_bad ("unmatched '['");
1580 /* Eliminate ']' and make sure it was the last thing
1584 if (*(end + 1) != '\0')
1586 as_bad ("garbage after index spec ignored");
1593 /*****************************************************************************
1596 * Look up a (suspected) register name in the register table and return the
1597 * associated register number (or -1 if not found).
1599 **************************************************************************** */
1602 get_regnum (regname)
1603 char *regname; /* Suspected register name */
1607 rP = (int *) hash_find (reg_hash, regname);
1608 return (rP == NULL) ? -1 : *rP;
1612 /*****************************************************************************
1613 * i_scan: perform lexical scan of ascii assembler instruction.
1615 * Input assumptions:
1616 * - input string is an i80960 instruction (not a pseudo-op)
1617 * - all comments and labels have been removed
1618 * - all strings of whitespace have been collapsed to a single blank.
1621 * args[0] points to opcode, other entries point to operands. All strings:
1622 * - are NULL-terminated
1623 * - contain no whitespace
1624 * - have character constants ('x') replaced with a decimal number
1627 * Number of operands (0,1,2, or 3) or -1 on error.
1629 **************************************************************************** */
1632 register char *iP; /* Pointer to ascii instruction; MUCKED BY US. */
1633 char *args[]; /* Output arg: pointers to opcode and operands placed
1634 * here. MUST ACCOMMODATE 4 ENTRIES.
1638 /* Isolate opcode */
1642 } /* Skip lead space, if any */
1644 for (; *iP != ' '; iP++)
1648 /* There are no operands */
1651 /* We never moved: there was no opcode either! */
1652 as_bad ("missing opcode");
1658 *iP++ = '\0'; /* Terminate opcode */
1659 return (get_args (iP, args));
1663 /*****************************************************************************
1664 * mem_fmt: generate a MEMA- or MEMB-format instruction
1666 **************************************************************************** */
1668 mem_fmt (args, oP, callx)
1669 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1670 struct i960_opcode *oP; /* Pointer to description of instruction */
1671 int callx; /* Is this a callx opcode */
1673 int i; /* Loop counter */
1674 struct regop regop; /* Description of register operand */
1675 char opdesc; /* Operand descriptor byte */
1676 memS instr; /* Description of binary to be output */
1677 char *outP; /* Where the binary was output to */
1678 expressionS expr; /* Parsed expression */
1679 fixS *fixP; /*->description of deferred address fixup */
1682 /* COFF support isn't in place yet for callx relaxing. */
1686 memset (&instr, '\0', sizeof (memS));
1687 instr.opcode = oP->opcode;
1689 /* Process operands. */
1690 for (i = 1; i <= oP->num_ops; i++)
1692 opdesc = oP->operand[i - 1];
1696 parse_memop (&instr, args[i], oP->format);
1700 parse_regop (®op, args[i], opdesc);
1701 instr.opcode |= regop.n << 19;
1706 outP = emit (instr.opcode);
1708 if (instr.disp == 0)
1713 /* Parse and process the displacement */
1714 parse_expr (instr.e, &expr);
1718 as_bad ("expression syntax error");
1722 if (instr.disp == 32)
1724 (void) emit (offs (expr)); /* Output displacement */
1728 /* 12-bit displacement */
1729 if (offs (expr) & ~0xfff)
1731 /* Won't fit in 12 bits: convert already-output
1732 * instruction to MEMB format, output
1735 mema_to_memb (outP);
1736 (void) emit (offs (expr));
1740 /* WILL fit in 12 bits: OR into opcode and
1741 * overwrite the binary we already put out
1743 instr.opcode |= offs (expr);
1744 md_number_to_chars (outP, instr.opcode, 4);
1750 if (instr.disp == 12)
1752 /* Displacement is dependent on a symbol, whose value
1753 * may change at link time. We HAVE to reserve 32 bits.
1754 * Convert already-output opcode to MEMB format.
1756 mema_to_memb (outP);
1759 /* Output 0 displacement and set up address fixup for when
1760 * this symbol's value becomes known.
1762 outP = emit ((long) 0);
1763 fixP = fix_new_exp (frag_now,
1764 outP - frag_now->fr_literal,
1769 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1770 /* Steve's linker relaxing hack. Mark this 32-bit relocation as
1771 being in the instruction stream, specifically as part of a callx
1773 fixP->fx_bsr = callx;
1779 /*****************************************************************************
1780 * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1782 * There are 2 possible MEMA formats:
1783 * - displacement only
1784 * - displacement + abase
1786 * They are distinguished by the setting of the MEMA_ABASE bit.
1788 **************************************************************************** */
1790 mema_to_memb (opcodeP)
1791 char *opcodeP; /* Where to find the opcode, in target byte order */
1793 long opcode; /* Opcode in host byte order */
1794 long mode; /* Mode bits for MEMB instruction */
1796 opcode = md_chars_to_number (opcodeP, 4);
1797 know (!(opcode & MEMB_BIT));
1799 mode = MEMB_BIT | D_BIT;
1800 if (opcode & MEMA_ABASE)
1805 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */
1806 opcode |= mode; /* Set MEMB mode bits */
1808 md_number_to_chars (opcodeP, opcode, 4);
1809 } /* mema_to_memb() */
1812 /*****************************************************************************
1813 * parse_expr: parse an expression
1815 * Use base assembler's expression parser to parse an expression.
1816 * It, unfortunately, runs off a global which we have to save/restore
1817 * in order to make it work for us.
1819 * An empty expression string is treated as an absolute 0.
1821 * Sets O_illegal regardless of expression evaluation if entire input
1822 * string is not consumed in the evaluation -- tolerate no dangling junk!
1824 **************************************************************************** */
1826 parse_expr (textP, expP)
1827 char *textP; /* Text of expression to be parsed */
1828 expressionS *expP; /* Where to put the results of parsing */
1830 char *save_in; /* Save global here */
1837 /* Treat empty string as absolute 0 */
1838 expP->X_add_symbol = expP->X_op_symbol = NULL;
1839 expP->X_add_number = 0;
1840 expP->X_op = O_constant;
1844 save_in = input_line_pointer; /* Save global */
1845 input_line_pointer = textP; /* Make parser work for us */
1847 (void) expression (expP);
1848 if (input_line_pointer - textP != strlen (textP))
1850 /* Did not consume all of the input */
1851 expP->X_op = O_illegal;
1853 symP = expP->X_add_symbol;
1854 if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
1856 /* Register name in an expression */
1857 /* FIXME: this isn't much of a check any more. */
1858 expP->X_op = O_illegal;
1861 input_line_pointer = save_in; /* Restore global */
1866 /*****************************************************************************
1868 * Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1869 * i80960 instruction.
1871 * Assumes the input consists of:
1872 * arg[0] opcode mnemonic ('ldconst')
1873 * arg[1] first operand (constant)
1874 * arg[2] name of register to be loaded
1876 * Replaces opcode and/or operands as appropriate.
1878 * Returns the new number of arguments, or -1 on failure.
1880 **************************************************************************** */
1884 char *arg[]; /* See above */
1886 int n; /* Constant to be loaded */
1887 int shift; /* Shift count for "shlo" instruction */
1888 static char buf[5]; /* Literal for first operand */
1889 static char buf2[5]; /* Literal for second operand */
1890 expressionS e; /* Parsed expression */
1893 arg[3] = NULL; /* So we can tell at the end if it got used or not */
1895 parse_expr (arg[1], &e);
1899 /* We're dependent on one or more symbols -- use "lda" */
1904 /* Try the following mappings:
1905 * ldconst 0,<reg> ->mov 0,<reg>
1906 * ldconst 31,<reg> ->mov 31,<reg>
1907 * ldconst 32,<reg> ->addo 1,31,<reg>
1908 * ldconst 62,<reg> ->addo 31,31,<reg>
1909 * ldconst 64,<reg> ->shlo 8,3,<reg>
1910 * ldconst -1,<reg> ->subo 1,0,<reg>
1911 * ldconst -31,<reg>->subo 31,0,<reg>
1913 * anthing else becomes:
1917 if ((0 <= n) && (n <= 31))
1922 else if ((-31 <= n) && (n <= -1))
1926 sprintf (buf, "%d", -n);
1931 else if ((32 <= n) && (n <= 62))
1936 sprintf (buf, "%d", n - 31);
1940 else if ((shift = shift_ok (n)) != 0)
1944 sprintf (buf, "%d", shift);
1946 sprintf (buf2, "%d", n >> shift);
1957 as_bad ("invalid constant");
1961 return (arg[3] == 0) ? 2 : 3;
1964 /*****************************************************************************
1965 * parse_memop: parse a memory operand
1967 * This routine is based on the observation that the 4 mode bits of the
1968 * MEMB format, taken individually, have fairly consistent meaning:
1970 * M3 (bit 13): 1 if displacement is present (D_BIT)
1971 * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1972 * M1 (bit 11): 1 if index is present (I_BIT)
1973 * M0 (bit 10): 1 if abase is present (A_BIT)
1975 * So we parse the memory operand and set bits in the mode as we find
1976 * things. Then at the end, if we go to MEMB format, we need only set
1977 * the MEMB bit (M2) and our mode is built for us.
1979 * Unfortunately, I said "fairly consistent". The exceptions:
1982 * 0100 Would seem illegal, but means "abase-only".
1984 * 0101 Would seem to mean "abase-only" -- it means IP-relative.
1985 * Must be converted to 0100.
1987 * 0110 Would seem to mean "index-only", but is reserved.
1988 * We turn on the D bit and provide a 0 displacement.
1990 * The other thing to observe is that we parse from the right, peeling
1991 * things * off as we go: first any index spec, then any abase, then
1994 **************************************************************************** */
1997 parse_memop (memP, argP, optype)
1998 memS *memP; /* Where to put the results */
1999 char *argP; /* Text of the operand to be parsed */
2000 int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
2002 char *indexP; /* Pointer to index specification with "[]" removed */
2003 char *p; /* Temp char pointer */
2004 char iprel_flag; /* True if this is an IP-relative operand */
2005 int regnum; /* Register number */
2006 int scale; /* Scale factor: 1,2,4,8, or 16. Later converted
2007 * to internal format (0,1,2,3,4 respectively).
2009 int mode; /* MEMB mode bits */
2010 int *intP; /* Pointer to register number */
2012 /* The following table contains the default scale factors for each
2013 * type of memory instruction. It is accessed using (optype-MEM1)
2014 * as an index -- thus it assumes the 'optype' constants are assigned
2015 * consecutive values, in the order they appear in this table
2017 static int def_scale[] =
2023 -1, /* MEM12 -- no valid default */
2028 iprel_flag = mode = 0;
2030 /* Any index present? */
2031 indexP = get_ispec (argP);
2034 p = strchr (indexP, '*');
2037 /* No explicit scale -- use default for this
2040 scale = def_scale[optype - MEM1];
2044 *p++ = '\0'; /* Eliminate '*' */
2046 /* Now indexP->a '\0'-terminated register name,
2047 * and p->a scale factor.
2050 if (!strcmp (p, "16"))
2054 else if (strchr ("1248", *p) && (p[1] == '\0'))
2064 regnum = get_regnum (indexP); /* Get index reg. # */
2065 if (!IS_RG_REG (regnum))
2067 as_bad ("invalid index register");
2071 /* Convert scale to its binary encoding */
2090 as_bad ("invalid scale factor");
2094 memP->opcode |= scale | regnum; /* Set index bits in opcode */
2095 mode |= I_BIT; /* Found a valid index spec */
2098 /* Any abase (Register Indirect) specification present? */
2099 if ((p = strrchr (argP, '(')) != NULL)
2101 /* "(" is there -- does it start a legal abase spec?
2102 * (If not it could be part of a displacement expression.)
2104 intP = (int *) hash_find (areg_hash, p);
2107 /* Got an abase here */
2109 *p = '\0'; /* discard register spec */
2110 if (regnum == IPREL)
2112 /* We have to specialcase ip-rel mode */
2117 memP->opcode |= regnum << 14;
2123 /* Any expression present? */
2130 /* Special-case ip-relative addressing */
2139 memP->opcode |= 5 << 10; /* IP-relative mode */
2145 /* Handle all other modes */
2149 /* Go with MEMA instruction format for now (grow to MEMB later
2150 * if 12 bits is not enough for the displacement).
2151 * MEMA format has a single mode bit: set it to indicate
2152 * that abase is present.
2154 memP->opcode |= MEMA_ABASE;
2159 /* Go with MEMA instruction format for now (grow to MEMB later
2160 * if 12 bits is not enough for the displacement).
2166 /* For some reason, the bit string for this mode is not
2167 * consistent: it should be 0 (exclusive of the MEMB bit),
2168 * so we set it "by hand" here.
2170 memP->opcode |= MEMB_BIT;
2174 /* set MEMB bit in mode, and OR in mode bits */
2175 memP->opcode |= mode | MEMB_BIT;
2179 /* Treat missing displacement as displacement of 0 */
2181 /***********************
2182 * Fall into next case *
2183 ********************** */
2184 case D_BIT | A_BIT | I_BIT:
2186 /* set MEMB bit in mode, and OR in mode bits */
2187 memP->opcode |= mode | MEMB_BIT;
2197 /*****************************************************************************
2198 * parse_po: parse machine-dependent pseudo-op
2200 * This is a top-level routine for machine-dependent pseudo-ops. It slurps
2201 * up the rest of the input line, breaks out the individual arguments,
2202 * and dispatches them to the correct handler.
2203 **************************************************************************** */
2207 int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
2209 char *args[4]; /* Pointers operands, with no embedded whitespace.
2211 * arg[1-3]->operands
2213 int n_ops; /* Number of operands */
2214 char *p; /* Pointer to beginning of unparsed argument string */
2215 char eol; /* Character that indicated end of line */
2217 extern char is_end_of_line[];
2219 /* Advance input pointer to end of line. */
2220 p = input_line_pointer;
2221 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2223 input_line_pointer++;
2225 eol = *input_line_pointer; /* Save end-of-line char */
2226 *input_line_pointer = '\0'; /* Terminate argument list */
2228 /* Parse out operands */
2229 n_ops = get_args (p, args);
2235 /* Dispatch to correct handler */
2239 s_sysproc (n_ops, args);
2242 s_leafproc (n_ops, args);
2249 /* Restore eol, so line numbers get updated correctly. Base assembler
2250 * assumes we leave input pointer pointing at char following the eol.
2252 *input_line_pointer++ = eol;
2255 /*****************************************************************************
2256 * parse_regop: parse a register operand.
2258 * In case of illegal operand, issue a message and return some valid
2259 * information so instruction processing can continue.
2260 **************************************************************************** */
2263 parse_regop (regopP, optext, opdesc)
2264 struct regop *regopP; /* Where to put description of register operand */
2265 char *optext; /* Text of operand */
2266 char opdesc; /* Descriptor byte: what's legal for this operand */
2268 int n; /* Register number */
2269 expressionS e; /* Parsed expression */
2271 /* See if operand is a register */
2272 n = get_regnum (optext);
2277 /* global or local register */
2278 if (!REG_ALIGN (opdesc, n))
2280 as_bad ("unaligned register");
2284 regopP->special = 0;
2287 else if (IS_FP_REG (n) && FP_OK (opdesc))
2289 /* Floating point register, and it's allowed */
2290 regopP->n = n - FP0;
2292 regopP->special = 0;
2295 else if (IS_SF_REG (n) && SFR_OK (opdesc))
2297 /* Special-function register, and it's allowed */
2298 regopP->n = n - SF0;
2300 regopP->special = 1;
2301 if (!targ_has_sfr (regopP->n))
2303 as_bad ("no such sfr in this architecture");
2308 else if (LIT_OK (opdesc))
2311 * How about a literal?
2314 regopP->special = 0;
2316 { /* floating point literal acceptable */
2317 /* Skip over 0f, 0d, or 0e prefix */
2318 if ((optext[0] == '0')
2319 && (optext[1] >= 'd')
2320 && (optext[1] <= 'f'))
2325 if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
2330 if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
2338 { /* fixed point literal acceptable */
2339 parse_expr (optext, &e);
2340 if (e.X_op != O_constant
2341 || (offs (e) < 0) || (offs (e) > 31))
2343 as_bad ("illegal literal");
2346 regopP->n = offs (e);
2351 /* Nothing worked */
2353 regopP->mode = 0; /* Register r0 is always a good one */
2355 regopP->special = 0;
2356 } /* parse_regop() */
2358 /*****************************************************************************
2359 * reg_fmt: generate a REG-format instruction
2361 **************************************************************************** */
2364 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2365 struct i960_opcode *oP; /* Pointer to description of instruction */
2367 long instr; /* Binary to be output */
2368 struct regop regop; /* Description of register operand */
2369 int n_ops; /* Number of operands */
2373 n_ops = oP->num_ops;
2377 parse_regop (®op, args[1], oP->operand[0]);
2379 if ((n_ops == 1) && !(instr & M3))
2381 /* 1-operand instruction in which the dst field should
2382 * be used (instead of src1).
2387 regop.mode = regop.special;
2394 /* regop.n goes in bit 0, needs no shifting */
2396 regop.special <<= 5;
2398 instr |= regop.n | regop.mode | regop.special;
2403 parse_regop (®op, args[2], oP->operand[1]);
2405 if ((n_ops == 2) && !(instr & M3))
2407 /* 2-operand instruction in which the dst field should
2408 * be used instead of src2).
2413 regop.mode = regop.special;
2422 regop.special <<= 6;
2424 instr |= regop.n | regop.mode | regop.special;
2428 parse_regop (®op, args[3], oP->operand[2]);
2431 regop.mode = regop.special;
2433 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2439 /*****************************************************************************
2441 * Replace cobr instruction in a code fragment with equivalent branch and
2442 * compare instructions, so it can reach beyond a 13-bit displacement.
2443 * Set up an address fix/relocation for the new branch instruction.
2445 **************************************************************************** */
2447 /* This "conditional jump" table maps cobr instructions into equivalent
2448 * compare and branch opcodes.
2458 { /* COBR OPCODE: */
2459 { CHKBIT, BNO }, /* 0x30 - bbc */
2460 { CMPO, BG }, /* 0x31 - cmpobg */
2461 { CMPO, BE }, /* 0x32 - cmpobe */
2462 { CMPO, BGE }, /* 0x33 - cmpobge */
2463 { CMPO, BL }, /* 0x34 - cmpobl */
2464 { CMPO, BNE }, /* 0x35 - cmpobne */
2465 { CMPO, BLE }, /* 0x36 - cmpoble */
2466 { CHKBIT, BO }, /* 0x37 - bbs */
2467 { CMPI, BNO }, /* 0x38 - cmpibno */
2468 { CMPI, BG }, /* 0x39 - cmpibg */
2469 { CMPI, BE }, /* 0x3a - cmpibe */
2470 { CMPI, BGE }, /* 0x3b - cmpibge */
2471 { CMPI, BL }, /* 0x3c - cmpibl */
2472 { CMPI, BNE }, /* 0x3d - cmpibne */
2473 { CMPI, BLE }, /* 0x3e - cmpible */
2474 { CMPI, BO }, /* 0x3f - cmpibo */
2480 register fragS *fragP; /* fragP->fr_opcode is assumed to point to
2481 * the cobr instruction, which comes at the
2482 * end of the code fragment.
2485 int opcode, src1, src2, m1, s2;
2486 /* Bit fields from cobr instruction */
2487 long bp_bits; /* Branch prediction bits from cobr instruction */
2488 long instr; /* A single i960 instruction */
2489 char *iP; /*->instruction to be replaced */
2490 fixS *fixP; /* Relocation that can be done at assembly time */
2492 /* PICK UP & PARSE COBR INSTRUCTION */
2493 iP = fragP->fr_opcode;
2494 instr = md_chars_to_number (iP, 4);
2495 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2496 src1 = (instr >> 19) & 0x1f;
2497 m1 = (instr >> 13) & 1;
2499 src2 = (instr >> 14) & 0x1f;
2500 bp_bits = instr & BP_MASK;
2502 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2503 instr = coj[opcode].compare
2504 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2505 md_number_to_chars (iP, instr, 4);
2507 /* OUTPUT BRANCH INSTRUCTION */
2508 md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
2510 /* SET UP ADDRESS FIXUP/RELOCATION */
2511 fixP = fix_new (fragP,
2512 iP + 4 - fragP->fr_literal,
2519 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */
2526 /*****************************************************************************
2527 * reloc_callj: Relocate a 'callj' instruction
2529 * This is a "non-(GNU)-standard" machine-dependent hook. The base
2530 * assembler calls it when it decides it can relocate an address at
2531 * assembly time instead of emitting a relocation directive.
2533 * Check to see if the relocation involves a 'callj' instruction to a:
2534 * sysproc: Replace the default 'call' instruction with a 'calls'
2535 * leafproc: Replace the default 'call' instruction with a 'bal'.
2536 * other proc: Do nothing.
2538 * See b.out.h for details on the 'n_other' field in a symbol structure.
2541 * Assumes the caller has already figured out, in the case of a leafproc,
2542 * to use the 'bal' entry point, and has substituted that symbol into the
2543 * passed fixup structure.
2545 **************************************************************************** */
2548 fixS *fixP; /* Relocation that can be done at assembly time */
2550 char *where; /*->the binary for the instruction being relocated */
2552 if (!fixP->fx_tcbit)
2555 } /* This wasn't a callj instruction in the first place */
2557 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2559 if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2561 /* Symbol is a .sysproc: replace 'call' with 'calls'.
2562 * System procedure number is (other-1).
2564 md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2566 /* Nothing else needs to be done for this instruction.
2567 * Make sure 'md_number_to_field()' will perform a no-op.
2569 fixP->fx_bit_fixP = (bit_fixS *) 1;
2572 else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2574 /* Should not happen: see block comment above */
2575 as_fatal ("Trying to 'bal' to %s", S_GET_NAME (fixP->fx_addsy));
2578 else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2580 /* Replace 'call' with 'bal'; both instructions have
2581 * the same format, so calling code should complete
2582 * relocation as if nothing happened here.
2584 md_number_to_chars (where, BAL, 4);
2586 else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2588 as_bad ("Looks like a proc, but can't tell what kind.\n");
2589 } /* switch on proc type */
2591 /* else Symbol is neither a sysproc nor a leafproc */
2595 /*****************************************************************************
2596 * s_leafproc: process .leafproc pseudo-op
2598 * .leafproc takes two arguments, the second one is optional:
2599 * arg[1]: name of 'call' entry point to leaf procedure
2600 * arg[2]: name of 'bal' entry point to leaf procedure
2602 * If the two arguments are identical, or if the second one is missing,
2603 * the first argument is taken to be the 'bal' entry point.
2605 * If there are 2 distinct arguments, we must make sure that the 'bal'
2606 * entry point immediately follows the 'call' entry point in the linked
2609 **************************************************************************** */
2611 s_leafproc (n_ops, args)
2612 int n_ops; /* Number of operands */
2613 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2615 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */
2616 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */
2618 if ((n_ops != 1) && (n_ops != 2))
2620 as_bad ("should have 1 or 2 operands");
2622 } /* Check number of arguments */
2624 /* Find or create symbol for 'call' entry point. */
2625 callP = symbol_find_or_make (args[1]);
2627 if (TC_S_IS_CALLNAME (callP))
2629 as_warn ("Redefining leafproc %s", S_GET_NAME (callP));
2632 /* If that was the only argument, use it as the 'bal' entry point.
2633 * Otherwise, mark it as the 'call' entry point and find or create
2634 * another symbol for the 'bal' entry point.
2636 if ((n_ops == 1) || !strcmp (args[1], args[2]))
2638 TC_S_FORCE_TO_BALNAME (callP);
2643 TC_S_FORCE_TO_CALLNAME (callP);
2645 balP = symbol_find_or_make (args[2]);
2646 if (TC_S_IS_CALLNAME (balP))
2648 as_warn ("Redefining leafproc %s", S_GET_NAME (balP));
2650 TC_S_FORCE_TO_BALNAME (balP);
2652 tc_set_bal_of_call (callP, balP);
2653 } /* if only one arg, or the args are the same */
2658 * s_sysproc: process .sysproc pseudo-op
2660 * .sysproc takes two arguments:
2661 * arg[1]: name of entry point to system procedure
2662 * arg[2]: 'entry_num' (index) of system procedure in the range
2665 * For [ab].out, we store the 'entrynum' in the 'n_other' field of
2666 * the symbol. Since that entry is normally 0, we bias 'entrynum'
2667 * by adding 1 to it. It must be unbiased before it is used.
2670 s_sysproc (n_ops, args)
2671 int n_ops; /* Number of operands */
2672 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2679 as_bad ("should have two operands");
2681 } /* bad arg count */
2683 /* Parse "entry_num" argument and check it for validity. */
2684 parse_expr (args[2], &exp);
2685 if (exp.X_op != O_constant
2687 || (offs (exp) > 31))
2689 as_bad ("'entry_num' must be absolute number in [0,31]");
2693 /* Find/make symbol and stick entry number (biased by +1) into it */
2694 symP = symbol_find_or_make (args[1]);
2696 if (TC_S_IS_SYSPROC (symP))
2698 as_warn ("Redefining entrynum for sysproc %s", S_GET_NAME (symP));
2701 TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */
2702 TC_S_FORCE_TO_SYSPROC (symP);
2706 /*****************************************************************************
2708 * Determine if a "shlo" instruction can be used to implement a "ldconst".
2709 * This means that some number X < 32 can be shifted left to produce the
2710 * constant of interest.
2712 * Return the shift count, or 0 if we can't do it.
2713 * Caller calculates X by shifting original constant right 'shift' places.
2715 **************************************************************************** */
2719 int n; /* The constant of interest */
2721 int shift; /* The shift count */
2725 /* Can't do it for negative numbers */
2729 /* Shift 'n' right until a 1 is about to be lost */
2730 for (shift = 0; (n & 1) == 0; shift++)
2743 /*****************************************************************************
2744 * syntax: issue syntax error
2746 **************************************************************************** */
2750 as_bad ("syntax error");
2754 /*****************************************************************************
2756 * Return TRUE iff the target architecture supports the specified
2757 * special-function register (sfr).
2759 *****************************************************************************/
2763 int n; /* Number (0-31) of sfr */
2765 switch (architecture)
2773 return ((0 <= n) && (n <= 2));
2778 /*****************************************************************************
2780 * Return TRUE iff the target architecture supports the indicated
2781 * class of instructions.
2783 *****************************************************************************/
2786 targ_has_iclass (ic)
2787 int ic; /* Instruction class; one of:
2788 * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM
2791 iclasses_seen |= ic;
2792 switch (architecture)
2795 return ic & (I_BASE | I_KX);
2797 return ic & (I_BASE | I_KX | I_FP | I_DEC);
2799 return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2801 return ic & (I_BASE | I_CX | I_CASIM);
2803 if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
2804 && (iclasses_seen & I_CX))
2806 as_warn ("architecture of opcode conflicts with that of earlier instruction(s)");
2807 iclasses_seen &= ~ic;
2814 /* Parse an operand that is machine-specific.
2815 We just return without modifying the expression if we have nothing
2820 md_operand (expressionP)
2821 expressionS *expressionP;
2825 /* We have no need to default values of symbols. */
2829 md_undefined_symbol (name)
2835 /* Exactly what point is a PC-relative offset relative TO?
2836 On the i960, they're relative to the address of the instruction,
2837 which we have set up as the address of the fixup too. */
2839 md_pcrel_from (fixP)
2842 return fixP->fx_where + fixP->fx_frag->fr_address;
2846 md_apply_fix (fixP, val)
2850 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2852 if (!fixP->fx_bit_fixP)
2853 switch (fixP->fx_im_disp)
2856 /* For callx, we always want to write out zero, and emit a
2857 symbolic relocation. */
2861 fixP->fx_addnumber = val;
2862 md_number_to_imm (place, val, fixP->fx_size, fixP);
2865 md_number_to_disp (place,
2867 ? val + fixP->fx_pcrel_adjust
2871 case 2: /* fix requested for .long .word etc */
2872 md_number_to_chars (place, val, fixP->fx_size);
2875 as_fatal ("Internal error in md_apply_fix() in file \"%s\"",
2879 md_number_to_field (place, val, fixP->fx_bit_fixP);
2882 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2884 tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
2887 relax_addressT segment_address_in_file;
2889 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
2890 struct relocation_info ri;
2893 memset ((char *) &ri, '\0', sizeof (ri));
2894 symbolP = fixP->fx_addsy;
2895 know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2896 ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2897 /* These two 'cuz of NS32K */
2898 ri.r_callj = fixP->fx_tcbit;
2899 if (fixP->fx_bit_fixP)
2902 ri.r_length = nbytes_r_length[fixP->fx_size];
2903 ri.r_pcrel = fixP->fx_pcrel;
2904 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2906 if (fixP->fx_r_type != NO_RELOC)
2908 switch (fixP->fx_r_type)
2913 ri.r_length = fixP->fx_size - 1;
2927 else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
2930 ri.r_index = symbolP->sy_number;
2935 ri.r_index = S_GET_TYPE (symbolP);
2938 /* Output the relocation information in machine-dependent form. */
2939 md_ri_to_chars (where, &ri);
2942 #endif /* OBJ_AOUT or OBJ_BOUT */
2944 #if defined (OBJ_COFF) && defined (BFD)
2946 tc_coff_fix2rtype (fixP)
2952 if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
2955 if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
2962 tc_coff_sizemachdep (frag)
2966 return frag->fr_next->fr_address - frag->fr_address;
2972 /* Align an address by rounding it up to the specified boundary. */
2974 md_section_align (seg, addr)
2976 valueT addr; /* Address to be rounded up */
2978 return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
2979 } /* md_section_align() */
2983 tc_headers_hook (headers)
2984 object_headers *headers;
2986 if (iclasses_seen == I_BASE)
2988 headers->filehdr.f_flags |= F_I960CORE;
2990 else if (iclasses_seen & I_CX)
2992 headers->filehdr.f_flags |= F_I960CA;
2994 else if (iclasses_seen & I_MIL)
2996 headers->filehdr.f_flags |= F_I960MC;
2998 else if (iclasses_seen & (I_DEC | I_FP))
3000 headers->filehdr.f_flags |= F_I960KB;
3004 headers->filehdr.f_flags |= F_I960KA;
3005 } /* set arch flag */
3009 headers->filehdr.f_magic = I960RWMAGIC;
3010 headers->aouthdr.magic = OMAGIC;
3014 headers->filehdr.f_magic = I960ROMAGIC;
3015 headers->aouthdr.magic = NMAGIC;
3016 } /* set magic numbers */
3019 #endif /* OBJ_COFF */
3022 * Things going on here:
3024 * For bout, We need to assure a couple of simplifying
3025 * assumptions about leafprocs for the linker: the leafproc
3026 * entry symbols will be defined in the same assembly in
3027 * which they're declared with the '.leafproc' directive;
3028 * and if a leafproc has both 'call' and 'bal' entry points
3029 * they are both global or both local.
3031 * For coff, the call symbol has a second aux entry that
3032 * contains the bal entry point. The bal symbol becomes a
3035 * For coff representation, the call symbol has a second aux entry that
3036 * contains the bal entry point. The bal symbol becomes a label.
3041 tc_crawl_symbol_chain (headers)
3042 object_headers *headers;
3046 for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
3049 if (TC_S_IS_SYSPROC (symbolP))
3051 /* second aux entry already contains the sysproc number */
3052 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3053 S_SET_STORAGE_CLASS (symbolP, C_SCALL);
3054 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3056 } /* rewrite sysproc */
3057 #endif /* OBJ_COFF */
3059 if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
3062 } /* Not a leafproc symbol */
3064 if (!S_IS_DEFINED (symbolP))
3066 as_bad ("leafproc symbol '%s' undefined", S_GET_NAME (symbolP));
3067 } /* undefined leaf */
3069 if (TC_S_IS_CALLNAME (symbolP))
3071 symbolS *balP = tc_get_bal_of_call (symbolP);
3072 if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
3074 S_SET_EXTERNAL (symbolP);
3075 S_SET_EXTERNAL (balP);
3076 as_warn ("Warning: making leafproc entries %s and %s both global\n",
3077 S_GET_NAME (symbolP), S_GET_NAME (balP));
3078 } /* externality mismatch */
3080 } /* walk the symbol chain */
3084 * For aout or bout, the bal immediately follows the call.
3086 * For coff, we cheat and store a pointer to the bal symbol
3087 * in the second aux entry of the call.
3099 tc_set_bal_of_call (callP, balP)
3103 know (TC_S_IS_CALLNAME (callP));
3104 know (TC_S_IS_BALNAME (balP));
3108 callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP;
3109 S_SET_NUMBER_AUXILIARY (callP, 2);
3111 #else /* ! OBJ_COFF */
3114 /* If the 'bal' entry doesn't immediately follow the 'call'
3115 * symbol, unlink it from the symbol list and re-insert it.
3117 if (symbol_next (callP) != balP)
3119 symbol_remove (balP, &symbol_rootP, &symbol_lastP);
3120 symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
3121 } /* if not in order */
3123 #else /* ! OBJ_ABOUT */
3124 (as yet unwritten.);
3125 #endif /* ! OBJ_ABOUT */
3126 #endif /* ! OBJ_COFF */
3130 _tc_get_bal_of_call (callP)
3135 know (TC_S_IS_CALLNAME (callP));
3138 retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry);
3141 retval = symbol_next (callP);
3143 (as yet unwritten.);
3144 #endif /* ! OBJ_ABOUT */
3145 #endif /* ! OBJ_COFF */
3147 know (TC_S_IS_BALNAME (retval));
3148 return ((char *) retval);
3149 } /* _tc_get_bal_of_call() */
3152 tc_coff_symbol_emit_hook (symbolP)
3155 if (TC_S_IS_CALLNAME (symbolP))
3158 symbolS *balP = tc_get_bal_of_call (symbolP);
3160 /* second aux entry contains the bal entry point */
3161 /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */
3162 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
3163 S_SET_STORAGE_CLASS (symbolP, (!SF_GET_LOCAL (symbolP) ? C_LEAFEXT : C_LEAFSTAT));
3164 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3165 /* fix up the bal symbol */
3166 S_SET_STORAGE_CLASS (balP, C_LABEL);
3167 #endif /* OBJ_COFF */
3168 } /* only on calls */
3172 i960_handle_align (fragp)
3182 as_bad ("option --link-relax is only supported in b.out format");
3188 /* The text section "ends" with another alignment reloc, to which we
3189 aren't adding padding. */
3190 if (fragp->fr_next == text_last_frag
3191 || fragp->fr_next == data_last_frag)
3194 /* alignment directive */
3195 fixp = fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
3196 (int) fragp->fr_type);
3197 #endif /* OBJ_BOUT */
3201 i960_validate_fix (fixP, this_segment_type, add_symbolPP)
3203 segT this_segment_type;
3204 symbolS **add_symbolPP;
3206 #define add_symbolP (*add_symbolPP)
3207 if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP))
3209 /* Relocation should be done via the associated 'bal'
3210 entry point symbol. */
3212 if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP)))
3214 as_bad ("No 'bal' entry point for leafproc %s",
3215 S_GET_NAME (add_symbolP));
3218 fixP->fx_addsy = add_symbolP = tc_get_bal_of_call (add_symbolP);
3221 /* Still have to work out other conditions for these tests. */
3225 as_bad ("callj to difference of two symbols");
3229 if ((int) fixP->fx_bit_fixP == 13)
3231 /* This is a COBR instruction. They have only a 13-bit
3232 displacement and are only to be used for local branches:
3233 flag as error, don't generate relocation. */
3234 as_bad ("can't use COBR format with external label");
3235 fixP->fx_addsy = NULL; /* No relocations please. */
3244 /* end of tc-i960.c */