1 /* tc-i960.c - All the i80960-specific stuff
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* See comment on md_parse_option for 80960-specific invocation options. */
23 /* There are 4 different lengths of (potentially) symbol-based displacements
24 in the 80960 instruction set, each of which could require address fix-ups
25 and (in the case of external symbols) emission of relocation directives:
28 This is a standard length for the base assembler and requires no
32 This is a non-standard length, but the base assembler has a
33 hook for bit field address fixups: the fixS structure can
34 point to a descriptor of the field, in which case our
35 md_number_to_field() routine gets called to process it.
37 I made the hook a little cleaner by having fix_new() (in the base
38 assembler) return a pointer to the fixS in question. And I made it a
39 little simpler by storing the field size (in this case 13) instead of
40 of a pointer to another structure: 80960 displacements are ALWAYS
41 stored in the low-order bits of a 4-byte word.
43 Since the target of a COBR cannot be external, no relocation
44 directives for this size displacement have to be generated.
45 But the base assembler had to be modified to issue error
46 messages if the symbol did turn out to be external.
49 Fixups are handled as for the 13-bit case (except that 24 is stored
52 The relocation directive generated is the same as that for the 32-bit
53 displacement, except that it's PC-relative (the 32-bit displacement
54 never is). The i80960 version of the linker needs a mod to
55 distinguish and handle the 24-bit case.
58 MEMA formats are always promoted to MEMB (32-bit) if the displacement
59 is based on a symbol, because it could be relocated at link time.
60 The only time we use the 12-bit format is if an absolute value of
61 less than 4096 is specified, in which case we need neither a fixup nor
62 a relocation directive. */
66 #include "safe-ctype.h"
68 #include "opcode/i960.h"
70 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
72 #define TC_S_IS_SYSPROC(s) ((1 <= S_GET_OTHER (s)) && (S_GET_OTHER (s) <= 32))
73 #define TC_S_IS_BALNAME(s) (S_GET_OTHER (s) == N_BALNAME)
74 #define TC_S_IS_CALLNAME(s) (S_GET_OTHER (s) == N_CALLNAME)
75 #define TC_S_IS_BADPROC(s) ((S_GET_OTHER (s) != 0) && !TC_S_IS_CALLNAME (s) && !TC_S_IS_BALNAME (s) && !TC_S_IS_SYSPROC (s))
77 #define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER ((s), (p) + 1))
78 #define TC_S_GET_SYSPROC(s) (S_GET_OTHER (s) - 1)
80 #define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER ((s), N_BALNAME))
81 #define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER ((s), N_CALLNAME))
82 #define TC_S_FORCE_TO_SYSPROC(s) {;}
84 #else /* ! OBJ_A/BOUT */
87 #define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS (s) == C_SCALL)
88 #define TC_S_IS_BALNAME(s) (SF_GET_BALNAME (s))
89 #define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME (s))
90 #define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC (s) && TC_S_GET_SYSPROC (s) < 0 && 31 < TC_S_GET_SYSPROC (s))
92 #define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
93 #define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
95 #define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME (s))
96 #define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME (s))
97 #define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS ((s), C_SCALL))
99 #else /* ! OBJ_COFF */
101 #define TC_S_IS_SYSPROC(s) 0
103 #define TC_S_IS_BALNAME(s) 0
104 #define TC_S_IS_CALLNAME(s) 0
105 #define TC_S_IS_BADPROC(s) 0
107 #define TC_S_SET_SYSPROC(s, p)
108 #define TC_S_GET_SYSPROC(s) 0
110 #define TC_S_FORCE_TO_BALNAME(s)
111 #define TC_S_FORCE_TO_CALLNAME(s)
112 #define TC_S_FORCE_TO_SYSPROC(s)
114 #error COFF, a.out, b.out, and ELF are the only supported formats.
115 #endif /* ! OBJ_ELF */
116 #endif /* ! OBJ_COFF */
117 #endif /* ! OBJ_A/BOUT */
119 extern char *input_line_pointer;
121 /* Local i80960 routines. */
125 /* See md_parse_option() for meanings of these options. */
126 static char norelax; /* True if -norelax switch seen. */
127 static char instrument_branches; /* True if -b switch seen. */
129 /* Characters that always start a comment.
130 If the pre-processor is disabled, these aren't very useful. */
131 const char comment_chars[] = "#";
133 /* Characters that only start a comment at the beginning of
134 a line. If the line seems to have the form '# 123 filename'
135 .line and .file directives will appear in the pre-processed output.
137 Note that input_file.c hand checks for '#' at the beginning of the
138 first line of the input file. This is because the compiler outputs
139 #NO_APP at the beginning of its output. */
141 /* Also note that comments started like this one will always work. */
143 const char line_comment_chars[] = "#";
144 const char line_separator_chars[] = ";";
146 /* Chars that can be used to separate mant from exp in floating point nums. */
147 const char EXP_CHARS[] = "eE";
149 /* Chars that mean this number is a floating point constant,
150 as in 0f12.456 or 0d1.2345e12. */
151 const char FLT_CHARS[] = "fFdDtT";
153 /* Table used by base assembler to relax addresses based on varying length
154 instructions. The fields are:
155 1) most positive reach of this state,
156 2) most negative reach of this state,
157 3) how many bytes this mode will add to the size of the current frag
158 4) which index into the table to try if we can't fit into this one.
160 For i80960, the only application is the (de-)optimization of cobr
161 instructions into separate compare and branch instructions when a 13-bit
162 displacement won't hack it. */
163 const relax_typeS md_relax_table[] =
165 {0, 0, 0, 0}, /* State 0 => no more relaxation possible. */
166 {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr). */
167 {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl). */
170 /* These are the machine dependent pseudo-ops.
172 This table describes all the machine specific pseudo-ops the assembler
173 has to support. The fields are:
174 pseudo-op name without dot
175 function to call to execute this pseudo-op
176 integer arg to pass to the function. */
180 /* Macros to extract info from an 'expressionS' structure 'e'. */
181 #define adds(e) e.X_add_symbol
182 #define offs(e) e.X_add_number
184 /* Branch-prediction bits for CTRL/COBR format opcodes. */
185 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit. */
186 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch. */
187 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch. */
189 /* Some instruction opcodes that we need explicitly. */
190 #define BE 0x12000000
191 #define BG 0x11000000
192 #define BGE 0x13000000
193 #define BL 0x14000000
194 #define BLE 0x16000000
195 #define BNE 0x15000000
196 #define BNO 0x10000000
197 #define BO 0x17000000
198 #define CHKBIT 0x5a002700
199 #define CMPI 0x5a002080
200 #define CMPO 0x5a002000
203 #define BAL 0x0b000000
204 #define CALL 0x09000000
205 #define CALLS 0x66003800
206 #define RET 0x0a000000
208 /* These masks are used to build up a set of MEMB mode bits. */
211 #define MEMB_BIT 0x1000
214 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
216 #define MEMA_ABASE 0x2000
218 /* Info from which a MEMA or MEMB format instruction can be generated. */
221 /* (First) 32 bits of instruction. */
223 /* 0-(none), 12- or, 32-bit displacement needed. */
225 /* The expression in the source instruction from which the
226 displacement should be determined. */
231 /* The two pieces of info we need to generate a register operand. */
234 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg. */
235 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0). */
236 int n; /* Register number or literal value. */
239 /* Number and assembler mnemonic for all registers that can appear in
281 /* Numbers for special-function registers are for assembler internal
282 use only: they are scaled back to range [0-31] for binary output. */
318 /* Numbers for floating point registers are for assembler internal
319 use only: they are scaled back to [0-3] for binary output. */
327 { NULL, 0 }, /* END OF LIST */
330 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
331 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
332 #define IS_FP_REG(n) ((n) >= FP0)
334 /* Number and assembler mnemonic for all registers that can appear as
335 'abase' (indirect addressing) registers. */
377 /* For assembler internal use only: this number never appears in binary
381 { NULL, 0 }, /* END OF LIST */
385 static struct hash_control *op_hash; /* Opcode mnemonics. */
386 static struct hash_control *reg_hash; /* Register name hash table. */
387 static struct hash_control *areg_hash; /* Abase register hash table. */
389 /* Architecture for which we are assembling. */
390 #define ARCH_ANY 0 /* Default: no architecture checking done. */
397 int architecture = ARCH_ANY; /* Architecture requested on invocation line. */
398 int iclasses_seen; /* OR of instruction classes (I_* constants)
399 for which we've actually assembled
402 /* BRANCH-PREDICTION INSTRUMENTATION
404 The following supports generation of branch-prediction instrumentation
405 (turned on by -b switch). The instrumentation collects counts
406 of branches taken/not-taken for later input to a utility that will
407 set the branch prediction bits of the instructions in accordance with
408 the behavior observed. (Note that the KX series does not have
411 The instrumentation consists of:
413 (1) before and after each conditional branch, a call to an external
414 routine that increments and steps over an inline counter. The
415 counter itself, initialized to 0, immediately follows the call
416 instruction. For each branch, the counter following the branch
417 is the number of times the branch was not taken, and the difference
418 between the counters is the number of times it was taken. An
419 example of an instrumented conditional branch:
427 (2) a table of pointers to the instrumented branches, so that an
428 external postprocessing routine can locate all of the counters.
429 the table begins with a 2-word header: a pointer to the next in
430 a linked list of such tables (initialized to 0); and a count
431 of the number of entries in the table (exclusive of the header.
433 Note that input source code is expected to already contain calls
434 an external routine that will link the branch local table into a
435 list of such tables. */
437 /* Number of branches instrumented so far. Also used to generate
438 unique local labels for each instrumented branch. */
441 #define BR_LABEL_BASE "LBRANCH"
442 /* Basename of local labels on instrumented branches, to avoid
443 conflict with compiler- generated local labels. */
445 #define BR_CNT_FUNC "__inc_branch"
446 /* Name of the external routine that will increment (and step over) an
449 #define BR_TAB_NAME "__BRANCH_TABLE__"
450 /* Name of the table of pointers to branches. A local (i.e.,
451 non-external) symbol. */
453 static void ctrl_fmt (char *, long, int);
459 int i; /* Loop counter. */
460 const struct i960_opcode *oP; /* Pointer into opcode table. */
461 const char *retval; /* Value returned by hash functions. */
463 op_hash = hash_new ();
464 reg_hash = hash_new ();
465 areg_hash = hash_new ();
467 /* For some reason, the base assembler uses an empty string for "no
468 error message", instead of a NULL pointer. */
471 for (oP = i960_opcodes; oP->name && !retval; oP++)
472 retval = hash_insert (op_hash, oP->name, (void *) oP);
474 for (i = 0; regnames[i].reg_name && !retval; i++)
475 retval = hash_insert (reg_hash, regnames[i].reg_name,
476 (char *) ®names[i].reg_num);
478 for (i = 0; aregs[i].areg_name && !retval; i++)
479 retval = hash_insert (areg_hash, aregs[i].areg_name,
480 (char *) &aregs[i].areg_num);
483 as_fatal (_("Hashing returned \"%s\"."), retval);
486 /* parse_expr: parse an expression
488 Use base assembler's expression parser to parse an expression.
489 It, unfortunately, runs off a global which we have to save/restore
490 in order to make it work for us.
492 An empty expression string is treated as an absolute 0.
494 Sets O_illegal regardless of expression evaluation if entire input
495 string is not consumed in the evaluation -- tolerate no dangling junk! */
498 parse_expr (char *textP, /* Text of expression to be parsed. */
499 expressionS *expP) /* Where to put the results of parsing. */
501 char *save_in; /* Save global here. */
508 /* Treat empty string as absolute 0. */
509 expP->X_add_symbol = expP->X_op_symbol = NULL;
510 expP->X_add_number = 0;
511 expP->X_op = O_constant;
515 save_in = input_line_pointer; /* Save global. */
516 input_line_pointer = textP; /* Make parser work for us. */
518 (void) expression (expP);
519 if ((size_t) (input_line_pointer - textP) != strlen (textP))
520 /* Did not consume all of the input. */
521 expP->X_op = O_illegal;
523 symP = expP->X_add_symbol;
524 if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
525 /* Register name in an expression. */
526 /* FIXME: this isn't much of a check any more. */
527 expP->X_op = O_illegal;
529 input_line_pointer = save_in; /* Restore global. */
533 /* emit: output instruction binary
535 Output instruction binary, in target byte order, 4 bytes at a time.
536 Return pointer to where it was placed. */
539 emit (long instr) /* Word to be output, host byte order. */
541 char *toP; /* Where to output it. */
543 toP = frag_more (4); /* Allocate storage. */
544 md_number_to_chars (toP, instr, 4); /* Convert to target byte order. */
548 /* get_cdisp: handle displacement for a COBR or CTRL instruction.
550 Parse displacement for a COBR or CTRL instruction.
552 If successful, output the instruction opcode and set up for it,
553 depending on the arg 'var_frag', either:
554 o an address fixup to be done when all symbol values are known, or
555 o a varying length code fragment, with address fixup info. This
556 will be done for cobr instructions that may have to be relaxed
557 in to compare/branch instructions (8 bytes) if the final
558 address displacement is greater than 13 bits. */
561 get_cdisp (char *dispP, /* Displacement as specified in source instruction. */
562 char *ifmtP, /* "COBR" or "CTRL" (for use in error message). */
563 long instr, /* Instruction needing the displacement. */
564 int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL). */
565 int var_frag,/* 1 if varying length code fragment should be emitted;
566 0 if an address fix should be emitted. */
567 int callj) /* 1 if callj relocation should be done; else 0. */
569 expressionS e; /* Parsed expression. */
570 fixS *fixP; /* Structure describing needed address fix. */
571 char *outP; /* Where instruction binary is output to. */
575 parse_expr (dispP, &e);
579 as_bad (_("expression syntax error"));
582 if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
583 || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
587 outP = frag_more (8); /* Allocate worst-case storage. */
588 md_number_to_chars (outP, instr, 4);
589 frag_variant (rs_machine_dependent, 4, 4, 1,
590 adds (e), offs (e), outP);
594 /* Set up a new fix structure, so address can be updated
595 when all symbol values are known. */
597 fixP = fix_new (frag_now,
598 outP - frag_now->fr_literal,
605 fixP->fx_tcbit = callj;
607 /* We want to modify a bit field when the address is
608 known. But we don't need all the garbage in the
609 bit_fix structure. So we're going to lie and store
610 the number of bits affected instead of a pointer. */
611 fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits;
615 as_bad (_("attempt to branch into different segment"));
619 as_bad (_("target of %s instruction must be a label"), ifmtP);
625 md_chars_to_number (char * val, /* Value in target byte order. */
626 int n) /* Number of bytes in the input. */
630 for (retval = 0; n--;)
633 retval |= (unsigned char) val[n];
638 /* mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
640 There are 2 possible MEMA formats:
642 - displacement + abase
644 They are distinguished by the setting of the MEMA_ABASE bit. */
647 mema_to_memb (char * opcodeP) /* Where to find the opcode, in target byte order. */
649 long opcode; /* Opcode in host byte order. */
650 long mode; /* Mode bits for MEMB instruction. */
652 opcode = md_chars_to_number (opcodeP, 4);
653 know (!(opcode & MEMB_BIT));
655 mode = MEMB_BIT | D_BIT;
656 if (opcode & MEMA_ABASE)
659 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits. */
660 opcode |= mode; /* Set MEMB mode bits. */
662 md_number_to_chars (opcodeP, opcode, 4);
667 Return TRUE iff the target architecture supports the specified
668 special-function register (sfr). */
671 targ_has_sfr (int n) /* Number (0-31) of sfr. */
673 switch (architecture)
681 return ((0 <= n) && (n <= 4));
684 return ((0 <= n) && (n <= 2));
688 /* Look up a (suspected) register name in the register table and return the
689 associated register number (or -1 if not found). */
692 get_regnum (char *regname) /* Suspected register name. */
696 rP = (int *) hash_find (reg_hash, regname);
697 return (rP == NULL) ? -1 : *rP;
700 /* syntax: Issue a syntax error. */
705 as_bad (_("syntax error"));
708 /* parse_regop: parse a register operand.
710 In case of illegal operand, issue a message and return some valid
711 information so instruction processing can continue. */
714 parse_regop (struct regop *regopP, /* Where to put description of register operand. */
715 char *optext, /* Text of operand. */
716 char opdesc) /* Descriptor byte: what's legal for this operand. */
718 int n; /* Register number. */
719 expressionS e; /* Parsed expression. */
721 /* See if operand is a register. */
722 n = get_regnum (optext);
727 /* Global or local register. */
728 if (!REG_ALIGN (opdesc, n))
729 as_bad (_("unaligned register"));
736 else if (IS_FP_REG (n) && FP_OK (opdesc))
738 /* Floating point register, and it's allowed. */
744 else if (IS_SF_REG (n) && SFR_OK (opdesc))
746 /* Special-function register, and it's allowed. */
750 if (!targ_has_sfr (regopP->n))
751 as_bad (_("no such sfr in this architecture"));
756 else if (LIT_OK (opdesc))
758 /* How about a literal? */
763 /* Floating point literal acceptable. */
764 /* Skip over 0f, 0d, or 0e prefix. */
765 if ((optext[0] == '0')
766 && (optext[1] >= 'd')
767 && (optext[1] <= 'f'))
770 if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
776 if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
784 /* Fixed point literal acceptable. */
785 parse_expr (optext, &e);
786 if (e.X_op != O_constant
787 || (offs (e) < 0) || (offs (e) > 31))
789 as_bad (_("illegal literal"));
792 regopP->n = offs (e);
797 /* Nothing worked. */
799 regopP->mode = 0; /* Register r0 is always a good one. */
804 /* get_ispec: parse a memory operand for an index specification
806 Here, an "index specification" is taken to be anything surrounded
807 by square brackets and NOT followed by anything else.
809 If it's found, detach it from the input string, remove the surrounding
810 square brackets, and return a pointer to it. Otherwise, return NULL. */
813 get_ispec (char *textP) /* Pointer to memory operand from source instruction, no white space. */
816 /* Points to start of index specification. */
818 /* Points to end of index specification. */
821 /* Find opening square bracket, if any. */
822 start = strchr (textP, '[');
826 /* Eliminate '[', detach from rest of operand. */
829 end = strchr (start, ']');
832 as_bad (_("unmatched '['"));
835 /* Eliminate ']' and make sure it was the last thing
838 if (*(end + 1) != '\0')
839 as_bad (_("garbage after index spec ignored"));
845 /* parse_memop: parse a memory operand
847 This routine is based on the observation that the 4 mode bits of the
848 MEMB format, taken individually, have fairly consistent meaning:
850 M3 (bit 13): 1 if displacement is present (D_BIT)
851 M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
852 M1 (bit 11): 1 if index is present (I_BIT)
853 M0 (bit 10): 1 if abase is present (A_BIT)
855 So we parse the memory operand and set bits in the mode as we find
856 things. Then at the end, if we go to MEMB format, we need only set
857 the MEMB bit (M2) and our mode is built for us.
859 Unfortunately, I said "fairly consistent". The exceptions:
862 0100 Would seem illegal, but means "abase-only".
864 0101 Would seem to mean "abase-only" -- it means IP-relative.
865 Must be converted to 0100.
867 0110 Would seem to mean "index-only", but is reserved.
868 We turn on the D bit and provide a 0 displacement.
870 The other thing to observe is that we parse from the right, peeling
871 things * off as we go: first any index spec, then any abase, then
875 parse_memop (memS *memP, /* Where to put the results. */
876 char *argP, /* Text of the operand to be parsed. */
877 int optype) /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16. */
879 char *indexP; /* Pointer to index specification with "[]" removed. */
880 char *p; /* Temp char pointer. */
881 char iprel_flag; /* True if this is an IP-relative operand. */
882 int regnum; /* Register number. */
883 /* Scale factor: 1,2,4,8, or 16. Later converted to internal format
884 (0,1,2,3,4 respectively). */
886 int mode; /* MEMB mode bits. */
887 int *intP; /* Pointer to register number. */
889 /* The following table contains the default scale factors for each
890 type of memory instruction. It is accessed using (optype-MEM1)
891 as an index -- thus it assumes the 'optype' constants are
892 assigned consecutive values, in the order they appear in this
894 static const int def_scale[] =
900 -1, /* MEM12 -- no valid default */
904 iprel_flag = mode = 0;
906 /* Any index present? */
907 indexP = get_ispec (argP);
910 p = strchr (indexP, '*');
913 /* No explicit scale -- use default for this instruction
914 type and assembler mode. */
918 /* GNU960 compatibility */
919 scale = def_scale[optype - MEM1];
923 *p++ = '\0'; /* Eliminate '*' */
925 /* Now indexP->a '\0'-terminated register name,
926 and p->a scale factor. */
928 if (!strcmp (p, "16"))
930 else if (strchr ("1248", *p) && (p[1] == '\0'))
936 regnum = get_regnum (indexP); /* Get index reg. # */
937 if (!IS_RG_REG (regnum))
939 as_bad (_("invalid index register"));
943 /* Convert scale to its binary encoding. */
962 as_bad (_("invalid scale factor"));
966 memP->opcode |= scale | regnum; /* Set index bits in opcode. */
967 mode |= I_BIT; /* Found a valid index spec. */
970 /* Any abase (Register Indirect) specification present? */
971 if ((p = strrchr (argP, '(')) != NULL)
973 /* "(" is there -- does it start a legal abase spec? If not, it
974 could be part of a displacement expression. */
975 intP = (int *) hash_find (areg_hash, p);
978 /* Got an abase here. */
980 *p = '\0'; /* Discard register spec. */
982 /* We have to specialcase ip-rel mode. */
986 memP->opcode |= regnum << 14;
992 /* Any expression present? */
997 /* Special-case ip-relative addressing. */
1004 memP->opcode |= 5 << 10; /* IP-relative mode. */
1010 /* Handle all other modes. */
1014 /* Go with MEMA instruction format for now (grow to MEMB later
1015 if 12 bits is not enough for the displacement). MEMA format
1016 has a single mode bit: set it to indicate that abase is
1018 memP->opcode |= MEMA_ABASE;
1023 /* Go with MEMA instruction format for now (grow to MEMB later
1024 if 12 bits is not enough for the displacement). */
1029 /* For some reason, the bit string for this mode is not
1030 consistent: it should be 0 (exclusive of the MEMB bit), so we
1031 set it "by hand" here. */
1032 memP->opcode |= MEMB_BIT;
1036 /* set MEMB bit in mode, and OR in mode bits. */
1037 memP->opcode |= mode | MEMB_BIT;
1041 /* Treat missing displacement as displacement of 0. */
1043 /* Fall into next case. */
1044 case D_BIT | A_BIT | I_BIT:
1046 /* Set MEMB bit in mode, and OR in mode bits. */
1047 memP->opcode |= mode | MEMB_BIT;
1057 /* Generate a MEMA- or MEMB-format instruction. */
1060 mem_fmt (char *args[], /* args[0]->opcode mnemonic, args[1-3]->operands. */
1061 struct i960_opcode *oP,/* Pointer to description of instruction. */
1062 int callx) /* Is this a callx opcode. */
1064 int i; /* Loop counter. */
1065 struct regop regop; /* Description of register operand. */
1066 char opdesc; /* Operand descriptor byte. */
1067 memS instr; /* Description of binary to be output. */
1068 char *outP; /* Where the binary was output to. */
1069 expressionS exp; /* Parsed expression. */
1070 /* ->description of deferred address fixup. */
1074 /* COFF support isn't in place yet for callx relaxing. */
1078 memset (&instr, '\0', sizeof (memS));
1079 instr.opcode = oP->opcode;
1081 /* Process operands. */
1082 for (i = 1; i <= oP->num_ops; i++)
1084 opdesc = oP->operand[i - 1];
1087 parse_memop (&instr, args[i], oP->format);
1090 parse_regop (®op, args[i], opdesc);
1091 instr.opcode |= regop.n << 19;
1095 /* Parse the displacement; this must be done before emitting the
1096 opcode, in case it is an expression using `.'. */
1097 parse_expr (instr.e, &exp);
1099 /* Output opcode. */
1100 outP = emit (instr.opcode);
1102 if (instr.disp == 0)
1105 /* Process the displacement. */
1109 as_bad (_("expression syntax error"));
1113 if (instr.disp == 32)
1114 (void) emit (offs (exp)); /* Output displacement. */
1117 /* 12-bit displacement. */
1118 if (offs (exp) & ~0xfff)
1120 /* Won't fit in 12 bits: convert already-output
1121 instruction to MEMB format, output
1123 mema_to_memb (outP);
1124 (void) emit (offs (exp));
1128 /* WILL fit in 12 bits: OR into opcode and
1129 overwrite the binary we already put out. */
1130 instr.opcode |= offs (exp);
1131 md_number_to_chars (outP, instr.opcode, 4);
1137 if (instr.disp == 12)
1138 /* Displacement is dependent on a symbol, whose value
1139 may change at link time. We HAVE to reserve 32 bits.
1140 Convert already-output opcode to MEMB format. */
1141 mema_to_memb (outP);
1143 /* Output 0 displacement and set up address fixup for when
1144 this symbol's value becomes known. */
1145 outP = emit ((long) 0);
1146 fixP = fix_new_exp (frag_now,
1147 outP - frag_now->fr_literal,
1148 4, &exp, 0, NO_RELOC);
1149 /* Steve's linker relaxing hack. Mark this 32-bit relocation as
1150 being in the instruction stream, specifically as part of a callx
1152 fixP->fx_bsr = callx;
1159 Return TRUE iff the target architecture supports the indicated
1160 class of instructions. */
1163 targ_has_iclass (int ic) /* Instruction class; one of:
1164 I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2. */
1166 iclasses_seen |= ic;
1168 switch (architecture)
1171 return ic & (I_BASE | I_KX);
1173 return ic & (I_BASE | I_KX | I_FP | I_DEC);
1175 return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
1177 return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
1179 return ic & (I_BASE | I_CX2 | I_JX);
1181 return ic & (I_BASE | I_CX2 | I_JX | I_HX);
1183 if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
1184 && (iclasses_seen & (I_CX | I_CX2)))
1186 as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
1187 iclasses_seen &= ~ic;
1194 Determine if a "shlo" instruction can be used to implement a "ldconst".
1195 This means that some number X < 32 can be shifted left to produce the
1196 constant of interest.
1198 Return the shift count, or 0 if we can't do it.
1199 Caller calculates X by shifting original constant right 'shift' places. */
1202 shift_ok (int n) /* The constant of interest. */
1204 int shift; /* The shift count. */
1207 /* Can't do it for negative numbers. */
1210 /* Shift 'n' right until a 1 is about to be lost. */
1211 for (shift = 0; (n & 1) == 0; shift++)
1221 Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1224 Assumes the input consists of:
1225 arg[0] opcode mnemonic ('ldconst')
1226 arg[1] first operand (constant)
1227 arg[2] name of register to be loaded
1229 Replaces opcode and/or operands as appropriate.
1231 Returns the new number of arguments, or -1 on failure. */
1234 parse_ldconst (char *arg[]) /* See above. */
1236 int n; /* Constant to be loaded. */
1237 int shift; /* Shift count for "shlo" instruction. */
1238 static char buf[5]; /* Literal for first operand. */
1239 static char buf2[5]; /* Literal for second operand. */
1240 expressionS e; /* Parsed expression. */
1242 arg[3] = NULL; /* So we can tell at the end if it got used or not. */
1244 parse_expr (arg[1], &e);
1248 /* We're dependent on one or more symbols -- use "lda". */
1253 /* Try the following mappings:
1254 ldconst 0,<reg> -> mov 0,<reg>
1255 ldconst 31,<reg> -> mov 31,<reg>
1256 ldconst 32,<reg> -> addo 1,31,<reg>
1257 ldconst 62,<reg> -> addo 31,31,<reg>
1258 ldconst 64,<reg> -> shlo 8,3,<reg>
1259 ldconst -1,<reg> -> subo 1,0,<reg>
1260 ldconst -31,<reg> -> subo 31,0,<reg>
1262 Anything else becomes:
1265 if ((0 <= n) && (n <= 31))
1267 else if ((-31 <= n) && (n <= -1))
1271 sprintf (buf, "%d", -n);
1275 else if ((32 <= n) && (n <= 62))
1280 sprintf (buf, "%d", n - 31);
1283 else if ((shift = shift_ok (n)) != 0)
1287 sprintf (buf, "%d", shift);
1289 sprintf (buf2, "%d", n >> shift);
1297 as_bad (_("invalid constant"));
1301 return (arg[3] == 0) ? 2 : 3;
1304 /* reg_fmt: generate a REG-format instruction. */
1307 reg_fmt (char *args[], /* args[0]->opcode mnemonic, args[1-3]->operands. */
1308 struct i960_opcode *oP)/* Pointer to description of instruction. */
1310 long instr; /* Binary to be output. */
1311 struct regop regop; /* Description of register operand. */
1312 int n_ops; /* Number of operands. */
1315 n_ops = oP->num_ops;
1319 parse_regop (®op, args[1], oP->operand[0]);
1321 if ((n_ops == 1) && !(instr & M3))
1323 /* 1-operand instruction in which the dst field should
1324 be used (instead of src1). */
1327 regop.mode = regop.special;
1333 /* regop.n goes in bit 0, needs no shifting. */
1335 regop.special <<= 5;
1337 instr |= regop.n | regop.mode | regop.special;
1342 parse_regop (®op, args[2], oP->operand[1]);
1344 if ((n_ops == 2) && !(instr & M3))
1346 /* 2-operand instruction in which the dst field should
1347 be used instead of src2). */
1350 regop.mode = regop.special;
1358 regop.special <<= 6;
1360 instr |= regop.n | regop.mode | regop.special;
1364 parse_regop (®op, args[3], oP->operand[2]);
1366 regop.mode = regop.special;
1367 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
1372 /* get_args: break individual arguments out of comma-separated list
1375 - all comments and labels have been removed
1376 - all strings of whitespace have been collapsed to a single blank.
1377 - all character constants ('x') have been replaced with decimal
1380 args[0] is untouched. args[1] points to first operand, etc. All args:
1381 - are NULL-terminated
1382 - contain no whitespace
1385 Number of operands (0,1,2, or 3) or -1 on error. */
1388 get_args (char *p, /* Pointer to comma-separated operands; Mucked by us. */
1389 char *args[]) /* Output arg: pointers to operands placed in args[1-3].
1390 Must accommodate 4 entries (args[0-3]). */
1393 int n; /* Number of operands. */
1396 /* Skip lead white space. */
1406 /* Squeze blanks out by moving non-blanks toward start of string.
1407 Isolate operands, whenever comma is found. */
1412 && (! ISALNUM (p[1])
1413 || ! ISALNUM (p[-1])))
1417 /* Start of operand. */
1420 as_bad (_("too many operands"));
1423 *to++ = '\0'; /* Terminate argument. */
1424 args[++n] = to; /* Start next argument. */
1434 /* i_scan: perform lexical scan of ascii assembler instruction.
1437 - input string is an i80960 instruction (not a pseudo-op)
1438 - all comments and labels have been removed
1439 - all strings of whitespace have been collapsed to a single blank.
1442 args[0] points to opcode, other entries point to operands. All strings:
1443 - are NULL-terminated
1444 - contain no whitespace
1445 - have character constants ('x') replaced with a decimal number
1448 Number of operands (0,1,2, or 3) or -1 on error. */
1451 i_scan (char *iP, /* Pointer to ascii instruction; Mucked by us. */
1452 char *args[]) /* Output arg: pointers to opcode and operands placed here.
1453 Must accommodate 4 entries. */
1455 /* Isolate opcode. */
1460 for (; *iP != ' '; iP++)
1464 /* There are no operands. */
1467 /* We never moved: there was no opcode either! */
1468 as_bad (_("missing opcode"));
1475 return (get_args (iP, args));
1481 /* Emit call to "increment" routine. */
1482 ctrl_fmt (BR_CNT_FUNC, CALL, 1);
1483 /* Emit inline counter to be incremented. */
1490 static char buf[20];
1492 sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1497 ctrl_fmt (char *targP, /* Pointer to text of lone operand (if any). */
1498 long opcode, /* Template of instruction. */
1499 int num_ops) /* Number of operands. */
1501 int instrument; /* TRUE iff we should add instrumentation to track
1502 how often the branch is taken. */
1505 emit (opcode); /* Output opcode. */
1508 instrument = instrument_branches && (opcode != CALL)
1509 && (opcode != B) && (opcode != RET) && (opcode != BAL);
1514 colon (brlab_next ());
1517 /* The operand MUST be an ip-relative displacement. Parse it
1518 and set up address fix for the instruction we just output. */
1519 get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1527 cobr_fmt (/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1529 /* Opcode, with branch-prediction bits already set if necessary. */
1531 /* Pointer to description of instruction. */
1532 struct i960_opcode *oP)
1534 long instr; /* 32-bit instruction. */
1535 struct regop regop; /* Description of register operand. */
1536 int n; /* Number of operands. */
1537 int var_frag; /* 1 if varying length code fragment should
1538 be emitted; 0 if an address fix
1539 should be emitted. */
1546 /* First operand (if any) of a COBR is always a register
1547 operand. Parse it. */
1548 parse_regop (®op, arg[1], oP->operand[0]);
1549 instr |= (regop.n << 19) | (regop.mode << 13);
1554 /* Second operand (if any) of a COBR is always a register
1555 operand. Parse it. */
1556 parse_regop (®op, arg[2], oP->operand[1]);
1557 instr |= (regop.n << 14) | regop.special;
1564 if (instrument_branches)
1567 colon (brlab_next ());
1570 /* A third operand to a COBR is always a displacement. Parse
1571 it; if it's relaxable (a cobr "j" directive, or any cobr
1572 other than bbs/bbc when the "-norelax" option is not in use)
1573 set up a variable code fragment; otherwise set up an address
1575 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1576 get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1578 if (instrument_branches)
1583 /* Assumptions about the passed-in text:
1584 - all comments, labels removed
1585 - text is an instruction
1586 - all white space compressed to single blanks
1587 - all character constants have been replaced with decimal. */
1590 md_assemble (char *textP)
1592 /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
1593 mnemonic arg[1-3]->operands, with char constants replaced by
1596 /* Number of instruction operands. */
1598 /* Pointer to instruction description. */
1599 struct i960_opcode *oP;
1600 /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
1603 /* Setting of branch-prediction bit(s) to be OR'd into instruction
1604 opcode of CTRL/COBR format instructions. */
1606 /* Offset of last character in opcode mnemonic. */
1608 const char *bp_error_msg = _("branch prediction invalid on this opcode");
1610 /* Parse instruction into opcode and operands. */
1611 memset (args, '\0', sizeof (args));
1613 n_ops = i_scan (textP, args);
1616 return; /* Error message already issued. */
1618 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction. */
1619 if (!strcmp (args[0], "ldconst"))
1621 n_ops = parse_ldconst (args);
1626 /* Check for branch-prediction suffix on opcode mnemonic, strip it off. */
1627 n = strlen (args[0]) - 1;
1631 if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
1633 /* We could check here to see if the target architecture
1634 supports branch prediction, but why bother? The bit will
1635 just be ignored by processors that don't use it. */
1637 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
1638 args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
1641 /* Look up opcode mnemonic in table and check number of operands.
1642 Check that opcode is legal for the target architecture. If all
1643 looks good, assemble instruction. */
1644 oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
1645 if (!oP || !targ_has_iclass (oP->iclass))
1646 as_bad (_("invalid opcode, \"%s\"."), args[0]);
1647 else if (n_ops != oP->num_ops)
1648 as_bad (_("improper number of operands. expecting %d, got %d"),
1649 oP->num_ops, n_ops);
1656 ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
1657 if (oP->format == FBRA)
1658 /* Now generate a 'bno' to same arg */
1659 ctrl_fmt (args[1], BNO | bp_bits, 1);
1663 cobr_fmt (args, oP->opcode | bp_bits, oP);
1667 as_warn ("%s", bp_error_msg);
1671 if (args[0][0] == 'c' && args[0][1] == 'a')
1674 as_warn ("%s", bp_error_msg);
1675 mem_fmt (args, oP, 1);
1684 as_warn ("%s", bp_error_msg);
1685 mem_fmt (args, oP, 0);
1689 as_warn ("%s", bp_error_msg);
1690 /* Output opcode & set up "fixup" (relocation); flag
1691 relocation as 'callj' type. */
1692 know (oP->num_ops == 1);
1693 get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
1696 BAD_CASE (oP->format);
1703 md_number_to_chars (char *buf,
1707 number_to_chars_littleendian (buf, value, n);
1711 md_atof (int type, char *litP, int *sizeP)
1713 return ieee_md_atof (type, litP, sizeP, FALSE);
1717 md_number_to_imm (char *buf, long val, int n)
1719 md_number_to_chars (buf, val, n);
1723 md_number_to_field (char *instrP, /* Pointer to instruction to be fixed. */
1724 long val, /* Address fixup value. */
1725 bit_fixS *bfixP) /* Description of bit field to be fixed up. */
1727 int numbits; /* Length of bit field to be fixed. */
1728 long instr; /* 32-bit instruction to be fixed-up. */
1729 long sign; /* 0 or -1, according to sign bit of 'val'. */
1731 /* Convert instruction back to host byte order. */
1732 instr = md_chars_to_number (instrP, 4);
1734 /* Surprise! -- we stored the number of bits to be modified rather
1735 than a pointer to a structure. */
1736 numbits = (int) (size_t) bfixP;
1738 /* This is a no-op, stuck here by reloc_callj(). */
1741 know ((numbits == 13) || (numbits == 24));
1743 /* Propagate sign bit of 'val' for the given number of bits. Result
1744 should be all 0 or all 1. */
1745 sign = val >> ((int) numbits - 1);
1746 if (((val < 0) && (sign != -1))
1747 || ((val > 0) && (sign != 0)))
1748 as_bad (_("Fixup of %ld too large for field width of %d"),
1752 /* Put bit field into instruction and write back in target
1754 val &= ~(-1 << (int) numbits); /* Clear unused sign bits. */
1756 md_number_to_chars (instrP, instr, 4);
1762 Invocation line includes a switch not recognized by the base assembler.
1763 See if it's a processor-specific option. For the 960, these are:
1766 Conditional branch instructions that require displacements
1767 greater than 13 bits (or that have external targets) should
1768 generate errors. The default is to replace each such
1769 instruction with the corresponding compare (or chkbit) and
1770 branch instructions. Note that the Intel "j" cobr directives
1771 are ALWAYS "de-optimized" in this way when necessary,
1772 regardless of the setting of this option.
1775 Add code to collect information about branches taken, for
1776 later optimization of branch prediction bits by a separate
1777 tool. COBR and CNTL format instructions have branch
1778 prediction bits (in the CX architecture); if "BR" represents
1779 an instruction in one of these classes, the following rep-
1780 resents the code generated by the assembler:
1782 call <increment routine>
1783 .word 0 # pre-counter
1785 call <increment routine>
1786 .word 0 # post-counter
1788 A table of all such "Labels" is also generated.
1790 -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
1791 Select the 80960 architecture. Instructions or features not
1792 supported by the selected architecture cause fatal errors.
1793 The default is to generate code for any instruction or feature
1794 that is supported by SOME version of the 960 (even if this
1795 means mixing architectures!). */
1797 const char *md_shortopts = "A:b";
1798 struct option md_longopts[] =
1800 #define OPTION_LINKRELAX (OPTION_MD_BASE)
1801 {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
1802 {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
1803 #define OPTION_NORELAX (OPTION_MD_BASE + 1)
1804 {"norelax", no_argument, NULL, OPTION_NORELAX},
1805 {"no-relax", no_argument, NULL, OPTION_NORELAX},
1806 {NULL, no_argument, NULL, 0}
1808 size_t md_longopts_size = sizeof (md_longopts);
1815 static const struct tabentry arch_tab[] =
1819 {"SA", ARCH_KA}, /* Synonym for KA. */
1820 {"SB", ARCH_KB}, /* Synonym for KB. */
1821 {"KC", ARCH_MC}, /* Synonym for MC. */
1830 md_parse_option (int c, char *arg)
1834 case OPTION_LINKRELAX:
1836 flag_keep_locals = 1;
1839 case OPTION_NORELAX:
1844 instrument_branches = 1;
1849 const struct tabentry *tp;
1852 for (tp = arch_tab; tp->flag != NULL; tp++)
1853 if (!strcmp (p, tp->flag))
1856 if (tp->flag == NULL)
1858 as_bad (_("invalid architecture %s"), p);
1862 architecture = tp->arch;
1874 md_show_usage (FILE *stream)
1878 fprintf (stream, _("I960 options:\n"));
1879 for (i = 0; arch_tab[i].flag; i++)
1880 fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
1881 fprintf (stream, _("\n\
1882 specify variant of 960 architecture\n\
1883 -b add code to collect statistics about branches taken\n\
1884 -link-relax preserve individual alignment directives so linker\n\
1885 can do relaxing (b.out format only)\n\
1886 -no-relax don't alter compare-and-branch instructions for\n\
1887 long displacements\n"));
1891 Replace cobr instruction in a code fragment with equivalent branch and
1892 compare instructions, so it can reach beyond a 13-bit displacement.
1893 Set up an address fix/relocation for the new branch instruction. */
1895 /* This "conditional jump" table maps cobr instructions into
1896 equivalent compare and branch opcodes. */
1906 { /* COBR OPCODE: */
1907 { CHKBIT, BNO }, /* 0x30 - bbc */
1908 { CMPO, BG }, /* 0x31 - cmpobg */
1909 { CMPO, BE }, /* 0x32 - cmpobe */
1910 { CMPO, BGE }, /* 0x33 - cmpobge */
1911 { CMPO, BL }, /* 0x34 - cmpobl */
1912 { CMPO, BNE }, /* 0x35 - cmpobne */
1913 { CMPO, BLE }, /* 0x36 - cmpoble */
1914 { CHKBIT, BO }, /* 0x37 - bbs */
1915 { CMPI, BNO }, /* 0x38 - cmpibno */
1916 { CMPI, BG }, /* 0x39 - cmpibg */
1917 { CMPI, BE }, /* 0x3a - cmpibe */
1918 { CMPI, BGE }, /* 0x3b - cmpibge */
1919 { CMPI, BL }, /* 0x3c - cmpibl */
1920 { CMPI, BNE }, /* 0x3d - cmpibne */
1921 { CMPI, BLE }, /* 0x3e - cmpible */
1922 { CMPI, BO }, /* 0x3f - cmpibo */
1926 relax_cobr (fragS *fragP) /* fragP->fr_opcode is assumed to point to
1927 the cobr instruction, which comes at the
1928 end of the code fragment. */
1930 int opcode, src1, src2, m1, s2;
1931 /* Bit fields from cobr instruction. */
1932 long bp_bits; /* Branch prediction bits from cobr instruction. */
1933 long instr; /* A single i960 instruction. */
1934 /* ->instruction to be replaced. */
1936 fixS *fixP; /* Relocation that can be done at assembly time. */
1938 /* Pick up & parse cobr instruction. */
1939 iP = fragP->fr_opcode;
1940 instr = md_chars_to_number (iP, 4);
1941 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index. */
1942 src1 = (instr >> 19) & 0x1f;
1943 m1 = (instr >> 13) & 1;
1945 src2 = (instr >> 14) & 0x1f;
1946 bp_bits = instr & BP_MASK;
1948 /* Generate and output compare instruction. */
1949 instr = coj[opcode].compare
1950 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
1951 md_number_to_chars (iP, instr, 4);
1953 /* Output branch instruction. */
1954 md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
1956 /* Set up address fixup/relocation. */
1957 fixP = fix_new (fragP,
1958 iP + 4 - fragP->fr_literal,
1965 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field. */
1973 Called by base assembler after address relaxation is finished: modify
1974 variable fragments according to how much relaxation was done.
1976 If the fragment substate is still 1, a 13-bit displacement was enough
1977 to reach the symbol in question. Set up an address fixup, but otherwise
1978 leave the cobr instruction alone.
1980 If the fragment substate is 2, a 13-bit displacement was not enough.
1981 Replace the cobr with a two instructions (a compare and a branch). */
1984 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
1985 segT sec ATTRIBUTE_UNUSED,
1988 /* Structure describing needed address fix. */
1991 switch (fragP->fr_subtype)
1994 /* Leave single cobr instruction. */
1995 fixP = fix_new (fragP,
1996 fragP->fr_opcode - fragP->fr_literal,
2003 fixP->fx_bit_fixP = (bit_fixS *) 13; /* Size of bit field. */
2006 /* Replace cobr with compare/branch instructions. */
2010 BAD_CASE (fragP->fr_subtype);
2015 /* md_estimate_size_before_relax: How much does it look like *fragP will grow?
2017 Called by base assembler just before address relaxation.
2018 Return the amount by which the fragment will grow.
2020 Any symbol that is now undefined will not become defined; cobr's
2021 based on undefined symbols will have to be replaced with a compare
2022 instruction and a branch instruction, and the code fragment will grow
2026 md_estimate_size_before_relax (fragS *fragP, segT segment_type)
2028 /* If symbol is undefined in this segment, go to "relaxed" state
2029 (compare and branch instructions instead of cobr) right now. */
2030 if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
2036 return md_relax_table[fragP->fr_subtype].rlx_length;
2039 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2042 This routine exists in order to overcome machine byte-order problems
2043 when dealing with bit-field entries in the relocation_info struct.
2045 But relocation info will be used on the host machine only (only
2046 executable code is actually downloaded to the i80960). Therefore,
2047 we leave it in host byte order. */
2050 md_ri_to_chars (char *where, struct relocation_info *ri)
2052 host_number_to_chars (where, ri->r_address, 4);
2053 host_number_to_chars (where + 4, ri->r_index, 3);
2055 where[7] = (ri->r_pcrel << 7
2063 where[7] = (ri->r_pcrel << 0
2073 #endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
2076 /* brtab_emit: generate the fetch-prediction branch table.
2078 See the comments above the declaration of 'br_cnt' for details on
2079 branch-prediction instrumentation.
2081 The code emitted here would be functionally equivalent to the following
2082 example assembler source.
2087 .word 0 # link to next table
2088 .word 3 # length of table
2089 .word LBRANCH0 # 1st entry in table proper
2098 /* Where the binary was output to. */
2101 if (!instrument_branches)
2104 subseg_set (data_section, 0); /* .data */
2105 frag_align (2, 0, 0); /* .align 2 */
2106 record_alignment (now_seg, 2);
2107 colon (BR_TAB_NAME); /* BR_TAB_NAME: */
2108 emit (0); /* .word 0 #link to next table */
2109 emit (br_cnt); /* .word n #length of table */
2111 for (i = 0; i < br_cnt; i++)
2113 sprintf (buf, "%s%d", BR_LABEL_BASE, i);
2116 p - frag_now->fr_literal,
2117 4, symbol_find (buf), 0, 0, NO_RELOC);
2121 /* s_leafproc: process .leafproc pseudo-op
2123 .leafproc takes two arguments, the second one is optional:
2124 arg[1]: name of 'call' entry point to leaf procedure
2125 arg[2]: name of 'bal' entry point to leaf procedure
2127 If the two arguments are identical, or if the second one is missing,
2128 the first argument is taken to be the 'bal' entry point.
2130 If there are 2 distinct arguments, we must make sure that the 'bal'
2131 entry point immediately follows the 'call' entry point in the linked
2135 s_leafproc (int n_ops, /* Number of operands. */
2136 char *args[]) /* args[1]->1st operand, args[2]->2nd operand. */
2138 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol. */
2139 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol. */
2141 if ((n_ops != 1) && (n_ops != 2))
2143 as_bad (_("should have 1 or 2 operands"));
2147 /* Find or create symbol for 'call' entry point. */
2148 callP = symbol_find_or_make (args[1]);
2150 if (TC_S_IS_CALLNAME (callP))
2151 as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
2153 /* If that was the only argument, use it as the 'bal' entry point.
2154 Otherwise, mark it as the 'call' entry point and find or create
2155 another symbol for the 'bal' entry point. */
2156 if ((n_ops == 1) || !strcmp (args[1], args[2]))
2158 TC_S_FORCE_TO_BALNAME (callP);
2162 TC_S_FORCE_TO_CALLNAME (callP);
2164 balP = symbol_find_or_make (args[2]);
2165 if (TC_S_IS_CALLNAME (balP))
2166 as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
2168 TC_S_FORCE_TO_BALNAME (balP);
2171 tc_set_bal_of_call (callP, balP);
2176 /* s_sysproc: process .sysproc pseudo-op
2178 .sysproc takes two arguments:
2179 arg[1]: name of entry point to system procedure
2180 arg[2]: 'entry_num' (index) of system procedure in the range
2183 For [ab].out, we store the 'entrynum' in the 'n_other' field of
2184 the symbol. Since that entry is normally 0, we bias 'entrynum'
2185 by adding 1 to it. It must be unbiased before it is used. */
2188 s_sysproc (int n_ops, /* Number of operands. */
2189 char *args[]) /* args[1]->1st operand, args[2]->2nd operand. */
2196 as_bad (_("should have two operands"));
2200 /* Parse "entry_num" argument and check it for validity. */
2201 parse_expr (args[2], &exp);
2202 if (exp.X_op != O_constant
2204 || (offs (exp) > 31))
2206 as_bad (_("'entry_num' must be absolute number in [0,31]"));
2210 /* Find/make symbol and stick entry number (biased by +1) into it. */
2211 symP = symbol_find_or_make (args[1]);
2213 if (TC_S_IS_SYSPROC (symP))
2214 as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
2216 TC_S_SET_SYSPROC (symP, offs (exp)); /* Encode entry number. */
2217 TC_S_FORCE_TO_SYSPROC (symP);
2220 /* parse_po: parse machine-dependent pseudo-op
2222 This is a top-level routine for machine-dependent pseudo-ops. It slurps
2223 up the rest of the input line, breaks out the individual arguments,
2224 and dispatches them to the correct handler. */
2227 parse_po (int po_num) /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC. */
2229 /* Pointers operands, with no embedded whitespace.
2230 arg[0] unused, arg[1-3]->operands. */
2232 int n_ops; /* Number of operands. */
2233 char *p; /* Pointer to beginning of unparsed argument string. */
2234 char eol; /* Character that indicated end of line. */
2236 extern char is_end_of_line[];
2238 /* Advance input pointer to end of line. */
2239 p = input_line_pointer;
2240 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2241 input_line_pointer++;
2243 eol = *input_line_pointer; /* Save end-of-line char. */
2244 *input_line_pointer = '\0'; /* Terminate argument list. */
2246 /* Parse out operands. */
2247 n_ops = get_args (p, args);
2251 /* Dispatch to correct handler. */
2255 s_sysproc (n_ops, args);
2258 s_leafproc (n_ops, args);
2265 /* Restore eol, so line numbers get updated correctly. Base
2266 assembler assumes we leave input pointer pointing at char
2267 following the eol. */
2268 *input_line_pointer++ = eol;
2271 /* reloc_callj: Relocate a 'callj' instruction
2273 This is a "non-(GNU)-standard" machine-dependent hook. The base
2274 assembler calls it when it decides it can relocate an address at
2275 assembly time instead of emitting a relocation directive.
2277 Check to see if the relocation involves a 'callj' instruction to a:
2278 sysproc: Replace the default 'call' instruction with a 'calls'
2279 leafproc: Replace the default 'call' instruction with a 'bal'.
2280 other proc: Do nothing.
2282 See b.out.h for details on the 'n_other' field in a symbol structure.
2285 Assumes the caller has already figured out, in the case of a leafproc,
2286 to use the 'bal' entry point, and has substituted that symbol into the
2287 passed fixup structure. */
2290 reloc_callj (fixS *fixP) /* Relocation that can be done at assembly time. */
2292 /* Points to the binary for the instruction being relocated. */
2295 if (!fixP->fx_tcbit)
2296 /* This wasn't a callj instruction in the first place. */
2299 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2301 if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2303 /* Symbol is a .sysproc: replace 'call' with 'calls'. System
2304 procedure number is (other-1). */
2305 md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2307 /* Nothing else needs to be done for this instruction. Make
2308 sure 'md_number_to_field()' will perform a no-op. */
2309 fixP->fx_bit_fixP = (bit_fixS *) 1;
2311 else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2313 /* Should not happen: see block comment above. */
2314 as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
2316 else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2318 /* Replace 'call' with 'bal'; both instructions have the same
2319 format, so calling code should complete relocation as if
2320 nothing happened here. */
2321 md_number_to_chars (where, BAL, 4);
2323 else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2324 as_bad (_("Looks like a proc, but can't tell what kind.\n"));
2326 /* Otherwise Symbol is neither a sysproc nor a leafproc. */
2330 /* Handle the MRI .endian pseudo-op. */
2333 s_endian (int ignore ATTRIBUTE_UNUSED)
2338 name = input_line_pointer;
2339 c = get_symbol_end ();
2340 if (strcasecmp (name, "little") == 0)
2342 else if (strcasecmp (name, "big") == 0)
2343 as_bad (_("big endian mode is not supported"));
2345 as_warn (_("ignoring unrecognized .endian type `%s'"), name);
2347 *input_line_pointer = c;
2349 demand_empty_rest_of_line ();
2352 /* We have no need to default values of symbols. */
2355 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
2360 /* Exactly what point is a PC-relative offset relative TO?
2361 On the i960, they're relative to the address of the instruction,
2362 which we have set up as the address of the fixup too. */
2364 md_pcrel_from (fixS *fixP)
2366 return fixP->fx_where + fixP->fx_frag->fr_address;
2370 md_apply_fix (fixS *fixP,
2372 segT seg ATTRIBUTE_UNUSED)
2375 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2377 if (!fixP->fx_bit_fixP)
2379 md_number_to_imm (place, val, fixP->fx_size);
2381 else if ((int) (size_t) fixP->fx_bit_fixP == 13
2382 && fixP->fx_addsy != NULL
2383 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
2385 /* This is a COBR instruction. They have only a
2386 13-bit displacement and are only to be used
2387 for local branches: flag as error, don't generate
2389 as_bad_where (fixP->fx_file, fixP->fx_line,
2390 _("can't use COBR format with external label"));
2391 fixP->fx_addsy = NULL;
2394 md_number_to_field (place, val, fixP->fx_bit_fixP);
2396 if (fixP->fx_addsy == NULL)
2400 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2402 tc_bout_fix_to_chars (char *where,
2404 relax_addressT segment_address_in_file)
2406 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
2407 struct relocation_info ri;
2410 memset ((char *) &ri, '\0', sizeof (ri));
2411 symbolP = fixP->fx_addsy;
2412 know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2413 ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2414 /* These two 'cuz of NS32K */
2415 ri.r_callj = fixP->fx_tcbit;
2416 if (fixP->fx_bit_fixP)
2419 ri.r_length = nbytes_r_length[fixP->fx_size];
2420 ri.r_pcrel = fixP->fx_pcrel;
2421 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2423 if (fixP->fx_r_type != NO_RELOC)
2425 switch (fixP->fx_r_type)
2430 ri.r_length = fixP->fx_size - 1;
2444 else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
2447 ri.r_index = symbolP->sy_number;
2452 ri.r_index = S_GET_TYPE (symbolP);
2455 /* Output the relocation information in machine-dependent form. */
2456 md_ri_to_chars (where, &ri);
2459 #endif /* OBJ_AOUT or OBJ_BOUT */
2461 /* Align an address by rounding it up to the specified boundary. */
2464 md_section_align (segT seg,
2465 valueT addr) /* Address to be rounded up. */
2469 align = bfd_get_section_alignment (stdoutput, seg);
2470 return (addr + (1 << align) - 1) & (-1 << align);
2473 extern int coff_flags;
2475 /* For aout or bout, the bal immediately follows the call.
2477 For coff, we cheat and store a pointer to the bal symbol in the
2478 second aux entry of the call. */
2489 tc_set_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED,
2490 symbolS *balP ATTRIBUTE_UNUSED)
2492 know (TC_S_IS_CALLNAME (callP));
2493 know (TC_S_IS_BALNAME (balP));
2497 callP->sy_tc = balP;
2498 S_SET_NUMBER_AUXILIARY (callP, 2);
2500 #else /* ! OBJ_COFF */
2503 /* If the 'bal' entry doesn't immediately follow the 'call'
2504 symbol, unlink it from the symbol list and re-insert it. */
2505 if (symbol_next (callP) != balP)
2507 symbol_remove (balP, &symbol_rootP, &symbol_lastP);
2508 symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
2509 } /* if not in order */
2511 #else /* ! OBJ_ABOUT */
2512 as_fatal ("Only supported for a.out, b.out, or COFF");
2513 #endif /* ! OBJ_ABOUT */
2514 #endif /* ! OBJ_COFF */
2518 tc_get_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED)
2522 know (TC_S_IS_CALLNAME (callP));
2525 retval = callP->sy_tc;
2528 retval = symbol_next (callP);
2530 as_fatal ("Only supported for a.out, b.out, or COFF");
2531 #endif /* ! OBJ_ABOUT */
2532 #endif /* ! OBJ_COFF */
2534 know (TC_S_IS_BALNAME (retval));
2540 tc_coff_symbol_emit_hook (symbolS *symbolP ATTRIBUTE_UNUSED)
2542 if (TC_S_IS_CALLNAME (symbolP))
2544 symbolS *balP = tc_get_bal_of_call (symbolP);
2546 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
2547 if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
2548 S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
2550 S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
2551 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
2552 /* Fix up the bal symbol. */
2553 S_SET_STORAGE_CLASS (balP, C_LABEL);
2556 #endif /* OBJ_COFF */
2559 i960_handle_align (fragS *fragp ATTRIBUTE_UNUSED)
2565 as_bad (_("option --link-relax is only supported in b.out format"));
2570 /* The text section "ends" with another alignment reloc, to which we
2571 aren't adding padding. */
2572 if (fragp->fr_next == text_last_frag
2573 || fragp->fr_next == data_last_frag)
2576 /* alignment directive */
2577 fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
2578 (int) fragp->fr_type);
2579 #endif /* OBJ_BOUT */
2583 i960_validate_fix (fixS *fixP, segT this_segment_type ATTRIBUTE_UNUSED)
2585 if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy))
2587 /* Relocation should be done via the associated 'bal'
2588 entry point symbol. */
2589 if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy)))
2591 as_bad_where (fixP->fx_file, fixP->fx_line,
2592 _("No 'bal' entry point for leafproc %s"),
2593 S_GET_NAME (fixP->fx_addsy));
2596 fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy);
2605 tc_bfd_fix2rtype (fixS *fixP)
2607 if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
2608 return BFD_RELOC_32;
2610 if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
2611 return BFD_RELOC_24_PCREL;
2617 /* Translate internal representation of relocation info to BFD target
2620 FIXME: To what extent can we get all relevant targets to use this? */
2623 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
2627 reloc = xmalloc (sizeof (arelent));
2629 /* HACK: Is this right? */
2630 fixP->fx_r_type = tc_bfd_fix2rtype (fixP);
2632 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
2633 if (reloc->howto == NULL)
2635 as_bad_where (fixP->fx_file, fixP->fx_line,
2636 _("internal error: can't export reloc type %d (`%s')"),
2638 bfd_get_reloc_code_name (fixP->fx_r_type));
2642 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
2644 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
2645 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
2646 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
2647 reloc->addend = fixP->fx_addnumber;
2652 /* end from cgen.c */
2654 const pseudo_typeS md_pseudo_table[] =
2656 {"bss", s_lcomm, 1},
2657 {"endian", s_endian, 0},
2658 {"extended", float_cons, 't'},
2659 {"leafproc", parse_po, S_LEAFPROC},
2660 {"sysproc", parse_po, S_SYSPROC},