1 /* tc-i960.c - All the i80960-specific stuff
2 Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GAS.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20 /* See comment on md_parse_option for 80960-specific invocation options. */
22 /******************************************************************************
24 * Header, symbol, and relocation info will be used on the host machine
25 * only -- only executable code is actually downloaded to the i80960.
26 * Therefore, leave all such information in host byte order.
28 * (That's a slight lie -- we DO download some header information, but
29 * the downloader converts the file format and corrects the byte-ordering
30 * of the relevant fields while doing so.)
32 * ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER
33 * FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO
34 * USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <==
36 ***************************************************************************** */
38 /* There are 4 different lengths of (potentially) symbol-based displacements
39 * in the 80960 instruction set, each of which could require address fix-ups
40 * and (in the case of external symbols) emission of relocation directives:
43 * This is a standard length for the base assembler and requires no
47 * This is a non-standard length, but the base assembler has a hook for
48 * bit field address fixups: the fixS structure can point to a descriptor
49 * of the field, in which case our md_number_to_field() routine gets called
52 * I made the hook a little cleaner by having fix_new() (in the base
53 * assembler) return a pointer to the fixS in question. And I made it a
54 * little simpler by storing the field size (in this case 13) instead of
55 * of a pointer to another structure: 80960 displacements are ALWAYS
56 * stored in the low-order bits of a 4-byte word.
58 * Since the target of a COBR cannot be external, no relocation directives
59 * for this size displacement have to be generated. But the base assembler
60 * had to be modified to issue error messages if the symbol did turn out
64 * Fixups are handled as for the 13-bit case (except that 24 is stored
67 * The relocation directive generated is the same as that for the 32-bit
68 * displacement, except that it's PC-relative (the 32-bit displacement
69 * never is). The i80960 version of the linker needs a mod to
70 * distinguish and handle the 24-bit case.
73 * MEMA formats are always promoted to MEMB (32-bit) if the displacement
74 * is based on a symbol, because it could be relocated at link time.
75 * The only time we use the 12-bit format is if an absolute value of
76 * less than 4096 is specified, in which case we need neither a fixup nor
77 * a relocation directive.
87 #include "opcode/i960.h"
89 extern char *input_line_pointer;
90 extern struct hash_control *po_hash;
91 extern char *next_object_file_charP;
94 const int md_reloc_size = sizeof (struct reloc);
96 const int md_reloc_size = sizeof (struct relocation_info);
99 /***************************
100 * Local i80960 routines *
101 ************************** */
103 static void brcnt_emit (); /* Emit branch-prediction instrumentation code */
104 static char *brlab_next (); /* Return next branch local label */
105 void brtab_emit (); /* Emit br-predict instrumentation table */
106 static void cobr_fmt (); /* Generate COBR instruction */
107 static void ctrl_fmt (); /* Generate CTRL instruction */
108 static char *emit (); /* Emit (internally) binary */
109 static int get_args (); /* Break arguments out of comma-separated list */
110 static void get_cdisp (); /* Handle COBR or CTRL displacement */
111 static char *get_ispec (); /* Find index specification string */
112 static int get_regnum (); /* Translate text to register number */
113 static int i_scan (); /* Lexical scan of instruction source */
114 static void mem_fmt (); /* Generate MEMA or MEMB instruction */
115 static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */
116 static segT parse_expr (); /* Parse an expression */
117 static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */
118 static void parse_memop (); /* Parse a memory operand */
119 static void parse_po (); /* Parse machine-dependent pseudo-op */
120 static void parse_regop (); /* Parse a register operand */
121 static void reg_fmt (); /* Generate a REG format instruction */
122 void reloc_callj (); /* Relocate a 'callj' instruction */
123 static void relax_cobr (); /* "De-optimize" cobr into compare/branch */
124 static void s_leafproc (); /* Process '.leafproc' pseudo-op */
125 static void s_sysproc (); /* Process '.sysproc' pseudo-op */
126 static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */
127 static void syntax (); /* Give syntax error */
128 static int targ_has_sfr (); /* Target chip supports spec-func register? */
129 static int targ_has_iclass (); /* Target chip supports instruction set? */
130 /* static void unlink_sym(); *//* Remove a symbol from the symbol list */
132 /* See md_parse_option() for meanings of these options */
133 static char norelax; /* True if -norelax switch seen */
134 static char instrument_branches;/* True if -b switch seen */
136 /* Characters that always start a comment.
137 * If the pre-processor is disabled, these aren't very useful.
139 const char comment_chars[] = "#";
141 /* Characters that only start a comment at the beginning of
142 * a line. If the line seems to have the form '# 123 filename'
143 * .line and .file directives will appear in the pre-processed output.
145 * Note that input_file.c hand checks for '#' at the beginning of the
146 * first line of the input file. This is because the compiler outputs
147 * #NO_APP at the beginning of its output.
150 /* Also note that comments started like this one will always work. */
152 const char line_comment_chars[1];
154 const char line_separator_chars[1];
156 /* Chars that can be used to separate mant from exp in floating point nums */
157 const char EXP_CHARS[] = "eE";
159 /* Chars that mean this number is a floating point constant,
160 * as in 0f12.456 or 0d1.2345e12
162 const char FLT_CHARS[] = "fFdDtT";
165 /* Table used by base assembler to relax addresses based on varying length
166 * instructions. The fields are:
167 * 1) most positive reach of this state,
168 * 2) most negative reach of this state,
169 * 3) how many bytes this mode will add to the size of the current frag
170 * 4) which index into the table to try if we can't fit into this one.
172 * For i80960, the only application is the (de-)optimization of cobr
173 * instructions into separate compare and branch instructions when a 13-bit
174 * displacement won't hack it.
179 {0, 0, 0, 0}, /* State 0 => no more relaxation possible */
180 {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */
181 {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */
185 /* These are the machine dependent pseudo-ops.
187 * This table describes all the machine specific pseudo-ops the assembler
188 * has to support. The fields are:
189 * pseudo-op name without dot
190 * function to call to execute this pseudo-op
191 * integer arg to pass to the function
196 const pseudo_typeS md_pseudo_table[] =
199 {"extended", float_cons, 't'},
200 {"leafproc", parse_po, S_LEAFPROC},
201 {"sysproc", parse_po, S_SYSPROC},
204 {"quad", big_cons, 16},
209 /* Macros to extract info from an 'expressionS' structure 'e' */
210 #define adds(e) e.X_add_symbol
211 #define subs(e) e.X_subtract_symbol
212 #define offs(e) e.X_add_number
213 #define segs(e) e.X_seg
216 /* Branch-prediction bits for CTRL/COBR format opcodes */
217 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
218 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
219 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
222 /* Some instruction opcodes that we need explicitly */
223 #define BE 0x12000000
224 #define BG 0x11000000
225 #define BGE 0x13000000
226 #define BL 0x14000000
227 #define BLE 0x16000000
228 #define BNE 0x15000000
229 #define BNO 0x10000000
230 #define BO 0x17000000
231 #define CHKBIT 0x5a002700
232 #define CMPI 0x5a002080
233 #define CMPO 0x5a002000
236 #define BAL 0x0b000000
237 #define CALL 0x09000000
238 #define CALLS 0x66003800
239 #define RET 0x0a000000
242 /* These masks are used to build up a set of MEMB mode bits. */
245 #define MEMB_BIT 0x1000
249 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
251 #define MEMA_ABASE 0x2000
253 /* Info from which a MEMA or MEMB format instruction can be generated */
256 /* (First) 32 bits of instruction */
258 /* 0-(none), 12- or, 32-bit displacement needed */
260 /* The expression in the source instruction from which the
261 displacement should be determined. */
268 /* The two pieces of info we need to generate a register operand */
271 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
272 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
273 int n; /* Register number or literal value */
277 /* Number and assembler mnemonic for all registers that can appear in operands */
319 /* Numbers for special-function registers are for assembler internal
320 use only: they are scaled back to range [0-31] for binary output. */
356 /* Numbers for floating point registers are for assembler internal use
357 * only: they are scaled back to [0-3] for binary output.
366 { NULL, 0 }, /* END OF LIST */
369 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
370 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
371 #define IS_FP_REG(n) ((n) >= FP0)
373 /* Number and assembler mnemonic for all registers that can appear as 'abase'
374 * (indirect addressing) registers.
418 /* For assembler internal use only: this number never appears in binary
422 { NULL, 0 }, /* END OF LIST */
427 static struct hash_control *op_hash; /* Opcode mnemonics */
428 static struct hash_control *reg_hash; /* Register name hash table */
429 static struct hash_control *areg_hash; /* Abase register hash table */
432 /* Architecture for which we are assembling */
433 #define ARCH_ANY 0 /* Default: no architecture checking done */
438 int architecture = ARCH_ANY; /* Architecture requested on invocation line */
439 int iclasses_seen; /* OR of instruction classes (I_* constants)
440 * for which we've actually assembled
445 /* BRANCH-PREDICTION INSTRUMENTATION
447 * The following supports generation of branch-prediction instrumentation
448 * (turned on by -b switch). The instrumentation collects counts
449 * of branches taken/not-taken for later input to a utility that will
450 * set the branch prediction bits of the instructions in accordance with
451 * the behavior observed. (Note that the KX series does not have
454 * The instrumentation consists of:
456 * (1) before and after each conditional branch, a call to an external
457 * routine that increments and steps over an inline counter. The
458 * counter itself, initialized to 0, immediately follows the call
459 * instruction. For each branch, the counter following the branch
460 * is the number of times the branch was not taken, and the difference
461 * between the counters is the number of times it was taken. An
462 * example of an instrumented conditional branch:
466 * LBRANCH23: be label
470 * (2) a table of pointers to the instrumented branches, so that an
471 * external postprocessing routine can locate all of the counters.
472 * the table begins with a 2-word header: a pointer to the next in
473 * a linked list of such tables (initialized to 0); and a count
474 * of the number of entries in the table (exclusive of the header.
476 * Note that input source code is expected to already contain calls
477 * an external routine that will link the branch local table into a
478 * list of such tables.
481 static int br_cnt; /* Number of branches instrumented so far.
482 * Also used to generate unique local labels
483 * for each instrumented branch
486 #define BR_LABEL_BASE "LBRANCH"
487 /* Basename of local labels on instrumented
488 * branches, to avoid conflict with compiler-
489 * generated local labels.
492 #define BR_CNT_FUNC "__inc_branch"
493 /* Name of the external routine that will
494 * increment (and step over) an inline counter.
497 #define BR_TAB_NAME "__BRANCH_TABLE__"
498 /* Name of the table of pointers to branches.
499 * A local (i.e., non-external) symbol.
502 /*****************************************************************************
503 * md_begin: One-time initialization.
505 * Set up hash tables.
507 **************************************************************************** */
511 int i; /* Loop counter */
512 const struct i960_opcode *oP; /* Pointer into opcode table */
513 char *retval; /* Value returned by hash functions */
515 if (((op_hash = hash_new ()) == 0)
516 || ((reg_hash = hash_new ()) == 0)
517 || ((areg_hash = hash_new ()) == 0))
519 as_fatal ("virtual memory exceeded");
522 /* For some reason, the base assembler uses an empty string for "no
523 error message", instead of a NULL pointer. */
526 for (oP = i960_opcodes; oP->name && !*retval; oP++)
528 retval = hash_insert (op_hash, oP->name, oP);
531 for (i = 0; regnames[i].reg_name && !*retval; i++)
533 retval = hash_insert (reg_hash, regnames[i].reg_name,
534 ®names[i].reg_num);
537 for (i = 0; aregs[i].areg_name && !*retval; i++)
539 retval = hash_insert (areg_hash, aregs[i].areg_name,
545 as_fatal ("Hashing returned \"%s\".", retval);
549 /*****************************************************************************
550 * md_end: One-time final cleanup
554 **************************************************************************** */
560 /*****************************************************************************
561 * md_assemble: Assemble an instruction
563 * Assumptions about the passed-in text:
564 * - all comments, labels removed
565 * - text is an instruction
566 * - all white space compressed to single blanks
567 * - all character constants have been replaced with decimal
569 **************************************************************************** */
572 char *textP; /* Source text of instruction */
574 /* Parsed instruction text, containing NO whitespace:
575 * arg[0]->opcode mnemonic
576 * arg[1-3]->operands, with char constants
577 * replaced by decimal numbers
581 int n_ops; /* Number of instruction operands */
583 /* Pointer to instruction description */
584 struct i960_opcode *oP;
585 /* TRUE iff opcode mnemonic included branch-prediction
586 * suffix (".f" or ".t")
589 /* Setting of branch-prediction bit(s) to be OR'd
590 * into instruction opcode of CTRL/COBR format
595 int n; /* Offset of last character in opcode mnemonic */
597 static const char bp_error_msg[] = "branch prediction invalid on this opcode";
600 /* Parse instruction into opcode and operands */
601 memset (args, '\0', sizeof (args));
602 n_ops = i_scan (textP, args);
605 return; /* Error message already issued */
608 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
609 if (!strcmp (args[0], "ldconst"))
611 n_ops = parse_ldconst (args);
620 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
621 n = strlen (args[0]) - 1;
624 if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
626 /* We could check here to see if the target architecture
627 * supports branch prediction, but why bother? The bit
628 * will just be ignored by processors that don't use it.
631 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
632 args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
635 /* Look up opcode mnemonic in table and check number of operands.
636 * Check that opcode is legal for the target architecture.
637 * If all looks good, assemble instruction.
639 oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
640 if (!oP || !targ_has_iclass (oP->iclass))
642 as_bad ("invalid opcode, \"%s\".", args[0]);
645 else if (n_ops != oP->num_ops)
647 as_bad ("improper number of operands. expecting %d, got %d",
656 ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
657 if (oP->format == FBRA)
659 /* Now generate a 'bno' to same arg */
660 ctrl_fmt (args[1], BNO | bp_bits, 1);
665 cobr_fmt (args, oP->opcode | bp_bits, oP);
670 as_warn (bp_error_msg);
675 if (args[0][0] == 'c' && args[0][1] == 'a')
679 as_warn (bp_error_msg);
681 mem_fmt (args, oP, 1);
691 as_warn (bp_error_msg);
693 mem_fmt (args, oP, 0);
698 as_warn (bp_error_msg);
700 /* Output opcode & set up "fixup" (relocation);
701 * flag relocation as 'callj' type.
703 know (oP->num_ops == 1);
704 get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
707 BAD_CASE (oP->format);
711 } /* md_assemble() */
713 /*****************************************************************************
714 * md_number_to_chars: convert a number to target byte order
716 **************************************************************************** */
718 md_number_to_chars (buf, value, n)
719 char *buf; /* Put output here */
720 valueT value; /* The integer to be converted */
721 int n; /* Number of bytes to output (significant bytes
731 /* XXX line number probably botched for this warning message. */
732 if (value != 0 && value != -1)
734 as_bad ("Displacement too long for instruction field length.");
738 } /* md_number_to_chars() */
740 /*****************************************************************************
741 * md_chars_to_number: convert from target byte order to host byte order.
743 **************************************************************************** */
745 md_chars_to_number (val, n)
746 unsigned char *val; /* Value in target byte order */
747 int n; /* Number of bytes in the input */
751 for (retval = 0; n--;)
760 #define MAX_LITTLENUMS 6
761 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
763 /*****************************************************************************
764 * md_atof: convert ascii to floating point
766 * Turn a string at input_line_pointer into a floating point constant of type
767 * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
768 * emitted is returned at 'sizeP'. An error message is returned, or a pointer
769 * to an empty message if OK.
771 * Note we call the i386 floating point routine, rather than complicating
772 * things with more files or symbolic links.
774 **************************************************************************** */
776 md_atof (type, litP, sizeP)
781 LITTLENUM_TYPE words[MAX_LITTLENUMS];
782 LITTLENUM_TYPE *wordP;
802 type = 'x'; /* That's what atof_ieee() understands */
807 return "Bad call to md_atof()";
810 t = atof_ieee (input_line_pointer, type, words);
813 input_line_pointer = t;
816 *sizeP = prec * LNUM_SIZE;
818 /* Output the LITTLENUMs in REVERSE order in accord with i80960
819 * word-order. (Dunno why atof_ieee doesn't do it in the right
820 * order in the first place -- probably because it's a hack of
824 for (wordP = words + prec - 1; prec--;)
826 md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
827 litP += sizeof (LITTLENUM_TYPE);
830 return ""; /* Someone should teach Dean about null pointers */
834 /*****************************************************************************
837 **************************************************************************** */
839 md_number_to_imm (buf, val, n)
844 md_number_to_chars (buf, val, n);
848 /*****************************************************************************
851 **************************************************************************** */
853 md_number_to_disp (buf, val, n)
858 md_number_to_chars (buf, val, n);
861 /*****************************************************************************
862 * md_number_to_field:
864 * Stick a value (an address fixup) into a bit field of
865 * previously-generated instruction.
867 **************************************************************************** */
869 md_number_to_field (instrP, val, bfixP)
870 char *instrP; /* Pointer to instruction to be fixed */
871 long val; /* Address fixup value */
872 bit_fixS *bfixP; /* Description of bit field to be fixed up */
874 int numbits; /* Length of bit field to be fixed */
875 long instr; /* 32-bit instruction to be fixed-up */
876 long sign; /* 0 or -1, according to sign bit of 'val' */
878 /* Convert instruction back to host byte order
880 instr = md_chars_to_number (instrP, 4);
882 /* Surprise! -- we stored the number of bits
883 * to be modified rather than a pointer to a structure.
885 numbits = (int) bfixP;
888 /* This is a no-op, stuck here by reloc_callj() */
892 know ((numbits == 13) || (numbits == 24));
894 /* Propagate sign bit of 'val' for the given number of bits.
895 * Result should be all 0 or all 1
897 sign = val >> ((int) numbits - 1);
898 if (((val < 0) && (sign != -1))
899 || ((val > 0) && (sign != 0)))
901 as_bad ("Fixup of %d too large for field width of %d",
906 /* Put bit field into instruction and write back in target
909 val &= ~(-1 << (int) numbits); /* Clear unused sign bits */
911 md_number_to_chars (instrP, instr, 4);
913 } /* md_number_to_field() */
916 /*****************************************************************************
918 * Invocation line includes a switch not recognized by the base assembler.
919 * See if it's a processor-specific option. For the 960, these are:
922 * Conditional branch instructions that require displacements
923 * greater than 13 bits (or that have external targets) should
924 * generate errors. The default is to replace each such
925 * instruction with the corresponding compare (or chkbit) and
926 * branch instructions. Note that the Intel "j" cobr directives
927 * are ALWAYS "de-optimized" in this way when necessary,
928 * regardless of the setting of this option.
931 * Add code to collect information about branches taken, for
932 * later optimization of branch prediction bits by a separate
933 * tool. COBR and CNTL format instructions have branch
934 * prediction bits (in the CX architecture); if "BR" represents
935 * an instruction in one of these classes, the following rep-
936 * resents the code generated by the assembler:
938 * call <increment routine>
939 * .word 0 # pre-counter
941 * call <increment routine>
942 * .word 0 # post-counter
944 * A table of all such "Labels" is also generated.
947 * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
948 * Select the 80960 architecture. Instructions or features not
949 * supported by the selected architecture cause fatal errors.
950 * The default is to generate code for any instruction or feature
951 * that is supported by SOME version of the 960 (even if this
952 * means mixing architectures!).
954 **************************************************************************** */
956 md_parse_option (argP, cntP, vecP)
967 static struct tabentry arch_tab[] =
971 "SA", ARCH_KA, /* Synonym for KA */
972 "SB", ARCH_KB, /* Synonym for KB */
973 "KC", ARCH_MC, /* Synonym for MC */
979 if (!strcmp (*argP, "linkrelax"))
984 else if (!strcmp (*argP, "norelax"))
989 else if (**argP == 'b')
991 instrument_branches = 1;
994 else if (**argP == 'A')
998 for (tp = arch_tab; tp->flag != NULL; tp++)
1000 if (!strcmp (p, tp->flag))
1006 if (tp->flag == NULL)
1008 as_bad ("unknown architecture: %s", p);
1012 architecture = tp->arch;
1017 /* Unknown option */
1021 **argP = '\0'; /* Done parsing this switch */
1025 /*****************************************************************************
1027 * Called by base assembler after address relaxation is finished: modify
1028 * variable fragments according to how much relaxation was done.
1030 * If the fragment substate is still 1, a 13-bit displacement was enough
1031 * to reach the symbol in question. Set up an address fixup, but otherwise
1032 * leave the cobr instruction alone.
1034 * If the fragment substate is 2, a 13-bit displacement was not enough.
1035 * Replace the cobr with a two instructions (a compare and a branch).
1037 **************************************************************************** */
1039 md_convert_frag (headers, fragP)
1040 object_headers *headers;
1043 fixS *fixP; /* Structure describing needed address fix */
1045 switch (fragP->fr_subtype)
1048 /* LEAVE SINGLE COBR INSTRUCTION */
1049 fixP = fix_new (fragP,
1050 fragP->fr_opcode - fragP->fr_literal,
1058 fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */
1061 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
1065 BAD_CASE (fragP->fr_subtype);
1070 /*****************************************************************************
1071 * md_estimate_size_before_relax: How much does it look like *fragP will grow?
1073 * Called by base assembler just before address relaxation.
1074 * Return the amount by which the fragment will grow.
1076 * Any symbol that is now undefined will not become defined; cobr's
1077 * based on undefined symbols will have to be replaced with a compare
1078 * instruction and a branch instruction, and the code fragment will grow
1081 **************************************************************************** */
1083 md_estimate_size_before_relax (fragP, segment_type)
1084 register fragS *fragP;
1085 register segT segment_type;
1087 /* If symbol is undefined in this segment, go to "relaxed" state
1088 * (compare and branch instructions instead of cobr) right now.
1090 if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
1096 } /* md_estimate_size_before_relax() */
1099 /*****************************************************************************
1101 * This routine exists in order to overcome machine byte-order problems
1102 * when dealing with bit-field entries in the relocation_info struct.
1104 * But relocation info will be used on the host machine only (only
1105 * executable code is actually downloaded to the i80960). Therefore,
1106 * we leave it in host byte order.
1108 * The above comment is no longer true. This routine now really
1109 * does do the reordering (Ian Taylor 28 Aug 92).
1111 **************************************************************************** */
1113 md_ri_to_chars (where, ri)
1115 struct relocation_info *ri;
1117 md_number_to_chars (where, ri->r_address,
1118 sizeof (ri->r_address));
1119 where[4] = ri->r_index & 0x0ff;
1120 where[5] = (ri->r_index >> 8) & 0x0ff;
1121 where[6] = (ri->r_index >> 16) & 0x0ff;
1122 where[7] = ((ri->r_pcrel << 0)
1123 | (ri->r_length << 1)
1124 | (ri->r_extern << 3)
1127 | (ri->r_callj << 6));
1128 } /* md_ri_to_chars() */
1130 #ifndef WORKING_DOT_WORD
1132 int md_short_jump_size = 0;
1133 int md_long_jump_size = 0;
1136 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
1143 as_fatal ("failed sanity check.");
1147 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
1149 addressT from_addr, to_addr;
1153 as_fatal ("failed sanity check.");
1158 /*************************************************************
1160 * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER *
1162 ************************************************************ */
1166 /*****************************************************************************
1167 * brcnt_emit: Emit code to increment inline branch counter.
1169 * See the comments above the declaration of 'br_cnt' for details on
1170 * branch-prediction instrumentation.
1171 **************************************************************************** */
1175 ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */
1176 emit (0); /* Emit inline counter to be incremented */
1179 /*****************************************************************************
1180 * brlab_next: generate the next branch local label
1182 * See the comments above the declaration of 'br_cnt' for details on
1183 * branch-prediction instrumentation.
1184 **************************************************************************** */
1188 static char buf[20];
1190 sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1194 /*****************************************************************************
1195 * brtab_emit: generate the fetch-prediction branch table.
1197 * See the comments above the declaration of 'br_cnt' for details on
1198 * branch-prediction instrumentation.
1200 * The code emitted here would be functionally equivalent to the following
1201 * example assembler source.
1206 * .word 0 # link to next table
1207 * .word 3 # length of table
1208 * .word LBRANCH0 # 1st entry in table proper
1211 ***************************************************************************** */
1217 char *p; /* Where the binary was output to */
1218 fixS *fixP; /*->description of deferred address fixup */
1220 if (!instrument_branches)
1225 subseg_new (SEG_DATA, 0); /* .data */
1226 frag_align (2, 0); /* .align 2 */
1227 record_alignment (now_seg, 2);
1228 colon (BR_TAB_NAME); /* BR_TAB_NAME: */
1229 emit (0); /* .word 0 #link to next table */
1230 emit (br_cnt); /* .word n #length of table */
1232 for (i = 0; i < br_cnt; i++)
1234 sprintf (buf, "%s%d", BR_LABEL_BASE, i);
1236 fixP = fix_new (frag_now,
1237 p - frag_now->fr_literal,
1244 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1248 /*****************************************************************************
1249 * cobr_fmt: generate a COBR-format instruction
1251 **************************************************************************** */
1254 cobr_fmt (arg, opcode, oP)
1255 char *arg[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1256 long opcode; /* Opcode, with branch-prediction bits already set
1259 struct i960_opcode *oP;
1260 /*->description of instruction */
1262 long instr; /* 32-bit instruction */
1263 struct regop regop; /* Description of register operand */
1264 int n; /* Number of operands */
1265 int var_frag; /* 1 if varying length code fragment should
1266 * be emitted; 0 if an address fix
1267 * should be emitted.
1275 /* First operand (if any) of a COBR is always a register
1276 * operand. Parse it.
1278 parse_regop (®op, arg[1], oP->operand[0]);
1279 instr |= (regop.n << 19) | (regop.mode << 13);
1283 /* Second operand (if any) of a COBR is always a register
1284 * operand. Parse it.
1286 parse_regop (®op, arg[2], oP->operand[1]);
1287 instr |= (regop.n << 14) | regop.special;
1298 if (instrument_branches)
1301 colon (brlab_next ());
1304 /* A third operand to a COBR is always a displacement.
1305 * Parse it; if it's relaxable (a cobr "j" directive, or any
1306 * cobr other than bbs/bbc when the "-norelax" option is not in
1307 * use) set up a variable code fragment; otherwise set up an
1310 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1311 get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1313 if (instrument_branches)
1321 /*****************************************************************************
1322 * ctrl_fmt: generate a CTRL-format instruction
1324 **************************************************************************** */
1327 ctrl_fmt (targP, opcode, num_ops)
1328 char *targP; /* Pointer to text of lone operand (if any) */
1329 long opcode; /* Template of instruction */
1330 int num_ops; /* Number of operands */
1332 int instrument; /* TRUE iff we should add instrumentation to track
1333 * how often the branch is taken
1339 emit (opcode); /* Output opcode */
1344 instrument = instrument_branches && (opcode != CALL)
1345 && (opcode != B) && (opcode != RET) && (opcode != BAL);
1350 colon (brlab_next ());
1353 /* The operand MUST be an ip-relative displacment. Parse it
1354 * and set up address fix for the instruction we just output.
1356 get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1367 /*****************************************************************************
1368 * emit: output instruction binary
1370 * Output instruction binary, in target byte order, 4 bytes at a time.
1371 * Return pointer to where it was placed.
1373 **************************************************************************** */
1377 long instr; /* Word to be output, host byte order */
1379 char *toP; /* Where to output it */
1381 toP = frag_more (4); /* Allocate storage */
1382 md_number_to_chars (toP, instr, 4); /* Convert to target byte order */
1387 /*****************************************************************************
1388 * get_args: break individual arguments out of comma-separated list
1390 * Input assumptions:
1391 * - all comments and labels have been removed
1392 * - all strings of whitespace have been collapsed to a single blank.
1393 * - all character constants ('x') have been replaced with decimal
1396 * args[0] is untouched. args[1] points to first operand, etc. All args:
1397 * - are NULL-terminated
1398 * - contain no whitespace
1401 * Number of operands (0,1,2, or 3) or -1 on error.
1403 **************************************************************************** */
1406 register char *p; /* Pointer to comma-separated operands; MUCKED BY US */
1407 char *args[]; /* Output arg: pointers to operands placed in args[1-3].
1408 * MUST ACCOMMODATE 4 ENTRIES (args[0-3]).
1411 register int n; /* Number of operands */
1417 /* Skip lead white space */
1431 /* Squeze blanks out by moving non-blanks toward start of string.
1432 * Isolate operands, whenever comma is found.
1446 /* Start of operand */
1449 as_bad ("too many operands");
1452 *to++ = '\0'; /* Terminate argument */
1453 args[++n] = to; /* Start next argument */
1467 /*****************************************************************************
1468 * get_cdisp: handle displacement for a COBR or CTRL instruction.
1470 * Parse displacement for a COBR or CTRL instruction.
1472 * If successful, output the instruction opcode and set up for it,
1473 * depending on the arg 'var_frag', either:
1474 * o an address fixup to be done when all symbol values are known, or
1475 * o a varying length code fragment, with address fixup info. This
1476 * will be done for cobr instructions that may have to be relaxed
1477 * in to compare/branch instructions (8 bytes) if the final
1478 * address displacement is greater than 13 bits.
1480 *****************************************************************************/
1483 get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
1484 /* displacement as specified in source instruction */
1486 /* "COBR" or "CTRL" (for use in error message) */
1488 /* Instruction needing the displacement */
1490 /* # bits of displacement (13 for COBR, 24 for CTRL) */
1492 /* 1 if varying length code fragment should be emitted;
1493 * 0 if an address fix should be emitted.
1496 /* 1 if callj relocation should be done; else 0 */
1499 expressionS e; /* Parsed expression */
1500 fixS *fixP; /* Structure describing needed address fix */
1501 char *outP; /* Where instruction binary is output to */
1505 switch (parse_expr (dispP, &e))
1509 as_bad ("expression syntax error");
1516 outP = frag_more (8); /* Allocate worst-case storage */
1517 md_number_to_chars (outP, instr, 4);
1518 frag_variant (rs_machine_dependent, 4, 4, 1,
1519 adds (e), offs (e), outP, 0, 0);
1523 /* Set up a new fix structure, so address can be updated
1524 * when all symbol values are known.
1526 outP = emit (instr);
1527 fixP = fix_new (frag_now,
1528 outP - frag_now->fr_literal,
1536 fixP->fx_callj = callj;
1538 /* We want to modify a bit field when the address is
1539 * known. But we don't need all the garbage in the
1540 * bit_fix structure. So we're going to lie and store
1541 * the number of bits affected instead of a pointer.
1543 fixP->fx_bit_fixP = (bit_fixS *) numbits;
1549 as_bad ("attempt to branch into different segment");
1553 as_bad ("target of %s instruction must be a label", ifmtP);
1559 /*****************************************************************************
1560 * get_ispec: parse a memory operand for an index specification
1562 * Here, an "index specification" is taken to be anything surrounded
1563 * by square brackets and NOT followed by anything else.
1565 * If it's found, detach it from the input string, remove the surrounding
1566 * square brackets, and return a pointer to it. Otherwise, return NULL.
1568 **************************************************************************** */
1572 char *textP; /*->memory operand from source instruction, no white space */
1574 char *start; /*->start of index specification */
1575 char *end; /*->end of index specification */
1577 /* Find opening square bracket, if any
1579 start = strchr (textP, '[');
1584 /* Eliminate '[', detach from rest of operand */
1587 end = strchr (start, ']');
1591 as_bad ("unmatched '['");
1596 /* Eliminate ']' and make sure it was the last thing
1600 if (*(end + 1) != '\0')
1602 as_bad ("garbage after index spec ignored");
1609 /*****************************************************************************
1612 * Look up a (suspected) register name in the register table and return the
1613 * associated register number (or -1 if not found).
1615 **************************************************************************** */
1618 get_regnum (regname)
1619 char *regname; /* Suspected register name */
1623 rP = (int *) hash_find (reg_hash, regname);
1624 return (rP == NULL) ? -1 : *rP;
1628 /*****************************************************************************
1629 * i_scan: perform lexical scan of ascii assembler instruction.
1631 * Input assumptions:
1632 * - input string is an i80960 instruction (not a pseudo-op)
1633 * - all comments and labels have been removed
1634 * - all strings of whitespace have been collapsed to a single blank.
1637 * args[0] points to opcode, other entries point to operands. All strings:
1638 * - are NULL-terminated
1639 * - contain no whitespace
1640 * - have character constants ('x') replaced with a decimal number
1643 * Number of operands (0,1,2, or 3) or -1 on error.
1645 **************************************************************************** */
1648 register char *iP; /* Pointer to ascii instruction; MUCKED BY US. */
1649 char *args[]; /* Output arg: pointers to opcode and operands placed
1650 * here. MUST ACCOMMODATE 4 ENTRIES.
1654 /* Isolate opcode */
1658 } /* Skip lead space, if any */
1660 for (; *iP != ' '; iP++)
1664 /* There are no operands */
1667 /* We never moved: there was no opcode either! */
1668 as_bad ("missing opcode");
1674 *iP++ = '\0'; /* Terminate opcode */
1675 return (get_args (iP, args));
1679 /*****************************************************************************
1680 * mem_fmt: generate a MEMA- or MEMB-format instruction
1682 **************************************************************************** */
1684 mem_fmt (args, oP, callx)
1685 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1686 struct i960_opcode *oP; /* Pointer to description of instruction */
1687 int callx; /* Is this a callx opcode */
1689 int i; /* Loop counter */
1690 struct regop regop; /* Description of register operand */
1691 char opdesc; /* Operand descriptor byte */
1692 memS instr; /* Description of binary to be output */
1693 char *outP; /* Where the binary was output to */
1694 expressionS expr; /* Parsed expression */
1695 fixS *fixP; /*->description of deferred address fixup */
1697 memset (&instr, '\0', sizeof (memS));
1698 instr.opcode = oP->opcode;
1700 /* Process operands. */
1701 for (i = 1; i <= oP->num_ops; i++)
1703 opdesc = oP->operand[i - 1];
1707 parse_memop (&instr, args[i], oP->format);
1711 parse_regop (®op, args[i], opdesc);
1712 instr.opcode |= regop.n << 19;
1717 outP = emit (instr.opcode);
1719 if (instr.disp == 0)
1724 /* Parse and process the displacement */
1725 switch (parse_expr (instr.e, &expr))
1729 as_bad ("expression syntax error");
1733 if (instr.disp == 32)
1735 (void) emit (offs (expr)); /* Output displacement */
1739 /* 12-bit displacement */
1740 if (offs (expr) & ~0xfff)
1742 /* Won't fit in 12 bits: convert already-output
1743 * instruction to MEMB format, output
1746 mema_to_memb (outP);
1747 (void) emit (offs (expr));
1751 /* WILL fit in 12 bits: OR into opcode and
1752 * overwrite the binary we already put out
1754 instr.opcode |= offs (expr);
1755 md_number_to_chars (outP, instr.opcode, 4);
1760 case SEG_DIFFERENCE:
1765 if (instr.disp == 12)
1767 /* Displacement is dependent on a symbol, whose value
1768 * may change at link time. We HAVE to reserve 32 bits.
1769 * Convert already-output opcode to MEMB format.
1771 mema_to_memb (outP);
1774 /* Output 0 displacement and set up address fixup for when
1775 * this symbol's value becomes known.
1777 outP = emit ((long) 0);
1778 fixP = fix_new (frag_now,
1779 outP - frag_now->fr_literal,
1786 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1787 fixP->fx_bsr = callx; /*SAC LD RELAX HACK *//* Mark reloc as being in i stream */
1791 BAD_CASE (segs (expr));
1797 /*****************************************************************************
1798 * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1800 * There are 2 possible MEMA formats:
1801 * - displacement only
1802 * - displacement + abase
1804 * They are distinguished by the setting of the MEMA_ABASE bit.
1806 **************************************************************************** */
1808 mema_to_memb (opcodeP)
1809 char *opcodeP; /* Where to find the opcode, in target byte order */
1811 long opcode; /* Opcode in host byte order */
1812 long mode; /* Mode bits for MEMB instruction */
1814 opcode = md_chars_to_number (opcodeP, 4);
1815 know (!(opcode & MEMB_BIT));
1817 mode = MEMB_BIT | D_BIT;
1818 if (opcode & MEMA_ABASE)
1823 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */
1824 opcode |= mode; /* Set MEMB mode bits */
1826 md_number_to_chars (opcodeP, opcode, 4);
1827 } /* mema_to_memb() */
1830 /*****************************************************************************
1831 * parse_expr: parse an expression
1833 * Use base assembler's expression parser to parse an expression.
1834 * It, unfortunately, runs off a global which we have to save/restore
1835 * in order to make it work for us.
1837 * An empty expression string is treated as an absolute 0.
1839 * Return "segment" to which the expression evaluates.
1840 * Return SEG_GOOF regardless of expression evaluation if entire input
1841 * string is not consumed in the evaluation -- tolerate no dangling junk!
1843 **************************************************************************** */
1846 parse_expr (textP, expP)
1847 char *textP; /* Text of expression to be parsed */
1848 expressionS *expP; /* Where to put the results of parsing */
1850 char *save_in; /* Save global here */
1851 segT seg; /* Segment to which expression evaluates */
1858 /* Treat empty string as absolute 0 */
1859 expP->X_add_symbol = expP->X_subtract_symbol = NULL;
1860 expP->X_add_number = 0;
1861 seg = expP->X_seg = SEG_ABSOLUTE;
1866 save_in = input_line_pointer; /* Save global */
1867 input_line_pointer = textP; /* Make parser work for us */
1869 seg = expression (expP);
1870 if (input_line_pointer - textP != strlen (textP))
1872 /* Did not consume all of the input */
1875 symP = expP->X_add_symbol;
1876 if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
1878 /* Register name in an expression */
1882 input_line_pointer = save_in; /* Restore global */
1888 /*****************************************************************************
1890 * Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1891 * i80960 instruction.
1893 * Assumes the input consists of:
1894 * arg[0] opcode mnemonic ('ldconst')
1895 * arg[1] first operand (constant)
1896 * arg[2] name of register to be loaded
1898 * Replaces opcode and/or operands as appropriate.
1900 * Returns the new number of arguments, or -1 on failure.
1902 **************************************************************************** */
1906 char *arg[]; /* See above */
1908 int n; /* Constant to be loaded */
1909 int shift; /* Shift count for "shlo" instruction */
1910 static char buf[5]; /* Literal for first operand */
1911 static char buf2[5]; /* Literal for second operand */
1912 expressionS e; /* Parsed expression */
1915 arg[3] = NULL; /* So we can tell at the end if it got used or not */
1917 switch (parse_expr (arg[1], &e))
1924 case SEG_DIFFERENCE:
1925 /* We're dependent on one or more symbols -- use "lda" */
1930 /* Try the following mappings:
1931 * ldconst 0,<reg> ->mov 0,<reg>
1932 * ldconst 31,<reg> ->mov 31,<reg>
1933 * ldconst 32,<reg> ->addo 1,31,<reg>
1934 * ldconst 62,<reg> ->addo 31,31,<reg>
1935 * ldconst 64,<reg> ->shlo 8,3,<reg>
1936 * ldconst -1,<reg> ->subo 1,0,<reg>
1937 * ldconst -31,<reg>->subo 31,0,<reg>
1939 * anthing else becomes:
1943 if ((0 <= n) && (n <= 31))
1948 else if ((-31 <= n) && (n <= -1))
1952 sprintf (buf, "%d", -n);
1957 else if ((32 <= n) && (n <= 62))
1962 sprintf (buf, "%d", n - 31);
1966 else if ((shift = shift_ok (n)) != 0)
1970 sprintf (buf, "%d", shift);
1972 sprintf (buf2, "%d", n >> shift);
1983 as_bad ("invalid constant");
1987 return (arg[3] == 0) ? 2 : 3;
1990 /*****************************************************************************
1991 * parse_memop: parse a memory operand
1993 * This routine is based on the observation that the 4 mode bits of the
1994 * MEMB format, taken individually, have fairly consistent meaning:
1996 * M3 (bit 13): 1 if displacement is present (D_BIT)
1997 * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1998 * M1 (bit 11): 1 if index is present (I_BIT)
1999 * M0 (bit 10): 1 if abase is present (A_BIT)
2001 * So we parse the memory operand and set bits in the mode as we find
2002 * things. Then at the end, if we go to MEMB format, we need only set
2003 * the MEMB bit (M2) and our mode is built for us.
2005 * Unfortunately, I said "fairly consistent". The exceptions:
2008 * 0100 Would seem illegal, but means "abase-only".
2010 * 0101 Would seem to mean "abase-only" -- it means IP-relative.
2011 * Must be converted to 0100.
2013 * 0110 Would seem to mean "index-only", but is reserved.
2014 * We turn on the D bit and provide a 0 displacement.
2016 * The other thing to observe is that we parse from the right, peeling
2017 * things * off as we go: first any index spec, then any abase, then
2020 **************************************************************************** */
2023 parse_memop (memP, argP, optype)
2024 memS *memP; /* Where to put the results */
2025 char *argP; /* Text of the operand to be parsed */
2026 int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
2028 char *indexP; /* Pointer to index specification with "[]" removed */
2029 char *p; /* Temp char pointer */
2030 char iprel_flag; /* True if this is an IP-relative operand */
2031 int regnum; /* Register number */
2032 int scale; /* Scale factor: 1,2,4,8, or 16. Later converted
2033 * to internal format (0,1,2,3,4 respectively).
2035 int mode; /* MEMB mode bits */
2036 int *intP; /* Pointer to register number */
2038 /* The following table contains the default scale factors for each
2039 * type of memory instruction. It is accessed using (optype-MEM1)
2040 * as an index -- thus it assumes the 'optype' constants are assigned
2041 * consecutive values, in the order they appear in this table
2043 static int def_scale[] =
2049 -1, /* MEM12 -- no valid default */
2054 iprel_flag = mode = 0;
2056 /* Any index present? */
2057 indexP = get_ispec (argP);
2060 p = strchr (indexP, '*');
2063 /* No explicit scale -- use default for this
2066 scale = def_scale[optype - MEM1];
2070 *p++ = '\0'; /* Eliminate '*' */
2072 /* Now indexP->a '\0'-terminated register name,
2073 * and p->a scale factor.
2076 if (!strcmp (p, "16"))
2080 else if (strchr ("1248", *p) && (p[1] == '\0'))
2090 regnum = get_regnum (indexP); /* Get index reg. # */
2091 if (!IS_RG_REG (regnum))
2093 as_bad ("invalid index register");
2097 /* Convert scale to its binary encoding */
2116 as_bad ("invalid scale factor");
2120 memP->opcode |= scale | regnum; /* Set index bits in opcode */
2121 mode |= I_BIT; /* Found a valid index spec */
2124 /* Any abase (Register Indirect) specification present? */
2125 if ((p = strrchr (argP, '(')) != NULL)
2127 /* "(" is there -- does it start a legal abase spec?
2128 * (If not it could be part of a displacement expression.)
2130 intP = (int *) hash_find (areg_hash, p);
2133 /* Got an abase here */
2135 *p = '\0'; /* discard register spec */
2136 if (regnum == IPREL)
2138 /* We have to specialcase ip-rel mode */
2143 memP->opcode |= regnum << 14;
2149 /* Any expression present? */
2156 /* Special-case ip-relative addressing */
2165 memP->opcode |= 5 << 10; /* IP-relative mode */
2171 /* Handle all other modes */
2175 /* Go with MEMA instruction format for now (grow to MEMB later
2176 * if 12 bits is not enough for the displacement).
2177 * MEMA format has a single mode bit: set it to indicate
2178 * that abase is present.
2180 memP->opcode |= MEMA_ABASE;
2185 /* Go with MEMA instruction format for now (grow to MEMB later
2186 * if 12 bits is not enough for the displacement).
2192 /* For some reason, the bit string for this mode is not
2193 * consistent: it should be 0 (exclusive of the MEMB bit),
2194 * so we set it "by hand" here.
2196 memP->opcode |= MEMB_BIT;
2200 /* set MEMB bit in mode, and OR in mode bits */
2201 memP->opcode |= mode | MEMB_BIT;
2205 /* Treat missing displacement as displacement of 0 */
2207 /***********************
2208 * Fall into next case *
2209 ********************** */
2210 case D_BIT | A_BIT | I_BIT:
2212 /* set MEMB bit in mode, and OR in mode bits */
2213 memP->opcode |= mode | MEMB_BIT;
2223 /*****************************************************************************
2224 * parse_po: parse machine-dependent pseudo-op
2226 * This is a top-level routine for machine-dependent pseudo-ops. It slurps
2227 * up the rest of the input line, breaks out the individual arguments,
2228 * and dispatches them to the correct handler.
2229 **************************************************************************** */
2233 int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
2235 char *args[4]; /* Pointers operands, with no embedded whitespace.
2237 * arg[1-3]->operands
2239 int n_ops; /* Number of operands */
2240 char *p; /* Pointer to beginning of unparsed argument string */
2241 char eol; /* Character that indicated end of line */
2243 extern char is_end_of_line[];
2245 /* Advance input pointer to end of line. */
2246 p = input_line_pointer;
2247 while (!is_end_of_line[*input_line_pointer])
2249 input_line_pointer++;
2251 eol = *input_line_pointer; /* Save end-of-line char */
2252 *input_line_pointer = '\0'; /* Terminate argument list */
2254 /* Parse out operands */
2255 n_ops = get_args (p, args);
2261 /* Dispatch to correct handler */
2265 s_sysproc (n_ops, args);
2268 s_leafproc (n_ops, args);
2275 /* Restore eol, so line numbers get updated correctly. Base assembler
2276 * assumes we leave input pointer pointing at char following the eol.
2278 *input_line_pointer++ = eol;
2281 /*****************************************************************************
2282 * parse_regop: parse a register operand.
2284 * In case of illegal operand, issue a message and return some valid
2285 * information so instruction processing can continue.
2286 **************************************************************************** */
2289 parse_regop (regopP, optext, opdesc)
2290 struct regop *regopP; /* Where to put description of register operand */
2291 char *optext; /* Text of operand */
2292 char opdesc; /* Descriptor byte: what's legal for this operand */
2294 int n; /* Register number */
2295 expressionS e; /* Parsed expression */
2297 /* See if operand is a register */
2298 n = get_regnum (optext);
2303 /* global or local register */
2304 if (!REG_ALIGN (opdesc, n))
2306 as_bad ("unaligned register");
2310 regopP->special = 0;
2313 else if (IS_FP_REG (n) && FP_OK (opdesc))
2315 /* Floating point register, and it's allowed */
2316 regopP->n = n - FP0;
2318 regopP->special = 0;
2321 else if (IS_SF_REG (n) && SFR_OK (opdesc))
2323 /* Special-function register, and it's allowed */
2324 regopP->n = n - SF0;
2326 regopP->special = 1;
2327 if (!targ_has_sfr (regopP->n))
2329 as_bad ("no such sfr in this architecture");
2334 else if (LIT_OK (opdesc))
2337 * How about a literal?
2340 regopP->special = 0;
2342 { /* floating point literal acceptable */
2343 /* Skip over 0f, 0d, or 0e prefix */
2344 if ((optext[0] == '0')
2345 && (optext[1] >= 'd')
2346 && (optext[1] <= 'f'))
2351 if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
2356 if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
2364 { /* fixed point literal acceptable */
2365 if ((parse_expr (optext, &e) != SEG_ABSOLUTE)
2366 || (offs (e) < 0) || (offs (e) > 31))
2368 as_bad ("illegal literal");
2371 regopP->n = offs (e);
2376 /* Nothing worked */
2378 regopP->mode = 0; /* Register r0 is always a good one */
2380 regopP->special = 0;
2381 } /* parse_regop() */
2383 /*****************************************************************************
2384 * reg_fmt: generate a REG-format instruction
2386 **************************************************************************** */
2389 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2390 struct i960_opcode *oP; /* Pointer to description of instruction */
2392 long instr; /* Binary to be output */
2393 struct regop regop; /* Description of register operand */
2394 int n_ops; /* Number of operands */
2398 n_ops = oP->num_ops;
2402 parse_regop (®op, args[1], oP->operand[0]);
2404 if ((n_ops == 1) && !(instr & M3))
2406 /* 1-operand instruction in which the dst field should
2407 * be used (instead of src1).
2412 regop.mode = regop.special;
2419 /* regop.n goes in bit 0, needs no shifting */
2421 regop.special <<= 5;
2423 instr |= regop.n | regop.mode | regop.special;
2428 parse_regop (®op, args[2], oP->operand[1]);
2430 if ((n_ops == 2) && !(instr & M3))
2432 /* 2-operand instruction in which the dst field should
2433 * be used instead of src2).
2438 regop.mode = regop.special;
2447 regop.special <<= 6;
2449 instr |= regop.n | regop.mode | regop.special;
2453 parse_regop (®op, args[3], oP->operand[2]);
2456 regop.mode = regop.special;
2458 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2464 /*****************************************************************************
2466 * Replace cobr instruction in a code fragment with equivalent branch and
2467 * compare instructions, so it can reach beyond a 13-bit displacement.
2468 * Set up an address fix/relocation for the new branch instruction.
2470 **************************************************************************** */
2472 /* This "conditional jump" table maps cobr instructions into equivalent
2473 * compare and branch opcodes.
2483 { /* COBR OPCODE: */
2484 CHKBIT, BNO, /* 0x30 - bbc */
2485 CMPO, BG, /* 0x31 - cmpobg */
2486 CMPO, BE, /* 0x32 - cmpobe */
2487 CMPO, BGE, /* 0x33 - cmpobge */
2488 CMPO, BL, /* 0x34 - cmpobl */
2489 CMPO, BNE, /* 0x35 - cmpobne */
2490 CMPO, BLE, /* 0x36 - cmpoble */
2491 CHKBIT, BO, /* 0x37 - bbs */
2492 CMPI, BNO, /* 0x38 - cmpibno */
2493 CMPI, BG, /* 0x39 - cmpibg */
2494 CMPI, BE, /* 0x3a - cmpibe */
2495 CMPI, BGE, /* 0x3b - cmpibge */
2496 CMPI, BL, /* 0x3c - cmpibl */
2497 CMPI, BNE, /* 0x3d - cmpibne */
2498 CMPI, BLE, /* 0x3e - cmpible */
2499 CMPI, BO, /* 0x3f - cmpibo */
2505 register fragS *fragP; /* fragP->fr_opcode is assumed to point to
2506 * the cobr instruction, which comes at the
2507 * end of the code fragment.
2510 int opcode, src1, src2, m1, s2;
2511 /* Bit fields from cobr instruction */
2512 long bp_bits; /* Branch prediction bits from cobr instruction */
2513 long instr; /* A single i960 instruction */
2514 char *iP; /*->instruction to be replaced */
2515 fixS *fixP; /* Relocation that can be done at assembly time */
2517 /* PICK UP & PARSE COBR INSTRUCTION */
2518 iP = fragP->fr_opcode;
2519 instr = md_chars_to_number (iP, 4);
2520 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2521 src1 = (instr >> 19) & 0x1f;
2522 m1 = (instr >> 13) & 1;
2524 src2 = (instr >> 14) & 0x1f;
2525 bp_bits = instr & BP_MASK;
2527 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2528 instr = coj[opcode].compare
2529 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2530 md_number_to_chars (iP, instr, 4);
2532 /* OUTPUT BRANCH INSTRUCTION */
2533 md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
2535 /* SET UP ADDRESS FIXUP/RELOCATION */
2536 fixP = fix_new (fragP,
2537 iP + 4 - fragP->fr_literal,
2545 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */
2552 /*****************************************************************************
2553 * reloc_callj: Relocate a 'callj' instruction
2555 * This is a "non-(GNU)-standard" machine-dependent hook. The base
2556 * assembler calls it when it decides it can relocate an address at
2557 * assembly time instead of emitting a relocation directive.
2559 * Check to see if the relocation involves a 'callj' instruction to a:
2560 * sysproc: Replace the default 'call' instruction with a 'calls'
2561 * leafproc: Replace the default 'call' instruction with a 'bal'.
2562 * other proc: Do nothing.
2564 * See b.out.h for details on the 'n_other' field in a symbol structure.
2567 * Assumes the caller has already figured out, in the case of a leafproc,
2568 * to use the 'bal' entry point, and has substituted that symbol into the
2569 * passed fixup structure.
2571 **************************************************************************** */
2574 fixS *fixP; /* Relocation that can be done at assembly time */
2576 char *where; /*->the binary for the instruction being relocated */
2578 if (!fixP->fx_callj)
2581 } /* This wasn't a callj instruction in the first place */
2583 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2585 if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2587 /* Symbol is a .sysproc: replace 'call' with 'calls'.
2588 * System procedure number is (other-1).
2590 md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2592 /* Nothing else needs to be done for this instruction.
2593 * Make sure 'md_number_to_field()' will perform a no-op.
2595 fixP->fx_bit_fixP = (bit_fixS *) 1;
2598 else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2600 /* Should not happen: see block comment above */
2601 as_fatal ("Trying to 'bal' to %s", S_GET_NAME (fixP->fx_addsy));
2604 else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2606 /* Replace 'call' with 'bal'; both instructions have
2607 * the same format, so calling code should complete
2608 * relocation as if nothing happened here.
2610 md_number_to_chars (where, BAL, 4);
2612 else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2614 as_bad ("Looks like a proc, but can't tell what kind.\n");
2615 } /* switch on proc type */
2617 /* else Symbol is neither a sysproc nor a leafproc */
2620 } /* reloc_callj() */
2623 /*****************************************************************************
2624 * s_leafproc: process .leafproc pseudo-op
2626 * .leafproc takes two arguments, the second one is optional:
2627 * arg[1]: name of 'call' entry point to leaf procedure
2628 * arg[2]: name of 'bal' entry point to leaf procedure
2630 * If the two arguments are identical, or if the second one is missing,
2631 * the first argument is taken to be the 'bal' entry point.
2633 * If there are 2 distinct arguments, we must make sure that the 'bal'
2634 * entry point immediately follows the 'call' entry point in the linked
2637 **************************************************************************** */
2639 s_leafproc (n_ops, args)
2640 int n_ops; /* Number of operands */
2641 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2643 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */
2644 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */
2646 if ((n_ops != 1) && (n_ops != 2))
2648 as_bad ("should have 1 or 2 operands");
2650 } /* Check number of arguments */
2652 /* Find or create symbol for 'call' entry point. */
2653 callP = symbol_find_or_make (args[1]);
2655 if (TC_S_IS_CALLNAME (callP))
2657 as_warn ("Redefining leafproc %s", S_GET_NAME (callP));
2660 /* If that was the only argument, use it as the 'bal' entry point.
2661 * Otherwise, mark it as the 'call' entry point and find or create
2662 * another symbol for the 'bal' entry point.
2664 if ((n_ops == 1) || !strcmp (args[1], args[2]))
2666 TC_S_FORCE_TO_BALNAME (callP);
2671 TC_S_FORCE_TO_CALLNAME (callP);
2673 balP = symbol_find_or_make (args[2]);
2674 if (TC_S_IS_CALLNAME (balP))
2676 as_warn ("Redefining leafproc %s", S_GET_NAME (balP));
2678 TC_S_FORCE_TO_BALNAME (balP);
2680 tc_set_bal_of_call (callP, balP);
2681 } /* if only one arg, or the args are the same */
2684 } /* s_leafproc() */
2688 * s_sysproc: process .sysproc pseudo-op
2690 * .sysproc takes two arguments:
2691 * arg[1]: name of entry point to system procedure
2692 * arg[2]: 'entry_num' (index) of system procedure in the range
2695 * For [ab].out, we store the 'entrynum' in the 'n_other' field of
2696 * the symbol. Since that entry is normally 0, we bias 'entrynum'
2697 * by adding 1 to it. It must be unbiased before it is used.
2700 s_sysproc (n_ops, args)
2701 int n_ops; /* Number of operands */
2702 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2709 as_bad ("should have two operands");
2711 } /* bad arg count */
2713 /* Parse "entry_num" argument and check it for validity. */
2714 if ((parse_expr (args[2], &exp) != SEG_ABSOLUTE)
2716 || (offs (exp) > 31))
2718 as_bad ("'entry_num' must be absolute number in [0,31]");
2722 /* Find/make symbol and stick entry number (biased by +1) into it */
2723 symP = symbol_find_or_make (args[1]);
2725 if (TC_S_IS_SYSPROC (symP))
2727 as_warn ("Redefining entrynum for sysproc %s", S_GET_NAME (symP));
2730 TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */
2731 TC_S_FORCE_TO_SYSPROC (symP);
2737 /*****************************************************************************
2739 * Determine if a "shlo" instruction can be used to implement a "ldconst".
2740 * This means that some number X < 32 can be shifted left to produce the
2741 * constant of interest.
2743 * Return the shift count, or 0 if we can't do it.
2744 * Caller calculates X by shifting original constant right 'shift' places.
2746 **************************************************************************** */
2750 int n; /* The constant of interest */
2752 int shift; /* The shift count */
2756 /* Can't do it for negative numbers */
2760 /* Shift 'n' right until a 1 is about to be lost */
2761 for (shift = 0; (n & 1) == 0; shift++)
2774 /*****************************************************************************
2775 * syntax: issue syntax error
2777 **************************************************************************** */
2781 as_bad ("syntax error");
2785 /*****************************************************************************
2787 * Return TRUE iff the target architecture supports the specified
2788 * special-function register (sfr).
2790 **************************************************************************** */
2794 int n; /* Number (0-31) of sfr */
2796 switch (architecture)
2804 return ((0 <= n) && (n <= 2));
2809 /*****************************************************************************
2811 * Return TRUE iff the target architecture supports the indicated
2812 * class of instructions.
2814 **************************************************************************** */
2817 targ_has_iclass (ic)
2818 int ic; /* Instruction class; one of:
2819 * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM
2822 iclasses_seen |= ic;
2823 switch (architecture)
2826 return ic & (I_BASE | I_KX);
2828 return ic & (I_BASE | I_KX | I_FP | I_DEC);
2830 return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2832 return ic & (I_BASE | I_CX | I_CASIM);
2834 if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
2835 && (iclasses_seen & I_CX))
2837 as_warn ("architecture of opcode conflicts with that of earlier instruction(s)");
2838 iclasses_seen &= ~ic;
2845 /* Parse an operand that is machine-specific.
2846 We just return without modifying the expression if we have nothing
2851 md_operand (expressionP)
2852 expressionS *expressionP;
2856 /* We have no need to default values of symbols. */
2860 md_undefined_symbol (name)
2864 } /* md_undefined_symbol() */
2866 /* Exactly what point is a PC-relative offset relative TO?
2867 On the i960, they're relative to the address of the instruction,
2868 which we have set up as the address of the fixup too. */
2870 md_pcrel_from (fixP)
2873 return fixP->fx_where + fixP->fx_frag->fr_address;
2877 md_apply_fix (fixP, val)
2881 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2883 if (!fixP->fx_bit_fixP)
2886 switch (fixP->fx_im_disp)
2889 fixP->fx_addnumber = val;
2890 md_number_to_imm (place, val, fixP->fx_size, fixP);
2893 md_number_to_disp (place,
2895 ? val + fixP->fx_pcrel_adjust
2899 case 2: /* fix requested for .long .word etc */
2900 md_number_to_chars (place, val, fixP->fx_size);
2903 as_fatal ("Internal error in md_apply_fix() in file \"%s\"",
2909 md_number_to_field (place, val, fixP->fx_bit_fixP);
2913 } /* md_apply_fix() */
2915 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2917 tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
2920 relax_addressT segment_address_in_file;
2922 static unsigned char nbytes_r_length[] =
2924 struct relocation_info ri;
2927 /* JF this is for paranoia */
2928 memset ((char *) &ri, '\0', sizeof (ri));
2929 symbolP = fixP->fx_addsy;
2930 know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2931 ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2932 /* These two 'cuz of NS32K */
2933 ri.r_callj = fixP->fx_callj;
2934 if (fixP->fx_bit_fixP)
2940 ri.r_length = nbytes_r_length[fixP->fx_size];
2942 ri.r_pcrel = fixP->fx_pcrel;
2943 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2945 if (fixP->fx_r_type != NO_RELOC)
2947 switch (fixP->fx_r_type)
2952 ri.r_length = fixP->fx_size - 1;
2966 else if (linkrelax || !S_IS_DEFINED (symbolP))
2969 ri.r_index = symbolP->sy_number;
2974 ri.r_index = S_GET_TYPE (symbolP);
2977 /* Output the relocation information in machine-dependent form. */
2978 md_ri_to_chars (where, &ri);
2981 } /* tc_bout_fix_to_chars() */
2983 #endif /* OBJ_AOUT or OBJ_BOUT */
2985 /* Align an address by rounding it up to the specified boundary.
2988 md_section_align (seg, addr)
2990 valueT addr; /* Address to be rounded up */
2992 return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
2993 } /* md_section_align() */
2997 tc_headers_hook (headers)
2998 object_headers *headers;
3000 /* FIXME: remove this line *//* unsigned short arch_flag = 0; */
3002 if (iclasses_seen == I_BASE)
3004 headers->filehdr.f_flags |= F_I960CORE;
3006 else if (iclasses_seen & I_CX)
3008 headers->filehdr.f_flags |= F_I960CA;
3010 else if (iclasses_seen & I_MIL)
3012 headers->filehdr.f_flags |= F_I960MC;
3014 else if (iclasses_seen & (I_DEC | I_FP))
3016 headers->filehdr.f_flags |= F_I960KB;
3020 headers->filehdr.f_flags |= F_I960KA;
3021 } /* set arch flag */
3025 headers->filehdr.f_magic = I960RWMAGIC;
3026 headers->aouthdr.magic = OMAGIC;
3030 headers->filehdr.f_magic = I960ROMAGIC;
3031 headers->aouthdr.magic = NMAGIC;
3032 } /* set magic numbers */
3035 } /* tc_headers_hook() */
3037 #endif /* OBJ_COFF */
3040 * Things going on here:
3042 * For bout, We need to assure a couple of simplifying
3043 * assumptions about leafprocs for the linker: the leafproc
3044 * entry symbols will be defined in the same assembly in
3045 * which they're declared with the '.leafproc' directive;
3046 * and if a leafproc has both 'call' and 'bal' entry points
3047 * they are both global or both local.
3049 * For coff, the call symbol has a second aux entry that
3050 * contains the bal entry point. The bal symbol becomes a
3053 * For coff representation, the call symbol has a second aux entry that
3054 * contains the bal entry point. The bal symbol becomes a label.
3059 tc_crawl_symbol_chain (headers)
3060 object_headers *headers;
3064 for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
3067 if (TC_S_IS_SYSPROC (symbolP))
3069 /* second aux entry already contains the sysproc number */
3070 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3071 S_SET_STORAGE_CLASS (symbolP, C_SCALL);
3072 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3074 } /* rewrite sysproc */
3075 #endif /* OBJ_COFF */
3077 if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
3080 } /* Not a leafproc symbol */
3082 if (!S_IS_DEFINED (symbolP))
3084 as_bad ("leafproc symbol '%s' undefined", S_GET_NAME (symbolP));
3085 } /* undefined leaf */
3087 if (TC_S_IS_CALLNAME (symbolP))
3089 symbolS *balP = tc_get_bal_of_call (symbolP);
3090 if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
3092 S_SET_EXTERNAL (symbolP);
3093 S_SET_EXTERNAL (balP);
3094 as_warn ("Warning: making leafproc entries %s and %s both global\n",
3095 S_GET_NAME (symbolP), S_GET_NAME (balP));
3096 } /* externality mismatch */
3098 } /* walk the symbol chain */
3101 } /* tc_crawl_symbol_chain() */
3104 * For aout or bout, the bal immediately follows the call.
3106 * For coff, we cheat and store a pointer to the bal symbol
3107 * in the second aux entry of the call.
3119 tc_set_bal_of_call (callP, balP)
3123 know (TC_S_IS_CALLNAME (callP));
3124 know (TC_S_IS_BALNAME (balP));
3128 callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP;
3129 S_SET_NUMBER_AUXILIARY (callP, 2);
3131 #else /* ! OBJ_COFF */
3134 /* If the 'bal' entry doesn't immediately follow the 'call'
3135 * symbol, unlink it from the symbol list and re-insert it.
3137 if (symbol_next (callP) != balP)
3139 symbol_remove (balP, &symbol_rootP, &symbol_lastP);
3140 symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
3141 } /* if not in order */
3143 #else /* ! OBJ_ABOUT */
3144 (as yet unwritten.);
3145 #endif /* ! OBJ_ABOUT */
3146 #endif /* ! OBJ_COFF */
3149 } /* tc_set_bal_of_call() */
3152 _tc_get_bal_of_call (callP)
3157 know (TC_S_IS_CALLNAME (callP));
3160 retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry);
3163 retval = symbol_next (callP);
3165 (as yet unwritten.);
3166 #endif /* ! OBJ_ABOUT */
3167 #endif /* ! OBJ_COFF */
3169 know (TC_S_IS_BALNAME (retval));
3170 return ((char *) retval);
3171 } /* _tc_get_bal_of_call() */
3174 tc_coff_symbol_emit_hook (symbolP)
3177 if (TC_S_IS_CALLNAME (symbolP))
3180 symbolS *balP = tc_get_bal_of_call (symbolP);
3182 /* second aux entry contains the bal entry point */
3183 /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */
3184 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
3185 S_SET_STORAGE_CLASS (symbolP, (!SF_GET_LOCAL (symbolP) ? C_LEAFEXT : C_LEAFSTAT));
3186 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3187 /* fix up the bal symbol */
3188 S_SET_STORAGE_CLASS (balP, C_LABEL);
3189 #endif /* OBJ_COFF */
3190 } /* only on calls */
3193 } /* tc_coff_symbol_emit_hook() */
3196 i960_handle_align (fragp)
3200 segT old_seg = now_seg, this_seg;
3201 int old_subseg = now_subseg;
3203 extern struct frag *text_last_frag, *data_last_frag;
3208 /* The text section "ends" with another alignment reloc, to which we
3209 aren't adding padding. */
3210 if (fragp->fr_next == text_last_frag
3211 || fragp->fr_next == data_last_frag)
3216 /* alignment directive */
3217 fixp = fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0, 0,
3218 (int) fragp->fr_type);
3221 /* end of tc-i960.c */