1 /* i960.c - All the i80960-specific stuff
2 Copyright (C) 1989, 1990, 1991 Free Software Foundation, Inc.
4 This file is part of GAS.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* See comment on md_parse_option for 80960-specific invocation options. */
24 /******************************************************************************
26 * Header, symbol, and relocation info will be used on the host machine
27 * only -- only executable code is actually downloaded to the i80960.
28 * Therefore, leave all such information in host byte order.
30 * (That's a slight lie -- we DO download some header information, but
31 * the downloader converts the file format and corrects the byte-ordering
32 * of the relevant fields while doing so.)
34 ***************************************************************************** */
36 /* There are 4 different lengths of (potentially) symbol-based displacements
37 * in the 80960 instruction set, each of which could require address fix-ups
38 * and (in the case of external symbols) emission of relocation directives:
41 * This is a standard length for the base assembler and requires no
45 * This is a non-standard length, but the base assembler has a hook for
46 * bit field address fixups: the fixS structure can point to a descriptor
47 * of the field, in which case our md_number_to_field() routine gets called
50 * I made the hook a little cleaner by having fix_new() (in the base
51 * assembler) return a pointer to the fixS in question. And I made it a
52 * little simpler by storing the field size (in this case 13) instead of
53 * of a pointer to another structure: 80960 displacements are ALWAYS
54 * stored in the low-order bits of a 4-byte word.
56 * Since the target of a COBR cannot be external, no relocation directives
57 * for this size displacement have to be generated. But the base assembler
58 * had to be modified to issue error messages if the symbol did turn out
62 * Fixups are handled as for the 13-bit case (except that 24 is stored
65 * The relocation directive generated is the same as that for the 32-bit
66 * displacement, except that it's PC-relative (the 32-bit displacement
67 * never is). The i80960 version of the linker needs a mod to
68 * distinguish and handle the 24-bit case.
71 * MEMA formats are always promoted to MEMB (32-bit) if the displacement
72 * is based on a symbol, because it could be relocated at link time.
73 * The only time we use the 12-bit format is if an absolute value of
74 * less than 4096 is specified, in which case we need neither a fixup nor
75 * a relocation directive.
85 #include "opcode/i960.h"
87 extern char *input_line_pointer;
88 extern struct hash_control *po_hash;
89 extern char *next_object_file_charP;
92 int md_reloc_size = sizeof(struct reloc);
94 int md_reloc_size = sizeof(struct relocation_info);
97 /***************************
98 * Local i80960 routines *
99 ************************** */
101 static void brcnt_emit(); /* Emit branch-prediction instrumentation code */
102 static char * brlab_next(); /* Return next branch local label */
103 void brtab_emit(); /* Emit br-predict instrumentation table */
104 static void cobr_fmt(); /* Generate COBR instruction */
105 static void ctrl_fmt(); /* Generate CTRL instruction */
106 static char * emit(); /* Emit (internally) binary */
107 static int get_args(); /* Break arguments out of comma-separated list */
108 static void get_cdisp(); /* Handle COBR or CTRL displacement */
109 static char * get_ispec(); /* Find index specification string */
110 static int get_regnum(); /* Translate text to register number */
111 static int i_scan(); /* Lexical scan of instruction source */
112 static void mem_fmt(); /* Generate MEMA or MEMB instruction */
113 static void mema_to_memb(); /* Convert MEMA instruction to MEMB format */
114 static segT parse_expr(); /* Parse an expression */
115 static int parse_ldconst();/* Parse and replace a 'ldconst' pseudo-op */
116 static void parse_memop(); /* Parse a memory operand */
117 static void parse_po(); /* Parse machine-dependent pseudo-op */
118 static void parse_regop(); /* Parse a register operand */
119 static void reg_fmt(); /* Generate a REG format instruction */
120 void reloc_callj(); /* Relocate a 'callj' instruction */
121 static void relax_cobr(); /* "De-optimize" cobr into compare/branch */
122 static void s_leafproc(); /* Process '.leafproc' pseudo-op */
123 static void s_sysproc(); /* Process '.sysproc' pseudo-op */
124 static int shift_ok(); /* Will a 'shlo' substiture for a 'ldconst'? */
125 static void syntax(); /* Give syntax error */
126 static int targ_has_sfr(); /* Target chip supports spec-func register? */
127 static int targ_has_iclass();/* Target chip supports instruction set? */
128 /* static void unlink_sym(); */ /* Remove a symbol from the symbol list */
130 /* See md_parse_option() for meanings of these options */
131 static char norelax = 0; /* True if -norelax switch seen */
132 static char instrument_branches = 0; /* True if -b switch seen */
134 /* Characters that always start a comment.
135 * If the pre-processor is disabled, these aren't very useful.
137 char comment_chars[] = "#";
139 /* Characters that only start a comment at the beginning of
140 * a line. If the line seems to have the form '# 123 filename'
141 * .line and .file directives will appear in the pre-processed output.
143 * Note that input_file.c hand checks for '#' at the beginning of the
144 * first line of the input file. This is because the compiler outputs
145 * #NO_APP at the beginning of its output.
148 /* Also note that comments started like this one will always work. */
150 char line_comment_chars[] = "";
152 /* Chars that can be used to separate mant from exp in floating point nums */
153 char EXP_CHARS[] = "eE";
155 /* Chars that mean this number is a floating point constant,
156 * as in 0f12.456 or 0d1.2345e12
158 char FLT_CHARS[] = "fFdDtT";
161 /* Table used by base assembler to relax addresses based on varying length
162 * instructions. The fields are:
163 * 1) most positive reach of this state,
164 * 2) most negative reach of this state,
165 * 3) how many bytes this mode will add to the size of the current frag
166 * 4) which index into the table to try if we can't fit into this one.
168 * For i80960, the only application is the (de-)optimization of cobr
169 * instructions into separate compare and branch instructions when a 13-bit
170 * displacement won't hack it.
174 {0, 0, 0,0}, /* State 0 => no more relaxation possible */
175 {4088, -4096, 0,2}, /* State 1: conditional branch (cobr) */
176 {0x800000-8,-0x800000,4,0}, /* State 2: compare (reg) & branch (ctrl) */
180 /* These are the machine dependent pseudo-ops.
182 * This table describes all the machine specific pseudo-ops the assembler
183 * has to support. The fields are:
184 * pseudo-op name without dot
185 * function to call to execute this pseudo-op
186 * integer arg to pass to the function
192 md_pseudo_table[] = {
194 { "bss", s_lcomm, 1 },
195 { "extended", float_cons, 't' },
196 { "leafproc", parse_po, S_LEAFPROC },
197 { "sysproc", parse_po, S_SYSPROC },
200 { "quad", big_cons, 16 },
205 /* Macros to extract info from an 'expressionS' structure 'e' */
206 #define adds(e) e.X_add_symbol
207 #define subs(e) e.X_subtract_symbol
208 #define offs(e) e.X_add_number
209 #define segs(e) e.X_seg
212 /* Branch-prediction bits for CTRL/COBR format opcodes */
213 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
214 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
215 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
218 /* Some instruction opcodes that we need explicitly */
219 #define BE 0x12000000
220 #define BG 0x11000000
221 #define BGE 0x13000000
222 #define BL 0x14000000
223 #define BLE 0x16000000
224 #define BNE 0x15000000
225 #define BNO 0x10000000
226 #define BO 0x17000000
227 #define CHKBIT 0x5a002700
228 #define CMPI 0x5a002080
229 #define CMPO 0x5a002000
232 #define BAL 0x0b000000
233 #define CALL 0x09000000
234 #define CALLS 0x66003800
235 #define RET 0x0a000000
238 /* These masks are used to build up a set of MEMB mode bits. */
241 #define MEMB_BIT 0x1000
245 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is used) */
246 #define MEMA_ABASE 0x2000
248 /* Info from which a MEMA or MEMB format instruction can be generated */
250 long opcode; /* (First) 32 bits of instruction */
251 int disp; /* 0-(none), 12- or, 32-bit displacement needed */
252 char *e; /* The expression in the source instruction from
253 * which the displacement should be determined
258 /* The two pieces of info we need to generate a register operand */
260 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
261 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
262 int n; /* Register number or literal value */
266 /* Number and assembler mnemonic for all registers that can appear in operands */
271 { "pfp", 0 }, { "sp", 1 }, { "rip", 2 }, { "r3", 3 },
272 { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 },
273 { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 },
274 { "r12", 12 }, { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
275 { "g0", 16 }, { "g1", 17 }, { "g2", 18 }, { "g3", 19 },
276 { "g4", 20 }, { "g5", 21 }, { "g6", 22 }, { "g7", 23 },
277 { "g8", 24 }, { "g9", 25 }, { "g10", 26 }, { "g11", 27 },
278 { "g12", 28 }, { "g13", 29 }, { "g14", 30 }, { "fp", 31 },
280 /* Numbers for special-function registers are for assembler internal
281 * use only: they are scaled back to range [0-31] for binary output.
285 { "sf0", 32 }, { "sf1", 33 }, { "sf2", 34 }, { "sf3", 35 },
286 { "sf4", 36 }, { "sf5", 37 }, { "sf6", 38 }, { "sf7", 39 },
287 { "sf8", 40 }, { "sf9", 41 }, { "sf10",42 }, { "sf11",43 },
288 { "sf12",44 }, { "sf13",45 }, { "sf14",46 }, { "sf15",47 },
289 { "sf16",48 }, { "sf17",49 }, { "sf18",50 }, { "sf19",51 },
290 { "sf20",52 }, { "sf21",53 }, { "sf22",54 }, { "sf23",55 },
291 { "sf24",56 }, { "sf25",57 }, { "sf26",58 }, { "sf27",59 },
292 { "sf28",60 }, { "sf29",61 }, { "sf30",62 }, { "sf31",63 },
294 /* Numbers for floating point registers are for assembler internal use
295 * only: they are scaled back to [0-3] for binary output.
299 { "fp0", 64 }, { "fp1", 65 }, { "fp2", 66 }, { "fp3", 67 },
301 { NULL, 0 }, /* END OF LIST */
304 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
305 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
306 #define IS_FP_REG(n) ((n) >= FP0)
308 /* Number and assembler mnemonic for all registers that can appear as 'abase'
309 * (indirect addressing) registers.
315 { "(pfp)", 0 }, { "(sp)", 1 }, { "(rip)", 2 }, { "(r3)", 3 },
316 { "(r4)", 4 }, { "(r5)", 5 }, { "(r6)", 6 }, { "(r7)", 7 },
317 { "(r8)", 8 }, { "(r9)", 9 }, { "(r10)", 10 }, { "(r11)", 11 },
318 { "(r12)", 12 }, { "(r13)", 13 }, { "(r14)", 14 }, { "(r15)", 15 },
319 { "(g0)", 16 }, { "(g1)", 17 }, { "(g2)", 18 }, { "(g3)", 19 },
320 { "(g4)", 20 }, { "(g5)", 21 }, { "(g6)", 22 }, { "(g7)", 23 },
321 { "(g8)", 24 }, { "(g9)", 25 }, { "(g10)", 26 }, { "(g11)", 27 },
322 { "(g12)", 28 }, { "(g13)", 29 }, { "(g14)", 30 }, { "(fp)", 31 },
325 /* for assembler internal use only: this number never appears in binary
330 { NULL, 0 }, /* END OF LIST */
335 static struct hash_control *op_hash = NULL; /* Opcode mnemonics */
336 static struct hash_control *reg_hash = NULL; /* Register name hash table */
337 static struct hash_control *areg_hash = NULL; /* Abase register hash table */
340 /* Architecture for which we are assembling */
341 #define ARCH_ANY 0 /* Default: no architecture checking done */
346 int architecture = ARCH_ANY; /* Architecture requested on invocation line */
347 int iclasses_seen = 0; /* OR of instruction classes (I_* constants)
348 * for which we've actually assembled
353 /* BRANCH-PREDICTION INSTRUMENTATION
355 * The following supports generation of branch-prediction instrumentation
356 * (turned on by -b switch). The instrumentation collects counts
357 * of branches taken/not-taken for later input to a utility that will
358 * set the branch prediction bits of the instructions in accordance with
359 * the behavior observed. (Note that the KX series does not have
362 * The instrumentation consists of:
364 * (1) before and after each conditional branch, a call to an external
365 * routine that increments and steps over an inline counter. The
366 * counter itself, initialized to 0, immediately follows the call
367 * instruction. For each branch, the counter following the branch
368 * is the number of times the branch was not taken, and the difference
369 * between the counters is the number of times it was taken. An
370 * example of an instrumented conditional branch:
374 * LBRANCH23: be label
378 * (2) a table of pointers to the instrumented branches, so that an
379 * external postprocessing routine can locate all of the counters.
380 * the table begins with a 2-word header: a pointer to the next in
381 * a linked list of such tables (initialized to 0); and a count
382 * of the number of entries in the table (exclusive of the header.
384 * Note that input source code is expected to already contain calls
385 * an external routine that will link the branch local table into a
386 * list of such tables.
389 static int br_cnt = 0; /* Number of branches instrumented so far.
390 * Also used to generate unique local labels
391 * for each instrumented branch
394 #define BR_LABEL_BASE "LBRANCH"
395 /* Basename of local labels on instrumented
396 * branches, to avoid conflict with compiler-
397 * generated local labels.
400 #define BR_CNT_FUNC "__inc_branch"
401 /* Name of the external routine that will
402 * increment (and step over) an inline counter.
405 #define BR_TAB_NAME "__BRANCH_TABLE__"
406 /* Name of the table of pointers to branches.
407 * A local (i.e., non-external) symbol.
410 /*****************************************************************************
411 * md_begin: One-time initialization.
413 * Set up hash tables.
415 **************************************************************************** */
419 int i; /* Loop counter */
420 const struct i960_opcode *oP; /* Pointer into opcode table */
421 char *retval; /* Value returned by hash functions */
423 if (((op_hash = hash_new()) == 0)
424 || ((reg_hash = hash_new()) == 0)
425 || ((areg_hash = hash_new()) == 0)) {
426 as_fatal("virtual memory exceeded");
429 retval = ""; /* For some reason, the base assembler uses an empty
430 * string for "no error message", instead of a NULL
434 for (oP=i960_opcodes; oP->name && !*retval; oP++) {
435 retval = hash_insert(op_hash, oP->name, oP);
438 for (i=0; regnames[i].reg_name && !*retval; i++) {
439 retval = hash_insert(reg_hash, regnames[i].reg_name,
440 ®names[i].reg_num);
443 for (i=0; aregs[i].areg_name && !*retval; i++){
444 retval = hash_insert(areg_hash, aregs[i].areg_name,
449 as_fatal("Hashing returned \"%s\".", retval);
453 /*****************************************************************************
454 * md_end: One-time final cleanup
458 **************************************************************************** */
464 /*****************************************************************************
465 * md_assemble: Assemble an instruction
467 * Assumptions about the passed-in text:
468 * - all comments, labels removed
469 * - text is an instruction
470 * - all white space compressed to single blanks
471 * - all character constants have been replaced with decimal
473 **************************************************************************** */
476 char *textP; /* Source text of instruction */
478 char *args[4]; /* Parsed instruction text, containing NO whitespace:
479 * arg[0]->opcode mnemonic
480 * arg[1-3]->operands, with char constants
481 * replaced by decimal numbers
483 int n_ops; /* Number of instruction operands */
485 struct i960_opcode *oP;
486 /* Pointer to instruction description */
488 /* TRUE iff opcode mnemonic included branch-prediction
489 * suffix (".f" or ".t")
491 long bp_bits; /* Setting of branch-prediction bit(s) to be OR'd
492 * into instruction opcode of CTRL/COBR format
495 int n; /* Offset of last character in opcode mnemonic */
497 static const char bp_error_msg[] = "branch prediction invalid on this opcode";
500 /* Parse instruction into opcode and operands */
501 bzero(args, sizeof(args));
502 n_ops = i_scan(textP, args);
504 return; /* Error message already issued */
507 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
508 if (!strcmp(args[0],"ldconst")){
509 n_ops = parse_ldconst(args);
515 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
516 n = strlen(args[0]) - 1;
519 if (args[0][n-1] == '.' && (args[0][n] == 't' || args[0][n] == 'f')){
520 /* We could check here to see if the target architecture
521 * supports branch prediction, but why bother? The bit
522 * will just be ignored by processors that don't use it.
525 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
526 args[0][n-1] = '\0'; /* Strip suffix from opcode mnemonic */
529 /* Look up opcode mnemonic in table and check number of operands.
530 * Check that opcode is legal for the target architecture.
531 * If all looks good, assemble instruction.
533 oP = (struct i960_opcode *) hash_find(op_hash, args[0]);
534 if (!oP || !targ_has_iclass(oP->iclass)) {
535 as_bad("invalid opcode, \"%s\".", args[0]);
537 } else if (n_ops != oP->num_ops) {
538 as_bad("improper number of operands. expecting %d, got %d", oP->num_ops, n_ops);
544 ctrl_fmt(args[1], oP->opcode | bp_bits, oP->num_ops);
545 if (oP->format == FBRA){
546 /* Now generate a 'bno' to same arg */
547 ctrl_fmt(args[1], BNO | bp_bits, 1);
552 cobr_fmt(args, oP->opcode | bp_bits, oP);
556 as_warn(bp_error_msg);
567 as_warn(bp_error_msg);
573 as_warn(bp_error_msg);
575 /* Output opcode & set up "fixup" (relocation);
576 * flag relocation as 'callj' type.
578 know(oP->num_ops == 1);
579 get_cdisp(args[1], "CTRL", oP->opcode, 24, 0, 1);
582 BAD_CASE(oP->format);
586 } /* md_assemble() */
588 /*****************************************************************************
589 * md_number_to_chars: convert a number to target byte order
591 **************************************************************************** */
593 md_number_to_chars(buf, value, n)
594 char *buf; /* Put output here */
595 long value; /* The integer to be converted */
596 int n; /* Number of bytes to output (significant bytes
605 /* XXX line number probably botched for this warning message. */
606 if (value != 0 && value != -1){
607 as_bad("Displacement too long for instruction field length.");
611 } /* md_number_to_chars() */
613 /*****************************************************************************
614 * md_chars_to_number: convert from target byte order to host byte order.
616 **************************************************************************** */
618 md_chars_to_number(val, n)
619 unsigned char *val; /* Value in target byte order */
620 int n; /* Number of bytes in the input */
624 for (retval=0; n--;){
632 #define MAX_LITTLENUMS 6
633 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
635 /*****************************************************************************
636 * md_atof: convert ascii to floating point
638 * Turn a string at input_line_pointer into a floating point constant of type
639 * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
640 * emitted is returned at 'sizeP'. An error message is returned, or a pointer
641 * to an empty message if OK.
643 * Note we call the i386 floating point routine, rather than complicating
644 * things with more files or symbolic links.
646 **************************************************************************** */
647 char * md_atof(type, litP, sizeP)
652 LITTLENUM_TYPE words[MAX_LITTLENUMS];
653 LITTLENUM_TYPE *wordP;
672 type = 'x'; /* That's what atof_ieee() understands */
677 return "Bad call to md_atof()";
680 t = atof_ieee(input_line_pointer, type, words);
682 input_line_pointer = t;
685 *sizeP = prec * LNUM_SIZE;
687 /* Output the LITTLENUMs in REVERSE order in accord with i80960
688 * word-order. (Dunno why atof_ieee doesn't do it in the right
689 * order in the first place -- probably because it's a hack of
693 for(wordP = words + prec - 1; prec--;){
694 md_number_to_chars(litP, (long) (*wordP--), LNUM_SIZE);
695 litP += sizeof(LITTLENUM_TYPE);
698 return ""; /* Someone should teach Dean about null pointers */
702 /*****************************************************************************
705 **************************************************************************** */
707 md_number_to_imm(buf, val, n)
712 md_number_to_chars(buf, val, n);
716 /*****************************************************************************
719 **************************************************************************** */
721 md_number_to_disp(buf, val, n)
726 md_number_to_chars(buf, val, n);
729 /*****************************************************************************
730 * md_number_to_field:
732 * Stick a value (an address fixup) into a bit field of
733 * previously-generated instruction.
735 **************************************************************************** */
737 md_number_to_field(instrP, val, bfixP)
738 char *instrP; /* Pointer to instruction to be fixed */
739 long val; /* Address fixup value */
740 bit_fixS *bfixP; /* Description of bit field to be fixed up */
742 int numbits; /* Length of bit field to be fixed */
743 long instr; /* 32-bit instruction to be fixed-up */
744 long sign; /* 0 or -1, according to sign bit of 'val' */
746 /* Convert instruction back to host byte order
748 instr = md_chars_to_number(instrP, 4);
750 /* Surprise! -- we stored the number of bits
751 * to be modified rather than a pointer to a structure.
753 numbits = (int)bfixP;
755 /* This is a no-op, stuck here by reloc_callj() */
759 know ((numbits==13) || (numbits==24));
761 /* Propagate sign bit of 'val' for the given number of bits.
762 * Result should be all 0 or all 1
764 sign = val >> ((int)numbits - 1);
765 if (((val < 0) && (sign != -1))
766 || ((val > 0) && (sign != 0))){
767 as_bad("Fixup of %d too large for field width of %d",
770 /* Put bit field into instruction and write back in target
773 val &= ~(-1 << (int)numbits); /* Clear unused sign bits */
775 md_number_to_chars(instrP, instr, 4);
777 } /* md_number_to_field() */
780 /*****************************************************************************
782 * Invocation line includes a switch not recognized by the base assembler.
783 * See if it's a processor-specific option. For the 960, these are:
786 * Conditional branch instructions that require displacements
787 * greater than 13 bits (or that have external targets) should
788 * generate errors. The default is to replace each such
789 * instruction with the corresponding compare (or chkbit) and
790 * branch instructions. Note that the Intel "j" cobr directives
791 * are ALWAYS "de-optimized" in this way when necessary,
792 * regardless of the setting of this option.
795 * Add code to collect information about branches taken, for
796 * later optimization of branch prediction bits by a separate
797 * tool. COBR and CNTL format instructions have branch
798 * prediction bits (in the CX architecture); if "BR" represents
799 * an instruction in one of these classes, the following rep-
800 * resents the code generated by the assembler:
802 * call <increment routine>
803 * .word 0 # pre-counter
805 * call <increment routine>
806 * .word 0 # post-counter
808 * A table of all such "Labels" is also generated.
811 * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
812 * Select the 80960 architecture. Instructions or features not
813 * supported by the selected architecture cause fatal errors.
814 * The default is to generate code for any instruction or feature
815 * that is supported by SOME version of the 960 (even if this
816 * means mixing architectures!).
818 **************************************************************************** */
820 md_parse_option(argP, cntP, vecP)
826 struct tabentry { char *flag; int arch; };
827 static struct tabentry arch_tab[] = {
830 "SA", ARCH_KA, /* Synonym for KA */
831 "SB", ARCH_KB, /* Synonym for KB */
832 "KC", ARCH_MC, /* Synonym for MC */
839 if (!strcmp(*argP,"norelax")){
842 } else if (**argP == 'b'){
843 instrument_branches = 1;
845 } else if (**argP == 'A'){
848 for (tp = arch_tab; tp->flag != NULL; tp++){
849 if (!strcmp(p,tp->flag)){
854 if (tp->flag == NULL){
855 as_bad("unknown architecture: %s", p);
857 architecture = tp->arch;
864 **argP = '\0'; /* Done parsing this switch */
868 /*****************************************************************************
870 * Called by base assembler after address relaxation is finished: modify
871 * variable fragments according to how much relaxation was done.
873 * If the fragment substate is still 1, a 13-bit displacement was enough
874 * to reach the symbol in question. Set up an address fixup, but otherwise
875 * leave the cobr instruction alone.
877 * If the fragment substate is 2, a 13-bit displacement was not enough.
878 * Replace the cobr with a two instructions (a compare and a branch).
880 **************************************************************************** */
882 md_convert_frag(headers, fragP)
883 object_headers *headers;
886 fixS *fixP; /* Structure describing needed address fix */
888 switch (fragP->fr_subtype){
890 /* LEAVE SINGLE COBR INSTRUCTION */
891 fixP = fix_new(fragP,
892 fragP->fr_opcode-fragP->fr_literal,
900 fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */
903 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
907 BAD_CASE(fragP->fr_subtype);
912 /*****************************************************************************
913 * md_estimate_size_before_relax: How much does it look like *fragP will grow?
915 * Called by base assembler just before address relaxation.
916 * Return the amount by which the fragment will grow.
918 * Any symbol that is now undefined will not become defined; cobr's
919 * based on undefined symbols will have to be replaced with a compare
920 * instruction and a branch instruction, and the code fragment will grow
923 **************************************************************************** */
925 md_estimate_size_before_relax(fragP, segment_type)
926 register fragS *fragP;
927 register segT segment_type;
929 /* If symbol is undefined in this segment, go to "relaxed" state
930 * (compare and branch instructions instead of cobr) right now.
932 if (S_GET_SEGMENT(fragP->fr_symbol) != segment_type) {
937 } /* md_estimate_size_before_relax() */
940 /*****************************************************************************
942 * This routine exists in order to overcome machine byte-order problems
943 * when dealing with bit-field entries in the relocation_info struct.
945 * But relocation info will be used on the host machine only (only
946 * executable code is actually downloaded to the i80960). Therefore,
947 * we leave it in host byte order.
949 **************************************************************************** */
950 void md_ri_to_chars(where, ri)
952 struct relocation_info *ri;
954 *((struct relocation_info *) where) = *ri; /* structure assignment */
955 } /* md_ri_to_chars() */
957 #ifndef WORKING_DOT_WORD
959 int md_short_jump_size = 0;
960 int md_long_jump_size = 0;
962 void md_create_short_jump(ptr, from_addr, to_addr, frag, to_symbol)
969 as_fatal("failed sanity check.");
973 md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol)
975 long from_addr, to_addr;
979 as_fatal("failed sanity check.");
983 /*************************************************************
985 * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER *
987 ************************************************************ */
991 /*****************************************************************************
992 * brcnt_emit: Emit code to increment inline branch counter.
994 * See the comments above the declaration of 'br_cnt' for details on
995 * branch-prediction instrumentation.
996 **************************************************************************** */
1000 ctrl_fmt(BR_CNT_FUNC,CALL,1);/* Emit call to "increment" routine */
1001 emit(0); /* Emit inline counter to be incremented */
1004 /*****************************************************************************
1005 * brlab_next: generate the next branch local label
1007 * See the comments above the declaration of 'br_cnt' for details on
1008 * branch-prediction instrumentation.
1009 **************************************************************************** */
1013 static char buf[20];
1015 sprintf(buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1019 /*****************************************************************************
1020 * brtab_emit: generate the fetch-prediction branch table.
1022 * See the comments above the declaration of 'br_cnt' for details on
1023 * branch-prediction instrumentation.
1025 * The code emitted here would be functionally equivalent to the following
1026 * example assembler source.
1031 * .word 0 # link to next table
1032 * .word 3 # length of table
1033 * .word LBRANCH0 # 1st entry in table proper
1036 ***************************************************************************** */
1042 char *p; /* Where the binary was output to */
1043 fixS *fixP; /*->description of deferred address fixup */
1045 if (!instrument_branches){
1049 subseg_new(SEG_DATA,0); /* .data */
1050 frag_align(2,0); /* .align 2 */
1051 record_alignment(now_seg,2);
1052 colon(BR_TAB_NAME); /* BR_TAB_NAME: */
1053 emit(0); /* .word 0 #link to next table */
1054 emit(br_cnt); /* .word n #length of table */
1056 for (i=0; i<br_cnt; i++){
1057 sprintf(buf, "%s%d", BR_LABEL_BASE, i);
1059 fixP = fix_new(frag_now,
1060 p - frag_now->fr_literal,
1067 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1071 /*****************************************************************************
1072 * cobr_fmt: generate a COBR-format instruction
1074 **************************************************************************** */
1077 cobr_fmt(arg, opcode, oP)
1078 char *arg[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1079 long opcode; /* Opcode, with branch-prediction bits already set
1082 struct i960_opcode *oP;
1083 /*->description of instruction */
1085 long instr; /* 32-bit instruction */
1086 struct regop regop; /* Description of register operand */
1087 int n; /* Number of operands */
1088 int var_frag; /* 1 if varying length code fragment should
1089 * be emitted; 0 if an address fix
1090 * should be emitted.
1097 /* First operand (if any) of a COBR is always a register
1098 * operand. Parse it.
1100 parse_regop(®op, arg[1], oP->operand[0]);
1101 instr |= (regop.n << 19) | (regop.mode << 13);
1104 /* Second operand (if any) of a COBR is always a register
1105 * operand. Parse it.
1107 parse_regop(®op, arg[2], oP->operand[1]);
1108 instr |= (regop.n << 14) | regop.special;
1116 if (instrument_branches){
1118 colon(brlab_next());
1121 /* A third operand to a COBR is always a displacement.
1122 * Parse it; if it's relaxable (a cobr "j" directive, or any
1123 * cobr other than bbs/bbc when the "-norelax" option is not in
1124 * use) set up a variable code fragment; otherwise set up an
1127 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1128 get_cdisp(arg[3], "COBR", instr, 13, var_frag, 0);
1130 if (instrument_branches){
1137 /*****************************************************************************
1138 * ctrl_fmt: generate a CTRL-format instruction
1140 **************************************************************************** */
1143 ctrl_fmt(targP, opcode, num_ops)
1144 char *targP; /* Pointer to text of lone operand (if any) */
1145 long opcode; /* Template of instruction */
1146 int num_ops; /* Number of operands */
1148 int instrument; /* TRUE iff we should add instrumentation to track
1149 * how often the branch is taken
1154 emit(opcode); /* Output opcode */
1157 instrument = instrument_branches && (opcode!=CALL)
1158 && (opcode!=B) && (opcode!=RET) && (opcode!=BAL);
1162 colon(brlab_next());
1165 /* The operand MUST be an ip-relative displacment. Parse it
1166 * and set up address fix for the instruction we just output.
1168 get_cdisp(targP, "CTRL", opcode, 24, 0, 0);
1178 /*****************************************************************************
1179 * emit: output instruction binary
1181 * Output instruction binary, in target byte order, 4 bytes at a time.
1182 * Return pointer to where it was placed.
1184 **************************************************************************** */
1188 long instr; /* Word to be output, host byte order */
1190 char *toP; /* Where to output it */
1192 toP = frag_more(4); /* Allocate storage */
1193 md_number_to_chars(toP, instr, 4); /* Convert to target byte order */
1198 /*****************************************************************************
1199 * get_args: break individual arguments out of comma-separated list
1201 * Input assumptions:
1202 * - all comments and labels have been removed
1203 * - all strings of whitespace have been collapsed to a single blank.
1204 * - all character constants ('x') have been replaced with decimal
1207 * args[0] is untouched. args[1] points to first operand, etc. All args:
1208 * - are NULL-terminated
1209 * - contain no whitespace
1212 * Number of operands (0,1,2, or 3) or -1 on error.
1214 **************************************************************************** */
1215 static int get_args(p, args)
1216 register char *p; /* Pointer to comma-separated operands; MUCKED BY US */
1217 char *args[]; /* Output arg: pointers to operands placed in args[1-3].
1218 * MUST ACCOMMODATE 4 ENTRIES (args[0-3]).
1221 register int n; /* Number of operands */
1227 /* Skip lead white space */
1239 /* Squeze blanks out by moving non-blanks toward start of string.
1240 * Isolate operands, whenever comma is found.
1248 } else if (*p == ','){
1250 /* Start of operand */
1252 as_bad("too many operands");
1255 *to++ = '\0'; /* Terminate argument */
1256 args[++n] = to; /* Start next argument */
1268 /*****************************************************************************
1269 * get_cdisp: handle displacement for a COBR or CTRL instruction.
1271 * Parse displacement for a COBR or CTRL instruction.
1273 * If successful, output the instruction opcode and set up for it,
1274 * depending on the arg 'var_frag', either:
1275 * o an address fixup to be done when all symbol values are known, or
1276 * o a varying length code fragment, with address fixup info. This
1277 * will be done for cobr instructions that may have to be relaxed
1278 * in to compare/branch instructions (8 bytes) if the final address
1279 * displacement is greater than 13 bits.
1281 **************************************************************************** */
1284 get_cdisp(dispP, ifmtP, instr, numbits, var_frag, callj)
1285 char *dispP; /*->displacement as specified in source instruction */
1286 char *ifmtP; /*->"COBR" or "CTRL" (for use in error message) */
1287 long instr; /* Instruction needing the displacement */
1288 int numbits; /* # bits of displacement (13 for COBR, 24 for CTRL) */
1289 int var_frag; /* 1 if varying length code fragment should be emitted;
1290 * 0 if an address fix should be emitted.
1292 int callj; /* 1 if callj relocation should be done; else 0 */
1294 expressionS e; /* Parsed expression */
1295 fixS *fixP; /* Structure describing needed address fix */
1296 char *outP; /* Where instruction binary is output to */
1300 switch (parse_expr(dispP,&e)) {
1303 as_bad("expression syntax error");
1309 outP = frag_more(8); /* Allocate worst-case storage */
1310 md_number_to_chars(outP, instr, 4);
1311 frag_variant(rs_machine_dependent, 4, 4, 1,
1312 adds(e), offs(e), outP, 0, 0);
1314 /* Set up a new fix structure, so address can be updated
1315 * when all symbol values are known.
1318 fixP = fix_new(frag_now,
1319 outP - frag_now->fr_literal,
1327 fixP->fx_callj = callj;
1329 /* We want to modify a bit field when the address is
1330 * known. But we don't need all the garbage in the
1331 * bit_fix structure. So we're going to lie and store
1332 * the number of bits affected instead of a pointer.
1334 fixP->fx_bit_fixP = (bit_fixS *) numbits;
1340 as_bad("attempt to branch into different segment");
1344 as_bad("target of %s instruction must be a label", ifmtP);
1350 /*****************************************************************************
1351 * get_ispec: parse a memory operand for an index specification
1353 * Here, an "index specification" is taken to be anything surrounded
1354 * by square brackets and NOT followed by anything else.
1356 * If it's found, detach it from the input string, remove the surrounding
1357 * square brackets, and return a pointer to it. Otherwise, return NULL.
1359 **************************************************************************** */
1363 char *textP; /*->memory operand from source instruction, no white space */
1365 char *start; /*->start of index specification */
1366 char *end; /*->end of index specification */
1368 /* Find opening square bracket, if any
1370 start = strchr(textP, '[');
1374 /* Eliminate '[', detach from rest of operand */
1377 end = strchr(start, ']');
1380 as_bad("unmatched '['");
1383 /* Eliminate ']' and make sure it was the last thing
1387 if (*(end+1) != '\0'){
1388 as_bad("garbage after index spec ignored");
1395 /*****************************************************************************
1398 * Look up a (suspected) register name in the register table and return the
1399 * associated register number (or -1 if not found).
1401 **************************************************************************** */
1405 char *regname; /* Suspected register name */
1409 rP = (int *) hash_find(reg_hash, regname);
1410 return (rP == NULL) ? -1 : *rP;
1414 /*****************************************************************************
1415 * i_scan: perform lexical scan of ascii assembler instruction.
1417 * Input assumptions:
1418 * - input string is an i80960 instruction (not a pseudo-op)
1419 * - all comments and labels have been removed
1420 * - all strings of whitespace have been collapsed to a single blank.
1423 * args[0] points to opcode, other entries point to operands. All strings:
1424 * - are NULL-terminated
1425 * - contain no whitespace
1426 * - have character constants ('x') replaced with a decimal number
1429 * Number of operands (0,1,2, or 3) or -1 on error.
1431 **************************************************************************** */
1432 static int i_scan(iP, args)
1433 register char *iP; /* Pointer to ascii instruction; MUCKED BY US. */
1434 char *args[]; /* Output arg: pointers to opcode and operands placed
1435 * here. MUST ACCOMMODATE 4 ENTRIES.
1439 /* Isolate opcode */
1442 } /* Skip lead space, if any */
1444 for (; *iP != ' '; iP++) {
1446 /* There are no operands */
1447 if (args[0] == iP) {
1448 /* We never moved: there was no opcode either! */
1449 as_bad("missing opcode");
1455 *iP++ = '\0'; /* Terminate opcode */
1456 return(get_args(iP, args));
1460 /*****************************************************************************
1461 * mem_fmt: generate a MEMA- or MEMB-format instruction
1463 **************************************************************************** */
1464 static void mem_fmt(args, oP)
1465 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1466 struct i960_opcode *oP; /* Pointer to description of instruction */
1468 int i; /* Loop counter */
1469 struct regop regop; /* Description of register operand */
1470 char opdesc; /* Operand descriptor byte */
1471 memS instr; /* Description of binary to be output */
1472 char *outP; /* Where the binary was output to */
1473 expressionS expr; /* Parsed expression */
1474 fixS *fixP; /*->description of deferred address fixup */
1476 bzero(&instr, sizeof(memS));
1477 instr.opcode = oP->opcode;
1479 /* Process operands. */
1480 for (i = 1; i <= oP->num_ops; i++){
1481 opdesc = oP->operand[i-1];
1484 parse_memop(&instr, args[i], oP->format);
1486 parse_regop(®op, args[i], opdesc);
1487 instr.opcode |= regop.n << 19;
1492 outP = emit(instr.opcode);
1494 if (instr.disp == 0){
1498 /* Parse and process the displacement */
1499 switch (parse_expr(instr.e,&expr)){
1502 as_bad("expression syntax error");
1506 if (instr.disp == 32){
1507 (void) emit(offs(expr)); /* Output displacement */
1509 /* 12-bit displacement */
1510 if (offs(expr) & ~0xfff){
1511 /* Won't fit in 12 bits: convert already-output
1512 * instruction to MEMB format, output
1516 (void) emit(offs(expr));
1518 /* WILL fit in 12 bits: OR into opcode and
1519 * overwrite the binary we already put out
1521 instr.opcode |= offs(expr);
1522 md_number_to_chars(outP, instr.opcode, 4);
1527 case SEG_DIFFERENCE:
1532 if (instr.disp == 12){
1533 /* Displacement is dependent on a symbol, whose value
1534 * may change at link time. We HAVE to reserve 32 bits.
1535 * Convert already-output opcode to MEMB format.
1540 /* Output 0 displacement and set up address fixup for when
1541 * this symbol's value becomes known.
1543 outP = emit((long) 0);
1544 fixP = fix_new(frag_now,
1545 outP - frag_now->fr_literal,
1552 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1556 BAD_CASE(segs(expr));
1562 /*****************************************************************************
1563 * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1565 * There are 2 possible MEMA formats:
1566 * - displacement only
1567 * - displacement + abase
1569 * They are distinguished by the setting of the MEMA_ABASE bit.
1571 **************************************************************************** */
1572 static void mema_to_memb(opcodeP)
1573 char *opcodeP; /* Where to find the opcode, in target byte order */
1575 long opcode; /* Opcode in host byte order */
1576 long mode; /* Mode bits for MEMB instruction */
1578 opcode = md_chars_to_number(opcodeP, 4);
1579 know(!(opcode & MEMB_BIT));
1581 mode = MEMB_BIT | D_BIT;
1582 if (opcode & MEMA_ABASE){
1586 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */
1587 opcode |= mode; /* Set MEMB mode bits */
1589 md_number_to_chars(opcodeP, opcode, 4);
1590 } /* mema_to_memb() */
1593 /*****************************************************************************
1594 * parse_expr: parse an expression
1596 * Use base assembler's expression parser to parse an expression.
1597 * It, unfortunately, runs off a global which we have to save/restore
1598 * in order to make it work for us.
1600 * An empty expression string is treated as an absolute 0.
1602 * Return "segment" to which the expression evaluates.
1603 * Return SEG_GOOF regardless of expression evaluation if entire input
1604 * string is not consumed in the evaluation -- tolerate no dangling junk!
1606 **************************************************************************** */
1609 parse_expr(textP, expP)
1610 char *textP; /* Text of expression to be parsed */
1611 expressionS *expP; /* Where to put the results of parsing */
1613 char *save_in; /* Save global here */
1614 segT seg; /* Segment to which expression evaluates */
1619 if (*textP == '\0') {
1620 /* Treat empty string as absolute 0 */
1621 expP->X_add_symbol = expP->X_subtract_symbol = NULL;
1622 expP->X_add_number = 0;
1623 seg = expP->X_seg = SEG_ABSOLUTE;
1626 save_in = input_line_pointer; /* Save global */
1627 input_line_pointer = textP; /* Make parser work for us */
1629 seg = expression(expP);
1630 if (input_line_pointer - textP != strlen(textP)) {
1631 /* Did not consume all of the input */
1634 symP = expP->X_add_symbol;
1635 if (symP && (hash_find(reg_hash, S_GET_NAME(symP)))) {
1636 /* Register name in an expression */
1640 input_line_pointer = save_in; /* Restore global */
1646 /*****************************************************************************
1648 * Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1649 * i80960 instruction.
1651 * Assumes the input consists of:
1652 * arg[0] opcode mnemonic ('ldconst')
1653 * arg[1] first operand (constant)
1654 * arg[2] name of register to be loaded
1656 * Replaces opcode and/or operands as appropriate.
1658 * Returns the new number of arguments, or -1 on failure.
1660 **************************************************************************** */
1664 char *arg[]; /* See above */
1666 int n; /* Constant to be loaded */
1667 int shift; /* Shift count for "shlo" instruction */
1668 static char buf[5]; /* Literal for first operand */
1669 static char buf2[5]; /* Literal for second operand */
1670 expressionS e; /* Parsed expression */
1673 arg[3] = NULL; /* So we can tell at the end if it got used or not */
1675 switch(parse_expr(arg[1],&e)){
1681 case SEG_DIFFERENCE:
1682 /* We're dependent on one or more symbols -- use "lda" */
1687 /* Try the following mappings:
1688 * ldconst 0,<reg> ->mov 0,<reg>
1689 * ldconst 31,<reg> ->mov 31,<reg>
1690 * ldconst 32,<reg> ->addo 1,31,<reg>
1691 * ldconst 62,<reg> ->addo 31,31,<reg>
1692 * ldconst 64,<reg> ->shlo 8,3,<reg>
1693 * ldconst -1,<reg> ->subo 1,0,<reg>
1694 * ldconst -31,<reg>->subo 31,0,<reg>
1696 * anthing else becomes:
1700 if ((0 <= n) && (n <= 31)){
1703 } else if ((-31 <= n) && (n <= -1)){
1706 sprintf(buf, "%d", -n);
1710 } else if ((32 <= n) && (n <= 62)){
1714 sprintf(buf, "%d", n-31);
1717 } else if ((shift = shift_ok(n)) != 0){
1720 sprintf(buf, "%d", shift);
1722 sprintf(buf2, "%d", n >> shift);
1731 as_bad("invalid constant");
1735 return (arg[3] == 0) ? 2: 3;
1738 /*****************************************************************************
1739 * parse_memop: parse a memory operand
1741 * This routine is based on the observation that the 4 mode bits of the
1742 * MEMB format, taken individually, have fairly consistent meaning:
1744 * M3 (bit 13): 1 if displacement is present (D_BIT)
1745 * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1746 * M1 (bit 11): 1 if index is present (I_BIT)
1747 * M0 (bit 10): 1 if abase is present (A_BIT)
1749 * So we parse the memory operand and set bits in the mode as we find
1750 * things. Then at the end, if we go to MEMB format, we need only set
1751 * the MEMB bit (M2) and our mode is built for us.
1753 * Unfortunately, I said "fairly consistent". The exceptions:
1756 * 0100 Would seem illegal, but means "abase-only".
1758 * 0101 Would seem to mean "abase-only" -- it means IP-relative.
1759 * Must be converted to 0100.
1761 * 0110 Would seem to mean "index-only", but is reserved.
1762 * We turn on the D bit and provide a 0 displacement.
1764 * The other thing to observe is that we parse from the right, peeling
1765 * things * off as we go: first any index spec, then any abase, then
1768 **************************************************************************** */
1771 parse_memop(memP, argP, optype)
1772 memS *memP; /* Where to put the results */
1773 char *argP; /* Text of the operand to be parsed */
1774 int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
1776 char *indexP; /* Pointer to index specification with "[]" removed */
1777 char *p; /* Temp char pointer */
1778 char iprel_flag;/* True if this is an IP-relative operand */
1779 int regnum; /* Register number */
1780 int scale; /* Scale factor: 1,2,4,8, or 16. Later converted
1781 * to internal format (0,1,2,3,4 respectively).
1783 int mode; /* MEMB mode bits */
1784 int *intP; /* Pointer to register number */
1786 /* The following table contains the default scale factors for each
1787 * type of memory instruction. It is accessed using (optype-MEM1)
1788 * as an index -- thus it assumes the 'optype' constants are assigned
1789 * consecutive values, in the order they appear in this table
1791 static int def_scale[] = {
1796 -1, /* MEM12 -- no valid default */
1801 iprel_flag = mode = 0;
1803 /* Any index present? */
1804 indexP = get_ispec(argP);
1806 p = strchr(indexP, '*');
1808 /* No explicit scale -- use default for this
1811 scale = def_scale[ optype - MEM1 ];
1813 *p++ = '\0'; /* Eliminate '*' */
1815 /* Now indexP->a '\0'-terminated register name,
1816 * and p->a scale factor.
1819 if (!strcmp(p,"16")){
1821 } else if (strchr("1248",*p) && (p[1] == '\0')){
1828 regnum = get_regnum(indexP); /* Get index reg. # */
1829 if (!IS_RG_REG(regnum)){
1830 as_bad("invalid index register");
1834 /* Convert scale to its binary encoding */
1836 case 1: scale = 0 << 7; break;
1837 case 2: scale = 1 << 7; break;
1838 case 4: scale = 2 << 7; break;
1839 case 8: scale = 3 << 7; break;
1840 case 16: scale = 4 << 7; break;
1841 default: as_bad("invalid scale factor"); return;
1844 memP->opcode |= scale | regnum; /* Set index bits in opcode */
1845 mode |= I_BIT; /* Found a valid index spec */
1848 /* Any abase (Register Indirect) specification present? */
1849 if ((p = strrchr(argP,'(')) != NULL) {
1850 /* "(" is there -- does it start a legal abase spec?
1851 * (If not it could be part of a displacement expression.)
1853 intP = (int *) hash_find(areg_hash, p);
1855 /* Got an abase here */
1857 *p = '\0'; /* discard register spec */
1858 if (regnum == IPREL){
1859 /* We have to specialcase ip-rel mode */
1862 memP->opcode |= regnum << 14;
1868 /* Any expression present? */
1874 /* Special-case ip-relative addressing */
1879 memP->opcode |= 5 << 10; /* IP-relative mode */
1885 /* Handle all other modes */
1888 /* Go with MEMA instruction format for now (grow to MEMB later
1889 * if 12 bits is not enough for the displacement).
1890 * MEMA format has a single mode bit: set it to indicate
1891 * that abase is present.
1893 memP->opcode |= MEMA_ABASE;
1898 /* Go with MEMA instruction format for now (grow to MEMB later
1899 * if 12 bits is not enough for the displacement).
1905 /* For some reason, the bit string for this mode is not
1906 * consistent: it should be 0 (exclusive of the MEMB bit),
1907 * so we set it "by hand" here.
1909 memP->opcode |= MEMB_BIT;
1913 /* set MEMB bit in mode, and OR in mode bits */
1914 memP->opcode |= mode | MEMB_BIT;
1918 /* Treat missing displacement as displacement of 0 */
1920 /***********************
1921 * Fall into next case *
1922 ********************** */
1923 case D_BIT | A_BIT | I_BIT:
1925 /* set MEMB bit in mode, and OR in mode bits */
1926 memP->opcode |= mode | MEMB_BIT;
1936 /*****************************************************************************
1937 * parse_po: parse machine-dependent pseudo-op
1939 * This is a top-level routine for machine-dependent pseudo-ops. It slurps
1940 * up the rest of the input line, breaks out the individual arguments,
1941 * and dispatches them to the correct handler.
1942 **************************************************************************** */
1946 int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
1948 char *args[4]; /* Pointers operands, with no embedded whitespace.
1950 * arg[1-3]->operands
1952 int n_ops; /* Number of operands */
1953 char *p; /* Pointer to beginning of unparsed argument string */
1954 char eol; /* Character that indicated end of line */
1956 extern char is_end_of_line[];
1958 /* Advance input pointer to end of line. */
1959 p = input_line_pointer;
1960 while (!is_end_of_line[ *input_line_pointer ]){
1961 input_line_pointer++;
1963 eol = *input_line_pointer; /* Save end-of-line char */
1964 *input_line_pointer = '\0'; /* Terminate argument list */
1966 /* Parse out operands */
1967 n_ops = get_args(p, args);
1972 /* Dispatch to correct handler */
1974 case S_SYSPROC: s_sysproc(n_ops, args); break;
1975 case S_LEAFPROC: s_leafproc(n_ops, args); break;
1976 default: BAD_CASE(po_num); break;
1979 /* Restore eol, so line numbers get updated correctly. Base assembler
1980 * assumes we leave input pointer pointing at char following the eol.
1982 *input_line_pointer++ = eol;
1985 /*****************************************************************************
1986 * parse_regop: parse a register operand.
1988 * In case of illegal operand, issue a message and return some valid
1989 * information so instruction processing can continue.
1990 **************************************************************************** */
1993 parse_regop(regopP, optext, opdesc)
1994 struct regop *regopP; /* Where to put description of register operand */
1995 char *optext; /* Text of operand */
1996 char opdesc; /* Descriptor byte: what's legal for this operand */
1998 int n; /* Register number */
1999 expressionS e; /* Parsed expression */
2001 /* See if operand is a register */
2002 n = get_regnum(optext);
2005 /* global or local register */
2006 if (!REG_ALIGN(opdesc,n)){
2007 as_bad("unaligned register");
2011 regopP->special = 0;
2013 } else if (IS_FP_REG(n) && FP_OK(opdesc)){
2014 /* Floating point register, and it's allowed */
2015 regopP->n = n - FP0;
2017 regopP->special = 0;
2019 } else if (IS_SF_REG(n) && SFR_OK(opdesc)){
2020 /* Special-function register, and it's allowed */
2021 regopP->n = n - SF0;
2023 regopP->special = 1;
2024 if (!targ_has_sfr(regopP->n)){
2025 as_bad("no such sfr in this architecture");
2029 } else if (LIT_OK(opdesc)){
2031 * How about a literal?
2034 regopP->special = 0;
2035 if (FP_OK(opdesc)){ /* floating point literal acceptable */
2036 /* Skip over 0f, 0d, or 0e prefix */
2037 if ( (optext[0] == '0')
2038 && (optext[1] >= 'd')
2039 && (optext[1] <= 'f') ){
2043 if (!strcmp(optext,"0.0") || !strcmp(optext,"0") ){
2047 if (!strcmp(optext,"1.0") || !strcmp(optext,"1") ){
2052 } else { /* fixed point literal acceptable */
2053 if ((parse_expr(optext,&e) != SEG_ABSOLUTE)
2054 || (offs(e) < 0) || (offs(e) > 31)){
2055 as_bad("illegal literal");
2058 regopP->n = offs(e);
2063 /* Nothing worked */
2065 regopP->mode = 0; /* Register r0 is always a good one */
2067 regopP->special = 0;
2068 } /* parse_regop() */
2070 /*****************************************************************************
2071 * reg_fmt: generate a REG-format instruction
2073 **************************************************************************** */
2074 static void reg_fmt(args, oP)
2075 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2076 struct i960_opcode *oP; /* Pointer to description of instruction */
2078 long instr; /* Binary to be output */
2079 struct regop regop; /* Description of register operand */
2080 int n_ops; /* Number of operands */
2084 n_ops = oP->num_ops;
2087 parse_regop(®op, args[1], oP->operand[0]);
2089 if ((n_ops == 1) && !(instr & M3)){
2090 /* 1-operand instruction in which the dst field should
2091 * be used (instead of src1).
2095 regop.mode = regop.special;
2100 /* regop.n goes in bit 0, needs no shifting */
2102 regop.special <<= 5;
2104 instr |= regop.n | regop.mode | regop.special;
2108 parse_regop(®op, args[2], oP->operand[1]);
2110 if ((n_ops == 2) && !(instr & M3)){
2111 /* 2-operand instruction in which the dst field should
2112 * be used instead of src2).
2116 regop.mode = regop.special;
2123 regop.special <<= 6;
2125 instr |= regop.n | regop.mode | regop.special;
2128 parse_regop(®op, args[3], oP->operand[2]);
2130 regop.mode = regop.special;
2132 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2138 /*****************************************************************************
2140 * Replace cobr instruction in a code fragment with equivalent branch and
2141 * compare instructions, so it can reach beyond a 13-bit displacement.
2142 * Set up an address fix/relocation for the new branch instruction.
2144 **************************************************************************** */
2146 /* This "conditional jump" table maps cobr instructions into equivalent
2147 * compare and branch opcodes.
2153 } coj[] = { /* COBR OPCODE: */
2154 CHKBIT, BNO, /* 0x30 - bbc */
2155 CMPO, BG, /* 0x31 - cmpobg */
2156 CMPO, BE, /* 0x32 - cmpobe */
2157 CMPO, BGE, /* 0x33 - cmpobge */
2158 CMPO, BL, /* 0x34 - cmpobl */
2159 CMPO, BNE, /* 0x35 - cmpobne */
2160 CMPO, BLE, /* 0x36 - cmpoble */
2161 CHKBIT, BO, /* 0x37 - bbs */
2162 CMPI, BNO, /* 0x38 - cmpibno */
2163 CMPI, BG, /* 0x39 - cmpibg */
2164 CMPI, BE, /* 0x3a - cmpibe */
2165 CMPI, BGE, /* 0x3b - cmpibge */
2166 CMPI, BL, /* 0x3c - cmpibl */
2167 CMPI, BNE, /* 0x3d - cmpibne */
2168 CMPI, BLE, /* 0x3e - cmpible */
2169 CMPI, BO, /* 0x3f - cmpibo */
2175 register fragS *fragP; /* fragP->fr_opcode is assumed to point to
2176 * the cobr instruction, which comes at the
2177 * end of the code fragment.
2180 int opcode, src1, src2, m1, s2;
2181 /* Bit fields from cobr instruction */
2182 long bp_bits; /* Branch prediction bits from cobr instruction */
2183 long instr; /* A single i960 instruction */
2184 char *iP; /*->instruction to be replaced */
2185 fixS *fixP; /* Relocation that can be done at assembly time */
2187 /* PICK UP & PARSE COBR INSTRUCTION */
2188 iP = fragP->fr_opcode;
2189 instr = md_chars_to_number(iP, 4);
2190 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2191 src1 = (instr >> 19) & 0x1f;
2192 m1 = (instr >> 13) & 1;
2194 src2 = (instr >> 14) & 0x1f;
2195 bp_bits= instr & BP_MASK;
2197 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2198 instr = coj[opcode].compare
2199 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2200 md_number_to_chars(iP, instr, 4);
2202 /* OUTPUT BRANCH INSTRUCTION */
2203 md_number_to_chars(iP+4, coj[opcode].branch | bp_bits, 4);
2205 /* SET UP ADDRESS FIXUP/RELOCATION */
2206 fixP = fix_new(fragP,
2207 iP+4 - fragP->fr_literal,
2215 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */
2222 /*****************************************************************************
2223 * reloc_callj: Relocate a 'callj' instruction
2225 * This is a "non-(GNU)-standard" machine-dependent hook. The base
2226 * assembler calls it when it decides it can relocate an address at
2227 * assembly time instead of emitting a relocation directive.
2229 * Check to see if the relocation involves a 'callj' instruction to a:
2230 * sysproc: Replace the default 'call' instruction with a 'calls'
2231 * leafproc: Replace the default 'call' instruction with a 'bal'.
2232 * other proc: Do nothing.
2234 * See b.out.h for details on the 'n_other' field in a symbol structure.
2237 * Assumes the caller has already figured out, in the case of a leafproc,
2238 * to use the 'bal' entry point, and has substituted that symbol into the
2239 * passed fixup structure.
2241 **************************************************************************** */
2242 void reloc_callj(fixP)
2243 fixS *fixP; /* Relocation that can be done at assembly time */
2245 char *where; /*->the binary for the instruction being relocated */
2247 if (!fixP->fx_callj) {
2249 } /* This wasn't a callj instruction in the first place */
2251 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2253 if (TC_S_IS_SYSPROC(fixP->fx_addsy)) {
2254 /* Symbol is a .sysproc: replace 'call' with 'calls'.
2255 * System procedure number is (other-1).
2257 md_number_to_chars(where, CALLS|TC_S_GET_SYSPROC(fixP->fx_addsy), 4);
2259 /* Nothing else needs to be done for this instruction.
2260 * Make sure 'md_number_to_field()' will perform a no-op.
2262 fixP->fx_bit_fixP = (bit_fixS *) 1;
2264 } else if (TC_S_IS_CALLNAME(fixP->fx_addsy)) {
2265 /* Should not happen: see block comment above */
2266 as_fatal("Trying to 'bal' to %s", S_GET_NAME(fixP->fx_addsy));
2268 } else if (TC_S_IS_BALNAME(fixP->fx_addsy)) {
2269 /* Replace 'call' with 'bal'; both instructions have
2270 * the same format, so calling code should complete
2271 * relocation as if nothing happened here.
2273 md_number_to_chars(where, BAL, 4);
2274 } else if (TC_S_IS_BADPROC(fixP->fx_addsy)) {
2275 as_bad("Looks like a proc, but can't tell what kind.\n");
2276 } /* switch on proc type */
2278 /* else Symbol is neither a sysproc nor a leafproc */
2281 } /* reloc_callj() */
2284 /*****************************************************************************
2285 * s_leafproc: process .leafproc pseudo-op
2287 * .leafproc takes two arguments, the second one is optional:
2288 * arg[1]: name of 'call' entry point to leaf procedure
2289 * arg[2]: name of 'bal' entry point to leaf procedure
2291 * If the two arguments are identical, or if the second one is missing,
2292 * the first argument is taken to be the 'bal' entry point.
2294 * If there are 2 distinct arguments, we must make sure that the 'bal'
2295 * entry point immediately follows the 'call' entry point in the linked
2298 **************************************************************************** */
2299 static void s_leafproc(n_ops, args)
2300 int n_ops; /* Number of operands */
2301 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2303 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */
2304 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */
2306 if ((n_ops != 1) && (n_ops != 2)) {
2307 as_bad("should have 1 or 2 operands");
2309 } /* Check number of arguments */
2311 /* Find or create symbol for 'call' entry point. */
2312 callP = symbol_find_or_make(args[1]);
2314 if (TC_S_IS_CALLNAME(callP)) {
2315 as_warn("Redefining leafproc %s", S_GET_NAME(callP));
2318 /* If that was the only argument, use it as the 'bal' entry point.
2319 * Otherwise, mark it as the 'call' entry point and find or create
2320 * another symbol for the 'bal' entry point.
2322 if ((n_ops == 1) || !strcmp(args[1],args[2])) {
2323 TC_S_FORCE_TO_BALNAME(callP);
2326 TC_S_FORCE_TO_CALLNAME(callP);
2328 balP = symbol_find_or_make(args[2]);
2329 if (TC_S_IS_CALLNAME(balP)) {
2330 as_warn("Redefining leafproc %s", S_GET_NAME(balP));
2332 TC_S_FORCE_TO_BALNAME(balP);
2334 tc_set_bal_of_call(callP, balP);
2335 } /* if only one arg, or the args are the same */
2338 } /* s_leafproc() */
2342 * s_sysproc: process .sysproc pseudo-op
2344 * .sysproc takes two arguments:
2345 * arg[1]: name of entry point to system procedure
2346 * arg[2]: 'entry_num' (index) of system procedure in the range
2349 * For [ab].out, we store the 'entrynum' in the 'n_other' field of
2350 * the symbol. Since that entry is normally 0, we bias 'entrynum'
2351 * by adding 1 to it. It must be unbiased before it is used.
2353 static void s_sysproc(n_ops, args)
2354 int n_ops; /* Number of operands */
2355 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2361 as_bad("should have two operands");
2363 } /* bad arg count */
2365 /* Parse "entry_num" argument and check it for validity. */
2366 if ((parse_expr(args[2],&exp) != SEG_ABSOLUTE)
2368 || (offs(exp) > 31)) {
2369 as_bad("'entry_num' must be absolute number in [0,31]");
2373 /* Find/make symbol and stick entry number (biased by +1) into it */
2374 symP = symbol_find_or_make(args[1]);
2376 if (TC_S_IS_SYSPROC(symP)) {
2377 as_warn("Redefining entrynum for sysproc %s", S_GET_NAME(symP));
2380 TC_S_SET_SYSPROC(symP, offs(exp)); /* encode entry number */
2381 TC_S_FORCE_TO_SYSPROC(symP);
2387 /*****************************************************************************
2389 * Determine if a "shlo" instruction can be used to implement a "ldconst".
2390 * This means that some number X < 32 can be shifted left to produce the
2391 * constant of interest.
2393 * Return the shift count, or 0 if we can't do it.
2394 * Caller calculates X by shifting original constant right 'shift' places.
2396 **************************************************************************** */
2400 int n; /* The constant of interest */
2402 int shift; /* The shift count */
2405 /* Can't do it for negative numbers */
2409 /* Shift 'n' right until a 1 is about to be lost */
2410 for (shift = 0; (n & 1) == 0; shift++){
2421 /*****************************************************************************
2422 * syntax: issue syntax error
2424 **************************************************************************** */
2425 static void syntax() {
2426 as_bad("syntax error");
2430 /*****************************************************************************
2432 * Return TRUE iff the target architecture supports the specified
2433 * special-function register (sfr).
2435 **************************************************************************** */
2439 int n; /* Number (0-31) of sfr */
2441 switch (architecture){
2448 return ((0<=n) && (n<=2));
2453 /*****************************************************************************
2455 * Return TRUE iff the target architecture supports the indicated
2456 * class of instructions.
2458 **************************************************************************** */
2462 int ic; /* Instruction class; one of:
2463 * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM
2466 iclasses_seen |= ic;
2467 switch (architecture){
2468 case ARCH_KA: return ic & (I_BASE | I_KX);
2469 case ARCH_KB: return ic & (I_BASE | I_KX | I_FP | I_DEC);
2470 case ARCH_MC: return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2471 case ARCH_CA: return ic & (I_BASE | I_CX | I_CASIM);
2473 if ((iclasses_seen & (I_KX|I_FP|I_DEC|I_MIL))
2474 && (iclasses_seen & I_CX)){
2475 as_warn("architecture of opcode conflicts with that of earlier instruction(s)");
2476 iclasses_seen &= ~ic;
2483 /* Parse an operand that is machine-specific.
2484 We just return without modifying the expression if we have nothing
2489 md_operand (expressionP)
2490 expressionS *expressionP;
2494 /* We have no need to default values of symbols. */
2497 symbolS *md_undefined_symbol(name)
2501 } /* md_undefined_symbol() */
2503 /* Exactly what point is a PC-relative offset relative TO?
2504 On the i960, they're relative to the address of the instruction,
2505 which we have set up as the address of the fixup too. */
2507 md_pcrel_from (fixP)
2510 return fixP->fx_where + fixP->fx_frag->fr_address;
2514 md_apply_fix(fixP, val)
2518 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2520 if (!fixP->fx_bit_fixP) {
2522 switch (fixP->fx_im_disp) {
2524 fixP->fx_addnumber = val;
2525 md_number_to_imm(place, val, fixP->fx_size, fixP);
2528 md_number_to_disp(place,
2529 fixP->fx_pcrel ? val + fixP->fx_pcrel_adjust : val,
2532 case 2: /* fix requested for .long .word etc */
2533 md_number_to_chars(place, val, fixP->fx_size);
2536 as_fatal("Internal error in md_apply_fix() in file \"%s\"", __FILE__);
2537 } /* OVE: maybe one ought to put _imm _disp _chars in one md-func */
2539 md_number_to_field(place, val, fixP->fx_bit_fixP);
2543 } /* md_apply_fix() */
2545 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2546 void tc_bout_fix_to_chars(where, fixP, segment_address_in_file)
2549 relax_addressT segment_address_in_file;
2551 static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 };
2552 struct relocation_info ri;
2555 /* JF this is for paranoia */
2556 bzero((char *)&ri, sizeof(ri));
2558 know((symbolP = fixP->fx_addsy) != 0);
2560 /* These two 'cuz of NS32K */
2561 ri.r_callj = fixP->fx_callj;
2563 ri.r_length = nbytes_r_length[fixP->fx_size];
2564 ri.r_pcrel = fixP->fx_pcrel;
2565 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2567 if (!S_IS_DEFINED(symbolP)) {
2569 ri.r_index = symbolP->sy_number;
2572 ri.r_index = S_GET_TYPE(symbolP);
2575 /* Output the relocation information in machine-dependent form. */
2576 md_ri_to_chars(where, &ri);
2579 } /* tc_bout_fix_to_chars() */
2581 #endif /* OBJ_AOUT or OBJ_BOUT */
2583 /* Align an address by rounding it up to the specified boundary.
2585 long md_section_align(seg, addr)
2587 long addr; /* Address to be rounded up */
2589 return((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
2590 } /* md_section_align() */
2593 void tc_headers_hook(headers)
2594 object_headers *headers;
2596 /* FIXME: remove this line */ /* unsigned short arch_flag = 0; */
2598 if (iclasses_seen == I_BASE){
2599 headers->filehdr.f_flags |= F_I960CORE;
2600 } else if (iclasses_seen & I_CX){
2601 headers->filehdr.f_flags |= F_I960CA;
2602 } else if (iclasses_seen & I_MIL){
2603 headers->filehdr.f_flags |= F_I960MC;
2604 } else if (iclasses_seen & (I_DEC|I_FP)){
2605 headers->filehdr.f_flags |= F_I960KB;
2607 headers->filehdr.f_flags |= F_I960KA;
2608 } /* set arch flag */
2610 if (flagseen['R']) {
2611 headers->filehdr.f_magic = I960RWMAGIC;
2612 headers->aouthdr.magic = OMAGIC;
2614 headers->filehdr.f_magic = I960ROMAGIC;
2615 headers->aouthdr.magic = NMAGIC;
2616 } /* set magic numbers */
2619 } /* tc_headers_hook() */
2620 #endif /* OBJ_COFF */
2623 * Things going on here:
2625 * For bout, We need to assure a couple of simplifying
2626 * assumptions about leafprocs for the linker: the leafproc
2627 * entry symbols will be defined in the same assembly in
2628 * which they're declared with the '.leafproc' directive;
2629 * and if a leafproc has both 'call' and 'bal' entry points
2630 * they are both global or both local.
2632 * For coff, the call symbol has a second aux entry that
2633 * contains the bal entry point. The bal symbol becomes a
2636 * For coff representation, the call symbol has a second aux entry that
2637 * contains the bal entry point. The bal symbol becomes a label.
2641 void tc_crawl_symbol_chain(headers)
2642 object_headers *headers;
2646 for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next(symbolP)) {
2648 if (TC_S_IS_SYSPROC(symbolP)) {
2649 /* second aux entry already contains the sysproc number */
2650 S_SET_NUMBER_AUXILIARY(symbolP, 2);
2651 S_SET_STORAGE_CLASS(symbolP, C_SCALL);
2652 S_SET_DATA_TYPE(symbolP, S_GET_DATA_TYPE(symbolP) | (DT_FCN << N_BTSHFT));
2654 } /* rewrite sysproc */
2655 #endif /* OBJ_COFF */
2657 if (!TC_S_IS_BALNAME(symbolP) && !TC_S_IS_CALLNAME(symbolP)) {
2659 } /* Not a leafproc symbol */
2661 if (!S_IS_DEFINED(symbolP)) {
2662 as_bad("leafproc symbol '%s' undefined", S_GET_NAME(symbolP));
2663 } /* undefined leaf */
2665 if (TC_S_IS_CALLNAME(symbolP)) {
2666 symbolS *balP = tc_get_bal_of_call(symbolP);
2667 if (S_IS_EXTERNAL(symbolP) != S_IS_EXTERNAL(balP)) {
2668 S_SET_EXTERNAL(symbolP);
2669 S_SET_EXTERNAL(balP);
2670 as_warn("Warning: making leafproc entries %s and %s both global\n",
2671 S_GET_NAME(symbolP), S_GET_NAME(balP));
2672 } /* externality mismatch */
2674 } /* walk the symbol chain */
2677 } /* tc_crawl_symbol_chain() */
2680 * For aout or bout, the bal immediately follows the call.
2682 * For coff, we cheat and store a pointer to the bal symbol
2683 * in the second aux entry of the call.
2686 void tc_set_bal_of_call(callP, balP)
2690 know(TC_S_IS_CALLNAME(callP));
2691 know(TC_S_IS_BALNAME(balP));
2695 callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP;
2696 S_SET_NUMBER_AUXILIARY(callP,2);
2698 #elif defined(OBJ_AOUT) || defined(OBJ_BOUT)
2700 /* If the 'bal' entry doesn't immediately follow the 'call'
2701 * symbol, unlink it from the symbol list and re-insert it.
2703 if (symbol_next(callP) != balP) {
2704 symbol_remove(balP, &symbol_rootP, &symbol_lastP);
2705 symbol_append(balP, callP, &symbol_rootP, &symbol_lastP);
2706 } /* if not in order */
2709 (as yet unwritten.);
2710 #endif /* switch on OBJ_FORMAT */
2713 } /* tc_set_bal_of_call() */
2715 char *_tc_get_bal_of_call(callP)
2720 know(TC_S_IS_CALLNAME(callP));
2723 retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry);
2724 #elif defined(OBJ_AOUT) || defined(OBJ_BOUT)
2725 retval = symbol_next(callP);
2727 (as yet unwritten.);
2728 #endif /* switch on OBJ_FORMAT */
2730 know(TC_S_IS_BALNAME(retval));
2731 return((char *) retval);
2732 } /* _tc_get_bal_of_call() */
2734 void tc_coff_symbol_emit_hook(symbolP)
2737 if (TC_S_IS_CALLNAME(symbolP)) {
2739 symbolS *balP = tc_get_bal_of_call(symbolP);
2741 /* second aux entry contains the bal entry point */
2742 /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */
2743 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE(balP);
2744 S_SET_STORAGE_CLASS(symbolP, (!SF_GET_LOCAL(symbolP) ? C_LEAFEXT : C_LEAFSTAT));
2745 S_SET_DATA_TYPE(symbolP, S_GET_DATA_TYPE(symbolP) | (DT_FCN << N_BTSHFT));
2746 /* fix up the bal symbol */
2747 S_SET_STORAGE_CLASS(balP, C_LABEL);
2748 #endif /* OBJ_COFF */
2749 } /* only on calls */
2752 } /* tc_coff_symbol_emit_hook() */