1 /* tc-i960.c - All the i80960-specific stuff
2 Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GAS.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20 /* See comment on md_parse_option for 80960-specific invocation options. */
22 /******************************************************************************
24 * Header, symbol, and relocation info will be used on the host machine
25 * only -- only executable code is actually downloaded to the i80960.
26 * Therefore, leave all such information in host byte order.
28 * (That's a slight lie -- we DO download some header information, but
29 * the downloader converts the file format and corrects the byte-ordering
30 * of the relevant fields while doing so.)
32 * ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER
33 * FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO
34 * USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <==
36 ***************************************************************************** */
38 /* There are 4 different lengths of (potentially) symbol-based displacements
39 * in the 80960 instruction set, each of which could require address fix-ups
40 * and (in the case of external symbols) emission of relocation directives:
43 * This is a standard length for the base assembler and requires no
47 * This is a non-standard length, but the base assembler has a hook for
48 * bit field address fixups: the fixS structure can point to a descriptor
49 * of the field, in which case our md_number_to_field() routine gets called
52 * I made the hook a little cleaner by having fix_new() (in the base
53 * assembler) return a pointer to the fixS in question. And I made it a
54 * little simpler by storing the field size (in this case 13) instead of
55 * of a pointer to another structure: 80960 displacements are ALWAYS
56 * stored in the low-order bits of a 4-byte word.
58 * Since the target of a COBR cannot be external, no relocation directives
59 * for this size displacement have to be generated. But the base assembler
60 * had to be modified to issue error messages if the symbol did turn out
64 * Fixups are handled as for the 13-bit case (except that 24 is stored
67 * The relocation directive generated is the same as that for the 32-bit
68 * displacement, except that it's PC-relative (the 32-bit displacement
69 * never is). The i80960 version of the linker needs a mod to
70 * distinguish and handle the 24-bit case.
73 * MEMA formats are always promoted to MEMB (32-bit) if the displacement
74 * is based on a symbol, because it could be relocated at link time.
75 * The only time we use the 12-bit format is if an absolute value of
76 * less than 4096 is specified, in which case we need neither a fixup nor
77 * a relocation directive.
87 #include "opcode/i960.h"
89 extern char *input_line_pointer;
90 extern struct hash_control *po_hash;
91 extern char *next_object_file_charP;
94 int md_reloc_size = sizeof(struct reloc);
96 int md_reloc_size = sizeof(struct relocation_info);
99 /***************************
100 * Local i80960 routines *
101 ************************** */
103 static void brcnt_emit(); /* Emit branch-prediction instrumentation code */
104 static char * brlab_next(); /* Return next branch local label */
105 void brtab_emit(); /* Emit br-predict instrumentation table */
106 static void cobr_fmt(); /* Generate COBR instruction */
107 static void ctrl_fmt(); /* Generate CTRL instruction */
108 static char * emit(); /* Emit (internally) binary */
109 static int get_args(); /* Break arguments out of comma-separated list */
110 static void get_cdisp(); /* Handle COBR or CTRL displacement */
111 static char * get_ispec(); /* Find index specification string */
112 static int get_regnum(); /* Translate text to register number */
113 static int i_scan(); /* Lexical scan of instruction source */
114 static void mem_fmt(); /* Generate MEMA or MEMB instruction */
115 static void mema_to_memb(); /* Convert MEMA instruction to MEMB format */
116 static segT parse_expr(); /* Parse an expression */
117 static int parse_ldconst();/* Parse and replace a 'ldconst' pseudo-op */
118 static void parse_memop(); /* Parse a memory operand */
119 static void parse_po(); /* Parse machine-dependent pseudo-op */
120 static void parse_regop(); /* Parse a register operand */
121 static void reg_fmt(); /* Generate a REG format instruction */
122 void reloc_callj(); /* Relocate a 'callj' instruction */
123 static void relax_cobr(); /* "De-optimize" cobr into compare/branch */
124 static void s_leafproc(); /* Process '.leafproc' pseudo-op */
125 static void s_sysproc(); /* Process '.sysproc' pseudo-op */
126 static int shift_ok(); /* Will a 'shlo' substiture for a 'ldconst'? */
127 static void syntax(); /* Give syntax error */
128 static int targ_has_sfr(); /* Target chip supports spec-func register? */
129 static int targ_has_iclass();/* Target chip supports instruction set? */
130 /* static void unlink_sym(); */ /* Remove a symbol from the symbol list */
132 /* See md_parse_option() for meanings of these options */
133 static char norelax; /* True if -norelax switch seen */
134 static char instrument_branches; /* True if -b switch seen */
136 /* Characters that always start a comment.
137 * If the pre-processor is disabled, these aren't very useful.
139 char comment_chars[] = "#";
141 /* Characters that only start a comment at the beginning of
142 * a line. If the line seems to have the form '# 123 filename'
143 * .line and .file directives will appear in the pre-processed output.
145 * Note that input_file.c hand checks for '#' at the beginning of the
146 * first line of the input file. This is because the compiler outputs
147 * #NO_APP at the beginning of its output.
150 /* Also note that comments started like this one will always work. */
152 char line_comment_chars[] = "";
154 /* Chars that can be used to separate mant from exp in floating point nums */
155 char EXP_CHARS[] = "eE";
157 /* Chars that mean this number is a floating point constant,
158 * as in 0f12.456 or 0d1.2345e12
160 char FLT_CHARS[] = "fFdDtT";
163 /* Table used by base assembler to relax addresses based on varying length
164 * instructions. The fields are:
165 * 1) most positive reach of this state,
166 * 2) most negative reach of this state,
167 * 3) how many bytes this mode will add to the size of the current frag
168 * 4) which index into the table to try if we can't fit into this one.
170 * For i80960, the only application is the (de-)optimization of cobr
171 * instructions into separate compare and branch instructions when a 13-bit
172 * displacement won't hack it.
176 {0, 0, 0,0}, /* State 0 => no more relaxation possible */
177 {4088, -4096, 0,2}, /* State 1: conditional branch (cobr) */
178 {0x800000-8,-0x800000,4,0}, /* State 2: compare (reg) & branch (ctrl) */
182 /* These are the machine dependent pseudo-ops.
184 * This table describes all the machine specific pseudo-ops the assembler
185 * has to support. The fields are:
186 * pseudo-op name without dot
187 * function to call to execute this pseudo-op
188 * integer arg to pass to the function
193 const pseudo_typeS md_pseudo_table[] = {
194 { "bss", s_lcomm, 1 },
195 { "extended", float_cons, 't' },
196 { "leafproc", parse_po, S_LEAFPROC },
197 { "sysproc", parse_po, S_SYSPROC },
200 { "quad", big_cons, 16 },
205 /* Macros to extract info from an 'expressionS' structure 'e' */
206 #define adds(e) e.X_add_symbol
207 #define subs(e) e.X_subtract_symbol
208 #define offs(e) e.X_add_number
209 #define segs(e) e.X_seg
212 /* Branch-prediction bits for CTRL/COBR format opcodes */
213 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
214 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
215 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
218 /* Some instruction opcodes that we need explicitly */
219 #define BE 0x12000000
220 #define BG 0x11000000
221 #define BGE 0x13000000
222 #define BL 0x14000000
223 #define BLE 0x16000000
224 #define BNE 0x15000000
225 #define BNO 0x10000000
226 #define BO 0x17000000
227 #define CHKBIT 0x5a002700
228 #define CMPI 0x5a002080
229 #define CMPO 0x5a002000
232 #define BAL 0x0b000000
233 #define CALL 0x09000000
234 #define CALLS 0x66003800
235 #define RET 0x0a000000
238 /* These masks are used to build up a set of MEMB mode bits. */
241 #define MEMB_BIT 0x1000
245 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is used) */
246 #define MEMA_ABASE 0x2000
248 /* Info from which a MEMA or MEMB format instruction can be generated */
250 long opcode; /* (First) 32 bits of instruction */
251 int disp; /* 0-(none), 12- or, 32-bit displacement needed */
252 char *e; /* The expression in the source instruction from
253 * which the displacement should be determined
258 /* The two pieces of info we need to generate a register operand */
260 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
261 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
262 int n; /* Register number or literal value */
266 /* Number and assembler mnemonic for all registers that can appear in operands */
271 { "pfp", 0 }, { "sp", 1 }, { "rip", 2 }, { "r3", 3 },
272 { "r4", 4 }, { "r5", 5 }, { "r6", 6 }, { "r7", 7 },
273 { "r8", 8 }, { "r9", 9 }, { "r10", 10 }, { "r11", 11 },
274 { "r12", 12 }, { "r13", 13 }, { "r14", 14 }, { "r15", 15 },
275 { "g0", 16 }, { "g1", 17 }, { "g2", 18 }, { "g3", 19 },
276 { "g4", 20 }, { "g5", 21 }, { "g6", 22 }, { "g7", 23 },
277 { "g8", 24 }, { "g9", 25 }, { "g10", 26 }, { "g11", 27 },
278 { "g12", 28 }, { "g13", 29 }, { "g14", 30 }, { "fp", 31 },
280 /* Numbers for special-function registers are for assembler internal
281 * use only: they are scaled back to range [0-31] for binary output.
285 { "sf0", 32 }, { "sf1", 33 }, { "sf2", 34 }, { "sf3", 35 },
286 { "sf4", 36 }, { "sf5", 37 }, { "sf6", 38 }, { "sf7", 39 },
287 { "sf8", 40 }, { "sf9", 41 }, { "sf10",42 }, { "sf11",43 },
288 { "sf12",44 }, { "sf13",45 }, { "sf14",46 }, { "sf15",47 },
289 { "sf16",48 }, { "sf17",49 }, { "sf18",50 }, { "sf19",51 },
290 { "sf20",52 }, { "sf21",53 }, { "sf22",54 }, { "sf23",55 },
291 { "sf24",56 }, { "sf25",57 }, { "sf26",58 }, { "sf27",59 },
292 { "sf28",60 }, { "sf29",61 }, { "sf30",62 }, { "sf31",63 },
294 /* Numbers for floating point registers are for assembler internal use
295 * only: they are scaled back to [0-3] for binary output.
299 { "fp0", 64 }, { "fp1", 65 }, { "fp2", 66 }, { "fp3", 67 },
301 { NULL, 0 }, /* END OF LIST */
304 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
305 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
306 #define IS_FP_REG(n) ((n) >= FP0)
308 /* Number and assembler mnemonic for all registers that can appear as 'abase'
309 * (indirect addressing) registers.
315 { "(pfp)", 0 }, { "(sp)", 1 }, { "(rip)", 2 }, { "(r3)", 3 },
316 { "(r4)", 4 }, { "(r5)", 5 }, { "(r6)", 6 }, { "(r7)", 7 },
317 { "(r8)", 8 }, { "(r9)", 9 }, { "(r10)", 10 }, { "(r11)", 11 },
318 { "(r12)", 12 }, { "(r13)", 13 }, { "(r14)", 14 }, { "(r15)", 15 },
319 { "(g0)", 16 }, { "(g1)", 17 }, { "(g2)", 18 }, { "(g3)", 19 },
320 { "(g4)", 20 }, { "(g5)", 21 }, { "(g6)", 22 }, { "(g7)", 23 },
321 { "(g8)", 24 }, { "(g9)", 25 }, { "(g10)", 26 }, { "(g11)", 27 },
322 { "(g12)", 28 }, { "(g13)", 29 }, { "(g14)", 30 }, { "(fp)", 31 },
325 /* for assembler internal use only: this number never appears in binary
330 { NULL, 0 }, /* END OF LIST */
335 static struct hash_control *op_hash = NULL; /* Opcode mnemonics */
336 static struct hash_control *reg_hash = NULL; /* Register name hash table */
337 static struct hash_control *areg_hash = NULL; /* Abase register hash table */
340 /* Architecture for which we are assembling */
341 #define ARCH_ANY 0 /* Default: no architecture checking done */
346 int architecture = ARCH_ANY; /* Architecture requested on invocation line */
347 int iclasses_seen = 0; /* OR of instruction classes (I_* constants)
348 * for which we've actually assembled
353 /* BRANCH-PREDICTION INSTRUMENTATION
355 * The following supports generation of branch-prediction instrumentation
356 * (turned on by -b switch). The instrumentation collects counts
357 * of branches taken/not-taken for later input to a utility that will
358 * set the branch prediction bits of the instructions in accordance with
359 * the behavior observed. (Note that the KX series does not have
362 * The instrumentation consists of:
364 * (1) before and after each conditional branch, a call to an external
365 * routine that increments and steps over an inline counter. The
366 * counter itself, initialized to 0, immediately follows the call
367 * instruction. For each branch, the counter following the branch
368 * is the number of times the branch was not taken, and the difference
369 * between the counters is the number of times it was taken. An
370 * example of an instrumented conditional branch:
374 * LBRANCH23: be label
378 * (2) a table of pointers to the instrumented branches, so that an
379 * external postprocessing routine can locate all of the counters.
380 * the table begins with a 2-word header: a pointer to the next in
381 * a linked list of such tables (initialized to 0); and a count
382 * of the number of entries in the table (exclusive of the header.
384 * Note that input source code is expected to already contain calls
385 * an external routine that will link the branch local table into a
386 * list of such tables.
389 static int br_cnt = 0; /* Number of branches instrumented so far.
390 * Also used to generate unique local labels
391 * for each instrumented branch
394 #define BR_LABEL_BASE "LBRANCH"
395 /* Basename of local labels on instrumented
396 * branches, to avoid conflict with compiler-
397 * generated local labels.
400 #define BR_CNT_FUNC "__inc_branch"
401 /* Name of the external routine that will
402 * increment (and step over) an inline counter.
405 #define BR_TAB_NAME "__BRANCH_TABLE__"
406 /* Name of the table of pointers to branches.
407 * A local (i.e., non-external) symbol.
410 /*****************************************************************************
411 * md_begin: One-time initialization.
413 * Set up hash tables.
415 **************************************************************************** */
419 int i; /* Loop counter */
420 const struct i960_opcode *oP; /* Pointer into opcode table */
421 char *retval; /* Value returned by hash functions */
423 if (((op_hash = hash_new()) == 0)
424 || ((reg_hash = hash_new()) == 0)
425 || ((areg_hash = hash_new()) == 0)) {
426 as_fatal("virtual memory exceeded");
429 retval = ""; /* For some reason, the base assembler uses an empty
430 * string for "no error message", instead of a NULL
434 for (oP=i960_opcodes; oP->name && !*retval; oP++) {
435 retval = hash_insert(op_hash, oP->name, oP);
438 for (i=0; regnames[i].reg_name && !*retval; i++) {
439 retval = hash_insert(reg_hash, regnames[i].reg_name,
440 ®names[i].reg_num);
443 for (i=0; aregs[i].areg_name && !*retval; i++){
444 retval = hash_insert(areg_hash, aregs[i].areg_name,
449 as_fatal("Hashing returned \"%s\".", retval);
453 /*****************************************************************************
454 * md_end: One-time final cleanup
458 **************************************************************************** */
464 /*****************************************************************************
465 * md_assemble: Assemble an instruction
467 * Assumptions about the passed-in text:
468 * - all comments, labels removed
469 * - text is an instruction
470 * - all white space compressed to single blanks
471 * - all character constants have been replaced with decimal
473 **************************************************************************** */
476 char *textP; /* Source text of instruction */
478 char *args[4]; /* Parsed instruction text, containing NO whitespace:
479 * arg[0]->opcode mnemonic
480 * arg[1-3]->operands, with char constants
481 * replaced by decimal numbers
483 int n_ops; /* Number of instruction operands */
485 struct i960_opcode *oP;
486 /* Pointer to instruction description */
488 /* TRUE iff opcode mnemonic included branch-prediction
489 * suffix (".f" or ".t")
491 long bp_bits; /* Setting of branch-prediction bit(s) to be OR'd
492 * into instruction opcode of CTRL/COBR format
495 int n; /* Offset of last character in opcode mnemonic */
497 static const char bp_error_msg[] = "branch prediction invalid on this opcode";
500 /* Parse instruction into opcode and operands */
501 memset(args, '\0', sizeof(args));
502 n_ops = i_scan(textP, args);
504 return; /* Error message already issued */
507 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
508 if (!strcmp(args[0],"ldconst")){
509 n_ops = parse_ldconst(args);
517 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
518 n = strlen(args[0]) - 1;
521 if (args[0][n-1] == '.' && (args[0][n] == 't' || args[0][n] == 'f')){
522 /* We could check here to see if the target architecture
523 * supports branch prediction, but why bother? The bit
524 * will just be ignored by processors that don't use it.
527 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
528 args[0][n-1] = '\0'; /* Strip suffix from opcode mnemonic */
531 /* Look up opcode mnemonic in table and check number of operands.
532 * Check that opcode is legal for the target architecture.
533 * If all looks good, assemble instruction.
535 oP = (struct i960_opcode *) hash_find(op_hash, args[0]);
536 if (!oP || !targ_has_iclass(oP->iclass)) {
537 as_bad("invalid opcode, \"%s\".", args[0]);
539 } else if (n_ops != oP->num_ops) {
540 as_bad("improper number of operands. expecting %d, got %d", oP->num_ops, n_ops);
546 ctrl_fmt(args[1], oP->opcode | bp_bits, oP->num_ops);
547 if (oP->format == FBRA){
548 /* Now generate a 'bno' to same arg */
549 ctrl_fmt(args[1], BNO | bp_bits, 1);
554 cobr_fmt(args, oP->opcode | bp_bits, oP);
558 as_warn(bp_error_msg);
563 if (args[0][0] == 'c' && args[0][1] == 'a')
567 as_warn(bp_error_msg);
569 mem_fmt(args, oP, 1);
578 as_warn(bp_error_msg);
580 mem_fmt(args, oP, 0);
584 as_warn(bp_error_msg);
586 /* Output opcode & set up "fixup" (relocation);
587 * flag relocation as 'callj' type.
589 know(oP->num_ops == 1);
590 get_cdisp(args[1], "CTRL", oP->opcode, 24, 0, 1);
593 BAD_CASE(oP->format);
597 } /* md_assemble() */
599 /*****************************************************************************
600 * md_number_to_chars: convert a number to target byte order
602 **************************************************************************** */
604 md_number_to_chars(buf, value, n)
605 char *buf; /* Put output here */
606 long value; /* The integer to be converted */
607 int n; /* Number of bytes to output (significant bytes
616 /* XXX line number probably botched for this warning message. */
617 if (value != 0 && value != -1){
618 as_bad("Displacement too long for instruction field length.");
622 } /* md_number_to_chars() */
624 /*****************************************************************************
625 * md_chars_to_number: convert from target byte order to host byte order.
627 **************************************************************************** */
629 md_chars_to_number(val, n)
630 unsigned char *val; /* Value in target byte order */
631 int n; /* Number of bytes in the input */
635 for (retval=0; n--;){
643 #define MAX_LITTLENUMS 6
644 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
646 /*****************************************************************************
647 * md_atof: convert ascii to floating point
649 * Turn a string at input_line_pointer into a floating point constant of type
650 * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
651 * emitted is returned at 'sizeP'. An error message is returned, or a pointer
652 * to an empty message if OK.
654 * Note we call the i386 floating point routine, rather than complicating
655 * things with more files or symbolic links.
657 **************************************************************************** */
658 char * md_atof(type, litP, sizeP)
663 LITTLENUM_TYPE words[MAX_LITTLENUMS];
664 LITTLENUM_TYPE *wordP;
683 type = 'x'; /* That's what atof_ieee() understands */
688 return "Bad call to md_atof()";
691 t = atof_ieee(input_line_pointer, type, words);
693 input_line_pointer = t;
696 *sizeP = prec * LNUM_SIZE;
698 /* Output the LITTLENUMs in REVERSE order in accord with i80960
699 * word-order. (Dunno why atof_ieee doesn't do it in the right
700 * order in the first place -- probably because it's a hack of
704 for(wordP = words + prec - 1; prec--;){
705 md_number_to_chars(litP, (long) (*wordP--), LNUM_SIZE);
706 litP += sizeof(LITTLENUM_TYPE);
709 return ""; /* Someone should teach Dean about null pointers */
713 /*****************************************************************************
716 **************************************************************************** */
718 md_number_to_imm(buf, val, n)
723 md_number_to_chars(buf, val, n);
727 /*****************************************************************************
730 **************************************************************************** */
732 md_number_to_disp(buf, val, n)
737 md_number_to_chars(buf, val, n);
740 /*****************************************************************************
741 * md_number_to_field:
743 * Stick a value (an address fixup) into a bit field of
744 * previously-generated instruction.
746 **************************************************************************** */
748 md_number_to_field(instrP, val, bfixP)
749 char *instrP; /* Pointer to instruction to be fixed */
750 long val; /* Address fixup value */
751 bit_fixS *bfixP; /* Description of bit field to be fixed up */
753 int numbits; /* Length of bit field to be fixed */
754 long instr; /* 32-bit instruction to be fixed-up */
755 long sign; /* 0 or -1, according to sign bit of 'val' */
757 /* Convert instruction back to host byte order
759 instr = md_chars_to_number(instrP, 4);
761 /* Surprise! -- we stored the number of bits
762 * to be modified rather than a pointer to a structure.
764 numbits = (int)bfixP;
766 /* This is a no-op, stuck here by reloc_callj() */
770 know ((numbits==13) || (numbits==24));
772 /* Propagate sign bit of 'val' for the given number of bits.
773 * Result should be all 0 or all 1
775 sign = val >> ((int)numbits - 1);
776 if (((val < 0) && (sign != -1))
777 || ((val > 0) && (sign != 0))){
778 as_bad("Fixup of %d too large for field width of %d",
781 /* Put bit field into instruction and write back in target
784 val &= ~(-1 << (int)numbits); /* Clear unused sign bits */
786 md_number_to_chars(instrP, instr, 4);
788 } /* md_number_to_field() */
791 /*****************************************************************************
793 * Invocation line includes a switch not recognized by the base assembler.
794 * See if it's a processor-specific option. For the 960, these are:
797 * Conditional branch instructions that require displacements
798 * greater than 13 bits (or that have external targets) should
799 * generate errors. The default is to replace each such
800 * instruction with the corresponding compare (or chkbit) and
801 * branch instructions. Note that the Intel "j" cobr directives
802 * are ALWAYS "de-optimized" in this way when necessary,
803 * regardless of the setting of this option.
806 * Add code to collect information about branches taken, for
807 * later optimization of branch prediction bits by a separate
808 * tool. COBR and CNTL format instructions have branch
809 * prediction bits (in the CX architecture); if "BR" represents
810 * an instruction in one of these classes, the following rep-
811 * resents the code generated by the assembler:
813 * call <increment routine>
814 * .word 0 # pre-counter
816 * call <increment routine>
817 * .word 0 # post-counter
819 * A table of all such "Labels" is also generated.
822 * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
823 * Select the 80960 architecture. Instructions or features not
824 * supported by the selected architecture cause fatal errors.
825 * The default is to generate code for any instruction or feature
826 * that is supported by SOME version of the 960 (even if this
827 * means mixing architectures!).
829 **************************************************************************** */
831 md_parse_option(argP, cntP, vecP)
837 struct tabentry { char *flag; int arch; };
838 static struct tabentry arch_tab[] = {
841 "SA", ARCH_KA, /* Synonym for KA */
842 "SB", ARCH_KB, /* Synonym for KB */
843 "KC", ARCH_MC, /* Synonym for MC */
849 if (!strcmp(*argP,"linkrelax")){
852 } else if (!strcmp(*argP,"norelax")){
855 } else if (**argP == 'b'){
856 instrument_branches = 1;
858 } else if (**argP == 'A'){
861 for (tp = arch_tab; tp->flag != NULL; tp++){
862 if (!strcmp(p,tp->flag)){
867 if (tp->flag == NULL){
868 as_bad("unknown architecture: %s", p);
870 architecture = tp->arch;
877 **argP = '\0'; /* Done parsing this switch */
881 /*****************************************************************************
883 * Called by base assembler after address relaxation is finished: modify
884 * variable fragments according to how much relaxation was done.
886 * If the fragment substate is still 1, a 13-bit displacement was enough
887 * to reach the symbol in question. Set up an address fixup, but otherwise
888 * leave the cobr instruction alone.
890 * If the fragment substate is 2, a 13-bit displacement was not enough.
891 * Replace the cobr with a two instructions (a compare and a branch).
893 **************************************************************************** */
895 md_convert_frag(headers, fragP)
896 object_headers *headers;
899 fixS *fixP; /* Structure describing needed address fix */
901 switch (fragP->fr_subtype){
903 /* LEAVE SINGLE COBR INSTRUCTION */
904 fixP = fix_new(fragP,
905 fragP->fr_opcode-fragP->fr_literal,
913 fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */
916 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
920 BAD_CASE(fragP->fr_subtype);
925 /*****************************************************************************
926 * md_estimate_size_before_relax: How much does it look like *fragP will grow?
928 * Called by base assembler just before address relaxation.
929 * Return the amount by which the fragment will grow.
931 * Any symbol that is now undefined will not become defined; cobr's
932 * based on undefined symbols will have to be replaced with a compare
933 * instruction and a branch instruction, and the code fragment will grow
936 **************************************************************************** */
938 md_estimate_size_before_relax(fragP, segment_type)
939 register fragS *fragP;
940 register segT segment_type;
942 /* If symbol is undefined in this segment, go to "relaxed" state
943 * (compare and branch instructions instead of cobr) right now.
945 if (S_GET_SEGMENT(fragP->fr_symbol) != segment_type) {
950 } /* md_estimate_size_before_relax() */
953 /*****************************************************************************
955 * This routine exists in order to overcome machine byte-order problems
956 * when dealing with bit-field entries in the relocation_info struct.
958 * But relocation info will be used on the host machine only (only
959 * executable code is actually downloaded to the i80960). Therefore,
960 * we leave it in host byte order.
962 * The above comment is no longer true. This routine now really
963 * does do the reordering (Ian Taylor 28 Aug 92).
965 **************************************************************************** */
966 void md_ri_to_chars(where, ri)
968 struct relocation_info *ri;
970 md_number_to_chars (where, ri->r_address,
971 sizeof (ri->r_address));
972 where[4] = ri->r_index & 0x0ff;
973 where[5] = (ri->r_index >> 8) & 0x0ff;
974 where[6] = (ri->r_index >> 16) & 0x0ff;
975 where[7] = ((ri->r_pcrel << 0)
976 | (ri->r_length << 1)
977 | (ri->r_extern << 3)
980 | (ri->r_callj << 6));
981 } /* md_ri_to_chars() */
983 #ifndef WORKING_DOT_WORD
985 int md_short_jump_size = 0;
986 int md_long_jump_size = 0;
988 void md_create_short_jump(ptr, from_addr, to_addr, frag, to_symbol)
995 as_fatal("failed sanity check.");
999 md_create_long_jump(ptr,from_addr,to_addr,frag,to_symbol)
1001 long from_addr, to_addr;
1005 as_fatal("failed sanity check.");
1009 /*************************************************************
1011 * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER *
1013 ************************************************************ */
1017 /*****************************************************************************
1018 * brcnt_emit: Emit code to increment inline branch counter.
1020 * See the comments above the declaration of 'br_cnt' for details on
1021 * branch-prediction instrumentation.
1022 **************************************************************************** */
1026 ctrl_fmt(BR_CNT_FUNC,CALL,1);/* Emit call to "increment" routine */
1027 emit(0); /* Emit inline counter to be incremented */
1030 /*****************************************************************************
1031 * brlab_next: generate the next branch local label
1033 * See the comments above the declaration of 'br_cnt' for details on
1034 * branch-prediction instrumentation.
1035 **************************************************************************** */
1039 static char buf[20];
1041 sprintf(buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1045 /*****************************************************************************
1046 * brtab_emit: generate the fetch-prediction branch table.
1048 * See the comments above the declaration of 'br_cnt' for details on
1049 * branch-prediction instrumentation.
1051 * The code emitted here would be functionally equivalent to the following
1052 * example assembler source.
1057 * .word 0 # link to next table
1058 * .word 3 # length of table
1059 * .word LBRANCH0 # 1st entry in table proper
1062 ***************************************************************************** */
1068 char *p; /* Where the binary was output to */
1069 fixS *fixP; /*->description of deferred address fixup */
1071 if (!instrument_branches){
1075 subseg_new(SEG_DATA,0); /* .data */
1076 frag_align(2,0); /* .align 2 */
1077 record_alignment(now_seg,2);
1078 colon(BR_TAB_NAME); /* BR_TAB_NAME: */
1079 emit(0); /* .word 0 #link to next table */
1080 emit(br_cnt); /* .word n #length of table */
1082 for (i=0; i<br_cnt; i++){
1083 sprintf(buf, "%s%d", BR_LABEL_BASE, i);
1085 fixP = fix_new(frag_now,
1086 p - frag_now->fr_literal,
1093 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1097 /*****************************************************************************
1098 * cobr_fmt: generate a COBR-format instruction
1100 **************************************************************************** */
1103 cobr_fmt(arg, opcode, oP)
1104 char *arg[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1105 long opcode; /* Opcode, with branch-prediction bits already set
1108 struct i960_opcode *oP;
1109 /*->description of instruction */
1111 long instr; /* 32-bit instruction */
1112 struct regop regop; /* Description of register operand */
1113 int n; /* Number of operands */
1114 int var_frag; /* 1 if varying length code fragment should
1115 * be emitted; 0 if an address fix
1116 * should be emitted.
1123 /* First operand (if any) of a COBR is always a register
1124 * operand. Parse it.
1126 parse_regop(®op, arg[1], oP->operand[0]);
1127 instr |= (regop.n << 19) | (regop.mode << 13);
1130 /* Second operand (if any) of a COBR is always a register
1131 * operand. Parse it.
1133 parse_regop(®op, arg[2], oP->operand[1]);
1134 instr |= (regop.n << 14) | regop.special;
1142 if (instrument_branches){
1144 colon(brlab_next());
1147 /* A third operand to a COBR is always a displacement.
1148 * Parse it; if it's relaxable (a cobr "j" directive, or any
1149 * cobr other than bbs/bbc when the "-norelax" option is not in
1150 * use) set up a variable code fragment; otherwise set up an
1153 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1154 get_cdisp(arg[3], "COBR", instr, 13, var_frag, 0);
1156 if (instrument_branches){
1163 /*****************************************************************************
1164 * ctrl_fmt: generate a CTRL-format instruction
1166 **************************************************************************** */
1169 ctrl_fmt(targP, opcode, num_ops)
1170 char *targP; /* Pointer to text of lone operand (if any) */
1171 long opcode; /* Template of instruction */
1172 int num_ops; /* Number of operands */
1174 int instrument; /* TRUE iff we should add instrumentation to track
1175 * how often the branch is taken
1180 emit(opcode); /* Output opcode */
1183 instrument = instrument_branches && (opcode!=CALL)
1184 && (opcode!=B) && (opcode!=RET) && (opcode!=BAL);
1188 colon(brlab_next());
1191 /* The operand MUST be an ip-relative displacment. Parse it
1192 * and set up address fix for the instruction we just output.
1194 get_cdisp(targP, "CTRL", opcode, 24, 0, 0);
1204 /*****************************************************************************
1205 * emit: output instruction binary
1207 * Output instruction binary, in target byte order, 4 bytes at a time.
1208 * Return pointer to where it was placed.
1210 **************************************************************************** */
1214 long instr; /* Word to be output, host byte order */
1216 char *toP; /* Where to output it */
1218 toP = frag_more(4); /* Allocate storage */
1219 md_number_to_chars(toP, instr, 4); /* Convert to target byte order */
1224 /*****************************************************************************
1225 * get_args: break individual arguments out of comma-separated list
1227 * Input assumptions:
1228 * - all comments and labels have been removed
1229 * - all strings of whitespace have been collapsed to a single blank.
1230 * - all character constants ('x') have been replaced with decimal
1233 * args[0] is untouched. args[1] points to first operand, etc. All args:
1234 * - are NULL-terminated
1235 * - contain no whitespace
1238 * Number of operands (0,1,2, or 3) or -1 on error.
1240 **************************************************************************** */
1241 static int get_args(p, args)
1242 register char *p; /* Pointer to comma-separated operands; MUCKED BY US */
1243 char *args[]; /* Output arg: pointers to operands placed in args[1-3].
1244 * MUST ACCOMMODATE 4 ENTRIES (args[0-3]).
1247 register int n; /* Number of operands */
1253 /* Skip lead white space */
1265 /* Squeze blanks out by moving non-blanks toward start of string.
1266 * Isolate operands, whenever comma is found.
1274 } else if (*p == ','){
1276 /* Start of operand */
1278 as_bad("too many operands");
1281 *to++ = '\0'; /* Terminate argument */
1282 args[++n] = to; /* Start next argument */
1294 /*****************************************************************************
1295 * get_cdisp: handle displacement for a COBR or CTRL instruction.
1297 * Parse displacement for a COBR or CTRL instruction.
1299 * If successful, output the instruction opcode and set up for it,
1300 * depending on the arg 'var_frag', either:
1301 * o an address fixup to be done when all symbol values are known, or
1302 * o a varying length code fragment, with address fixup info. This
1303 * will be done for cobr instructions that may have to be relaxed
1304 * in to compare/branch instructions (8 bytes) if the final address
1305 * displacement is greater than 13 bits.
1307 **************************************************************************** */
1310 get_cdisp(dispP, ifmtP, instr, numbits, var_frag, callj)
1311 char *dispP; /*->displacement as specified in source instruction */
1312 char *ifmtP; /*->"COBR" or "CTRL" (for use in error message) */
1313 long instr; /* Instruction needing the displacement */
1314 int numbits; /* # bits of displacement (13 for COBR, 24 for CTRL) */
1315 int var_frag; /* 1 if varying length code fragment should be emitted;
1316 * 0 if an address fix should be emitted.
1318 int callj; /* 1 if callj relocation should be done; else 0 */
1320 expressionS e; /* Parsed expression */
1321 fixS *fixP; /* Structure describing needed address fix */
1322 char *outP; /* Where instruction binary is output to */
1326 switch (parse_expr(dispP,&e)) {
1329 as_bad("expression syntax error");
1335 outP = frag_more(8); /* Allocate worst-case storage */
1336 md_number_to_chars(outP, instr, 4);
1337 frag_variant(rs_machine_dependent, 4, 4, 1,
1338 adds(e), offs(e), outP, 0, 0);
1340 /* Set up a new fix structure, so address can be updated
1341 * when all symbol values are known.
1344 fixP = fix_new(frag_now,
1345 outP - frag_now->fr_literal,
1353 fixP->fx_callj = callj;
1355 /* We want to modify a bit field when the address is
1356 * known. But we don't need all the garbage in the
1357 * bit_fix structure. So we're going to lie and store
1358 * the number of bits affected instead of a pointer.
1360 fixP->fx_bit_fixP = (bit_fixS *) numbits;
1366 as_bad("attempt to branch into different segment");
1370 as_bad("target of %s instruction must be a label", ifmtP);
1376 /*****************************************************************************
1377 * get_ispec: parse a memory operand for an index specification
1379 * Here, an "index specification" is taken to be anything surrounded
1380 * by square brackets and NOT followed by anything else.
1382 * If it's found, detach it from the input string, remove the surrounding
1383 * square brackets, and return a pointer to it. Otherwise, return NULL.
1385 **************************************************************************** */
1389 char *textP; /*->memory operand from source instruction, no white space */
1391 char *start; /*->start of index specification */
1392 char *end; /*->end of index specification */
1394 /* Find opening square bracket, if any
1396 start = strchr(textP, '[');
1400 /* Eliminate '[', detach from rest of operand */
1403 end = strchr(start, ']');
1406 as_bad("unmatched '['");
1409 /* Eliminate ']' and make sure it was the last thing
1413 if (*(end+1) != '\0'){
1414 as_bad("garbage after index spec ignored");
1421 /*****************************************************************************
1424 * Look up a (suspected) register name in the register table and return the
1425 * associated register number (or -1 if not found).
1427 **************************************************************************** */
1431 char *regname; /* Suspected register name */
1435 rP = (int *) hash_find(reg_hash, regname);
1436 return (rP == NULL) ? -1 : *rP;
1440 /*****************************************************************************
1441 * i_scan: perform lexical scan of ascii assembler instruction.
1443 * Input assumptions:
1444 * - input string is an i80960 instruction (not a pseudo-op)
1445 * - all comments and labels have been removed
1446 * - all strings of whitespace have been collapsed to a single blank.
1449 * args[0] points to opcode, other entries point to operands. All strings:
1450 * - are NULL-terminated
1451 * - contain no whitespace
1452 * - have character constants ('x') replaced with a decimal number
1455 * Number of operands (0,1,2, or 3) or -1 on error.
1457 **************************************************************************** */
1458 static int i_scan(iP, args)
1459 register char *iP; /* Pointer to ascii instruction; MUCKED BY US. */
1460 char *args[]; /* Output arg: pointers to opcode and operands placed
1461 * here. MUST ACCOMMODATE 4 ENTRIES.
1465 /* Isolate opcode */
1468 } /* Skip lead space, if any */
1470 for (; *iP != ' '; iP++) {
1472 /* There are no operands */
1473 if (args[0] == iP) {
1474 /* We never moved: there was no opcode either! */
1475 as_bad("missing opcode");
1481 *iP++ = '\0'; /* Terminate opcode */
1482 return(get_args(iP, args));
1486 /*****************************************************************************
1487 * mem_fmt: generate a MEMA- or MEMB-format instruction
1489 **************************************************************************** */
1490 static void mem_fmt(args, oP, callx)
1491 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1492 struct i960_opcode *oP; /* Pointer to description of instruction */
1493 int callx; /* Is this a callx opcode */
1495 int i; /* Loop counter */
1496 struct regop regop; /* Description of register operand */
1497 char opdesc; /* Operand descriptor byte */
1498 memS instr; /* Description of binary to be output */
1499 char *outP; /* Where the binary was output to */
1500 expressionS expr; /* Parsed expression */
1501 fixS *fixP; /*->description of deferred address fixup */
1503 memset(&instr, '\0', sizeof(memS));
1504 instr.opcode = oP->opcode;
1506 /* Process operands. */
1507 for (i = 1; i <= oP->num_ops; i++){
1508 opdesc = oP->operand[i-1];
1511 parse_memop(&instr, args[i], oP->format);
1513 parse_regop(®op, args[i], opdesc);
1514 instr.opcode |= regop.n << 19;
1519 outP = emit(instr.opcode);
1521 if (instr.disp == 0){
1525 /* Parse and process the displacement */
1526 switch (parse_expr(instr.e,&expr)){
1529 as_bad("expression syntax error");
1533 if (instr.disp == 32){
1534 (void) emit(offs(expr)); /* Output displacement */
1536 /* 12-bit displacement */
1537 if (offs(expr) & ~0xfff){
1538 /* Won't fit in 12 bits: convert already-output
1539 * instruction to MEMB format, output
1543 (void) emit(offs(expr));
1545 /* WILL fit in 12 bits: OR into opcode and
1546 * overwrite the binary we already put out
1548 instr.opcode |= offs(expr);
1549 md_number_to_chars(outP, instr.opcode, 4);
1554 case SEG_DIFFERENCE:
1559 if (instr.disp == 12){
1560 /* Displacement is dependent on a symbol, whose value
1561 * may change at link time. We HAVE to reserve 32 bits.
1562 * Convert already-output opcode to MEMB format.
1567 /* Output 0 displacement and set up address fixup for when
1568 * this symbol's value becomes known.
1570 outP = emit((long) 0);
1571 fixP = fix_new(frag_now,
1572 outP - frag_now->fr_literal,
1579 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1580 fixP->fx_bsr = callx; /*SAC LD RELAX HACK */ /* Mark reloc as being in i stream */
1584 BAD_CASE(segs(expr));
1590 /*****************************************************************************
1591 * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1593 * There are 2 possible MEMA formats:
1594 * - displacement only
1595 * - displacement + abase
1597 * They are distinguished by the setting of the MEMA_ABASE bit.
1599 **************************************************************************** */
1600 static void mema_to_memb(opcodeP)
1601 char *opcodeP; /* Where to find the opcode, in target byte order */
1603 long opcode; /* Opcode in host byte order */
1604 long mode; /* Mode bits for MEMB instruction */
1606 opcode = md_chars_to_number(opcodeP, 4);
1607 know(!(opcode & MEMB_BIT));
1609 mode = MEMB_BIT | D_BIT;
1610 if (opcode & MEMA_ABASE){
1614 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */
1615 opcode |= mode; /* Set MEMB mode bits */
1617 md_number_to_chars(opcodeP, opcode, 4);
1618 } /* mema_to_memb() */
1621 /*****************************************************************************
1622 * parse_expr: parse an expression
1624 * Use base assembler's expression parser to parse an expression.
1625 * It, unfortunately, runs off a global which we have to save/restore
1626 * in order to make it work for us.
1628 * An empty expression string is treated as an absolute 0.
1630 * Return "segment" to which the expression evaluates.
1631 * Return SEG_GOOF regardless of expression evaluation if entire input
1632 * string is not consumed in the evaluation -- tolerate no dangling junk!
1634 **************************************************************************** */
1637 parse_expr(textP, expP)
1638 char *textP; /* Text of expression to be parsed */
1639 expressionS *expP; /* Where to put the results of parsing */
1641 char *save_in; /* Save global here */
1642 segT seg; /* Segment to which expression evaluates */
1647 if (*textP == '\0') {
1648 /* Treat empty string as absolute 0 */
1649 expP->X_add_symbol = expP->X_subtract_symbol = NULL;
1650 expP->X_add_number = 0;
1651 seg = expP->X_seg = SEG_ABSOLUTE;
1654 save_in = input_line_pointer; /* Save global */
1655 input_line_pointer = textP; /* Make parser work for us */
1657 seg = expression(expP);
1658 if (input_line_pointer - textP != strlen(textP)) {
1659 /* Did not consume all of the input */
1662 symP = expP->X_add_symbol;
1663 if (symP && (hash_find(reg_hash, S_GET_NAME(symP)))) {
1664 /* Register name in an expression */
1668 input_line_pointer = save_in; /* Restore global */
1674 /*****************************************************************************
1676 * Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1677 * i80960 instruction.
1679 * Assumes the input consists of:
1680 * arg[0] opcode mnemonic ('ldconst')
1681 * arg[1] first operand (constant)
1682 * arg[2] name of register to be loaded
1684 * Replaces opcode and/or operands as appropriate.
1686 * Returns the new number of arguments, or -1 on failure.
1688 **************************************************************************** */
1692 char *arg[]; /* See above */
1694 int n; /* Constant to be loaded */
1695 int shift; /* Shift count for "shlo" instruction */
1696 static char buf[5]; /* Literal for first operand */
1697 static char buf2[5]; /* Literal for second operand */
1698 expressionS e; /* Parsed expression */
1701 arg[3] = NULL; /* So we can tell at the end if it got used or not */
1703 switch(parse_expr(arg[1],&e)){
1709 case SEG_DIFFERENCE:
1710 /* We're dependent on one or more symbols -- use "lda" */
1715 /* Try the following mappings:
1716 * ldconst 0,<reg> ->mov 0,<reg>
1717 * ldconst 31,<reg> ->mov 31,<reg>
1718 * ldconst 32,<reg> ->addo 1,31,<reg>
1719 * ldconst 62,<reg> ->addo 31,31,<reg>
1720 * ldconst 64,<reg> ->shlo 8,3,<reg>
1721 * ldconst -1,<reg> ->subo 1,0,<reg>
1722 * ldconst -31,<reg>->subo 31,0,<reg>
1724 * anthing else becomes:
1728 if ((0 <= n) && (n <= 31)){
1731 } else if ((-31 <= n) && (n <= -1)){
1734 sprintf(buf, "%d", -n);
1738 } else if ((32 <= n) && (n <= 62)){
1742 sprintf(buf, "%d", n-31);
1745 } else if ((shift = shift_ok(n)) != 0){
1748 sprintf(buf, "%d", shift);
1750 sprintf(buf2, "%d", n >> shift);
1759 as_bad("invalid constant");
1763 return (arg[3] == 0) ? 2: 3;
1766 /*****************************************************************************
1767 * parse_memop: parse a memory operand
1769 * This routine is based on the observation that the 4 mode bits of the
1770 * MEMB format, taken individually, have fairly consistent meaning:
1772 * M3 (bit 13): 1 if displacement is present (D_BIT)
1773 * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1774 * M1 (bit 11): 1 if index is present (I_BIT)
1775 * M0 (bit 10): 1 if abase is present (A_BIT)
1777 * So we parse the memory operand and set bits in the mode as we find
1778 * things. Then at the end, if we go to MEMB format, we need only set
1779 * the MEMB bit (M2) and our mode is built for us.
1781 * Unfortunately, I said "fairly consistent". The exceptions:
1784 * 0100 Would seem illegal, but means "abase-only".
1786 * 0101 Would seem to mean "abase-only" -- it means IP-relative.
1787 * Must be converted to 0100.
1789 * 0110 Would seem to mean "index-only", but is reserved.
1790 * We turn on the D bit and provide a 0 displacement.
1792 * The other thing to observe is that we parse from the right, peeling
1793 * things * off as we go: first any index spec, then any abase, then
1796 **************************************************************************** */
1799 parse_memop(memP, argP, optype)
1800 memS *memP; /* Where to put the results */
1801 char *argP; /* Text of the operand to be parsed */
1802 int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
1804 char *indexP; /* Pointer to index specification with "[]" removed */
1805 char *p; /* Temp char pointer */
1806 char iprel_flag;/* True if this is an IP-relative operand */
1807 int regnum; /* Register number */
1808 int scale; /* Scale factor: 1,2,4,8, or 16. Later converted
1809 * to internal format (0,1,2,3,4 respectively).
1811 int mode; /* MEMB mode bits */
1812 int *intP; /* Pointer to register number */
1814 /* The following table contains the default scale factors for each
1815 * type of memory instruction. It is accessed using (optype-MEM1)
1816 * as an index -- thus it assumes the 'optype' constants are assigned
1817 * consecutive values, in the order they appear in this table
1819 static int def_scale[] = {
1824 -1, /* MEM12 -- no valid default */
1829 iprel_flag = mode = 0;
1831 /* Any index present? */
1832 indexP = get_ispec(argP);
1834 p = strchr(indexP, '*');
1836 /* No explicit scale -- use default for this
1839 scale = def_scale[ optype - MEM1 ];
1841 *p++ = '\0'; /* Eliminate '*' */
1843 /* Now indexP->a '\0'-terminated register name,
1844 * and p->a scale factor.
1847 if (!strcmp(p,"16")){
1849 } else if (strchr("1248",*p) && (p[1] == '\0')){
1856 regnum = get_regnum(indexP); /* Get index reg. # */
1857 if (!IS_RG_REG(regnum)){
1858 as_bad("invalid index register");
1862 /* Convert scale to its binary encoding */
1864 case 1: scale = 0 << 7; break;
1865 case 2: scale = 1 << 7; break;
1866 case 4: scale = 2 << 7; break;
1867 case 8: scale = 3 << 7; break;
1868 case 16: scale = 4 << 7; break;
1869 default: as_bad("invalid scale factor"); return;
1872 memP->opcode |= scale | regnum; /* Set index bits in opcode */
1873 mode |= I_BIT; /* Found a valid index spec */
1876 /* Any abase (Register Indirect) specification present? */
1877 if ((p = strrchr(argP,'(')) != NULL) {
1878 /* "(" is there -- does it start a legal abase spec?
1879 * (If not it could be part of a displacement expression.)
1881 intP = (int *) hash_find(areg_hash, p);
1883 /* Got an abase here */
1885 *p = '\0'; /* discard register spec */
1886 if (regnum == IPREL){
1887 /* We have to specialcase ip-rel mode */
1890 memP->opcode |= regnum << 14;
1896 /* Any expression present? */
1902 /* Special-case ip-relative addressing */
1907 memP->opcode |= 5 << 10; /* IP-relative mode */
1913 /* Handle all other modes */
1916 /* Go with MEMA instruction format for now (grow to MEMB later
1917 * if 12 bits is not enough for the displacement).
1918 * MEMA format has a single mode bit: set it to indicate
1919 * that abase is present.
1921 memP->opcode |= MEMA_ABASE;
1926 /* Go with MEMA instruction format for now (grow to MEMB later
1927 * if 12 bits is not enough for the displacement).
1933 /* For some reason, the bit string for this mode is not
1934 * consistent: it should be 0 (exclusive of the MEMB bit),
1935 * so we set it "by hand" here.
1937 memP->opcode |= MEMB_BIT;
1941 /* set MEMB bit in mode, and OR in mode bits */
1942 memP->opcode |= mode | MEMB_BIT;
1946 /* Treat missing displacement as displacement of 0 */
1948 /***********************
1949 * Fall into next case *
1950 ********************** */
1951 case D_BIT | A_BIT | I_BIT:
1953 /* set MEMB bit in mode, and OR in mode bits */
1954 memP->opcode |= mode | MEMB_BIT;
1964 /*****************************************************************************
1965 * parse_po: parse machine-dependent pseudo-op
1967 * This is a top-level routine for machine-dependent pseudo-ops. It slurps
1968 * up the rest of the input line, breaks out the individual arguments,
1969 * and dispatches them to the correct handler.
1970 **************************************************************************** */
1974 int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
1976 char *args[4]; /* Pointers operands, with no embedded whitespace.
1978 * arg[1-3]->operands
1980 int n_ops; /* Number of operands */
1981 char *p; /* Pointer to beginning of unparsed argument string */
1982 char eol; /* Character that indicated end of line */
1984 extern char is_end_of_line[];
1986 /* Advance input pointer to end of line. */
1987 p = input_line_pointer;
1988 while (!is_end_of_line[ *input_line_pointer ]){
1989 input_line_pointer++;
1991 eol = *input_line_pointer; /* Save end-of-line char */
1992 *input_line_pointer = '\0'; /* Terminate argument list */
1994 /* Parse out operands */
1995 n_ops = get_args(p, args);
2000 /* Dispatch to correct handler */
2002 case S_SYSPROC: s_sysproc(n_ops, args); break;
2003 case S_LEAFPROC: s_leafproc(n_ops, args); break;
2004 default: BAD_CASE(po_num); break;
2007 /* Restore eol, so line numbers get updated correctly. Base assembler
2008 * assumes we leave input pointer pointing at char following the eol.
2010 *input_line_pointer++ = eol;
2013 /*****************************************************************************
2014 * parse_regop: parse a register operand.
2016 * In case of illegal operand, issue a message and return some valid
2017 * information so instruction processing can continue.
2018 **************************************************************************** */
2021 parse_regop(regopP, optext, opdesc)
2022 struct regop *regopP; /* Where to put description of register operand */
2023 char *optext; /* Text of operand */
2024 char opdesc; /* Descriptor byte: what's legal for this operand */
2026 int n; /* Register number */
2027 expressionS e; /* Parsed expression */
2029 /* See if operand is a register */
2030 n = get_regnum(optext);
2033 /* global or local register */
2034 if (!REG_ALIGN(opdesc,n)){
2035 as_bad("unaligned register");
2039 regopP->special = 0;
2041 } else if (IS_FP_REG(n) && FP_OK(opdesc)){
2042 /* Floating point register, and it's allowed */
2043 regopP->n = n - FP0;
2045 regopP->special = 0;
2047 } else if (IS_SF_REG(n) && SFR_OK(opdesc)){
2048 /* Special-function register, and it's allowed */
2049 regopP->n = n - SF0;
2051 regopP->special = 1;
2052 if (!targ_has_sfr(regopP->n)){
2053 as_bad("no such sfr in this architecture");
2057 } else if (LIT_OK(opdesc)){
2059 * How about a literal?
2062 regopP->special = 0;
2063 if (FP_OK(opdesc)){ /* floating point literal acceptable */
2064 /* Skip over 0f, 0d, or 0e prefix */
2065 if ( (optext[0] == '0')
2066 && (optext[1] >= 'd')
2067 && (optext[1] <= 'f') ){
2071 if (!strcmp(optext,"0.0") || !strcmp(optext,"0") ){
2075 if (!strcmp(optext,"1.0") || !strcmp(optext,"1") ){
2080 } else { /* fixed point literal acceptable */
2081 if ((parse_expr(optext,&e) != SEG_ABSOLUTE)
2082 || (offs(e) < 0) || (offs(e) > 31)){
2083 as_bad("illegal literal");
2086 regopP->n = offs(e);
2091 /* Nothing worked */
2093 regopP->mode = 0; /* Register r0 is always a good one */
2095 regopP->special = 0;
2096 } /* parse_regop() */
2098 /*****************************************************************************
2099 * reg_fmt: generate a REG-format instruction
2101 **************************************************************************** */
2102 static void reg_fmt(args, oP)
2103 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2104 struct i960_opcode *oP; /* Pointer to description of instruction */
2106 long instr; /* Binary to be output */
2107 struct regop regop; /* Description of register operand */
2108 int n_ops; /* Number of operands */
2112 n_ops = oP->num_ops;
2115 parse_regop(®op, args[1], oP->operand[0]);
2117 if ((n_ops == 1) && !(instr & M3)){
2118 /* 1-operand instruction in which the dst field should
2119 * be used (instead of src1).
2123 regop.mode = regop.special;
2128 /* regop.n goes in bit 0, needs no shifting */
2130 regop.special <<= 5;
2132 instr |= regop.n | regop.mode | regop.special;
2136 parse_regop(®op, args[2], oP->operand[1]);
2138 if ((n_ops == 2) && !(instr & M3)){
2139 /* 2-operand instruction in which the dst field should
2140 * be used instead of src2).
2144 regop.mode = regop.special;
2151 regop.special <<= 6;
2153 instr |= regop.n | regop.mode | regop.special;
2156 parse_regop(®op, args[3], oP->operand[2]);
2158 regop.mode = regop.special;
2160 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2166 /*****************************************************************************
2168 * Replace cobr instruction in a code fragment with equivalent branch and
2169 * compare instructions, so it can reach beyond a 13-bit displacement.
2170 * Set up an address fix/relocation for the new branch instruction.
2172 **************************************************************************** */
2174 /* This "conditional jump" table maps cobr instructions into equivalent
2175 * compare and branch opcodes.
2181 } coj[] = { /* COBR OPCODE: */
2182 CHKBIT, BNO, /* 0x30 - bbc */
2183 CMPO, BG, /* 0x31 - cmpobg */
2184 CMPO, BE, /* 0x32 - cmpobe */
2185 CMPO, BGE, /* 0x33 - cmpobge */
2186 CMPO, BL, /* 0x34 - cmpobl */
2187 CMPO, BNE, /* 0x35 - cmpobne */
2188 CMPO, BLE, /* 0x36 - cmpoble */
2189 CHKBIT, BO, /* 0x37 - bbs */
2190 CMPI, BNO, /* 0x38 - cmpibno */
2191 CMPI, BG, /* 0x39 - cmpibg */
2192 CMPI, BE, /* 0x3a - cmpibe */
2193 CMPI, BGE, /* 0x3b - cmpibge */
2194 CMPI, BL, /* 0x3c - cmpibl */
2195 CMPI, BNE, /* 0x3d - cmpibne */
2196 CMPI, BLE, /* 0x3e - cmpible */
2197 CMPI, BO, /* 0x3f - cmpibo */
2203 register fragS *fragP; /* fragP->fr_opcode is assumed to point to
2204 * the cobr instruction, which comes at the
2205 * end of the code fragment.
2208 int opcode, src1, src2, m1, s2;
2209 /* Bit fields from cobr instruction */
2210 long bp_bits; /* Branch prediction bits from cobr instruction */
2211 long instr; /* A single i960 instruction */
2212 char *iP; /*->instruction to be replaced */
2213 fixS *fixP; /* Relocation that can be done at assembly time */
2215 /* PICK UP & PARSE COBR INSTRUCTION */
2216 iP = fragP->fr_opcode;
2217 instr = md_chars_to_number(iP, 4);
2218 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2219 src1 = (instr >> 19) & 0x1f;
2220 m1 = (instr >> 13) & 1;
2222 src2 = (instr >> 14) & 0x1f;
2223 bp_bits= instr & BP_MASK;
2225 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2226 instr = coj[opcode].compare
2227 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2228 md_number_to_chars(iP, instr, 4);
2230 /* OUTPUT BRANCH INSTRUCTION */
2231 md_number_to_chars(iP+4, coj[opcode].branch | bp_bits, 4);
2233 /* SET UP ADDRESS FIXUP/RELOCATION */
2234 fixP = fix_new(fragP,
2235 iP+4 - fragP->fr_literal,
2243 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */
2250 /*****************************************************************************
2251 * reloc_callj: Relocate a 'callj' instruction
2253 * This is a "non-(GNU)-standard" machine-dependent hook. The base
2254 * assembler calls it when it decides it can relocate an address at
2255 * assembly time instead of emitting a relocation directive.
2257 * Check to see if the relocation involves a 'callj' instruction to a:
2258 * sysproc: Replace the default 'call' instruction with a 'calls'
2259 * leafproc: Replace the default 'call' instruction with a 'bal'.
2260 * other proc: Do nothing.
2262 * See b.out.h for details on the 'n_other' field in a symbol structure.
2265 * Assumes the caller has already figured out, in the case of a leafproc,
2266 * to use the 'bal' entry point, and has substituted that symbol into the
2267 * passed fixup structure.
2269 **************************************************************************** */
2270 void reloc_callj(fixP)
2271 fixS *fixP; /* Relocation that can be done at assembly time */
2273 char *where; /*->the binary for the instruction being relocated */
2275 if (!fixP->fx_callj) {
2277 } /* This wasn't a callj instruction in the first place */
2279 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2281 if (TC_S_IS_SYSPROC(fixP->fx_addsy)) {
2282 /* Symbol is a .sysproc: replace 'call' with 'calls'.
2283 * System procedure number is (other-1).
2285 md_number_to_chars(where, CALLS|TC_S_GET_SYSPROC(fixP->fx_addsy), 4);
2287 /* Nothing else needs to be done for this instruction.
2288 * Make sure 'md_number_to_field()' will perform a no-op.
2290 fixP->fx_bit_fixP = (bit_fixS *) 1;
2292 } else if (TC_S_IS_CALLNAME(fixP->fx_addsy)) {
2293 /* Should not happen: see block comment above */
2294 as_fatal("Trying to 'bal' to %s", S_GET_NAME(fixP->fx_addsy));
2296 } else if (TC_S_IS_BALNAME(fixP->fx_addsy)) {
2297 /* Replace 'call' with 'bal'; both instructions have
2298 * the same format, so calling code should complete
2299 * relocation as if nothing happened here.
2301 md_number_to_chars(where, BAL, 4);
2302 } else if (TC_S_IS_BADPROC(fixP->fx_addsy)) {
2303 as_bad("Looks like a proc, but can't tell what kind.\n");
2304 } /* switch on proc type */
2306 /* else Symbol is neither a sysproc nor a leafproc */
2309 } /* reloc_callj() */
2312 /*****************************************************************************
2313 * s_leafproc: process .leafproc pseudo-op
2315 * .leafproc takes two arguments, the second one is optional:
2316 * arg[1]: name of 'call' entry point to leaf procedure
2317 * arg[2]: name of 'bal' entry point to leaf procedure
2319 * If the two arguments are identical, or if the second one is missing,
2320 * the first argument is taken to be the 'bal' entry point.
2322 * If there are 2 distinct arguments, we must make sure that the 'bal'
2323 * entry point immediately follows the 'call' entry point in the linked
2326 **************************************************************************** */
2327 static void s_leafproc(n_ops, args)
2328 int n_ops; /* Number of operands */
2329 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2331 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */
2332 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */
2334 if ((n_ops != 1) && (n_ops != 2)) {
2335 as_bad("should have 1 or 2 operands");
2337 } /* Check number of arguments */
2339 /* Find or create symbol for 'call' entry point. */
2340 callP = symbol_find_or_make(args[1]);
2342 if (TC_S_IS_CALLNAME(callP)) {
2343 as_warn("Redefining leafproc %s", S_GET_NAME(callP));
2346 /* If that was the only argument, use it as the 'bal' entry point.
2347 * Otherwise, mark it as the 'call' entry point and find or create
2348 * another symbol for the 'bal' entry point.
2350 if ((n_ops == 1) || !strcmp(args[1],args[2])) {
2351 TC_S_FORCE_TO_BALNAME(callP);
2354 TC_S_FORCE_TO_CALLNAME(callP);
2356 balP = symbol_find_or_make(args[2]);
2357 if (TC_S_IS_CALLNAME(balP)) {
2358 as_warn("Redefining leafproc %s", S_GET_NAME(balP));
2360 TC_S_FORCE_TO_BALNAME(balP);
2362 tc_set_bal_of_call(callP, balP);
2363 } /* if only one arg, or the args are the same */
2366 } /* s_leafproc() */
2370 * s_sysproc: process .sysproc pseudo-op
2372 * .sysproc takes two arguments:
2373 * arg[1]: name of entry point to system procedure
2374 * arg[2]: 'entry_num' (index) of system procedure in the range
2377 * For [ab].out, we store the 'entrynum' in the 'n_other' field of
2378 * the symbol. Since that entry is normally 0, we bias 'entrynum'
2379 * by adding 1 to it. It must be unbiased before it is used.
2381 static void s_sysproc(n_ops, args)
2382 int n_ops; /* Number of operands */
2383 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2389 as_bad("should have two operands");
2391 } /* bad arg count */
2393 /* Parse "entry_num" argument and check it for validity. */
2394 if ((parse_expr(args[2],&exp) != SEG_ABSOLUTE)
2396 || (offs(exp) > 31)) {
2397 as_bad("'entry_num' must be absolute number in [0,31]");
2401 /* Find/make symbol and stick entry number (biased by +1) into it */
2402 symP = symbol_find_or_make(args[1]);
2404 if (TC_S_IS_SYSPROC(symP)) {
2405 as_warn("Redefining entrynum for sysproc %s", S_GET_NAME(symP));
2408 TC_S_SET_SYSPROC(symP, offs(exp)); /* encode entry number */
2409 TC_S_FORCE_TO_SYSPROC(symP);
2415 /*****************************************************************************
2417 * Determine if a "shlo" instruction can be used to implement a "ldconst".
2418 * This means that some number X < 32 can be shifted left to produce the
2419 * constant of interest.
2421 * Return the shift count, or 0 if we can't do it.
2422 * Caller calculates X by shifting original constant right 'shift' places.
2424 **************************************************************************** */
2428 int n; /* The constant of interest */
2430 int shift; /* The shift count */
2433 /* Can't do it for negative numbers */
2437 /* Shift 'n' right until a 1 is about to be lost */
2438 for (shift = 0; (n & 1) == 0; shift++){
2449 /*****************************************************************************
2450 * syntax: issue syntax error
2452 **************************************************************************** */
2453 static void syntax() {
2454 as_bad("syntax error");
2458 /*****************************************************************************
2460 * Return TRUE iff the target architecture supports the specified
2461 * special-function register (sfr).
2463 **************************************************************************** */
2467 int n; /* Number (0-31) of sfr */
2469 switch (architecture){
2476 return ((0<=n) && (n<=2));
2481 /*****************************************************************************
2483 * Return TRUE iff the target architecture supports the indicated
2484 * class of instructions.
2486 **************************************************************************** */
2490 int ic; /* Instruction class; one of:
2491 * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM
2494 iclasses_seen |= ic;
2495 switch (architecture){
2496 case ARCH_KA: return ic & (I_BASE | I_KX);
2497 case ARCH_KB: return ic & (I_BASE | I_KX | I_FP | I_DEC);
2498 case ARCH_MC: return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2499 case ARCH_CA: return ic & (I_BASE | I_CX | I_CASIM);
2501 if ((iclasses_seen & (I_KX|I_FP|I_DEC|I_MIL))
2502 && (iclasses_seen & I_CX)){
2503 as_warn("architecture of opcode conflicts with that of earlier instruction(s)");
2504 iclasses_seen &= ~ic;
2511 /* Parse an operand that is machine-specific.
2512 We just return without modifying the expression if we have nothing
2517 md_operand (expressionP)
2518 expressionS *expressionP;
2522 /* We have no need to default values of symbols. */
2525 symbolS *md_undefined_symbol(name)
2529 } /* md_undefined_symbol() */
2531 /* Exactly what point is a PC-relative offset relative TO?
2532 On the i960, they're relative to the address of the instruction,
2533 which we have set up as the address of the fixup too. */
2535 md_pcrel_from (fixP)
2538 return fixP->fx_where + fixP->fx_frag->fr_address;
2542 md_apply_fix(fixP, val)
2546 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2548 if (!fixP->fx_bit_fixP) {
2550 switch (fixP->fx_im_disp) {
2552 fixP->fx_addnumber = val;
2553 md_number_to_imm(place, val, fixP->fx_size, fixP);
2556 md_number_to_disp(place,
2557 fixP->fx_pcrel ? val + fixP->fx_pcrel_adjust : val,
2560 case 2: /* fix requested for .long .word etc */
2561 md_number_to_chars(place, val, fixP->fx_size);
2564 as_fatal("Internal error in md_apply_fix() in file \"%s\"", __FILE__);
2565 } /* OVE: maybe one ought to put _imm _disp _chars in one md-func */
2567 md_number_to_field(place, val, fixP->fx_bit_fixP);
2571 } /* md_apply_fix() */
2573 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2574 void tc_bout_fix_to_chars(where, fixP, segment_address_in_file)
2577 relax_addressT segment_address_in_file;
2579 static unsigned char nbytes_r_length [] = { 42, 0, 1, 42, 2 };
2580 struct relocation_info ri;
2583 /* JF this is for paranoia */
2584 memset((char *)&ri, '\0', sizeof(ri));
2585 symbolP = fixP->fx_addsy;
2586 know(symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2587 ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2588 /* These two 'cuz of NS32K */
2589 ri.r_callj = fixP->fx_callj;
2590 if(fixP->fx_bit_fixP) {
2594 ri.r_length = nbytes_r_length[fixP->fx_size];
2596 ri.r_pcrel = fixP->fx_pcrel;
2597 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2599 if (fixP->fx_r_type != NO_RELOC)
2601 switch (fixP->fx_r_type)
2606 ri.r_length = fixP->fx_size - 1;
2620 else if (linkrelax || !S_IS_DEFINED(symbolP)) {
2622 ri.r_index = symbolP->sy_number;
2625 ri.r_index = S_GET_TYPE(symbolP);
2628 /* Output the relocation information in machine-dependent form. */
2629 md_ri_to_chars(where, &ri);
2632 } /* tc_bout_fix_to_chars() */
2634 #endif /* OBJ_AOUT or OBJ_BOUT */
2636 /* Align an address by rounding it up to the specified boundary.
2638 long md_section_align(seg, addr)
2640 long addr; /* Address to be rounded up */
2642 return((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
2643 } /* md_section_align() */
2646 void tc_headers_hook(headers)
2647 object_headers *headers;
2649 /* FIXME: remove this line */ /* unsigned short arch_flag = 0; */
2651 if (iclasses_seen == I_BASE){
2652 headers->filehdr.f_flags |= F_I960CORE;
2653 } else if (iclasses_seen & I_CX){
2654 headers->filehdr.f_flags |= F_I960CA;
2655 } else if (iclasses_seen & I_MIL){
2656 headers->filehdr.f_flags |= F_I960MC;
2657 } else if (iclasses_seen & (I_DEC|I_FP)){
2658 headers->filehdr.f_flags |= F_I960KB;
2660 headers->filehdr.f_flags |= F_I960KA;
2661 } /* set arch flag */
2663 if (flagseen['R']) {
2664 headers->filehdr.f_magic = I960RWMAGIC;
2665 headers->aouthdr.magic = OMAGIC;
2667 headers->filehdr.f_magic = I960ROMAGIC;
2668 headers->aouthdr.magic = NMAGIC;
2669 } /* set magic numbers */
2672 } /* tc_headers_hook() */
2673 #endif /* OBJ_COFF */
2676 * Things going on here:
2678 * For bout, We need to assure a couple of simplifying
2679 * assumptions about leafprocs for the linker: the leafproc
2680 * entry symbols will be defined in the same assembly in
2681 * which they're declared with the '.leafproc' directive;
2682 * and if a leafproc has both 'call' and 'bal' entry points
2683 * they are both global or both local.
2685 * For coff, the call symbol has a second aux entry that
2686 * contains the bal entry point. The bal symbol becomes a
2689 * For coff representation, the call symbol has a second aux entry that
2690 * contains the bal entry point. The bal symbol becomes a label.
2694 void tc_crawl_symbol_chain(headers)
2695 object_headers *headers;
2699 for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next(symbolP)) {
2701 if (TC_S_IS_SYSPROC(symbolP)) {
2702 /* second aux entry already contains the sysproc number */
2703 S_SET_NUMBER_AUXILIARY(symbolP, 2);
2704 S_SET_STORAGE_CLASS(symbolP, C_SCALL);
2705 S_SET_DATA_TYPE(symbolP, S_GET_DATA_TYPE(symbolP) | (DT_FCN << N_BTSHFT));
2707 } /* rewrite sysproc */
2708 #endif /* OBJ_COFF */
2710 if (!TC_S_IS_BALNAME(symbolP) && !TC_S_IS_CALLNAME(symbolP)) {
2712 } /* Not a leafproc symbol */
2714 if (!S_IS_DEFINED(symbolP)) {
2715 as_bad("leafproc symbol '%s' undefined", S_GET_NAME(symbolP));
2716 } /* undefined leaf */
2718 if (TC_S_IS_CALLNAME(symbolP)) {
2719 symbolS *balP = tc_get_bal_of_call(symbolP);
2720 if (S_IS_EXTERNAL(symbolP) != S_IS_EXTERNAL(balP)) {
2721 S_SET_EXTERNAL(symbolP);
2722 S_SET_EXTERNAL(balP);
2723 as_warn("Warning: making leafproc entries %s and %s both global\n",
2724 S_GET_NAME(symbolP), S_GET_NAME(balP));
2725 } /* externality mismatch */
2727 } /* walk the symbol chain */
2730 } /* tc_crawl_symbol_chain() */
2733 * For aout or bout, the bal immediately follows the call.
2735 * For coff, we cheat and store a pointer to the bal symbol
2736 * in the second aux entry of the call.
2739 void tc_set_bal_of_call(callP, balP)
2743 know(TC_S_IS_CALLNAME(callP));
2744 know(TC_S_IS_BALNAME(balP));
2748 callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP;
2749 S_SET_NUMBER_AUXILIARY(callP,2);
2751 #elif defined(OBJ_AOUT) || defined(OBJ_BOUT)
2753 /* If the 'bal' entry doesn't immediately follow the 'call'
2754 * symbol, unlink it from the symbol list and re-insert it.
2756 if (symbol_next(callP) != balP) {
2757 symbol_remove(balP, &symbol_rootP, &symbol_lastP);
2758 symbol_append(balP, callP, &symbol_rootP, &symbol_lastP);
2759 } /* if not in order */
2762 (as yet unwritten.);
2763 #endif /* switch on OBJ_FORMAT */
2766 } /* tc_set_bal_of_call() */
2768 char *_tc_get_bal_of_call(callP)
2773 know(TC_S_IS_CALLNAME(callP));
2776 retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry);
2777 #elif defined(OBJ_AOUT) || defined(OBJ_BOUT)
2778 retval = symbol_next(callP);
2780 (as yet unwritten.);
2781 #endif /* switch on OBJ_FORMAT */
2783 know(TC_S_IS_BALNAME(retval));
2784 return((char *) retval);
2785 } /* _tc_get_bal_of_call() */
2787 void tc_coff_symbol_emit_hook(symbolP)
2790 if (TC_S_IS_CALLNAME(symbolP)) {
2792 symbolS *balP = tc_get_bal_of_call(symbolP);
2794 /* second aux entry contains the bal entry point */
2795 /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */
2796 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE(balP);
2797 S_SET_STORAGE_CLASS(symbolP, (!SF_GET_LOCAL(symbolP) ? C_LEAFEXT : C_LEAFSTAT));
2798 S_SET_DATA_TYPE(symbolP, S_GET_DATA_TYPE(symbolP) | (DT_FCN << N_BTSHFT));
2799 /* fix up the bal symbol */
2800 S_SET_STORAGE_CLASS(balP, C_LABEL);
2801 #endif /* OBJ_COFF */
2802 } /* only on calls */
2805 } /* tc_coff_symbol_emit_hook() */
2808 i960_handle_align (fragp)
2812 segT old_seg = now_seg, this_seg;
2813 int old_subseg = now_subseg;
2815 extern struct frag *text_last_frag, *data_last_frag;
2820 /* The text section "ends" with another alignment reloc, to which we
2821 aren't adding padding. */
2822 if (fragp->fr_next == text_last_frag
2823 || fragp->fr_next == data_last_frag)
2828 /* alignment directive */
2829 fixp = fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0, 0,
2830 (int) fragp->fr_type);
2840 /* end of tc-i960.c */