1 /* tc-i960.c - All the i80960-specific stuff
2 Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
4 This file is part of GAS.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20 /* See comment on md_parse_option for 80960-specific invocation options. */
22 /******************************************************************************
24 * Header, symbol, and relocation info will be used on the host machine
25 * only -- only executable code is actually downloaded to the i80960.
26 * Therefore, leave all such information in host byte order.
28 * (That's a slight lie -- we DO download some header information, but
29 * the downloader converts the file format and corrects the byte-ordering
30 * of the relevant fields while doing so.)
32 * ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER
33 * FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO
34 * USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <==
36 ***************************************************************************** */
38 /* There are 4 different lengths of (potentially) symbol-based displacements
39 * in the 80960 instruction set, each of which could require address fix-ups
40 * and (in the case of external symbols) emission of relocation directives:
43 * This is a standard length for the base assembler and requires no
47 * This is a non-standard length, but the base assembler has a hook for
48 * bit field address fixups: the fixS structure can point to a descriptor
49 * of the field, in which case our md_number_to_field() routine gets called
52 * I made the hook a little cleaner by having fix_new() (in the base
53 * assembler) return a pointer to the fixS in question. And I made it a
54 * little simpler by storing the field size (in this case 13) instead of
55 * of a pointer to another structure: 80960 displacements are ALWAYS
56 * stored in the low-order bits of a 4-byte word.
58 * Since the target of a COBR cannot be external, no relocation directives
59 * for this size displacement have to be generated. But the base assembler
60 * had to be modified to issue error messages if the symbol did turn out
64 * Fixups are handled as for the 13-bit case (except that 24 is stored
67 * The relocation directive generated is the same as that for the 32-bit
68 * displacement, except that it's PC-relative (the 32-bit displacement
69 * never is). The i80960 version of the linker needs a mod to
70 * distinguish and handle the 24-bit case.
73 * MEMA formats are always promoted to MEMB (32-bit) if the displacement
74 * is based on a symbol, because it could be relocated at link time.
75 * The only time we use the 12-bit format is if an absolute value of
76 * less than 4096 is specified, in which case we need neither a fixup nor
77 * a relocation directive.
87 #include "opcode/i960.h"
89 extern char *input_line_pointer;
90 extern struct hash_control *po_hash;
91 extern char *next_object_file_charP;
94 const int md_reloc_size = sizeof (struct reloc);
96 const int md_reloc_size = sizeof (struct relocation_info);
99 /***************************
100 * Local i80960 routines *
101 ************************** */
103 static void brcnt_emit (); /* Emit branch-prediction instrumentation code */
104 static char *brlab_next (); /* Return next branch local label */
105 void brtab_emit (); /* Emit br-predict instrumentation table */
106 static void cobr_fmt (); /* Generate COBR instruction */
107 static void ctrl_fmt (); /* Generate CTRL instruction */
108 static char *emit (); /* Emit (internally) binary */
109 static int get_args (); /* Break arguments out of comma-separated list */
110 static void get_cdisp (); /* Handle COBR or CTRL displacement */
111 static char *get_ispec (); /* Find index specification string */
112 static int get_regnum (); /* Translate text to register number */
113 static int i_scan (); /* Lexical scan of instruction source */
114 static void mem_fmt (); /* Generate MEMA or MEMB instruction */
115 static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */
116 static void parse_expr (); /* Parse an expression */
117 static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */
118 static void parse_memop (); /* Parse a memory operand */
119 static void parse_po (); /* Parse machine-dependent pseudo-op */
120 static void parse_regop (); /* Parse a register operand */
121 static void reg_fmt (); /* Generate a REG format instruction */
122 void reloc_callj (); /* Relocate a 'callj' instruction */
123 static void relax_cobr (); /* "De-optimize" cobr into compare/branch */
124 static void s_leafproc (); /* Process '.leafproc' pseudo-op */
125 static void s_sysproc (); /* Process '.sysproc' pseudo-op */
126 static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */
127 static void syntax (); /* Give syntax error */
128 static int targ_has_sfr (); /* Target chip supports spec-func register? */
129 static int targ_has_iclass (); /* Target chip supports instruction set? */
130 /* static void unlink_sym(); *//* Remove a symbol from the symbol list */
132 /* See md_parse_option() for meanings of these options */
133 static char norelax; /* True if -norelax switch seen */
134 static char instrument_branches;/* True if -b switch seen */
136 /* Characters that always start a comment.
137 * If the pre-processor is disabled, these aren't very useful.
139 const char comment_chars[] = "#";
141 /* Characters that only start a comment at the beginning of
142 * a line. If the line seems to have the form '# 123 filename'
143 * .line and .file directives will appear in the pre-processed output.
145 * Note that input_file.c hand checks for '#' at the beginning of the
146 * first line of the input file. This is because the compiler outputs
147 * #NO_APP at the beginning of its output.
150 /* Also note that comments started like this one will always work. */
152 const char line_comment_chars[1];
154 const char line_separator_chars[1];
156 /* Chars that can be used to separate mant from exp in floating point nums */
157 const char EXP_CHARS[] = "eE";
159 /* Chars that mean this number is a floating point constant,
160 * as in 0f12.456 or 0d1.2345e12
162 const char FLT_CHARS[] = "fFdDtT";
165 /* Table used by base assembler to relax addresses based on varying length
166 * instructions. The fields are:
167 * 1) most positive reach of this state,
168 * 2) most negative reach of this state,
169 * 3) how many bytes this mode will add to the size of the current frag
170 * 4) which index into the table to try if we can't fit into this one.
172 * For i80960, the only application is the (de-)optimization of cobr
173 * instructions into separate compare and branch instructions when a 13-bit
174 * displacement won't hack it.
179 {0, 0, 0, 0}, /* State 0 => no more relaxation possible */
180 {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */
181 {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */
185 /* These are the machine dependent pseudo-ops.
187 * This table describes all the machine specific pseudo-ops the assembler
188 * has to support. The fields are:
189 * pseudo-op name without dot
190 * function to call to execute this pseudo-op
191 * integer arg to pass to the function
196 const pseudo_typeS md_pseudo_table[] =
199 {"extended", float_cons, 't'},
200 {"leafproc", parse_po, S_LEAFPROC},
201 {"sysproc", parse_po, S_SYSPROC},
209 /* Macros to extract info from an 'expressionS' structure 'e' */
210 #define adds(e) e.X_add_symbol
211 #define offs(e) e.X_add_number
214 /* Branch-prediction bits for CTRL/COBR format opcodes */
215 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
216 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
217 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
220 /* Some instruction opcodes that we need explicitly */
221 #define BE 0x12000000
222 #define BG 0x11000000
223 #define BGE 0x13000000
224 #define BL 0x14000000
225 #define BLE 0x16000000
226 #define BNE 0x15000000
227 #define BNO 0x10000000
228 #define BO 0x17000000
229 #define CHKBIT 0x5a002700
230 #define CMPI 0x5a002080
231 #define CMPO 0x5a002000
234 #define BAL 0x0b000000
235 #define CALL 0x09000000
236 #define CALLS 0x66003800
237 #define RET 0x0a000000
240 /* These masks are used to build up a set of MEMB mode bits. */
243 #define MEMB_BIT 0x1000
247 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
249 #define MEMA_ABASE 0x2000
251 /* Info from which a MEMA or MEMB format instruction can be generated */
254 /* (First) 32 bits of instruction */
256 /* 0-(none), 12- or, 32-bit displacement needed */
258 /* The expression in the source instruction from which the
259 displacement should be determined. */
266 /* The two pieces of info we need to generate a register operand */
269 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
270 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
271 int n; /* Register number or literal value */
275 /* Number and assembler mnemonic for all registers that can appear in operands */
317 /* Numbers for special-function registers are for assembler internal
318 use only: they are scaled back to range [0-31] for binary output. */
354 /* Numbers for floating point registers are for assembler internal use
355 * only: they are scaled back to [0-3] for binary output.
364 { NULL, 0 }, /* END OF LIST */
367 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
368 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
369 #define IS_FP_REG(n) ((n) >= FP0)
371 /* Number and assembler mnemonic for all registers that can appear as 'abase'
372 * (indirect addressing) registers.
416 /* For assembler internal use only: this number never appears in binary
420 { NULL, 0 }, /* END OF LIST */
425 static struct hash_control *op_hash; /* Opcode mnemonics */
426 static struct hash_control *reg_hash; /* Register name hash table */
427 static struct hash_control *areg_hash; /* Abase register hash table */
430 /* Architecture for which we are assembling */
431 #define ARCH_ANY 0 /* Default: no architecture checking done */
436 int architecture = ARCH_ANY; /* Architecture requested on invocation line */
437 int iclasses_seen; /* OR of instruction classes (I_* constants)
438 * for which we've actually assembled
443 /* BRANCH-PREDICTION INSTRUMENTATION
445 * The following supports generation of branch-prediction instrumentation
446 * (turned on by -b switch). The instrumentation collects counts
447 * of branches taken/not-taken for later input to a utility that will
448 * set the branch prediction bits of the instructions in accordance with
449 * the behavior observed. (Note that the KX series does not have
452 * The instrumentation consists of:
454 * (1) before and after each conditional branch, a call to an external
455 * routine that increments and steps over an inline counter. The
456 * counter itself, initialized to 0, immediately follows the call
457 * instruction. For each branch, the counter following the branch
458 * is the number of times the branch was not taken, and the difference
459 * between the counters is the number of times it was taken. An
460 * example of an instrumented conditional branch:
464 * LBRANCH23: be label
468 * (2) a table of pointers to the instrumented branches, so that an
469 * external postprocessing routine can locate all of the counters.
470 * the table begins with a 2-word header: a pointer to the next in
471 * a linked list of such tables (initialized to 0); and a count
472 * of the number of entries in the table (exclusive of the header.
474 * Note that input source code is expected to already contain calls
475 * an external routine that will link the branch local table into a
476 * list of such tables.
479 static int br_cnt; /* Number of branches instrumented so far.
480 * Also used to generate unique local labels
481 * for each instrumented branch
484 #define BR_LABEL_BASE "LBRANCH"
485 /* Basename of local labels on instrumented
486 * branches, to avoid conflict with compiler-
487 * generated local labels.
490 #define BR_CNT_FUNC "__inc_branch"
491 /* Name of the external routine that will
492 * increment (and step over) an inline counter.
495 #define BR_TAB_NAME "__BRANCH_TABLE__"
496 /* Name of the table of pointers to branches.
497 * A local (i.e., non-external) symbol.
500 /*****************************************************************************
501 * md_begin: One-time initialization.
503 * Set up hash tables.
505 **************************************************************************** */
509 int i; /* Loop counter */
510 const struct i960_opcode *oP; /* Pointer into opcode table */
511 const char *retval; /* Value returned by hash functions */
513 if (((op_hash = hash_new ()) == 0)
514 || ((reg_hash = hash_new ()) == 0)
515 || ((areg_hash = hash_new ()) == 0))
516 as_fatal ("virtual memory exceeded");
518 /* For some reason, the base assembler uses an empty string for "no
519 error message", instead of a NULL pointer. */
522 for (oP = i960_opcodes; oP->name && !retval; oP++)
523 retval = hash_insert (op_hash, oP->name, (PTR) oP);
525 for (i = 0; regnames[i].reg_name && !retval; i++)
526 retval = hash_insert (reg_hash, regnames[i].reg_name,
527 ®names[i].reg_num);
529 for (i = 0; aregs[i].areg_name && !retval; i++)
530 retval = hash_insert (areg_hash, aregs[i].areg_name,
534 as_fatal ("Hashing returned \"%s\".", retval);
537 /*****************************************************************************
538 * md_end: One-time final cleanup
542 **************************************************************************** */
548 /*****************************************************************************
549 * md_assemble: Assemble an instruction
551 * Assumptions about the passed-in text:
552 * - all comments, labels removed
553 * - text is an instruction
554 * - all white space compressed to single blanks
555 * - all character constants have been replaced with decimal
557 **************************************************************************** */
560 char *textP; /* Source text of instruction */
562 /* Parsed instruction text, containing NO whitespace:
563 * arg[0]->opcode mnemonic
564 * arg[1-3]->operands, with char constants
565 * replaced by decimal numbers
569 int n_ops; /* Number of instruction operands */
570 /* Pointer to instruction description */
571 struct i960_opcode *oP;
572 /* TRUE iff opcode mnemonic included branch-prediction
573 * suffix (".f" or ".t")
576 /* Setting of branch-prediction bit(s) to be OR'd
577 * into instruction opcode of CTRL/COBR format
582 int n; /* Offset of last character in opcode mnemonic */
584 static const char bp_error_msg[] = "branch prediction invalid on this opcode";
587 /* Parse instruction into opcode and operands */
588 memset (args, '\0', sizeof (args));
589 n_ops = i_scan (textP, args);
592 return; /* Error message already issued */
595 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
596 if (!strcmp (args[0], "ldconst"))
598 n_ops = parse_ldconst (args);
607 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
608 n = strlen (args[0]) - 1;
611 if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
613 /* We could check here to see if the target architecture
614 * supports branch prediction, but why bother? The bit
615 * will just be ignored by processors that don't use it.
618 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
619 args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
622 /* Look up opcode mnemonic in table and check number of operands.
623 * Check that opcode is legal for the target architecture.
624 * If all looks good, assemble instruction.
626 oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
627 if (!oP || !targ_has_iclass (oP->iclass))
629 as_bad ("invalid opcode, \"%s\".", args[0]);
632 else if (n_ops != oP->num_ops)
634 as_bad ("improper number of operands. expecting %d, got %d",
643 ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
644 if (oP->format == FBRA)
646 /* Now generate a 'bno' to same arg */
647 ctrl_fmt (args[1], BNO | bp_bits, 1);
652 cobr_fmt (args, oP->opcode | bp_bits, oP);
657 as_warn (bp_error_msg);
662 if (args[0][0] == 'c' && args[0][1] == 'a')
666 as_warn (bp_error_msg);
668 mem_fmt (args, oP, 1);
678 as_warn (bp_error_msg);
680 mem_fmt (args, oP, 0);
685 as_warn (bp_error_msg);
687 /* Output opcode & set up "fixup" (relocation);
688 * flag relocation as 'callj' type.
690 know (oP->num_ops == 1);
691 get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
694 BAD_CASE (oP->format);
698 } /* md_assemble() */
700 /*****************************************************************************
701 * md_number_to_chars: convert a number to target byte order
703 **************************************************************************** */
705 md_number_to_chars (buf, value, n)
706 char *buf; /* Put output here */
707 valueT value; /* The integer to be converted */
708 int n; /* Number of bytes to output (significant bytes
718 /* XXX line number probably botched for this warning message. */
719 if (value != 0 && value != -1)
721 as_bad ("Displacement too long for instruction field length.");
725 } /* md_number_to_chars() */
727 /*****************************************************************************
728 * md_chars_to_number: convert from target byte order to host byte order.
730 **************************************************************************** */
732 md_chars_to_number (val, n)
733 unsigned char *val; /* Value in target byte order */
734 int n; /* Number of bytes in the input */
738 for (retval = 0; n--;)
747 #define MAX_LITTLENUMS 6
748 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
750 /*****************************************************************************
751 * md_atof: convert ascii to floating point
753 * Turn a string at input_line_pointer into a floating point constant of type
754 * 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
755 * emitted is returned at 'sizeP'. An error message is returned, or a pointer
756 * to an empty message if OK.
758 * Note we call the i386 floating point routine, rather than complicating
759 * things with more files or symbolic links.
761 **************************************************************************** */
763 md_atof (type, litP, sizeP)
768 LITTLENUM_TYPE words[MAX_LITTLENUMS];
769 LITTLENUM_TYPE *wordP;
789 type = 'x'; /* That's what atof_ieee() understands */
794 return "Bad call to md_atof()";
797 t = atof_ieee (input_line_pointer, type, words);
800 input_line_pointer = t;
803 *sizeP = prec * LNUM_SIZE;
805 /* Output the LITTLENUMs in REVERSE order in accord with i80960
806 * word-order. (Dunno why atof_ieee doesn't do it in the right
807 * order in the first place -- probably because it's a hack of
811 for (wordP = words + prec - 1; prec--;)
813 md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
814 litP += sizeof (LITTLENUM_TYPE);
817 return ""; /* Someone should teach Dean about null pointers */
821 /*****************************************************************************
824 **************************************************************************** */
826 md_number_to_imm (buf, val, n)
831 md_number_to_chars (buf, val, n);
835 /*****************************************************************************
838 **************************************************************************** */
840 md_number_to_disp (buf, val, n)
845 md_number_to_chars (buf, val, n);
848 /*****************************************************************************
849 * md_number_to_field:
851 * Stick a value (an address fixup) into a bit field of
852 * previously-generated instruction.
854 **************************************************************************** */
856 md_number_to_field (instrP, val, bfixP)
857 char *instrP; /* Pointer to instruction to be fixed */
858 long val; /* Address fixup value */
859 bit_fixS *bfixP; /* Description of bit field to be fixed up */
861 int numbits; /* Length of bit field to be fixed */
862 long instr; /* 32-bit instruction to be fixed-up */
863 long sign; /* 0 or -1, according to sign bit of 'val' */
865 /* Convert instruction back to host byte order
867 instr = md_chars_to_number (instrP, 4);
869 /* Surprise! -- we stored the number of bits
870 * to be modified rather than a pointer to a structure.
872 numbits = (int) bfixP;
875 /* This is a no-op, stuck here by reloc_callj() */
879 know ((numbits == 13) || (numbits == 24));
881 /* Propagate sign bit of 'val' for the given number of bits.
882 * Result should be all 0 or all 1
884 sign = val >> ((int) numbits - 1);
885 if (((val < 0) && (sign != -1))
886 || ((val > 0) && (sign != 0)))
888 as_bad ("Fixup of %ld too large for field width of %d",
893 /* Put bit field into instruction and write back in target
896 val &= ~(-1 << (int) numbits); /* Clear unused sign bits */
898 md_number_to_chars (instrP, instr, 4);
900 } /* md_number_to_field() */
903 /*****************************************************************************
905 * Invocation line includes a switch not recognized by the base assembler.
906 * See if it's a processor-specific option. For the 960, these are:
909 * Conditional branch instructions that require displacements
910 * greater than 13 bits (or that have external targets) should
911 * generate errors. The default is to replace each such
912 * instruction with the corresponding compare (or chkbit) and
913 * branch instructions. Note that the Intel "j" cobr directives
914 * are ALWAYS "de-optimized" in this way when necessary,
915 * regardless of the setting of this option.
918 * Add code to collect information about branches taken, for
919 * later optimization of branch prediction bits by a separate
920 * tool. COBR and CNTL format instructions have branch
921 * prediction bits (in the CX architecture); if "BR" represents
922 * an instruction in one of these classes, the following rep-
923 * resents the code generated by the assembler:
925 * call <increment routine>
926 * .word 0 # pre-counter
928 * call <increment routine>
929 * .word 0 # post-counter
931 * A table of all such "Labels" is also generated.
934 * -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
935 * Select the 80960 architecture. Instructions or features not
936 * supported by the selected architecture cause fatal errors.
937 * The default is to generate code for any instruction or feature
938 * that is supported by SOME version of the 960 (even if this
939 * means mixing architectures!).
941 **************************************************************************** */
943 md_parse_option (argP, cntP, vecP)
954 static struct tabentry arch_tab[] =
958 { "SA", ARCH_KA }, /* Synonym for KA */
959 { "SB", ARCH_KB }, /* Synonym for KB */
960 { "KC", ARCH_MC }, /* Synonym for MC */
966 if (!strcmp (*argP, "linkrelax"))
971 else if (!strcmp (*argP, "norelax"))
976 else if (**argP == 'b')
978 instrument_branches = 1;
981 else if (**argP == 'A')
985 for (tp = arch_tab; tp->flag != NULL; tp++)
987 if (!strcmp (p, tp->flag))
993 if (tp->flag == NULL)
995 as_bad ("unknown architecture: %s", p);
999 architecture = tp->arch;
1004 /* Unknown option */
1008 **argP = '\0'; /* Done parsing this switch */
1012 /*****************************************************************************
1014 * Called by base assembler after address relaxation is finished: modify
1015 * variable fragments according to how much relaxation was done.
1017 * If the fragment substate is still 1, a 13-bit displacement was enough
1018 * to reach the symbol in question. Set up an address fixup, but otherwise
1019 * leave the cobr instruction alone.
1021 * If the fragment substate is 2, a 13-bit displacement was not enough.
1022 * Replace the cobr with a two instructions (a compare and a branch).
1024 **************************************************************************** */
1026 md_convert_frag (headers, fragP)
1027 object_headers *headers;
1030 fixS *fixP; /* Structure describing needed address fix */
1032 switch (fragP->fr_subtype)
1035 /* LEAVE SINGLE COBR INSTRUCTION */
1036 fixP = fix_new (fragP,
1037 fragP->fr_opcode - fragP->fr_literal,
1044 fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */
1047 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
1051 BAD_CASE (fragP->fr_subtype);
1056 /*****************************************************************************
1057 * md_estimate_size_before_relax: How much does it look like *fragP will grow?
1059 * Called by base assembler just before address relaxation.
1060 * Return the amount by which the fragment will grow.
1062 * Any symbol that is now undefined will not become defined; cobr's
1063 * based on undefined symbols will have to be replaced with a compare
1064 * instruction and a branch instruction, and the code fragment will grow
1067 **************************************************************************** */
1069 md_estimate_size_before_relax (fragP, segment_type)
1070 register fragS *fragP;
1071 register segT segment_type;
1073 /* If symbol is undefined in this segment, go to "relaxed" state
1074 * (compare and branch instructions instead of cobr) right now.
1076 if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
1082 } /* md_estimate_size_before_relax() */
1085 /*****************************************************************************
1087 * This routine exists in order to overcome machine byte-order problems
1088 * when dealing with bit-field entries in the relocation_info struct.
1090 * But relocation info will be used on the host machine only (only
1091 * executable code is actually downloaded to the i80960). Therefore,
1092 * we leave it in host byte order.
1094 * The above comment is no longer true. This routine now really
1095 * does do the reordering (Ian Taylor 28 Aug 92).
1097 **************************************************************************** */
1099 md_ri_to_chars (where, ri)
1101 struct relocation_info *ri;
1103 md_number_to_chars (where, ri->r_address,
1104 sizeof (ri->r_address));
1105 where[4] = ri->r_index & 0x0ff;
1106 where[5] = (ri->r_index >> 8) & 0x0ff;
1107 where[6] = (ri->r_index >> 16) & 0x0ff;
1108 where[7] = ((ri->r_pcrel << 0)
1109 | (ri->r_length << 1)
1110 | (ri->r_extern << 3)
1113 | (ri->r_callj << 6));
1114 } /* md_ri_to_chars() */
1116 #ifndef WORKING_DOT_WORD
1118 int md_short_jump_size = 0;
1119 int md_long_jump_size = 0;
1122 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
1129 as_fatal ("failed sanity check.");
1133 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
1135 addressT from_addr, to_addr;
1139 as_fatal ("failed sanity check.");
1144 /*************************************************************
1146 * FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER *
1148 ************************************************************ */
1152 /*****************************************************************************
1153 * brcnt_emit: Emit code to increment inline branch counter.
1155 * See the comments above the declaration of 'br_cnt' for details on
1156 * branch-prediction instrumentation.
1157 **************************************************************************** */
1161 ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */
1162 emit (0); /* Emit inline counter to be incremented */
1165 /*****************************************************************************
1166 * brlab_next: generate the next branch local label
1168 * See the comments above the declaration of 'br_cnt' for details on
1169 * branch-prediction instrumentation.
1170 **************************************************************************** */
1174 static char buf[20];
1176 sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1180 /*****************************************************************************
1181 * brtab_emit: generate the fetch-prediction branch table.
1183 * See the comments above the declaration of 'br_cnt' for details on
1184 * branch-prediction instrumentation.
1186 * The code emitted here would be functionally equivalent to the following
1187 * example assembler source.
1192 * .word 0 # link to next table
1193 * .word 3 # length of table
1194 * .word LBRANCH0 # 1st entry in table proper
1197 ***************************************************************************** */
1203 char *p; /* Where the binary was output to */
1204 fixS *fixP; /*->description of deferred address fixup */
1206 if (!instrument_branches)
1211 subseg_set (SEG_DATA, 0); /* .data */
1212 frag_align (2, 0); /* .align 2 */
1213 record_alignment (now_seg, 2);
1214 colon (BR_TAB_NAME); /* BR_TAB_NAME: */
1215 emit (0); /* .word 0 #link to next table */
1216 emit (br_cnt); /* .word n #length of table */
1218 for (i = 0; i < br_cnt; i++)
1220 sprintf (buf, "%s%d", BR_LABEL_BASE, i);
1222 fixP = fix_new (frag_now,
1223 p - frag_now->fr_literal,
1229 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1233 /*****************************************************************************
1234 * cobr_fmt: generate a COBR-format instruction
1236 **************************************************************************** */
1239 cobr_fmt (arg, opcode, oP)
1240 char *arg[]; /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1241 long opcode; /* Opcode, with branch-prediction bits already set
1244 struct i960_opcode *oP;
1245 /*->description of instruction */
1247 long instr; /* 32-bit instruction */
1248 struct regop regop; /* Description of register operand */
1249 int n; /* Number of operands */
1250 int var_frag; /* 1 if varying length code fragment should
1251 * be emitted; 0 if an address fix
1252 * should be emitted.
1260 /* First operand (if any) of a COBR is always a register
1261 * operand. Parse it.
1263 parse_regop (®op, arg[1], oP->operand[0]);
1264 instr |= (regop.n << 19) | (regop.mode << 13);
1268 /* Second operand (if any) of a COBR is always a register
1269 * operand. Parse it.
1271 parse_regop (®op, arg[2], oP->operand[1]);
1272 instr |= (regop.n << 14) | regop.special;
1283 if (instrument_branches)
1286 colon (brlab_next ());
1289 /* A third operand to a COBR is always a displacement.
1290 * Parse it; if it's relaxable (a cobr "j" directive, or any
1291 * cobr other than bbs/bbc when the "-norelax" option is not in
1292 * use) set up a variable code fragment; otherwise set up an
1295 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1296 get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1298 if (instrument_branches)
1306 /*****************************************************************************
1307 * ctrl_fmt: generate a CTRL-format instruction
1309 **************************************************************************** */
1312 ctrl_fmt (targP, opcode, num_ops)
1313 char *targP; /* Pointer to text of lone operand (if any) */
1314 long opcode; /* Template of instruction */
1315 int num_ops; /* Number of operands */
1317 int instrument; /* TRUE iff we should add instrumentation to track
1318 * how often the branch is taken
1324 emit (opcode); /* Output opcode */
1329 instrument = instrument_branches && (opcode != CALL)
1330 && (opcode != B) && (opcode != RET) && (opcode != BAL);
1335 colon (brlab_next ());
1338 /* The operand MUST be an ip-relative displacment. Parse it
1339 * and set up address fix for the instruction we just output.
1341 get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1352 /*****************************************************************************
1353 * emit: output instruction binary
1355 * Output instruction binary, in target byte order, 4 bytes at a time.
1356 * Return pointer to where it was placed.
1358 **************************************************************************** */
1362 long instr; /* Word to be output, host byte order */
1364 char *toP; /* Where to output it */
1366 toP = frag_more (4); /* Allocate storage */
1367 md_number_to_chars (toP, instr, 4); /* Convert to target byte order */
1372 /*****************************************************************************
1373 * get_args: break individual arguments out of comma-separated list
1375 * Input assumptions:
1376 * - all comments and labels have been removed
1377 * - all strings of whitespace have been collapsed to a single blank.
1378 * - all character constants ('x') have been replaced with decimal
1381 * args[0] is untouched. args[1] points to first operand, etc. All args:
1382 * - are NULL-terminated
1383 * - contain no whitespace
1386 * Number of operands (0,1,2, or 3) or -1 on error.
1388 **************************************************************************** */
1391 register char *p; /* Pointer to comma-separated operands; MUCKED BY US */
1392 char *args[]; /* Output arg: pointers to operands placed in args[1-3].
1393 * MUST ACCOMMODATE 4 ENTRIES (args[0-3]).
1396 register int n; /* Number of operands */
1402 /* Skip lead white space */
1416 /* Squeze blanks out by moving non-blanks toward start of string.
1417 * Isolate operands, whenever comma is found.
1431 /* Start of operand */
1434 as_bad ("too many operands");
1437 *to++ = '\0'; /* Terminate argument */
1438 args[++n] = to; /* Start next argument */
1452 /*****************************************************************************
1453 * get_cdisp: handle displacement for a COBR or CTRL instruction.
1455 * Parse displacement for a COBR or CTRL instruction.
1457 * If successful, output the instruction opcode and set up for it,
1458 * depending on the arg 'var_frag', either:
1459 * o an address fixup to be done when all symbol values are known, or
1460 * o a varying length code fragment, with address fixup info. This
1461 * will be done for cobr instructions that may have to be relaxed
1462 * in to compare/branch instructions (8 bytes) if the final
1463 * address displacement is greater than 13 bits.
1465 *****************************************************************************/
1468 get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
1469 /* displacement as specified in source instruction */
1471 /* "COBR" or "CTRL" (for use in error message) */
1473 /* Instruction needing the displacement */
1475 /* # bits of displacement (13 for COBR, 24 for CTRL) */
1477 /* 1 if varying length code fragment should be emitted;
1478 * 0 if an address fix should be emitted.
1481 /* 1 if callj relocation should be done; else 0 */
1484 expressionS e; /* Parsed expression */
1485 fixS *fixP; /* Structure describing needed address fix */
1486 char *outP; /* Where instruction binary is output to */
1490 parse_expr (dispP, &e);
1494 as_bad ("expression syntax error");
1497 if (S_GET_SEGMENT (e.X_add_symbol) == text_section
1498 || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
1502 outP = frag_more (8); /* Allocate worst-case storage */
1503 md_number_to_chars (outP, instr, 4);
1504 frag_variant (rs_machine_dependent, 4, 4, 1,
1505 adds (e), offs (e), outP, 0, 0);
1509 /* Set up a new fix structure, so address can be updated
1510 * when all symbol values are known.
1512 outP = emit (instr);
1513 fixP = fix_new (frag_now,
1514 outP - frag_now->fr_literal,
1521 fixP->fx_callj = callj;
1523 /* We want to modify a bit field when the address is
1524 * known. But we don't need all the garbage in the
1525 * bit_fix structure. So we're going to lie and store
1526 * the number of bits affected instead of a pointer.
1528 fixP->fx_bit_fixP = (bit_fixS *) numbits;
1532 as_bad ("attempt to branch into different segment");
1536 as_bad ("target of %s instruction must be a label", ifmtP);
1542 /*****************************************************************************
1543 * get_ispec: parse a memory operand for an index specification
1545 * Here, an "index specification" is taken to be anything surrounded
1546 * by square brackets and NOT followed by anything else.
1548 * If it's found, detach it from the input string, remove the surrounding
1549 * square brackets, and return a pointer to it. Otherwise, return NULL.
1551 **************************************************************************** */
1555 char *textP; /*->memory operand from source instruction, no white space */
1557 char *start; /*->start of index specification */
1558 char *end; /*->end of index specification */
1560 /* Find opening square bracket, if any
1562 start = strchr (textP, '[');
1567 /* Eliminate '[', detach from rest of operand */
1570 end = strchr (start, ']');
1574 as_bad ("unmatched '['");
1579 /* Eliminate ']' and make sure it was the last thing
1583 if (*(end + 1) != '\0')
1585 as_bad ("garbage after index spec ignored");
1592 /*****************************************************************************
1595 * Look up a (suspected) register name in the register table and return the
1596 * associated register number (or -1 if not found).
1598 **************************************************************************** */
1601 get_regnum (regname)
1602 char *regname; /* Suspected register name */
1606 rP = (int *) hash_find (reg_hash, regname);
1607 return (rP == NULL) ? -1 : *rP;
1611 /*****************************************************************************
1612 * i_scan: perform lexical scan of ascii assembler instruction.
1614 * Input assumptions:
1615 * - input string is an i80960 instruction (not a pseudo-op)
1616 * - all comments and labels have been removed
1617 * - all strings of whitespace have been collapsed to a single blank.
1620 * args[0] points to opcode, other entries point to operands. All strings:
1621 * - are NULL-terminated
1622 * - contain no whitespace
1623 * - have character constants ('x') replaced with a decimal number
1626 * Number of operands (0,1,2, or 3) or -1 on error.
1628 **************************************************************************** */
1631 register char *iP; /* Pointer to ascii instruction; MUCKED BY US. */
1632 char *args[]; /* Output arg: pointers to opcode and operands placed
1633 * here. MUST ACCOMMODATE 4 ENTRIES.
1637 /* Isolate opcode */
1641 } /* Skip lead space, if any */
1643 for (; *iP != ' '; iP++)
1647 /* There are no operands */
1650 /* We never moved: there was no opcode either! */
1651 as_bad ("missing opcode");
1657 *iP++ = '\0'; /* Terminate opcode */
1658 return (get_args (iP, args));
1662 /*****************************************************************************
1663 * mem_fmt: generate a MEMA- or MEMB-format instruction
1665 **************************************************************************** */
1667 mem_fmt (args, oP, callx)
1668 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1669 struct i960_opcode *oP; /* Pointer to description of instruction */
1670 int callx; /* Is this a callx opcode */
1672 int i; /* Loop counter */
1673 struct regop regop; /* Description of register operand */
1674 char opdesc; /* Operand descriptor byte */
1675 memS instr; /* Description of binary to be output */
1676 char *outP; /* Where the binary was output to */
1677 expressionS expr; /* Parsed expression */
1678 fixS *fixP; /*->description of deferred address fixup */
1680 memset (&instr, '\0', sizeof (memS));
1681 instr.opcode = oP->opcode;
1683 /* Process operands. */
1684 for (i = 1; i <= oP->num_ops; i++)
1686 opdesc = oP->operand[i - 1];
1690 parse_memop (&instr, args[i], oP->format);
1694 parse_regop (®op, args[i], opdesc);
1695 instr.opcode |= regop.n << 19;
1700 outP = emit (instr.opcode);
1702 if (instr.disp == 0)
1707 /* Parse and process the displacement */
1708 parse_expr (instr.e, &expr);
1712 as_bad ("expression syntax error");
1716 if (instr.disp == 32)
1718 (void) emit (offs (expr)); /* Output displacement */
1722 /* 12-bit displacement */
1723 if (offs (expr) & ~0xfff)
1725 /* Won't fit in 12 bits: convert already-output
1726 * instruction to MEMB format, output
1729 mema_to_memb (outP);
1730 (void) emit (offs (expr));
1734 /* WILL fit in 12 bits: OR into opcode and
1735 * overwrite the binary we already put out
1737 instr.opcode |= offs (expr);
1738 md_number_to_chars (outP, instr.opcode, 4);
1744 if (instr.disp == 12)
1746 /* Displacement is dependent on a symbol, whose value
1747 * may change at link time. We HAVE to reserve 32 bits.
1748 * Convert already-output opcode to MEMB format.
1750 mema_to_memb (outP);
1753 /* Output 0 displacement and set up address fixup for when
1754 * this symbol's value becomes known.
1756 outP = emit ((long) 0);
1757 fixP = fix_new_exp (frag_now,
1758 outP - frag_now->fr_literal,
1763 fixP->fx_im_disp = 2; /* 32-bit displacement fix */
1764 fixP->fx_bsr = callx; /*SAC LD RELAX HACK *//* Mark reloc as being in i stream */
1770 /*****************************************************************************
1771 * mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1773 * There are 2 possible MEMA formats:
1774 * - displacement only
1775 * - displacement + abase
1777 * They are distinguished by the setting of the MEMA_ABASE bit.
1779 **************************************************************************** */
1781 mema_to_memb (opcodeP)
1782 char *opcodeP; /* Where to find the opcode, in target byte order */
1784 long opcode; /* Opcode in host byte order */
1785 long mode; /* Mode bits for MEMB instruction */
1787 opcode = md_chars_to_number (opcodeP, 4);
1788 know (!(opcode & MEMB_BIT));
1790 mode = MEMB_BIT | D_BIT;
1791 if (opcode & MEMA_ABASE)
1796 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */
1797 opcode |= mode; /* Set MEMB mode bits */
1799 md_number_to_chars (opcodeP, opcode, 4);
1800 } /* mema_to_memb() */
1803 /*****************************************************************************
1804 * parse_expr: parse an expression
1806 * Use base assembler's expression parser to parse an expression.
1807 * It, unfortunately, runs off a global which we have to save/restore
1808 * in order to make it work for us.
1810 * An empty expression string is treated as an absolute 0.
1812 * Sets O_illegal regardless of expression evaluation if entire input
1813 * string is not consumed in the evaluation -- tolerate no dangling junk!
1815 **************************************************************************** */
1817 parse_expr (textP, expP)
1818 char *textP; /* Text of expression to be parsed */
1819 expressionS *expP; /* Where to put the results of parsing */
1821 char *save_in; /* Save global here */
1828 /* Treat empty string as absolute 0 */
1829 expP->X_add_symbol = expP->X_op_symbol = NULL;
1830 expP->X_add_number = 0;
1831 expP->X_op = O_constant;
1835 save_in = input_line_pointer; /* Save global */
1836 input_line_pointer = textP; /* Make parser work for us */
1838 (void) expression (expP);
1839 if (input_line_pointer - textP != strlen (textP))
1841 /* Did not consume all of the input */
1842 expP->X_op = O_illegal;
1844 symP = expP->X_add_symbol;
1845 if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
1847 /* Register name in an expression */
1848 /* FIXME: this isn't much of a check any more. */
1849 expP->X_op = O_illegal;
1852 input_line_pointer = save_in; /* Restore global */
1857 /*****************************************************************************
1859 * Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1860 * i80960 instruction.
1862 * Assumes the input consists of:
1863 * arg[0] opcode mnemonic ('ldconst')
1864 * arg[1] first operand (constant)
1865 * arg[2] name of register to be loaded
1867 * Replaces opcode and/or operands as appropriate.
1869 * Returns the new number of arguments, or -1 on failure.
1871 **************************************************************************** */
1875 char *arg[]; /* See above */
1877 int n; /* Constant to be loaded */
1878 int shift; /* Shift count for "shlo" instruction */
1879 static char buf[5]; /* Literal for first operand */
1880 static char buf2[5]; /* Literal for second operand */
1881 expressionS e; /* Parsed expression */
1884 arg[3] = NULL; /* So we can tell at the end if it got used or not */
1886 parse_expr (arg[1], &e);
1890 /* We're dependent on one or more symbols -- use "lda" */
1895 /* Try the following mappings:
1896 * ldconst 0,<reg> ->mov 0,<reg>
1897 * ldconst 31,<reg> ->mov 31,<reg>
1898 * ldconst 32,<reg> ->addo 1,31,<reg>
1899 * ldconst 62,<reg> ->addo 31,31,<reg>
1900 * ldconst 64,<reg> ->shlo 8,3,<reg>
1901 * ldconst -1,<reg> ->subo 1,0,<reg>
1902 * ldconst -31,<reg>->subo 31,0,<reg>
1904 * anthing else becomes:
1908 if ((0 <= n) && (n <= 31))
1913 else if ((-31 <= n) && (n <= -1))
1917 sprintf (buf, "%d", -n);
1922 else if ((32 <= n) && (n <= 62))
1927 sprintf (buf, "%d", n - 31);
1931 else if ((shift = shift_ok (n)) != 0)
1935 sprintf (buf, "%d", shift);
1937 sprintf (buf2, "%d", n >> shift);
1948 as_bad ("invalid constant");
1952 return (arg[3] == 0) ? 2 : 3;
1955 /*****************************************************************************
1956 * parse_memop: parse a memory operand
1958 * This routine is based on the observation that the 4 mode bits of the
1959 * MEMB format, taken individually, have fairly consistent meaning:
1961 * M3 (bit 13): 1 if displacement is present (D_BIT)
1962 * M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1963 * M1 (bit 11): 1 if index is present (I_BIT)
1964 * M0 (bit 10): 1 if abase is present (A_BIT)
1966 * So we parse the memory operand and set bits in the mode as we find
1967 * things. Then at the end, if we go to MEMB format, we need only set
1968 * the MEMB bit (M2) and our mode is built for us.
1970 * Unfortunately, I said "fairly consistent". The exceptions:
1973 * 0100 Would seem illegal, but means "abase-only".
1975 * 0101 Would seem to mean "abase-only" -- it means IP-relative.
1976 * Must be converted to 0100.
1978 * 0110 Would seem to mean "index-only", but is reserved.
1979 * We turn on the D bit and provide a 0 displacement.
1981 * The other thing to observe is that we parse from the right, peeling
1982 * things * off as we go: first any index spec, then any abase, then
1985 **************************************************************************** */
1988 parse_memop (memP, argP, optype)
1989 memS *memP; /* Where to put the results */
1990 char *argP; /* Text of the operand to be parsed */
1991 int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
1993 char *indexP; /* Pointer to index specification with "[]" removed */
1994 char *p; /* Temp char pointer */
1995 char iprel_flag; /* True if this is an IP-relative operand */
1996 int regnum; /* Register number */
1997 int scale; /* Scale factor: 1,2,4,8, or 16. Later converted
1998 * to internal format (0,1,2,3,4 respectively).
2000 int mode; /* MEMB mode bits */
2001 int *intP; /* Pointer to register number */
2003 /* The following table contains the default scale factors for each
2004 * type of memory instruction. It is accessed using (optype-MEM1)
2005 * as an index -- thus it assumes the 'optype' constants are assigned
2006 * consecutive values, in the order they appear in this table
2008 static int def_scale[] =
2014 -1, /* MEM12 -- no valid default */
2019 iprel_flag = mode = 0;
2021 /* Any index present? */
2022 indexP = get_ispec (argP);
2025 p = strchr (indexP, '*');
2028 /* No explicit scale -- use default for this
2031 scale = def_scale[optype - MEM1];
2035 *p++ = '\0'; /* Eliminate '*' */
2037 /* Now indexP->a '\0'-terminated register name,
2038 * and p->a scale factor.
2041 if (!strcmp (p, "16"))
2045 else if (strchr ("1248", *p) && (p[1] == '\0'))
2055 regnum = get_regnum (indexP); /* Get index reg. # */
2056 if (!IS_RG_REG (regnum))
2058 as_bad ("invalid index register");
2062 /* Convert scale to its binary encoding */
2081 as_bad ("invalid scale factor");
2085 memP->opcode |= scale | regnum; /* Set index bits in opcode */
2086 mode |= I_BIT; /* Found a valid index spec */
2089 /* Any abase (Register Indirect) specification present? */
2090 if ((p = strrchr (argP, '(')) != NULL)
2092 /* "(" is there -- does it start a legal abase spec?
2093 * (If not it could be part of a displacement expression.)
2095 intP = (int *) hash_find (areg_hash, p);
2098 /* Got an abase here */
2100 *p = '\0'; /* discard register spec */
2101 if (regnum == IPREL)
2103 /* We have to specialcase ip-rel mode */
2108 memP->opcode |= regnum << 14;
2114 /* Any expression present? */
2121 /* Special-case ip-relative addressing */
2130 memP->opcode |= 5 << 10; /* IP-relative mode */
2136 /* Handle all other modes */
2140 /* Go with MEMA instruction format for now (grow to MEMB later
2141 * if 12 bits is not enough for the displacement).
2142 * MEMA format has a single mode bit: set it to indicate
2143 * that abase is present.
2145 memP->opcode |= MEMA_ABASE;
2150 /* Go with MEMA instruction format for now (grow to MEMB later
2151 * if 12 bits is not enough for the displacement).
2157 /* For some reason, the bit string for this mode is not
2158 * consistent: it should be 0 (exclusive of the MEMB bit),
2159 * so we set it "by hand" here.
2161 memP->opcode |= MEMB_BIT;
2165 /* set MEMB bit in mode, and OR in mode bits */
2166 memP->opcode |= mode | MEMB_BIT;
2170 /* Treat missing displacement as displacement of 0 */
2172 /***********************
2173 * Fall into next case *
2174 ********************** */
2175 case D_BIT | A_BIT | I_BIT:
2177 /* set MEMB bit in mode, and OR in mode bits */
2178 memP->opcode |= mode | MEMB_BIT;
2188 /*****************************************************************************
2189 * parse_po: parse machine-dependent pseudo-op
2191 * This is a top-level routine for machine-dependent pseudo-ops. It slurps
2192 * up the rest of the input line, breaks out the individual arguments,
2193 * and dispatches them to the correct handler.
2194 **************************************************************************** */
2198 int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
2200 char *args[4]; /* Pointers operands, with no embedded whitespace.
2202 * arg[1-3]->operands
2204 int n_ops; /* Number of operands */
2205 char *p; /* Pointer to beginning of unparsed argument string */
2206 char eol; /* Character that indicated end of line */
2208 extern char is_end_of_line[];
2210 /* Advance input pointer to end of line. */
2211 p = input_line_pointer;
2212 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2214 input_line_pointer++;
2216 eol = *input_line_pointer; /* Save end-of-line char */
2217 *input_line_pointer = '\0'; /* Terminate argument list */
2219 /* Parse out operands */
2220 n_ops = get_args (p, args);
2226 /* Dispatch to correct handler */
2230 s_sysproc (n_ops, args);
2233 s_leafproc (n_ops, args);
2240 /* Restore eol, so line numbers get updated correctly. Base assembler
2241 * assumes we leave input pointer pointing at char following the eol.
2243 *input_line_pointer++ = eol;
2246 /*****************************************************************************
2247 * parse_regop: parse a register operand.
2249 * In case of illegal operand, issue a message and return some valid
2250 * information so instruction processing can continue.
2251 **************************************************************************** */
2254 parse_regop (regopP, optext, opdesc)
2255 struct regop *regopP; /* Where to put description of register operand */
2256 char *optext; /* Text of operand */
2257 char opdesc; /* Descriptor byte: what's legal for this operand */
2259 int n; /* Register number */
2260 expressionS e; /* Parsed expression */
2262 /* See if operand is a register */
2263 n = get_regnum (optext);
2268 /* global or local register */
2269 if (!REG_ALIGN (opdesc, n))
2271 as_bad ("unaligned register");
2275 regopP->special = 0;
2278 else if (IS_FP_REG (n) && FP_OK (opdesc))
2280 /* Floating point register, and it's allowed */
2281 regopP->n = n - FP0;
2283 regopP->special = 0;
2286 else if (IS_SF_REG (n) && SFR_OK (opdesc))
2288 /* Special-function register, and it's allowed */
2289 regopP->n = n - SF0;
2291 regopP->special = 1;
2292 if (!targ_has_sfr (regopP->n))
2294 as_bad ("no such sfr in this architecture");
2299 else if (LIT_OK (opdesc))
2302 * How about a literal?
2305 regopP->special = 0;
2307 { /* floating point literal acceptable */
2308 /* Skip over 0f, 0d, or 0e prefix */
2309 if ((optext[0] == '0')
2310 && (optext[1] >= 'd')
2311 && (optext[1] <= 'f'))
2316 if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
2321 if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
2329 { /* fixed point literal acceptable */
2330 parse_expr (optext, &e);
2331 if (e.X_op != O_constant
2332 || (offs (e) < 0) || (offs (e) > 31))
2334 as_bad ("illegal literal");
2337 regopP->n = offs (e);
2342 /* Nothing worked */
2344 regopP->mode = 0; /* Register r0 is always a good one */
2346 regopP->special = 0;
2347 } /* parse_regop() */
2349 /*****************************************************************************
2350 * reg_fmt: generate a REG-format instruction
2352 **************************************************************************** */
2355 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2356 struct i960_opcode *oP; /* Pointer to description of instruction */
2358 long instr; /* Binary to be output */
2359 struct regop regop; /* Description of register operand */
2360 int n_ops; /* Number of operands */
2364 n_ops = oP->num_ops;
2368 parse_regop (®op, args[1], oP->operand[0]);
2370 if ((n_ops == 1) && !(instr & M3))
2372 /* 1-operand instruction in which the dst field should
2373 * be used (instead of src1).
2378 regop.mode = regop.special;
2385 /* regop.n goes in bit 0, needs no shifting */
2387 regop.special <<= 5;
2389 instr |= regop.n | regop.mode | regop.special;
2394 parse_regop (®op, args[2], oP->operand[1]);
2396 if ((n_ops == 2) && !(instr & M3))
2398 /* 2-operand instruction in which the dst field should
2399 * be used instead of src2).
2404 regop.mode = regop.special;
2413 regop.special <<= 6;
2415 instr |= regop.n | regop.mode | regop.special;
2419 parse_regop (®op, args[3], oP->operand[2]);
2422 regop.mode = regop.special;
2424 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2430 /*****************************************************************************
2432 * Replace cobr instruction in a code fragment with equivalent branch and
2433 * compare instructions, so it can reach beyond a 13-bit displacement.
2434 * Set up an address fix/relocation for the new branch instruction.
2436 **************************************************************************** */
2438 /* This "conditional jump" table maps cobr instructions into equivalent
2439 * compare and branch opcodes.
2449 { /* COBR OPCODE: */
2450 { CHKBIT, BNO }, /* 0x30 - bbc */
2451 { CMPO, BG }, /* 0x31 - cmpobg */
2452 { CMPO, BE }, /* 0x32 - cmpobe */
2453 { CMPO, BGE }, /* 0x33 - cmpobge */
2454 { CMPO, BL }, /* 0x34 - cmpobl */
2455 { CMPO, BNE }, /* 0x35 - cmpobne */
2456 { CMPO, BLE }, /* 0x36 - cmpoble */
2457 { CHKBIT, BO }, /* 0x37 - bbs */
2458 { CMPI, BNO }, /* 0x38 - cmpibno */
2459 { CMPI, BG }, /* 0x39 - cmpibg */
2460 { CMPI, BE }, /* 0x3a - cmpibe */
2461 { CMPI, BGE }, /* 0x3b - cmpibge */
2462 { CMPI, BL }, /* 0x3c - cmpibl */
2463 { CMPI, BNE }, /* 0x3d - cmpibne */
2464 { CMPI, BLE }, /* 0x3e - cmpible */
2465 { CMPI, BO }, /* 0x3f - cmpibo */
2471 register fragS *fragP; /* fragP->fr_opcode is assumed to point to
2472 * the cobr instruction, which comes at the
2473 * end of the code fragment.
2476 int opcode, src1, src2, m1, s2;
2477 /* Bit fields from cobr instruction */
2478 long bp_bits; /* Branch prediction bits from cobr instruction */
2479 long instr; /* A single i960 instruction */
2480 char *iP; /*->instruction to be replaced */
2481 fixS *fixP; /* Relocation that can be done at assembly time */
2483 /* PICK UP & PARSE COBR INSTRUCTION */
2484 iP = fragP->fr_opcode;
2485 instr = md_chars_to_number (iP, 4);
2486 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2487 src1 = (instr >> 19) & 0x1f;
2488 m1 = (instr >> 13) & 1;
2490 src2 = (instr >> 14) & 0x1f;
2491 bp_bits = instr & BP_MASK;
2493 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2494 instr = coj[opcode].compare
2495 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2496 md_number_to_chars (iP, instr, 4);
2498 /* OUTPUT BRANCH INSTRUCTION */
2499 md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
2501 /* SET UP ADDRESS FIXUP/RELOCATION */
2502 fixP = fix_new (fragP,
2503 iP + 4 - fragP->fr_literal,
2510 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */
2517 /*****************************************************************************
2518 * reloc_callj: Relocate a 'callj' instruction
2520 * This is a "non-(GNU)-standard" machine-dependent hook. The base
2521 * assembler calls it when it decides it can relocate an address at
2522 * assembly time instead of emitting a relocation directive.
2524 * Check to see if the relocation involves a 'callj' instruction to a:
2525 * sysproc: Replace the default 'call' instruction with a 'calls'
2526 * leafproc: Replace the default 'call' instruction with a 'bal'.
2527 * other proc: Do nothing.
2529 * See b.out.h for details on the 'n_other' field in a symbol structure.
2532 * Assumes the caller has already figured out, in the case of a leafproc,
2533 * to use the 'bal' entry point, and has substituted that symbol into the
2534 * passed fixup structure.
2536 **************************************************************************** */
2539 fixS *fixP; /* Relocation that can be done at assembly time */
2541 char *where; /*->the binary for the instruction being relocated */
2543 if (!fixP->fx_callj)
2546 } /* This wasn't a callj instruction in the first place */
2548 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2550 if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2552 /* Symbol is a .sysproc: replace 'call' with 'calls'.
2553 * System procedure number is (other-1).
2555 md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2557 /* Nothing else needs to be done for this instruction.
2558 * Make sure 'md_number_to_field()' will perform a no-op.
2560 fixP->fx_bit_fixP = (bit_fixS *) 1;
2563 else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2565 /* Should not happen: see block comment above */
2566 as_fatal ("Trying to 'bal' to %s", S_GET_NAME (fixP->fx_addsy));
2569 else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2571 /* Replace 'call' with 'bal'; both instructions have
2572 * the same format, so calling code should complete
2573 * relocation as if nothing happened here.
2575 md_number_to_chars (where, BAL, 4);
2577 else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2579 as_bad ("Looks like a proc, but can't tell what kind.\n");
2580 } /* switch on proc type */
2582 /* else Symbol is neither a sysproc nor a leafproc */
2585 } /* reloc_callj() */
2588 /*****************************************************************************
2589 * s_leafproc: process .leafproc pseudo-op
2591 * .leafproc takes two arguments, the second one is optional:
2592 * arg[1]: name of 'call' entry point to leaf procedure
2593 * arg[2]: name of 'bal' entry point to leaf procedure
2595 * If the two arguments are identical, or if the second one is missing,
2596 * the first argument is taken to be the 'bal' entry point.
2598 * If there are 2 distinct arguments, we must make sure that the 'bal'
2599 * entry point immediately follows the 'call' entry point in the linked
2602 **************************************************************************** */
2604 s_leafproc (n_ops, args)
2605 int n_ops; /* Number of operands */
2606 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2608 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */
2609 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */
2611 if ((n_ops != 1) && (n_ops != 2))
2613 as_bad ("should have 1 or 2 operands");
2615 } /* Check number of arguments */
2617 /* Find or create symbol for 'call' entry point. */
2618 callP = symbol_find_or_make (args[1]);
2620 if (TC_S_IS_CALLNAME (callP))
2622 as_warn ("Redefining leafproc %s", S_GET_NAME (callP));
2625 /* If that was the only argument, use it as the 'bal' entry point.
2626 * Otherwise, mark it as the 'call' entry point and find or create
2627 * another symbol for the 'bal' entry point.
2629 if ((n_ops == 1) || !strcmp (args[1], args[2]))
2631 TC_S_FORCE_TO_BALNAME (callP);
2636 TC_S_FORCE_TO_CALLNAME (callP);
2638 balP = symbol_find_or_make (args[2]);
2639 if (TC_S_IS_CALLNAME (balP))
2641 as_warn ("Redefining leafproc %s", S_GET_NAME (balP));
2643 TC_S_FORCE_TO_BALNAME (balP);
2645 tc_set_bal_of_call (callP, balP);
2646 } /* if only one arg, or the args are the same */
2649 } /* s_leafproc() */
2653 * s_sysproc: process .sysproc pseudo-op
2655 * .sysproc takes two arguments:
2656 * arg[1]: name of entry point to system procedure
2657 * arg[2]: 'entry_num' (index) of system procedure in the range
2660 * For [ab].out, we store the 'entrynum' in the 'n_other' field of
2661 * the symbol. Since that entry is normally 0, we bias 'entrynum'
2662 * by adding 1 to it. It must be unbiased before it is used.
2665 s_sysproc (n_ops, args)
2666 int n_ops; /* Number of operands */
2667 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2674 as_bad ("should have two operands");
2676 } /* bad arg count */
2678 /* Parse "entry_num" argument and check it for validity. */
2679 parse_expr (args[2], &exp);
2680 if (exp.X_op != O_constant
2682 || (offs (exp) > 31))
2684 as_bad ("'entry_num' must be absolute number in [0,31]");
2688 /* Find/make symbol and stick entry number (biased by +1) into it */
2689 symP = symbol_find_or_make (args[1]);
2691 if (TC_S_IS_SYSPROC (symP))
2693 as_warn ("Redefining entrynum for sysproc %s", S_GET_NAME (symP));
2696 TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */
2697 TC_S_FORCE_TO_SYSPROC (symP);
2703 /*****************************************************************************
2705 * Determine if a "shlo" instruction can be used to implement a "ldconst".
2706 * This means that some number X < 32 can be shifted left to produce the
2707 * constant of interest.
2709 * Return the shift count, or 0 if we can't do it.
2710 * Caller calculates X by shifting original constant right 'shift' places.
2712 **************************************************************************** */
2716 int n; /* The constant of interest */
2718 int shift; /* The shift count */
2722 /* Can't do it for negative numbers */
2726 /* Shift 'n' right until a 1 is about to be lost */
2727 for (shift = 0; (n & 1) == 0; shift++)
2740 /*****************************************************************************
2741 * syntax: issue syntax error
2743 **************************************************************************** */
2747 as_bad ("syntax error");
2751 /*****************************************************************************
2753 * Return TRUE iff the target architecture supports the specified
2754 * special-function register (sfr).
2756 **************************************************************************** */
2760 int n; /* Number (0-31) of sfr */
2762 switch (architecture)
2770 return ((0 <= n) && (n <= 2));
2775 /*****************************************************************************
2777 * Return TRUE iff the target architecture supports the indicated
2778 * class of instructions.
2780 **************************************************************************** */
2783 targ_has_iclass (ic)
2784 int ic; /* Instruction class; one of:
2785 * I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM
2788 iclasses_seen |= ic;
2789 switch (architecture)
2792 return ic & (I_BASE | I_KX);
2794 return ic & (I_BASE | I_KX | I_FP | I_DEC);
2796 return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2798 return ic & (I_BASE | I_CX | I_CASIM);
2800 if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
2801 && (iclasses_seen & I_CX))
2803 as_warn ("architecture of opcode conflicts with that of earlier instruction(s)");
2804 iclasses_seen &= ~ic;
2811 /* Parse an operand that is machine-specific.
2812 We just return without modifying the expression if we have nothing
2817 md_operand (expressionP)
2818 expressionS *expressionP;
2822 /* We have no need to default values of symbols. */
2826 md_undefined_symbol (name)
2830 } /* md_undefined_symbol() */
2832 /* Exactly what point is a PC-relative offset relative TO?
2833 On the i960, they're relative to the address of the instruction,
2834 which we have set up as the address of the fixup too. */
2836 md_pcrel_from (fixP)
2839 return fixP->fx_where + fixP->fx_frag->fr_address;
2843 md_apply_fix (fixP, val)
2847 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2849 if (!fixP->fx_bit_fixP)
2852 switch (fixP->fx_im_disp)
2855 fixP->fx_addnumber = val;
2856 md_number_to_imm (place, val, fixP->fx_size, fixP);
2859 md_number_to_disp (place,
2861 ? val + fixP->fx_pcrel_adjust
2865 case 2: /* fix requested for .long .word etc */
2866 md_number_to_chars (place, val, fixP->fx_size);
2869 as_fatal ("Internal error in md_apply_fix() in file \"%s\"",
2875 md_number_to_field (place, val, fixP->fx_bit_fixP);
2879 } /* md_apply_fix() */
2881 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2883 tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
2886 relax_addressT segment_address_in_file;
2888 static unsigned char nbytes_r_length[] =
2890 struct relocation_info ri;
2893 /* JF this is for paranoia */
2894 memset ((char *) &ri, '\0', sizeof (ri));
2895 symbolP = fixP->fx_addsy;
2896 know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2897 ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2898 /* These two 'cuz of NS32K */
2899 ri.r_callj = fixP->fx_callj;
2900 if (fixP->fx_bit_fixP)
2906 ri.r_length = nbytes_r_length[fixP->fx_size];
2908 ri.r_pcrel = fixP->fx_pcrel;
2909 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2911 if (fixP->fx_r_type != NO_RELOC)
2913 switch (fixP->fx_r_type)
2918 ri.r_length = fixP->fx_size - 1;
2932 else if (linkrelax || !S_IS_DEFINED (symbolP))
2935 ri.r_index = symbolP->sy_number;
2940 ri.r_index = S_GET_TYPE (symbolP);
2943 /* Output the relocation information in machine-dependent form. */
2944 md_ri_to_chars (where, &ri);
2947 } /* tc_bout_fix_to_chars() */
2949 #endif /* OBJ_AOUT or OBJ_BOUT */
2951 /* Align an address by rounding it up to the specified boundary.
2954 md_section_align (seg, addr)
2956 valueT addr; /* Address to be rounded up */
2958 return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
2959 } /* md_section_align() */
2963 tc_headers_hook (headers)
2964 object_headers *headers;
2966 /* FIXME: remove this line *//* unsigned short arch_flag = 0; */
2968 if (iclasses_seen == I_BASE)
2970 headers->filehdr.f_flags |= F_I960CORE;
2972 else if (iclasses_seen & I_CX)
2974 headers->filehdr.f_flags |= F_I960CA;
2976 else if (iclasses_seen & I_MIL)
2978 headers->filehdr.f_flags |= F_I960MC;
2980 else if (iclasses_seen & (I_DEC | I_FP))
2982 headers->filehdr.f_flags |= F_I960KB;
2986 headers->filehdr.f_flags |= F_I960KA;
2987 } /* set arch flag */
2991 headers->filehdr.f_magic = I960RWMAGIC;
2992 headers->aouthdr.magic = OMAGIC;
2996 headers->filehdr.f_magic = I960ROMAGIC;
2997 headers->aouthdr.magic = NMAGIC;
2998 } /* set magic numbers */
3001 } /* tc_headers_hook() */
3003 #endif /* OBJ_COFF */
3006 * Things going on here:
3008 * For bout, We need to assure a couple of simplifying
3009 * assumptions about leafprocs for the linker: the leafproc
3010 * entry symbols will be defined in the same assembly in
3011 * which they're declared with the '.leafproc' directive;
3012 * and if a leafproc has both 'call' and 'bal' entry points
3013 * they are both global or both local.
3015 * For coff, the call symbol has a second aux entry that
3016 * contains the bal entry point. The bal symbol becomes a
3019 * For coff representation, the call symbol has a second aux entry that
3020 * contains the bal entry point. The bal symbol becomes a label.
3025 tc_crawl_symbol_chain (headers)
3026 object_headers *headers;
3030 for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
3033 if (TC_S_IS_SYSPROC (symbolP))
3035 /* second aux entry already contains the sysproc number */
3036 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3037 S_SET_STORAGE_CLASS (symbolP, C_SCALL);
3038 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3040 } /* rewrite sysproc */
3041 #endif /* OBJ_COFF */
3043 if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
3046 } /* Not a leafproc symbol */
3048 if (!S_IS_DEFINED (symbolP))
3050 as_bad ("leafproc symbol '%s' undefined", S_GET_NAME (symbolP));
3051 } /* undefined leaf */
3053 if (TC_S_IS_CALLNAME (symbolP))
3055 symbolS *balP = tc_get_bal_of_call (symbolP);
3056 if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
3058 S_SET_EXTERNAL (symbolP);
3059 S_SET_EXTERNAL (balP);
3060 as_warn ("Warning: making leafproc entries %s and %s both global\n",
3061 S_GET_NAME (symbolP), S_GET_NAME (balP));
3062 } /* externality mismatch */
3064 } /* walk the symbol chain */
3067 } /* tc_crawl_symbol_chain() */
3070 * For aout or bout, the bal immediately follows the call.
3072 * For coff, we cheat and store a pointer to the bal symbol
3073 * in the second aux entry of the call.
3085 tc_set_bal_of_call (callP, balP)
3089 know (TC_S_IS_CALLNAME (callP));
3090 know (TC_S_IS_BALNAME (balP));
3094 callP->sy_symbol.ost_auxent[1].x_bal.x_balntry = (int) balP;
3095 S_SET_NUMBER_AUXILIARY (callP, 2);
3097 #else /* ! OBJ_COFF */
3100 /* If the 'bal' entry doesn't immediately follow the 'call'
3101 * symbol, unlink it from the symbol list and re-insert it.
3103 if (symbol_next (callP) != balP)
3105 symbol_remove (balP, &symbol_rootP, &symbol_lastP);
3106 symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
3107 } /* if not in order */
3109 #else /* ! OBJ_ABOUT */
3110 (as yet unwritten.);
3111 #endif /* ! OBJ_ABOUT */
3112 #endif /* ! OBJ_COFF */
3115 } /* tc_set_bal_of_call() */
3118 _tc_get_bal_of_call (callP)
3123 know (TC_S_IS_CALLNAME (callP));
3126 retval = (symbolS *) (callP->sy_symbol.ost_auxent[1].x_bal.x_balntry);
3129 retval = symbol_next (callP);
3131 (as yet unwritten.);
3132 #endif /* ! OBJ_ABOUT */
3133 #endif /* ! OBJ_COFF */
3135 know (TC_S_IS_BALNAME (retval));
3136 return ((char *) retval);
3137 } /* _tc_get_bal_of_call() */
3140 tc_coff_symbol_emit_hook (symbolP)
3143 if (TC_S_IS_CALLNAME (symbolP))
3146 symbolS *balP = tc_get_bal_of_call (symbolP);
3148 /* second aux entry contains the bal entry point */
3149 /* S_SET_NUMBER_AUXILIARY(symbolP, 2); */
3150 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
3151 S_SET_STORAGE_CLASS (symbolP, (!SF_GET_LOCAL (symbolP) ? C_LEAFEXT : C_LEAFSTAT));
3152 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3153 /* fix up the bal symbol */
3154 S_SET_STORAGE_CLASS (balP, C_LABEL);
3155 #endif /* OBJ_COFF */
3156 } /* only on calls */
3159 } /* tc_coff_symbol_emit_hook() */
3162 i960_handle_align (fragp)
3170 /* The text section "ends" with another alignment reloc, to which we
3171 aren't adding padding. */
3172 if (fragp->fr_next == text_last_frag
3173 || fragp->fr_next == data_last_frag)
3178 /* alignment directive */
3179 fixp = fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
3180 (int) fragp->fr_type);
3183 /* end of tc-i960.c */