1 /* tc-i960.c - All the i80960-specific stuff
2 Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 1998
3 Free Software Foundation, Inc.
5 This file is part of GAS.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* See comment on md_parse_option for 80960-specific invocation options. */
24 /* There are 4 different lengths of (potentially) symbol-based displacements
25 in the 80960 instruction set, each of which could require address fix-ups
26 and (in the case of external symbols) emission of relocation directives:
29 This is a standard length for the base assembler and requires no
33 This is a non-standard length, but the base assembler has a
34 hook for bit field address fixups: the fixS structure can
35 point to a descriptor of the field, in which case our
36 md_number_to_field() routine gets called to process it.
38 I made the hook a little cleaner by having fix_new() (in the base
39 assembler) return a pointer to the fixS in question. And I made it a
40 little simpler by storing the field size (in this case 13) instead of
41 of a pointer to another structure: 80960 displacements are ALWAYS
42 stored in the low-order bits of a 4-byte word.
44 Since the target of a COBR cannot be external, no relocation
45 directives for this size displacement have to be generated.
46 But the base assembler had to be modified to issue error
47 messages if the symbol did turn out to be external.
50 Fixups are handled as for the 13-bit case (except that 24 is stored
53 The relocation directive generated is the same as that for the 32-bit
54 displacement, except that it's PC-relative (the 32-bit displacement
55 never is). The i80960 version of the linker needs a mod to
56 distinguish and handle the 24-bit case.
59 MEMA formats are always promoted to MEMB (32-bit) if the displacement
60 is based on a symbol, because it could be relocated at link time.
61 The only time we use the 12-bit format is if an absolute value of
62 less than 4096 is specified, in which case we need neither a fixup nor
63 a relocation directive. */
72 #include "opcode/i960.h"
74 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
76 #define TC_S_IS_SYSPROC(s) ((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
77 #define TC_S_IS_BALNAME(s) (S_GET_OTHER(s) == N_BALNAME)
78 #define TC_S_IS_CALLNAME(s) (S_GET_OTHER(s) == N_CALLNAME)
79 #define TC_S_IS_BADPROC(s) ((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
81 #define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER((s), (p)+1))
82 #define TC_S_GET_SYSPROC(s) (S_GET_OTHER(s)-1)
84 #define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER((s), N_BALNAME))
85 #define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER((s), N_CALLNAME))
86 #define TC_S_FORCE_TO_SYSPROC(s) {;}
88 #else /* ! OBJ_A/BOUT */
91 #define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS(s) == C_SCALL)
92 #define TC_S_IS_BALNAME(s) (SF_GET_BALNAME(s))
93 #define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME(s))
94 #define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
96 #define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
97 #define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
99 #define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME(s))
100 #define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME(s))
101 #define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS((s), C_SCALL))
103 #else /* ! OBJ_COFF */
105 #endif /* ! OBJ_COFF */
106 #endif /* ! OBJ_A/BOUT */
108 extern char *input_line_pointer;
110 #if !defined (BFD_ASSEMBLER) && !defined (BFD)
112 const int md_reloc_size = sizeof (struct reloc);
114 const int md_reloc_size = sizeof (struct relocation_info);
115 #endif /* OBJ_COFF */
118 /* Local i80960 routines. */
120 static void brcnt_emit (); /* Emit branch-prediction instrumentation code */
121 static char *brlab_next (); /* Return next branch local label */
122 void brtab_emit (); /* Emit br-predict instrumentation table */
123 static void cobr_fmt (); /* Generate COBR instruction */
124 static void ctrl_fmt (); /* Generate CTRL instruction */
125 static char *emit (); /* Emit (internally) binary */
126 static int get_args (); /* Break arguments out of comma-separated list */
127 static void get_cdisp (); /* Handle COBR or CTRL displacement */
128 static char *get_ispec (); /* Find index specification string */
129 static int get_regnum (); /* Translate text to register number */
130 static int i_scan (); /* Lexical scan of instruction source */
131 static void mem_fmt (); /* Generate MEMA or MEMB instruction */
132 static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */
133 static void parse_expr (); /* Parse an expression */
134 static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */
135 static void parse_memop (); /* Parse a memory operand */
136 static void parse_po (); /* Parse machine-dependent pseudo-op */
137 static void parse_regop (); /* Parse a register operand */
138 static void reg_fmt (); /* Generate a REG format instruction */
139 void reloc_callj (); /* Relocate a 'callj' instruction */
140 static void relax_cobr (); /* "De-optimize" cobr into compare/branch */
141 static void s_leafproc (); /* Process '.leafproc' pseudo-op */
142 static void s_sysproc (); /* Process '.sysproc' pseudo-op */
143 static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */
144 static void syntax (); /* Give syntax error */
145 static int targ_has_sfr (); /* Target chip supports spec-func register? */
146 static int targ_has_iclass (); /* Target chip supports instruction set? */
148 /* See md_parse_option() for meanings of these options */
149 static char norelax; /* True if -norelax switch seen */
150 static char instrument_branches; /* True if -b switch seen */
152 /* Characters that always start a comment.
153 If the pre-processor is disabled, these aren't very useful.
155 const char comment_chars[] = "#";
157 /* Characters that only start a comment at the beginning of
158 a line. If the line seems to have the form '# 123 filename'
159 .line and .file directives will appear in the pre-processed output.
161 Note that input_file.c hand checks for '#' at the beginning of the
162 first line of the input file. This is because the compiler outputs
163 #NO_APP at the beginning of its output.
166 /* Also note that comments started like this one will always work. */
168 const char line_comment_chars[1];
170 const char line_separator_chars[1];
172 /* Chars that can be used to separate mant from exp in floating point nums */
173 const char EXP_CHARS[] = "eE";
175 /* Chars that mean this number is a floating point constant,
176 as in 0f12.456 or 0d1.2345e12
178 const char FLT_CHARS[] = "fFdDtT";
181 /* Table used by base assembler to relax addresses based on varying length
182 instructions. The fields are:
183 1) most positive reach of this state,
184 2) most negative reach of this state,
185 3) how many bytes this mode will add to the size of the current frag
186 4) which index into the table to try if we can't fit into this one.
188 For i80960, the only application is the (de-)optimization of cobr
189 instructions into separate compare and branch instructions when a 13-bit
190 displacement won't hack it.
192 const relax_typeS md_relax_table[] =
194 {0, 0, 0, 0}, /* State 0 => no more relaxation possible */
195 {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */
196 {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */
199 static void s_endian PARAMS ((int));
201 /* These are the machine dependent pseudo-ops.
203 This table describes all the machine specific pseudo-ops the assembler
204 has to support. The fields are:
205 pseudo-op name without dot
206 function to call to execute this pseudo-op
207 integer arg to pass to the function
212 const pseudo_typeS md_pseudo_table[] =
215 {"endian", s_endian, 0},
216 {"extended", float_cons, 't'},
217 {"leafproc", parse_po, S_LEAFPROC},
218 {"sysproc", parse_po, S_SYSPROC},
226 /* Macros to extract info from an 'expressionS' structure 'e' */
227 #define adds(e) e.X_add_symbol
228 #define offs(e) e.X_add_number
231 /* Branch-prediction bits for CTRL/COBR format opcodes */
232 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
233 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
234 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
237 /* Some instruction opcodes that we need explicitly */
238 #define BE 0x12000000
239 #define BG 0x11000000
240 #define BGE 0x13000000
241 #define BL 0x14000000
242 #define BLE 0x16000000
243 #define BNE 0x15000000
244 #define BNO 0x10000000
245 #define BO 0x17000000
246 #define CHKBIT 0x5a002700
247 #define CMPI 0x5a002080
248 #define CMPO 0x5a002000
251 #define BAL 0x0b000000
252 #define CALL 0x09000000
253 #define CALLS 0x66003800
254 #define RET 0x0a000000
257 /* These masks are used to build up a set of MEMB mode bits. */
260 #define MEMB_BIT 0x1000
264 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
266 #define MEMA_ABASE 0x2000
268 /* Info from which a MEMA or MEMB format instruction can be generated */
271 /* (First) 32 bits of instruction */
273 /* 0-(none), 12- or, 32-bit displacement needed */
275 /* The expression in the source instruction from which the
276 displacement should be determined. */
283 /* The two pieces of info we need to generate a register operand */
286 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
287 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
288 int n; /* Register number or literal value */
292 /* Number and assembler mnemonic for all registers that can appear in
334 /* Numbers for special-function registers are for assembler internal
335 use only: they are scaled back to range [0-31] for binary output. */
371 /* Numbers for floating point registers are for assembler internal
372 use only: they are scaled back to [0-3] for binary output. */
380 { NULL, 0 }, /* END OF LIST */
383 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
384 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
385 #define IS_FP_REG(n) ((n) >= FP0)
387 /* Number and assembler mnemonic for all registers that can appear as
388 'abase' (indirect addressing) registers. */
430 /* For assembler internal use only: this number never appears in binary
434 { NULL, 0 }, /* END OF LIST */
439 static struct hash_control *op_hash; /* Opcode mnemonics */
440 static struct hash_control *reg_hash; /* Register name hash table */
441 static struct hash_control *areg_hash; /* Abase register hash table */
444 /* Architecture for which we are assembling */
445 #define ARCH_ANY 0 /* Default: no architecture checking done */
452 int architecture = ARCH_ANY; /* Architecture requested on invocation line */
453 int iclasses_seen; /* OR of instruction classes (I_* constants)
454 * for which we've actually assembled
459 /* BRANCH-PREDICTION INSTRUMENTATION
461 The following supports generation of branch-prediction instrumentation
462 (turned on by -b switch). The instrumentation collects counts
463 of branches taken/not-taken for later input to a utility that will
464 set the branch prediction bits of the instructions in accordance with
465 the behavior observed. (Note that the KX series does not have
468 The instrumentation consists of:
470 (1) before and after each conditional branch, a call to an external
471 routine that increments and steps over an inline counter. The
472 counter itself, initialized to 0, immediately follows the call
473 instruction. For each branch, the counter following the branch
474 is the number of times the branch was not taken, and the difference
475 between the counters is the number of times it was taken. An
476 example of an instrumented conditional branch:
484 (2) a table of pointers to the instrumented branches, so that an
485 external postprocessing routine can locate all of the counters.
486 the table begins with a 2-word header: a pointer to the next in
487 a linked list of such tables (initialized to 0); and a count
488 of the number of entries in the table (exclusive of the header.
490 Note that input source code is expected to already contain calls
491 an external routine that will link the branch local table into a
495 /* Number of branches instrumented so far. Also used to generate
496 unique local labels for each instrumented branch. */
499 #define BR_LABEL_BASE "LBRANCH"
500 /* Basename of local labels on instrumented branches, to avoid
501 conflict with compiler- generated local labels. */
503 #define BR_CNT_FUNC "__inc_branch"
504 /* Name of the external routine that will increment (and step over) an
507 #define BR_TAB_NAME "__BRANCH_TABLE__"
508 /* Name of the table of pointers to branches. A local (i.e.,
509 non-external) symbol. */
511 /*****************************************************************************
512 md_begin: One-time initialization.
516 *************************************************************************** */
520 int i; /* Loop counter */
521 const struct i960_opcode *oP; /* Pointer into opcode table */
522 const char *retval; /* Value returned by hash functions */
524 op_hash = hash_new ();
525 reg_hash = hash_new ();
526 areg_hash = hash_new ();
528 /* For some reason, the base assembler uses an empty string for "no
529 error message", instead of a NULL pointer. */
532 for (oP = i960_opcodes; oP->name && !retval; oP++)
533 retval = hash_insert (op_hash, oP->name, (PTR) oP);
535 for (i = 0; regnames[i].reg_name && !retval; i++)
536 retval = hash_insert (reg_hash, regnames[i].reg_name,
537 (char *) ®names[i].reg_num);
539 for (i = 0; aregs[i].areg_name && !retval; i++)
540 retval = hash_insert (areg_hash, aregs[i].areg_name,
541 (char *) &aregs[i].areg_num);
544 as_fatal (_("Hashing returned \"%s\"."), retval);
547 /*****************************************************************************
548 md_assemble: Assemble an instruction
550 Assumptions about the passed-in text:
551 - all comments, labels removed
552 - text is an instruction
553 - all white space compressed to single blanks
554 - all character constants have been replaced with decimal
556 *************************************************************************** */
559 char *textP; /* Source text of instruction */
561 /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
562 mnemonic arg[1-3]->operands, with char constants replaced by
566 int n_ops; /* Number of instruction operands */
567 /* Pointer to instruction description */
568 struct i960_opcode *oP;
569 /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
572 /* Setting of branch-prediction bit(s) to be OR'd into instruction
573 opcode of CTRL/COBR format instructions. */
576 int n; /* Offset of last character in opcode mnemonic */
578 const char *bp_error_msg = _("branch prediction invalid on this opcode");
581 /* Parse instruction into opcode and operands */
582 memset (args, '\0', sizeof (args));
583 n_ops = i_scan (textP, args);
586 return; /* Error message already issued */
589 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
590 if (!strcmp (args[0], "ldconst"))
592 n_ops = parse_ldconst (args);
601 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
602 n = strlen (args[0]) - 1;
605 if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
607 /* We could check here to see if the target architecture
608 supports branch prediction, but why bother? The bit will
609 just be ignored by processors that don't use it. */
611 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
612 args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
615 /* Look up opcode mnemonic in table and check number of operands.
616 Check that opcode is legal for the target architecture. If all
617 looks good, assemble instruction. */
618 oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
619 if (!oP || !targ_has_iclass (oP->iclass))
621 as_bad (_("invalid opcode, \"%s\"."), args[0]);
624 else if (n_ops != oP->num_ops)
626 as_bad (_("improper number of operands. expecting %d, got %d"),
635 ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
636 if (oP->format == FBRA)
638 /* Now generate a 'bno' to same arg */
639 ctrl_fmt (args[1], BNO | bp_bits, 1);
644 cobr_fmt (args, oP->opcode | bp_bits, oP);
649 as_warn (bp_error_msg);
654 if (args[0][0] == 'c' && args[0][1] == 'a')
658 as_warn (bp_error_msg);
660 mem_fmt (args, oP, 1);
670 as_warn (bp_error_msg);
672 mem_fmt (args, oP, 0);
677 as_warn (bp_error_msg);
679 /* Output opcode & set up "fixup" (relocation); flag
680 relocation as 'callj' type. */
681 know (oP->num_ops == 1);
682 get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
685 BAD_CASE (oP->format);
689 } /* md_assemble() */
691 /*****************************************************************************
692 md_number_to_chars: convert a number to target byte order
694 *************************************************************************** */
696 md_number_to_chars (buf, value, n)
701 number_to_chars_littleendian (buf, value, n);
704 /*****************************************************************************
705 md_chars_to_number: convert from target byte order to host byte order.
707 *************************************************************************** */
709 md_chars_to_number (val, n)
710 unsigned char *val; /* Value in target byte order */
711 int n; /* Number of bytes in the input */
715 for (retval = 0; n--;)
724 #define MAX_LITTLENUMS 6
725 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
727 /*****************************************************************************
728 md_atof: convert ascii to floating point
730 Turn a string at input_line_pointer into a floating point constant of type
731 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
732 emitted is returned at 'sizeP'. An error message is returned, or a pointer
733 to an empty message if OK.
735 Note we call the i386 floating point routine, rather than complicating
736 things with more files or symbolic links.
738 *************************************************************************** */
740 md_atof (type, litP, sizeP)
745 LITTLENUM_TYPE words[MAX_LITTLENUMS];
746 LITTLENUM_TYPE *wordP;
766 type = 'x'; /* That's what atof_ieee() understands */
771 return _("Bad call to md_atof()");
774 t = atof_ieee (input_line_pointer, type, words);
777 input_line_pointer = t;
780 *sizeP = prec * LNUM_SIZE;
782 /* Output the LITTLENUMs in REVERSE order in accord with i80960
783 word-order. (Dunno why atof_ieee doesn't do it in the right
784 order in the first place -- probably because it's a hack of
787 for (wordP = words + prec - 1; prec--;)
789 md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
790 litP += sizeof (LITTLENUM_TYPE);
797 /*****************************************************************************
800 *************************************************************************** */
802 md_number_to_imm (buf, val, n)
807 md_number_to_chars (buf, val, n);
811 /*****************************************************************************
814 *************************************************************************** */
816 md_number_to_disp (buf, val, n)
821 md_number_to_chars (buf, val, n);
824 /*****************************************************************************
827 Stick a value (an address fixup) into a bit field of
828 previously-generated instruction.
830 *************************************************************************** */
832 md_number_to_field (instrP, val, bfixP)
833 char *instrP; /* Pointer to instruction to be fixed */
834 long val; /* Address fixup value */
835 bit_fixS *bfixP; /* Description of bit field to be fixed up */
837 int numbits; /* Length of bit field to be fixed */
838 long instr; /* 32-bit instruction to be fixed-up */
839 long sign; /* 0 or -1, according to sign bit of 'val' */
841 /* Convert instruction back to host byte order. */
842 instr = md_chars_to_number (instrP, 4);
844 /* Surprise! -- we stored the number of bits to be modified rather
845 than a pointer to a structure. */
846 numbits = (int) bfixP;
849 /* This is a no-op, stuck here by reloc_callj() */
853 know ((numbits == 13) || (numbits == 24));
855 /* Propagate sign bit of 'val' for the given number of bits. Result
856 should be all 0 or all 1. */
857 sign = val >> ((int) numbits - 1);
858 if (((val < 0) && (sign != -1))
859 || ((val > 0) && (sign != 0)))
861 as_bad (_("Fixup of %ld too large for field width of %d"),
866 /* Put bit field into instruction and write back in target
869 val &= ~(-1 << (int) numbits); /* Clear unused sign bits */
871 md_number_to_chars (instrP, instr, 4);
873 } /* md_number_to_field() */
876 /*****************************************************************************
878 Invocation line includes a switch not recognized by the base assembler.
879 See if it's a processor-specific option. For the 960, these are:
882 Conditional branch instructions that require displacements
883 greater than 13 bits (or that have external targets) should
884 generate errors. The default is to replace each such
885 instruction with the corresponding compare (or chkbit) and
886 branch instructions. Note that the Intel "j" cobr directives
887 are ALWAYS "de-optimized" in this way when necessary,
888 regardless of the setting of this option.
891 Add code to collect information about branches taken, for
892 later optimization of branch prediction bits by a separate
893 tool. COBR and CNTL format instructions have branch
894 prediction bits (in the CX architecture); if "BR" represents
895 an instruction in one of these classes, the following rep-
896 resents the code generated by the assembler:
898 call <increment routine>
899 .word 0 # pre-counter
901 call <increment routine>
902 .word 0 # post-counter
904 A table of all such "Labels" is also generated.
907 -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
908 Select the 80960 architecture. Instructions or features not
909 supported by the selected architecture cause fatal errors.
910 The default is to generate code for any instruction or feature
911 that is supported by SOME version of the 960 (even if this
912 means mixing architectures!).
914 ****************************************************************************/
916 CONST char *md_shortopts = "A:b";
917 struct option md_longopts[] =
919 #define OPTION_LINKRELAX (OPTION_MD_BASE)
920 {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
921 {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
922 #define OPTION_NORELAX (OPTION_MD_BASE + 1)
923 {"norelax", no_argument, NULL, OPTION_NORELAX},
924 {"no-relax", no_argument, NULL, OPTION_NORELAX},
925 {NULL, no_argument, NULL, 0}
927 size_t md_longopts_size = sizeof (md_longopts);
934 static const struct tabentry arch_tab[] =
938 {"SA", ARCH_KA}, /* Synonym for KA */
939 {"SB", ARCH_KB}, /* Synonym for KB */
940 {"KC", ARCH_MC}, /* Synonym for MC */
949 md_parse_option (c, arg)
955 case OPTION_LINKRELAX:
957 flag_keep_locals = 1;
965 instrument_branches = 1;
970 const struct tabentry *tp;
973 for (tp = arch_tab; tp->flag != NULL; tp++)
974 if (!strcmp (p, tp->flag))
977 if (tp->flag == NULL)
979 as_bad (_("invalid architecture %s"), p);
983 architecture = tp->arch;
995 md_show_usage (stream)
999 fprintf (stream, _("I960 options:\n"));
1000 for (i = 0; arch_tab[i].flag; i++)
1001 fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
1002 fprintf (stream, _("\n\
1003 specify variant of 960 architecture\n\
1004 -b add code to collect statistics about branches taken\n\
1005 -link-relax preserve individual alignment directives so linker\n\
1006 can do relaxing (b.out format only)\n\
1007 -no-relax don't alter compare-and-branch instructions for\n\
1008 long displacements\n"));
1012 #ifndef BFD_ASSEMBLER
1013 /*****************************************************************************
1015 Called by base assembler after address relaxation is finished: modify
1016 variable fragments according to how much relaxation was done.
1018 If the fragment substate is still 1, a 13-bit displacement was enough
1019 to reach the symbol in question. Set up an address fixup, but otherwise
1020 leave the cobr instruction alone.
1022 If the fragment substate is 2, a 13-bit displacement was not enough.
1023 Replace the cobr with a two instructions (a compare and a branch).
1025 *************************************************************************** */
1027 md_convert_frag (headers, seg, fragP)
1028 object_headers *headers;
1032 fixS *fixP; /* Structure describing needed address fix */
1034 switch (fragP->fr_subtype)
1037 /* LEAVE SINGLE COBR INSTRUCTION */
1038 fixP = fix_new (fragP,
1039 fragP->fr_opcode - fragP->fr_literal,
1046 fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */
1049 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
1053 BAD_CASE (fragP->fr_subtype);
1058 /*****************************************************************************
1059 md_estimate_size_before_relax: How much does it look like *fragP will grow?
1061 Called by base assembler just before address relaxation.
1062 Return the amount by which the fragment will grow.
1064 Any symbol that is now undefined will not become defined; cobr's
1065 based on undefined symbols will have to be replaced with a compare
1066 instruction and a branch instruction, and the code fragment will grow
1069 *************************************************************************** */
1071 md_estimate_size_before_relax (fragP, segment_type)
1072 register fragS *fragP;
1073 register segT segment_type;
1075 /* If symbol is undefined in this segment, go to "relaxed" state
1076 (compare and branch instructions instead of cobr) right now. */
1077 if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
1083 } /* md_estimate_size_before_relax() */
1086 /*****************************************************************************
1088 This routine exists in order to overcome machine byte-order problems
1089 when dealing with bit-field entries in the relocation_info struct.
1091 But relocation info will be used on the host machine only (only
1092 executable code is actually downloaded to the i80960). Therefore,
1093 we leave it in host byte order.
1095 The above comment is no longer true. This routine now really
1096 does do the reordering (Ian Taylor 28 Aug 92).
1098 *************************************************************************** */
1100 md_ri_to_chars (where, ri)
1102 struct relocation_info *ri;
1104 md_number_to_chars (where, ri->r_address,
1105 sizeof (ri->r_address));
1106 where[4] = ri->r_index & 0x0ff;
1107 where[5] = (ri->r_index >> 8) & 0x0ff;
1108 where[6] = (ri->r_index >> 16) & 0x0ff;
1109 where[7] = ((ri->r_pcrel << 0)
1110 | (ri->r_length << 1)
1111 | (ri->r_extern << 3)
1114 | (ri->r_callj << 6));
1117 #endif /* BFD_ASSEMBLER */
1119 /* FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER */
1121 /*****************************************************************************
1122 brcnt_emit: Emit code to increment inline branch counter.
1124 See the comments above the declaration of 'br_cnt' for details on
1125 branch-prediction instrumentation.
1126 *************************************************************************** */
1130 ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */
1131 emit (0); /* Emit inline counter to be incremented */
1134 /*****************************************************************************
1135 brlab_next: generate the next branch local label
1137 See the comments above the declaration of 'br_cnt' for details on
1138 branch-prediction instrumentation.
1139 *************************************************************************** */
1143 static char buf[20];
1145 sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1149 /*****************************************************************************
1150 brtab_emit: generate the fetch-prediction branch table.
1152 See the comments above the declaration of 'br_cnt' for details on
1153 branch-prediction instrumentation.
1155 The code emitted here would be functionally equivalent to the following
1156 example assembler source.
1161 .word 0 # link to next table
1162 .word 3 # length of table
1163 .word LBRANCH0 # 1st entry in table proper
1166 **************************************************************************** */
1172 char *p; /* Where the binary was output to */
1173 /* Pointer to description of deferred address fixup. */
1176 if (!instrument_branches)
1181 subseg_set (data_section, 0); /* .data */
1182 frag_align (2, 0, 0); /* .align 2 */
1183 record_alignment (now_seg, 2);
1184 colon (BR_TAB_NAME); /* BR_TAB_NAME: */
1185 emit (0); /* .word 0 #link to next table */
1186 emit (br_cnt); /* .word n #length of table */
1188 for (i = 0; i < br_cnt; i++)
1190 sprintf (buf, "%s%d", BR_LABEL_BASE, i);
1192 fixP = fix_new (frag_now,
1193 p - frag_now->fr_literal,
1202 /*****************************************************************************
1203 cobr_fmt: generate a COBR-format instruction
1205 *************************************************************************** */
1208 cobr_fmt (arg, opcode, oP)
1209 /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1211 /* Opcode, with branch-prediction bits already set if necessary. */
1213 /* Pointer to description of instruction. */
1214 struct i960_opcode *oP;
1216 long instr; /* 32-bit instruction */
1217 struct regop regop; /* Description of register operand */
1218 int n; /* Number of operands */
1219 int var_frag; /* 1 if varying length code fragment should
1220 * be emitted; 0 if an address fix
1221 * should be emitted.
1229 /* First operand (if any) of a COBR is always a register
1230 operand. Parse it. */
1231 parse_regop (®op, arg[1], oP->operand[0]);
1232 instr |= (regop.n << 19) | (regop.mode << 13);
1236 /* Second operand (if any) of a COBR is always a register
1237 operand. Parse it. */
1238 parse_regop (®op, arg[2], oP->operand[1]);
1239 instr |= (regop.n << 14) | regop.special;
1250 if (instrument_branches)
1253 colon (brlab_next ());
1256 /* A third operand to a COBR is always a displacement. Parse
1257 it; if it's relaxable (a cobr "j" directive, or any cobr
1258 other than bbs/bbc when the "-norelax" option is not in use)
1259 set up a variable code fragment; otherwise set up an address
1261 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1262 get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1264 if (instrument_branches)
1272 /*****************************************************************************
1273 ctrl_fmt: generate a CTRL-format instruction
1275 *************************************************************************** */
1278 ctrl_fmt (targP, opcode, num_ops)
1279 char *targP; /* Pointer to text of lone operand (if any) */
1280 long opcode; /* Template of instruction */
1281 int num_ops; /* Number of operands */
1283 int instrument; /* TRUE iff we should add instrumentation to track
1284 * how often the branch is taken
1290 emit (opcode); /* Output opcode */
1295 instrument = instrument_branches && (opcode != CALL)
1296 && (opcode != B) && (opcode != RET) && (opcode != BAL);
1301 colon (brlab_next ());
1304 /* The operand MUST be an ip-relative displacment. Parse it
1305 * and set up address fix for the instruction we just output.
1307 get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1318 /*****************************************************************************
1319 emit: output instruction binary
1321 Output instruction binary, in target byte order, 4 bytes at a time.
1322 Return pointer to where it was placed.
1324 *************************************************************************** */
1328 long instr; /* Word to be output, host byte order */
1330 char *toP; /* Where to output it */
1332 toP = frag_more (4); /* Allocate storage */
1333 md_number_to_chars (toP, instr, 4); /* Convert to target byte order */
1338 /*****************************************************************************
1339 get_args: break individual arguments out of comma-separated list
1342 - all comments and labels have been removed
1343 - all strings of whitespace have been collapsed to a single blank.
1344 - all character constants ('x') have been replaced with decimal
1347 args[0] is untouched. args[1] points to first operand, etc. All args:
1348 - are NULL-terminated
1349 - contain no whitespace
1352 Number of operands (0,1,2, or 3) or -1 on error.
1354 *************************************************************************** */
1357 /* Pointer to comma-separated operands; MUCKED BY US */
1359 /* Output arg: pointers to operands placed in args[1-3]. MUST
1360 ACCOMMODATE 4 ENTRIES (args[0-3]). */
1363 register int n; /* Number of operands */
1366 /* Skip lead white space */
1380 /* Squeze blanks out by moving non-blanks toward start of string.
1381 * Isolate operands, whenever comma is found.
1388 && (! isalnum ((unsigned char) p[1])
1389 || ! isalnum ((unsigned char) p[-1])))
1397 /* Start of operand */
1400 as_bad (_("too many operands"));
1403 *to++ = '\0'; /* Terminate argument */
1404 args[++n] = to; /* Start next argument */
1418 /*****************************************************************************
1419 get_cdisp: handle displacement for a COBR or CTRL instruction.
1421 Parse displacement for a COBR or CTRL instruction.
1423 If successful, output the instruction opcode and set up for it,
1424 depending on the arg 'var_frag', either:
1425 o an address fixup to be done when all symbol values are known, or
1426 o a varying length code fragment, with address fixup info. This
1427 will be done for cobr instructions that may have to be relaxed
1428 in to compare/branch instructions (8 bytes) if the final
1429 address displacement is greater than 13 bits.
1431 ****************************************************************************/
1434 get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
1435 /* displacement as specified in source instruction */
1437 /* "COBR" or "CTRL" (for use in error message) */
1439 /* Instruction needing the displacement */
1441 /* # bits of displacement (13 for COBR, 24 for CTRL) */
1443 /* 1 if varying length code fragment should be emitted;
1444 * 0 if an address fix should be emitted.
1447 /* 1 if callj relocation should be done; else 0 */
1450 expressionS e; /* Parsed expression */
1451 fixS *fixP; /* Structure describing needed address fix */
1452 char *outP; /* Where instruction binary is output to */
1456 parse_expr (dispP, &e);
1460 as_bad (_("expression syntax error"));
1463 if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
1464 || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
1468 outP = frag_more (8); /* Allocate worst-case storage */
1469 md_number_to_chars (outP, instr, 4);
1470 frag_variant (rs_machine_dependent, 4, 4, 1,
1471 adds (e), offs (e), outP);
1475 /* Set up a new fix structure, so address can be updated
1476 * when all symbol values are known.
1478 outP = emit (instr);
1479 fixP = fix_new (frag_now,
1480 outP - frag_now->fr_literal,
1487 fixP->fx_tcbit = callj;
1489 /* We want to modify a bit field when the address is
1490 * known. But we don't need all the garbage in the
1491 * bit_fix structure. So we're going to lie and store
1492 * the number of bits affected instead of a pointer.
1494 fixP->fx_bit_fixP = (bit_fixS *) numbits;
1498 as_bad (_("attempt to branch into different segment"));
1502 as_bad (_("target of %s instruction must be a label"), ifmtP);
1508 /*****************************************************************************
1509 get_ispec: parse a memory operand for an index specification
1511 Here, an "index specification" is taken to be anything surrounded
1512 by square brackets and NOT followed by anything else.
1514 If it's found, detach it from the input string, remove the surrounding
1515 square brackets, and return a pointer to it. Otherwise, return NULL.
1517 *************************************************************************** */
1521 /* Pointer to memory operand from source instruction, no white space. */
1524 /* Points to start of index specification. */
1526 /* Points to end of index specification. */
1529 /* Find opening square bracket, if any. */
1530 start = strchr (textP, '[');
1535 /* Eliminate '[', detach from rest of operand */
1538 end = strchr (start, ']');
1542 as_bad (_("unmatched '['"));
1547 /* Eliminate ']' and make sure it was the last thing
1551 if (*(end + 1) != '\0')
1553 as_bad (_("garbage after index spec ignored"));
1560 /*****************************************************************************
1563 Look up a (suspected) register name in the register table and return the
1564 associated register number (or -1 if not found).
1566 *************************************************************************** */
1569 get_regnum (regname)
1570 char *regname; /* Suspected register name */
1574 rP = (int *) hash_find (reg_hash, regname);
1575 return (rP == NULL) ? -1 : *rP;
1579 /*****************************************************************************
1580 i_scan: perform lexical scan of ascii assembler instruction.
1583 - input string is an i80960 instruction (not a pseudo-op)
1584 - all comments and labels have been removed
1585 - all strings of whitespace have been collapsed to a single blank.
1588 args[0] points to opcode, other entries point to operands. All strings:
1589 - are NULL-terminated
1590 - contain no whitespace
1591 - have character constants ('x') replaced with a decimal number
1594 Number of operands (0,1,2, or 3) or -1 on error.
1596 *************************************************************************** */
1599 /* Pointer to ascii instruction; MUCKED BY US. */
1601 /* Output arg: pointers to opcode and operands placed here. MUST
1602 ACCOMMODATE 4 ENTRIES. */
1606 /* Isolate opcode */
1610 } /* Skip lead space, if any */
1612 for (; *iP != ' '; iP++)
1616 /* There are no operands */
1619 /* We never moved: there was no opcode either! */
1620 as_bad (_("missing opcode"));
1626 *iP++ = '\0'; /* Terminate opcode */
1627 return (get_args (iP, args));
1631 /*****************************************************************************
1632 mem_fmt: generate a MEMA- or MEMB-format instruction
1634 *************************************************************************** */
1636 mem_fmt (args, oP, callx)
1637 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1638 struct i960_opcode *oP; /* Pointer to description of instruction */
1639 int callx; /* Is this a callx opcode */
1641 int i; /* Loop counter */
1642 struct regop regop; /* Description of register operand */
1643 char opdesc; /* Operand descriptor byte */
1644 memS instr; /* Description of binary to be output */
1645 char *outP; /* Where the binary was output to */
1646 expressionS expr; /* Parsed expression */
1647 /* ->description of deferred address fixup */
1651 /* COFF support isn't in place yet for callx relaxing. */
1655 memset (&instr, '\0', sizeof (memS));
1656 instr.opcode = oP->opcode;
1658 /* Process operands. */
1659 for (i = 1; i <= oP->num_ops; i++)
1661 opdesc = oP->operand[i - 1];
1665 parse_memop (&instr, args[i], oP->format);
1669 parse_regop (®op, args[i], opdesc);
1670 instr.opcode |= regop.n << 19;
1674 /* Parse the displacement; this must be done before emitting the
1675 opcode, in case it is an expression using `.'. */
1676 parse_expr (instr.e, &expr);
1679 outP = emit (instr.opcode);
1681 if (instr.disp == 0)
1686 /* Process the displacement */
1690 as_bad (_("expression syntax error"));
1694 if (instr.disp == 32)
1696 (void) emit (offs (expr)); /* Output displacement */
1700 /* 12-bit displacement */
1701 if (offs (expr) & ~0xfff)
1703 /* Won't fit in 12 bits: convert already-output
1704 * instruction to MEMB format, output
1707 mema_to_memb (outP);
1708 (void) emit (offs (expr));
1712 /* WILL fit in 12 bits: OR into opcode and
1713 * overwrite the binary we already put out
1715 instr.opcode |= offs (expr);
1716 md_number_to_chars (outP, instr.opcode, 4);
1722 if (instr.disp == 12)
1724 /* Displacement is dependent on a symbol, whose value
1725 * may change at link time. We HAVE to reserve 32 bits.
1726 * Convert already-output opcode to MEMB format.
1728 mema_to_memb (outP);
1731 /* Output 0 displacement and set up address fixup for when
1732 * this symbol's value becomes known.
1734 outP = emit ((long) 0);
1735 fixP = fix_new_exp (frag_now,
1736 outP - frag_now->fr_literal,
1741 /* Steve's linker relaxing hack. Mark this 32-bit relocation as
1742 being in the instruction stream, specifically as part of a callx
1744 fixP->fx_bsr = callx;
1750 /*****************************************************************************
1751 mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1753 There are 2 possible MEMA formats:
1755 - displacement + abase
1757 They are distinguished by the setting of the MEMA_ABASE bit.
1759 *************************************************************************** */
1761 mema_to_memb (opcodeP)
1762 char *opcodeP; /* Where to find the opcode, in target byte order */
1764 long opcode; /* Opcode in host byte order */
1765 long mode; /* Mode bits for MEMB instruction */
1767 opcode = md_chars_to_number (opcodeP, 4);
1768 know (!(opcode & MEMB_BIT));
1770 mode = MEMB_BIT | D_BIT;
1771 if (opcode & MEMA_ABASE)
1776 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */
1777 opcode |= mode; /* Set MEMB mode bits */
1779 md_number_to_chars (opcodeP, opcode, 4);
1780 } /* mema_to_memb() */
1783 /*****************************************************************************
1784 parse_expr: parse an expression
1786 Use base assembler's expression parser to parse an expression.
1787 It, unfortunately, runs off a global which we have to save/restore
1788 in order to make it work for us.
1790 An empty expression string is treated as an absolute 0.
1792 Sets O_illegal regardless of expression evaluation if entire input
1793 string is not consumed in the evaluation -- tolerate no dangling junk!
1795 *************************************************************************** */
1797 parse_expr (textP, expP)
1798 char *textP; /* Text of expression to be parsed */
1799 expressionS *expP; /* Where to put the results of parsing */
1801 char *save_in; /* Save global here */
1808 /* Treat empty string as absolute 0 */
1809 expP->X_add_symbol = expP->X_op_symbol = NULL;
1810 expP->X_add_number = 0;
1811 expP->X_op = O_constant;
1815 save_in = input_line_pointer; /* Save global */
1816 input_line_pointer = textP; /* Make parser work for us */
1818 (void) expression (expP);
1819 if ((size_t) (input_line_pointer - textP) != strlen (textP))
1821 /* Did not consume all of the input */
1822 expP->X_op = O_illegal;
1824 symP = expP->X_add_symbol;
1825 if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
1827 /* Register name in an expression */
1828 /* FIXME: this isn't much of a check any more. */
1829 expP->X_op = O_illegal;
1832 input_line_pointer = save_in; /* Restore global */
1837 /*****************************************************************************
1839 Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1842 Assumes the input consists of:
1843 arg[0] opcode mnemonic ('ldconst')
1844 arg[1] first operand (constant)
1845 arg[2] name of register to be loaded
1847 Replaces opcode and/or operands as appropriate.
1849 Returns the new number of arguments, or -1 on failure.
1851 *************************************************************************** */
1855 char *arg[]; /* See above */
1857 int n; /* Constant to be loaded */
1858 int shift; /* Shift count for "shlo" instruction */
1859 static char buf[5]; /* Literal for first operand */
1860 static char buf2[5]; /* Literal for second operand */
1861 expressionS e; /* Parsed expression */
1864 arg[3] = NULL; /* So we can tell at the end if it got used or not */
1866 parse_expr (arg[1], &e);
1870 /* We're dependent on one or more symbols -- use "lda" */
1875 /* Try the following mappings:
1876 * ldconst 0,<reg> ->mov 0,<reg>
1877 * ldconst 31,<reg> ->mov 31,<reg>
1878 * ldconst 32,<reg> ->addo 1,31,<reg>
1879 * ldconst 62,<reg> ->addo 31,31,<reg>
1880 * ldconst 64,<reg> ->shlo 8,3,<reg>
1881 * ldconst -1,<reg> ->subo 1,0,<reg>
1882 * ldconst -31,<reg>->subo 31,0,<reg>
1884 * anthing else becomes:
1888 if ((0 <= n) && (n <= 31))
1893 else if ((-31 <= n) && (n <= -1))
1897 sprintf (buf, "%d", -n);
1902 else if ((32 <= n) && (n <= 62))
1907 sprintf (buf, "%d", n - 31);
1911 else if ((shift = shift_ok (n)) != 0)
1915 sprintf (buf, "%d", shift);
1917 sprintf (buf2, "%d", n >> shift);
1928 as_bad (_("invalid constant"));
1932 return (arg[3] == 0) ? 2 : 3;
1935 /*****************************************************************************
1936 parse_memop: parse a memory operand
1938 This routine is based on the observation that the 4 mode bits of the
1939 MEMB format, taken individually, have fairly consistent meaning:
1941 M3 (bit 13): 1 if displacement is present (D_BIT)
1942 M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1943 M1 (bit 11): 1 if index is present (I_BIT)
1944 M0 (bit 10): 1 if abase is present (A_BIT)
1946 So we parse the memory operand and set bits in the mode as we find
1947 things. Then at the end, if we go to MEMB format, we need only set
1948 the MEMB bit (M2) and our mode is built for us.
1950 Unfortunately, I said "fairly consistent". The exceptions:
1953 0100 Would seem illegal, but means "abase-only".
1955 0101 Would seem to mean "abase-only" -- it means IP-relative.
1956 Must be converted to 0100.
1958 0110 Would seem to mean "index-only", but is reserved.
1959 We turn on the D bit and provide a 0 displacement.
1961 The other thing to observe is that we parse from the right, peeling
1962 things * off as we go: first any index spec, then any abase, then
1965 *************************************************************************** */
1968 parse_memop (memP, argP, optype)
1969 memS *memP; /* Where to put the results */
1970 char *argP; /* Text of the operand to be parsed */
1971 int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
1973 char *indexP; /* Pointer to index specification with "[]" removed */
1974 char *p; /* Temp char pointer */
1975 char iprel_flag; /* True if this is an IP-relative operand */
1976 int regnum; /* Register number */
1977 /* Scale factor: 1,2,4,8, or 16. Later converted to internal format
1978 (0,1,2,3,4 respectively). */
1980 int mode; /* MEMB mode bits */
1981 int *intP; /* Pointer to register number */
1983 /* The following table contains the default scale factors for each
1984 type of memory instruction. It is accessed using (optype-MEM1)
1985 as an index -- thus it assumes the 'optype' constants are
1986 assigned consecutive values, in the order they appear in this
1988 static const int def_scale[] =
1994 -1, /* MEM12 -- no valid default */
1999 iprel_flag = mode = 0;
2001 /* Any index present? */
2002 indexP = get_ispec (argP);
2005 p = strchr (indexP, '*');
2008 /* No explicit scale -- use default for this instruction
2009 type and assembler mode. */
2013 /* GNU960 compatibility */
2014 scale = def_scale[optype - MEM1];
2018 *p++ = '\0'; /* Eliminate '*' */
2020 /* Now indexP->a '\0'-terminated register name,
2021 * and p->a scale factor.
2024 if (!strcmp (p, "16"))
2028 else if (strchr ("1248", *p) && (p[1] == '\0'))
2038 regnum = get_regnum (indexP); /* Get index reg. # */
2039 if (!IS_RG_REG (regnum))
2041 as_bad (_("invalid index register"));
2045 /* Convert scale to its binary encoding */
2064 as_bad (_("invalid scale factor"));
2068 memP->opcode |= scale | regnum; /* Set index bits in opcode */
2069 mode |= I_BIT; /* Found a valid index spec */
2072 /* Any abase (Register Indirect) specification present? */
2073 if ((p = strrchr (argP, '(')) != NULL)
2075 /* "(" is there -- does it start a legal abase spec? If not, it
2076 could be part of a displacement expression. */
2077 intP = (int *) hash_find (areg_hash, p);
2080 /* Got an abase here */
2082 *p = '\0'; /* discard register spec */
2083 if (regnum == IPREL)
2085 /* We have to specialcase ip-rel mode */
2090 memP->opcode |= regnum << 14;
2096 /* Any expression present? */
2103 /* Special-case ip-relative addressing */
2112 memP->opcode |= 5 << 10; /* IP-relative mode */
2118 /* Handle all other modes */
2122 /* Go with MEMA instruction format for now (grow to MEMB later
2123 if 12 bits is not enough for the displacement). MEMA format
2124 has a single mode bit: set it to indicate that abase is
2126 memP->opcode |= MEMA_ABASE;
2131 /* Go with MEMA instruction format for now (grow to MEMB later
2132 if 12 bits is not enough for the displacement). */
2137 /* For some reason, the bit string for this mode is not
2138 consistent: it should be 0 (exclusive of the MEMB bit), so we
2139 set it "by hand" here. */
2140 memP->opcode |= MEMB_BIT;
2144 /* set MEMB bit in mode, and OR in mode bits */
2145 memP->opcode |= mode | MEMB_BIT;
2149 /* Treat missing displacement as displacement of 0. */
2151 /* Fall into next case. */
2152 case D_BIT | A_BIT | I_BIT:
2154 /* set MEMB bit in mode, and OR in mode bits */
2155 memP->opcode |= mode | MEMB_BIT;
2165 /*****************************************************************************
2166 parse_po: parse machine-dependent pseudo-op
2168 This is a top-level routine for machine-dependent pseudo-ops. It slurps
2169 up the rest of the input line, breaks out the individual arguments,
2170 and dispatches them to the correct handler.
2171 *************************************************************************** */
2175 int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
2177 /* Pointers operands, with no embedded whitespace.
2178 arg[0] unused, arg[1-3]->operands */
2180 int n_ops; /* Number of operands */
2181 char *p; /* Pointer to beginning of unparsed argument string */
2182 char eol; /* Character that indicated end of line */
2184 extern char is_end_of_line[];
2186 /* Advance input pointer to end of line. */
2187 p = input_line_pointer;
2188 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2190 input_line_pointer++;
2192 eol = *input_line_pointer; /* Save end-of-line char */
2193 *input_line_pointer = '\0'; /* Terminate argument list */
2195 /* Parse out operands */
2196 n_ops = get_args (p, args);
2202 /* Dispatch to correct handler */
2206 s_sysproc (n_ops, args);
2209 s_leafproc (n_ops, args);
2216 /* Restore eol, so line numbers get updated correctly. Base
2217 assembler assumes we leave input pointer pointing at char
2218 following the eol. */
2219 *input_line_pointer++ = eol;
2222 /*****************************************************************************
2223 parse_regop: parse a register operand.
2225 In case of illegal operand, issue a message and return some valid
2226 information so instruction processing can continue.
2227 *************************************************************************** */
2230 parse_regop (regopP, optext, opdesc)
2231 struct regop *regopP; /* Where to put description of register operand */
2232 char *optext; /* Text of operand */
2233 char opdesc; /* Descriptor byte: what's legal for this operand */
2235 int n; /* Register number */
2236 expressionS e; /* Parsed expression */
2238 /* See if operand is a register */
2239 n = get_regnum (optext);
2244 /* global or local register */
2245 if (!REG_ALIGN (opdesc, n))
2247 as_bad (_("unaligned register"));
2251 regopP->special = 0;
2254 else if (IS_FP_REG (n) && FP_OK (opdesc))
2256 /* Floating point register, and it's allowed */
2257 regopP->n = n - FP0;
2259 regopP->special = 0;
2262 else if (IS_SF_REG (n) && SFR_OK (opdesc))
2264 /* Special-function register, and it's allowed */
2265 regopP->n = n - SF0;
2267 regopP->special = 1;
2268 if (!targ_has_sfr (regopP->n))
2270 as_bad (_("no such sfr in this architecture"));
2275 else if (LIT_OK (opdesc))
2277 /* How about a literal? */
2279 regopP->special = 0;
2281 { /* floating point literal acceptable */
2282 /* Skip over 0f, 0d, or 0e prefix */
2283 if ((optext[0] == '0')
2284 && (optext[1] >= 'd')
2285 && (optext[1] <= 'f'))
2290 if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
2295 if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
2303 { /* fixed point literal acceptable */
2304 parse_expr (optext, &e);
2305 if (e.X_op != O_constant
2306 || (offs (e) < 0) || (offs (e) > 31))
2308 as_bad (_("illegal literal"));
2311 regopP->n = offs (e);
2316 /* Nothing worked */
2318 regopP->mode = 0; /* Register r0 is always a good one */
2320 regopP->special = 0;
2321 } /* parse_regop() */
2323 /*****************************************************************************
2324 reg_fmt: generate a REG-format instruction
2326 *************************************************************************** */
2329 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2330 struct i960_opcode *oP; /* Pointer to description of instruction */
2332 long instr; /* Binary to be output */
2333 struct regop regop; /* Description of register operand */
2334 int n_ops; /* Number of operands */
2338 n_ops = oP->num_ops;
2342 parse_regop (®op, args[1], oP->operand[0]);
2344 if ((n_ops == 1) && !(instr & M3))
2346 /* 1-operand instruction in which the dst field should
2347 * be used (instead of src1).
2352 regop.mode = regop.special;
2359 /* regop.n goes in bit 0, needs no shifting */
2361 regop.special <<= 5;
2363 instr |= regop.n | regop.mode | regop.special;
2368 parse_regop (®op, args[2], oP->operand[1]);
2370 if ((n_ops == 2) && !(instr & M3))
2372 /* 2-operand instruction in which the dst field should
2373 * be used instead of src2).
2378 regop.mode = regop.special;
2387 regop.special <<= 6;
2389 instr |= regop.n | regop.mode | regop.special;
2393 parse_regop (®op, args[3], oP->operand[2]);
2396 regop.mode = regop.special;
2398 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2404 /*****************************************************************************
2406 Replace cobr instruction in a code fragment with equivalent branch and
2407 compare instructions, so it can reach beyond a 13-bit displacement.
2408 Set up an address fix/relocation for the new branch instruction.
2410 *************************************************************************** */
2412 /* This "conditional jump" table maps cobr instructions into
2413 equivalent compare and branch opcodes. */
2422 { /* COBR OPCODE: */
2423 { CHKBIT, BNO }, /* 0x30 - bbc */
2424 { CMPO, BG }, /* 0x31 - cmpobg */
2425 { CMPO, BE }, /* 0x32 - cmpobe */
2426 { CMPO, BGE }, /* 0x33 - cmpobge */
2427 { CMPO, BL }, /* 0x34 - cmpobl */
2428 { CMPO, BNE }, /* 0x35 - cmpobne */
2429 { CMPO, BLE }, /* 0x36 - cmpoble */
2430 { CHKBIT, BO }, /* 0x37 - bbs */
2431 { CMPI, BNO }, /* 0x38 - cmpibno */
2432 { CMPI, BG }, /* 0x39 - cmpibg */
2433 { CMPI, BE }, /* 0x3a - cmpibe */
2434 { CMPI, BGE }, /* 0x3b - cmpibge */
2435 { CMPI, BL }, /* 0x3c - cmpibl */
2436 { CMPI, BNE }, /* 0x3d - cmpibne */
2437 { CMPI, BLE }, /* 0x3e - cmpible */
2438 { CMPI, BO }, /* 0x3f - cmpibo */
2444 register fragS *fragP; /* fragP->fr_opcode is assumed to point to
2445 * the cobr instruction, which comes at the
2446 * end of the code fragment.
2449 int opcode, src1, src2, m1, s2;
2450 /* Bit fields from cobr instruction */
2451 long bp_bits; /* Branch prediction bits from cobr instruction */
2452 long instr; /* A single i960 instruction */
2453 /* ->instruction to be replaced */
2455 fixS *fixP; /* Relocation that can be done at assembly time */
2457 /* PICK UP & PARSE COBR INSTRUCTION */
2458 iP = fragP->fr_opcode;
2459 instr = md_chars_to_number (iP, 4);
2460 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2461 src1 = (instr >> 19) & 0x1f;
2462 m1 = (instr >> 13) & 1;
2464 src2 = (instr >> 14) & 0x1f;
2465 bp_bits = instr & BP_MASK;
2467 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2468 instr = coj[opcode].compare
2469 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2470 md_number_to_chars (iP, instr, 4);
2472 /* OUTPUT BRANCH INSTRUCTION */
2473 md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
2475 /* SET UP ADDRESS FIXUP/RELOCATION */
2476 fixP = fix_new (fragP,
2477 iP + 4 - fragP->fr_literal,
2484 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */
2491 /*****************************************************************************
2492 reloc_callj: Relocate a 'callj' instruction
2494 This is a "non-(GNU)-standard" machine-dependent hook. The base
2495 assembler calls it when it decides it can relocate an address at
2496 assembly time instead of emitting a relocation directive.
2498 Check to see if the relocation involves a 'callj' instruction to a:
2499 sysproc: Replace the default 'call' instruction with a 'calls'
2500 leafproc: Replace the default 'call' instruction with a 'bal'.
2501 other proc: Do nothing.
2503 See b.out.h for details on the 'n_other' field in a symbol structure.
2506 Assumes the caller has already figured out, in the case of a leafproc,
2507 to use the 'bal' entry point, and has substituted that symbol into the
2508 passed fixup structure.
2510 *************************************************************************** */
2513 /* Relocation that can be done at assembly time */
2516 /* Points to the binary for the instruction being relocated. */
2519 if (!fixP->fx_tcbit)
2521 /* This wasn't a callj instruction in the first place */
2525 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2527 if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2529 /* Symbol is a .sysproc: replace 'call' with 'calls'. System
2530 procedure number is (other-1). */
2531 md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2533 /* Nothing else needs to be done for this instruction. Make
2534 sure 'md_number_to_field()' will perform a no-op. */
2535 fixP->fx_bit_fixP = (bit_fixS *) 1;
2538 else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2540 /* Should not happen: see block comment above */
2541 as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
2543 else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2545 /* Replace 'call' with 'bal'; both instructions have the same
2546 format, so calling code should complete relocation as if
2547 nothing happened here. */
2548 md_number_to_chars (where, BAL, 4);
2550 else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2552 as_bad (_("Looks like a proc, but can't tell what kind.\n"));
2553 } /* switch on proc type */
2555 /* else Symbol is neither a sysproc nor a leafproc */
2559 /*****************************************************************************
2560 s_leafproc: process .leafproc pseudo-op
2562 .leafproc takes two arguments, the second one is optional:
2563 arg[1]: name of 'call' entry point to leaf procedure
2564 arg[2]: name of 'bal' entry point to leaf procedure
2566 If the two arguments are identical, or if the second one is missing,
2567 the first argument is taken to be the 'bal' entry point.
2569 If there are 2 distinct arguments, we must make sure that the 'bal'
2570 entry point immediately follows the 'call' entry point in the linked
2573 *************************************************************************** */
2575 s_leafproc (n_ops, args)
2576 int n_ops; /* Number of operands */
2577 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2579 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */
2580 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */
2582 if ((n_ops != 1) && (n_ops != 2))
2584 as_bad (_("should have 1 or 2 operands"));
2586 } /* Check number of arguments */
2588 /* Find or create symbol for 'call' entry point. */
2589 callP = symbol_find_or_make (args[1]);
2591 if (TC_S_IS_CALLNAME (callP))
2593 as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
2596 /* If that was the only argument, use it as the 'bal' entry point.
2597 * Otherwise, mark it as the 'call' entry point and find or create
2598 * another symbol for the 'bal' entry point.
2600 if ((n_ops == 1) || !strcmp (args[1], args[2]))
2602 TC_S_FORCE_TO_BALNAME (callP);
2607 TC_S_FORCE_TO_CALLNAME (callP);
2609 balP = symbol_find_or_make (args[2]);
2610 if (TC_S_IS_CALLNAME (balP))
2612 as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
2614 TC_S_FORCE_TO_BALNAME (balP);
2616 tc_set_bal_of_call (callP, balP);
2617 } /* if only one arg, or the args are the same */
2622 s_sysproc: process .sysproc pseudo-op
2624 .sysproc takes two arguments:
2625 arg[1]: name of entry point to system procedure
2626 arg[2]: 'entry_num' (index) of system procedure in the range
2629 For [ab].out, we store the 'entrynum' in the 'n_other' field of
2630 the symbol. Since that entry is normally 0, we bias 'entrynum'
2631 by adding 1 to it. It must be unbiased before it is used. */
2633 s_sysproc (n_ops, args)
2634 int n_ops; /* Number of operands */
2635 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2642 as_bad (_("should have two operands"));
2644 } /* bad arg count */
2646 /* Parse "entry_num" argument and check it for validity. */
2647 parse_expr (args[2], &exp);
2648 if (exp.X_op != O_constant
2650 || (offs (exp) > 31))
2652 as_bad (_("'entry_num' must be absolute number in [0,31]"));
2656 /* Find/make symbol and stick entry number (biased by +1) into it */
2657 symP = symbol_find_or_make (args[1]);
2659 if (TC_S_IS_SYSPROC (symP))
2661 as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
2664 TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */
2665 TC_S_FORCE_TO_SYSPROC (symP);
2669 /*****************************************************************************
2671 Determine if a "shlo" instruction can be used to implement a "ldconst".
2672 This means that some number X < 32 can be shifted left to produce the
2673 constant of interest.
2675 Return the shift count, or 0 if we can't do it.
2676 Caller calculates X by shifting original constant right 'shift' places.
2678 *************************************************************************** */
2682 int n; /* The constant of interest */
2684 int shift; /* The shift count */
2688 /* Can't do it for negative numbers */
2692 /* Shift 'n' right until a 1 is about to be lost */
2693 for (shift = 0; (n & 1) == 0; shift++)
2706 /* syntax: issue syntax error */
2711 as_bad (_("syntax error"));
2717 Return TRUE iff the target architecture supports the specified
2718 special-function register (sfr). */
2723 int n; /* Number (0-31) of sfr */
2725 switch (architecture)
2733 return ((0 <= n) && (n <= 4));
2736 return ((0 <= n) && (n <= 2));
2743 Return TRUE iff the target architecture supports the indicated
2744 class of instructions. */
2747 targ_has_iclass (ic)
2748 /* Instruction class; one of:
2749 I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2
2753 iclasses_seen |= ic;
2754 switch (architecture)
2757 return ic & (I_BASE | I_KX);
2759 return ic & (I_BASE | I_KX | I_FP | I_DEC);
2761 return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2763 return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
2765 return ic & (I_BASE | I_CX2 | I_JX);
2767 return ic & (I_BASE | I_CX2 | I_JX | I_HX);
2769 if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
2770 && (iclasses_seen & (I_CX | I_CX2)))
2772 as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
2773 iclasses_seen &= ~ic;
2779 /* Handle the MRI .endian pseudo-op. */
2788 name = input_line_pointer;
2789 c = get_symbol_end ();
2790 if (strcasecmp (name, "little") == 0)
2792 else if (strcasecmp (name, "big") == 0)
2793 as_bad (_("big endian mode is not supported"));
2795 as_warn (_("ignoring unrecognized .endian type `%s'"), name);
2797 *input_line_pointer = c;
2799 demand_empty_rest_of_line ();
2802 /* We have no need to default values of symbols. */
2806 md_undefined_symbol (name)
2812 /* Exactly what point is a PC-relative offset relative TO?
2813 On the i960, they're relative to the address of the instruction,
2814 which we have set up as the address of the fixup too. */
2816 md_pcrel_from (fixP)
2819 return fixP->fx_where + fixP->fx_frag->fr_address;
2823 md_apply_fix (fixP, val)
2827 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2829 if (!fixP->fx_bit_fixP)
2831 /* For callx, we always want to write out zero, and emit a
2832 symbolic relocation. */
2836 fixP->fx_addnumber = val;
2837 md_number_to_imm (place, val, fixP->fx_size, fixP);
2840 md_number_to_field (place, val, fixP->fx_bit_fixP);
2843 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2845 tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
2848 relax_addressT segment_address_in_file;
2850 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
2851 struct relocation_info ri;
2854 memset ((char *) &ri, '\0', sizeof (ri));
2855 symbolP = fixP->fx_addsy;
2856 know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2857 ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2858 /* These two 'cuz of NS32K */
2859 ri.r_callj = fixP->fx_tcbit;
2860 if (fixP->fx_bit_fixP)
2863 ri.r_length = nbytes_r_length[fixP->fx_size];
2864 ri.r_pcrel = fixP->fx_pcrel;
2865 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2867 if (fixP->fx_r_type != NO_RELOC)
2869 switch (fixP->fx_r_type)
2874 ri.r_length = fixP->fx_size - 1;
2888 else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
2891 ri.r_index = symbolP->sy_number;
2896 ri.r_index = S_GET_TYPE (symbolP);
2899 /* Output the relocation information in machine-dependent form. */
2900 md_ri_to_chars (where, &ri);
2903 #endif /* OBJ_AOUT or OBJ_BOUT */
2905 #if defined (OBJ_COFF) && defined (BFD)
2907 tc_coff_fix2rtype (fixP)
2913 if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
2916 if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
2924 tc_coff_sizemachdep (frag)
2928 return frag->fr_next->fr_address - frag->fr_address;
2934 /* Align an address by rounding it up to the specified boundary. */
2936 md_section_align (seg, addr)
2938 valueT addr; /* Address to be rounded up */
2940 return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
2941 } /* md_section_align() */
2943 extern int coff_flags;
2947 tc_headers_hook (headers)
2948 object_headers *headers;
2950 switch (architecture)
2953 coff_flags |= F_I960KA;
2957 coff_flags |= F_I960KB;
2961 coff_flags |= F_I960MC;
2965 coff_flags |= F_I960CA;
2969 coff_flags |= F_I960JX;
2973 coff_flags |= F_I960HX;
2977 if (iclasses_seen == I_BASE)
2978 coff_flags |= F_I960CORE;
2979 else if (iclasses_seen & I_CX)
2980 coff_flags |= F_I960CA;
2981 else if (iclasses_seen & I_HX)
2982 coff_flags |= F_I960HX;
2983 else if (iclasses_seen & I_JX)
2984 coff_flags |= F_I960JX;
2985 else if (iclasses_seen & I_CX2)
2986 coff_flags |= F_I960CA;
2987 else if (iclasses_seen & I_MIL)
2988 coff_flags |= F_I960MC;
2989 else if (iclasses_seen & (I_DEC | I_FP))
2990 coff_flags |= F_I960KB;
2992 coff_flags |= F_I960KA;
2996 if (flag_readonly_data_in_text)
2998 headers->filehdr.f_magic = I960RWMAGIC;
2999 headers->aouthdr.magic = OMAGIC;
3003 headers->filehdr.f_magic = I960ROMAGIC;
3004 headers->aouthdr.magic = NMAGIC;
3005 } /* set magic numbers */
3008 #endif /* OBJ_COFF */
3010 /* Things going on here:
3012 For bout, We need to assure a couple of simplifying
3013 assumptions about leafprocs for the linker: the leafproc
3014 entry symbols will be defined in the same assembly in
3015 which they're declared with the '.leafproc' directive;
3016 and if a leafproc has both 'call' and 'bal' entry points
3017 they are both global or both local.
3019 For coff, the call symbol has a second aux entry that
3020 contains the bal entry point. The bal symbol becomes a
3023 For coff representation, the call symbol has a second aux entry that
3024 contains the bal entry point. The bal symbol becomes a label. */
3027 tc_crawl_symbol_chain (headers)
3028 object_headers *headers;
3032 for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
3035 if (TC_S_IS_SYSPROC (symbolP))
3037 /* second aux entry already contains the sysproc number */
3038 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3039 S_SET_STORAGE_CLASS (symbolP, C_SCALL);
3040 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3042 } /* rewrite sysproc */
3043 #endif /* OBJ_COFF */
3045 if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
3048 } /* Not a leafproc symbol */
3050 if (!S_IS_DEFINED (symbolP))
3052 as_bad (_("leafproc symbol '%s' undefined"), S_GET_NAME (symbolP));
3053 } /* undefined leaf */
3055 if (TC_S_IS_CALLNAME (symbolP))
3057 symbolS *balP = tc_get_bal_of_call (symbolP);
3058 if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
3060 S_SET_EXTERNAL (symbolP);
3061 S_SET_EXTERNAL (balP);
3062 as_warn (_("Warning: making leafproc entries %s and %s both global\n"),
3063 S_GET_NAME (symbolP), S_GET_NAME (balP));
3064 } /* externality mismatch */
3066 } /* walk the symbol chain */
3069 /* For aout or bout, the bal immediately follows the call.
3071 For coff, we cheat and store a pointer to the bal symbol in the
3072 second aux entry of the call. */
3083 tc_set_bal_of_call (callP, balP)
3087 know (TC_S_IS_CALLNAME (callP));
3088 know (TC_S_IS_BALNAME (balP));
3092 callP->sy_tc = balP;
3093 S_SET_NUMBER_AUXILIARY (callP, 2);
3095 #else /* ! OBJ_COFF */
3098 /* If the 'bal' entry doesn't immediately follow the 'call'
3099 * symbol, unlink it from the symbol list and re-insert it.
3101 if (symbol_next (callP) != balP)
3103 symbol_remove (balP, &symbol_rootP, &symbol_lastP);
3104 symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
3105 } /* if not in order */
3107 #else /* ! OBJ_ABOUT */
3108 (as yet unwritten.);
3109 #endif /* ! OBJ_ABOUT */
3110 #endif /* ! OBJ_COFF */
3114 tc_get_bal_of_call (callP)
3119 know (TC_S_IS_CALLNAME (callP));
3122 retval = callP->sy_tc;
3125 retval = symbol_next (callP);
3127 (as yet unwritten.);
3128 #endif /* ! OBJ_ABOUT */
3129 #endif /* ! OBJ_COFF */
3131 know (TC_S_IS_BALNAME (retval));
3133 } /* _tc_get_bal_of_call() */
3136 tc_coff_symbol_emit_hook (symbolP)
3139 if (TC_S_IS_CALLNAME (symbolP))
3142 symbolS *balP = tc_get_bal_of_call (symbolP);
3145 /* second aux entry contains the bal entry point */
3146 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3148 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
3149 if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
3150 S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
3152 S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
3153 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3154 /* fix up the bal symbol */
3155 S_SET_STORAGE_CLASS (balP, C_LABEL);
3156 #endif /* OBJ_COFF */
3157 } /* only on calls */
3161 i960_handle_align (fragp)
3169 as_bad (_("option --link-relax is only supported in b.out format"));
3175 /* The text section "ends" with another alignment reloc, to which we
3176 aren't adding padding. */
3177 if (fragp->fr_next == text_last_frag
3178 || fragp->fr_next == data_last_frag)
3181 /* alignment directive */
3182 fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
3183 (int) fragp->fr_type);
3184 #endif /* OBJ_BOUT */
3188 i960_validate_fix (fixP, this_segment_type, add_symbolPP)
3190 segT this_segment_type;
3191 symbolS **add_symbolPP;
3193 #define add_symbolP (*add_symbolPP)
3194 if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP))
3196 /* Relocation should be done via the associated 'bal'
3197 entry point symbol. */
3199 if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP)))
3201 as_bad (_("No 'bal' entry point for leafproc %s"),
3202 S_GET_NAME (add_symbolP));
3205 fixP->fx_addsy = add_symbolP = tc_get_bal_of_call (add_symbolP);
3208 /* Still have to work out other conditions for these tests. */
3212 as_bad (_("callj to difference of two symbols"));
3216 if ((int) fixP->fx_bit_fixP == 13)
3218 /* This is a COBR instruction. They have only a 13-bit
3219 displacement and are only to be used for local branches:
3220 flag as error, don't generate relocation. */
3221 as_bad (_("can't use COBR format with external label"));
3222 fixP->fx_addsy = NULL; /* No relocations please. */
3231 /* end of tc-i960.c */