1 /* tc-i960.c - All the i80960-specific stuff
2 Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
5 This file is part of GAS.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* See comment on md_parse_option for 80960-specific invocation options. */
24 /* There are 4 different lengths of (potentially) symbol-based displacements
25 in the 80960 instruction set, each of which could require address fix-ups
26 and (in the case of external symbols) emission of relocation directives:
29 This is a standard length for the base assembler and requires no
33 This is a non-standard length, but the base assembler has a
34 hook for bit field address fixups: the fixS structure can
35 point to a descriptor of the field, in which case our
36 md_number_to_field() routine gets called to process it.
38 I made the hook a little cleaner by having fix_new() (in the base
39 assembler) return a pointer to the fixS in question. And I made it a
40 little simpler by storing the field size (in this case 13) instead of
41 of a pointer to another structure: 80960 displacements are ALWAYS
42 stored in the low-order bits of a 4-byte word.
44 Since the target of a COBR cannot be external, no relocation
45 directives for this size displacement have to be generated.
46 But the base assembler had to be modified to issue error
47 messages if the symbol did turn out to be external.
50 Fixups are handled as for the 13-bit case (except that 24 is stored
53 The relocation directive generated is the same as that for the 32-bit
54 displacement, except that it's PC-relative (the 32-bit displacement
55 never is). The i80960 version of the linker needs a mod to
56 distinguish and handle the 24-bit case.
59 MEMA formats are always promoted to MEMB (32-bit) if the displacement
60 is based on a symbol, because it could be relocated at link time.
61 The only time we use the 12-bit format is if an absolute value of
62 less than 4096 is specified, in which case we need neither a fixup nor
63 a relocation directive. */
72 #include "opcode/i960.h"
74 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
76 #define TC_S_IS_SYSPROC(s) ((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
77 #define TC_S_IS_BALNAME(s) (S_GET_OTHER(s) == N_BALNAME)
78 #define TC_S_IS_CALLNAME(s) (S_GET_OTHER(s) == N_CALLNAME)
79 #define TC_S_IS_BADPROC(s) ((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
81 #define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER((s), (p)+1))
82 #define TC_S_GET_SYSPROC(s) (S_GET_OTHER(s)-1)
84 #define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER((s), N_BALNAME))
85 #define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER((s), N_CALLNAME))
86 #define TC_S_FORCE_TO_SYSPROC(s) {;}
88 #else /* ! OBJ_A/BOUT */
91 #define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS(s) == C_SCALL)
92 #define TC_S_IS_BALNAME(s) (SF_GET_BALNAME(s))
93 #define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME(s))
94 #define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
96 #define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
97 #define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
99 #define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME(s))
100 #define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME(s))
101 #define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS((s), C_SCALL))
103 #else /* ! OBJ_COFF */
105 #endif /* ! OBJ_COFF */
106 #endif /* ! OBJ_A/BOUT */
108 extern char *input_line_pointer;
110 #if !defined (BFD_ASSEMBLER) && !defined (BFD)
112 const int md_reloc_size = sizeof (struct reloc);
114 const int md_reloc_size = sizeof (struct relocation_info);
115 #endif /* OBJ_COFF */
118 /* Local i80960 routines. */
120 static void brcnt_emit (); /* Emit branch-prediction instrumentation code */
121 static char *brlab_next (); /* Return next branch local label */
122 void brtab_emit (); /* Emit br-predict instrumentation table */
123 static void cobr_fmt (); /* Generate COBR instruction */
124 static void ctrl_fmt (); /* Generate CTRL instruction */
125 static char *emit (); /* Emit (internally) binary */
126 static int get_args (); /* Break arguments out of comma-separated list */
127 static void get_cdisp (); /* Handle COBR or CTRL displacement */
128 static char *get_ispec (); /* Find index specification string */
129 static int get_regnum (); /* Translate text to register number */
130 static int i_scan (); /* Lexical scan of instruction source */
131 static void mem_fmt (); /* Generate MEMA or MEMB instruction */
132 static void mema_to_memb (); /* Convert MEMA instruction to MEMB format */
133 static void parse_expr (); /* Parse an expression */
134 static int parse_ldconst (); /* Parse and replace a 'ldconst' pseudo-op */
135 static void parse_memop (); /* Parse a memory operand */
136 static void parse_po (); /* Parse machine-dependent pseudo-op */
137 static void parse_regop (); /* Parse a register operand */
138 static void reg_fmt (); /* Generate a REG format instruction */
139 void reloc_callj (); /* Relocate a 'callj' instruction */
140 static void relax_cobr (); /* "De-optimize" cobr into compare/branch */
141 static void s_leafproc (); /* Process '.leafproc' pseudo-op */
142 static void s_sysproc (); /* Process '.sysproc' pseudo-op */
143 static int shift_ok (); /* Will a 'shlo' substiture for a 'ldconst'? */
144 static void syntax (); /* Give syntax error */
145 static int targ_has_sfr (); /* Target chip supports spec-func register? */
146 static int targ_has_iclass (); /* Target chip supports instruction set? */
148 /* See md_parse_option() for meanings of these options */
149 static char norelax; /* True if -norelax switch seen */
150 static char instrument_branches; /* True if -b switch seen */
152 /* Characters that always start a comment.
153 If the pre-processor is disabled, these aren't very useful.
155 const char comment_chars[] = "#";
157 /* Characters that only start a comment at the beginning of
158 a line. If the line seems to have the form '# 123 filename'
159 .line and .file directives will appear in the pre-processed output.
161 Note that input_file.c hand checks for '#' at the beginning of the
162 first line of the input file. This is because the compiler outputs
163 #NO_APP at the beginning of its output.
166 /* Also note that comments started like this one will always work. */
168 const char line_comment_chars[1];
170 const char line_separator_chars[1];
172 /* Chars that can be used to separate mant from exp in floating point nums */
173 const char EXP_CHARS[] = "eE";
175 /* Chars that mean this number is a floating point constant,
176 as in 0f12.456 or 0d1.2345e12
178 const char FLT_CHARS[] = "fFdDtT";
181 /* Table used by base assembler to relax addresses based on varying length
182 instructions. The fields are:
183 1) most positive reach of this state,
184 2) most negative reach of this state,
185 3) how many bytes this mode will add to the size of the current frag
186 4) which index into the table to try if we can't fit into this one.
188 For i80960, the only application is the (de-)optimization of cobr
189 instructions into separate compare and branch instructions when a 13-bit
190 displacement won't hack it.
192 const relax_typeS md_relax_table[] =
194 {0, 0, 0, 0}, /* State 0 => no more relaxation possible */
195 {4088, -4096, 0, 2}, /* State 1: conditional branch (cobr) */
196 {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl) */
199 static void s_endian PARAMS ((int));
201 /* These are the machine dependent pseudo-ops.
203 This table describes all the machine specific pseudo-ops the assembler
204 has to support. The fields are:
205 pseudo-op name without dot
206 function to call to execute this pseudo-op
207 integer arg to pass to the function
212 const pseudo_typeS md_pseudo_table[] =
215 {"endian", s_endian, 0},
216 {"extended", float_cons, 't'},
217 {"leafproc", parse_po, S_LEAFPROC},
218 {"sysproc", parse_po, S_SYSPROC},
226 /* Macros to extract info from an 'expressionS' structure 'e' */
227 #define adds(e) e.X_add_symbol
228 #define offs(e) e.X_add_number
231 /* Branch-prediction bits for CTRL/COBR format opcodes */
232 #define BP_MASK 0x00000002 /* Mask for branch-prediction bit */
233 #define BP_TAKEN 0x00000000 /* Value to OR in to predict branch */
234 #define BP_NOT_TAKEN 0x00000002 /* Value to OR in to predict no branch */
237 /* Some instruction opcodes that we need explicitly */
238 #define BE 0x12000000
239 #define BG 0x11000000
240 #define BGE 0x13000000
241 #define BL 0x14000000
242 #define BLE 0x16000000
243 #define BNE 0x15000000
244 #define BNO 0x10000000
245 #define BO 0x17000000
246 #define CHKBIT 0x5a002700
247 #define CMPI 0x5a002080
248 #define CMPO 0x5a002000
251 #define BAL 0x0b000000
252 #define CALL 0x09000000
253 #define CALLS 0x66003800
254 #define RET 0x0a000000
257 /* These masks are used to build up a set of MEMB mode bits. */
260 #define MEMB_BIT 0x1000
264 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
266 #define MEMA_ABASE 0x2000
268 /* Info from which a MEMA or MEMB format instruction can be generated */
271 /* (First) 32 bits of instruction */
273 /* 0-(none), 12- or, 32-bit displacement needed */
275 /* The expression in the source instruction from which the
276 displacement should be determined. */
283 /* The two pieces of info we need to generate a register operand */
286 int mode; /* 0 =>local/global/spec reg; 1=> literal or fp reg */
287 int special; /* 0 =>not a sfr; 1=> is a sfr (not valid w/mode=0) */
288 int n; /* Register number or literal value */
292 /* Number and assembler mnemonic for all registers that can appear in
334 /* Numbers for special-function registers are for assembler internal
335 use only: they are scaled back to range [0-31] for binary output. */
371 /* Numbers for floating point registers are for assembler internal
372 use only: they are scaled back to [0-3] for binary output. */
380 { NULL, 0 }, /* END OF LIST */
383 #define IS_RG_REG(n) ((0 <= (n)) && ((n) < SF0))
384 #define IS_SF_REG(n) ((SF0 <= (n)) && ((n) < FP0))
385 #define IS_FP_REG(n) ((n) >= FP0)
387 /* Number and assembler mnemonic for all registers that can appear as
388 'abase' (indirect addressing) registers. */
430 /* For assembler internal use only: this number never appears in binary
434 { NULL, 0 }, /* END OF LIST */
439 static struct hash_control *op_hash; /* Opcode mnemonics */
440 static struct hash_control *reg_hash; /* Register name hash table */
441 static struct hash_control *areg_hash; /* Abase register hash table */
444 /* Architecture for which we are assembling */
445 #define ARCH_ANY 0 /* Default: no architecture checking done */
452 int architecture = ARCH_ANY; /* Architecture requested on invocation line */
453 int iclasses_seen; /* OR of instruction classes (I_* constants)
454 * for which we've actually assembled
459 /* BRANCH-PREDICTION INSTRUMENTATION
461 The following supports generation of branch-prediction instrumentation
462 (turned on by -b switch). The instrumentation collects counts
463 of branches taken/not-taken for later input to a utility that will
464 set the branch prediction bits of the instructions in accordance with
465 the behavior observed. (Note that the KX series does not have
468 The instrumentation consists of:
470 (1) before and after each conditional branch, a call to an external
471 routine that increments and steps over an inline counter. The
472 counter itself, initialized to 0, immediately follows the call
473 instruction. For each branch, the counter following the branch
474 is the number of times the branch was not taken, and the difference
475 between the counters is the number of times it was taken. An
476 example of an instrumented conditional branch:
484 (2) a table of pointers to the instrumented branches, so that an
485 external postprocessing routine can locate all of the counters.
486 the table begins with a 2-word header: a pointer to the next in
487 a linked list of such tables (initialized to 0); and a count
488 of the number of entries in the table (exclusive of the header.
490 Note that input source code is expected to already contain calls
491 an external routine that will link the branch local table into a
495 /* Number of branches instrumented so far. Also used to generate
496 unique local labels for each instrumented branch. */
499 #define BR_LABEL_BASE "LBRANCH"
500 /* Basename of local labels on instrumented branches, to avoid
501 conflict with compiler- generated local labels. */
503 #define BR_CNT_FUNC "__inc_branch"
504 /* Name of the external routine that will increment (and step over) an
507 #define BR_TAB_NAME "__BRANCH_TABLE__"
508 /* Name of the table of pointers to branches. A local (i.e.,
509 non-external) symbol. */
511 /*****************************************************************************
512 md_begin: One-time initialization.
516 *************************************************************************** */
520 int i; /* Loop counter */
521 const struct i960_opcode *oP; /* Pointer into opcode table */
522 const char *retval; /* Value returned by hash functions */
524 op_hash = hash_new ();
525 reg_hash = hash_new ();
526 areg_hash = hash_new ();
528 /* For some reason, the base assembler uses an empty string for "no
529 error message", instead of a NULL pointer. */
532 for (oP = i960_opcodes; oP->name && !retval; oP++)
533 retval = hash_insert (op_hash, oP->name, (PTR) oP);
535 for (i = 0; regnames[i].reg_name && !retval; i++)
536 retval = hash_insert (reg_hash, regnames[i].reg_name,
537 (char *) ®names[i].reg_num);
539 for (i = 0; aregs[i].areg_name && !retval; i++)
540 retval = hash_insert (areg_hash, aregs[i].areg_name,
541 (char *) &aregs[i].areg_num);
544 as_fatal (_("Hashing returned \"%s\"."), retval);
547 /*****************************************************************************
548 md_assemble: Assemble an instruction
550 Assumptions about the passed-in text:
551 - all comments, labels removed
552 - text is an instruction
553 - all white space compressed to single blanks
554 - all character constants have been replaced with decimal
556 *************************************************************************** */
559 char *textP; /* Source text of instruction */
561 /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
562 mnemonic arg[1-3]->operands, with char constants replaced by
566 int n_ops; /* Number of instruction operands */
567 /* Pointer to instruction description */
568 struct i960_opcode *oP;
569 /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
572 /* Setting of branch-prediction bit(s) to be OR'd into instruction
573 opcode of CTRL/COBR format instructions. */
576 int n; /* Offset of last character in opcode mnemonic */
578 static const char bp_error_msg[] = _("branch prediction invalid on this opcode");
581 /* Parse instruction into opcode and operands */
582 memset (args, '\0', sizeof (args));
583 n_ops = i_scan (textP, args);
586 return; /* Error message already issued */
589 /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
590 if (!strcmp (args[0], "ldconst"))
592 n_ops = parse_ldconst (args);
601 /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
602 n = strlen (args[0]) - 1;
605 if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
607 /* We could check here to see if the target architecture
608 supports branch prediction, but why bother? The bit will
609 just be ignored by processors that don't use it. */
611 bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
612 args[0][n - 1] = '\0'; /* Strip suffix from opcode mnemonic */
615 /* Look up opcode mnemonic in table and check number of operands.
616 Check that opcode is legal for the target architecture. If all
617 looks good, assemble instruction. */
618 oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
619 if (!oP || !targ_has_iclass (oP->iclass))
621 as_bad (_("invalid opcode, \"%s\"."), args[0]);
624 else if (n_ops != oP->num_ops)
626 as_bad (_("improper number of operands. expecting %d, got %d"),
635 ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
636 if (oP->format == FBRA)
638 /* Now generate a 'bno' to same arg */
639 ctrl_fmt (args[1], BNO | bp_bits, 1);
644 cobr_fmt (args, oP->opcode | bp_bits, oP);
649 as_warn (bp_error_msg);
654 if (args[0][0] == 'c' && args[0][1] == 'a')
658 as_warn (bp_error_msg);
660 mem_fmt (args, oP, 1);
670 as_warn (bp_error_msg);
672 mem_fmt (args, oP, 0);
677 as_warn (bp_error_msg);
679 /* Output opcode & set up "fixup" (relocation); flag
680 relocation as 'callj' type. */
681 know (oP->num_ops == 1);
682 get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
685 BAD_CASE (oP->format);
689 } /* md_assemble() */
691 /*****************************************************************************
692 md_number_to_chars: convert a number to target byte order
694 *************************************************************************** */
696 md_number_to_chars (buf, value, n)
701 number_to_chars_littleendian (buf, value, n);
704 /*****************************************************************************
705 md_chars_to_number: convert from target byte order to host byte order.
707 *************************************************************************** */
709 md_chars_to_number (val, n)
710 unsigned char *val; /* Value in target byte order */
711 int n; /* Number of bytes in the input */
715 for (retval = 0; n--;)
724 #define MAX_LITTLENUMS 6
725 #define LNUM_SIZE sizeof(LITTLENUM_TYPE)
727 /*****************************************************************************
728 md_atof: convert ascii to floating point
730 Turn a string at input_line_pointer into a floating point constant of type
731 'type', and store the appropriate bytes at *litP. The number of LITTLENUMS
732 emitted is returned at 'sizeP'. An error message is returned, or a pointer
733 to an empty message if OK.
735 Note we call the i386 floating point routine, rather than complicating
736 things with more files or symbolic links.
738 *************************************************************************** */
740 md_atof (type, litP, sizeP)
745 LITTLENUM_TYPE words[MAX_LITTLENUMS];
746 LITTLENUM_TYPE *wordP;
766 type = 'x'; /* That's what atof_ieee() understands */
771 return _("Bad call to md_atof()");
774 t = atof_ieee (input_line_pointer, type, words);
777 input_line_pointer = t;
780 *sizeP = prec * LNUM_SIZE;
782 /* Output the LITTLENUMs in REVERSE order in accord with i80960
783 word-order. (Dunno why atof_ieee doesn't do it in the right
784 order in the first place -- probably because it's a hack of
787 for (wordP = words + prec - 1; prec--;)
789 md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
790 litP += sizeof (LITTLENUM_TYPE);
797 /*****************************************************************************
800 *************************************************************************** */
802 md_number_to_imm (buf, val, n)
807 md_number_to_chars (buf, val, n);
811 /*****************************************************************************
814 *************************************************************************** */
816 md_number_to_disp (buf, val, n)
821 md_number_to_chars (buf, val, n);
824 /*****************************************************************************
827 Stick a value (an address fixup) into a bit field of
828 previously-generated instruction.
830 *************************************************************************** */
832 md_number_to_field (instrP, val, bfixP)
833 char *instrP; /* Pointer to instruction to be fixed */
834 long val; /* Address fixup value */
835 bit_fixS *bfixP; /* Description of bit field to be fixed up */
837 int numbits; /* Length of bit field to be fixed */
838 long instr; /* 32-bit instruction to be fixed-up */
839 long sign; /* 0 or -1, according to sign bit of 'val' */
841 /* Convert instruction back to host byte order. */
842 instr = md_chars_to_number (instrP, 4);
844 /* Surprise! -- we stored the number of bits to be modified rather
845 than a pointer to a structure. */
846 numbits = (int) bfixP;
849 /* This is a no-op, stuck here by reloc_callj() */
853 know ((numbits == 13) || (numbits == 24));
855 /* Propagate sign bit of 'val' for the given number of bits. Result
856 should be all 0 or all 1. */
857 sign = val >> ((int) numbits - 1);
858 if (((val < 0) && (sign != -1))
859 || ((val > 0) && (sign != 0)))
861 as_bad (_("Fixup of %ld too large for field width of %d"),
866 /* Put bit field into instruction and write back in target
869 val &= ~(-1 << (int) numbits); /* Clear unused sign bits */
871 md_number_to_chars (instrP, instr, 4);
873 } /* md_number_to_field() */
876 /*****************************************************************************
878 Invocation line includes a switch not recognized by the base assembler.
879 See if it's a processor-specific option. For the 960, these are:
882 Conditional branch instructions that require displacements
883 greater than 13 bits (or that have external targets) should
884 generate errors. The default is to replace each such
885 instruction with the corresponding compare (or chkbit) and
886 branch instructions. Note that the Intel "j" cobr directives
887 are ALWAYS "de-optimized" in this way when necessary,
888 regardless of the setting of this option.
891 Add code to collect information about branches taken, for
892 later optimization of branch prediction bits by a separate
893 tool. COBR and CNTL format instructions have branch
894 prediction bits (in the CX architecture); if "BR" represents
895 an instruction in one of these classes, the following rep-
896 resents the code generated by the assembler:
898 call <increment routine>
899 .word 0 # pre-counter
901 call <increment routine>
902 .word 0 # post-counter
904 A table of all such "Labels" is also generated.
907 -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
908 Select the 80960 architecture. Instructions or features not
909 supported by the selected architecture cause fatal errors.
910 The default is to generate code for any instruction or feature
911 that is supported by SOME version of the 960 (even if this
912 means mixing architectures!).
914 ****************************************************************************/
916 CONST char *md_shortopts = "A:b";
917 struct option md_longopts[] =
919 #define OPTION_LINKRELAX (OPTION_MD_BASE)
920 {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
921 {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
922 #define OPTION_NORELAX (OPTION_MD_BASE + 1)
923 {"norelax", no_argument, NULL, OPTION_NORELAX},
924 {"no-relax", no_argument, NULL, OPTION_NORELAX},
925 {NULL, no_argument, NULL, 0}
927 size_t md_longopts_size = sizeof (md_longopts);
934 static const struct tabentry arch_tab[] =
938 {"SA", ARCH_KA}, /* Synonym for KA */
939 {"SB", ARCH_KB}, /* Synonym for KB */
940 {"KC", ARCH_MC}, /* Synonym for MC */
949 md_parse_option (c, arg)
955 case OPTION_LINKRELAX:
957 flag_keep_locals = 1;
965 instrument_branches = 1;
970 const struct tabentry *tp;
973 for (tp = arch_tab; tp->flag != NULL; tp++)
974 if (!strcmp (p, tp->flag))
977 if (tp->flag == NULL)
979 as_bad (_("invalid architecture %s"), p);
983 architecture = tp->arch;
995 md_show_usage (stream)
999 fprintf (stream, _("I960 options:\n"));
1000 for (i = 0; arch_tab[i].flag; i++)
1001 fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
1002 fprintf (stream, _("\n\
1003 specify variant of 960 architecture\n\
1004 -b add code to collect statistics about branches taken\n\
1005 -link-relax preserve individual alignment directives so linker\n\
1006 can do relaxing (b.out format only)\n\
1007 -no-relax don't alter compare-and-branch instructions for\n\
1008 long displacements\n"));
1012 #ifndef BFD_ASSEMBLER
1013 /*****************************************************************************
1015 Called by base assembler after address relaxation is finished: modify
1016 variable fragments according to how much relaxation was done.
1018 If the fragment substate is still 1, a 13-bit displacement was enough
1019 to reach the symbol in question. Set up an address fixup, but otherwise
1020 leave the cobr instruction alone.
1022 If the fragment substate is 2, a 13-bit displacement was not enough.
1023 Replace the cobr with a two instructions (a compare and a branch).
1025 *************************************************************************** */
1027 md_convert_frag (headers, seg, fragP)
1028 object_headers *headers;
1032 fixS *fixP; /* Structure describing needed address fix */
1034 switch (fragP->fr_subtype)
1037 /* LEAVE SINGLE COBR INSTRUCTION */
1038 fixP = fix_new (fragP,
1039 fragP->fr_opcode - fragP->fr_literal,
1046 fixP->fx_bit_fixP = (bit_fixS *) 13; /* size of bit field */
1049 /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
1053 BAD_CASE (fragP->fr_subtype);
1058 /*****************************************************************************
1059 md_estimate_size_before_relax: How much does it look like *fragP will grow?
1061 Called by base assembler just before address relaxation.
1062 Return the amount by which the fragment will grow.
1064 Any symbol that is now undefined will not become defined; cobr's
1065 based on undefined symbols will have to be replaced with a compare
1066 instruction and a branch instruction, and the code fragment will grow
1069 *************************************************************************** */
1071 md_estimate_size_before_relax (fragP, segment_type)
1072 register fragS *fragP;
1073 register segT segment_type;
1075 /* If symbol is undefined in this segment, go to "relaxed" state
1076 (compare and branch instructions instead of cobr) right now. */
1077 if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
1083 } /* md_estimate_size_before_relax() */
1086 /*****************************************************************************
1088 This routine exists in order to overcome machine byte-order problems
1089 when dealing with bit-field entries in the relocation_info struct.
1091 But relocation info will be used on the host machine only (only
1092 executable code is actually downloaded to the i80960). Therefore,
1093 we leave it in host byte order.
1095 The above comment is no longer true. This routine now really
1096 does do the reordering (Ian Taylor 28 Aug 92).
1098 *************************************************************************** */
1100 md_ri_to_chars (where, ri)
1102 struct relocation_info *ri;
1104 md_number_to_chars (where, ri->r_address,
1105 sizeof (ri->r_address));
1106 where[4] = ri->r_index & 0x0ff;
1107 where[5] = (ri->r_index >> 8) & 0x0ff;
1108 where[6] = (ri->r_index >> 16) & 0x0ff;
1109 where[7] = ((ri->r_pcrel << 0)
1110 | (ri->r_length << 1)
1111 | (ri->r_extern << 3)
1114 | (ri->r_callj << 6));
1117 #ifndef WORKING_DOT_WORD
1119 int md_short_jump_size = 0;
1120 int md_long_jump_size = 0;
1123 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
1130 as_fatal (_("failed sanity check."));
1134 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
1136 addressT from_addr, to_addr;
1140 as_fatal (_("failed sanity check."));
1144 #endif /* BFD_ASSEMBLER */
1146 /* FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER */
1148 /*****************************************************************************
1149 brcnt_emit: Emit code to increment inline branch counter.
1151 See the comments above the declaration of 'br_cnt' for details on
1152 branch-prediction instrumentation.
1153 *************************************************************************** */
1157 ctrl_fmt (BR_CNT_FUNC, CALL, 1); /* Emit call to "increment" routine */
1158 emit (0); /* Emit inline counter to be incremented */
1161 /*****************************************************************************
1162 brlab_next: generate the next branch local label
1164 See the comments above the declaration of 'br_cnt' for details on
1165 branch-prediction instrumentation.
1166 *************************************************************************** */
1170 static char buf[20];
1172 sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1176 /*****************************************************************************
1177 brtab_emit: generate the fetch-prediction branch table.
1179 See the comments above the declaration of 'br_cnt' for details on
1180 branch-prediction instrumentation.
1182 The code emitted here would be functionally equivalent to the following
1183 example assembler source.
1188 .word 0 # link to next table
1189 .word 3 # length of table
1190 .word LBRANCH0 # 1st entry in table proper
1193 **************************************************************************** */
1199 char *p; /* Where the binary was output to */
1200 /* Pointer to description of deferred address fixup. */
1203 if (!instrument_branches)
1208 subseg_set (data_section, 0); /* .data */
1209 frag_align (2, 0, 0); /* .align 2 */
1210 record_alignment (now_seg, 2);
1211 colon (BR_TAB_NAME); /* BR_TAB_NAME: */
1212 emit (0); /* .word 0 #link to next table */
1213 emit (br_cnt); /* .word n #length of table */
1215 for (i = 0; i < br_cnt; i++)
1217 sprintf (buf, "%s%d", BR_LABEL_BASE, i);
1219 fixP = fix_new (frag_now,
1220 p - frag_now->fr_literal,
1229 /*****************************************************************************
1230 cobr_fmt: generate a COBR-format instruction
1232 *************************************************************************** */
1235 cobr_fmt (arg, opcode, oP)
1236 /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1238 /* Opcode, with branch-prediction bits already set if necessary. */
1240 /* Pointer to description of instruction. */
1241 struct i960_opcode *oP;
1243 long instr; /* 32-bit instruction */
1244 struct regop regop; /* Description of register operand */
1245 int n; /* Number of operands */
1246 int var_frag; /* 1 if varying length code fragment should
1247 * be emitted; 0 if an address fix
1248 * should be emitted.
1256 /* First operand (if any) of a COBR is always a register
1257 operand. Parse it. */
1258 parse_regop (®op, arg[1], oP->operand[0]);
1259 instr |= (regop.n << 19) | (regop.mode << 13);
1263 /* Second operand (if any) of a COBR is always a register
1264 operand. Parse it. */
1265 parse_regop (®op, arg[2], oP->operand[1]);
1266 instr |= (regop.n << 14) | regop.special;
1277 if (instrument_branches)
1280 colon (brlab_next ());
1283 /* A third operand to a COBR is always a displacement. Parse
1284 it; if it's relaxable (a cobr "j" directive, or any cobr
1285 other than bbs/bbc when the "-norelax" option is not in use)
1286 set up a variable code fragment; otherwise set up an address
1288 var_frag = !norelax || (oP->format == COJ); /* TRUE or FALSE */
1289 get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1291 if (instrument_branches)
1299 /*****************************************************************************
1300 ctrl_fmt: generate a CTRL-format instruction
1302 *************************************************************************** */
1305 ctrl_fmt (targP, opcode, num_ops)
1306 char *targP; /* Pointer to text of lone operand (if any) */
1307 long opcode; /* Template of instruction */
1308 int num_ops; /* Number of operands */
1310 int instrument; /* TRUE iff we should add instrumentation to track
1311 * how often the branch is taken
1317 emit (opcode); /* Output opcode */
1322 instrument = instrument_branches && (opcode != CALL)
1323 && (opcode != B) && (opcode != RET) && (opcode != BAL);
1328 colon (brlab_next ());
1331 /* The operand MUST be an ip-relative displacment. Parse it
1332 * and set up address fix for the instruction we just output.
1334 get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1345 /*****************************************************************************
1346 emit: output instruction binary
1348 Output instruction binary, in target byte order, 4 bytes at a time.
1349 Return pointer to where it was placed.
1351 *************************************************************************** */
1355 long instr; /* Word to be output, host byte order */
1357 char *toP; /* Where to output it */
1359 toP = frag_more (4); /* Allocate storage */
1360 md_number_to_chars (toP, instr, 4); /* Convert to target byte order */
1365 /*****************************************************************************
1366 get_args: break individual arguments out of comma-separated list
1369 - all comments and labels have been removed
1370 - all strings of whitespace have been collapsed to a single blank.
1371 - all character constants ('x') have been replaced with decimal
1374 args[0] is untouched. args[1] points to first operand, etc. All args:
1375 - are NULL-terminated
1376 - contain no whitespace
1379 Number of operands (0,1,2, or 3) or -1 on error.
1381 *************************************************************************** */
1384 /* Pointer to comma-separated operands; MUCKED BY US */
1386 /* Output arg: pointers to operands placed in args[1-3]. MUST
1387 ACCOMMODATE 4 ENTRIES (args[0-3]). */
1390 register int n; /* Number of operands */
1393 /* Skip lead white space */
1407 /* Squeze blanks out by moving non-blanks toward start of string.
1408 * Isolate operands, whenever comma is found.
1415 && (! isalnum (p[1]) || ! isalnum (p[-1])))
1423 /* Start of operand */
1426 as_bad (_("too many operands"));
1429 *to++ = '\0'; /* Terminate argument */
1430 args[++n] = to; /* Start next argument */
1444 /*****************************************************************************
1445 get_cdisp: handle displacement for a COBR or CTRL instruction.
1447 Parse displacement for a COBR or CTRL instruction.
1449 If successful, output the instruction opcode and set up for it,
1450 depending on the arg 'var_frag', either:
1451 o an address fixup to be done when all symbol values are known, or
1452 o a varying length code fragment, with address fixup info. This
1453 will be done for cobr instructions that may have to be relaxed
1454 in to compare/branch instructions (8 bytes) if the final
1455 address displacement is greater than 13 bits.
1457 ****************************************************************************/
1460 get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
1461 /* displacement as specified in source instruction */
1463 /* "COBR" or "CTRL" (for use in error message) */
1465 /* Instruction needing the displacement */
1467 /* # bits of displacement (13 for COBR, 24 for CTRL) */
1469 /* 1 if varying length code fragment should be emitted;
1470 * 0 if an address fix should be emitted.
1473 /* 1 if callj relocation should be done; else 0 */
1476 expressionS e; /* Parsed expression */
1477 fixS *fixP; /* Structure describing needed address fix */
1478 char *outP; /* Where instruction binary is output to */
1482 parse_expr (dispP, &e);
1486 as_bad (_("expression syntax error"));
1489 if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
1490 || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
1494 outP = frag_more (8); /* Allocate worst-case storage */
1495 md_number_to_chars (outP, instr, 4);
1496 frag_variant (rs_machine_dependent, 4, 4, 1,
1497 adds (e), offs (e), outP);
1501 /* Set up a new fix structure, so address can be updated
1502 * when all symbol values are known.
1504 outP = emit (instr);
1505 fixP = fix_new (frag_now,
1506 outP - frag_now->fr_literal,
1513 fixP->fx_tcbit = callj;
1515 /* We want to modify a bit field when the address is
1516 * known. But we don't need all the garbage in the
1517 * bit_fix structure. So we're going to lie and store
1518 * the number of bits affected instead of a pointer.
1520 fixP->fx_bit_fixP = (bit_fixS *) numbits;
1524 as_bad (_("attempt to branch into different segment"));
1528 as_bad (_("target of %s instruction must be a label"), ifmtP);
1534 /*****************************************************************************
1535 get_ispec: parse a memory operand for an index specification
1537 Here, an "index specification" is taken to be anything surrounded
1538 by square brackets and NOT followed by anything else.
1540 If it's found, detach it from the input string, remove the surrounding
1541 square brackets, and return a pointer to it. Otherwise, return NULL.
1543 *************************************************************************** */
1547 /* Pointer to memory operand from source instruction, no white space. */
1550 /* Points to start of index specification. */
1552 /* Points to end of index specification. */
1555 /* Find opening square bracket, if any. */
1556 start = strchr (textP, '[');
1561 /* Eliminate '[', detach from rest of operand */
1564 end = strchr (start, ']');
1568 as_bad (_("unmatched '['"));
1573 /* Eliminate ']' and make sure it was the last thing
1577 if (*(end + 1) != '\0')
1579 as_bad (_("garbage after index spec ignored"));
1586 /*****************************************************************************
1589 Look up a (suspected) register name in the register table and return the
1590 associated register number (or -1 if not found).
1592 *************************************************************************** */
1595 get_regnum (regname)
1596 char *regname; /* Suspected register name */
1600 rP = (int *) hash_find (reg_hash, regname);
1601 return (rP == NULL) ? -1 : *rP;
1605 /*****************************************************************************
1606 i_scan: perform lexical scan of ascii assembler instruction.
1609 - input string is an i80960 instruction (not a pseudo-op)
1610 - all comments and labels have been removed
1611 - all strings of whitespace have been collapsed to a single blank.
1614 args[0] points to opcode, other entries point to operands. All strings:
1615 - are NULL-terminated
1616 - contain no whitespace
1617 - have character constants ('x') replaced with a decimal number
1620 Number of operands (0,1,2, or 3) or -1 on error.
1622 *************************************************************************** */
1625 /* Pointer to ascii instruction; MUCKED BY US. */
1627 /* Output arg: pointers to opcode and operands placed here. MUST
1628 ACCOMMODATE 4 ENTRIES. */
1632 /* Isolate opcode */
1636 } /* Skip lead space, if any */
1638 for (; *iP != ' '; iP++)
1642 /* There are no operands */
1645 /* We never moved: there was no opcode either! */
1646 as_bad (_("missing opcode"));
1652 *iP++ = '\0'; /* Terminate opcode */
1653 return (get_args (iP, args));
1657 /*****************************************************************************
1658 mem_fmt: generate a MEMA- or MEMB-format instruction
1660 *************************************************************************** */
1662 mem_fmt (args, oP, callx)
1663 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
1664 struct i960_opcode *oP; /* Pointer to description of instruction */
1665 int callx; /* Is this a callx opcode */
1667 int i; /* Loop counter */
1668 struct regop regop; /* Description of register operand */
1669 char opdesc; /* Operand descriptor byte */
1670 memS instr; /* Description of binary to be output */
1671 char *outP; /* Where the binary was output to */
1672 expressionS expr; /* Parsed expression */
1673 /* ->description of deferred address fixup */
1677 /* COFF support isn't in place yet for callx relaxing. */
1681 memset (&instr, '\0', sizeof (memS));
1682 instr.opcode = oP->opcode;
1684 /* Process operands. */
1685 for (i = 1; i <= oP->num_ops; i++)
1687 opdesc = oP->operand[i - 1];
1691 parse_memop (&instr, args[i], oP->format);
1695 parse_regop (®op, args[i], opdesc);
1696 instr.opcode |= regop.n << 19;
1700 /* Parse the displacement; this must be done before emitting the
1701 opcode, in case it is an expression using `.'. */
1702 parse_expr (instr.e, &expr);
1705 outP = emit (instr.opcode);
1707 if (instr.disp == 0)
1712 /* Process the displacement */
1716 as_bad (_("expression syntax error"));
1720 if (instr.disp == 32)
1722 (void) emit (offs (expr)); /* Output displacement */
1726 /* 12-bit displacement */
1727 if (offs (expr) & ~0xfff)
1729 /* Won't fit in 12 bits: convert already-output
1730 * instruction to MEMB format, output
1733 mema_to_memb (outP);
1734 (void) emit (offs (expr));
1738 /* WILL fit in 12 bits: OR into opcode and
1739 * overwrite the binary we already put out
1741 instr.opcode |= offs (expr);
1742 md_number_to_chars (outP, instr.opcode, 4);
1748 if (instr.disp == 12)
1750 /* Displacement is dependent on a symbol, whose value
1751 * may change at link time. We HAVE to reserve 32 bits.
1752 * Convert already-output opcode to MEMB format.
1754 mema_to_memb (outP);
1757 /* Output 0 displacement and set up address fixup for when
1758 * this symbol's value becomes known.
1760 outP = emit ((long) 0);
1761 fixP = fix_new_exp (frag_now,
1762 outP - frag_now->fr_literal,
1767 /* Steve's linker relaxing hack. Mark this 32-bit relocation as
1768 being in the instruction stream, specifically as part of a callx
1770 fixP->fx_bsr = callx;
1776 /*****************************************************************************
1777 mema_to_memb: convert a MEMA-format opcode to a MEMB-format opcode.
1779 There are 2 possible MEMA formats:
1781 - displacement + abase
1783 They are distinguished by the setting of the MEMA_ABASE bit.
1785 *************************************************************************** */
1787 mema_to_memb (opcodeP)
1788 char *opcodeP; /* Where to find the opcode, in target byte order */
1790 long opcode; /* Opcode in host byte order */
1791 long mode; /* Mode bits for MEMB instruction */
1793 opcode = md_chars_to_number (opcodeP, 4);
1794 know (!(opcode & MEMB_BIT));
1796 mode = MEMB_BIT | D_BIT;
1797 if (opcode & MEMA_ABASE)
1802 opcode &= 0xffffc000; /* Clear MEMA offset and mode bits */
1803 opcode |= mode; /* Set MEMB mode bits */
1805 md_number_to_chars (opcodeP, opcode, 4);
1806 } /* mema_to_memb() */
1809 /*****************************************************************************
1810 parse_expr: parse an expression
1812 Use base assembler's expression parser to parse an expression.
1813 It, unfortunately, runs off a global which we have to save/restore
1814 in order to make it work for us.
1816 An empty expression string is treated as an absolute 0.
1818 Sets O_illegal regardless of expression evaluation if entire input
1819 string is not consumed in the evaluation -- tolerate no dangling junk!
1821 *************************************************************************** */
1823 parse_expr (textP, expP)
1824 char *textP; /* Text of expression to be parsed */
1825 expressionS *expP; /* Where to put the results of parsing */
1827 char *save_in; /* Save global here */
1834 /* Treat empty string as absolute 0 */
1835 expP->X_add_symbol = expP->X_op_symbol = NULL;
1836 expP->X_add_number = 0;
1837 expP->X_op = O_constant;
1841 save_in = input_line_pointer; /* Save global */
1842 input_line_pointer = textP; /* Make parser work for us */
1844 (void) expression (expP);
1845 if (input_line_pointer - textP != strlen (textP))
1847 /* Did not consume all of the input */
1848 expP->X_op = O_illegal;
1850 symP = expP->X_add_symbol;
1851 if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
1853 /* Register name in an expression */
1854 /* FIXME: this isn't much of a check any more. */
1855 expP->X_op = O_illegal;
1858 input_line_pointer = save_in; /* Restore global */
1863 /*****************************************************************************
1865 Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1868 Assumes the input consists of:
1869 arg[0] opcode mnemonic ('ldconst')
1870 arg[1] first operand (constant)
1871 arg[2] name of register to be loaded
1873 Replaces opcode and/or operands as appropriate.
1875 Returns the new number of arguments, or -1 on failure.
1877 *************************************************************************** */
1881 char *arg[]; /* See above */
1883 int n; /* Constant to be loaded */
1884 int shift; /* Shift count for "shlo" instruction */
1885 static char buf[5]; /* Literal for first operand */
1886 static char buf2[5]; /* Literal for second operand */
1887 expressionS e; /* Parsed expression */
1890 arg[3] = NULL; /* So we can tell at the end if it got used or not */
1892 parse_expr (arg[1], &e);
1896 /* We're dependent on one or more symbols -- use "lda" */
1901 /* Try the following mappings:
1902 * ldconst 0,<reg> ->mov 0,<reg>
1903 * ldconst 31,<reg> ->mov 31,<reg>
1904 * ldconst 32,<reg> ->addo 1,31,<reg>
1905 * ldconst 62,<reg> ->addo 31,31,<reg>
1906 * ldconst 64,<reg> ->shlo 8,3,<reg>
1907 * ldconst -1,<reg> ->subo 1,0,<reg>
1908 * ldconst -31,<reg>->subo 31,0,<reg>
1910 * anthing else becomes:
1914 if ((0 <= n) && (n <= 31))
1919 else if ((-31 <= n) && (n <= -1))
1923 sprintf (buf, "%d", -n);
1928 else if ((32 <= n) && (n <= 62))
1933 sprintf (buf, "%d", n - 31);
1937 else if ((shift = shift_ok (n)) != 0)
1941 sprintf (buf, "%d", shift);
1943 sprintf (buf2, "%d", n >> shift);
1954 as_bad (_("invalid constant"));
1958 return (arg[3] == 0) ? 2 : 3;
1961 /*****************************************************************************
1962 parse_memop: parse a memory operand
1964 This routine is based on the observation that the 4 mode bits of the
1965 MEMB format, taken individually, have fairly consistent meaning:
1967 M3 (bit 13): 1 if displacement is present (D_BIT)
1968 M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1969 M1 (bit 11): 1 if index is present (I_BIT)
1970 M0 (bit 10): 1 if abase is present (A_BIT)
1972 So we parse the memory operand and set bits in the mode as we find
1973 things. Then at the end, if we go to MEMB format, we need only set
1974 the MEMB bit (M2) and our mode is built for us.
1976 Unfortunately, I said "fairly consistent". The exceptions:
1979 0100 Would seem illegal, but means "abase-only".
1981 0101 Would seem to mean "abase-only" -- it means IP-relative.
1982 Must be converted to 0100.
1984 0110 Would seem to mean "index-only", but is reserved.
1985 We turn on the D bit and provide a 0 displacement.
1987 The other thing to observe is that we parse from the right, peeling
1988 things * off as we go: first any index spec, then any abase, then
1991 *************************************************************************** */
1994 parse_memop (memP, argP, optype)
1995 memS *memP; /* Where to put the results */
1996 char *argP; /* Text of the operand to be parsed */
1997 int optype; /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
1999 char *indexP; /* Pointer to index specification with "[]" removed */
2000 char *p; /* Temp char pointer */
2001 char iprel_flag; /* True if this is an IP-relative operand */
2002 int regnum; /* Register number */
2003 /* Scale factor: 1,2,4,8, or 16. Later converted to internal format
2004 (0,1,2,3,4 respectively). */
2006 int mode; /* MEMB mode bits */
2007 int *intP; /* Pointer to register number */
2009 /* The following table contains the default scale factors for each
2010 type of memory instruction. It is accessed using (optype-MEM1)
2011 as an index -- thus it assumes the 'optype' constants are
2012 assigned consecutive values, in the order they appear in this
2014 static const int def_scale[] =
2020 -1, /* MEM12 -- no valid default */
2025 iprel_flag = mode = 0;
2027 /* Any index present? */
2028 indexP = get_ispec (argP);
2031 p = strchr (indexP, '*');
2034 /* No explicit scale -- use default for this instruction
2035 type and assembler mode. */
2039 /* GNU960 compatibility */
2040 scale = def_scale[optype - MEM1];
2044 *p++ = '\0'; /* Eliminate '*' */
2046 /* Now indexP->a '\0'-terminated register name,
2047 * and p->a scale factor.
2050 if (!strcmp (p, "16"))
2054 else if (strchr ("1248", *p) && (p[1] == '\0'))
2064 regnum = get_regnum (indexP); /* Get index reg. # */
2065 if (!IS_RG_REG (regnum))
2067 as_bad (_("invalid index register"));
2071 /* Convert scale to its binary encoding */
2090 as_bad (_("invalid scale factor"));
2094 memP->opcode |= scale | regnum; /* Set index bits in opcode */
2095 mode |= I_BIT; /* Found a valid index spec */
2098 /* Any abase (Register Indirect) specification present? */
2099 if ((p = strrchr (argP, '(')) != NULL)
2101 /* "(" is there -- does it start a legal abase spec? If not, it
2102 could be part of a displacement expression. */
2103 intP = (int *) hash_find (areg_hash, p);
2106 /* Got an abase here */
2108 *p = '\0'; /* discard register spec */
2109 if (regnum == IPREL)
2111 /* We have to specialcase ip-rel mode */
2116 memP->opcode |= regnum << 14;
2122 /* Any expression present? */
2129 /* Special-case ip-relative addressing */
2138 memP->opcode |= 5 << 10; /* IP-relative mode */
2144 /* Handle all other modes */
2148 /* Go with MEMA instruction format for now (grow to MEMB later
2149 if 12 bits is not enough for the displacement). MEMA format
2150 has a single mode bit: set it to indicate that abase is
2152 memP->opcode |= MEMA_ABASE;
2157 /* Go with MEMA instruction format for now (grow to MEMB later
2158 if 12 bits is not enough for the displacement). */
2163 /* For some reason, the bit string for this mode is not
2164 consistent: it should be 0 (exclusive of the MEMB bit), so we
2165 set it "by hand" here. */
2166 memP->opcode |= MEMB_BIT;
2170 /* set MEMB bit in mode, and OR in mode bits */
2171 memP->opcode |= mode | MEMB_BIT;
2175 /* Treat missing displacement as displacement of 0. */
2177 /* Fall into next case. */
2178 case D_BIT | A_BIT | I_BIT:
2180 /* set MEMB bit in mode, and OR in mode bits */
2181 memP->opcode |= mode | MEMB_BIT;
2191 /*****************************************************************************
2192 parse_po: parse machine-dependent pseudo-op
2194 This is a top-level routine for machine-dependent pseudo-ops. It slurps
2195 up the rest of the input line, breaks out the individual arguments,
2196 and dispatches them to the correct handler.
2197 *************************************************************************** */
2201 int po_num; /* Pseudo-op number: currently S_LEAFPROC or S_SYSPROC */
2203 /* Pointers operands, with no embedded whitespace.
2204 arg[0] unused, arg[1-3]->operands */
2206 int n_ops; /* Number of operands */
2207 char *p; /* Pointer to beginning of unparsed argument string */
2208 char eol; /* Character that indicated end of line */
2210 extern char is_end_of_line[];
2212 /* Advance input pointer to end of line. */
2213 p = input_line_pointer;
2214 while (!is_end_of_line[(unsigned char) *input_line_pointer])
2216 input_line_pointer++;
2218 eol = *input_line_pointer; /* Save end-of-line char */
2219 *input_line_pointer = '\0'; /* Terminate argument list */
2221 /* Parse out operands */
2222 n_ops = get_args (p, args);
2228 /* Dispatch to correct handler */
2232 s_sysproc (n_ops, args);
2235 s_leafproc (n_ops, args);
2242 /* Restore eol, so line numbers get updated correctly. Base
2243 assembler assumes we leave input pointer pointing at char
2244 following the eol. */
2245 *input_line_pointer++ = eol;
2248 /*****************************************************************************
2249 parse_regop: parse a register operand.
2251 In case of illegal operand, issue a message and return some valid
2252 information so instruction processing can continue.
2253 *************************************************************************** */
2256 parse_regop (regopP, optext, opdesc)
2257 struct regop *regopP; /* Where to put description of register operand */
2258 char *optext; /* Text of operand */
2259 char opdesc; /* Descriptor byte: what's legal for this operand */
2261 int n; /* Register number */
2262 expressionS e; /* Parsed expression */
2264 /* See if operand is a register */
2265 n = get_regnum (optext);
2270 /* global or local register */
2271 if (!REG_ALIGN (opdesc, n))
2273 as_bad (_("unaligned register"));
2277 regopP->special = 0;
2280 else if (IS_FP_REG (n) && FP_OK (opdesc))
2282 /* Floating point register, and it's allowed */
2283 regopP->n = n - FP0;
2285 regopP->special = 0;
2288 else if (IS_SF_REG (n) && SFR_OK (opdesc))
2290 /* Special-function register, and it's allowed */
2291 regopP->n = n - SF0;
2293 regopP->special = 1;
2294 if (!targ_has_sfr (regopP->n))
2296 as_bad (_("no such sfr in this architecture"));
2301 else if (LIT_OK (opdesc))
2303 /* How about a literal? */
2305 regopP->special = 0;
2307 { /* floating point literal acceptable */
2308 /* Skip over 0f, 0d, or 0e prefix */
2309 if ((optext[0] == '0')
2310 && (optext[1] >= 'd')
2311 && (optext[1] <= 'f'))
2316 if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
2321 if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
2329 { /* fixed point literal acceptable */
2330 parse_expr (optext, &e);
2331 if (e.X_op != O_constant
2332 || (offs (e) < 0) || (offs (e) > 31))
2334 as_bad (_("illegal literal"));
2337 regopP->n = offs (e);
2342 /* Nothing worked */
2344 regopP->mode = 0; /* Register r0 is always a good one */
2346 regopP->special = 0;
2347 } /* parse_regop() */
2349 /*****************************************************************************
2350 reg_fmt: generate a REG-format instruction
2352 *************************************************************************** */
2355 char *args[]; /* args[0]->opcode mnemonic, args[1-3]->operands */
2356 struct i960_opcode *oP; /* Pointer to description of instruction */
2358 long instr; /* Binary to be output */
2359 struct regop regop; /* Description of register operand */
2360 int n_ops; /* Number of operands */
2364 n_ops = oP->num_ops;
2368 parse_regop (®op, args[1], oP->operand[0]);
2370 if ((n_ops == 1) && !(instr & M3))
2372 /* 1-operand instruction in which the dst field should
2373 * be used (instead of src1).
2378 regop.mode = regop.special;
2385 /* regop.n goes in bit 0, needs no shifting */
2387 regop.special <<= 5;
2389 instr |= regop.n | regop.mode | regop.special;
2394 parse_regop (®op, args[2], oP->operand[1]);
2396 if ((n_ops == 2) && !(instr & M3))
2398 /* 2-operand instruction in which the dst field should
2399 * be used instead of src2).
2404 regop.mode = regop.special;
2413 regop.special <<= 6;
2415 instr |= regop.n | regop.mode | regop.special;
2419 parse_regop (®op, args[3], oP->operand[2]);
2422 regop.mode = regop.special;
2424 instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2430 /*****************************************************************************
2432 Replace cobr instruction in a code fragment with equivalent branch and
2433 compare instructions, so it can reach beyond a 13-bit displacement.
2434 Set up an address fix/relocation for the new branch instruction.
2436 *************************************************************************** */
2438 /* This "conditional jump" table maps cobr instructions into
2439 equivalent compare and branch opcodes. */
2448 { /* COBR OPCODE: */
2449 { CHKBIT, BNO }, /* 0x30 - bbc */
2450 { CMPO, BG }, /* 0x31 - cmpobg */
2451 { CMPO, BE }, /* 0x32 - cmpobe */
2452 { CMPO, BGE }, /* 0x33 - cmpobge */
2453 { CMPO, BL }, /* 0x34 - cmpobl */
2454 { CMPO, BNE }, /* 0x35 - cmpobne */
2455 { CMPO, BLE }, /* 0x36 - cmpoble */
2456 { CHKBIT, BO }, /* 0x37 - bbs */
2457 { CMPI, BNO }, /* 0x38 - cmpibno */
2458 { CMPI, BG }, /* 0x39 - cmpibg */
2459 { CMPI, BE }, /* 0x3a - cmpibe */
2460 { CMPI, BGE }, /* 0x3b - cmpibge */
2461 { CMPI, BL }, /* 0x3c - cmpibl */
2462 { CMPI, BNE }, /* 0x3d - cmpibne */
2463 { CMPI, BLE }, /* 0x3e - cmpible */
2464 { CMPI, BO }, /* 0x3f - cmpibo */
2470 register fragS *fragP; /* fragP->fr_opcode is assumed to point to
2471 * the cobr instruction, which comes at the
2472 * end of the code fragment.
2475 int opcode, src1, src2, m1, s2;
2476 /* Bit fields from cobr instruction */
2477 long bp_bits; /* Branch prediction bits from cobr instruction */
2478 long instr; /* A single i960 instruction */
2479 /* ->instruction to be replaced */
2481 fixS *fixP; /* Relocation that can be done at assembly time */
2483 /* PICK UP & PARSE COBR INSTRUCTION */
2484 iP = fragP->fr_opcode;
2485 instr = md_chars_to_number (iP, 4);
2486 opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index */
2487 src1 = (instr >> 19) & 0x1f;
2488 m1 = (instr >> 13) & 1;
2490 src2 = (instr >> 14) & 0x1f;
2491 bp_bits = instr & BP_MASK;
2493 /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2494 instr = coj[opcode].compare
2495 | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2496 md_number_to_chars (iP, instr, 4);
2498 /* OUTPUT BRANCH INSTRUCTION */
2499 md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
2501 /* SET UP ADDRESS FIXUP/RELOCATION */
2502 fixP = fix_new (fragP,
2503 iP + 4 - fragP->fr_literal,
2510 fixP->fx_bit_fixP = (bit_fixS *) 24; /* Store size of bit field */
2517 /*****************************************************************************
2518 reloc_callj: Relocate a 'callj' instruction
2520 This is a "non-(GNU)-standard" machine-dependent hook. The base
2521 assembler calls it when it decides it can relocate an address at
2522 assembly time instead of emitting a relocation directive.
2524 Check to see if the relocation involves a 'callj' instruction to a:
2525 sysproc: Replace the default 'call' instruction with a 'calls'
2526 leafproc: Replace the default 'call' instruction with a 'bal'.
2527 other proc: Do nothing.
2529 See b.out.h for details on the 'n_other' field in a symbol structure.
2532 Assumes the caller has already figured out, in the case of a leafproc,
2533 to use the 'bal' entry point, and has substituted that symbol into the
2534 passed fixup structure.
2536 *************************************************************************** */
2539 /* Relocation that can be done at assembly time */
2542 /* Points to the binary for the instruction being relocated. */
2545 if (!fixP->fx_tcbit)
2547 /* This wasn't a callj instruction in the first place */
2551 where = fixP->fx_frag->fr_literal + fixP->fx_where;
2553 if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2555 /* Symbol is a .sysproc: replace 'call' with 'calls'. System
2556 procedure number is (other-1). */
2557 md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2559 /* Nothing else needs to be done for this instruction. Make
2560 sure 'md_number_to_field()' will perform a no-op. */
2561 fixP->fx_bit_fixP = (bit_fixS *) 1;
2564 else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2566 /* Should not happen: see block comment above */
2567 as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
2569 else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2571 /* Replace 'call' with 'bal'; both instructions have the same
2572 format, so calling code should complete relocation as if
2573 nothing happened here. */
2574 md_number_to_chars (where, BAL, 4);
2576 else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2578 as_bad (_("Looks like a proc, but can't tell what kind.\n"));
2579 } /* switch on proc type */
2581 /* else Symbol is neither a sysproc nor a leafproc */
2585 /*****************************************************************************
2586 s_leafproc: process .leafproc pseudo-op
2588 .leafproc takes two arguments, the second one is optional:
2589 arg[1]: name of 'call' entry point to leaf procedure
2590 arg[2]: name of 'bal' entry point to leaf procedure
2592 If the two arguments are identical, or if the second one is missing,
2593 the first argument is taken to be the 'bal' entry point.
2595 If there are 2 distinct arguments, we must make sure that the 'bal'
2596 entry point immediately follows the 'call' entry point in the linked
2599 *************************************************************************** */
2601 s_leafproc (n_ops, args)
2602 int n_ops; /* Number of operands */
2603 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2605 symbolS *callP; /* Pointer to leafproc 'call' entry point symbol */
2606 symbolS *balP; /* Pointer to leafproc 'bal' entry point symbol */
2608 if ((n_ops != 1) && (n_ops != 2))
2610 as_bad (_("should have 1 or 2 operands"));
2612 } /* Check number of arguments */
2614 /* Find or create symbol for 'call' entry point. */
2615 callP = symbol_find_or_make (args[1]);
2617 if (TC_S_IS_CALLNAME (callP))
2619 as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
2622 /* If that was the only argument, use it as the 'bal' entry point.
2623 * Otherwise, mark it as the 'call' entry point and find or create
2624 * another symbol for the 'bal' entry point.
2626 if ((n_ops == 1) || !strcmp (args[1], args[2]))
2628 TC_S_FORCE_TO_BALNAME (callP);
2633 TC_S_FORCE_TO_CALLNAME (callP);
2635 balP = symbol_find_or_make (args[2]);
2636 if (TC_S_IS_CALLNAME (balP))
2638 as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
2640 TC_S_FORCE_TO_BALNAME (balP);
2642 tc_set_bal_of_call (callP, balP);
2643 } /* if only one arg, or the args are the same */
2648 s_sysproc: process .sysproc pseudo-op
2650 .sysproc takes two arguments:
2651 arg[1]: name of entry point to system procedure
2652 arg[2]: 'entry_num' (index) of system procedure in the range
2655 For [ab].out, we store the 'entrynum' in the 'n_other' field of
2656 the symbol. Since that entry is normally 0, we bias 'entrynum'
2657 by adding 1 to it. It must be unbiased before it is used. */
2659 s_sysproc (n_ops, args)
2660 int n_ops; /* Number of operands */
2661 char *args[]; /* args[1]->1st operand, args[2]->2nd operand */
2668 as_bad (_("should have two operands"));
2670 } /* bad arg count */
2672 /* Parse "entry_num" argument and check it for validity. */
2673 parse_expr (args[2], &exp);
2674 if (exp.X_op != O_constant
2676 || (offs (exp) > 31))
2678 as_bad (_("'entry_num' must be absolute number in [0,31]"));
2682 /* Find/make symbol and stick entry number (biased by +1) into it */
2683 symP = symbol_find_or_make (args[1]);
2685 if (TC_S_IS_SYSPROC (symP))
2687 as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
2690 TC_S_SET_SYSPROC (symP, offs (exp)); /* encode entry number */
2691 TC_S_FORCE_TO_SYSPROC (symP);
2695 /*****************************************************************************
2697 Determine if a "shlo" instruction can be used to implement a "ldconst".
2698 This means that some number X < 32 can be shifted left to produce the
2699 constant of interest.
2701 Return the shift count, or 0 if we can't do it.
2702 Caller calculates X by shifting original constant right 'shift' places.
2704 *************************************************************************** */
2708 int n; /* The constant of interest */
2710 int shift; /* The shift count */
2714 /* Can't do it for negative numbers */
2718 /* Shift 'n' right until a 1 is about to be lost */
2719 for (shift = 0; (n & 1) == 0; shift++)
2732 /* syntax: issue syntax error */
2737 as_bad (_("syntax error"));
2743 Return TRUE iff the target architecture supports the specified
2744 special-function register (sfr). */
2749 int n; /* Number (0-31) of sfr */
2751 switch (architecture)
2759 return ((0 <= n) && (n <= 4));
2762 return ((0 <= n) && (n <= 2));
2769 Return TRUE iff the target architecture supports the indicated
2770 class of instructions. */
2773 targ_has_iclass (ic)
2774 /* Instruction class; one of:
2775 I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2
2779 iclasses_seen |= ic;
2780 switch (architecture)
2783 return ic & (I_BASE | I_KX);
2785 return ic & (I_BASE | I_KX | I_FP | I_DEC);
2787 return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2789 return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
2791 return ic & (I_BASE | I_CX2 | I_JX);
2793 return ic & (I_BASE | I_CX2 | I_JX | I_HX);
2795 if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
2796 && (iclasses_seen & (I_CX | I_CX2)))
2798 as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
2799 iclasses_seen &= ~ic;
2805 /* Handle the MRI .endian pseudo-op. */
2814 name = input_line_pointer;
2815 c = get_symbol_end ();
2816 if (strcasecmp (name, "little") == 0)
2818 else if (strcasecmp (name, "big") == 0)
2819 as_bad (_("big endian mode is not supported"));
2821 as_warn (_("ignoring unrecognized .endian type `%s'"), name);
2823 *input_line_pointer = c;
2825 demand_empty_rest_of_line ();
2828 /* We have no need to default values of symbols. */
2832 md_undefined_symbol (name)
2838 /* Exactly what point is a PC-relative offset relative TO?
2839 On the i960, they're relative to the address of the instruction,
2840 which we have set up as the address of the fixup too. */
2842 md_pcrel_from (fixP)
2845 return fixP->fx_where + fixP->fx_frag->fr_address;
2849 md_apply_fix (fixP, val)
2853 char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2855 if (!fixP->fx_bit_fixP)
2857 /* For callx, we always want to write out zero, and emit a
2858 symbolic relocation. */
2862 fixP->fx_addnumber = val;
2863 md_number_to_imm (place, val, fixP->fx_size, fixP);
2866 md_number_to_field (place, val, fixP->fx_bit_fixP);
2869 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2871 tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
2874 relax_addressT segment_address_in_file;
2876 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
2877 struct relocation_info ri;
2880 memset ((char *) &ri, '\0', sizeof (ri));
2881 symbolP = fixP->fx_addsy;
2882 know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2883 ri.r_bsr = fixP->fx_bsr; /*SAC LD RELAX HACK */
2884 /* These two 'cuz of NS32K */
2885 ri.r_callj = fixP->fx_tcbit;
2886 if (fixP->fx_bit_fixP)
2889 ri.r_length = nbytes_r_length[fixP->fx_size];
2890 ri.r_pcrel = fixP->fx_pcrel;
2891 ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2893 if (fixP->fx_r_type != NO_RELOC)
2895 switch (fixP->fx_r_type)
2900 ri.r_length = fixP->fx_size - 1;
2914 else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
2917 ri.r_index = symbolP->sy_number;
2922 ri.r_index = S_GET_TYPE (symbolP);
2925 /* Output the relocation information in machine-dependent form. */
2926 md_ri_to_chars (where, &ri);
2929 #endif /* OBJ_AOUT or OBJ_BOUT */
2931 #if defined (OBJ_COFF) && defined (BFD)
2933 tc_coff_fix2rtype (fixP)
2939 if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
2942 if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
2950 tc_coff_sizemachdep (frag)
2954 return frag->fr_next->fr_address - frag->fr_address;
2960 /* Align an address by rounding it up to the specified boundary. */
2962 md_section_align (seg, addr)
2964 valueT addr; /* Address to be rounded up */
2966 return ((addr + (1 << section_alignment[(int) seg]) - 1) & (-1 << section_alignment[(int) seg]));
2967 } /* md_section_align() */
2969 extern int coff_flags;
2973 tc_headers_hook (headers)
2974 object_headers *headers;
2976 switch (architecture)
2979 coff_flags |= F_I960KA;
2983 coff_flags |= F_I960KB;
2987 coff_flags |= F_I960MC;
2991 coff_flags |= F_I960CA;
2995 coff_flags |= F_I960JX;
2999 coff_flags |= F_I960HX;
3003 if (iclasses_seen == I_BASE)
3004 coff_flags |= F_I960CORE;
3005 else if (iclasses_seen & I_CX)
3006 coff_flags |= F_I960CA;
3007 else if (iclasses_seen & I_HX)
3008 coff_flags |= F_I960HX;
3009 else if (iclasses_seen & I_JX)
3010 coff_flags |= F_I960JX;
3011 else if (iclasses_seen & I_CX2)
3012 coff_flags |= F_I960CA;
3013 else if (iclasses_seen & I_MIL)
3014 coff_flags |= F_I960MC;
3015 else if (iclasses_seen & (I_DEC | I_FP))
3016 coff_flags |= F_I960KB;
3018 coff_flags |= F_I960KA;
3022 if (flag_readonly_data_in_text)
3024 headers->filehdr.f_magic = I960RWMAGIC;
3025 headers->aouthdr.magic = OMAGIC;
3029 headers->filehdr.f_magic = I960ROMAGIC;
3030 headers->aouthdr.magic = NMAGIC;
3031 } /* set magic numbers */
3034 #endif /* OBJ_COFF */
3036 /* Things going on here:
3038 For bout, We need to assure a couple of simplifying
3039 assumptions about leafprocs for the linker: the leafproc
3040 entry symbols will be defined in the same assembly in
3041 which they're declared with the '.leafproc' directive;
3042 and if a leafproc has both 'call' and 'bal' entry points
3043 they are both global or both local.
3045 For coff, the call symbol has a second aux entry that
3046 contains the bal entry point. The bal symbol becomes a
3049 For coff representation, the call symbol has a second aux entry that
3050 contains the bal entry point. The bal symbol becomes a label. */
3053 tc_crawl_symbol_chain (headers)
3054 object_headers *headers;
3058 for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
3061 if (TC_S_IS_SYSPROC (symbolP))
3063 /* second aux entry already contains the sysproc number */
3064 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3065 S_SET_STORAGE_CLASS (symbolP, C_SCALL);
3066 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3068 } /* rewrite sysproc */
3069 #endif /* OBJ_COFF */
3071 if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
3074 } /* Not a leafproc symbol */
3076 if (!S_IS_DEFINED (symbolP))
3078 as_bad (_("leafproc symbol '%s' undefined"), S_GET_NAME (symbolP));
3079 } /* undefined leaf */
3081 if (TC_S_IS_CALLNAME (symbolP))
3083 symbolS *balP = tc_get_bal_of_call (symbolP);
3084 if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
3086 S_SET_EXTERNAL (symbolP);
3087 S_SET_EXTERNAL (balP);
3088 as_warn (_("Warning: making leafproc entries %s and %s both global\n"),
3089 S_GET_NAME (symbolP), S_GET_NAME (balP));
3090 } /* externality mismatch */
3092 } /* walk the symbol chain */
3095 /* For aout or bout, the bal immediately follows the call.
3097 For coff, we cheat and store a pointer to the bal symbol in the
3098 second aux entry of the call. */
3109 tc_set_bal_of_call (callP, balP)
3113 know (TC_S_IS_CALLNAME (callP));
3114 know (TC_S_IS_BALNAME (balP));
3118 callP->sy_tc = balP;
3119 S_SET_NUMBER_AUXILIARY (callP, 2);
3121 #else /* ! OBJ_COFF */
3124 /* If the 'bal' entry doesn't immediately follow the 'call'
3125 * symbol, unlink it from the symbol list and re-insert it.
3127 if (symbol_next (callP) != balP)
3129 symbol_remove (balP, &symbol_rootP, &symbol_lastP);
3130 symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
3131 } /* if not in order */
3133 #else /* ! OBJ_ABOUT */
3134 (as yet unwritten.);
3135 #endif /* ! OBJ_ABOUT */
3136 #endif /* ! OBJ_COFF */
3140 tc_get_bal_of_call (callP)
3145 know (TC_S_IS_CALLNAME (callP));
3148 retval = callP->sy_tc;
3151 retval = symbol_next (callP);
3153 (as yet unwritten.);
3154 #endif /* ! OBJ_ABOUT */
3155 #endif /* ! OBJ_COFF */
3157 know (TC_S_IS_BALNAME (retval));
3159 } /* _tc_get_bal_of_call() */
3162 tc_coff_symbol_emit_hook (symbolP)
3165 if (TC_S_IS_CALLNAME (symbolP))
3168 symbolS *balP = tc_get_bal_of_call (symbolP);
3171 /* second aux entry contains the bal entry point */
3172 S_SET_NUMBER_AUXILIARY (symbolP, 2);
3174 symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
3175 if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
3176 S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
3178 S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
3179 S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3180 /* fix up the bal symbol */
3181 S_SET_STORAGE_CLASS (balP, C_LABEL);
3182 #endif /* OBJ_COFF */
3183 } /* only on calls */
3187 i960_handle_align (fragp)
3195 as_bad (_("option --link-relax is only supported in b.out format"));
3201 /* The text section "ends" with another alignment reloc, to which we
3202 aren't adding padding. */
3203 if (fragp->fr_next == text_last_frag
3204 || fragp->fr_next == data_last_frag)
3207 /* alignment directive */
3208 fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
3209 (int) fragp->fr_type);
3210 #endif /* OBJ_BOUT */
3214 i960_validate_fix (fixP, this_segment_type, add_symbolPP)
3216 segT this_segment_type;
3217 symbolS **add_symbolPP;
3219 #define add_symbolP (*add_symbolPP)
3220 if (fixP->fx_tcbit && TC_S_IS_CALLNAME (add_symbolP))
3222 /* Relocation should be done via the associated 'bal'
3223 entry point symbol. */
3225 if (!TC_S_IS_BALNAME (tc_get_bal_of_call (add_symbolP)))
3227 as_bad (_("No 'bal' entry point for leafproc %s"),
3228 S_GET_NAME (add_symbolP));
3231 fixP->fx_addsy = add_symbolP = tc_get_bal_of_call (add_symbolP);
3234 /* Still have to work out other conditions for these tests. */
3238 as_bad (_("callj to difference of two symbols"));
3242 if ((int) fixP->fx_bit_fixP == 13)
3244 /* This is a COBR instruction. They have only a 13-bit
3245 displacement and are only to be used for local branches:
3246 flag as error, don't generate relocation. */
3247 as_bad (_("can't use COBR format with external label"));
3248 fixP->fx_addsy = NULL; /* No relocations please. */
3257 /* end of tc-i960.c */